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81fdc5f8 TS |
1 | /* |
2 | * CRIS helper routines. | |
3 | * | |
4 | * Copyright (c) 2007 AXIS Communications AB | |
5 | * Written by Edgar E. Iglesias. | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
81fdc5f8 TS |
19 | */ |
20 | ||
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | ||
24 | #include "config.h" | |
25 | #include "cpu.h" | |
26 | #include "mmu.h" | |
941db528 | 27 | #include "host-utils.h" |
81fdc5f8 | 28 | |
d12d51d5 AL |
29 | |
30 | //#define CRIS_HELPER_DEBUG | |
31 | ||
32 | ||
33 | #ifdef CRIS_HELPER_DEBUG | |
34 | #define D(x) x | |
93fcfe39 | 35 | #define D_LOG(...) qemu_log(__VA__ARGS__) |
d12d51d5 | 36 | #else |
e62b5b13 | 37 | #define D(x) |
d12d51d5 AL |
38 | #define D_LOG(...) do { } while (0) |
39 | #endif | |
e62b5b13 | 40 | |
81fdc5f8 TS |
41 | #if defined(CONFIG_USER_ONLY) |
42 | ||
43 | void do_interrupt (CPUState *env) | |
44 | { | |
bbaf29c7 EI |
45 | env->exception_index = -1; |
46 | env->pregs[PR_ERP] = env->pc; | |
81fdc5f8 TS |
47 | } |
48 | ||
49 | int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, | |
97b348e7 | 50 | int mmu_idx) |
81fdc5f8 | 51 | { |
bbaf29c7 | 52 | env->exception_index = 0xaa; |
30abcfc7 | 53 | env->pregs[PR_EDA] = address; |
bbaf29c7 | 54 | cpu_dump_state(env, stderr, fprintf, 0); |
bbaf29c7 | 55 | return 1; |
81fdc5f8 TS |
56 | } |
57 | ||
81fdc5f8 TS |
58 | #else /* !CONFIG_USER_ONLY */ |
59 | ||
e62b5b13 EI |
60 | |
61 | static void cris_shift_ccs(CPUState *env) | |
62 | { | |
63 | uint32_t ccs; | |
64 | /* Apply the ccs shift. */ | |
65 | ccs = env->pregs[PR_CCS]; | |
b41f7df0 | 66 | ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff; |
e62b5b13 EI |
67 | env->pregs[PR_CCS] = ccs; |
68 | } | |
69 | ||
81fdc5f8 | 70 | int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
97b348e7 | 71 | int mmu_idx) |
81fdc5f8 | 72 | { |
2fa73ec8 | 73 | struct cris_mmu_result res; |
81fdc5f8 | 74 | int prot, miss; |
e62b5b13 | 75 | int r = -1; |
81fdc5f8 TS |
76 | target_ulong phy; |
77 | ||
b41f7df0 | 78 | D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw)); |
be9f2ded | 79 | miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, |
9f5a1fae | 80 | rw, mmu_idx, 0); |
81fdc5f8 TS |
81 | if (miss) |
82 | { | |
1b1a38b0 | 83 | if (env->exception_index == EXCP_BUSFAULT) |
7a977356 | 84 | cpu_abort(env, |
ef29a70d | 85 | "CRIS: Illegal recursive bus fault." |
7a977356 EI |
86 | "addr=%x rw=%d\n", |
87 | address, rw); | |
ef29a70d | 88 | |
be9f2ded | 89 | env->pregs[PR_EDA] = address; |
1b1a38b0 | 90 | env->exception_index = EXCP_BUSFAULT; |
e62b5b13 EI |
91 | env->fault_vector = res.bf_vec; |
92 | r = 1; | |
81fdc5f8 TS |
93 | } |
94 | else | |
95 | { | |
980f8a0b EI |
96 | /* |
97 | * Mask off the cache selection bit. The ETRAX busses do not | |
98 | * see the top bit. | |
99 | */ | |
100 | phy = res.phy & ~0x80000000; | |
b41f7df0 | 101 | prot = res.prot; |
d4c430a8 | 102 | tlb_set_page(env, address & TARGET_PAGE_MASK, phy, |
58aebb94 | 103 | prot, mmu_idx, TARGET_PAGE_SIZE); |
d4c430a8 | 104 | r = 0; |
81fdc5f8 | 105 | } |
b41f7df0 | 106 | if (r > 0) |
97b348e7 BS |
107 | D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n", |
108 | __func__, r, env->interrupt_request, address, res.phy, | |
109 | res.bf_vec, env->pc); | |
e62b5b13 | 110 | return r; |
81fdc5f8 TS |
111 | } |
112 | ||
7a977356 EI |
113 | static void do_interruptv10(CPUState *env) |
114 | { | |
115 | int ex_vec = -1; | |
116 | ||
117 | D_LOG( "exception index=%d interrupt_req=%d\n", | |
118 | env->exception_index, | |
119 | env->interrupt_request); | |
120 | ||
121 | assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); | |
122 | switch (env->exception_index) | |
123 | { | |
124 | case EXCP_BREAK: | |
125 | /* These exceptions are genereated by the core itself. | |
126 | ERP should point to the insn following the brk. */ | |
127 | ex_vec = env->trap_vector; | |
128 | env->pregs[PR_ERP] = env->pc; | |
129 | break; | |
130 | ||
131 | case EXCP_NMI: | |
132 | /* NMI is hardwired to vector zero. */ | |
133 | ex_vec = 0; | |
134 | env->pregs[PR_CCS] &= ~M_FLAG; | |
135 | env->pregs[PR_NRP] = env->pc; | |
136 | break; | |
137 | ||
138 | case EXCP_BUSFAULT: | |
43dc2a64 | 139 | cpu_abort(env, "Unhandled busfault"); |
7a977356 EI |
140 | break; |
141 | ||
142 | default: | |
143 | /* The interrupt controller gives us the vector. */ | |
144 | ex_vec = env->interrupt_vector; | |
145 | /* Normal interrupts are taken between | |
146 | TB's. env->pc is valid here. */ | |
147 | env->pregs[PR_ERP] = env->pc; | |
148 | break; | |
149 | } | |
150 | ||
151 | if (env->pregs[PR_CCS] & U_FLAG) { | |
152 | /* Swap stack pointers. */ | |
153 | env->pregs[PR_USP] = env->regs[R_SP]; | |
154 | env->regs[R_SP] = env->ksp; | |
155 | } | |
156 | ||
157 | /* Now that we are in kernel mode, load the handlers address. */ | |
158 | env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4); | |
159 | env->locked_irq = 1; | |
160 | ||
161 | qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", | |
162 | __func__, env->pc, ex_vec, | |
163 | env->pregs[PR_CCS], | |
164 | env->pregs[PR_PID], | |
165 | env->pregs[PR_ERP]); | |
166 | } | |
167 | ||
81fdc5f8 TS |
168 | void do_interrupt(CPUState *env) |
169 | { | |
e62b5b13 | 170 | int ex_vec = -1; |
81fdc5f8 | 171 | |
7a977356 EI |
172 | if (env->pregs[PR_VR] < 32) |
173 | return do_interruptv10(env); | |
174 | ||
d12d51d5 | 175 | D_LOG( "exception index=%d interrupt_req=%d\n", |
b41f7df0 | 176 | env->exception_index, |
d12d51d5 | 177 | env->interrupt_request); |
81fdc5f8 TS |
178 | |
179 | switch (env->exception_index) | |
180 | { | |
181 | case EXCP_BREAK: | |
e62b5b13 EI |
182 | /* These exceptions are genereated by the core itself. |
183 | ERP should point to the insn following the brk. */ | |
184 | ex_vec = env->trap_vector; | |
a1aebcb8 | 185 | env->pregs[PR_ERP] = env->pc; |
81fdc5f8 | 186 | break; |
e62b5b13 | 187 | |
1b1a38b0 EI |
188 | case EXCP_NMI: |
189 | /* NMI is hardwired to vector zero. */ | |
190 | ex_vec = 0; | |
191 | env->pregs[PR_CCS] &= ~M_FLAG; | |
192 | env->pregs[PR_NRP] = env->pc; | |
193 | break; | |
194 | ||
195 | case EXCP_BUSFAULT: | |
e62b5b13 | 196 | ex_vec = env->fault_vector; |
b41f7df0 | 197 | env->pregs[PR_ERP] = env->pc; |
81fdc5f8 TS |
198 | break; |
199 | ||
200 | default: | |
1b1a38b0 | 201 | /* The interrupt controller gives us the vector. */ |
b41f7df0 EI |
202 | ex_vec = env->interrupt_vector; |
203 | /* Normal interrupts are taken between | |
204 | TB's. env->pc is valid here. */ | |
205 | env->pregs[PR_ERP] = env->pc; | |
206 | break; | |
207 | } | |
208 | ||
cddffe37 EI |
209 | /* Fill in the IDX field. */ |
210 | env->pregs[PR_EXS] = (ex_vec & 0xff) << 8; | |
211 | ||
cf1d97f0 | 212 | if (env->dslot) { |
d12d51d5 | 213 | D_LOG("excp isr=%x PC=%x ds=%d SP=%x" |
cf1d97f0 EI |
214 | " ERP=%x pid=%x ccs=%x cc=%d %x\n", |
215 | ex_vec, env->pc, env->dslot, | |
ef29a70d | 216 | env->regs[R_SP], |
b41f7df0 EI |
217 | env->pregs[PR_ERP], env->pregs[PR_PID], |
218 | env->pregs[PR_CCS], | |
d12d51d5 | 219 | env->cc_op, env->cc_mask); |
cf1d97f0 EI |
220 | /* We loose the btarget, btaken state here so rexec the |
221 | branch. */ | |
222 | env->pregs[PR_ERP] -= env->dslot; | |
223 | /* Exception starts with dslot cleared. */ | |
224 | env->dslot = 0; | |
81fdc5f8 | 225 | } |
b41f7df0 | 226 | |
b41f7df0 EI |
227 | if (env->pregs[PR_CCS] & U_FLAG) { |
228 | /* Swap stack pointers. */ | |
229 | env->pregs[PR_USP] = env->regs[R_SP]; | |
230 | env->regs[R_SP] = env->ksp; | |
231 | } | |
232 | ||
233 | /* Apply the CRIS CCS shift. Clears U if set. */ | |
e62b5b13 | 234 | cris_shift_ccs(env); |
218951ef | 235 | |
abdfd950 EI |
236 | /* Now that we are in kernel mode, load the handlers address. |
237 | This load may not fault, real hw leaves that behaviour as | |
238 | undefined. */ | |
218951ef EI |
239 | env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4); |
240 | ||
abdfd950 EI |
241 | /* Clear the excption_index to avoid spurios hw_aborts for recursive |
242 | bus faults. */ | |
243 | env->exception_index = -1; | |
244 | ||
7a977356 EI |
245 | D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", |
246 | __func__, env->pc, ex_vec, | |
b41f7df0 EI |
247 | env->pregs[PR_CCS], |
248 | env->pregs[PR_PID], | |
d12d51d5 | 249 | env->pregs[PR_ERP]); |
81fdc5f8 TS |
250 | } |
251 | ||
c227f099 | 252 | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
81fdc5f8 | 253 | { |
81fdc5f8 | 254 | uint32_t phy = addr; |
2fa73ec8 | 255 | struct cris_mmu_result res; |
81fdc5f8 | 256 | int miss; |
3c4fe427 | 257 | |
9f5a1fae | 258 | miss = cris_mmu_translate(&res, env, addr, 0, 0, 1); |
3c4fe427 EI |
259 | /* If D TLB misses, try I TLB. */ |
260 | if (miss) { | |
9f5a1fae | 261 | miss = cris_mmu_translate(&res, env, addr, 2, 0, 1); |
3c4fe427 EI |
262 | } |
263 | ||
81fdc5f8 TS |
264 | if (!miss) |
265 | phy = res.phy; | |
e62b5b13 | 266 | D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy)); |
81fdc5f8 TS |
267 | return phy; |
268 | } | |
269 | #endif |