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target-*: Unconditionally emit tcg_gen_insn_start
[mirror_qemu.git] / target-cris / translate_v10.c
CommitLineData
40e9eddd
EI		 1/*
2 * CRISv10 emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2010 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
70539e18 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
40e9eddd
EI		 19 */
20
21#include "crisv10-decode.h"
22
23static const char *regnames_v10[] =
24{
bf76bafa
EI		 25 "$r0", "$r1", "$r2", "$r3",
26 "$r4", "$r5", "$r6", "$r7",
27 "$r8", "$r9", "$r10", "$r11",
28 "$r12", "$r13", "$sp", "$pc",
40e9eddd
EI		 29};
30
31static const char *pregnames_v10[] =
32{
bf76bafa
EI		 33 "$bz", "$vr", "$p2", "$p3",
34 "$wz", "$ccr", "$p6-prefix", "$mof",
35 "$dz", "$ibr", "$irp", "$srp",
36 "$bar", "$dccr", "$brp", "$usp",
40e9eddd
EI		 37};
38
39/* We need this table to handle preg-moves with implicit width. */
40static int preg_sizes_v10[] = {
bf76bafa
EI		 41 1, /* bz. */
42 1, /* vr. */
43 1, /* pid. */
44 1, /* srs. */
45 2, /* wz. */
46 2, 2, 4,
47 4, 4, 4, 4,
48 4, 4, 4, 4,
40e9eddd
EI		 49};
50
51static inline int dec10_size(unsigned int size)
52{
53 size++;
54 if (size == 3)
55 size++;
56 return size;
57}
58
59static inline void cris_illegal_insn(DisasContext *dc)
60{
61 qemu_log("illegal insn at pc=%x\n", dc->pc);
62 t_gen_raise_exception(EXCP_BREAK);
63}
64
774d5c5b
SS		 65static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
66 unsigned int size, int mem_index)
67{
42a268c2 68 TCGLabel *l1 = gen_new_label();
774d5c5b
SS		 69 TCGv taddr = tcg_temp_local_new();
70 TCGv tval = tcg_temp_local_new();
71 TCGv t1 = tcg_temp_local_new();
72 dc->postinc = 0;
73 cris_evaluate_flags(dc);
74
75 tcg_gen_mov_tl(taddr, addr);
76 tcg_gen_mov_tl(tval, val);
77
78 /* Store only if F flag isn't set */
79 tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10);
80 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
81 if (size == 1) {
82 tcg_gen_qemu_st8(tval, taddr, mem_index);
83 } else if (size == 2) {
84 tcg_gen_qemu_st16(tval, taddr, mem_index);
85 } else {
86 tcg_gen_qemu_st32(tval, taddr, mem_index);
87 }
88 gen_set_label(l1);
89 tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */
90 tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
91 tcg_temp_free(t1);
92 tcg_temp_free(tval);
93 tcg_temp_free(taddr);
94}
95
96static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
97 unsigned int size)
98{
97ed5ccd 99 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
774d5c5b
SS		 100
101 /* If we get a fault on a delayslot we must keep the jmp state in
102 the cpu-state to be able to re-execute the jmp. */
103 if (dc->delayed_branch == 1) {
104 cris_store_direct_jmp(dc);
105 }
106
107 /* Conditional writes. We only support the kind were X is known
108 at translation time. */
109 if (dc->flagx_known && dc->flags_x) {
110 gen_store_v10_conditional(dc, addr, val, size, mem_index);
111 return;
112 }
113
114 if (size == 1) {
115 tcg_gen_qemu_st8(val, addr, mem_index);
116 } else if (size == 2) {
117 tcg_gen_qemu_st16(val, addr, mem_index);
118 } else {
119 tcg_gen_qemu_st32(val, addr, mem_index);
120 }
121}
122
123
40e9eddd
EI		 124/* Prefix flag and register are used to handle the more complex
125 addressing modes. */
126static void cris_set_prefix(DisasContext *dc)
127{
128 dc->clear_prefix = 0;
129 dc->tb_flags |= PFIX_FLAG;
130 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG);
131
132 /* prefix insns dont clear the x flag. */
133 dc->clear_x = 0;
134 cris_lock_irq(dc);
135}
136
137static void crisv10_prepare_memaddr(DisasContext *dc,
138 TCGv addr, unsigned int size)
139{
140 if (dc->tb_flags & PFIX_FLAG) {
141 tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]);
142 } else {
143 tcg_gen_mov_tl(addr, cpu_R[dc->src]);
144 }
145}
146
147static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
148{
149 unsigned int insn_len = 0;
150
151 if (dc->tb_flags & PFIX_FLAG) {
152 if (dc->mode == CRISV10_MODE_AUTOINC) {
153 tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]);
154 }
155 } else {
156 if (dc->mode == CRISV10_MODE_AUTOINC) {
157 if (dc->src == 15) {
158 insn_len += size & ~1;
159 } else {
160 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size);
161 }
162 }
163 }
164 return insn_len;
165}
166
cf7e0c80
AJ		 167static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc,
168 int s_ext, int memsize, TCGv dst)
40e9eddd 169{
03e654c0 170 unsigned int rs;
bf76bafa
EI		 171 uint32_t imm;
172 int is_imm;
173 int insn_len = 0;
174
175 rs = dc->src;
bf76bafa
EI		 176 is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG);
177 LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n",
03e654c0 178 rs, dc->dst, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG);
bf76bafa
EI		 179
180 /* Load [$rs] onto T1. */
181 if (is_imm) {
182 if (memsize != 4) {
183 if (s_ext) {
184 if (memsize == 1)
cf7e0c80 185 imm = cpu_ldsb_code(env, dc->pc + 2);
40e9eddd 186 else
cf7e0c80 187 imm = cpu_ldsw_code(env, dc->pc + 2);
bf76bafa
EI		 188 } else {
189 if (memsize == 1)
cf7e0c80 190 imm = cpu_ldub_code(env, dc->pc + 2);
bf76bafa 191 else
cf7e0c80 192 imm = cpu_lduw_code(env, dc->pc + 2);
bf76bafa
EI		 193 }
194 } else
cf7e0c80 195 imm = cpu_ldl_code(env, dc->pc + 2);
bf76bafa
EI		 196
197 tcg_gen_movi_tl(dst, imm);
40e9eddd 198
bf76bafa
EI		 199 if (dc->mode == CRISV10_MODE_AUTOINC) {
200 insn_len += memsize;
201 if (memsize == 1)
202 insn_len++;
203 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len);
40e9eddd 204 }
bf76bafa
EI		 205 } else {
206 TCGv addr;
207
208 addr = tcg_temp_new();
209 cris_flush_cc_state(dc);
210 crisv10_prepare_memaddr(dc, addr, memsize);
211 gen_load(dc, dst, addr, memsize, 0);
212 if (s_ext)
213 t_gen_sext(dst, dst, memsize);
214 else
215 t_gen_zext(dst, dst, memsize);
216 insn_len += crisv10_post_memaddr(dc, memsize);
217 tcg_temp_free(addr);
218 }
219
220 if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) {
221 dc->dst = dc->src;
222 }
223 return insn_len;
40e9eddd
EI		 224}
225
226static unsigned int dec10_quick_imm(DisasContext *dc)
227{
228 int32_t imm, simm;
229 int op;
230
231 /* sign extend. */
232 imm = dc->ir & ((1 << 6) - 1);
233 simm = (int8_t) (imm << 2);
234 simm >>= 2;
235 switch (dc->opcode) {
236 case CRISV10_QIMM_BDAP_R0:
237 case CRISV10_QIMM_BDAP_R1:
238 case CRISV10_QIMM_BDAP_R2:
239 case CRISV10_QIMM_BDAP_R3:
240 simm = (int8_t)dc->ir;
241 LOG_DIS("bdap %d $r%d\n", simm, dc->dst);
242 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
243 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
244 cris_set_prefix(dc);
245 if (dc->dst == 15) {
246 tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm);
247 } else {
248 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
249 }
250 break;
251
252 case CRISV10_QIMM_MOVEQ:
253 LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);
254
255 cris_cc_mask(dc, CC_MASK_NZVC);
256 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
257 cpu_R[dc->dst], tcg_const_tl(simm), 4);
258 break;
259 case CRISV10_QIMM_CMPQ:
260 LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
261
262 cris_cc_mask(dc, CC_MASK_NZVC);
263 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
264 cpu_R[dc->dst], tcg_const_tl(simm), 4);
265 break;
266 case CRISV10_QIMM_ADDQ:
267 LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
268
269 cris_cc_mask(dc, CC_MASK_NZVC);
270 cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
271 cpu_R[dc->dst], tcg_const_tl(imm), 4);
272 break;
273 case CRISV10_QIMM_ANDQ:
274 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
275
276 cris_cc_mask(dc, CC_MASK_NZVC);
277 cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
278 cpu_R[dc->dst], tcg_const_tl(simm), 4);
279 break;
280 case CRISV10_QIMM_ASHQ:
281 LOG_DIS("ashq %d, $r%d\n", simm, dc->dst);
282
283 cris_cc_mask(dc, CC_MASK_NZVC);
284 op = imm & (1 << 5);
285 imm &= 0x1f;
286 if (op) {
287 cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
288 cpu_R[dc->dst], tcg_const_tl(imm), 4);
289 } else {
290 /* BTST */
291 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
febc9920 292 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
40e9eddd
EI		 293 tcg_const_tl(imm), cpu_PR[PR_CCS]);
294 }
295 break;
296 case CRISV10_QIMM_LSHQ:
297 LOG_DIS("lshq %d, $r%d\n", simm, dc->dst);
298
299 op = CC_OP_LSL;
300 if (imm & (1 << 5)) {
301 op = CC_OP_LSR;
302 }
303 imm &= 0x1f;
304 cris_cc_mask(dc, CC_MASK_NZVC);
305 cris_alu(dc, op, cpu_R[dc->dst],
306 cpu_R[dc->dst], tcg_const_tl(imm), 4);
307 break;
308 case CRISV10_QIMM_SUBQ:
309 LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
310
311 cris_cc_mask(dc, CC_MASK_NZVC);
312 cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
313 cpu_R[dc->dst], tcg_const_tl(imm), 4);
314 break;
315 case CRISV10_QIMM_ORQ:
316 LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
317
318 cris_cc_mask(dc, CC_MASK_NZVC);
319 cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
320 cpu_R[dc->dst], tcg_const_tl(simm), 4);
321 break;
322
323 case CRISV10_QIMM_BCC_R0:
40e9eddd
EI		 324 case CRISV10_QIMM_BCC_R1:
325 case CRISV10_QIMM_BCC_R2:
326 case CRISV10_QIMM_BCC_R3:
327 imm = dc->ir & 0xff;
328 /* bit 0 is a sign bit. */
329 if (imm & 1) {
330 imm |= 0xffffff00; /* sign extend. */
331 imm &= ~1; /* get rid of the sign bit. */
332 }
333 imm += 2;
334 LOG_DIS("b%s %d\n", cc_name(dc->cond), imm);
335
336 cris_cc_mask(dc, 0);
337 cris_prepare_cc_branch(dc, imm, dc->cond);
338 break;
339
340 default:
341 LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
342 dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
0dd106c5 343 cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n");
40e9eddd
EI		 344 break;
345 }
346 return 2;
347}
348
349static unsigned int dec10_setclrf(DisasContext *dc)
350{
351 uint32_t flags;
352 unsigned int set = ~dc->opcode & 1;
353
354 flags = EXTRACT_FIELD(dc->ir, 0, 3)
355 | (EXTRACT_FIELD(dc->ir, 12, 15) << 4);
356 LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags);
357
358
359 if (flags & X_FLAG) {
360 dc->flagx_known = 1;
361 if (set)
362 dc->flags_x = X_FLAG;
363 else
364 dc->flags_x = 0;
365 }
366
367 cris_evaluate_flags (dc);
368 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
369 cris_update_cc_x(dc);
370 tcg_gen_movi_tl(cc_op, dc->cc_op);
371
372 if (set) {
373 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
374 } else {
774d5c5b
SS		 375 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS],
376 ~(flags|F_FLAG_V10|P_FLAG_V10));
40e9eddd
EI		 377 }
378
379 dc->flags_uptodate = 1;
380 dc->clear_x = 0;
381 cris_lock_irq(dc);
382 return 2;
383}
384
385static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext,
386 TCGv dd, TCGv ds, TCGv sd, TCGv ss)
387{
388 if (sext) {
389 t_gen_sext(dd, sd, size);
390 t_gen_sext(ds, ss, size);
391 } else {
392 t_gen_zext(dd, sd, size);
393 t_gen_zext(ds, ss, size);
394 }
395}
396
397static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext)
398{
399 TCGv t[2];
400
401 t[0] = tcg_temp_new();
402 t[1] = tcg_temp_new();
403 dec10_reg_prep_sext(dc, size, sext,
404 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
405
406 if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) {
407 tcg_gen_andi_tl(t[1], t[1], 63);
408 }
409
410 assert(dc->dst != 15);
411 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size);
412 tcg_temp_free(t[0]);
413 tcg_temp_free(t[1]);
414}
415
416static void dec10_reg_bound(DisasContext *dc, int size)
417{
418 TCGv t;
419
420 t = tcg_temp_local_new();
421 t_gen_zext(t, cpu_R[dc->src], size);
422 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
423 tcg_temp_free(t);
424}
425
426static void dec10_reg_mul(DisasContext *dc, int size, int sext)
427{
428 int op = sext ? CC_OP_MULS : CC_OP_MULU;
429 TCGv t[2];
430
431 t[0] = tcg_temp_new();
432 t[1] = tcg_temp_new();
433 dec10_reg_prep_sext(dc, size, sext,
434 t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);
435
436 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4);
437
438 tcg_temp_free(t[0]);
439 tcg_temp_free(t[1]);
440}
441
442
443static void dec10_reg_movs(DisasContext *dc)
444{
445 int size = (dc->size & 1) + 1;
446 TCGv t;
447
448 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
449 cris_cc_mask(dc, CC_MASK_NZVC);
450
451 t = tcg_temp_new();
452 if (dc->ir & 32)
453 t_gen_sext(t, cpu_R[dc->src], size);
454 else
455 t_gen_zext(t, cpu_R[dc->src], size);
456
457 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
458 tcg_temp_free(t);
459}
460
461static void dec10_reg_alux(DisasContext *dc, int op)
462{
463 int size = (dc->size & 1) + 1;
464 TCGv t;
465
466 LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst);
467 cris_cc_mask(dc, CC_MASK_NZVC);
468
469 t = tcg_temp_new();
470 if (dc->ir & 32)
471 t_gen_sext(t, cpu_R[dc->src], size);
472 else
473 t_gen_zext(t, cpu_R[dc->src], size);
474
475 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
476 tcg_temp_free(t);
477}
478
479static void dec10_reg_mov_pr(DisasContext *dc)
480{
481 LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]);
482 cris_lock_irq(dc);
483 if (dc->src == 15) {
484 tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]);
485 cris_prepare_jmp(dc, JMP_INDIRECT);
486 return;
487 }
488 if (dc->dst == PR_CCS) {
489 cris_evaluate_flags(dc);
490 }
491 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src],
492 cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]);
493}
494
495static void dec10_reg_abs(DisasContext *dc)
496{
bf76bafa 497 TCGv t0;
40e9eddd 498
bf76bafa 499 LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst);
40e9eddd 500
bf76bafa
EI		 501 assert(dc->dst != 15);
502 t0 = tcg_temp_new();
503 tcg_gen_sari_tl(t0, cpu_R[dc->src], 31);
504 tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0);
505 tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0);
40e9eddd 506
bf76bafa
EI		 507 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
508 tcg_temp_free(t0);
40e9eddd
EI		 509}
510
511static void dec10_reg_swap(DisasContext *dc)
512{
513 TCGv t0;
514
515 LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst);
516
517 cris_cc_mask(dc, CC_MASK_NZVC);
518 t0 = tcg_temp_new();
08397c4b 519 tcg_gen_mov_tl(t0, cpu_R[dc->src]);
40e9eddd
EI		 520 if (dc->dst & 8)
521 tcg_gen_not_tl(t0, t0);
522 if (dc->dst & 4)
523 t_gen_swapw(t0, t0);
524 if (dc->dst & 2)
525 t_gen_swapb(t0, t0);
526 if (dc->dst & 1)
527 t_gen_swapr(t0, t0);
528 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4);
529 tcg_temp_free(t0);
530}
531
532static void dec10_reg_scc(DisasContext *dc)
533{
bf76bafa 534 int cond = dc->dst;
40e9eddd 535
bf76bafa 536 LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src);
40e9eddd 537
88174019
RH		 538 gen_tst_cc(dc, cpu_R[dc->src], cond);
539 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->src], cpu_R[dc->src], 0);
40e9eddd 540
bf76bafa 541 cris_cc_mask(dc, 0);
40e9eddd
EI		 542}
543
544static unsigned int dec10_reg(DisasContext *dc)
545{
546 TCGv t;
547 unsigned int insn_len = 2;
548 unsigned int size = dec10_size(dc->size);
549 unsigned int tmp;
550
551 if (dc->size != 3) {
552 switch (dc->opcode) {
553 case CRISV10_REG_MOVE_R:
554 LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst);
555 cris_cc_mask(dc, CC_MASK_NZVC);
556 dec10_reg_alu(dc, CC_OP_MOVE, size, 0);
557 if (dc->dst == 15) {
558 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
559 cris_prepare_jmp(dc, JMP_INDIRECT);
560 dc->delayed_branch = 1;
561 }
562 break;
563 case CRISV10_REG_MOVX:
564 cris_cc_mask(dc, CC_MASK_NZVC);
565 dec10_reg_movs(dc);
566 break;
567 case CRISV10_REG_ADDX:
568 cris_cc_mask(dc, CC_MASK_NZVC);
569 dec10_reg_alux(dc, CC_OP_ADD);
570 break;
571 case CRISV10_REG_SUBX:
572 cris_cc_mask(dc, CC_MASK_NZVC);
573 dec10_reg_alux(dc, CC_OP_SUB);
574 break;
575 case CRISV10_REG_ADD:
576 LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
577 cris_cc_mask(dc, CC_MASK_NZVC);
578 dec10_reg_alu(dc, CC_OP_ADD, size, 0);
579 break;
580 case CRISV10_REG_SUB:
581 LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
582 cris_cc_mask(dc, CC_MASK_NZVC);
583 dec10_reg_alu(dc, CC_OP_SUB, size, 0);
584 break;
585 case CRISV10_REG_CMP:
586 LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
587 cris_cc_mask(dc, CC_MASK_NZVC);
588 dec10_reg_alu(dc, CC_OP_CMP, size, 0);
589 break;
590 case CRISV10_REG_BOUND:
591 LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
592 cris_cc_mask(dc, CC_MASK_NZVC);
593 dec10_reg_bound(dc, size);
594 break;
595 case CRISV10_REG_AND:
596 LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
597 cris_cc_mask(dc, CC_MASK_NZVC);
598 dec10_reg_alu(dc, CC_OP_AND, size, 0);
599 break;
600 case CRISV10_REG_ADDI:
601 if (dc->src == 15) {
602 /* nop. */
603 return 2;
604 }
605 t = tcg_temp_new();
606 LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size);
607 tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3);
608 tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t);
609 tcg_temp_free(t);
610 break;
611 case CRISV10_REG_LSL:
612 LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
613 cris_cc_mask(dc, CC_MASK_NZVC);
614 dec10_reg_alu(dc, CC_OP_LSL, size, 0);
615 break;
616 case CRISV10_REG_LSR:
617 LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
618 cris_cc_mask(dc, CC_MASK_NZVC);
619 dec10_reg_alu(dc, CC_OP_LSR, size, 0);
620 break;
621 case CRISV10_REG_ASR:
622 LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
623 cris_cc_mask(dc, CC_MASK_NZVC);
624 dec10_reg_alu(dc, CC_OP_ASR, size, 1);
625 break;
626 case CRISV10_REG_OR:
627 LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
628 cris_cc_mask(dc, CC_MASK_NZVC);
629 dec10_reg_alu(dc, CC_OP_OR, size, 0);
630 break;
631 case CRISV10_REG_NEG:
632 LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
633 cris_cc_mask(dc, CC_MASK_NZVC);
634 dec10_reg_alu(dc, CC_OP_NEG, size, 0);
635 break;
636 case CRISV10_REG_BIAP:
637 LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc,
638 dc->opcode, dc->src, dc->dst, size);
639 switch (size) {
640 case 4: tmp = 2; break;
641 case 2: tmp = 1; break;
642 case 1: tmp = 0; break;
43dc2a64 643 default:
0dd106c5 644 cpu_abort(CPU(dc->cpu), "Unhandled BIAP");
43dc2a64 645 break;
40e9eddd
EI		 646 }
647
648 t = tcg_temp_new();
649 tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp);
650 if (dc->src == 15) {
651 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1);
652 } else {
653 tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t);
654 }
655 tcg_temp_free(t);
656 cris_set_prefix(dc);
657 break;
658
659 default:
660 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
661 dc->opcode, dc->src, dc->dst);
0dd106c5 662 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
40e9eddd
EI		 663 break;
664 }
665 } else {
666 switch (dc->opcode) {
667 case CRISV10_REG_MOVX:
668 cris_cc_mask(dc, CC_MASK_NZVC);
669 dec10_reg_movs(dc);
670 break;
671 case CRISV10_REG_ADDX:
672 cris_cc_mask(dc, CC_MASK_NZVC);
673 dec10_reg_alux(dc, CC_OP_ADD);
674 break;
675 case CRISV10_REG_SUBX:
676 cris_cc_mask(dc, CC_MASK_NZVC);
677 dec10_reg_alux(dc, CC_OP_SUB);
678 break;
679 case CRISV10_REG_MOVE_SPR_R:
680 cris_evaluate_flags(dc);
681 cris_cc_mask(dc, 0);
682 dec10_reg_mov_pr(dc);
683 break;
684 case CRISV10_REG_MOVE_R_SPR:
685 LOG_DIS("move r%d p%d\n", dc->src, dc->dst);
686 cris_evaluate_flags(dc);
687 if (dc->src != 11) /* fast for srp. */
688 dc->cpustate_changed = 1;
689 t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]);
690 break;
691 case CRISV10_REG_SETF:
692 case CRISV10_REG_CLEARF:
693 dec10_setclrf(dc);
694 break;
695 case CRISV10_REG_SWAP:
696 dec10_reg_swap(dc);
697 break;
698 case CRISV10_REG_ABS:
699 cris_cc_mask(dc, CC_MASK_NZVC);
700 dec10_reg_abs(dc);
701 break;
702 case CRISV10_REG_LZ:
703 LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
704 cris_cc_mask(dc, CC_MASK_NZVC);
705 dec10_reg_alu(dc, CC_OP_LZ, 4, 0);
706 break;
707 case CRISV10_REG_XOR:
708 LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
709 cris_cc_mask(dc, CC_MASK_NZVC);
710 dec10_reg_alu(dc, CC_OP_XOR, 4, 0);
711 break;
712 case CRISV10_REG_BTST:
713 LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
714 cris_cc_mask(dc, CC_MASK_NZVC);
715 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
febc9920 716 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
40e9eddd
EI		 717 cpu_R[dc->src], cpu_PR[PR_CCS]);
718 break;
719 case CRISV10_REG_DSTEP:
720 LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
721 cris_cc_mask(dc, CC_MASK_NZVC);
722 cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst],
723 cpu_R[dc->dst], cpu_R[dc->src], 4);
724 break;
725 case CRISV10_REG_MSTEP:
726 LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
727 cris_evaluate_flags(dc);
728 cris_cc_mask(dc, CC_MASK_NZVC);
729 cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst],
730 cpu_R[dc->dst], cpu_R[dc->src], 4);
731 break;
732 case CRISV10_REG_SCC:
733 dec10_reg_scc(dc);
734 break;
735 default:
736 LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
737 dc->opcode, dc->src, dc->dst);
0dd106c5 738 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
40e9eddd
EI		 739 break;
740 }
741 }
742 return insn_len;
743}
744
cf7e0c80
AJ		 745static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc,
746 unsigned int size)
40e9eddd
EI		 747{
748 unsigned int insn_len = 2;
749 TCGv t;
750
751 LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__,
752 size, dc->src, dc->dst);
753
754 cris_cc_mask(dc, CC_MASK_NZVC);
755 t = tcg_temp_new();
cf7e0c80 756 insn_len += dec10_prep_move_m(env, dc, 0, size, t);
40e9eddd
EI		 757 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size);
758 if (dc->dst == 15) {
759 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
760 cris_prepare_jmp(dc, JMP_INDIRECT);
761 dc->delayed_branch = 1;
762 return insn_len;
763 }
764
765 tcg_temp_free(t);
766 return insn_len;
767}
768
769static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
770{
771 unsigned int insn_len = 2;
772 TCGv addr;
773
774 LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
775 addr = tcg_temp_new();
776 crisv10_prepare_memaddr(dc, addr, size);
774d5c5b 777 gen_store_v10(dc, addr, cpu_R[dc->dst], size);
40e9eddd
EI		 778 insn_len += crisv10_post_memaddr(dc, size);
779
780 return insn_len;
781}
782
cf7e0c80 783static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
40e9eddd
EI		 784{
785 unsigned int insn_len = 2, rd = dc->dst;
786 TCGv t, addr;
787
788 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
789 cris_lock_irq(dc);
790
791 addr = tcg_temp_new();
792 t = tcg_temp_new();
cf7e0c80 793 insn_len += dec10_prep_move_m(env, dc, 0, 4, t);
40e9eddd
EI		 794 if (rd == 15) {
795 tcg_gen_mov_tl(env_btarget, t);
796 cris_prepare_jmp(dc, JMP_INDIRECT);
797 dc->delayed_branch = 1;
798 return insn_len;
799 }
800
801 tcg_gen_mov_tl(cpu_PR[rd], t);
802 dc->cpustate_changed = 1;
803 tcg_temp_free(addr);
804 tcg_temp_free(t);
805 return insn_len;
806}
807
808static unsigned int dec10_ind_move_pr_m(DisasContext *dc)
809{
810 unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst];
811 TCGv addr, t0;
812
813 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
814
815 addr = tcg_temp_new();
816 crisv10_prepare_memaddr(dc, addr, size);
817 if (dc->dst == PR_CCS) {
818 t0 = tcg_temp_new();
819 cris_evaluate_flags(dc);
820 tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG);
774d5c5b 821 gen_store_v10(dc, addr, t0, size);
40e9eddd
EI		 822 tcg_temp_free(t0);
823 } else {
774d5c5b 824 gen_store_v10(dc, addr, cpu_PR[dc->dst], size);
40e9eddd
EI		 825 }
826 t0 = tcg_temp_new();
827 insn_len += crisv10_post_memaddr(dc, size);
828 cris_lock_irq(dc);
829
830 return insn_len;
831}
832
833static void dec10_movem_r_m(DisasContext *dc)
834{
835 int i, pfix = dc->tb_flags & PFIX_FLAG;
836 TCGv addr, t0;
837
838 LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__,
839 dc->dst, dc->src, dc->postinc, dc->ir);
840
841 addr = tcg_temp_new();
842 t0 = tcg_temp_new();
843 crisv10_prepare_memaddr(dc, addr, 4);
844 tcg_gen_mov_tl(t0, addr);
845 for (i = dc->dst; i >= 0; i--) {
846 if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
774d5c5b 847 gen_store_v10(dc, addr, t0, 4);
40e9eddd 848 } else {
774d5c5b 849 gen_store_v10(dc, addr, cpu_R[i], 4);
40e9eddd
EI		 850 }
851 tcg_gen_addi_tl(addr, addr, 4);
852 }
853
854 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
855 tcg_gen_mov_tl(cpu_R[dc->src], t0);
856 }
857
858 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
859 tcg_gen_mov_tl(cpu_R[dc->src], addr);
860 }
861 tcg_temp_free(addr);
862 tcg_temp_free(t0);
863}
864
865static void dec10_movem_m_r(DisasContext *dc)
866{
867 int i, pfix = dc->tb_flags & PFIX_FLAG;
868 TCGv addr, t0;
869
870 LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__,
871 dc->src, dc->dst, dc->postinc, dc->ir);
872
873 addr = tcg_temp_new();
874 t0 = tcg_temp_new();
875 crisv10_prepare_memaddr(dc, addr, 4);
876 tcg_gen_mov_tl(t0, addr);
877 for (i = dc->dst; i >= 0; i--) {
878 gen_load(dc, cpu_R[i], addr, 4, 0);
879 tcg_gen_addi_tl(addr, addr, 4);
880 }
881
882 if (pfix && dc->mode == CRISV10_MODE_AUTOINC) {
883 tcg_gen_mov_tl(cpu_R[dc->src], t0);
884 }
885
40e9eddd
EI		 886 if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
887 tcg_gen_mov_tl(cpu_R[dc->src], addr);
888 }
889 tcg_temp_free(addr);
890 tcg_temp_free(t0);
891}
892
cf7e0c80
AJ		 893static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
894 int op, unsigned int size)
40e9eddd
EI		 895{
896 int insn_len = 0;
897 int rd = dc->dst;
898 TCGv t[2];
899
900 cris_alu_m_alloc_temps(t);
cf7e0c80 901 insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
40e9eddd
EI		 902 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size);
903 if (dc->dst == 15) {
904 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
905 cris_prepare_jmp(dc, JMP_INDIRECT);
906 dc->delayed_branch = 1;
907 return insn_len;
908 }
909
910 cris_alu_m_free_temps(t);
911
912 return insn_len;
913}
914
cf7e0c80
AJ		 915static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
916 unsigned int size)
40e9eddd
EI		 917{
918 int insn_len = 0;
919 int rd = dc->dst;
920 TCGv t;
921
922 t = tcg_temp_local_new();
cf7e0c80 923 insn_len += dec10_prep_move_m(env, dc, 0, size, t);
40e9eddd
EI		 924 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
925 if (dc->dst == 15) {
926 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
927 cris_prepare_jmp(dc, JMP_INDIRECT);
928 dc->delayed_branch = 1;
929 return insn_len;
930 }
931
932 tcg_temp_free(t);
933 return insn_len;
934}
935
cf7e0c80 936static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op)
40e9eddd
EI		 937{
938 unsigned int size = (dc->size & 1) ? 2 : 1;
939 unsigned int sx = !!(dc->size & 2);
940 int insn_len = 2;
941 int rd = dc->dst;
942 TCGv t;
943
944 LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst);
945
946 t = tcg_temp_new();
947
948 cris_cc_mask(dc, CC_MASK_NZVC);
cf7e0c80 949 insn_len += dec10_prep_move_m(env, dc, sx, size, t);
40e9eddd
EI		 950 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4);
951 if (dc->dst == 15) {
952 tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]);
953 cris_prepare_jmp(dc, JMP_INDIRECT);
954 dc->delayed_branch = 1;
955 return insn_len;
956 }
957
958 tcg_temp_free(t);
959 return insn_len;
960}
961
cf7e0c80 962static int dec10_dip(CPUCRISState *env, DisasContext *dc)
40e9eddd
EI		 963{
964 int insn_len = 2;
965 uint32_t imm;
966
967 LOG_DIS("dip pc=%x opcode=%d r%d r%d\n",
968 dc->pc, dc->opcode, dc->src, dc->dst);
969 if (dc->src == 15) {
cf7e0c80 970 imm = cpu_ldl_code(env, dc->pc + 2);
40e9eddd
EI		 971 tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm);
972 if (dc->postinc)
973 insn_len += 4;
974 tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2);
975 } else {
976 gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0);
977 if (dc->postinc)
978 tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4);
979 }
980
981 cris_set_prefix(dc);
982 return insn_len;
983}
984
cf7e0c80 985static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)
40e9eddd
EI		 986{
987 int insn_len = 2;
988 int rd = dc->dst;
989
990 LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n",
991 dc->pc, dc->opcode, dc->src, dc->dst, size);
992
993 assert(dc->dst != 15);
994#if 0
995 /* 8bit embedded offset? */
996 if (!dc->postinc && (dc->ir & (1 << 11))) {
997 int simm = dc->ir & 0xff;
998
0dd106c5 999 /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */
40e9eddd
EI		 1000 /* sign extended. */
1001 simm = (int8_t)simm;
1002
1003 tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm);
1004
1005 cris_set_prefix(dc);
1006 return insn_len;
1007 }
1008#endif
8186e783 1009 /* Now the rest of the modes are truly indirect. */
cf7e0c80 1010 insn_len += dec10_prep_move_m(env, dc, 1, size, cpu_PR[PR_PREFIX]);
40e9eddd
EI		 1011 tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]);
1012 cris_set_prefix(dc);
1013 return insn_len;
1014}
1015
cf7e0c80 1016static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
40e9eddd
EI		 1017{
1018 unsigned int insn_len = 2;
1019 unsigned int size = dec10_size(dc->size);
1020 uint32_t imm;
1021 int32_t simm;
1022 TCGv t[2];
1023
1024 if (dc->size != 3) {
1025 switch (dc->opcode) {
1026 case CRISV10_IND_MOVE_M_R:
cf7e0c80 1027 return dec10_ind_move_m_r(env, dc, size);
40e9eddd
EI		 1028 break;
1029 case CRISV10_IND_MOVE_R_M:
1030 return dec10_ind_move_r_m(dc, size);
1031 break;
1032 case CRISV10_IND_CMP:
1033 LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst);
1034 cris_cc_mask(dc, CC_MASK_NZVC);
cf7e0c80 1035 insn_len += dec10_ind_alu(env, dc, CC_OP_CMP, size);
40e9eddd
EI		 1036 break;
1037 case CRISV10_IND_TEST:
1038 LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst);
1039
1040 cris_evaluate_flags(dc);
1041 cris_cc_mask(dc, CC_MASK_NZVC);
1042 cris_alu_m_alloc_temps(t);
cf7e0c80 1043 insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
40e9eddd
EI		 1044 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
1045 cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
1046 t[0], tcg_const_tl(0), size);
1047 cris_alu_m_free_temps(t);
1048 break;
1049 case CRISV10_IND_ADD:
1050 LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
1051 cris_cc_mask(dc, CC_MASK_NZVC);
cf7e0c80 1052 insn_len += dec10_ind_alu(env, dc, CC_OP_ADD, size);
40e9eddd
EI		 1053 break;
1054 case CRISV10_IND_SUB:
1055 LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst);
1056 cris_cc_mask(dc, CC_MASK_NZVC);
cf7e0c80 1057 insn_len += dec10_ind_alu(env, dc, CC_OP_SUB, size);
40e9eddd
EI		 1058 break;
1059 case CRISV10_IND_BOUND:
1060 LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst);
1061 cris_cc_mask(dc, CC_MASK_NZVC);
cf7e0c80 1062 insn_len += dec10_ind_bound(env, dc, size);
40e9eddd
EI		 1063 break;
1064 case CRISV10_IND_AND:
1065 LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst);
1066 cris_cc_mask(dc, CC_MASK_NZVC);
cf7e0c80 1067 insn_len += dec10_ind_alu(env, dc, CC_OP_AND, size);
40e9eddd
EI		 1068 break;
1069 case CRISV10_IND_OR:
1070 LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst);
1071 cris_cc_mask(dc, CC_MASK_NZVC);
cf7e0c80 1072 insn_len += dec10_ind_alu(env, dc, CC_OP_OR, size);
40e9eddd
EI		 1073 break;
1074 case CRISV10_IND_MOVX:
cf7e0c80 1075 insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
40e9eddd
EI		 1076 break;
1077 case CRISV10_IND_ADDX:
cf7e0c80 1078 insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
40e9eddd
EI		 1079 break;
1080 case CRISV10_IND_SUBX:
cf7e0c80 1081 insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
40e9eddd
EI		 1082 break;
1083 case CRISV10_IND_CMPX:
cf7e0c80 1084 insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
40e9eddd
EI		 1085 break;
1086 case CRISV10_IND_MUL:
1087 /* This is a reg insn coded in the mem indir space. */
1088 LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode);
1089 cris_cc_mask(dc, CC_MASK_NZVC);
1090 dec10_reg_mul(dc, size, dc->ir & (1 << 10));
1091 break;
1092 case CRISV10_IND_BDAP_M:
cf7e0c80 1093 insn_len = dec10_bdap_m(env, dc, size);
40e9eddd
EI		 1094 break;
1095 default:
1096 LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
1097 dc->pc, size, dc->opcode, dc->src, dc->dst);
0dd106c5 1098 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
40e9eddd
EI		 1099 break;
1100 }
1101 return insn_len;
1102 }
1103
1104 switch (dc->opcode) {
1105 case CRISV10_IND_MOVE_M_SPR:
cf7e0c80 1106 insn_len = dec10_ind_move_m_pr(env, dc);
40e9eddd
EI		 1107 break;
1108 case CRISV10_IND_MOVE_SPR_M:
1109 insn_len = dec10_ind_move_pr_m(dc);
1110 break;
1111 case CRISV10_IND_JUMP_M:
1112 if (dc->src == 15) {
5cabc5cc 1113 LOG_DIS("jump.%d %d r%d r%d direct\n", size,
40e9eddd 1114 dc->opcode, dc->src, dc->dst);
cf7e0c80 1115 imm = cpu_ldl_code(env, dc->pc + 2);
40e9eddd
EI		 1116 if (dc->mode == CRISV10_MODE_AUTOINC)
1117 insn_len += size;
1118
1119 t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
5cabc5cc
EI		 1120 dc->jmp_pc = imm;
1121 cris_prepare_jmp(dc, JMP_DIRECT);
40e9eddd
EI		 1122 dc->delayed_branch--; /* v10 has no dslot here. */
1123 } else {
1124 if (dc->dst == 14) {
1125 LOG_DIS("break %d\n", dc->src);
1126 cris_evaluate_flags(dc);
1127 tcg_gen_movi_tl(env_pc, dc->pc + 2);
f756c7a7 1128 t_gen_mov_env_TN(trap_vector, tcg_const_tl(dc->src + 2));
40e9eddd
EI		 1129 t_gen_raise_exception(EXCP_BREAK);
1130 dc->is_jmp = DISAS_UPDATE;
1131 return insn_len;
1132 }
1133 LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
1134 dc->opcode, dc->src, dc->dst);
1135 t[0] = tcg_temp_new();
1136 t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
1137 crisv10_prepare_memaddr(dc, t[0], size);
1138 gen_load(dc, env_btarget, t[0], 4, 0);
1139 insn_len += crisv10_post_memaddr(dc, size);
1140 cris_prepare_jmp(dc, JMP_INDIRECT);
1141 dc->delayed_branch--; /* v10 has no dslot here. */
1142 tcg_temp_free(t[0]);
1143 }
1144 break;
1145
1146 case CRISV10_IND_MOVEM_R_M:
1147 LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n",
1148 dc->pc, dc->opcode, dc->dst, dc->src);
1149 dec10_movem_r_m(dc);
1150 break;
1151 case CRISV10_IND_MOVEM_M_R:
1152 LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode);
1153 dec10_movem_m_r(dc);
1154 break;
1155 case CRISV10_IND_JUMP_R:
1156 LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
1157 dc->pc, dc->opcode, dc->dst, dc->src);
1158 tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
1159 t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
1160 cris_prepare_jmp(dc, JMP_INDIRECT);
1161 dc->delayed_branch--; /* v10 has no dslot here. */
1162 break;
1163 case CRISV10_IND_MOVX:
cf7e0c80 1164 insn_len = dec10_alux_m(env, dc, CC_OP_MOVE);
40e9eddd
EI		 1165 break;
1166 case CRISV10_IND_ADDX:
cf7e0c80 1167 insn_len = dec10_alux_m(env, dc, CC_OP_ADD);
40e9eddd
EI		 1168 break;
1169 case CRISV10_IND_SUBX:
cf7e0c80 1170 insn_len = dec10_alux_m(env, dc, CC_OP_SUB);
40e9eddd
EI		 1171 break;
1172 case CRISV10_IND_CMPX:
cf7e0c80 1173 insn_len = dec10_alux_m(env, dc, CC_OP_CMP);
40e9eddd
EI		 1174 break;
1175 case CRISV10_IND_DIP:
cf7e0c80 1176 insn_len = dec10_dip(env, dc);
40e9eddd
EI		 1177 break;
1178 case CRISV10_IND_BCC_M:
1179
1180 cris_cc_mask(dc, 0);
cf7e0c80 1181 imm = cpu_ldsw_code(env, dc->pc + 2);
40e9eddd
EI		 1182 simm = (int16_t)imm;
1183 simm += 4;
1184
1185 LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm);
1186 cris_prepare_cc_branch(dc, simm, dc->cond);
1187 insn_len = 4;
1188 break;
1189 default:
1190 LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
0dd106c5 1191 cpu_abort(CPU(dc->cpu), "Unhandled opcode");
40e9eddd
EI		 1192 break;
1193 }
1194
1195 return insn_len;
1196}
1197
cf7e0c80 1198static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
40e9eddd
EI		 1199{
1200 unsigned int insn_len = 2;
1201
40e9eddd 1202 /* Load a halfword onto the instruction register. */
cf7e0c80 1203 dc->ir = cpu_lduw_code(env, dc->pc);
40e9eddd
EI		 1204
1205 /* Now decode it. */
1206 dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9);
1207 dc->mode = EXTRACT_FIELD(dc->ir, 10, 11);
1208 dc->src = EXTRACT_FIELD(dc->ir, 0, 3);
1209 dc->size = EXTRACT_FIELD(dc->ir, 4, 5);
1210 dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15);
1211 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
1212
1213 dc->clear_prefix = 1;
1214
1215 /* FIXME: What if this insn insn't 2 in length?? */
1216 if (dc->src == 15 || dc->dst == 15)
1217 tcg_gen_movi_tl(cpu_R[15], dc->pc + 2);
1218
1219 switch (dc->mode) {
1220 case CRISV10_MODE_QIMMEDIATE:
1221 insn_len = dec10_quick_imm(dc);
1222 break;
1223 case CRISV10_MODE_REG:
1224 insn_len = dec10_reg(dc);
1225 break;
1226 case CRISV10_MODE_AUTOINC:
1227 case CRISV10_MODE_INDIRECT:
cf7e0c80 1228 insn_len = dec10_ind(env, dc);
40e9eddd
EI		 1229 break;
1230 }
1231
1232 if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
1233 dc->tb_flags &= ~PFIX_FLAG;
1234 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG);
5cabc5cc
EI		 1235 if (dc->tb_flags != dc->tb->flags) {
1236 dc->cpustate_changed = 1;
1237 }
40e9eddd
EI		 1238 }
1239
4ffb9ae2
EI		 1240 /* CRISv10 locks out interrupts on dslots. */
1241 if (dc->delayed_branch == 2) {
1242 cris_lock_irq(dc);
1243 }
40e9eddd
EI		 1244 return insn_len;
1245}
1246
d1a94fec 1247void cris_initialize_crisv10_tcg(void)
40e9eddd
EI		 1248{
1249 int i;
1250
1251 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1252 cc_x = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1253 offsetof(CPUCRISState, cc_x), "cc_x");
40e9eddd 1254 cc_src = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1255 offsetof(CPUCRISState, cc_src), "cc_src");
40e9eddd 1256 cc_dest = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1257 offsetof(CPUCRISState, cc_dest),
40e9eddd
EI		 1258 "cc_dest");
1259 cc_result = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1260 offsetof(CPUCRISState, cc_result),
40e9eddd
EI		 1261 "cc_result");
1262 cc_op = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1263 offsetof(CPUCRISState, cc_op), "cc_op");
40e9eddd 1264 cc_size = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1265 offsetof(CPUCRISState, cc_size),
40e9eddd
EI		 1266 "cc_size");
1267 cc_mask = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1268 offsetof(CPUCRISState, cc_mask),
40e9eddd
EI		 1269 "cc_mask");
1270
1271 env_pc = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1272 offsetof(CPUCRISState, pc),
40e9eddd
EI		 1273 "pc");
1274 env_btarget = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1275 offsetof(CPUCRISState, btarget),
40e9eddd
EI		 1276 "btarget");
1277 env_btaken = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1278 offsetof(CPUCRISState, btaken),
40e9eddd
EI		 1279 "btaken");
1280 for (i = 0; i < 16; i++) {
1281 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1282 offsetof(CPUCRISState, regs[i]),
40e9eddd
EI		 1283 regnames_v10[i]);
1284 }
1285 for (i = 0; i < 16; i++) {
1286 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
a1170bfd 1287 offsetof(CPUCRISState, pregs[i]),
40e9eddd
EI		 1288 pregnames_v10[i]);
1289 }
40e9eddd 1290}
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