[qemu.git] / target-i386 / cc_helper.c

/*
 *  x86 condition code helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "helper.h"

const uint8_t parity_table[256] = {
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
};

#define SHIFT 0
#include "cc_helper_template.h"
#undef SHIFT

#define SHIFT 1
#include "cc_helper_template.h"
#undef SHIFT

#define SHIFT 2
#include "cc_helper_template.h"
#undef SHIFT

#ifdef TARGET_X86_64

#define SHIFT 3
#include "cc_helper_template.h"
#undef SHIFT

#endif

uint32_t helper_cc_compute_all(CPUX86State *env, int op)
{
    target_ulong dst = CC_DST, src1 = CC_SRC;

    switch (op) {
    default: /* should never happen */
        return 0;

    case CC_OP_EFLAGS:
        return src1;

    case CC_OP_MULB:
        return compute_all_mulb(dst, src1);
    case CC_OP_MULW:
        return compute_all_mulw(dst, src1);
    case CC_OP_MULL:
        return compute_all_mull(dst, src1);

    case CC_OP_ADDB:
        return compute_all_addb(dst, src1);
    case CC_OP_ADDW:
        return compute_all_addw(dst, src1);
    case CC_OP_ADDL:
        return compute_all_addl(dst, src1);

    case CC_OP_ADCB:
        return compute_all_adcb(dst, src1);
    case CC_OP_ADCW:
        return compute_all_adcw(dst, src1);
    case CC_OP_ADCL:
        return compute_all_adcl(dst, src1);

    case CC_OP_SUBB:
        return compute_all_subb(dst, src1);
    case CC_OP_SUBW:
        return compute_all_subw(dst, src1);
    case CC_OP_SUBL:
        return compute_all_subl(dst, src1);

    case CC_OP_SBBB:
        return compute_all_sbbb(dst, src1);
    case CC_OP_SBBW:
        return compute_all_sbbw(dst, src1);
    case CC_OP_SBBL:
        return compute_all_sbbl(dst, src1);

    case CC_OP_LOGICB:
        return compute_all_logicb(dst, src1);
    case CC_OP_LOGICW:
        return compute_all_logicw(dst, src1);
    case CC_OP_LOGICL:
        return compute_all_logicl(dst, src1);

    case CC_OP_INCB:
        return compute_all_incb(dst, src1);
    case CC_OP_INCW:
        return compute_all_incw(dst, src1);
    case CC_OP_INCL:
        return compute_all_incl(dst, src1);

    case CC_OP_DECB:
        return compute_all_decb(dst, src1);
    case CC_OP_DECW:
        return compute_all_decw(dst, src1);
    case CC_OP_DECL:
        return compute_all_decl(dst, src1);

    case CC_OP_SHLB:
        return compute_all_shlb(dst, src1);
    case CC_OP_SHLW:
        return compute_all_shlw(dst, src1);
    case CC_OP_SHLL:
        return compute_all_shll(dst, src1);

    case CC_OP_SARB:
        return compute_all_sarb(dst, src1);
    case CC_OP_SARW:
        return compute_all_sarw(dst, src1);
    case CC_OP_SARL:
        return compute_all_sarl(dst, src1);

#ifdef TARGET_X86_64
    case CC_OP_MULQ:
        return compute_all_mulq(dst, src1);
    case CC_OP_ADDQ:
        return compute_all_addq(dst, src1);
    case CC_OP_ADCQ:
        return compute_all_adcq(dst, src1);
    case CC_OP_SUBQ:
        return compute_all_subq(dst, src1);
    case CC_OP_SBBQ:
        return compute_all_sbbq(dst, src1);
    case CC_OP_LOGICQ:
        return compute_all_logicq(dst, src1);
    case CC_OP_INCQ:
        return compute_all_incq(dst, src1);
    case CC_OP_DECQ:
        return compute_all_decq(dst, src1);
    case CC_OP_SHLQ:
        return compute_all_shlq(dst, src1);
    case CC_OP_SARQ:
        return compute_all_sarq(dst, src1);
#endif
    }
}

uint32_t cpu_cc_compute_all(CPUX86State *env, int op)
{
    return helper_cc_compute_all(env, op);
}

uint32_t helper_cc_compute_c(CPUX86State *env, int op)
{
    target_ulong dst = CC_DST, src1 = CC_SRC;

    switch (op) {
    default: /* should never happen */
    case CC_OP_LOGICB:
    case CC_OP_LOGICW:
    case CC_OP_LOGICL:
    case CC_OP_LOGICQ:
        return 0;

    case CC_OP_EFLAGS:
    case CC_OP_SARB:
    case CC_OP_SARW:
    case CC_OP_SARL:
    case CC_OP_SARQ:
        return src1 & 1;

    case CC_OP_INCB:
    case CC_OP_INCW:
    case CC_OP_INCL:
    case CC_OP_INCQ:
    case CC_OP_DECB:
    case CC_OP_DECW:
    case CC_OP_DECL:
    case CC_OP_DECQ:
        return src1;

    case CC_OP_MULB:
    case CC_OP_MULW:
    case CC_OP_MULL:
    case CC_OP_MULQ:
        return src1 != 0;

    case CC_OP_ADDB:
        return compute_c_addb(dst, src1);
    case CC_OP_ADDW:
        return compute_c_addw(dst, src1);
    case CC_OP_ADDL:
        return compute_c_addl(dst, src1);

    case CC_OP_ADCB:
        return compute_c_adcb(dst, src1);
    case CC_OP_ADCW:
        return compute_c_adcw(dst, src1);
    case CC_OP_ADCL:
        return compute_c_adcl(dst, src1);

    case CC_OP_SUBB:
        return compute_c_subb(dst, src1);
    case CC_OP_SUBW:
        return compute_c_subw(dst, src1);
    case CC_OP_SUBL:
        return compute_c_subl(dst, src1);

    case CC_OP_SBBB:
        return compute_c_sbbb(dst, src1);
    case CC_OP_SBBW:
        return compute_c_sbbw(dst, src1);
    case CC_OP_SBBL:
        return compute_c_sbbl(dst, src1);

    case CC_OP_SHLB:
        return compute_c_shlb(dst, src1);
    case CC_OP_SHLW:
        return compute_c_shlw(dst, src1);
    case CC_OP_SHLL:
        return compute_c_shll(dst, src1);

#ifdef TARGET_X86_64
    case CC_OP_ADDQ:
        return compute_c_addq(dst, src1);
    case CC_OP_ADCQ:
        return compute_c_adcq(dst, src1);
    case CC_OP_SUBQ:
        return compute_c_subq(dst, src1);
    case CC_OP_SBBQ:
        return compute_c_sbbq(dst, src1);
    case CC_OP_SHLQ:
        return compute_c_shlq(dst, src1);
#endif
    }
}

void helper_write_eflags(CPUX86State *env, target_ulong t0,
                         uint32_t update_mask)
{
    cpu_load_eflags(env, t0, update_mask);
}

target_ulong helper_read_eflags(CPUX86State *env)
{
    uint32_t eflags;

    eflags = helper_cc_compute_all(env, CC_OP);
    eflags |= (DF & DF_MASK);
    eflags |= env->eflags & ~(VM_MASK | RF_MASK);
    return eflags;
}

void helper_clts(CPUX86State *env)
{
    env->cr[0] &= ~CR0_TS_MASK;
    env->hflags &= ~HF_TS_MASK;
}

void helper_reset_rf(CPUX86State *env)
{
    env->eflags &= ~RF_MASK;
}

void helper_cli(CPUX86State *env)
{
    env->eflags &= ~IF_MASK;
}

void helper_sti(CPUX86State *env)
{
    env->eflags |= IF_MASK;
}

void helper_clac(CPUX86State *env)
{
    env->eflags &= ~AC_MASK;
}

void helper_stac(CPUX86State *env)
{
    env->eflags |= AC_MASK;
}

#if 0
/* vm86plus instructions */
void helper_cli_vm(CPUX86State *env)
{
    env->eflags &= ~VIF_MASK;
}

void helper_sti_vm(CPUX86State *env)
{
    env->eflags |= VIF_MASK;
    if (env->eflags & VIP_MASK) {
        raise_exception(env, EXCP0D_GPF);
    }
}
#endif

void helper_set_inhibit_irq(CPUX86State *env)
{
    env->hflags |= HF_INHIBIT_IRQ_MASK;
}

void helper_reset_inhibit_irq(CPUX86State *env)
{
    env->hflags &= ~HF_INHIBIT_IRQ_MASK;
}
Commit	Line	Data
5918fffb BS	1	/*
	2	* x86 condition code helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "cpu.h"
5918fffb BS	21	#include "helper.h"
	22
	23	const uint8_t parity_table[256] = {
	24	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	25	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	26	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	27	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	28	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	29	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	30	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	31	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	32	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	33	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	34	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	35	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	36	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	37	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	38	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	39	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	40	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	41	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	42	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	43	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	44	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	45	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	46	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	47	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	48	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	49	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	50	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	51	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	52	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	53	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	54	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	55	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	56	};
	57
	58	#define SHIFT 0
	59	#include "cc_helper_template.h"
	60	#undef SHIFT
	61
	62	#define SHIFT 1
	63	#include "cc_helper_template.h"
	64	#undef SHIFT
	65
	66	#define SHIFT 2
	67	#include "cc_helper_template.h"
	68	#undef SHIFT
	69
	70	#ifdef TARGET_X86_64
	71
	72	#define SHIFT 3
	73	#include "cc_helper_template.h"
	74	#undef SHIFT
	75
	76	#endif
	77
f0967a1a	78	uint32_t helper_cc_compute_all(CPUX86State *env, int op)
5918fffb	79	{
8601c0b6 RH	80	target_ulong dst = CC_DST, src1 = CC_SRC;
8601c0b6 RH	81
5918fffb BS	82	switch (op) {
	83	default: /* should never happen */
	84	return 0;
	85
	86	case CC_OP_EFLAGS:
8601c0b6	87	return src1;
5918fffb BS	88
5918fffb BS	89	case CC_OP_MULB:
8601c0b6	90	return compute_all_mulb(dst, src1);
5918fffb	91	case CC_OP_MULW:
8601c0b6	92	return compute_all_mulw(dst, src1);
5918fffb	93	case CC_OP_MULL:
8601c0b6	94	return compute_all_mull(dst, src1);
5918fffb BS	95
5918fffb BS	96	case CC_OP_ADDB:
8601c0b6	97	return compute_all_addb(dst, src1);
5918fffb	98	case CC_OP_ADDW:
8601c0b6	99	return compute_all_addw(dst, src1);
5918fffb	100	case CC_OP_ADDL:
8601c0b6	101	return compute_all_addl(dst, src1);
5918fffb BS	102
5918fffb BS	103	case CC_OP_ADCB:
8601c0b6	104	return compute_all_adcb(dst, src1);
5918fffb	105	case CC_OP_ADCW:
8601c0b6	106	return compute_all_adcw(dst, src1);
5918fffb	107	case CC_OP_ADCL:
8601c0b6	108	return compute_all_adcl(dst, src1);
5918fffb BS	109
5918fffb BS	110	case CC_OP_SUBB:
8601c0b6	111	return compute_all_subb(dst, src1);
5918fffb	112	case CC_OP_SUBW:
8601c0b6	113	return compute_all_subw(dst, src1);
5918fffb	114	case CC_OP_SUBL:
8601c0b6	115	return compute_all_subl(dst, src1);
5918fffb BS	116
5918fffb BS	117	case CC_OP_SBBB:
8601c0b6	118	return compute_all_sbbb(dst, src1);
5918fffb	119	case CC_OP_SBBW:
8601c0b6	120	return compute_all_sbbw(dst, src1);
5918fffb	121	case CC_OP_SBBL:
8601c0b6	122	return compute_all_sbbl(dst, src1);
5918fffb BS	123
5918fffb BS	124	case CC_OP_LOGICB:
8601c0b6	125	return compute_all_logicb(dst, src1);
5918fffb	126	case CC_OP_LOGICW:
8601c0b6	127	return compute_all_logicw(dst, src1);
5918fffb	128	case CC_OP_LOGICL:
8601c0b6	129	return compute_all_logicl(dst, src1);
5918fffb BS	130
5918fffb BS	131	case CC_OP_INCB:
8601c0b6	132	return compute_all_incb(dst, src1);
5918fffb	133	case CC_OP_INCW:
8601c0b6	134	return compute_all_incw(dst, src1);
5918fffb	135	case CC_OP_INCL:
8601c0b6	136	return compute_all_incl(dst, src1);
5918fffb BS	137
5918fffb BS	138	case CC_OP_DECB:
8601c0b6	139	return compute_all_decb(dst, src1);
5918fffb	140	case CC_OP_DECW:
8601c0b6	141	return compute_all_decw(dst, src1);
5918fffb	142	case CC_OP_DECL:
8601c0b6	143	return compute_all_decl(dst, src1);
5918fffb BS	144
5918fffb BS	145	case CC_OP_SHLB:
8601c0b6	146	return compute_all_shlb(dst, src1);
5918fffb	147	case CC_OP_SHLW:
8601c0b6	148	return compute_all_shlw(dst, src1);
5918fffb	149	case CC_OP_SHLL:
8601c0b6	150	return compute_all_shll(dst, src1);
5918fffb BS	151
5918fffb BS	152	case CC_OP_SARB:
8601c0b6	153	return compute_all_sarb(dst, src1);
5918fffb	154	case CC_OP_SARW:
8601c0b6	155	return compute_all_sarw(dst, src1);
5918fffb	156	case CC_OP_SARL:
8601c0b6	157	return compute_all_sarl(dst, src1);
5918fffb BS	158
	159	#ifdef TARGET_X86_64
	160	case CC_OP_MULQ:
8601c0b6	161	return compute_all_mulq(dst, src1);
5918fffb	162	case CC_OP_ADDQ:
8601c0b6	163	return compute_all_addq(dst, src1);
5918fffb	164	case CC_OP_ADCQ:
8601c0b6	165	return compute_all_adcq(dst, src1);
5918fffb	166	case CC_OP_SUBQ:
8601c0b6	167	return compute_all_subq(dst, src1);
5918fffb	168	case CC_OP_SBBQ:
8601c0b6	169	return compute_all_sbbq(dst, src1);
5918fffb	170	case CC_OP_LOGICQ:
8601c0b6	171	return compute_all_logicq(dst, src1);
5918fffb	172	case CC_OP_INCQ:
8601c0b6	173	return compute_all_incq(dst, src1);
5918fffb	174	case CC_OP_DECQ:
8601c0b6	175	return compute_all_decq(dst, src1);
5918fffb	176	case CC_OP_SHLQ:
8601c0b6	177	return compute_all_shlq(dst, src1);
5918fffb	178	case CC_OP_SARQ:
8601c0b6	179	return compute_all_sarq(dst, src1);
5918fffb BS	180	#endif
	181	}
	182	}
	183
f0967a1a	184	uint32_t cpu_cc_compute_all(CPUX86State *env, int op)
5918fffb	185	{
f0967a1a	186	return helper_cc_compute_all(env, op);
5918fffb BS	187	}
5918fffb BS	188
f0967a1a	189	uint32_t helper_cc_compute_c(CPUX86State *env, int op)
5918fffb	190	{
8601c0b6 RH	191	target_ulong dst = CC_DST, src1 = CC_SRC;
8601c0b6 RH	192
5918fffb BS	193	switch (op) {
5918fffb BS	194	default: /* should never happen */
8601c0b6 RH	195	case CC_OP_LOGICB:
	196	case CC_OP_LOGICW:
	197	case CC_OP_LOGICL:
	198	case CC_OP_LOGICQ:
5918fffb BS	199	return 0;
	200
	201	case CC_OP_EFLAGS:
8601c0b6 RH	202	case CC_OP_SARB:
	203	case CC_OP_SARW:
	204	case CC_OP_SARL:
	205	case CC_OP_SARQ:
	206	return src1 & 1;
	207
	208	case CC_OP_INCB:
	209	case CC_OP_INCW:
	210	case CC_OP_INCL:
	211	case CC_OP_INCQ:
	212	case CC_OP_DECB:
	213	case CC_OP_DECW:
	214	case CC_OP_DECL:
	215	case CC_OP_DECQ:
	216	return src1;
5918fffb BS	217
5918fffb BS	218	case CC_OP_MULB:
5918fffb	219	case CC_OP_MULW:
5918fffb	220	case CC_OP_MULL:
8601c0b6 RH	221	case CC_OP_MULQ:
8601c0b6 RH	222	return src1 != 0;
5918fffb BS	223
5918fffb BS	224	case CC_OP_ADDB:
8601c0b6	225	return compute_c_addb(dst, src1);
5918fffb	226	case CC_OP_ADDW:
8601c0b6	227	return compute_c_addw(dst, src1);
5918fffb	228	case CC_OP_ADDL:
8601c0b6	229	return compute_c_addl(dst, src1);
5918fffb BS	230
5918fffb BS	231	case CC_OP_ADCB:
8601c0b6	232	return compute_c_adcb(dst, src1);
5918fffb	233	case CC_OP_ADCW:
8601c0b6	234	return compute_c_adcw(dst, src1);
5918fffb	235	case CC_OP_ADCL:
8601c0b6	236	return compute_c_adcl(dst, src1);
5918fffb BS	237
5918fffb BS	238	case CC_OP_SUBB:
8601c0b6	239	return compute_c_subb(dst, src1);
5918fffb	240	case CC_OP_SUBW:
8601c0b6	241	return compute_c_subw(dst, src1);
5918fffb	242	case CC_OP_SUBL:
8601c0b6	243	return compute_c_subl(dst, src1);
5918fffb BS	244
5918fffb BS	245	case CC_OP_SBBB:
8601c0b6	246	return compute_c_sbbb(dst, src1);
5918fffb	247	case CC_OP_SBBW:
8601c0b6	248	return compute_c_sbbw(dst, src1);
5918fffb	249	case CC_OP_SBBL:
8601c0b6	250	return compute_c_sbbl(dst, src1);
5918fffb BS	251
5918fffb BS	252	case CC_OP_SHLB:
8601c0b6	253	return compute_c_shlb(dst, src1);
5918fffb	254	case CC_OP_SHLW:
8601c0b6	255	return compute_c_shlw(dst, src1);
5918fffb	256	case CC_OP_SHLL:
8601c0b6	257	return compute_c_shll(dst, src1);
5918fffb BS	258
5918fffb BS	259	#ifdef TARGET_X86_64
5918fffb	260	case CC_OP_ADDQ:
8601c0b6	261	return compute_c_addq(dst, src1);
5918fffb	262	case CC_OP_ADCQ:
8601c0b6	263	return compute_c_adcq(dst, src1);
5918fffb	264	case CC_OP_SUBQ:
8601c0b6	265	return compute_c_subq(dst, src1);
5918fffb	266	case CC_OP_SBBQ:
8601c0b6	267	return compute_c_sbbq(dst, src1);
5918fffb	268	case CC_OP_SHLQ:
8601c0b6	269	return compute_c_shlq(dst, src1);
5918fffb BS	270	#endif
	271	}
	272	}
	273
f0967a1a BS	274	void helper_write_eflags(CPUX86State *env, target_ulong t0,
f0967a1a BS	275	uint32_t update_mask)
5918fffb BS	276	{
	277	cpu_load_eflags(env, t0, update_mask);
	278	}
	279
f0967a1a	280	target_ulong helper_read_eflags(CPUX86State *env)
5918fffb BS	281	{
	282	uint32_t eflags;
	283
f0967a1a	284	eflags = helper_cc_compute_all(env, CC_OP);
5918fffb BS	285	eflags \|= (DF & DF_MASK);
	286	eflags \|= env->eflags & ~(VM_MASK \| RF_MASK);
	287	return eflags;
	288	}
	289
f0967a1a	290	void helper_clts(CPUX86State *env)
5918fffb BS	291	{
	292	env->cr[0] &= ~CR0_TS_MASK;
	293	env->hflags &= ~HF_TS_MASK;
	294	}
	295
f0967a1a	296	void helper_reset_rf(CPUX86State *env)
5918fffb BS	297	{
	298	env->eflags &= ~RF_MASK;
	299	}
	300
f0967a1a	301	void helper_cli(CPUX86State *env)
5918fffb BS	302	{
	303	env->eflags &= ~IF_MASK;
	304	}
	305
f0967a1a	306	void helper_sti(CPUX86State *env)
5918fffb BS	307	{
	308	env->eflags \|= IF_MASK;
	309	}
	310
a9321a4d PA	311	void helper_clac(CPUX86State *env)
	312	{
	313	env->eflags &= ~AC_MASK;
	314	}
	315
	316	void helper_stac(CPUX86State *env)
	317	{
	318	env->eflags \|= AC_MASK;
	319	}
	320
5918fffb BS	321	#if 0
5918fffb BS	322	/* vm86plus instructions */
f0967a1a	323	void helper_cli_vm(CPUX86State *env)
5918fffb BS	324	{
	325	env->eflags &= ~VIF_MASK;
	326	}
	327
f0967a1a	328	void helper_sti_vm(CPUX86State *env)
5918fffb BS	329	{
	330	env->eflags \|= VIF_MASK;
	331	if (env->eflags & VIP_MASK) {
	332	raise_exception(env, EXCP0D_GPF);
	333	}
	334	}
	335	#endif
	336
f0967a1a	337	void helper_set_inhibit_irq(CPUX86State *env)
5918fffb BS	338	{
	339	env->hflags \|= HF_INHIBIT_IRQ_MASK;
	340	}
	341
f0967a1a	342	void helper_reset_inhibit_irq(CPUX86State *env)
5918fffb BS	343	{
	344	env->hflags &= ~HF_INHIBIT_IRQ_MASK;
	345	}