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Commit | Line | Data |
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2c0262af | 1 | /* |
5fafdf24 | 2 | * i386 execution defines |
2c0262af FB |
3 | * |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
7d3505c5 | 20 | #include "config.h" |
2c0262af FB |
21 | #include "dyngen-exec.h" |
22 | ||
14ce26e7 | 23 | /* XXX: factorize this mess */ |
14ce26e7 FB |
24 | #ifdef TARGET_X86_64 |
25 | #define TARGET_LONG_BITS 64 | |
26 | #else | |
27 | #define TARGET_LONG_BITS 32 | |
28 | #endif | |
29 | ||
d785e6be FB |
30 | #include "cpu-defs.h" |
31 | ||
2c0262af | 32 | register struct CPUX86State *env asm(AREG0); |
14ce26e7 | 33 | |
79383c9c | 34 | #include "qemu-log.h" |
2c0262af | 35 | |
2c0262af | 36 | #define EAX (env->regs[R_EAX]) |
2c0262af | 37 | #define ECX (env->regs[R_ECX]) |
2c0262af | 38 | #define EDX (env->regs[R_EDX]) |
2c0262af | 39 | #define EBX (env->regs[R_EBX]) |
2c0262af | 40 | #define ESP (env->regs[R_ESP]) |
2c0262af | 41 | #define EBP (env->regs[R_EBP]) |
2c0262af | 42 | #define ESI (env->regs[R_ESI]) |
2c0262af | 43 | #define EDI (env->regs[R_EDI]) |
1e4840bf | 44 | #define EIP (env->eip) |
2c0262af FB |
45 | #define DF (env->df) |
46 | ||
47 | #define CC_SRC (env->cc_src) | |
48 | #define CC_DST (env->cc_dst) | |
49 | #define CC_OP (env->cc_op) | |
50 | ||
51 | /* float macros */ | |
52 | #define FT0 (env->ft0) | |
664e0f19 FB |
53 | #define ST0 (env->fpregs[env->fpstt].d) |
54 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) | |
2c0262af FB |
55 | #define ST1 ST(1) |
56 | ||
2c0262af FB |
57 | #include "cpu.h" |
58 | #include "exec-all.h" | |
59 | ||
14ce26e7 | 60 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); |
1ac157da | 61 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); |
5fafdf24 | 62 | int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, |
6ebbf390 | 63 | int is_write, int mmu_idx, int is_softmmu); |
2c0262af FB |
64 | void __hidden cpu_lock(void); |
65 | void __hidden cpu_unlock(void); | |
5fafdf24 | 66 | void do_interrupt(int intno, int is_int, int error_code, |
14ce26e7 | 67 | target_ulong next_eip, int is_hw); |
5fafdf24 | 68 | void do_interrupt_user(int intno, int is_int, int error_code, |
14ce26e7 | 69 | target_ulong next_eip); |
5fafdf24 | 70 | void raise_interrupt(int intno, int is_int, int error_code, |
a8ede8ba | 71 | int next_eip_addend); |
2c0262af FB |
72 | void raise_exception_err(int exception_index, int error_code); |
73 | void raise_exception(int exception_index); | |
3b21e03e | 74 | void do_smm_enter(void); |
2c0262af | 75 | void __hidden cpu_loop_exit(void); |
2c0262af FB |
76 | |
77 | void OPPROTO op_movl_eflags_T0(void); | |
78 | void OPPROTO op_movl_T0_eflags(void); | |
57fec1fe | 79 | |
b6abf97d FB |
80 | /* n must be a constant to be efficient */ |
81 | static inline target_long lshift(target_long x, int n) | |
82 | { | |
83 | if (n >= 0) | |
84 | return x << n; | |
85 | else | |
86 | return x >> (-n); | |
87 | } | |
88 | ||
57fec1fe FB |
89 | #include "helper.h" |
90 | ||
b8b6a50b FB |
91 | static inline void svm_check_intercept(uint32_t type) |
92 | { | |
93 | helper_svm_check_intercept_param(type, 0); | |
94 | } | |
3e25f951 | 95 | |
9951bf39 FB |
96 | #if !defined(CONFIG_USER_ONLY) |
97 | ||
a9049a07 | 98 | #include "softmmu_exec.h" |
9951bf39 | 99 | |
9951bf39 FB |
100 | #endif /* !defined(CONFIG_USER_ONLY) */ |
101 | ||
2c0262af FB |
102 | #ifdef USE_X86LDOUBLE |
103 | /* use long double functions */ | |
7a0e1f41 FB |
104 | #define floatx_to_int32 floatx80_to_int32 |
105 | #define floatx_to_int64 floatx80_to_int64 | |
465e9838 FB |
106 | #define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero |
107 | #define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero | |
19e6c4b8 FB |
108 | #define int32_to_floatx int32_to_floatx80 |
109 | #define int64_to_floatx int64_to_floatx80 | |
110 | #define float32_to_floatx float32_to_floatx80 | |
111 | #define float64_to_floatx float64_to_floatx80 | |
112 | #define floatx_to_float32 floatx80_to_float32 | |
113 | #define floatx_to_float64 floatx80_to_float64 | |
7a0e1f41 FB |
114 | #define floatx_abs floatx80_abs |
115 | #define floatx_chs floatx80_chs | |
116 | #define floatx_round_to_int floatx80_round_to_int | |
8422b113 FB |
117 | #define floatx_compare floatx80_compare |
118 | #define floatx_compare_quiet floatx80_compare_quiet | |
7d3505c5 | 119 | #else |
7a0e1f41 FB |
120 | #define floatx_to_int32 float64_to_int32 |
121 | #define floatx_to_int64 float64_to_int64 | |
465e9838 FB |
122 | #define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero |
123 | #define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero | |
19e6c4b8 FB |
124 | #define int32_to_floatx int32_to_float64 |
125 | #define int64_to_floatx int64_to_float64 | |
126 | #define float32_to_floatx float32_to_float64 | |
127 | #define float64_to_floatx(x, e) (x) | |
128 | #define floatx_to_float32 float64_to_float32 | |
129 | #define floatx_to_float64(x, e) (x) | |
7a0e1f41 FB |
130 | #define floatx_abs float64_abs |
131 | #define floatx_chs float64_chs | |
132 | #define floatx_round_to_int float64_round_to_int | |
8422b113 FB |
133 | #define floatx_compare float64_compare |
134 | #define floatx_compare_quiet float64_compare_quiet | |
7d3505c5 | 135 | #endif |
7a0e1f41 | 136 | |
2c0262af FB |
137 | #define RC_MASK 0xc00 |
138 | #define RC_NEAR 0x000 | |
139 | #define RC_DOWN 0x400 | |
140 | #define RC_UP 0x800 | |
141 | #define RC_CHOP 0xc00 | |
142 | ||
143 | #define MAXTAN 9223372036854775808.0 | |
144 | ||
2c0262af FB |
145 | #ifdef USE_X86LDOUBLE |
146 | ||
147 | /* only for x86 */ | |
148 | typedef union { | |
149 | long double d; | |
150 | struct { | |
151 | unsigned long long lower; | |
152 | unsigned short upper; | |
153 | } l; | |
154 | } CPU86_LDoubleU; | |
155 | ||
156 | /* the following deal with x86 long double-precision numbers */ | |
157 | #define MAXEXPD 0x7fff | |
158 | #define EXPBIAS 16383 | |
159 | #define EXPD(fp) (fp.l.upper & 0x7fff) | |
160 | #define SIGND(fp) ((fp.l.upper) & 0x8000) | |
161 | #define MANTD(fp) (fp.l.lower) | |
162 | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS | |
163 | ||
164 | #else | |
165 | ||
166 | /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */ | |
167 | typedef union { | |
168 | double d; | |
169 | #if !defined(WORDS_BIGENDIAN) && !defined(__arm__) | |
170 | struct { | |
171 | uint32_t lower; | |
172 | int32_t upper; | |
173 | } l; | |
174 | #else | |
175 | struct { | |
176 | int32_t upper; | |
177 | uint32_t lower; | |
178 | } l; | |
179 | #endif | |
180 | #ifndef __arm__ | |
181 | int64_t ll; | |
182 | #endif | |
183 | } CPU86_LDoubleU; | |
184 | ||
185 | /* the following deal with IEEE double-precision numbers */ | |
186 | #define MAXEXPD 0x7ff | |
187 | #define EXPBIAS 1023 | |
188 | #define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF) | |
189 | #define SIGND(fp) ((fp.l.upper) & 0x80000000) | |
190 | #ifdef __arm__ | |
191 | #define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32)) | |
192 | #else | |
193 | #define MANTD(fp) (fp.ll & ((1LL << 52) - 1)) | |
194 | #endif | |
195 | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20) | |
196 | #endif | |
197 | ||
198 | static inline void fpush(void) | |
199 | { | |
200 | env->fpstt = (env->fpstt - 1) & 7; | |
201 | env->fptags[env->fpstt] = 0; /* validate stack entry */ | |
202 | } | |
203 | ||
204 | static inline void fpop(void) | |
205 | { | |
206 | env->fptags[env->fpstt] = 1; /* invvalidate stack entry */ | |
207 | env->fpstt = (env->fpstt + 1) & 7; | |
208 | } | |
209 | ||
210 | #ifndef USE_X86LDOUBLE | |
14ce26e7 | 211 | static inline CPU86_LDouble helper_fldt(target_ulong ptr) |
2c0262af FB |
212 | { |
213 | CPU86_LDoubleU temp; | |
214 | int upper, e; | |
215 | uint64_t ll; | |
216 | ||
217 | /* mantissa */ | |
218 | upper = lduw(ptr + 8); | |
219 | /* XXX: handle overflow ? */ | |
220 | e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */ | |
221 | e |= (upper >> 4) & 0x800; /* sign */ | |
222 | ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1); | |
223 | #ifdef __arm__ | |
224 | temp.l.upper = (e << 20) | (ll >> 32); | |
225 | temp.l.lower = ll; | |
226 | #else | |
227 | temp.ll = ll | ((uint64_t)e << 52); | |
228 | #endif | |
229 | return temp.d; | |
230 | } | |
231 | ||
664e0f19 | 232 | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr) |
2c0262af FB |
233 | { |
234 | CPU86_LDoubleU temp; | |
235 | int e; | |
236 | ||
237 | temp.d = f; | |
238 | /* mantissa */ | |
239 | stq(ptr, (MANTD(temp) << 11) | (1LL << 63)); | |
240 | /* exponent + sign */ | |
241 | e = EXPD(temp) - EXPBIAS + 16383; | |
242 | e |= SIGND(temp) >> 16; | |
243 | stw(ptr + 8, e); | |
244 | } | |
9951bf39 FB |
245 | #else |
246 | ||
9951bf39 FB |
247 | /* we use memory access macros */ |
248 | ||
14ce26e7 | 249 | static inline CPU86_LDouble helper_fldt(target_ulong ptr) |
9951bf39 FB |
250 | { |
251 | CPU86_LDoubleU temp; | |
252 | ||
253 | temp.l.lower = ldq(ptr); | |
254 | temp.l.upper = lduw(ptr + 8); | |
255 | return temp.d; | |
256 | } | |
257 | ||
14ce26e7 | 258 | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr) |
9951bf39 FB |
259 | { |
260 | CPU86_LDoubleU temp; | |
3b46e624 | 261 | |
9951bf39 FB |
262 | temp.d = f; |
263 | stq(ptr, temp.l.lower); | |
264 | stw(ptr + 8, temp.l.upper); | |
265 | } | |
266 | ||
9951bf39 | 267 | #endif /* USE_X86LDOUBLE */ |
2c0262af | 268 | |
2ee73ac3 FB |
269 | #define FPUS_IE (1 << 0) |
270 | #define FPUS_DE (1 << 1) | |
271 | #define FPUS_ZE (1 << 2) | |
272 | #define FPUS_OE (1 << 3) | |
273 | #define FPUS_UE (1 << 4) | |
274 | #define FPUS_PE (1 << 5) | |
275 | #define FPUS_SF (1 << 6) | |
276 | #define FPUS_SE (1 << 7) | |
277 | #define FPUS_B (1 << 15) | |
278 | ||
279 | #define FPUC_EM 0x3f | |
280 | ||
83fb7adf | 281 | extern const CPU86_LDouble f15rk[7]; |
2c0262af | 282 | |
2ee73ac3 | 283 | void fpu_raise_exception(void); |
03857e31 FB |
284 | void restore_native_fp_state(CPUState *env); |
285 | void save_native_fp_state(CPUState *env); | |
2c0262af | 286 | |
83fb7adf FB |
287 | extern const uint8_t parity_table[256]; |
288 | extern const uint8_t rclw_table[32]; | |
289 | extern const uint8_t rclb_table[32]; | |
2c0262af FB |
290 | |
291 | static inline uint32_t compute_eflags(void) | |
292 | { | |
293 | return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); | |
294 | } | |
295 | ||
2c0262af FB |
296 | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ |
297 | static inline void load_eflags(int eflags, int update_mask) | |
298 | { | |
299 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
300 | DF = 1 - (2 * ((eflags >> 10) & 1)); | |
5fafdf24 | 301 | env->eflags = (env->eflags & ~update_mask) | |
093f8f06 | 302 | (eflags & update_mask) | 0x2; |
2c0262af FB |
303 | } |
304 | ||
0d1a29f9 FB |
305 | static inline void env_to_regs(void) |
306 | { | |
307 | #ifdef reg_EAX | |
308 | EAX = env->regs[R_EAX]; | |
309 | #endif | |
310 | #ifdef reg_ECX | |
311 | ECX = env->regs[R_ECX]; | |
312 | #endif | |
313 | #ifdef reg_EDX | |
314 | EDX = env->regs[R_EDX]; | |
315 | #endif | |
316 | #ifdef reg_EBX | |
317 | EBX = env->regs[R_EBX]; | |
318 | #endif | |
319 | #ifdef reg_ESP | |
320 | ESP = env->regs[R_ESP]; | |
321 | #endif | |
322 | #ifdef reg_EBP | |
323 | EBP = env->regs[R_EBP]; | |
324 | #endif | |
325 | #ifdef reg_ESI | |
326 | ESI = env->regs[R_ESI]; | |
327 | #endif | |
328 | #ifdef reg_EDI | |
329 | EDI = env->regs[R_EDI]; | |
330 | #endif | |
331 | } | |
332 | ||
333 | static inline void regs_to_env(void) | |
334 | { | |
335 | #ifdef reg_EAX | |
336 | env->regs[R_EAX] = EAX; | |
337 | #endif | |
338 | #ifdef reg_ECX | |
339 | env->regs[R_ECX] = ECX; | |
340 | #endif | |
341 | #ifdef reg_EDX | |
342 | env->regs[R_EDX] = EDX; | |
343 | #endif | |
344 | #ifdef reg_EBX | |
345 | env->regs[R_EBX] = EBX; | |
346 | #endif | |
347 | #ifdef reg_ESP | |
348 | env->regs[R_ESP] = ESP; | |
349 | #endif | |
350 | #ifdef reg_EBP | |
351 | env->regs[R_EBP] = EBP; | |
352 | #endif | |
353 | #ifdef reg_ESI | |
354 | env->regs[R_ESI] = ESI; | |
355 | #endif | |
356 | #ifdef reg_EDI | |
357 | env->regs[R_EDI] = EDI; | |
358 | #endif | |
359 | } | |
bfed01fc TS |
360 | |
361 | static inline int cpu_halted(CPUState *env) { | |
362 | /* handle exit of HALTED state */ | |
ce5232c5 | 363 | if (!env->halted) |
bfed01fc TS |
364 | return 0; |
365 | /* disable halt condition */ | |
474ea849 AJ |
366 | if (((env->interrupt_request & CPU_INTERRUPT_HARD) && |
367 | (env->eflags & IF_MASK)) || | |
368 | (env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
ce5232c5 | 369 | env->halted = 0; |
bfed01fc TS |
370 | return 0; |
371 | } | |
372 | return EXCP_HALTED; | |
373 | } | |
0573fbfc | 374 | |
5efc27bb FB |
375 | /* load efer and update the corresponding hflags. XXX: do consistency |
376 | checks with cpuid bits ? */ | |
377 | static inline void cpu_load_efer(CPUState *env, uint64_t val) | |
378 | { | |
379 | env->efer = val; | |
380 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); | |
381 | if (env->efer & MSR_EFER_LMA) | |
382 | env->hflags |= HF_LMA_MASK; | |
383 | if (env->efer & MSR_EFER_SVME) | |
384 | env->hflags |= HF_SVME_MASK; | |
385 | } |