[qemu.git] / target-i386 / exec.h

/*
 *  i386 execution defines
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include "config.h"
#include "dyngen-exec.h"

/* XXX: factorize this mess */
#ifdef TARGET_X86_64
#define TARGET_LONG_BITS 64
#else
#define TARGET_LONG_BITS 32
#endif

#include "cpu-defs.h"

register struct CPUX86State *env asm(AREG0);

extern FILE *logfile;
extern int loglevel;

#define EAX (env->regs[R_EAX])
#define ECX (env->regs[R_ECX])
#define EDX (env->regs[R_EDX])
#define EBX (env->regs[R_EBX])
#define ESP (env->regs[R_ESP])
#define EBP (env->regs[R_EBP])
#define ESI (env->regs[R_ESI])
#define EDI (env->regs[R_EDI])
#define EIP (env->eip)
#define DF  (env->df)

#define CC_SRC (env->cc_src)
#define CC_DST (env->cc_dst)
#define CC_OP  (env->cc_op)

/* float macros */
#define FT0    (env->ft0)
#define ST0    (env->fpregs[env->fpstt].d)
#define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
#define ST1    ST(1)

#include "cpu.h"
#include "exec-all.h"

void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
                             int is_write, int mmu_idx, int is_softmmu);
void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
              void *retaddr);
void __hidden cpu_lock(void);
void __hidden cpu_unlock(void);
void do_interrupt(int intno, int is_int, int error_code,
                  target_ulong next_eip, int is_hw);
void do_interrupt_user(int intno, int is_int, int error_code,
                       target_ulong next_eip);
void raise_interrupt(int intno, int is_int, int error_code,
                     int next_eip_addend);
void raise_exception_err(int exception_index, int error_code);
void raise_exception(int exception_index);
void do_smm_enter(void);
void __hidden cpu_loop_exit(void);

void OPPROTO op_movl_eflags_T0(void);
void OPPROTO op_movl_T0_eflags(void);

/* n must be a constant to be efficient */
static inline target_long lshift(target_long x, int n)
{
    if (n >= 0)
        return x << n;
    else
        return x >> (-n);
}

#include "helper.h"

static inline void svm_check_intercept(uint32_t type)
{
    helper_svm_check_intercept_param(type, 0);
}

#if !defined(CONFIG_USER_ONLY)

#include "softmmu_exec.h"

#endif /* !defined(CONFIG_USER_ONLY) */

#ifdef USE_X86LDOUBLE
/* use long double functions */
#define floatx_to_int32 floatx80_to_int32
#define floatx_to_int64 floatx80_to_int64
#define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
#define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
#define int32_to_floatx int32_to_floatx80
#define int64_to_floatx int64_to_floatx80
#define float32_to_floatx float32_to_floatx80
#define float64_to_floatx float64_to_floatx80
#define floatx_to_float32 floatx80_to_float32
#define floatx_to_float64 floatx80_to_float64
#define floatx_abs floatx80_abs
#define floatx_chs floatx80_chs
#define floatx_round_to_int floatx80_round_to_int
#define floatx_compare floatx80_compare
#define floatx_compare_quiet floatx80_compare_quiet
#define sin sinl
#define cos cosl
#define sqrt sqrtl
#define pow powl
#define log logl
#define tan tanl
#define atan2 atan2l
#define floor floorl
#define ceil ceill
#define ldexp ldexpl
#else
#define floatx_to_int32 float64_to_int32
#define floatx_to_int64 float64_to_int64
#define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
#define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
#define int32_to_floatx int32_to_float64
#define int64_to_floatx int64_to_float64
#define float32_to_floatx float32_to_float64
#define float64_to_floatx(x, e) (x)
#define floatx_to_float32 float64_to_float32
#define floatx_to_float64(x, e) (x)
#define floatx_abs float64_abs
#define floatx_chs float64_chs
#define floatx_round_to_int float64_round_to_int
#define floatx_compare float64_compare
#define floatx_compare_quiet float64_compare_quiet
#endif

extern CPU86_LDouble sin(CPU86_LDouble x);
extern CPU86_LDouble cos(CPU86_LDouble x);
extern CPU86_LDouble sqrt(CPU86_LDouble x);
extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
extern CPU86_LDouble log(CPU86_LDouble x);
extern CPU86_LDouble tan(CPU86_LDouble x);
extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
extern CPU86_LDouble floor(CPU86_LDouble x);
extern CPU86_LDouble ceil(CPU86_LDouble x);

#define RC_MASK         0xc00
#define RC_NEAR		0x000
#define RC_DOWN		0x400
#define RC_UP		0x800
#define RC_CHOP		0xc00

#define MAXTAN 9223372036854775808.0

#ifdef USE_X86LDOUBLE

/* only for x86 */
typedef union {
    long double d;
    struct {
        unsigned long long lower;
        unsigned short upper;
    } l;
} CPU86_LDoubleU;

/* the following deal with x86 long double-precision numbers */
#define MAXEXPD 0x7fff
#define EXPBIAS 16383
#define EXPD(fp)	(fp.l.upper & 0x7fff)
#define SIGND(fp)	((fp.l.upper) & 0x8000)
#define MANTD(fp)       (fp.l.lower)
#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS

#else

/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
typedef union {
    double d;
#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
    struct {
        uint32_t lower;
        int32_t upper;
    } l;
#else
    struct {
        int32_t upper;
        uint32_t lower;
    } l;
#endif
#ifndef __arm__
    int64_t ll;
#endif
} CPU86_LDoubleU;

/* the following deal with IEEE double-precision numbers */
#define MAXEXPD 0x7ff
#define EXPBIAS 1023
#define EXPD(fp)	(((fp.l.upper) >> 20) & 0x7FF)
#define SIGND(fp)	((fp.l.upper) & 0x80000000)
#ifdef __arm__
#define MANTD(fp)	(fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
#else
#define MANTD(fp)	(fp.ll & ((1LL << 52) - 1))
#endif
#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
#endif

static inline void fpush(void)
{
    env->fpstt = (env->fpstt - 1) & 7;
    env->fptags[env->fpstt] = 0; /* validate stack entry */
}

static inline void fpop(void)
{
    env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
    env->fpstt = (env->fpstt + 1) & 7;
}

#ifndef USE_X86LDOUBLE
static inline CPU86_LDouble helper_fldt(target_ulong ptr)
{
    CPU86_LDoubleU temp;
    int upper, e;
    uint64_t ll;

    /* mantissa */
    upper = lduw(ptr + 8);
    /* XXX: handle overflow ? */
    e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
    e |= (upper >> 4) & 0x800; /* sign */
    ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
#ifdef __arm__
    temp.l.upper = (e << 20) | (ll >> 32);
    temp.l.lower = ll;
#else
    temp.ll = ll | ((uint64_t)e << 52);
#endif
    return temp.d;
}

static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
{
    CPU86_LDoubleU temp;
    int e;

    temp.d = f;
    /* mantissa */
    stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
    /* exponent + sign */
    e = EXPD(temp) - EXPBIAS + 16383;
    e |= SIGND(temp) >> 16;
    stw(ptr + 8, e);
}
#else

/* we use memory access macros */

static inline CPU86_LDouble helper_fldt(target_ulong ptr)
{
    CPU86_LDoubleU temp;

    temp.l.lower = ldq(ptr);
    temp.l.upper = lduw(ptr + 8);
    return temp.d;
}

static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
{
    CPU86_LDoubleU temp;

    temp.d = f;
    stq(ptr, temp.l.lower);
    stw(ptr + 8, temp.l.upper);
}

#endif /* USE_X86LDOUBLE */

#define FPUS_IE (1 << 0)
#define FPUS_DE (1 << 1)
#define FPUS_ZE (1 << 2)
#define FPUS_OE (1 << 3)
#define FPUS_UE (1 << 4)
#define FPUS_PE (1 << 5)
#define FPUS_SF (1 << 6)
#define FPUS_SE (1 << 7)
#define FPUS_B  (1 << 15)

#define FPUC_EM 0x3f

extern const CPU86_LDouble f15rk[7];

void fpu_raise_exception(void);
void restore_native_fp_state(CPUState *env);
void save_native_fp_state(CPUState *env);

extern const uint8_t parity_table[256];
extern const uint8_t rclw_table[32];
extern const uint8_t rclb_table[32];

static inline uint32_t compute_eflags(void)
{
    return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
}

/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
static inline void load_eflags(int eflags, int update_mask)
{
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
    DF = 1 - (2 * ((eflags >> 10) & 1));
    env->eflags = (env->eflags & ~update_mask) |
        (eflags & update_mask) | 0x2;
}

static inline void env_to_regs(void)
{
#ifdef reg_EAX
    EAX = env->regs[R_EAX];
#endif
#ifdef reg_ECX
    ECX = env->regs[R_ECX];
#endif
#ifdef reg_EDX
    EDX = env->regs[R_EDX];
#endif
#ifdef reg_EBX
    EBX = env->regs[R_EBX];
#endif
#ifdef reg_ESP
    ESP = env->regs[R_ESP];
#endif
#ifdef reg_EBP
    EBP = env->regs[R_EBP];
#endif
#ifdef reg_ESI
    ESI = env->regs[R_ESI];
#endif
#ifdef reg_EDI
    EDI = env->regs[R_EDI];
#endif
}

static inline void regs_to_env(void)
{
#ifdef reg_EAX
    env->regs[R_EAX] = EAX;
#endif
#ifdef reg_ECX
    env->regs[R_ECX] = ECX;
#endif
#ifdef reg_EDX
    env->regs[R_EDX] = EDX;
#endif
#ifdef reg_EBX
    env->regs[R_EBX] = EBX;
#endif
#ifdef reg_ESP
    env->regs[R_ESP] = ESP;
#endif
#ifdef reg_EBP
    env->regs[R_EBP] = EBP;
#endif
#ifdef reg_ESI
    env->regs[R_ESI] = ESI;
#endif
#ifdef reg_EDI
    env->regs[R_EDI] = EDI;
#endif
}

static inline int cpu_halted(CPUState *env) {
    /* handle exit of HALTED state */
    if (!env->halted)
        return 0;
    /* disable halt condition */
    if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
         (env->eflags & IF_MASK)) ||
        (env->interrupt_request & CPU_INTERRUPT_NMI)) {
        env->halted = 0;
        return 0;
    }
    return EXCP_HALTED;
}

/* load efer and update the corresponding hflags. XXX: do consistency
   checks with cpuid bits ? */
static inline void cpu_load_efer(CPUState *env, uint64_t val)
{
    env->efer = val;
    env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
    if (env->efer & MSR_EFER_LMA)
        env->hflags |= HF_LMA_MASK;
    if (env->efer & MSR_EFER_SVME)
        env->hflags |= HF_SVME_MASK;
}
Commit	Line	Data
2c0262af	1	/*
5fafdf24	2	* i386 execution defines
2c0262af FB	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
7d3505c5	20	#include "config.h"
2c0262af FB	21	#include "dyngen-exec.h"
2c0262af FB	22
14ce26e7	23	/* XXX: factorize this mess */
14ce26e7 FB	24	#ifdef TARGET_X86_64
	25	#define TARGET_LONG_BITS 64
	26	#else
	27	#define TARGET_LONG_BITS 32
	28	#endif
	29
d785e6be FB	30	#include "cpu-defs.h"
d785e6be FB	31
2c0262af	32	register struct CPUX86State *env asm(AREG0);
14ce26e7	33
2c0262af FB	34	extern FILE *logfile;
	35	extern int loglevel;
	36
2c0262af	37	#define EAX (env->regs[R_EAX])
2c0262af	38	#define ECX (env->regs[R_ECX])
2c0262af	39	#define EDX (env->regs[R_EDX])
2c0262af	40	#define EBX (env->regs[R_EBX])
2c0262af	41	#define ESP (env->regs[R_ESP])
2c0262af	42	#define EBP (env->regs[R_EBP])
2c0262af	43	#define ESI (env->regs[R_ESI])
2c0262af	44	#define EDI (env->regs[R_EDI])
1e4840bf	45	#define EIP (env->eip)
2c0262af FB	46	#define DF (env->df)
	47
	48	#define CC_SRC (env->cc_src)
	49	#define CC_DST (env->cc_dst)
	50	#define CC_OP (env->cc_op)
	51
	52	/* float macros */
	53	#define FT0 (env->ft0)
664e0f19 FB	54	#define ST0 (env->fpregs[env->fpstt].d)
664e0f19 FB	55	#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
2c0262af FB	56	#define ST1 ST(1)
2c0262af FB	57
2c0262af FB	58	#include "cpu.h"
	59	#include "exec-all.h"
	60
1ac157da	61	void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
14ce26e7	62	void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1ac157da	63	void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
5fafdf24	64	int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
6ebbf390 JM	65	int is_write, int mmu_idx, int is_softmmu);
6ebbf390 JM	66	void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
61382a50	67	void *retaddr);
2c0262af FB	68	void __hidden cpu_lock(void);
2c0262af FB	69	void __hidden cpu_unlock(void);
5fafdf24	70	void do_interrupt(int intno, int is_int, int error_code,
14ce26e7	71	target_ulong next_eip, int is_hw);
5fafdf24	72	void do_interrupt_user(int intno, int is_int, int error_code,
14ce26e7	73	target_ulong next_eip);
5fafdf24	74	void raise_interrupt(int intno, int is_int, int error_code,
a8ede8ba	75	int next_eip_addend);
2c0262af FB	76	void raise_exception_err(int exception_index, int error_code);
2c0262af FB	77	void raise_exception(int exception_index);
3b21e03e	78	void do_smm_enter(void);
2c0262af	79	void __hidden cpu_loop_exit(void);
2c0262af FB	80
	81	void OPPROTO op_movl_eflags_T0(void);
	82	void OPPROTO op_movl_T0_eflags(void);
57fec1fe	83
b6abf97d FB	84	/* n must be a constant to be efficient */
	85	static inline target_long lshift(target_long x, int n)
	86	{
	87	if (n >= 0)
	88	return x << n;
	89	else
	90	return x >> (-n);
	91	}
	92
57fec1fe FB	93	#include "helper.h"
57fec1fe FB	94
b8b6a50b FB	95	static inline void svm_check_intercept(uint32_t type)
	96	{
	97	helper_svm_check_intercept_param(type, 0);
	98	}
3e25f951	99
9951bf39 FB	100	#if !defined(CONFIG_USER_ONLY)
9951bf39 FB	101
a9049a07	102	#include "softmmu_exec.h"
9951bf39	103
9951bf39 FB	104	#endif /* !defined(CONFIG_USER_ONLY) */
9951bf39 FB	105
2c0262af FB	106	#ifdef USE_X86LDOUBLE
2c0262af FB	107	/* use long double functions */
7a0e1f41 FB	108	#define floatx_to_int32 floatx80_to_int32
7a0e1f41 FB	109	#define floatx_to_int64 floatx80_to_int64
465e9838 FB	110	#define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
465e9838 FB	111	#define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
19e6c4b8 FB	112	#define int32_to_floatx int32_to_floatx80
	113	#define int64_to_floatx int64_to_floatx80
	114	#define float32_to_floatx float32_to_floatx80
	115	#define float64_to_floatx float64_to_floatx80
	116	#define floatx_to_float32 floatx80_to_float32
	117	#define floatx_to_float64 floatx80_to_float64
7a0e1f41 FB	118	#define floatx_abs floatx80_abs
	119	#define floatx_chs floatx80_chs
	120	#define floatx_round_to_int floatx80_round_to_int
8422b113 FB	121	#define floatx_compare floatx80_compare
8422b113 FB	122	#define floatx_compare_quiet floatx80_compare_quiet
2c0262af FB	123	#define sin sinl
	124	#define cos cosl
	125	#define sqrt sqrtl
	126	#define pow powl
	127	#define log logl
	128	#define tan tanl
	129	#define atan2 atan2l
	130	#define floor floorl
	131	#define ceil ceill
57e4c06e	132	#define ldexp ldexpl
7d3505c5	133	#else
7a0e1f41 FB	134	#define floatx_to_int32 float64_to_int32
7a0e1f41 FB	135	#define floatx_to_int64 float64_to_int64
465e9838 FB	136	#define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
465e9838 FB	137	#define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
19e6c4b8 FB	138	#define int32_to_floatx int32_to_float64
	139	#define int64_to_floatx int64_to_float64
	140	#define float32_to_floatx float32_to_float64
	141	#define float64_to_floatx(x, e) (x)
	142	#define floatx_to_float32 float64_to_float32
	143	#define floatx_to_float64(x, e) (x)
7a0e1f41 FB	144	#define floatx_abs float64_abs
	145	#define floatx_chs float64_chs
	146	#define floatx_round_to_int float64_round_to_int
8422b113 FB	147	#define floatx_compare float64_compare
8422b113 FB	148	#define floatx_compare_quiet float64_compare_quiet
7d3505c5	149	#endif
7a0e1f41	150
2c0262af FB	151	extern CPU86_LDouble sin(CPU86_LDouble x);
	152	extern CPU86_LDouble cos(CPU86_LDouble x);
	153	extern CPU86_LDouble sqrt(CPU86_LDouble x);
	154	extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
	155	extern CPU86_LDouble log(CPU86_LDouble x);
	156	extern CPU86_LDouble tan(CPU86_LDouble x);
	157	extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
	158	extern CPU86_LDouble floor(CPU86_LDouble x);
	159	extern CPU86_LDouble ceil(CPU86_LDouble x);
2c0262af FB	160
	161	#define RC_MASK 0xc00
	162	#define RC_NEAR 0x000
	163	#define RC_DOWN 0x400
	164	#define RC_UP 0x800
	165	#define RC_CHOP 0xc00
	166
	167	#define MAXTAN 9223372036854775808.0
	168
2c0262af FB	169	#ifdef USE_X86LDOUBLE
	170
	171	/* only for x86 */
	172	typedef union {
	173	long double d;
	174	struct {
	175	unsigned long long lower;
	176	unsigned short upper;
	177	} l;
	178	} CPU86_LDoubleU;
	179
	180	/* the following deal with x86 long double-precision numbers */
	181	#define MAXEXPD 0x7fff
	182	#define EXPBIAS 16383
	183	#define EXPD(fp) (fp.l.upper & 0x7fff)
	184	#define SIGND(fp) ((fp.l.upper) & 0x8000)
	185	#define MANTD(fp) (fp.l.lower)
	186	#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) \| EXPBIAS
	187
	188	#else
	189
	190	/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
	191	typedef union {
	192	double d;
	193	#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
	194	struct {
	195	uint32_t lower;
	196	int32_t upper;
	197	} l;
	198	#else
	199	struct {
	200	int32_t upper;
	201	uint32_t lower;
	202	} l;
	203	#endif
	204	#ifndef __arm__
	205	int64_t ll;
	206	#endif
	207	} CPU86_LDoubleU;
	208
	209	/* the following deal with IEEE double-precision numbers */
	210	#define MAXEXPD 0x7ff
	211	#define EXPBIAS 1023
	212	#define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF)
	213	#define SIGND(fp) ((fp.l.upper) & 0x80000000)
	214	#ifdef __arm__
	215	#define MANTD(fp) (fp.l.lower \| ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
	216	#else
	217	#define MANTD(fp) (fp.ll & ((1LL << 52) - 1))
	218	#endif
	219	#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) \| (EXPBIAS << 20)
	220	#endif
	221
	222	static inline void fpush(void)
	223	{
	224	env->fpstt = (env->fpstt - 1) & 7;
	225	env->fptags[env->fpstt] = 0; /* validate stack entry */
	226	}
	227
	228	static inline void fpop(void)
	229	{
	230	env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
	231	env->fpstt = (env->fpstt + 1) & 7;
	232	}
233
234	#ifndef USE_X86LDOUBLE
14ce26e7	235	static inline CPU86_LDouble helper_fldt(target_ulong ptr)
2c0262af FB	236	{
	237	CPU86_LDoubleU temp;
	238	int upper, e;
	239	uint64_t ll;
	240
	241	/* mantissa */
	242	upper = lduw(ptr + 8);
	243	/* XXX: handle overflow ? */
	244	e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
	245	e \|= (upper >> 4) & 0x800; /* sign */
	246	ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
	247	#ifdef __arm__
	248	temp.l.upper = (e << 20) \| (ll >> 32);
	249	temp.l.lower = ll;
	250	#else
	251	temp.ll = ll \| ((uint64_t)e << 52);
	252	#endif
	253	return temp.d;
	254	}
	255
664e0f19	256	static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
2c0262af FB	257	{
	258	CPU86_LDoubleU temp;
	259	int e;
	260
	261	temp.d = f;
	262	/* mantissa */
	263	stq(ptr, (MANTD(temp) << 11) \| (1LL << 63));
	264	/* exponent + sign */
	265	e = EXPD(temp) - EXPBIAS + 16383;
	266	e \|= SIGND(temp) >> 16;
	267	stw(ptr + 8, e);
	268	}
9951bf39 FB	269	#else
9951bf39 FB	270
9951bf39 FB	271	/* we use memory access macros */
9951bf39 FB	272
14ce26e7	273	static inline CPU86_LDouble helper_fldt(target_ulong ptr)
9951bf39 FB	274	{
	275	CPU86_LDoubleU temp;
	276
	277	temp.l.lower = ldq(ptr);
	278	temp.l.upper = lduw(ptr + 8);
	279	return temp.d;
	280	}
	281
14ce26e7	282	static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
9951bf39 FB	283	{
9951bf39 FB	284	CPU86_LDoubleU temp;
3b46e624	285
9951bf39 FB	286	temp.d = f;
	287	stq(ptr, temp.l.lower);
	288	stw(ptr + 8, temp.l.upper);
	289	}
	290
9951bf39	291	#endif /* USE_X86LDOUBLE */
2c0262af	292
2ee73ac3 FB	293	#define FPUS_IE (1 << 0)
	294	#define FPUS_DE (1 << 1)
	295	#define FPUS_ZE (1 << 2)
	296	#define FPUS_OE (1 << 3)
	297	#define FPUS_UE (1 << 4)
	298	#define FPUS_PE (1 << 5)
	299	#define FPUS_SF (1 << 6)
	300	#define FPUS_SE (1 << 7)
	301	#define FPUS_B (1 << 15)
	302
	303	#define FPUC_EM 0x3f
	304
83fb7adf	305	extern const CPU86_LDouble f15rk[7];
2c0262af	306
2ee73ac3	307	void fpu_raise_exception(void);
03857e31 FB	308	void restore_native_fp_state(CPUState *env);
03857e31 FB	309	void save_native_fp_state(CPUState *env);
2c0262af	310
83fb7adf FB	311	extern const uint8_t parity_table[256];
	312	extern const uint8_t rclw_table[32];
	313	extern const uint8_t rclb_table[32];
2c0262af FB	314
	315	static inline uint32_t compute_eflags(void)
	316	{
	317	return env->eflags \| cc_table[CC_OP].compute_all() \| (DF & DF_MASK);
	318	}
	319
2c0262af FB	320	/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
	321	static inline void load_eflags(int eflags, int update_mask)
	322	{
	323	CC_SRC = eflags & (CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C);
	324	DF = 1 - (2 * ((eflags >> 10) & 1));
5fafdf24	325	env->eflags = (env->eflags & ~update_mask) \|
093f8f06	326	(eflags & update_mask) \| 0x2;
2c0262af FB	327	}
2c0262af FB	328
0d1a29f9 FB	329	static inline void env_to_regs(void)
	330	{
	331	#ifdef reg_EAX
	332	EAX = env->regs[R_EAX];
	333	#endif
	334	#ifdef reg_ECX
	335	ECX = env->regs[R_ECX];
	336	#endif
	337	#ifdef reg_EDX
	338	EDX = env->regs[R_EDX];
	339	#endif
	340	#ifdef reg_EBX
	341	EBX = env->regs[R_EBX];
	342	#endif
	343	#ifdef reg_ESP
	344	ESP = env->regs[R_ESP];
	345	#endif
	346	#ifdef reg_EBP
	347	EBP = env->regs[R_EBP];
	348	#endif
	349	#ifdef reg_ESI
	350	ESI = env->regs[R_ESI];
	351	#endif
	352	#ifdef reg_EDI
	353	EDI = env->regs[R_EDI];
	354	#endif
	355	}
	356
	357	static inline void regs_to_env(void)
	358	{
	359	#ifdef reg_EAX
	360	env->regs[R_EAX] = EAX;
	361	#endif
	362	#ifdef reg_ECX
	363	env->regs[R_ECX] = ECX;
	364	#endif
	365	#ifdef reg_EDX
	366	env->regs[R_EDX] = EDX;
	367	#endif
	368	#ifdef reg_EBX
	369	env->regs[R_EBX] = EBX;
	370	#endif
	371	#ifdef reg_ESP
	372	env->regs[R_ESP] = ESP;
	373	#endif
	374	#ifdef reg_EBP
	375	env->regs[R_EBP] = EBP;
	376	#endif
	377	#ifdef reg_ESI
	378	env->regs[R_ESI] = ESI;
	379	#endif
	380	#ifdef reg_EDI
	381	env->regs[R_EDI] = EDI;
	382	#endif
	383	}
bfed01fc TS	384
	385	static inline int cpu_halted(CPUState *env) {
	386	/* handle exit of HALTED state */
ce5232c5	387	if (!env->halted)
bfed01fc TS	388	return 0;
bfed01fc TS	389	/* disable halt condition */
474ea849 AJ	390	if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
	391	(env->eflags & IF_MASK)) \|\|
	392	(env->interrupt_request & CPU_INTERRUPT_NMI)) {
ce5232c5	393	env->halted = 0;
bfed01fc TS	394	return 0;
	395	}
	396	return EXCP_HALTED;
	397	}
0573fbfc	398
5efc27bb FB	399	/* load efer and update the corresponding hflags. XXX: do consistency
	400	checks with cpuid bits ? */
	401	static inline void cpu_load_efer(CPUState *env, uint64_t val)
	402	{
	403	env->efer = val;
	404	env->hflags &= ~(HF_LMA_MASK \| HF_SVME_MASK);
	405	if (env->efer & MSR_EFER_LMA)
	406	env->hflags \|= HF_LMA_MASK;
	407	if (env->efer & MSR_EFER_SVME)
	408	env->hflags \|= HF_SVME_MASK;
	409	}