]>
Commit | Line | Data |
---|---|---|
05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
21 | ||
22 | #include "qemu-common.h" | |
23 | #include "sysemu.h" | |
24 | #include "kvm.h" | |
25 | #include "cpu.h" | |
e22a25c9 | 26 | #include "gdbstub.h" |
0e607a80 | 27 | #include "host-utils.h" |
4c5b10b7 | 28 | #include "hw/pc.h" |
408392b3 | 29 | #include "hw/apic.h" |
35bed8ee | 30 | #include "ioport.h" |
e7701825 | 31 | #include "kvm_x86.h" |
05330448 | 32 | |
bb0300dc GN |
33 | #ifdef CONFIG_KVM_PARA |
34 | #include <linux/kvm_para.h> | |
35 | #endif | |
36 | // | |
05330448 AL |
37 | //#define DEBUG_KVM |
38 | ||
39 | #ifdef DEBUG_KVM | |
8c0d577e | 40 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
41 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
42 | #else | |
8c0d577e | 43 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
44 | do { } while (0) |
45 | #endif | |
46 | ||
1a03675d GC |
47 | #define MSR_KVM_WALL_CLOCK 0x11 |
48 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
49 | ||
c0532a76 MT |
50 | #ifndef BUS_MCEERR_AR |
51 | #define BUS_MCEERR_AR 4 | |
52 | #endif | |
53 | #ifndef BUS_MCEERR_AO | |
54 | #define BUS_MCEERR_AO 5 | |
55 | #endif | |
56 | ||
94a8d39a JK |
57 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
58 | KVM_CAP_INFO(SET_TSS_ADDR), | |
59 | KVM_CAP_INFO(EXT_CPUID), | |
60 | KVM_CAP_INFO(MP_STATE), | |
61 | KVM_CAP_LAST_INFO | |
62 | }; | |
25d2e361 | 63 | |
c3a3a7d3 JK |
64 | static bool has_msr_star; |
65 | static bool has_msr_hsave_pa; | |
c5999bfc JK |
66 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
67 | static bool has_msr_async_pf_en; | |
68 | #endif | |
25d2e361 | 69 | static int lm_capable_kernel; |
b827df58 AK |
70 | |
71 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
72 | { | |
73 | struct kvm_cpuid2 *cpuid; | |
74 | int r, size; | |
75 | ||
76 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
77 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
78 | cpuid->nent = max; | |
79 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
80 | if (r == 0 && cpuid->nent >= max) { |
81 | r = -E2BIG; | |
82 | } | |
b827df58 AK |
83 | if (r < 0) { |
84 | if (r == -E2BIG) { | |
85 | qemu_free(cpuid); | |
86 | return NULL; | |
87 | } else { | |
88 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
89 | strerror(-r)); | |
90 | exit(1); | |
91 | } | |
92 | } | |
93 | return cpuid; | |
94 | } | |
95 | ||
c958a8bd SY |
96 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
97 | uint32_t index, int reg) | |
b827df58 AK |
98 | { |
99 | struct kvm_cpuid2 *cpuid; | |
100 | int i, max; | |
101 | uint32_t ret = 0; | |
102 | uint32_t cpuid_1_edx; | |
103 | ||
b827df58 AK |
104 | max = 1; |
105 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
106 | max *= 2; | |
107 | } | |
108 | ||
109 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
110 | if (cpuid->entries[i].function == function && |
111 | cpuid->entries[i].index == index) { | |
b827df58 AK |
112 | switch (reg) { |
113 | case R_EAX: | |
114 | ret = cpuid->entries[i].eax; | |
115 | break; | |
116 | case R_EBX: | |
117 | ret = cpuid->entries[i].ebx; | |
118 | break; | |
119 | case R_ECX: | |
120 | ret = cpuid->entries[i].ecx; | |
121 | break; | |
122 | case R_EDX: | |
123 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
124 | switch (function) { |
125 | case 1: | |
126 | /* KVM before 2.6.30 misreports the following features */ | |
127 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
128 | break; | |
129 | case 0x80000001: | |
b827df58 AK |
130 | /* On Intel, kvm returns cpuid according to the Intel spec, |
131 | * so add missing bits according to the AMD spec: | |
132 | */ | |
c958a8bd | 133 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 134 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 135 | break; |
b827df58 AK |
136 | } |
137 | break; | |
138 | } | |
139 | } | |
140 | } | |
141 | ||
142 | qemu_free(cpuid); | |
143 | ||
144 | return ret; | |
145 | } | |
146 | ||
bb0300dc GN |
147 | #ifdef CONFIG_KVM_PARA |
148 | struct kvm_para_features { | |
b9bec74b JK |
149 | int cap; |
150 | int feature; | |
bb0300dc | 151 | } para_features[] = { |
b9bec74b | 152 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, |
b9bec74b | 153 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, |
b9bec74b | 154 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, |
f6584ee2 | 155 | #ifdef KVM_CAP_ASYNC_PF |
b9bec74b | 156 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
bb0300dc | 157 | #endif |
b9bec74b | 158 | { -1, -1 } |
bb0300dc GN |
159 | }; |
160 | ||
161 | static int get_para_features(CPUState *env) | |
162 | { | |
b9bec74b | 163 | int i, features = 0; |
bb0300dc | 164 | |
b9bec74b JK |
165 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { |
166 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) { | |
167 | features |= (1 << para_features[i].feature); | |
bb0300dc | 168 | } |
b9bec74b | 169 | } |
b3a98367 | 170 | #ifdef KVM_CAP_ASYNC_PF |
c5999bfc | 171 | has_msr_async_pf_en = features & (1 << KVM_FEATURE_ASYNC_PF); |
b3a98367 | 172 | #endif |
b9bec74b | 173 | return features; |
bb0300dc GN |
174 | } |
175 | #endif | |
176 | ||
e7701825 MT |
177 | #ifdef KVM_CAP_MCE |
178 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, | |
179 | int *max_banks) | |
180 | { | |
181 | int r; | |
182 | ||
14a09518 | 183 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
184 | if (r > 0) { |
185 | *max_banks = r; | |
186 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
187 | } | |
188 | return -ENOSYS; | |
189 | } | |
190 | ||
191 | static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap) | |
192 | { | |
193 | return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap); | |
194 | } | |
195 | ||
196 | static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m) | |
197 | { | |
198 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m); | |
199 | } | |
200 | ||
c0532a76 MT |
201 | static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n) |
202 | { | |
203 | struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs); | |
204 | int r; | |
205 | ||
206 | kmsrs->nmsrs = n; | |
207 | memcpy(kmsrs->entries, msrs, n * sizeof *msrs); | |
208 | r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs); | |
209 | memcpy(msrs, kmsrs->entries, n * sizeof *msrs); | |
210 | free(kmsrs); | |
211 | return r; | |
212 | } | |
213 | ||
214 | /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */ | |
6643e2f0 | 215 | static int kvm_mce_in_progress(CPUState *env) |
c0532a76 MT |
216 | { |
217 | struct kvm_msr_entry msr_mcg_status = { | |
218 | .index = MSR_MCG_STATUS, | |
219 | }; | |
220 | int r; | |
221 | ||
222 | r = kvm_get_msr(env, &msr_mcg_status, 1); | |
223 | if (r == -1 || r == 0) { | |
6643e2f0 JD |
224 | fprintf(stderr, "Failed to get MCE status\n"); |
225 | return 0; | |
c0532a76 MT |
226 | } |
227 | return !!(msr_mcg_status.data & MCG_STATUS_MCIP); | |
228 | } | |
229 | ||
e7701825 MT |
230 | struct kvm_x86_mce_data |
231 | { | |
232 | CPUState *env; | |
233 | struct kvm_x86_mce *mce; | |
c0532a76 | 234 | int abort_on_error; |
e7701825 MT |
235 | }; |
236 | ||
237 | static void kvm_do_inject_x86_mce(void *_data) | |
238 | { | |
239 | struct kvm_x86_mce_data *data = _data; | |
240 | int r; | |
241 | ||
f8502cfb HS |
242 | /* If there is an MCE exception being processed, ignore this SRAO MCE */ |
243 | if ((data->env->mcg_cap & MCG_SER_P) && | |
244 | !(data->mce->status & MCI_STATUS_AR)) { | |
6643e2f0 | 245 | if (kvm_mce_in_progress(data->env)) { |
f8502cfb HS |
246 | return; |
247 | } | |
248 | } | |
c0532a76 | 249 | |
e7701825 | 250 | r = kvm_set_mce(data->env, data->mce); |
c0532a76 | 251 | if (r < 0) { |
e7701825 | 252 | perror("kvm_set_mce FAILED"); |
c0532a76 MT |
253 | if (data->abort_on_error) { |
254 | abort(); | |
255 | } | |
256 | } | |
e7701825 | 257 | } |
31ce5e0c | 258 | |
7cc2cc3e JD |
259 | static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce, |
260 | int flag) | |
261 | { | |
262 | struct kvm_x86_mce_data data = { | |
263 | .env = env, | |
264 | .mce = mce, | |
265 | .abort_on_error = (flag & ABORT_ON_ERROR), | |
266 | }; | |
267 | ||
268 | if (!env->mcg_cap) { | |
269 | fprintf(stderr, "MCE support is not enabled!\n"); | |
270 | return; | |
271 | } | |
272 | ||
273 | run_on_cpu(env, kvm_do_inject_x86_mce, &data); | |
274 | } | |
275 | ||
31ce5e0c | 276 | static void kvm_mce_broadcast_rest(CPUState *env); |
e7701825 MT |
277 | #endif |
278 | ||
279 | void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, | |
c0532a76 | 280 | uint64_t mcg_status, uint64_t addr, uint64_t misc, |
31ce5e0c | 281 | int flag) |
e7701825 MT |
282 | { |
283 | #ifdef KVM_CAP_MCE | |
284 | struct kvm_x86_mce mce = { | |
285 | .bank = bank, | |
286 | .status = status, | |
287 | .mcg_status = mcg_status, | |
288 | .addr = addr, | |
289 | .misc = misc, | |
290 | }; | |
e7701825 | 291 | |
31ce5e0c JD |
292 | if (flag & MCE_BROADCAST) { |
293 | kvm_mce_broadcast_rest(cenv); | |
c0532a76 MT |
294 | } |
295 | ||
7cc2cc3e | 296 | kvm_inject_x86_mce_on(cenv, &mce, flag); |
c0532a76 | 297 | #else |
31ce5e0c | 298 | if (flag & ABORT_ON_ERROR) { |
c0532a76 | 299 | abort(); |
31ce5e0c | 300 | } |
e7701825 MT |
301 | #endif |
302 | } | |
303 | ||
b8cc45d6 GC |
304 | static void cpu_update_state(void *opaque, int running, int reason) |
305 | { | |
306 | CPUState *env = opaque; | |
307 | ||
308 | if (running) { | |
309 | env->tsc_valid = false; | |
310 | } | |
311 | } | |
312 | ||
05330448 AL |
313 | int kvm_arch_init_vcpu(CPUState *env) |
314 | { | |
315 | struct { | |
486bd5a2 AL |
316 | struct kvm_cpuid2 cpuid; |
317 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 318 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 319 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 320 | uint32_t unused; |
bb0300dc | 321 | struct kvm_cpuid_entry2 *c; |
521f0798 | 322 | #ifdef CONFIG_KVM_PARA |
bb0300dc GN |
323 | uint32_t signature[3]; |
324 | #endif | |
05330448 | 325 | |
c958a8bd | 326 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
327 | |
328 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 329 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
330 | env->cpuid_ext_features |= i; |
331 | ||
457dfed6 | 332 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 333 | 0, R_EDX); |
457dfed6 | 334 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 335 | 0, R_ECX); |
296acb64 JR |
336 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A, |
337 | 0, R_EDX); | |
338 | ||
6c1f42fe | 339 | |
05330448 AL |
340 | cpuid_i = 0; |
341 | ||
bb0300dc GN |
342 | #ifdef CONFIG_KVM_PARA |
343 | /* Paravirtualization CPUIDs */ | |
344 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
345 | c = &cpuid_data.entries[cpuid_i++]; | |
346 | memset(c, 0, sizeof(*c)); | |
347 | c->function = KVM_CPUID_SIGNATURE; | |
348 | c->eax = 0; | |
349 | c->ebx = signature[0]; | |
350 | c->ecx = signature[1]; | |
351 | c->edx = signature[2]; | |
352 | ||
353 | c = &cpuid_data.entries[cpuid_i++]; | |
354 | memset(c, 0, sizeof(*c)); | |
355 | c->function = KVM_CPUID_FEATURES; | |
356 | c->eax = env->cpuid_kvm_features & get_para_features(env); | |
357 | #endif | |
358 | ||
a33609ca | 359 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
360 | |
361 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 362 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
363 | |
364 | switch (i) { | |
a36b1029 AL |
365 | case 2: { |
366 | /* Keep reading function 2 till all the input is received */ | |
367 | int times; | |
368 | ||
a36b1029 | 369 | c->function = i; |
a33609ca AL |
370 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
371 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
372 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
373 | times = c->eax & 0xff; | |
a36b1029 AL |
374 | |
375 | for (j = 1; j < times; ++j) { | |
a33609ca | 376 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 377 | c->function = i; |
a33609ca AL |
378 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
379 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
380 | } |
381 | break; | |
382 | } | |
486bd5a2 AL |
383 | case 4: |
384 | case 0xb: | |
385 | case 0xd: | |
386 | for (j = 0; ; j++) { | |
486bd5a2 AL |
387 | c->function = i; |
388 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
389 | c->index = j; | |
a33609ca | 390 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 391 | |
b9bec74b | 392 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 393 | break; |
b9bec74b JK |
394 | } |
395 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 396 | break; |
b9bec74b JK |
397 | } |
398 | if (i == 0xd && c->eax == 0) { | |
486bd5a2 | 399 | break; |
b9bec74b | 400 | } |
a33609ca | 401 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
402 | } |
403 | break; | |
404 | default: | |
486bd5a2 | 405 | c->function = i; |
a33609ca AL |
406 | c->flags = 0; |
407 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
408 | break; |
409 | } | |
05330448 | 410 | } |
a33609ca | 411 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
412 | |
413 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 414 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 415 | |
05330448 | 416 | c->function = i; |
a33609ca AL |
417 | c->flags = 0; |
418 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
419 | } |
420 | ||
421 | cpuid_data.cpuid.nent = cpuid_i; | |
422 | ||
e7701825 MT |
423 | #ifdef KVM_CAP_MCE |
424 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
425 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
426 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
427 | uint64_t mcg_cap; | |
428 | int banks; | |
429 | ||
b9bec74b | 430 | if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) { |
e7701825 | 431 | perror("kvm_get_mce_cap_supported FAILED"); |
b9bec74b | 432 | } else { |
e7701825 MT |
433 | if (banks > MCE_BANKS_DEF) |
434 | banks = MCE_BANKS_DEF; | |
435 | mcg_cap &= MCE_CAP_DEF; | |
436 | mcg_cap |= banks; | |
b9bec74b | 437 | if (kvm_setup_mce(env, &mcg_cap)) { |
e7701825 | 438 | perror("kvm_setup_mce FAILED"); |
b9bec74b | 439 | } else { |
e7701825 | 440 | env->mcg_cap = mcg_cap; |
b9bec74b | 441 | } |
e7701825 MT |
442 | } |
443 | } | |
444 | #endif | |
445 | ||
b8cc45d6 GC |
446 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
447 | ||
486bd5a2 | 448 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
449 | } |
450 | ||
caa5af0f JK |
451 | void kvm_arch_reset_vcpu(CPUState *env) |
452 | { | |
e73223a5 | 453 | env->exception_injected = -1; |
0e607a80 | 454 | env->interrupt_injected = -1; |
1a5e9d2f | 455 | env->xcr0 = 1; |
ddced198 MT |
456 | if (kvm_irqchip_in_kernel()) { |
457 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
458 | KVM_MP_STATE_UNINITIALIZED; | |
459 | } else { | |
460 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
461 | } | |
caa5af0f JK |
462 | } |
463 | ||
c3a3a7d3 | 464 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 465 | { |
75b10c43 | 466 | static int kvm_supported_msrs; |
c3a3a7d3 | 467 | int ret = 0; |
05330448 AL |
468 | |
469 | /* first time */ | |
75b10c43 | 470 | if (kvm_supported_msrs == 0) { |
05330448 AL |
471 | struct kvm_msr_list msr_list, *kvm_msr_list; |
472 | ||
75b10c43 | 473 | kvm_supported_msrs = -1; |
05330448 AL |
474 | |
475 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
476 | * save/restore */ | |
4c9f7372 | 477 | msr_list.nmsrs = 0; |
c3a3a7d3 | 478 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 479 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 480 | return ret; |
6fb6d245 | 481 | } |
d9db889f JK |
482 | /* Old kernel modules had a bug and could write beyond the provided |
483 | memory. Allocate at least a safe amount of 1K. */ | |
484 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
485 | msr_list.nmsrs * | |
486 | sizeof(msr_list.indices[0]))); | |
05330448 | 487 | |
55308450 | 488 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 489 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
490 | if (ret >= 0) { |
491 | int i; | |
492 | ||
493 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
494 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 495 | has_msr_star = true; |
75b10c43 MT |
496 | continue; |
497 | } | |
498 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 499 | has_msr_hsave_pa = true; |
75b10c43 | 500 | continue; |
05330448 AL |
501 | } |
502 | } | |
503 | } | |
504 | ||
505 | free(kvm_msr_list); | |
506 | } | |
507 | ||
c3a3a7d3 | 508 | return ret; |
05330448 AL |
509 | } |
510 | ||
cad1e282 | 511 | int kvm_arch_init(KVMState *s) |
20420430 | 512 | { |
11076198 | 513 | uint64_t identity_base = 0xfffbc000; |
20420430 | 514 | int ret; |
25d2e361 | 515 | struct utsname utsname; |
20420430 | 516 | |
c3a3a7d3 | 517 | ret = kvm_get_supported_msrs(s); |
20420430 | 518 | if (ret < 0) { |
20420430 SY |
519 | return ret; |
520 | } | |
25d2e361 MT |
521 | |
522 | uname(&utsname); | |
523 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
524 | ||
4c5b10b7 | 525 | /* |
11076198 JK |
526 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
527 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
528 | * Since these must be part of guest physical memory, we need to allocate | |
529 | * them, both by setting their start addresses in the kernel and by | |
530 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
531 | * | |
532 | * Older KVM versions may not support setting the identity map base. In | |
533 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
534 | * size. | |
4c5b10b7 | 535 | */ |
11076198 JK |
536 | #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR |
537 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
538 | /* Allows up to 16M BIOSes. */ | |
539 | identity_base = 0xfeffc000; | |
540 | ||
541 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
542 | if (ret < 0) { | |
543 | return ret; | |
544 | } | |
4c5b10b7 | 545 | } |
11076198 JK |
546 | #endif |
547 | /* Set TSS base one page after EPT identity map. */ | |
548 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
549 | if (ret < 0) { |
550 | return ret; | |
551 | } | |
552 | ||
11076198 JK |
553 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
554 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 555 | if (ret < 0) { |
11076198 | 556 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
557 | return ret; |
558 | } | |
559 | ||
11076198 | 560 | return 0; |
05330448 | 561 | } |
b9bec74b | 562 | |
05330448 AL |
563 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
564 | { | |
565 | lhs->selector = rhs->selector; | |
566 | lhs->base = rhs->base; | |
567 | lhs->limit = rhs->limit; | |
568 | lhs->type = 3; | |
569 | lhs->present = 1; | |
570 | lhs->dpl = 3; | |
571 | lhs->db = 0; | |
572 | lhs->s = 1; | |
573 | lhs->l = 0; | |
574 | lhs->g = 0; | |
575 | lhs->avl = 0; | |
576 | lhs->unusable = 0; | |
577 | } | |
578 | ||
579 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
580 | { | |
581 | unsigned flags = rhs->flags; | |
582 | lhs->selector = rhs->selector; | |
583 | lhs->base = rhs->base; | |
584 | lhs->limit = rhs->limit; | |
585 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
586 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 587 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
588 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
589 | lhs->s = (flags & DESC_S_MASK) != 0; | |
590 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
591 | lhs->g = (flags & DESC_G_MASK) != 0; | |
592 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
593 | lhs->unusable = 0; | |
594 | } | |
595 | ||
596 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
597 | { | |
598 | lhs->selector = rhs->selector; | |
599 | lhs->base = rhs->base; | |
600 | lhs->limit = rhs->limit; | |
b9bec74b JK |
601 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
602 | (rhs->present * DESC_P_MASK) | | |
603 | (rhs->dpl << DESC_DPL_SHIFT) | | |
604 | (rhs->db << DESC_B_SHIFT) | | |
605 | (rhs->s * DESC_S_MASK) | | |
606 | (rhs->l << DESC_L_SHIFT) | | |
607 | (rhs->g * DESC_G_MASK) | | |
608 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
609 | } |
610 | ||
611 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
612 | { | |
b9bec74b | 613 | if (set) { |
05330448 | 614 | *kvm_reg = *qemu_reg; |
b9bec74b | 615 | } else { |
05330448 | 616 | *qemu_reg = *kvm_reg; |
b9bec74b | 617 | } |
05330448 AL |
618 | } |
619 | ||
620 | static int kvm_getput_regs(CPUState *env, int set) | |
621 | { | |
622 | struct kvm_regs regs; | |
623 | int ret = 0; | |
624 | ||
625 | if (!set) { | |
626 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
b9bec74b | 627 | if (ret < 0) { |
05330448 | 628 | return ret; |
b9bec74b | 629 | } |
05330448 AL |
630 | } |
631 | ||
632 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
633 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
634 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
635 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
636 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
637 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
638 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
639 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
640 | #ifdef TARGET_X86_64 | |
641 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
642 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
643 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
644 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
645 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
646 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
647 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
648 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
649 | #endif | |
650 | ||
651 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
652 | kvm_getput_reg(®s.rip, &env->eip, set); | |
653 | ||
b9bec74b | 654 | if (set) { |
05330448 | 655 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
b9bec74b | 656 | } |
05330448 AL |
657 | |
658 | return ret; | |
659 | } | |
660 | ||
661 | static int kvm_put_fpu(CPUState *env) | |
662 | { | |
663 | struct kvm_fpu fpu; | |
664 | int i; | |
665 | ||
666 | memset(&fpu, 0, sizeof fpu); | |
667 | fpu.fsw = env->fpus & ~(7 << 11); | |
668 | fpu.fsw |= (env->fpstt & 7) << 11; | |
669 | fpu.fcw = env->fpuc; | |
b9bec74b JK |
670 | for (i = 0; i < 8; ++i) { |
671 | fpu.ftwx |= (!env->fptags[i]) << i; | |
672 | } | |
05330448 AL |
673 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
674 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
675 | fpu.mxcsr = env->mxcsr; | |
676 | ||
677 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
678 | } | |
679 | ||
f1665b21 SY |
680 | #ifdef KVM_CAP_XSAVE |
681 | #define XSAVE_CWD_RIP 2 | |
682 | #define XSAVE_CWD_RDP 4 | |
683 | #define XSAVE_MXCSR 6 | |
684 | #define XSAVE_ST_SPACE 8 | |
685 | #define XSAVE_XMM_SPACE 40 | |
686 | #define XSAVE_XSTATE_BV 128 | |
687 | #define XSAVE_YMMH_SPACE 144 | |
688 | #endif | |
689 | ||
690 | static int kvm_put_xsave(CPUState *env) | |
691 | { | |
692 | #ifdef KVM_CAP_XSAVE | |
0f53994f | 693 | int i, r; |
f1665b21 SY |
694 | struct kvm_xsave* xsave; |
695 | uint16_t cwd, swd, twd, fop; | |
696 | ||
b9bec74b | 697 | if (!kvm_has_xsave()) { |
f1665b21 | 698 | return kvm_put_fpu(env); |
b9bec74b | 699 | } |
f1665b21 SY |
700 | |
701 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
702 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
703 | cwd = swd = twd = fop = 0; | |
704 | swd = env->fpus & ~(7 << 11); | |
705 | swd |= (env->fpstt & 7) << 11; | |
706 | cwd = env->fpuc; | |
b9bec74b | 707 | for (i = 0; i < 8; ++i) { |
f1665b21 | 708 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 709 | } |
f1665b21 SY |
710 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; |
711 | xsave->region[1] = (uint32_t)(fop << 16) + twd; | |
712 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
713 | sizeof env->fpregs); | |
714 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
715 | sizeof env->xmm_regs); | |
716 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
717 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
718 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
719 | sizeof env->ymmh_regs); | |
0f53994f MT |
720 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
721 | qemu_free(xsave); | |
722 | return r; | |
f1665b21 SY |
723 | #else |
724 | return kvm_put_fpu(env); | |
725 | #endif | |
726 | } | |
727 | ||
728 | static int kvm_put_xcrs(CPUState *env) | |
729 | { | |
730 | #ifdef KVM_CAP_XCRS | |
731 | struct kvm_xcrs xcrs; | |
732 | ||
b9bec74b | 733 | if (!kvm_has_xcrs()) { |
f1665b21 | 734 | return 0; |
b9bec74b | 735 | } |
f1665b21 SY |
736 | |
737 | xcrs.nr_xcrs = 1; | |
738 | xcrs.flags = 0; | |
739 | xcrs.xcrs[0].xcr = 0; | |
740 | xcrs.xcrs[0].value = env->xcr0; | |
741 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
742 | #else | |
743 | return 0; | |
744 | #endif | |
745 | } | |
746 | ||
05330448 AL |
747 | static int kvm_put_sregs(CPUState *env) |
748 | { | |
749 | struct kvm_sregs sregs; | |
750 | ||
0e607a80 JK |
751 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
752 | if (env->interrupt_injected >= 0) { | |
753 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
754 | (uint64_t)1 << (env->interrupt_injected % 64); | |
755 | } | |
05330448 AL |
756 | |
757 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
758 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
759 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
760 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
761 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
762 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
763 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 764 | } else { |
b9bec74b JK |
765 | set_seg(&sregs.cs, &env->segs[R_CS]); |
766 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
767 | set_seg(&sregs.es, &env->segs[R_ES]); | |
768 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
769 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
770 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
771 | } |
772 | ||
773 | set_seg(&sregs.tr, &env->tr); | |
774 | set_seg(&sregs.ldt, &env->ldt); | |
775 | ||
776 | sregs.idt.limit = env->idt.limit; | |
777 | sregs.idt.base = env->idt.base; | |
778 | sregs.gdt.limit = env->gdt.limit; | |
779 | sregs.gdt.base = env->gdt.base; | |
780 | ||
781 | sregs.cr0 = env->cr[0]; | |
782 | sregs.cr2 = env->cr[2]; | |
783 | sregs.cr3 = env->cr[3]; | |
784 | sregs.cr4 = env->cr[4]; | |
785 | ||
4a942cea BS |
786 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
787 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
788 | |
789 | sregs.efer = env->efer; | |
790 | ||
791 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
792 | } | |
793 | ||
794 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
795 | uint32_t index, uint64_t value) | |
796 | { | |
797 | entry->index = index; | |
798 | entry->data = value; | |
799 | } | |
800 | ||
ea643051 | 801 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
802 | { |
803 | struct { | |
804 | struct kvm_msrs info; | |
805 | struct kvm_msr_entry entries[100]; | |
806 | } msr_data; | |
807 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 808 | int n = 0; |
05330448 AL |
809 | |
810 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
811 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
812 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
c3a3a7d3 | 813 | if (has_msr_star) { |
b9bec74b JK |
814 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
815 | } | |
c3a3a7d3 | 816 | if (has_msr_hsave_pa) { |
75b10c43 | 817 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 818 | } |
05330448 | 819 | #ifdef TARGET_X86_64 |
25d2e361 MT |
820 | if (lm_capable_kernel) { |
821 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
822 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
823 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
824 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
825 | } | |
05330448 | 826 | #endif |
ea643051 | 827 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
828 | /* |
829 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
830 | * writeback. Until this is fixed, we only write the offset to SMP | |
831 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
832 | * huge jump-backs that would occur without any writeback at all. | |
833 | */ | |
834 | if (smp_cpus == 1 || env->tsc != 0) { | |
835 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
836 | } | |
ff5c186b JK |
837 | } |
838 | /* | |
839 | * The following paravirtual MSRs have side effects on the guest or are | |
840 | * too heavy for normal writeback. Limit them to reset or full state | |
841 | * updates. | |
842 | */ | |
843 | if (level >= KVM_PUT_RESET_STATE) { | |
ea643051 JK |
844 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
845 | env->system_time_msr); | |
846 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
521f0798 | 847 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
c5999bfc JK |
848 | if (has_msr_async_pf_en) { |
849 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
850 | env->async_pf_en_msr); | |
851 | } | |
f6584ee2 | 852 | #endif |
ea643051 | 853 | } |
57780495 MT |
854 | #ifdef KVM_CAP_MCE |
855 | if (env->mcg_cap) { | |
d8da8574 | 856 | int i; |
b9bec74b JK |
857 | |
858 | if (level == KVM_PUT_RESET_STATE) { | |
57780495 | 859 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
b9bec74b | 860 | } else if (level == KVM_PUT_FULL_STATE) { |
57780495 MT |
861 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
862 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
b9bec74b | 863 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 864 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); |
b9bec74b | 865 | } |
57780495 MT |
866 | } |
867 | } | |
868 | #endif | |
1a03675d | 869 | |
05330448 AL |
870 | msr_data.info.nmsrs = n; |
871 | ||
872 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
873 | ||
874 | } | |
875 | ||
876 | ||
877 | static int kvm_get_fpu(CPUState *env) | |
878 | { | |
879 | struct kvm_fpu fpu; | |
880 | int i, ret; | |
881 | ||
882 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
b9bec74b | 883 | if (ret < 0) { |
05330448 | 884 | return ret; |
b9bec74b | 885 | } |
05330448 AL |
886 | |
887 | env->fpstt = (fpu.fsw >> 11) & 7; | |
888 | env->fpus = fpu.fsw; | |
889 | env->fpuc = fpu.fcw; | |
b9bec74b JK |
890 | for (i = 0; i < 8; ++i) { |
891 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
892 | } | |
05330448 AL |
893 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
894 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
895 | env->mxcsr = fpu.mxcsr; | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
f1665b21 SY |
900 | static int kvm_get_xsave(CPUState *env) |
901 | { | |
902 | #ifdef KVM_CAP_XSAVE | |
903 | struct kvm_xsave* xsave; | |
904 | int ret, i; | |
905 | uint16_t cwd, swd, twd, fop; | |
906 | ||
b9bec74b | 907 | if (!kvm_has_xsave()) { |
f1665b21 | 908 | return kvm_get_fpu(env); |
b9bec74b | 909 | } |
f1665b21 SY |
910 | |
911 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
912 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
0f53994f MT |
913 | if (ret < 0) { |
914 | qemu_free(xsave); | |
f1665b21 | 915 | return ret; |
0f53994f | 916 | } |
f1665b21 SY |
917 | |
918 | cwd = (uint16_t)xsave->region[0]; | |
919 | swd = (uint16_t)(xsave->region[0] >> 16); | |
920 | twd = (uint16_t)xsave->region[1]; | |
921 | fop = (uint16_t)(xsave->region[1] >> 16); | |
922 | env->fpstt = (swd >> 11) & 7; | |
923 | env->fpus = swd; | |
924 | env->fpuc = cwd; | |
b9bec74b | 925 | for (i = 0; i < 8; ++i) { |
f1665b21 | 926 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 927 | } |
f1665b21 SY |
928 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
929 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
930 | sizeof env->fpregs); | |
931 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
932 | sizeof env->xmm_regs); | |
933 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
934 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
935 | sizeof env->ymmh_regs); | |
0f53994f | 936 | qemu_free(xsave); |
f1665b21 SY |
937 | return 0; |
938 | #else | |
939 | return kvm_get_fpu(env); | |
940 | #endif | |
941 | } | |
942 | ||
943 | static int kvm_get_xcrs(CPUState *env) | |
944 | { | |
945 | #ifdef KVM_CAP_XCRS | |
946 | int i, ret; | |
947 | struct kvm_xcrs xcrs; | |
948 | ||
b9bec74b | 949 | if (!kvm_has_xcrs()) { |
f1665b21 | 950 | return 0; |
b9bec74b | 951 | } |
f1665b21 SY |
952 | |
953 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
b9bec74b | 954 | if (ret < 0) { |
f1665b21 | 955 | return ret; |
b9bec74b | 956 | } |
f1665b21 | 957 | |
b9bec74b | 958 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
959 | /* Only support xcr0 now */ |
960 | if (xcrs.xcrs[0].xcr == 0) { | |
961 | env->xcr0 = xcrs.xcrs[0].value; | |
962 | break; | |
963 | } | |
b9bec74b | 964 | } |
f1665b21 SY |
965 | return 0; |
966 | #else | |
967 | return 0; | |
968 | #endif | |
969 | } | |
970 | ||
05330448 AL |
971 | static int kvm_get_sregs(CPUState *env) |
972 | { | |
973 | struct kvm_sregs sregs; | |
974 | uint32_t hflags; | |
0e607a80 | 975 | int bit, i, ret; |
05330448 AL |
976 | |
977 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
b9bec74b | 978 | if (ret < 0) { |
05330448 | 979 | return ret; |
b9bec74b | 980 | } |
05330448 | 981 | |
0e607a80 JK |
982 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
983 | to find it and save its number instead (-1 for none). */ | |
984 | env->interrupt_injected = -1; | |
985 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
986 | if (sregs.interrupt_bitmap[i]) { | |
987 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
988 | env->interrupt_injected = i * 64 + bit; | |
989 | break; | |
990 | } | |
991 | } | |
05330448 AL |
992 | |
993 | get_seg(&env->segs[R_CS], &sregs.cs); | |
994 | get_seg(&env->segs[R_DS], &sregs.ds); | |
995 | get_seg(&env->segs[R_ES], &sregs.es); | |
996 | get_seg(&env->segs[R_FS], &sregs.fs); | |
997 | get_seg(&env->segs[R_GS], &sregs.gs); | |
998 | get_seg(&env->segs[R_SS], &sregs.ss); | |
999 | ||
1000 | get_seg(&env->tr, &sregs.tr); | |
1001 | get_seg(&env->ldt, &sregs.ldt); | |
1002 | ||
1003 | env->idt.limit = sregs.idt.limit; | |
1004 | env->idt.base = sregs.idt.base; | |
1005 | env->gdt.limit = sregs.gdt.limit; | |
1006 | env->gdt.base = sregs.gdt.base; | |
1007 | ||
1008 | env->cr[0] = sregs.cr0; | |
1009 | env->cr[2] = sregs.cr2; | |
1010 | env->cr[3] = sregs.cr3; | |
1011 | env->cr[4] = sregs.cr4; | |
1012 | ||
4a942cea | 1013 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
1014 | |
1015 | env->efer = sregs.efer; | |
4a942cea | 1016 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 | 1017 | |
b9bec74b JK |
1018 | #define HFLAG_COPY_MASK \ |
1019 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1020 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1021 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1022 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1023 | |
1024 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1025 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1026 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1027 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1028 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1029 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1030 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1031 | |
1032 | if (env->efer & MSR_EFER_LMA) { | |
1033 | hflags |= HF_LMA_MASK; | |
1034 | } | |
1035 | ||
1036 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1037 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1038 | } else { | |
1039 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1040 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1041 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1042 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1043 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1044 | !(hflags & HF_CS32_MASK)) { | |
1045 | hflags |= HF_ADDSEG_MASK; | |
1046 | } else { | |
1047 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1048 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1049 | } | |
05330448 AL |
1050 | } |
1051 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1052 | |
1053 | return 0; | |
1054 | } | |
1055 | ||
1056 | static int kvm_get_msrs(CPUState *env) | |
1057 | { | |
1058 | struct { | |
1059 | struct kvm_msrs info; | |
1060 | struct kvm_msr_entry entries[100]; | |
1061 | } msr_data; | |
1062 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1063 | int ret, i, n; | |
1064 | ||
1065 | n = 0; | |
1066 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1067 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1068 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
c3a3a7d3 | 1069 | if (has_msr_star) { |
b9bec74b JK |
1070 | msrs[n++].index = MSR_STAR; |
1071 | } | |
c3a3a7d3 | 1072 | if (has_msr_hsave_pa) { |
75b10c43 | 1073 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1074 | } |
b8cc45d6 GC |
1075 | |
1076 | if (!env->tsc_valid) { | |
1077 | msrs[n++].index = MSR_IA32_TSC; | |
1078 | env->tsc_valid = !vm_running; | |
1079 | } | |
1080 | ||
05330448 | 1081 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1082 | if (lm_capable_kernel) { |
1083 | msrs[n++].index = MSR_CSTAR; | |
1084 | msrs[n++].index = MSR_KERNELGSBASE; | |
1085 | msrs[n++].index = MSR_FMASK; | |
1086 | msrs[n++].index = MSR_LSTAR; | |
1087 | } | |
05330448 | 1088 | #endif |
1a03675d GC |
1089 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1090 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
521f0798 | 1091 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
c5999bfc JK |
1092 | if (has_msr_async_pf_en) { |
1093 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1094 | } | |
f6584ee2 | 1095 | #endif |
1a03675d | 1096 | |
57780495 MT |
1097 | #ifdef KVM_CAP_MCE |
1098 | if (env->mcg_cap) { | |
1099 | msrs[n++].index = MSR_MCG_STATUS; | |
1100 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1101 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1102 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1103 | } |
57780495 MT |
1104 | } |
1105 | #endif | |
1106 | ||
05330448 AL |
1107 | msr_data.info.nmsrs = n; |
1108 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
b9bec74b | 1109 | if (ret < 0) { |
05330448 | 1110 | return ret; |
b9bec74b | 1111 | } |
05330448 AL |
1112 | |
1113 | for (i = 0; i < ret; i++) { | |
1114 | switch (msrs[i].index) { | |
1115 | case MSR_IA32_SYSENTER_CS: | |
1116 | env->sysenter_cs = msrs[i].data; | |
1117 | break; | |
1118 | case MSR_IA32_SYSENTER_ESP: | |
1119 | env->sysenter_esp = msrs[i].data; | |
1120 | break; | |
1121 | case MSR_IA32_SYSENTER_EIP: | |
1122 | env->sysenter_eip = msrs[i].data; | |
1123 | break; | |
1124 | case MSR_STAR: | |
1125 | env->star = msrs[i].data; | |
1126 | break; | |
1127 | #ifdef TARGET_X86_64 | |
1128 | case MSR_CSTAR: | |
1129 | env->cstar = msrs[i].data; | |
1130 | break; | |
1131 | case MSR_KERNELGSBASE: | |
1132 | env->kernelgsbase = msrs[i].data; | |
1133 | break; | |
1134 | case MSR_FMASK: | |
1135 | env->fmask = msrs[i].data; | |
1136 | break; | |
1137 | case MSR_LSTAR: | |
1138 | env->lstar = msrs[i].data; | |
1139 | break; | |
1140 | #endif | |
1141 | case MSR_IA32_TSC: | |
1142 | env->tsc = msrs[i].data; | |
1143 | break; | |
aa851e36 MT |
1144 | case MSR_VM_HSAVE_PA: |
1145 | env->vm_hsave = msrs[i].data; | |
1146 | break; | |
1a03675d GC |
1147 | case MSR_KVM_SYSTEM_TIME: |
1148 | env->system_time_msr = msrs[i].data; | |
1149 | break; | |
1150 | case MSR_KVM_WALL_CLOCK: | |
1151 | env->wall_clock_msr = msrs[i].data; | |
1152 | break; | |
57780495 MT |
1153 | #ifdef KVM_CAP_MCE |
1154 | case MSR_MCG_STATUS: | |
1155 | env->mcg_status = msrs[i].data; | |
1156 | break; | |
1157 | case MSR_MCG_CTL: | |
1158 | env->mcg_ctl = msrs[i].data; | |
1159 | break; | |
1160 | #endif | |
1161 | default: | |
1162 | #ifdef KVM_CAP_MCE | |
1163 | if (msrs[i].index >= MSR_MC0_CTL && | |
1164 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1165 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 MT |
1166 | } |
1167 | #endif | |
d8da8574 | 1168 | break; |
521f0798 | 1169 | #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF) |
f6584ee2 GN |
1170 | case MSR_KVM_ASYNC_PF_EN: |
1171 | env->async_pf_en_msr = msrs[i].data; | |
1172 | break; | |
1173 | #endif | |
05330448 AL |
1174 | } |
1175 | } | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
9bdbe550 HB |
1180 | static int kvm_put_mp_state(CPUState *env) |
1181 | { | |
1182 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1183 | ||
1184 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1185 | } | |
1186 | ||
1187 | static int kvm_get_mp_state(CPUState *env) | |
1188 | { | |
1189 | struct kvm_mp_state mp_state; | |
1190 | int ret; | |
1191 | ||
1192 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1193 | if (ret < 0) { | |
1194 | return ret; | |
1195 | } | |
1196 | env->mp_state = mp_state.mp_state; | |
c14750e8 JK |
1197 | if (kvm_irqchip_in_kernel()) { |
1198 | env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
1199 | } | |
9bdbe550 HB |
1200 | return 0; |
1201 | } | |
1202 | ||
ea643051 | 1203 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c JK |
1204 | { |
1205 | #ifdef KVM_CAP_VCPU_EVENTS | |
1206 | struct kvm_vcpu_events events; | |
1207 | ||
1208 | if (!kvm_has_vcpu_events()) { | |
1209 | return 0; | |
1210 | } | |
1211 | ||
31827373 JK |
1212 | events.exception.injected = (env->exception_injected >= 0); |
1213 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1214 | events.exception.has_error_code = env->has_error_code; |
1215 | events.exception.error_code = env->error_code; | |
1216 | ||
1217 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1218 | events.interrupt.nr = env->interrupt_injected; | |
1219 | events.interrupt.soft = env->soft_interrupt; | |
1220 | ||
1221 | events.nmi.injected = env->nmi_injected; | |
1222 | events.nmi.pending = env->nmi_pending; | |
1223 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1224 | ||
1225 | events.sipi_vector = env->sipi_vector; | |
1226 | ||
ea643051 JK |
1227 | events.flags = 0; |
1228 | if (level >= KVM_PUT_RESET_STATE) { | |
1229 | events.flags |= | |
1230 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1231 | } | |
aee028b9 | 1232 | |
a0fb002c JK |
1233 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
1234 | #else | |
1235 | return 0; | |
1236 | #endif | |
1237 | } | |
1238 | ||
1239 | static int kvm_get_vcpu_events(CPUState *env) | |
1240 | { | |
1241 | #ifdef KVM_CAP_VCPU_EVENTS | |
1242 | struct kvm_vcpu_events events; | |
1243 | int ret; | |
1244 | ||
1245 | if (!kvm_has_vcpu_events()) { | |
1246 | return 0; | |
1247 | } | |
1248 | ||
1249 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1250 | if (ret < 0) { | |
1251 | return ret; | |
1252 | } | |
31827373 | 1253 | env->exception_injected = |
a0fb002c JK |
1254 | events.exception.injected ? events.exception.nr : -1; |
1255 | env->has_error_code = events.exception.has_error_code; | |
1256 | env->error_code = events.exception.error_code; | |
1257 | ||
1258 | env->interrupt_injected = | |
1259 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1260 | env->soft_interrupt = events.interrupt.soft; | |
1261 | ||
1262 | env->nmi_injected = events.nmi.injected; | |
1263 | env->nmi_pending = events.nmi.pending; | |
1264 | if (events.nmi.masked) { | |
1265 | env->hflags2 |= HF2_NMI_MASK; | |
1266 | } else { | |
1267 | env->hflags2 &= ~HF2_NMI_MASK; | |
1268 | } | |
1269 | ||
1270 | env->sipi_vector = events.sipi_vector; | |
1271 | #endif | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | ||
b0b1d690 JK |
1276 | static int kvm_guest_debug_workarounds(CPUState *env) |
1277 | { | |
1278 | int ret = 0; | |
1279 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
1280 | unsigned long reinject_trap = 0; | |
1281 | ||
1282 | if (!kvm_has_vcpu_events()) { | |
1283 | if (env->exception_injected == 1) { | |
1284 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1285 | } else if (env->exception_injected == 3) { | |
1286 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1287 | } | |
1288 | env->exception_injected = -1; | |
1289 | } | |
1290 | ||
1291 | /* | |
1292 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1293 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1294 | * by updating the debug state once again if single-stepping is on. | |
1295 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1296 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1297 | * reinject them via SET_GUEST_DEBUG. | |
1298 | */ | |
1299 | if (reinject_trap || | |
1300 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1301 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1302 | } | |
1303 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
1304 | return ret; | |
1305 | } | |
1306 | ||
ff44f1a3 JK |
1307 | static int kvm_put_debugregs(CPUState *env) |
1308 | { | |
1309 | #ifdef KVM_CAP_DEBUGREGS | |
1310 | struct kvm_debugregs dbgregs; | |
1311 | int i; | |
1312 | ||
1313 | if (!kvm_has_debugregs()) { | |
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | for (i = 0; i < 4; i++) { | |
1318 | dbgregs.db[i] = env->dr[i]; | |
1319 | } | |
1320 | dbgregs.dr6 = env->dr[6]; | |
1321 | dbgregs.dr7 = env->dr[7]; | |
1322 | dbgregs.flags = 0; | |
1323 | ||
1324 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1325 | #else | |
1326 | return 0; | |
1327 | #endif | |
1328 | } | |
1329 | ||
1330 | static int kvm_get_debugregs(CPUState *env) | |
1331 | { | |
1332 | #ifdef KVM_CAP_DEBUGREGS | |
1333 | struct kvm_debugregs dbgregs; | |
1334 | int i, ret; | |
1335 | ||
1336 | if (!kvm_has_debugregs()) { | |
1337 | return 0; | |
1338 | } | |
1339 | ||
1340 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1341 | if (ret < 0) { | |
b9bec74b | 1342 | return ret; |
ff44f1a3 JK |
1343 | } |
1344 | for (i = 0; i < 4; i++) { | |
1345 | env->dr[i] = dbgregs.db[i]; | |
1346 | } | |
1347 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1348 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1349 | #endif | |
1350 | ||
1351 | return 0; | |
1352 | } | |
1353 | ||
ea375f9a | 1354 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1355 | { |
1356 | int ret; | |
1357 | ||
b7680cb6 | 1358 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1359 | |
05330448 | 1360 | ret = kvm_getput_regs(env, 1); |
b9bec74b | 1361 | if (ret < 0) { |
05330448 | 1362 | return ret; |
b9bec74b | 1363 | } |
f1665b21 | 1364 | ret = kvm_put_xsave(env); |
b9bec74b | 1365 | if (ret < 0) { |
f1665b21 | 1366 | return ret; |
b9bec74b | 1367 | } |
f1665b21 | 1368 | ret = kvm_put_xcrs(env); |
b9bec74b | 1369 | if (ret < 0) { |
05330448 | 1370 | return ret; |
b9bec74b | 1371 | } |
05330448 | 1372 | ret = kvm_put_sregs(env); |
b9bec74b | 1373 | if (ret < 0) { |
05330448 | 1374 | return ret; |
b9bec74b | 1375 | } |
ea643051 | 1376 | ret = kvm_put_msrs(env, level); |
b9bec74b | 1377 | if (ret < 0) { |
05330448 | 1378 | return ret; |
b9bec74b | 1379 | } |
ea643051 JK |
1380 | if (level >= KVM_PUT_RESET_STATE) { |
1381 | ret = kvm_put_mp_state(env); | |
b9bec74b | 1382 | if (ret < 0) { |
ea643051 | 1383 | return ret; |
b9bec74b | 1384 | } |
ea643051 | 1385 | } |
ea643051 | 1386 | ret = kvm_put_vcpu_events(env, level); |
b9bec74b | 1387 | if (ret < 0) { |
a0fb002c | 1388 | return ret; |
b9bec74b | 1389 | } |
0d75a9ec | 1390 | ret = kvm_put_debugregs(env); |
b9bec74b | 1391 | if (ret < 0) { |
b0b1d690 | 1392 | return ret; |
b9bec74b | 1393 | } |
b0b1d690 JK |
1394 | /* must be last */ |
1395 | ret = kvm_guest_debug_workarounds(env); | |
b9bec74b | 1396 | if (ret < 0) { |
ff44f1a3 | 1397 | return ret; |
b9bec74b | 1398 | } |
05330448 AL |
1399 | return 0; |
1400 | } | |
1401 | ||
1402 | int kvm_arch_get_registers(CPUState *env) | |
1403 | { | |
1404 | int ret; | |
1405 | ||
b7680cb6 | 1406 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1407 | |
05330448 | 1408 | ret = kvm_getput_regs(env, 0); |
b9bec74b | 1409 | if (ret < 0) { |
05330448 | 1410 | return ret; |
b9bec74b | 1411 | } |
f1665b21 | 1412 | ret = kvm_get_xsave(env); |
b9bec74b | 1413 | if (ret < 0) { |
f1665b21 | 1414 | return ret; |
b9bec74b | 1415 | } |
f1665b21 | 1416 | ret = kvm_get_xcrs(env); |
b9bec74b | 1417 | if (ret < 0) { |
05330448 | 1418 | return ret; |
b9bec74b | 1419 | } |
05330448 | 1420 | ret = kvm_get_sregs(env); |
b9bec74b | 1421 | if (ret < 0) { |
05330448 | 1422 | return ret; |
b9bec74b | 1423 | } |
05330448 | 1424 | ret = kvm_get_msrs(env); |
b9bec74b | 1425 | if (ret < 0) { |
05330448 | 1426 | return ret; |
b9bec74b | 1427 | } |
5a2e3c2e | 1428 | ret = kvm_get_mp_state(env); |
b9bec74b | 1429 | if (ret < 0) { |
5a2e3c2e | 1430 | return ret; |
b9bec74b | 1431 | } |
a0fb002c | 1432 | ret = kvm_get_vcpu_events(env); |
b9bec74b | 1433 | if (ret < 0) { |
a0fb002c | 1434 | return ret; |
b9bec74b | 1435 | } |
ff44f1a3 | 1436 | ret = kvm_get_debugregs(env); |
b9bec74b | 1437 | if (ret < 0) { |
ff44f1a3 | 1438 | return ret; |
b9bec74b | 1439 | } |
05330448 AL |
1440 | return 0; |
1441 | } | |
1442 | ||
7a39fe58 | 1443 | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
05330448 | 1444 | { |
ce377af3 JK |
1445 | int ret; |
1446 | ||
276ce815 LJ |
1447 | /* Inject NMI */ |
1448 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1449 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1450 | DPRINTF("injected NMI\n"); | |
ce377af3 JK |
1451 | ret = kvm_vcpu_ioctl(env, KVM_NMI); |
1452 | if (ret < 0) { | |
1453 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
1454 | strerror(-ret)); | |
1455 | } | |
276ce815 LJ |
1456 | } |
1457 | ||
db1669bc JK |
1458 | if (!kvm_irqchip_in_kernel()) { |
1459 | /* Force the VCPU out of its inner loop to process the INIT request */ | |
1460 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1461 | env->exit_request = 1; | |
05330448 | 1462 | } |
05330448 | 1463 | |
db1669bc JK |
1464 | /* Try to inject an interrupt if the guest can accept it */ |
1465 | if (run->ready_for_interrupt_injection && | |
1466 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1467 | (env->eflags & IF_MASK)) { | |
1468 | int irq; | |
1469 | ||
1470 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1471 | irq = cpu_get_pic_interrupt(env); | |
1472 | if (irq >= 0) { | |
1473 | struct kvm_interrupt intr; | |
1474 | ||
1475 | intr.irq = irq; | |
db1669bc | 1476 | DPRINTF("injected interrupt %d\n", irq); |
ce377af3 JK |
1477 | ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1478 | if (ret < 0) { | |
1479 | fprintf(stderr, | |
1480 | "KVM: injection failed, interrupt lost (%s)\n", | |
1481 | strerror(-ret)); | |
1482 | } | |
db1669bc JK |
1483 | } |
1484 | } | |
05330448 | 1485 | |
db1669bc JK |
1486 | /* If we have an interrupt but the guest is not ready to receive an |
1487 | * interrupt, request an interrupt window exit. This will | |
1488 | * cause a return to userspace as soon as the guest is ready to | |
1489 | * receive interrupts. */ | |
1490 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { | |
1491 | run->request_interrupt_window = 1; | |
1492 | } else { | |
1493 | run->request_interrupt_window = 0; | |
1494 | } | |
1495 | ||
1496 | DPRINTF("setting tpr\n"); | |
1497 | run->cr8 = cpu_get_apic_tpr(env->apic_state); | |
1498 | } | |
05330448 AL |
1499 | } |
1500 | ||
7a39fe58 | 1501 | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
05330448 | 1502 | { |
b9bec74b | 1503 | if (run->if_flag) { |
05330448 | 1504 | env->eflags |= IF_MASK; |
b9bec74b | 1505 | } else { |
05330448 | 1506 | env->eflags &= ~IF_MASK; |
b9bec74b | 1507 | } |
4a942cea BS |
1508 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1509 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1510 | } |
1511 | ||
0af691d7 MT |
1512 | int kvm_arch_process_irqchip_events(CPUState *env) |
1513 | { | |
db1669bc JK |
1514 | if (kvm_irqchip_in_kernel()) { |
1515 | return 0; | |
1516 | } | |
1517 | ||
6792a57b JK |
1518 | if (env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI)) { |
1519 | env->halted = 0; | |
1520 | } | |
0af691d7 MT |
1521 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { |
1522 | kvm_cpu_synchronize_state(env); | |
1523 | do_cpu_init(env); | |
0af691d7 | 1524 | } |
0af691d7 MT |
1525 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { |
1526 | kvm_cpu_synchronize_state(env); | |
1527 | do_cpu_sipi(env); | |
1528 | } | |
1529 | ||
1530 | return env->halted; | |
1531 | } | |
1532 | ||
05330448 AL |
1533 | static int kvm_handle_halt(CPUState *env) |
1534 | { | |
1535 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1536 | (env->eflags & IF_MASK)) && | |
1537 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1538 | env->halted = 1; | |
05330448 AL |
1539 | return 0; |
1540 | } | |
1541 | ||
1542 | return 1; | |
1543 | } | |
1544 | ||
bb44e0d1 JK |
1545 | static bool host_supports_vmx(void) |
1546 | { | |
1547 | uint32_t ecx, unused; | |
1548 | ||
1549 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
1550 | return ecx & CPUID_EXT_VMX; | |
1551 | } | |
1552 | ||
1553 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
1554 | ||
05330448 AL |
1555 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
1556 | { | |
bb44e0d1 | 1557 | uint64_t code; |
05330448 AL |
1558 | int ret = 0; |
1559 | ||
1560 | switch (run->exit_reason) { | |
1561 | case KVM_EXIT_HLT: | |
8c0d577e | 1562 | DPRINTF("handle_hlt\n"); |
05330448 AL |
1563 | ret = kvm_handle_halt(env); |
1564 | break; | |
646042e1 JK |
1565 | case KVM_EXIT_SET_TPR: |
1566 | ret = 1; | |
1567 | break; | |
bb44e0d1 JK |
1568 | case KVM_EXIT_FAIL_ENTRY: |
1569 | code = run->fail_entry.hardware_entry_failure_reason; | |
1570 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
1571 | code); | |
1572 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
1573 | fprintf(stderr, | |
1574 | "\nIf you're runnning a guest on an Intel machine without " | |
1575 | "unrestricted mode\n" | |
1576 | "support, the failure can be most likely due to the guest " | |
1577 | "entering an invalid\n" | |
1578 | "state for Intel VT. For example, the guest maybe running " | |
1579 | "in big real mode\n" | |
1580 | "which is not supported on less recent Intel processors." | |
1581 | "\n\n"); | |
1582 | } | |
1583 | ret = -1; | |
1584 | break; | |
1585 | case KVM_EXIT_EXCEPTION: | |
1586 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
1587 | run->ex.exception, run->ex.error_code); | |
1588 | ret = -1; | |
1589 | break; | |
73aaec4a JK |
1590 | default: |
1591 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
1592 | ret = -1; | |
1593 | break; | |
05330448 AL |
1594 | } |
1595 | ||
1596 | return ret; | |
1597 | } | |
e22a25c9 AL |
1598 | |
1599 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
e22a25c9 AL |
1600 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1601 | { | |
38972938 | 1602 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1603 | |
e22a25c9 | 1604 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
b9bec74b | 1605 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
e22a25c9 | 1606 | return -EINVAL; |
b9bec74b | 1607 | } |
e22a25c9 AL |
1608 | return 0; |
1609 | } | |
1610 | ||
1611 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1612 | { | |
1613 | uint8_t int3; | |
1614 | ||
1615 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
b9bec74b | 1616 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
e22a25c9 | 1617 | return -EINVAL; |
b9bec74b | 1618 | } |
e22a25c9 AL |
1619 | return 0; |
1620 | } | |
1621 | ||
1622 | static struct { | |
1623 | target_ulong addr; | |
1624 | int len; | |
1625 | int type; | |
1626 | } hw_breakpoint[4]; | |
1627 | ||
1628 | static int nb_hw_breakpoint; | |
1629 | ||
1630 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1631 | { | |
1632 | int n; | |
1633 | ||
b9bec74b | 1634 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1635 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1636 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1637 | return n; |
b9bec74b JK |
1638 | } |
1639 | } | |
e22a25c9 AL |
1640 | return -1; |
1641 | } | |
1642 | ||
1643 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1644 | target_ulong len, int type) | |
1645 | { | |
1646 | switch (type) { | |
1647 | case GDB_BREAKPOINT_HW: | |
1648 | len = 1; | |
1649 | break; | |
1650 | case GDB_WATCHPOINT_WRITE: | |
1651 | case GDB_WATCHPOINT_ACCESS: | |
1652 | switch (len) { | |
1653 | case 1: | |
1654 | break; | |
1655 | case 2: | |
1656 | case 4: | |
1657 | case 8: | |
b9bec74b | 1658 | if (addr & (len - 1)) { |
e22a25c9 | 1659 | return -EINVAL; |
b9bec74b | 1660 | } |
e22a25c9 AL |
1661 | break; |
1662 | default: | |
1663 | return -EINVAL; | |
1664 | } | |
1665 | break; | |
1666 | default: | |
1667 | return -ENOSYS; | |
1668 | } | |
1669 | ||
b9bec74b | 1670 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 1671 | return -ENOBUFS; |
b9bec74b JK |
1672 | } |
1673 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 1674 | return -EEXIST; |
b9bec74b | 1675 | } |
e22a25c9 AL |
1676 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1677 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1678 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1679 | nb_hw_breakpoint++; | |
1680 | ||
1681 | return 0; | |
1682 | } | |
1683 | ||
1684 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1685 | target_ulong len, int type) | |
1686 | { | |
1687 | int n; | |
1688 | ||
1689 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 1690 | if (n < 0) { |
e22a25c9 | 1691 | return -ENOENT; |
b9bec74b | 1692 | } |
e22a25c9 AL |
1693 | nb_hw_breakpoint--; |
1694 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1695 | ||
1696 | return 0; | |
1697 | } | |
1698 | ||
1699 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1700 | { | |
1701 | nb_hw_breakpoint = 0; | |
1702 | } | |
1703 | ||
1704 | static CPUWatchpoint hw_watchpoint; | |
1705 | ||
1706 | int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) | |
1707 | { | |
1708 | int handle = 0; | |
1709 | int n; | |
1710 | ||
1711 | if (arch_info->exception == 1) { | |
1712 | if (arch_info->dr6 & (1 << 14)) { | |
b9bec74b | 1713 | if (cpu_single_env->singlestep_enabled) { |
e22a25c9 | 1714 | handle = 1; |
b9bec74b | 1715 | } |
e22a25c9 | 1716 | } else { |
b9bec74b JK |
1717 | for (n = 0; n < 4; n++) { |
1718 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
1719 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1720 | case 0x0: | |
1721 | handle = 1; | |
1722 | break; | |
1723 | case 0x1: | |
1724 | handle = 1; | |
1725 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1726 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1727 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1728 | break; | |
1729 | case 0x3: | |
1730 | handle = 1; | |
1731 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1732 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1733 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1734 | break; | |
1735 | } | |
b9bec74b JK |
1736 | } |
1737 | } | |
e22a25c9 | 1738 | } |
b9bec74b | 1739 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
e22a25c9 | 1740 | handle = 1; |
b9bec74b | 1741 | } |
b0b1d690 JK |
1742 | if (!handle) { |
1743 | cpu_synchronize_state(cpu_single_env); | |
1744 | assert(cpu_single_env->exception_injected == -1); | |
1745 | ||
1746 | cpu_single_env->exception_injected = arch_info->exception; | |
1747 | cpu_single_env->has_error_code = 0; | |
1748 | } | |
e22a25c9 AL |
1749 | |
1750 | return handle; | |
1751 | } | |
1752 | ||
1753 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1754 | { | |
1755 | const uint8_t type_code[] = { | |
1756 | [GDB_BREAKPOINT_HW] = 0x0, | |
1757 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1758 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1759 | }; | |
1760 | const uint8_t len_code[] = { | |
1761 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1762 | }; | |
1763 | int n; | |
1764 | ||
b9bec74b | 1765 | if (kvm_sw_breakpoints_active(env)) { |
e22a25c9 | 1766 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 1767 | } |
e22a25c9 AL |
1768 | if (nb_hw_breakpoint > 0) { |
1769 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1770 | dbg->arch.debugreg[7] = 0x0600; | |
1771 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1772 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1773 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1774 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 1775 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
1776 | } |
1777 | } | |
1778 | } | |
1779 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
4513d923 GN |
1780 | |
1781 | bool kvm_arch_stop_on_emulation_error(CPUState *env) | |
1782 | { | |
b9bec74b JK |
1783 | return !(env->cr[0] & CR0_PE_MASK) || |
1784 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 GN |
1785 | } |
1786 | ||
c0532a76 MT |
1787 | static void hardware_memory_error(void) |
1788 | { | |
1789 | fprintf(stderr, "Hardware memory error!\n"); | |
1790 | exit(1); | |
1791 | } | |
1792 | ||
f71ac88f HS |
1793 | #ifdef KVM_CAP_MCE |
1794 | static void kvm_mce_broadcast_rest(CPUState *env) | |
1795 | { | |
7cc2cc3e JD |
1796 | struct kvm_x86_mce mce = { |
1797 | .bank = 1, | |
1798 | .status = MCI_STATUS_VAL | MCI_STATUS_UC, | |
1799 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
1800 | .addr = 0, | |
1801 | .misc = 0, | |
1802 | }; | |
f71ac88f | 1803 | CPUState *cenv; |
f71ac88f HS |
1804 | |
1805 | /* Broadcast MCA signal for processor version 06H_EH and above */ | |
2bd3e04c | 1806 | if (cpu_x86_support_mca_broadcast(env)) { |
f71ac88f HS |
1807 | for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) { |
1808 | if (cenv == env) { | |
1809 | continue; | |
1810 | } | |
7cc2cc3e | 1811 | kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR); |
f71ac88f HS |
1812 | } |
1813 | } | |
1814 | } | |
e387c338 JD |
1815 | |
1816 | static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr) | |
1817 | { | |
1818 | struct kvm_x86_mce mce = { | |
1819 | .bank = 9, | |
1820 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1821 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1822 | | MCI_STATUS_AR | 0x134, | |
1823 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV, | |
1824 | .addr = paddr, | |
1825 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
1826 | }; | |
1827 | int r; | |
1828 | ||
1829 | r = kvm_set_mce(env, &mce); | |
1830 | if (r < 0) { | |
1831 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
1832 | abort(); | |
1833 | } | |
1834 | kvm_mce_broadcast_rest(env); | |
1835 | } | |
1836 | ||
1837 | static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr) | |
1838 | { | |
1839 | struct kvm_x86_mce mce = { | |
1840 | .bank = 9, | |
1841 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1842 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1843 | | 0xc0, | |
1844 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
1845 | .addr = paddr, | |
1846 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
1847 | }; | |
1848 | int r; | |
1849 | ||
1850 | r = kvm_set_mce(env, &mce); | |
1851 | if (r < 0) { | |
1852 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
1853 | abort(); | |
1854 | } | |
1855 | kvm_mce_broadcast_rest(env); | |
1856 | } | |
1857 | ||
1858 | static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr) | |
1859 | { | |
7cc2cc3e JD |
1860 | struct kvm_x86_mce mce = { |
1861 | .bank = 9, | |
1862 | .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1863 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1864 | | 0xc0, | |
1865 | .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV, | |
1866 | .addr = paddr, | |
1867 | .misc = (MCM_ADDR_PHYS << 6) | 0xc, | |
1868 | }; | |
e387c338 | 1869 | |
7cc2cc3e | 1870 | kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR); |
e387c338 JD |
1871 | kvm_mce_broadcast_rest(env); |
1872 | } | |
1873 | ||
f71ac88f HS |
1874 | #endif |
1875 | ||
a1b87fe0 | 1876 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) |
c0532a76 MT |
1877 | { |
1878 | #if defined(KVM_CAP_MCE) | |
c0532a76 MT |
1879 | void *vaddr; |
1880 | ram_addr_t ram_addr; | |
1881 | target_phys_addr_t paddr; | |
c0532a76 MT |
1882 | |
1883 | if ((env->mcg_cap & MCG_SER_P) && addr | |
1884 | && (code == BUS_MCEERR_AR | |
1885 | || code == BUS_MCEERR_AO)) { | |
c0532a76 MT |
1886 | vaddr = (void *)addr; |
1887 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1888 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) { | |
1889 | fprintf(stderr, "Hardware memory error for memory used by " | |
1890 | "QEMU itself instead of guest system!\n"); | |
1891 | /* Hope we are lucky for AO MCE */ | |
1892 | if (code == BUS_MCEERR_AO) { | |
1893 | return 0; | |
1894 | } else { | |
1895 | hardware_memory_error(); | |
1896 | } | |
1897 | } | |
e387c338 JD |
1898 | |
1899 | if (code == BUS_MCEERR_AR) { | |
1900 | /* Fake an Intel architectural Data Load SRAR UCR */ | |
1901 | kvm_mce_inj_srar_dataload(env, paddr); | |
1902 | } else { | |
1903 | /* | |
1904 | * If there is an MCE excpetion being processed, ignore | |
1905 | * this SRAO MCE | |
1906 | */ | |
1907 | if (!kvm_mce_in_progress(env)) { | |
1908 | /* Fake an Intel architectural Memory scrubbing UCR */ | |
1909 | kvm_mce_inj_srao_memscrub(env, paddr); | |
1910 | } | |
c0532a76 MT |
1911 | } |
1912 | } else | |
1913 | #endif | |
1914 | { | |
1915 | if (code == BUS_MCEERR_AO) { | |
1916 | return 0; | |
1917 | } else if (code == BUS_MCEERR_AR) { | |
1918 | hardware_memory_error(); | |
1919 | } else { | |
1920 | return 1; | |
1921 | } | |
1922 | } | |
1923 | return 0; | |
1924 | } | |
1925 | ||
a1b87fe0 | 1926 | int kvm_arch_on_sigbus(int code, void *addr) |
c0532a76 MT |
1927 | { |
1928 | #if defined(KVM_CAP_MCE) | |
1929 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
c0532a76 MT |
1930 | void *vaddr; |
1931 | ram_addr_t ram_addr; | |
1932 | target_phys_addr_t paddr; | |
c0532a76 MT |
1933 | |
1934 | /* Hope we are lucky for AO MCE */ | |
1935 | vaddr = addr; | |
1936 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1937 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) { | |
1938 | fprintf(stderr, "Hardware memory error for memory used by " | |
1939 | "QEMU itself instead of guest system!: %p\n", addr); | |
1940 | return 0; | |
1941 | } | |
e387c338 | 1942 | kvm_mce_inj_srao_memscrub2(first_cpu, paddr); |
c0532a76 MT |
1943 | } else |
1944 | #endif | |
1945 | { | |
1946 | if (code == BUS_MCEERR_AO) { | |
1947 | return 0; | |
1948 | } else if (code == BUS_MCEERR_AR) { | |
1949 | hardware_memory_error(); | |
1950 | } else { | |
1951 | return 1; | |
1952 | } | |
1953 | } | |
1954 | return 0; | |
1955 | } |