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s390x/kvm: fix build against qemu_uuid
[mirror_qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c
AS		 28#include "hyperv.h"
29
022c62cb 30#include "exec/gdbstub.h"
1de7afc9
PB		 31#include "qemu/host-utils.h"
32#include "qemu/config-file.h"
1c4a55db 33#include "qemu/error-report.h"
0d09e41a
PB		 34#include "hw/i386/pc.h"
35#include "hw/i386/apic.h"
e0723c45
PB		 36#include "hw/i386/apic_internal.h"
37#include "hw/i386/apic-msidef.h"
8b5ed7df 38#include "hw/i386/intel_iommu.h"
e1d4fb2d 39#include "hw/i386/x86-iommu.h"
50efe82c 40
022c62cb 41#include "exec/ioport.h"
73aa529a 42#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 43#include "hw/pci/pci.h"
15eafc2e 44#include "hw/pci/msi.h"
68bfd0ad 45#include "migration/migration.h"
4c663752 46#include "exec/memattrs.h"
8b5ed7df 47#include "trace.h"
05330448
AL		 48
49//#define DEBUG_KVM
50
51#ifdef DEBUG_KVM
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54#else
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { } while (0)
57#endif
58
1a03675d
GC		 59#define MSR_KVM_WALL_CLOCK 0x11
60#define MSR_KVM_SYSTEM_TIME 0x12
61
d1138251
EH		 62/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64#define MSR_BUF_SIZE 4096
d71b62a1 65
c0532a76
MT		 66#ifndef BUS_MCEERR_AR
67#define BUS_MCEERR_AR 4
68#endif
69#ifndef BUS_MCEERR_AO
70#define BUS_MCEERR_AO 5
71#endif
72
94a8d39a
JK		 73const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
74 KVM_CAP_INFO(SET_TSS_ADDR),
75 KVM_CAP_INFO(EXT_CPUID),
76 KVM_CAP_INFO(MP_STATE),
77 KVM_CAP_LAST_INFO
78};
25d2e361 79
c3a3a7d3
JK		 80static bool has_msr_star;
81static bool has_msr_hsave_pa;
c9b8f6b6 82static bool has_msr_tsc_aux;
f28558d3 83static bool has_msr_tsc_adjust;
aa82ba54 84static bool has_msr_tsc_deadline;
df67696e 85static bool has_msr_feature_control;
21e87c46 86static bool has_msr_misc_enable;
fc12d72e 87static bool has_msr_smbase;
79e9ebeb 88static bool has_msr_bndcfgs;
25d2e361 89static int lm_capable_kernel;
7bc3d711 90static bool has_msr_hv_hypercall;
f2a53c9e 91static bool has_msr_hv_crash;
744b8a94 92static bool has_msr_hv_reset;
8c145d7c 93static bool has_msr_hv_vpindex;
46eb8f98 94static bool has_msr_hv_runtime;
866eea9a 95static bool has_msr_hv_synic;
ff99aa64 96static bool has_msr_hv_stimer;
18cd2c17 97static bool has_msr_xss;
b827df58 98
0d894367
PB		 99static bool has_msr_architectural_pmu;
100static uint32_t num_architectural_pmu_counters;
101
28143b40
TH		 102static int has_xsave;
103static int has_xcrs;
104static int has_pit_state2;
105
87f8b626
AR		 106static bool has_msr_mcg_ext_ctl;
107
494e95e9
CP		 108static struct kvm_cpuid2 *cpuid_cache;
109
28143b40
TH		 110int kvm_has_pit_state2(void)
111{
112 return has_pit_state2;
113}
114
355023f2
PB		 115bool kvm_has_smm(void)
116{
117 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
118}
119
1d31f66b
PM		 120bool kvm_allows_irq0_override(void)
121{
122 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
123}
124
0fd7e098
LL		 125static int kvm_get_tsc(CPUState *cs)
126{
127 X86CPU *cpu = X86_CPU(cs);
128 CPUX86State *env = &cpu->env;
129 struct {
130 struct kvm_msrs info;
131 struct kvm_msr_entry entries[1];
132 } msr_data;
133 int ret;
134
135 if (env->tsc_valid) {
136 return 0;
137 }
138
139 msr_data.info.nmsrs = 1;
140 msr_data.entries[0].index = MSR_IA32_TSC;
141 env->tsc_valid = !runstate_is_running();
142
143 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
144 if (ret < 0) {
145 return ret;
146 }
147
48e1a45c 148 assert(ret == 1);
0fd7e098
LL		 149 env->tsc = msr_data.entries[0].data;
150 return 0;
151}
152
153static inline void do_kvm_synchronize_tsc(void *arg)
154{
155 CPUState *cpu = arg;
156
157 kvm_get_tsc(cpu);
158}
159
160void kvm_synchronize_all_tsc(void)
161{
162 CPUState *cpu;
163
164 if (kvm_enabled()) {
165 CPU_FOREACH(cpu) {
166 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
167 }
168 }
169}
170
b827df58
AK		 171static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
172{
173 struct kvm_cpuid2 *cpuid;
174 int r, size;
175
176 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 177 cpuid = g_malloc0(size);
b827df58
AK		 178 cpuid->nent = max;
179 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 180 if (r == 0 && cpuid->nent >= max) {
181 r = -E2BIG;
182 }
b827df58
AK		 183 if (r < 0) {
184 if (r == -E2BIG) {
7267c094 185 g_free(cpuid);
b827df58
AK		 186 return NULL;
187 } else {
188 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
189 strerror(-r));
190 exit(1);
191 }
192 }
193 return cpuid;
194}
195
dd87f8a6
EH		 196/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
197 * for all entries.
198 */
199static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
200{
201 struct kvm_cpuid2 *cpuid;
202 int max = 1;
494e95e9
CP		 203
204 if (cpuid_cache != NULL) {
205 return cpuid_cache;
206 }
dd87f8a6
EH		 207 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
208 max *= 2;
209 }
494e95e9 210 cpuid_cache = cpuid;
dd87f8a6
EH		 211 return cpuid;
212}
213
a443bc34 214static const struct kvm_para_features {
0c31b744
GC		 215 int cap;
216 int feature;
217} para_features[] = {
218 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
219 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
220 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 221 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 222};
223
ba9bc59e 224static int get_para_features(KVMState *s)
0c31b744
GC		 225{
226 int i, features = 0;
227
8e03c100 228 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 229 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 230 features |= (1 << para_features[i].feature);
231 }
232 }
233
234 return features;
235}
0c31b744
GC		 236
237
829ae2f9
EH		 238/* Returns the value for a specific register on the cpuid entry
239 */
240static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
241{
242 uint32_t ret = 0;
243 switch (reg) {
244 case R_EAX:
245 ret = entry->eax;
246 break;
247 case R_EBX:
248 ret = entry->ebx;
249 break;
250 case R_ECX:
251 ret = entry->ecx;
252 break;
253 case R_EDX:
254 ret = entry->edx;
255 break;
256 }
257 return ret;
258}
259
4fb73f1d
EH		 260/* Find matching entry for function/index on kvm_cpuid2 struct
261 */
262static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
263 uint32_t function,
264 uint32_t index)
265{
266 int i;
267 for (i = 0; i < cpuid->nent; ++i) {
268 if (cpuid->entries[i].function == function &&
269 cpuid->entries[i].index == index) {
270 return &cpuid->entries[i];
271 }
272 }
273 /* not found: */
274 return NULL;
275}
276
ba9bc59e 277uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 278 uint32_t index, int reg)
b827df58
AK		 279{
280 struct kvm_cpuid2 *cpuid;
b827df58
AK		 281 uint32_t ret = 0;
282 uint32_t cpuid_1_edx;
8c723b79 283 bool found = false;
b827df58 284
dd87f8a6 285 cpuid = get_supported_cpuid(s);
b827df58 286
4fb73f1d
EH		 287 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
288 if (entry) {
289 found = true;
290 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 291 }
292
7b46e5ce
EH		 293 /* Fixups for the data returned by KVM, below */
294
c2acb022
EH		 295 if (function == 1 && reg == R_EDX) {
296 /* KVM before 2.6.30 misreports the following features */
297 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 298 } else if (function == 1 && reg == R_ECX) {
299 /* We can set the hypervisor flag, even if KVM does not return it on
300 * GET_SUPPORTED_CPUID
301 */
302 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 303 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
304 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
305 * and the irqchip is in the kernel.
306 */
307 if (kvm_irqchip_in_kernel() &&
308 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
309 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
310 }
41e5e76d
EH		 311
312 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
313 * without the in-kernel irqchip
314 */
315 if (!kvm_irqchip_in_kernel()) {
316 ret &= ~CPUID_EXT_X2APIC;
b827df58 317 }
28b8e4d0
JK		 318 } else if (function == 6 && reg == R_EAX) {
319 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 320 } else if (function == 0x80000001 && reg == R_EDX) {
321 /* On Intel, kvm returns cpuid according to the Intel spec,
322 * so add missing bits according to the AMD spec:
323 */
324 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
325 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 326 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
327 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
328 * be enabled without the in-kernel irqchip
329 */
330 if (!kvm_irqchip_in_kernel()) {
331 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
332 }
b827df58
AK		 333 }
334
0c31b744 335 /* fallback for older kernels */
8c723b79 336 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 337 ret = get_para_features(s);
b9bec74b 338 }
0c31b744
GC		 339
340 return ret;
bb0300dc 341}
bb0300dc 342
3c85e74f
HY		 343typedef struct HWPoisonPage {
344 ram_addr_t ram_addr;
345 QLIST_ENTRY(HWPoisonPage) list;
346} HWPoisonPage;
347
348static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
349 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
350
351static void kvm_unpoison_all(void *param)
352{
353 HWPoisonPage *page, *next_page;
354
355 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
356 QLIST_REMOVE(page, list);
357 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 358 g_free(page);
3c85e74f
HY		 359 }
360}
361
3c85e74f
HY		 362static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
363{
364 HWPoisonPage *page;
365
366 QLIST_FOREACH(page, &hwpoison_page_list, list) {
367 if (page->ram_addr == ram_addr) {
368 return;
369 }
370 }
ab3ad07f 371 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 372 page->ram_addr = ram_addr;
373 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
374}
375
e7701825
MT		 376static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
377 int *max_banks)
378{
379 int r;
380
14a09518 381 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 382 if (r > 0) {
383 *max_banks = r;
384 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
385 }
386 return -ENOSYS;
387}
388
bee615d4 389static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 390{
87f8b626 391 CPUState *cs = CPU(cpu);
bee615d4 392 CPUX86State *env = &cpu->env;
c34d440a
JK		 393 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
394 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
395 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 396 int flags = 0;
e7701825 397
c34d440a
JK		 398 if (code == BUS_MCEERR_AR) {
399 status |= MCI_STATUS_AR | 0x134;
400 mcg_status |= MCG_STATUS_EIPV;
401 } else {
402 status |= 0xc0;
403 mcg_status |= MCG_STATUS_RIPV;
419fb20a 404 }
87f8b626
AR		 405
406 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
407 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
408 * guest kernel back into env->mcg_ext_ctl.
409 */
410 cpu_synchronize_state(cs);
411 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
412 mcg_status |= MCG_STATUS_LMCE;
413 flags = 0;
414 }
415
8c5cf3b6 416 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 417 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 418}
419fb20a
JK		 419
420static void hardware_memory_error(void)
421{
422 fprintf(stderr, "Hardware memory error!\n");
423 exit(1);
424}
425
20d695a9 426int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 427{
20d695a9
AF		 428 X86CPU *cpu = X86_CPU(c);
429 CPUX86State *env = &cpu->env;
419fb20a 430 ram_addr_t ram_addr;
a8170e5e 431 hwaddr paddr;
419fb20a
JK		 432
433 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 434 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
07bdaa41
PB		 435 ram_addr = qemu_ram_addr_from_host(addr);
436 if (ram_addr == RAM_ADDR_INVALID ||
a60f24b5 437 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 438 fprintf(stderr, "Hardware memory error for memory used by "
439 "QEMU itself instead of guest system!\n");
440 /* Hope we are lucky for AO MCE */
441 if (code == BUS_MCEERR_AO) {
442 return 0;
443 } else {
444 hardware_memory_error();
445 }
446 }
3c85e74f 447 kvm_hwpoison_page_add(ram_addr);
bee615d4 448 kvm_mce_inject(cpu, paddr, code);
e56ff191 449 } else {
419fb20a
JK		 450 if (code == BUS_MCEERR_AO) {
451 return 0;
452 } else if (code == BUS_MCEERR_AR) {
453 hardware_memory_error();
454 } else {
455 return 1;
456 }
457 }
458 return 0;
459}
460
461int kvm_arch_on_sigbus(int code, void *addr)
462{
182735ef
AF		 463 X86CPU *cpu = X86_CPU(first_cpu);
464
465 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 466 ram_addr_t ram_addr;
a8170e5e 467 hwaddr paddr;
419fb20a
JK		 468
469 /* Hope we are lucky for AO MCE */
07bdaa41
PB		 470 ram_addr = qemu_ram_addr_from_host(addr);
471 if (ram_addr == RAM_ADDR_INVALID ||
182735ef 472 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 473 addr, &paddr)) {
419fb20a
JK		 474 fprintf(stderr, "Hardware memory error for memory used by "
475 "QEMU itself instead of guest system!: %p\n", addr);
476 return 0;
477 }
3c85e74f 478 kvm_hwpoison_page_add(ram_addr);
182735ef 479 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 480 } else {
419fb20a
JK		 481 if (code == BUS_MCEERR_AO) {
482 return 0;
483 } else if (code == BUS_MCEERR_AR) {
484 hardware_memory_error();
485 } else {
486 return 1;
487 }
488 }
489 return 0;
490}
e7701825 491
1bc22652 492static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 493{
1bc22652
AF		 494 CPUX86State *env = &cpu->env;
495
ab443475
JK		 496 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
497 unsigned int bank, bank_num = env->mcg_cap & 0xff;
498 struct kvm_x86_mce mce;
499
500 env->exception_injected = -1;
501
502 /*
503 * There must be at least one bank in use if an MCE is pending.
504 * Find it and use its values for the event injection.
505 */
506 for (bank = 0; bank < bank_num; bank++) {
507 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
508 break;
509 }
510 }
511 assert(bank < bank_num);
512
513 mce.bank = bank;
514 mce.status = env->mce_banks[bank * 4 + 1];
515 mce.mcg_status = env->mcg_status;
516 mce.addr = env->mce_banks[bank * 4 + 2];
517 mce.misc = env->mce_banks[bank * 4 + 3];
518
1bc22652 519 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 520 }
ab443475
JK		 521 return 0;
522}
523
1dfb4dd9 524static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 525{
317ac620 526 CPUX86State *env = opaque;
b8cc45d6
GC		 527
528 if (running) {
529 env->tsc_valid = false;
530 }
531}
532
83b17af5 533unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 534{
83b17af5 535 X86CPU *cpu = X86_CPU(cs);
7e72a45c 536 return cpu->apic_id;
b164e48e
EH		 537}
538
92067bf4
IM		 539#ifndef KVM_CPUID_SIGNATURE_NEXT
540#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
541#endif
542
543static bool hyperv_hypercall_available(X86CPU *cpu)
544{
545 return cpu->hyperv_vapic ||
546 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
547}
548
549static bool hyperv_enabled(X86CPU *cpu)
550{
7bc3d711
PB		 551 CPUState *cs = CPU(cpu);
552 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
553 (hyperv_hypercall_available(cpu) ||
48a5f3bc 554 cpu->hyperv_time ||
f2a53c9e 555 cpu->hyperv_relaxed_timing ||
744b8a94 556 cpu->hyperv_crash ||
8c145d7c 557 cpu->hyperv_reset ||
46eb8f98 558 cpu->hyperv_vpindex ||
866eea9a 559 cpu->hyperv_runtime ||
ff99aa64
AS		 560 cpu->hyperv_synic ||
561 cpu->hyperv_stimer);
92067bf4
IM		 562}
563
5031283d
HZ		 564static int kvm_arch_set_tsc_khz(CPUState *cs)
565{
566 X86CPU *cpu = X86_CPU(cs);
567 CPUX86State *env = &cpu->env;
568 int r;
569
570 if (!env->tsc_khz) {
571 return 0;
572 }
573
574 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
575 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
576 -ENOTSUP;
577 if (r < 0) {
578 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
579 * TSC frequency doesn't match the one we want.
580 */
581 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
582 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
583 -ENOTSUP;
584 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
585 error_report("warning: TSC frequency mismatch between "
d6276d26
EH		 586 "VM (%" PRId64 " kHz) and host (%d kHz), "
587 "and TSC scaling unavailable",
588 env->tsc_khz, cur_freq);
5031283d
HZ		 589 return r;
590 }
591 }
592
593 return 0;
594}
595
c35bd19a
EY		 596static int hyperv_handle_properties(CPUState *cs)
597{
598 X86CPU *cpu = X86_CPU(cs);
599 CPUX86State *env = &cpu->env;
600
3ddcd2ed
EH		 601 if (cpu->hyperv_time &&
602 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
603 cpu->hyperv_time = false;
604 }
605
c35bd19a
EY		 606 if (cpu->hyperv_relaxed_timing) {
607 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
608 }
609 if (cpu->hyperv_vapic) {
610 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
611 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
c35bd19a 612 }
3ddcd2ed 613 if (cpu->hyperv_time) {
c35bd19a
EY		 614 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
615 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
616 env->features[FEAT_HYPERV_EAX] |= 0x200;
c35bd19a
EY		 617 }
618 if (cpu->hyperv_crash && has_msr_hv_crash) {
619 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
620 }
621 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
622 if (cpu->hyperv_reset && has_msr_hv_reset) {
623 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
624 }
625 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
626 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
627 }
628 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
629 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
630 }
631 if (cpu->hyperv_synic) {
632 int sint;
633
634 if (!has_msr_hv_synic ||
635 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
636 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
637 return -ENOSYS;
638 }
639
640 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
641 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
642 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
643 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
644 }
645 }
646 if (cpu->hyperv_stimer) {
647 if (!has_msr_hv_stimer) {
648 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
649 return -ENOSYS;
650 }
651 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
652 }
653 return 0;
654}
655
68bfd0ad
MT		 656static Error *invtsc_mig_blocker;
657
f8bb0565 658#define KVM_MAX_CPUID_ENTRIES 100
0893d460 659
20d695a9 660int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 661{
662 struct {
486bd5a2 663 struct kvm_cpuid2 cpuid;
f8bb0565 664 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 665 } QEMU_PACKED cpuid_data;
20d695a9
AF		 666 X86CPU *cpu = X86_CPU(cs);
667 CPUX86State *env = &cpu->env;
486bd5a2 668 uint32_t limit, i, j, cpuid_i;
a33609ca 669 uint32_t unused;
bb0300dc 670 struct kvm_cpuid_entry2 *c;
bb0300dc 671 uint32_t signature[3];
234cc647 672 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 673 int r;
05330448 674
ef4cbe14
SW		 675 memset(&cpuid_data, 0, sizeof(cpuid_data));
676
05330448
AL		 677 cpuid_i = 0;
678
bb0300dc 679 /* Paravirtualization CPUIDs */
234cc647
PB		 680 if (hyperv_enabled(cpu)) {
681 c = &cpuid_data.entries[cpuid_i++];
682 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 683 if (!cpu->hyperv_vendor_id) {
684 memcpy(signature, "Microsoft Hv", 12);
685 } else {
686 size_t len = strlen(cpu->hyperv_vendor_id);
687
688 if (len > 12) {
689 error_report("hv-vendor-id truncated to 12 characters");
690 len = 12;
691 }
692 memset(signature, 0, 12);
693 memcpy(signature, cpu->hyperv_vendor_id, len);
694 }
eab70139 695 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 696 c->ebx = signature[0];
697 c->ecx = signature[1];
698 c->edx = signature[2];
0c31b744 699
234cc647
PB		 700 c = &cpuid_data.entries[cpuid_i++];
701 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 702 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
703 c->eax = signature[0];
234cc647
PB		 704 c->ebx = 0;
705 c->ecx = 0;
706 c->edx = 0;
eab70139
VR		 707
708 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 709 c->function = HYPERV_CPUID_VERSION;
710 c->eax = 0x00001bbc;
711 c->ebx = 0x00060001;
712
713 c = &cpuid_data.entries[cpuid_i++];
eab70139 714 c->function = HYPERV_CPUID_FEATURES;
c35bd19a
EY		 715 r = hyperv_handle_properties(cs);
716 if (r) {
717 return r;
46eb8f98 718 }
c35bd19a
EY		 719 c->eax = env->features[FEAT_HYPERV_EAX];
720 c->ebx = env->features[FEAT_HYPERV_EBX];
721 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 722
eab70139 723 c = &cpuid_data.entries[cpuid_i++];
eab70139 724 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 725 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 726 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
727 }
2d5aa872 728 if (cpu->hyperv_vapic) {
eab70139
VR		 729 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
730 }
92067bf4 731 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 732
733 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 734 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
735 c->eax = 0x40;
736 c->ebx = 0x40;
737
234cc647 738 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 739 has_msr_hv_hypercall = true;
eab70139
VR		 740 }
741
f522d2ac
AW		 742 if (cpu->expose_kvm) {
743 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
744 c = &cpuid_data.entries[cpuid_i++];
745 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 746 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 747 c->ebx = signature[0];
748 c->ecx = signature[1];
749 c->edx = signature[2];
234cc647 750
f522d2ac
AW		 751 c = &cpuid_data.entries[cpuid_i++];
752 c->function = KVM_CPUID_FEATURES | kvm_base;
753 c->eax = env->features[FEAT_KVM];
f522d2ac 754 }
917367aa 755
a33609ca 756 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 757
758 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 759 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
760 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
761 abort();
762 }
bb0300dc 763 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 764
765 switch (i) {
a36b1029
AL		 766 case 2: {
767 /* Keep reading function 2 till all the input is received */
768 int times;
769
a36b1029 770 c->function = i;
a33609ca
AL		 771 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
772 KVM_CPUID_FLAG_STATE_READ_NEXT;
773 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
774 times = c->eax & 0xff;
a36b1029
AL		 775
776 for (j = 1; j < times; ++j) {
f8bb0565
IM		 777 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
778 fprintf(stderr, "cpuid_data is full, no space for "
779 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
780 abort();
781 }
a33609ca 782 c = &cpuid_data.entries[cpuid_i++];
a36b1029 783 c->function = i;
a33609ca
AL		 784 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
785 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 786 }
787 break;
788 }
486bd5a2
AL		 789 case 4:
790 case 0xb:
791 case 0xd:
792 for (j = 0; ; j++) {
31e8c696
AP		 793 if (i == 0xd && j == 64) {
794 break;
795 }
486bd5a2
AL		 796 c->function = i;
797 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
798 c->index = j;
a33609ca 799 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 800
b9bec74b 801 if (i == 4 && c->eax == 0) {
486bd5a2 802 break;
b9bec74b
JK		 803 }
804 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 805 break;
b9bec74b
JK		 806 }
807 if (i == 0xd && c->eax == 0) {
31e8c696 808 continue;
b9bec74b 809 }
f8bb0565
IM		 810 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
811 fprintf(stderr, "cpuid_data is full, no space for "
812 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
813 abort();
814 }
a33609ca 815 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 816 }
817 break;
818 default:
486bd5a2 819 c->function = i;
a33609ca
AL		 820 c->flags = 0;
821 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 822 break;
823 }
05330448 824 }
0d894367
PB		 825
826 if (limit >= 0x0a) {
827 uint32_t ver;
828
829 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
830 if ((ver & 0xff) > 0) {
831 has_msr_architectural_pmu = true;
832 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
833
834 /* Shouldn't be more than 32, since that's the number of bits
835 * available in EBX to tell us _which_ counters are available.
836 * Play it safe.
837 */
838 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
839 num_architectural_pmu_counters = MAX_GP_COUNTERS;
840 }
841 }
842 }
843
a33609ca 844 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 845
846 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 847 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
848 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
849 abort();
850 }
bb0300dc 851 c = &cpuid_data.entries[cpuid_i++];
05330448 852
05330448 853 c->function = i;
a33609ca
AL		 854 c->flags = 0;
855 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 856 }
857
b3baa152
BW		 858 /* Call Centaur's CPUID instructions they are supported. */
859 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 860 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
861
862 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 863 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
864 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
865 abort();
866 }
b3baa152
BW		 867 c = &cpuid_data.entries[cpuid_i++];
868
869 c->function = i;
870 c->flags = 0;
871 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
872 }
873 }
874
05330448
AL		 875 cpuid_data.cpuid.nent = cpuid_i;
876
e7701825 877 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 878 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 879 (CPUID_MCE | CPUID_MCA)
a60f24b5 880 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 881 uint64_t mcg_cap, unsupported_caps;
e7701825 882 int banks;
32a42024 883 int ret;
e7701825 884
a60f24b5 885 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 886 if (ret < 0) {
887 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
888 return ret;
e7701825 889 }
75d49497 890
2590f15b 891 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 892 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 893 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 894 return -ENOTSUP;
75d49497 895 }
49b69cbf 896
5120901a
EH		 897 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
898 if (unsupported_caps) {
87f8b626
AR		 899 if (unsupported_caps & MCG_LMCE_P) {
900 error_report("kvm: LMCE not supported");
901 return -ENOTSUP;
902 }
5120901a
EH		 903 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
904 unsupported_caps);
905 }
906
2590f15b
EH		 907 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
908 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 909 if (ret < 0) {
910 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
911 return ret;
912 }
e7701825 913 }
e7701825 914
b8cc45d6
GC		 915 qemu_add_vm_change_state_handler(cpu_update_state, env);
916
df67696e
LJ		 917 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
918 if (c) {
919 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
920 !!(c->ecx & CPUID_EXT_SMX);
921 }
922
87f8b626
AR		 923 if (env->mcg_cap & MCG_LMCE_P) {
924 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
925 }
926
68bfd0ad
MT		 927 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
928 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
929 /* for migration */
930 error_setg(&invtsc_mig_blocker,
931 "State blocked by non-migratable CPU device"
932 " (invtsc flag)");
933 migrate_add_blocker(invtsc_mig_blocker);
934 /* for savevm */
935 vmstate_x86_cpu.unmigratable = 1;
936 }
937
7e680753 938 cpuid_data.cpuid.padding = 0;
1bc22652 939 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a
JK		 940 if (r) {
941 return r;
942 }
e7429073 943
5031283d
HZ		 944 r = kvm_arch_set_tsc_khz(cs);
945 if (r < 0) {
946 return r;
e7429073 947 }
e7429073 948
bcffbeeb
HZ		 949 /* vcpu's TSC frequency is either specified by user, or following
950 * the value used by KVM if the former is not present. In the
951 * latter case, we query it from KVM and record in env->tsc_khz,
952 * so that vcpu's TSC frequency can be migrated later via this field.
953 */
954 if (!env->tsc_khz) {
955 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
956 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
957 -ENOTSUP;
958 if (r > 0) {
959 env->tsc_khz = r;
960 }
961 }
962
28143b40 963 if (has_xsave) {
fabacc0f
JK		 964 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
965 }
d71b62a1 966 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 967
273c515c
PB		 968 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
969 has_msr_tsc_aux = false;
970 }
d1ae67f6 971
e7429073 972 return 0;
05330448
AL		 973}
974
50a2c6e5 975void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 976{
20d695a9 977 CPUX86State *env = &cpu->env;
dd673288 978
e73223a5 979 env->exception_injected = -1;
0e607a80 980 env->interrupt_injected = -1;
1a5e9d2f 981 env->xcr0 = 1;
ddced198 982 if (kvm_irqchip_in_kernel()) {
dd673288 983 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 984 KVM_MP_STATE_UNINITIALIZED;
985 } else {
986 env->mp_state = KVM_MP_STATE_RUNNABLE;
987 }
caa5af0f
JK		 988}
989
e0723c45
PB		 990void kvm_arch_do_init_vcpu(X86CPU *cpu)
991{
992 CPUX86State *env = &cpu->env;
993
994 /* APs get directly into wait-for-SIPI state. */
995 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
996 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
997 }
998}
999
c3a3a7d3 1000static int kvm_get_supported_msrs(KVMState *s)
05330448 1001{
75b10c43 1002 static int kvm_supported_msrs;
c3a3a7d3 1003 int ret = 0;
05330448
AL		 1004
1005 /* first time */
75b10c43 1006 if (kvm_supported_msrs == 0) {
05330448
AL		 1007 struct kvm_msr_list msr_list, *kvm_msr_list;
1008
75b10c43 1009 kvm_supported_msrs = -1;
05330448
AL		 1010
1011 /* Obtain MSR list from KVM. These are the MSRs that we must
1012 * save/restore */
4c9f7372 1013 msr_list.nmsrs = 0;
c3a3a7d3 1014 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1015 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1016 return ret;
6fb6d245 1017 }
d9db889f
JK		 1018 /* Old kernel modules had a bug and could write beyond the provided
1019 memory. Allocate at least a safe amount of 1K. */
7267c094 1020 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1021 msr_list.nmsrs *
1022 sizeof(msr_list.indices[0])));
05330448 1023
55308450 1024 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1025 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1026 if (ret >= 0) {
1027 int i;
1028
1029 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1030 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 1031 has_msr_star = true;
75b10c43
MT		 1032 continue;
1033 }
1034 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 1035 has_msr_hsave_pa = true;
75b10c43 1036 continue;
05330448 1037 }
c9b8f6b6
AS		 1038 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1039 has_msr_tsc_aux = true;
1040 continue;
1041 }
f28558d3
WA		 1042 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1043 has_msr_tsc_adjust = true;
1044 continue;
1045 }
aa82ba54
LJ		 1046 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1047 has_msr_tsc_deadline = true;
1048 continue;
1049 }
fc12d72e
PB		 1050 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1051 has_msr_smbase = true;
1052 continue;
1053 }
21e87c46
AK		 1054 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1055 has_msr_misc_enable = true;
1056 continue;
1057 }
79e9ebeb
LJ		 1058 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1059 has_msr_bndcfgs = true;
1060 continue;
1061 }
18cd2c17
WL		 1062 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1063 has_msr_xss = true;
1064 continue;
1065 }
f2a53c9e
AS		 1066 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1067 has_msr_hv_crash = true;
1068 continue;
1069 }
744b8a94
AS		 1070 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1071 has_msr_hv_reset = true;
1072 continue;
1073 }
8c145d7c
AS		 1074 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1075 has_msr_hv_vpindex = true;
1076 continue;
1077 }
46eb8f98
AS		 1078 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1079 has_msr_hv_runtime = true;
1080 continue;
1081 }
866eea9a
AS		 1082 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1083 has_msr_hv_synic = true;
1084 continue;
1085 }
ff99aa64
AS		 1086 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1087 has_msr_hv_stimer = true;
1088 continue;
1089 }
05330448
AL		 1090 }
1091 }
1092
7267c094 1093 g_free(kvm_msr_list);
05330448
AL		 1094 }
1095
c3a3a7d3 1096 return ret;
05330448
AL		 1097}
1098
6410848b
PB		 1099static Notifier smram_machine_done;
1100static KVMMemoryListener smram_listener;
1101static AddressSpace smram_address_space;
1102static MemoryRegion smram_as_root;
1103static MemoryRegion smram_as_mem;
1104
1105static void register_smram_listener(Notifier *n, void *unused)
1106{
1107 MemoryRegion *smram =
1108 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1109
1110 /* Outer container... */
1111 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1112 memory_region_set_enabled(&smram_as_root, true);
1113
1114 /* ... with two regions inside: normal system memory with low
1115 * priority, and...
1116 */
1117 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1118 get_system_memory(), 0, ~0ull);
1119 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1120 memory_region_set_enabled(&smram_as_mem, true);
1121
1122 if (smram) {
1123 /* ... SMRAM with higher priority */
1124 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1125 memory_region_set_enabled(smram, true);
1126 }
1127
1128 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1129 kvm_memory_listener_register(kvm_state, &smram_listener,
1130 &smram_address_space, 1);
1131}
1132
b16565b3 1133int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1134{
11076198 1135 uint64_t identity_base = 0xfffbc000;
39d6960a 1136 uint64_t shadow_mem;
20420430 1137 int ret;
25d2e361 1138 struct utsname utsname;
20420430 1139
28143b40
TH		 1140#ifdef KVM_CAP_XSAVE
1141 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1142#endif
1143
1144#ifdef KVM_CAP_XCRS
1145 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1146#endif
1147
1148#ifdef KVM_CAP_PIT_STATE2
1149 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1150#endif
1151
c3a3a7d3 1152 ret = kvm_get_supported_msrs(s);
20420430 1153 if (ret < 0) {
20420430
SY		 1154 return ret;
1155 }
25d2e361
MT		 1156
1157 uname(&utsname);
1158 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1159
4c5b10b7 1160 /*
11076198
JK		 1161 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1162 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1163 * Since these must be part of guest physical memory, we need to allocate
1164 * them, both by setting their start addresses in the kernel and by
1165 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1166 *
1167 * Older KVM versions may not support setting the identity map base. In
1168 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1169 * size.
4c5b10b7 1170 */
11076198
JK		 1171 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1172 /* Allows up to 16M BIOSes. */
1173 identity_base = 0xfeffc000;
1174
1175 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1176 if (ret < 0) {
1177 return ret;
1178 }
4c5b10b7 1179 }
e56ff191 1180
11076198
JK		 1181 /* Set TSS base one page after EPT identity map. */
1182 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1183 if (ret < 0) {
1184 return ret;
1185 }
1186
11076198
JK		 1187 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1188 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1189 if (ret < 0) {
11076198 1190 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1191 return ret;
1192 }
3c85e74f 1193 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1194
4689b77b 1195 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1196 if (shadow_mem != -1) {
1197 shadow_mem /= 4096;
1198 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1199 if (ret < 0) {
1200 return ret;
39d6960a
JK		 1201 }
1202 }
6410848b
PB		 1203
1204 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1205 smram_machine_done.notify = register_smram_listener;
1206 qemu_add_machine_init_done_notifier(&smram_machine_done);
1207 }
11076198 1208 return 0;
05330448 1209}
b9bec74b 1210
05330448
AL		 1211static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1212{
1213 lhs->selector = rhs->selector;
1214 lhs->base = rhs->base;
1215 lhs->limit = rhs->limit;
1216 lhs->type = 3;
1217 lhs->present = 1;
1218 lhs->dpl = 3;
1219 lhs->db = 0;
1220 lhs->s = 1;
1221 lhs->l = 0;
1222 lhs->g = 0;
1223 lhs->avl = 0;
1224 lhs->unusable = 0;
1225}
1226
1227static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1228{
1229 unsigned flags = rhs->flags;
1230 lhs->selector = rhs->selector;
1231 lhs->base = rhs->base;
1232 lhs->limit = rhs->limit;
1233 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1234 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1235 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1236 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1237 lhs->s = (flags & DESC_S_MASK) != 0;
1238 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1239 lhs->g = (flags & DESC_G_MASK) != 0;
1240 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1241 lhs->unusable = !lhs->present;
7e680753 1242 lhs->padding = 0;
05330448
AL		 1243}
1244
1245static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1246{
1247 lhs->selector = rhs->selector;
1248 lhs->base = rhs->base;
1249 lhs->limit = rhs->limit;
4cae9c97
MC		 1250 if (rhs->unusable) {
1251 lhs->flags = 0;
1252 } else {
1253 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1254 (rhs->present * DESC_P_MASK) |
1255 (rhs->dpl << DESC_DPL_SHIFT) |
1256 (rhs->db << DESC_B_SHIFT) |
1257 (rhs->s * DESC_S_MASK) |
1258 (rhs->l << DESC_L_SHIFT) |
1259 (rhs->g * DESC_G_MASK) |
1260 (rhs->avl * DESC_AVL_MASK);
1261 }
05330448
AL		 1262}
1263
1264static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1265{
b9bec74b 1266 if (set) {
05330448 1267 *kvm_reg = *qemu_reg;
b9bec74b 1268 } else {
05330448 1269 *qemu_reg = *kvm_reg;
b9bec74b 1270 }
05330448
AL		 1271}
1272
1bc22652 1273static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1274{
1bc22652 1275 CPUX86State *env = &cpu->env;
05330448
AL		 1276 struct kvm_regs regs;
1277 int ret = 0;
1278
1279 if (!set) {
1bc22652 1280 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1281 if (ret < 0) {
05330448 1282 return ret;
b9bec74b 1283 }
05330448
AL		 1284 }
1285
1286 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1287 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1288 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1289 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1290 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1291 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1292 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1293 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1294#ifdef TARGET_X86_64
1295 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1296 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1297 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1298 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1299 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1300 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1301 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1302 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1303#endif
1304
1305 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1306 kvm_getput_reg(&regs.rip, &env->eip, set);
1307
b9bec74b 1308 if (set) {
1bc22652 1309 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1310 }
05330448
AL		 1311
1312 return ret;
1313}
1314
1bc22652 1315static int kvm_put_fpu(X86CPU *cpu)
05330448 1316{
1bc22652 1317 CPUX86State *env = &cpu->env;
05330448
AL		 1318 struct kvm_fpu fpu;
1319 int i;
1320
1321 memset(&fpu, 0, sizeof fpu);
1322 fpu.fsw = env->fpus & ~(7 << 11);
1323 fpu.fsw |= (env->fpstt & 7) << 11;
1324 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1325 fpu.last_opcode = env->fpop;
1326 fpu.last_ip = env->fpip;
1327 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1328 for (i = 0; i < 8; ++i) {
1329 fpu.ftwx |= (!env->fptags[i]) << i;
1330 }
05330448 1331 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1332 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1333 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1334 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1335 }
05330448
AL		 1336 fpu.mxcsr = env->mxcsr;
1337
1bc22652 1338 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1339}
1340
6b42494b
JK		 1341#define XSAVE_FCW_FSW 0
1342#define XSAVE_FTW_FOP 1
f1665b21
SY		 1343#define XSAVE_CWD_RIP 2
1344#define XSAVE_CWD_RDP 4
1345#define XSAVE_MXCSR 6
1346#define XSAVE_ST_SPACE 8
1347#define XSAVE_XMM_SPACE 40
1348#define XSAVE_XSTATE_BV 128
1349#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1350#define XSAVE_BNDREGS 240
1351#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1352#define XSAVE_OPMASK 272
1353#define XSAVE_ZMM_Hi256 288
1354#define XSAVE_Hi16_ZMM 416
f74eefe0 1355#define XSAVE_PKRU 672
f1665b21 1356
b503717d
EH		 1357#define XSAVE_BYTE_OFFSET(word_offset) \
1358 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1359
1360#define ASSERT_OFFSET(word_offset, field) \
1361 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1362 offsetof(X86XSaveArea, field))
1363
1364ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1365ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1366ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1367ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1368ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1369ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1370ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1371ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1372ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1373ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1374ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1375ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1376ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1377ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1378ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1379
1bc22652 1380static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1381{
1bc22652 1382 CPUX86State *env = &cpu->env;
86cd2ea0 1383 X86XSaveArea *xsave = env->kvm_xsave_buf;
42cc8fa6 1384 uint16_t cwd, swd, twd;
9be38598 1385 int i;
f1665b21 1386
28143b40 1387 if (!has_xsave) {
1bc22652 1388 return kvm_put_fpu(cpu);
b9bec74b 1389 }
f1665b21 1390
f1665b21 1391 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1392 twd = 0;
f1665b21
SY		 1393 swd = env->fpus & ~(7 << 11);
1394 swd |= (env->fpstt & 7) << 11;
1395 cwd = env->fpuc;
b9bec74b 1396 for (i = 0; i < 8; ++i) {
f1665b21 1397 twd |= (!env->fptags[i]) << i;
b9bec74b 1398 }
86cd2ea0
EH		 1399 xsave->legacy.fcw = cwd;
1400 xsave->legacy.fsw = swd;
1401 xsave->legacy.ftw = twd;
1402 xsave->legacy.fpop = env->fpop;
1403 xsave->legacy.fpip = env->fpip;
1404 xsave->legacy.fpdp = env->fpdp;
1405 memcpy(&xsave->legacy.fpregs, env->fpregs,
f1665b21 1406 sizeof env->fpregs);
86cd2ea0
EH		 1407 xsave->legacy.mxcsr = env->mxcsr;
1408 xsave->header.xstate_bv = env->xstate_bv;
1409 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
79e9ebeb 1410 sizeof env->bnd_regs);
86cd2ea0
EH		 1411 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1412 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
9aecd6f8 1413 sizeof env->opmask_regs);
bee81887 1414
86cd2ea0
EH		 1415 for (i = 0; i < CPU_NB_REGS; i++) {
1416 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1417 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1418 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1419 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1420 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1421 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1422 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1423 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1424 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1425 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1426 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
bee81887
PB		 1427 }
1428
9aecd6f8 1429#ifdef TARGET_X86_64
86cd2ea0 1430 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
b7711471 1431 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1432 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
9aecd6f8 1433#endif
9be38598 1434 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1435}
1436
1bc22652 1437static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1438{
1bc22652 1439 CPUX86State *env = &cpu->env;
bdfc8480 1440 struct kvm_xcrs xcrs = {};
f1665b21 1441
28143b40 1442 if (!has_xcrs) {
f1665b21 1443 return 0;
b9bec74b 1444 }
f1665b21
SY		 1445
1446 xcrs.nr_xcrs = 1;
1447 xcrs.flags = 0;
1448 xcrs.xcrs[0].xcr = 0;
1449 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1450 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1451}
1452
1bc22652 1453static int kvm_put_sregs(X86CPU *cpu)
05330448 1454{
1bc22652 1455 CPUX86State *env = &cpu->env;
05330448
AL		 1456 struct kvm_sregs sregs;
1457
0e607a80
JK		 1458 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1459 if (env->interrupt_injected >= 0) {
1460 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1461 (uint64_t)1 << (env->interrupt_injected % 64);
1462 }
05330448
AL		 1463
1464 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1465 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1466 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1467 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1468 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1469 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1470 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1471 } else {
b9bec74b
JK		 1472 set_seg(&sregs.cs, &env->segs[R_CS]);
1473 set_seg(&sregs.ds, &env->segs[R_DS]);
1474 set_seg(&sregs.es, &env->segs[R_ES]);
1475 set_seg(&sregs.fs, &env->segs[R_FS]);
1476 set_seg(&sregs.gs, &env->segs[R_GS]);
1477 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1478 }
1479
1480 set_seg(&sregs.tr, &env->tr);
1481 set_seg(&sregs.ldt, &env->ldt);
1482
1483 sregs.idt.limit = env->idt.limit;
1484 sregs.idt.base = env->idt.base;
7e680753 1485 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1486 sregs.gdt.limit = env->gdt.limit;
1487 sregs.gdt.base = env->gdt.base;
7e680753 1488 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1489
1490 sregs.cr0 = env->cr[0];
1491 sregs.cr2 = env->cr[2];
1492 sregs.cr3 = env->cr[3];
1493 sregs.cr4 = env->cr[4];
1494
02e51483
CF		 1495 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1496 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1497
1498 sregs.efer = env->efer;
1499
1bc22652 1500 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1501}
1502
d71b62a1
EH		 1503static void kvm_msr_buf_reset(X86CPU *cpu)
1504{
1505 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1506}
1507
9c600a84
EH		 1508static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1509{
1510 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1511 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1512 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1513
1514 assert((void *)(entry + 1) <= limit);
1515
1abc2cae
EH		 1516 entry->index = index;
1517 entry->reserved = 0;
1518 entry->data = value;
9c600a84
EH		 1519 msrs->nmsrs++;
1520}
1521
73e1b8f2
PB		 1522static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1523{
1524 kvm_msr_buf_reset(cpu);
1525 kvm_msr_entry_add(cpu, index, value);
1526
1527 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1528}
1529
f8d9ccf8
DDAG		 1530void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1531{
1532 int ret;
1533
1534 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1535 assert(ret == 1);
1536}
1537
7477cd38
MT		 1538static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1539{
1540 CPUX86State *env = &cpu->env;
48e1a45c 1541 int ret;
7477cd38
MT		 1542
1543 if (!has_msr_tsc_deadline) {
1544 return 0;
1545 }
1546
73e1b8f2 1547 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1548 if (ret < 0) {
1549 return ret;
1550 }
1551
1552 assert(ret == 1);
1553 return 0;
7477cd38
MT		 1554}
1555
6bdf863d
JK		 1556/*
1557 * Provide a separate write service for the feature control MSR in order to
1558 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1559 * before writing any other state because forcibly leaving nested mode
1560 * invalidates the VCPU state.
1561 */
1562static int kvm_put_msr_feature_control(X86CPU *cpu)
1563{
48e1a45c
PB		 1564 int ret;
1565
1566 if (!has_msr_feature_control) {
1567 return 0;
1568 }
6bdf863d 1569
73e1b8f2
PB		 1570 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1571 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1572 if (ret < 0) {
1573 return ret;
1574 }
1575
1576 assert(ret == 1);
1577 return 0;
6bdf863d
JK		 1578}
1579
1bc22652 1580static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1581{
1bc22652 1582 CPUX86State *env = &cpu->env;
9c600a84 1583 int i;
48e1a45c 1584 int ret;
05330448 1585
d71b62a1
EH		 1586 kvm_msr_buf_reset(cpu);
1587
9c600a84
EH		 1588 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1589 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1590 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1591 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1592 if (has_msr_star) {
9c600a84 1593 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1594 }
c3a3a7d3 1595 if (has_msr_hsave_pa) {
9c600a84 1596 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1597 }
c9b8f6b6 1598 if (has_msr_tsc_aux) {
9c600a84 1599 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1600 }
f28558d3 1601 if (has_msr_tsc_adjust) {
9c600a84 1602 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1603 }
21e87c46 1604 if (has_msr_misc_enable) {
9c600a84 1605 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1606 env->msr_ia32_misc_enable);
1607 }
fc12d72e 1608 if (has_msr_smbase) {
9c600a84 1609 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1610 }
439d19f2 1611 if (has_msr_bndcfgs) {
9c600a84 1612 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1613 }
18cd2c17 1614 if (has_msr_xss) {
9c600a84 1615 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1616 }
05330448 1617#ifdef TARGET_X86_64
25d2e361 1618 if (lm_capable_kernel) {
9c600a84
EH		 1619 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1620 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1621 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1622 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1623 }
05330448 1624#endif
ff5c186b 1625 /*
0d894367
PB		 1626 * The following MSRs have side effects on the guest or are too heavy
1627 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1628 */
1629 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1630 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1631 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1632 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1633 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1634 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1635 }
55c911a5 1636 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1637 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1638 }
55c911a5 1639 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1640 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1641 }
0d894367
PB		 1642 if (has_msr_architectural_pmu) {
1643 /* Stop the counter. */
9c600a84
EH		 1644 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1645 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1646
1647 /* Set the counter values. */
1648 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1649 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1650 env->msr_fixed_counters[i]);
1651 }
1652 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1653 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1654 env->msr_gp_counters[i]);
9c600a84 1655 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1656 env->msr_gp_evtsel[i]);
1657 }
9c600a84 1658 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1659 env->msr_global_status);
9c600a84 1660 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1661 env->msr_global_ovf_ctrl);
1662
1663 /* Now start the PMU. */
9c600a84 1664 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1665 env->msr_fixed_ctr_ctrl);
9c600a84 1666 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1667 env->msr_global_ctrl);
1668 }
7bc3d711 1669 if (has_msr_hv_hypercall) {
9c600a84 1670 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1671 env->msr_hv_guest_os_id);
9c600a84 1672 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1673 env->msr_hv_hypercall);
eab70139 1674 }
2d5aa872 1675 if (cpu->hyperv_vapic) {
9c600a84 1676 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1677 env->msr_hv_vapic);
eab70139 1678 }
3ddcd2ed 1679 if (cpu->hyperv_time) {
9c600a84 1680 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1681 }
f2a53c9e
AS		 1682 if (has_msr_hv_crash) {
1683 int j;
1684
1685 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
9c600a84 1686 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1687 env->msr_hv_crash_params[j]);
1688
9c600a84 1689 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
f2a53c9e
AS		 1690 HV_X64_MSR_CRASH_CTL_NOTIFY);
1691 }
46eb8f98 1692 if (has_msr_hv_runtime) {
9c600a84 1693 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1694 }
866eea9a
AS		 1695 if (cpu->hyperv_synic) {
1696 int j;
1697
9c600a84 1698 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1699 env->msr_hv_synic_control);
9c600a84 1700 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1701 env->msr_hv_synic_version);
9c600a84 1702 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1703 env->msr_hv_synic_evt_page);
9c600a84 1704 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1705 env->msr_hv_synic_msg_page);
1706
1707 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1708 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1709 env->msr_hv_synic_sint[j]);
1710 }
1711 }
ff99aa64
AS		 1712 if (has_msr_hv_stimer) {
1713 int j;
1714
1715 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1716 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1717 env->msr_hv_stimer_config[j]);
1718 }
1719
1720 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1721 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1722 env->msr_hv_stimer_count[j]);
1723 }
1724 }
1eabfce6 1725 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1726 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1727
9c600a84
EH		 1728 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1729 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1730 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1731 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1732 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1733 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1734 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1735 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1736 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1737 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1738 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1739 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1740 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1741 /* The CPU GPs if we write to a bit above the physical limit of
1742 * the host CPU (and KVM emulates that)
1743 */
1744 uint64_t mask = env->mtrr_var[i].mask;
1745 mask &= phys_mask;
1746
9c600a84
EH		 1747 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1748 env->mtrr_var[i].base);
112dad69 1749 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1750 }
1751 }
6bdf863d
JK		 1752
1753 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1754 * kvm_put_msr_feature_control. */
ea643051 1755 }
57780495 1756 if (env->mcg_cap) {
d8da8574 1757 int i;
b9bec74b 1758
9c600a84
EH		 1759 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1760 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1761 if (has_msr_mcg_ext_ctl) {
1762 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1763 }
c34d440a 1764 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1765 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1766 }
1767 }
1a03675d 1768
d71b62a1 1769 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1770 if (ret < 0) {
1771 return ret;
1772 }
05330448 1773
9c600a84 1774 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1775 return 0;
05330448
AL		 1776}
1777
1778
1bc22652 1779static int kvm_get_fpu(X86CPU *cpu)
05330448 1780{
1bc22652 1781 CPUX86State *env = &cpu->env;
05330448
AL		 1782 struct kvm_fpu fpu;
1783 int i, ret;
1784
1bc22652 1785 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1786 if (ret < 0) {
05330448 1787 return ret;
b9bec74b 1788 }
05330448
AL		 1789
1790 env->fpstt = (fpu.fsw >> 11) & 7;
1791 env->fpus = fpu.fsw;
1792 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1793 env->fpop = fpu.last_opcode;
1794 env->fpip = fpu.last_ip;
1795 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1796 for (i = 0; i < 8; ++i) {
1797 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1798 }
05330448 1799 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1800 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1801 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1802 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1803 }
05330448
AL		 1804 env->mxcsr = fpu.mxcsr;
1805
1806 return 0;
1807}
1808
1bc22652 1809static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1810{
1bc22652 1811 CPUX86State *env = &cpu->env;
86cd2ea0 1812 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1813 int ret, i;
42cc8fa6 1814 uint16_t cwd, swd, twd;
f1665b21 1815
28143b40 1816 if (!has_xsave) {
1bc22652 1817 return kvm_get_fpu(cpu);
b9bec74b 1818 }
f1665b21 1819
1bc22652 1820 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1821 if (ret < 0) {
f1665b21 1822 return ret;
0f53994f 1823 }
f1665b21 1824
86cd2ea0
EH		 1825 cwd = xsave->legacy.fcw;
1826 swd = xsave->legacy.fsw;
1827 twd = xsave->legacy.ftw;
1828 env->fpop = xsave->legacy.fpop;
f1665b21
SY		 1829 env->fpstt = (swd >> 11) & 7;
1830 env->fpus = swd;
1831 env->fpuc = cwd;
b9bec74b 1832 for (i = 0; i < 8; ++i) {
f1665b21 1833 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1834 }
86cd2ea0
EH		 1835 env->fpip = xsave->legacy.fpip;
1836 env->fpdp = xsave->legacy.fpdp;
1837 env->mxcsr = xsave->legacy.mxcsr;
1838 memcpy(env->fpregs, &xsave->legacy.fpregs,
f1665b21 1839 sizeof env->fpregs);
86cd2ea0
EH		 1840 env->xstate_bv = xsave->header.xstate_bv;
1841 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
79e9ebeb 1842 sizeof env->bnd_regs);
86cd2ea0
EH		 1843 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1844 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
9aecd6f8 1845 sizeof env->opmask_regs);
bee81887 1846
86cd2ea0
EH		 1847 for (i = 0; i < CPU_NB_REGS; i++) {
1848 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1849 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1850 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1851 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1852 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1853 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1854 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1855 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1856 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1857 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1858 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1859 }
1860
9aecd6f8 1861#ifdef TARGET_X86_64
86cd2ea0 1862 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
b7711471 1863 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1864 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
9aecd6f8 1865#endif
f1665b21 1866 return 0;
f1665b21
SY		 1867}
1868
1bc22652 1869static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1870{
1bc22652 1871 CPUX86State *env = &cpu->env;
f1665b21
SY		 1872 int i, ret;
1873 struct kvm_xcrs xcrs;
1874
28143b40 1875 if (!has_xcrs) {
f1665b21 1876 return 0;
b9bec74b 1877 }
f1665b21 1878
1bc22652 1879 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1880 if (ret < 0) {
f1665b21 1881 return ret;
b9bec74b 1882 }
f1665b21 1883
b9bec74b 1884 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1885 /* Only support xcr0 now */
0fd53fec
PB		 1886 if (xcrs.xcrs[i].xcr == 0) {
1887 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1888 break;
1889 }
b9bec74b 1890 }
f1665b21 1891 return 0;
f1665b21
SY		 1892}
1893
1bc22652 1894static int kvm_get_sregs(X86CPU *cpu)
05330448 1895{
1bc22652 1896 CPUX86State *env = &cpu->env;
05330448
AL		 1897 struct kvm_sregs sregs;
1898 uint32_t hflags;
0e607a80 1899 int bit, i, ret;
05330448 1900
1bc22652 1901 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1902 if (ret < 0) {
05330448 1903 return ret;
b9bec74b 1904 }
05330448 1905
0e607a80
JK		 1906 /* There can only be one pending IRQ set in the bitmap at a time, so try
1907 to find it and save its number instead (-1 for none). */
1908 env->interrupt_injected = -1;
1909 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1910 if (sregs.interrupt_bitmap[i]) {
1911 bit = ctz64(sregs.interrupt_bitmap[i]);
1912 env->interrupt_injected = i * 64 + bit;
1913 break;
1914 }
1915 }
05330448
AL		 1916
1917 get_seg(&env->segs[R_CS], &sregs.cs);
1918 get_seg(&env->segs[R_DS], &sregs.ds);
1919 get_seg(&env->segs[R_ES], &sregs.es);
1920 get_seg(&env->segs[R_FS], &sregs.fs);
1921 get_seg(&env->segs[R_GS], &sregs.gs);
1922 get_seg(&env->segs[R_SS], &sregs.ss);
1923
1924 get_seg(&env->tr, &sregs.tr);
1925 get_seg(&env->ldt, &sregs.ldt);
1926
1927 env->idt.limit = sregs.idt.limit;
1928 env->idt.base = sregs.idt.base;
1929 env->gdt.limit = sregs.gdt.limit;
1930 env->gdt.base = sregs.gdt.base;
1931
1932 env->cr[0] = sregs.cr0;
1933 env->cr[2] = sregs.cr2;
1934 env->cr[3] = sregs.cr3;
1935 env->cr[4] = sregs.cr4;
1936
05330448 1937 env->efer = sregs.efer;
cce47516
JK		 1938
1939 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1940
b9bec74b
JK		 1941#define HFLAG_COPY_MASK \
1942 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1943 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1944 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1945 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1946
19dc85db
RH		 1947 hflags = env->hflags & HFLAG_COPY_MASK;
1948 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1949 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1950 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1951 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 1952 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 1953
1954 if (env->cr[4] & CR4_OSFXSR_MASK) {
1955 hflags |= HF_OSFXSR_MASK;
1956 }
05330448
AL		 1957
1958 if (env->efer & MSR_EFER_LMA) {
1959 hflags |= HF_LMA_MASK;
1960 }
1961
1962 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1963 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1964 } else {
1965 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1966 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1967 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1968 (DESC_B_SHIFT - HF_SS32_SHIFT);
1969 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1970 !(hflags & HF_CS32_MASK)) {
1971 hflags |= HF_ADDSEG_MASK;
1972 } else {
1973 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1974 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1975 }
05330448 1976 }
19dc85db 1977 env->hflags = hflags;
05330448
AL		 1978
1979 return 0;
1980}
1981
1bc22652 1982static int kvm_get_msrs(X86CPU *cpu)
05330448 1983{
1bc22652 1984 CPUX86State *env = &cpu->env;
d71b62a1 1985 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 1986 int ret, i;
fcc35e7c 1987 uint64_t mtrr_top_bits;
05330448 1988
d71b62a1
EH		 1989 kvm_msr_buf_reset(cpu);
1990
9c600a84
EH		 1991 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1992 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1993 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1994 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 1995 if (has_msr_star) {
9c600a84 1996 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 1997 }
c3a3a7d3 1998 if (has_msr_hsave_pa) {
9c600a84 1999 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2000 }
c9b8f6b6 2001 if (has_msr_tsc_aux) {
9c600a84 2002 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2003 }
f28558d3 2004 if (has_msr_tsc_adjust) {
9c600a84 2005 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2006 }
aa82ba54 2007 if (has_msr_tsc_deadline) {
9c600a84 2008 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2009 }
21e87c46 2010 if (has_msr_misc_enable) {
9c600a84 2011 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2012 }
fc12d72e 2013 if (has_msr_smbase) {
9c600a84 2014 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2015 }
df67696e 2016 if (has_msr_feature_control) {
9c600a84 2017 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2018 }
79e9ebeb 2019 if (has_msr_bndcfgs) {
9c600a84 2020 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2021 }
18cd2c17 2022 if (has_msr_xss) {
9c600a84 2023 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 2024 }
2025
b8cc45d6
GC		 2026
2027 if (!env->tsc_valid) {
9c600a84 2028 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2029 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2030 }
2031
05330448 2032#ifdef TARGET_X86_64
25d2e361 2033 if (lm_capable_kernel) {
9c600a84
EH		 2034 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2035 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2036 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2037 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2038 }
05330448 2039#endif
9c600a84
EH		 2040 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2041 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2042 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2043 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2044 }
55c911a5 2045 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2046 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2047 }
55c911a5 2048 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2049 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2050 }
0d894367 2051 if (has_msr_architectural_pmu) {
9c600a84
EH		 2052 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2053 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2054 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2055 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2056 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2057 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2058 }
2059 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2060 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2061 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2062 }
2063 }
1a03675d 2064
57780495 2065 if (env->mcg_cap) {
9c600a84
EH		 2066 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2067 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2068 if (has_msr_mcg_ext_ctl) {
2069 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2070 }
b9bec74b 2071 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2072 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2073 }
57780495 2074 }
57780495 2075
1c90ef26 2076 if (has_msr_hv_hypercall) {
9c600a84
EH		 2077 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2078 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2079 }
2d5aa872 2080 if (cpu->hyperv_vapic) {
9c600a84 2081 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2082 }
3ddcd2ed 2083 if (cpu->hyperv_time) {
9c600a84 2084 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2085 }
f2a53c9e
AS		 2086 if (has_msr_hv_crash) {
2087 int j;
2088
2089 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
9c600a84 2090 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2091 }
2092 }
46eb8f98 2093 if (has_msr_hv_runtime) {
9c600a84 2094 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2095 }
866eea9a
AS		 2096 if (cpu->hyperv_synic) {
2097 uint32_t msr;
2098
9c600a84
EH		 2099 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2100 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2101 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2102 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2103 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2104 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2105 }
2106 }
ff99aa64
AS		 2107 if (has_msr_hv_stimer) {
2108 uint32_t msr;
2109
2110 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2111 msr++) {
9c600a84 2112 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2113 }
2114 }
1eabfce6 2115 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2116 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2117 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2118 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2119 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2120 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2121 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2122 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2123 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2124 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2125 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2126 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2127 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2128 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2129 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2130 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2131 }
2132 }
5ef68987 2133
d71b62a1 2134 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2135 if (ret < 0) {
05330448 2136 return ret;
b9bec74b 2137 }
05330448 2138
9c600a84 2139 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2140 /*
2141 * MTRR masks: Each mask consists of 5 parts
2142 * a 10..0: must be zero
2143 * b 11 : valid bit
2144 * c n-1.12: actual mask bits
2145 * d 51..n: reserved must be zero
2146 * e 63.52: reserved must be zero
2147 *
2148 * 'n' is the number of physical bits supported by the CPU and is
2149 * apparently always <= 52. We know our 'n' but don't know what
2150 * the destinations 'n' is; it might be smaller, in which case
2151 * it masks (c) on loading. It might be larger, in which case
2152 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2153 * we're migrating to.
2154 */
2155
2156 if (cpu->fill_mtrr_mask) {
2157 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2158 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2159 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2160 } else {
2161 mtrr_top_bits = 0;
2162 }
2163
05330448 2164 for (i = 0; i < ret; i++) {
0d894367
PB		 2165 uint32_t index = msrs[i].index;
2166 switch (index) {
05330448
AL		 2167 case MSR_IA32_SYSENTER_CS:
2168 env->sysenter_cs = msrs[i].data;
2169 break;
2170 case MSR_IA32_SYSENTER_ESP:
2171 env->sysenter_esp = msrs[i].data;
2172 break;
2173 case MSR_IA32_SYSENTER_EIP:
2174 env->sysenter_eip = msrs[i].data;
2175 break;
0c03266a
JK		 2176 case MSR_PAT:
2177 env->pat = msrs[i].data;
2178 break;
05330448
AL		 2179 case MSR_STAR:
2180 env->star = msrs[i].data;
2181 break;
2182#ifdef TARGET_X86_64
2183 case MSR_CSTAR:
2184 env->cstar = msrs[i].data;
2185 break;
2186 case MSR_KERNELGSBASE:
2187 env->kernelgsbase = msrs[i].data;
2188 break;
2189 case MSR_FMASK:
2190 env->fmask = msrs[i].data;
2191 break;
2192 case MSR_LSTAR:
2193 env->lstar = msrs[i].data;
2194 break;
2195#endif
2196 case MSR_IA32_TSC:
2197 env->tsc = msrs[i].data;
2198 break;
c9b8f6b6
AS		 2199 case MSR_TSC_AUX:
2200 env->tsc_aux = msrs[i].data;
2201 break;
f28558d3
WA		 2202 case MSR_TSC_ADJUST:
2203 env->tsc_adjust = msrs[i].data;
2204 break;
aa82ba54
LJ		 2205 case MSR_IA32_TSCDEADLINE:
2206 env->tsc_deadline = msrs[i].data;
2207 break;
aa851e36
MT		 2208 case MSR_VM_HSAVE_PA:
2209 env->vm_hsave = msrs[i].data;
2210 break;
1a03675d
GC		 2211 case MSR_KVM_SYSTEM_TIME:
2212 env->system_time_msr = msrs[i].data;
2213 break;
2214 case MSR_KVM_WALL_CLOCK:
2215 env->wall_clock_msr = msrs[i].data;
2216 break;
57780495
MT		 2217 case MSR_MCG_STATUS:
2218 env->mcg_status = msrs[i].data;
2219 break;
2220 case MSR_MCG_CTL:
2221 env->mcg_ctl = msrs[i].data;
2222 break;
87f8b626
AR		 2223 case MSR_MCG_EXT_CTL:
2224 env->mcg_ext_ctl = msrs[i].data;
2225 break;
21e87c46
AK		 2226 case MSR_IA32_MISC_ENABLE:
2227 env->msr_ia32_misc_enable = msrs[i].data;
2228 break;
fc12d72e
PB		 2229 case MSR_IA32_SMBASE:
2230 env->smbase = msrs[i].data;
2231 break;
0779caeb
ACL		 2232 case MSR_IA32_FEATURE_CONTROL:
2233 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2234 break;
79e9ebeb
LJ		 2235 case MSR_IA32_BNDCFGS:
2236 env->msr_bndcfgs = msrs[i].data;
2237 break;
18cd2c17
WL		 2238 case MSR_IA32_XSS:
2239 env->xss = msrs[i].data;
2240 break;
57780495 2241 default:
57780495
MT		 2242 if (msrs[i].index >= MSR_MC0_CTL &&
2243 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2244 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2245 }
d8da8574 2246 break;
f6584ee2
GN		 2247 case MSR_KVM_ASYNC_PF_EN:
2248 env->async_pf_en_msr = msrs[i].data;
2249 break;
bc9a839d
MT		 2250 case MSR_KVM_PV_EOI_EN:
2251 env->pv_eoi_en_msr = msrs[i].data;
2252 break;
917367aa
MT		 2253 case MSR_KVM_STEAL_TIME:
2254 env->steal_time_msr = msrs[i].data;
2255 break;
0d894367
PB		 2256 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2257 env->msr_fixed_ctr_ctrl = msrs[i].data;
2258 break;
2259 case MSR_CORE_PERF_GLOBAL_CTRL:
2260 env->msr_global_ctrl = msrs[i].data;
2261 break;
2262 case MSR_CORE_PERF_GLOBAL_STATUS:
2263 env->msr_global_status = msrs[i].data;
2264 break;
2265 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2266 env->msr_global_ovf_ctrl = msrs[i].data;
2267 break;
2268 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2269 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2270 break;
2271 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2272 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2273 break;
2274 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2275 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2276 break;
1c90ef26
VR		 2277 case HV_X64_MSR_HYPERCALL:
2278 env->msr_hv_hypercall = msrs[i].data;
2279 break;
2280 case HV_X64_MSR_GUEST_OS_ID:
2281 env->msr_hv_guest_os_id = msrs[i].data;
2282 break;
5ef68987
VR		 2283 case HV_X64_MSR_APIC_ASSIST_PAGE:
2284 env->msr_hv_vapic = msrs[i].data;
2285 break;
48a5f3bc
VR		 2286 case HV_X64_MSR_REFERENCE_TSC:
2287 env->msr_hv_tsc = msrs[i].data;
2288 break;
f2a53c9e
AS		 2289 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2290 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2291 break;
46eb8f98
AS		 2292 case HV_X64_MSR_VP_RUNTIME:
2293 env->msr_hv_runtime = msrs[i].data;
2294 break;
866eea9a
AS		 2295 case HV_X64_MSR_SCONTROL:
2296 env->msr_hv_synic_control = msrs[i].data;
2297 break;
2298 case HV_X64_MSR_SVERSION:
2299 env->msr_hv_synic_version = msrs[i].data;
2300 break;
2301 case HV_X64_MSR_SIEFP:
2302 env->msr_hv_synic_evt_page = msrs[i].data;
2303 break;
2304 case HV_X64_MSR_SIMP:
2305 env->msr_hv_synic_msg_page = msrs[i].data;
2306 break;
2307 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2308 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2309 break;
2310 case HV_X64_MSR_STIMER0_CONFIG:
2311 case HV_X64_MSR_STIMER1_CONFIG:
2312 case HV_X64_MSR_STIMER2_CONFIG:
2313 case HV_X64_MSR_STIMER3_CONFIG:
2314 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2315 msrs[i].data;
2316 break;
2317 case HV_X64_MSR_STIMER0_COUNT:
2318 case HV_X64_MSR_STIMER1_COUNT:
2319 case HV_X64_MSR_STIMER2_COUNT:
2320 case HV_X64_MSR_STIMER3_COUNT:
2321 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2322 msrs[i].data;
866eea9a 2323 break;
d1ae67f6
AW		 2324 case MSR_MTRRdefType:
2325 env->mtrr_deftype = msrs[i].data;
2326 break;
2327 case MSR_MTRRfix64K_00000:
2328 env->mtrr_fixed[0] = msrs[i].data;
2329 break;
2330 case MSR_MTRRfix16K_80000:
2331 env->mtrr_fixed[1] = msrs[i].data;
2332 break;
2333 case MSR_MTRRfix16K_A0000:
2334 env->mtrr_fixed[2] = msrs[i].data;
2335 break;
2336 case MSR_MTRRfix4K_C0000:
2337 env->mtrr_fixed[3] = msrs[i].data;
2338 break;
2339 case MSR_MTRRfix4K_C8000:
2340 env->mtrr_fixed[4] = msrs[i].data;
2341 break;
2342 case MSR_MTRRfix4K_D0000:
2343 env->mtrr_fixed[5] = msrs[i].data;
2344 break;
2345 case MSR_MTRRfix4K_D8000:
2346 env->mtrr_fixed[6] = msrs[i].data;
2347 break;
2348 case MSR_MTRRfix4K_E0000:
2349 env->mtrr_fixed[7] = msrs[i].data;
2350 break;
2351 case MSR_MTRRfix4K_E8000:
2352 env->mtrr_fixed[8] = msrs[i].data;
2353 break;
2354 case MSR_MTRRfix4K_F0000:
2355 env->mtrr_fixed[9] = msrs[i].data;
2356 break;
2357 case MSR_MTRRfix4K_F8000:
2358 env->mtrr_fixed[10] = msrs[i].data;
2359 break;
2360 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2361 if (index & 1) {
fcc35e7c
DDAG		 2362 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2363 mtrr_top_bits;
d1ae67f6
AW		 2364 } else {
2365 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2366 }
2367 break;
05330448
AL		 2368 }
2369 }
2370
2371 return 0;
2372}
2373
1bc22652 2374static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2375{
1bc22652 2376 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2377
1bc22652 2378 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2379}
2380
23d02d9b 2381static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2382{
259186a7 2383 CPUState *cs = CPU(cpu);
23d02d9b 2384 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2385 struct kvm_mp_state mp_state;
2386 int ret;
2387
259186a7 2388 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2389 if (ret < 0) {
2390 return ret;
2391 }
2392 env->mp_state = mp_state.mp_state;
c14750e8 2393 if (kvm_irqchip_in_kernel()) {
259186a7 2394 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2395 }
9bdbe550
HB		 2396 return 0;
2397}
2398
1bc22652 2399static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2400{
02e51483 2401 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2402 struct kvm_lapic_state kapic;
2403 int ret;
2404
3d4b2649 2405 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2406 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2407 if (ret < 0) {
2408 return ret;
2409 }
2410
2411 kvm_get_apic_state(apic, &kapic);
2412 }
2413 return 0;
2414}
2415
1bc22652 2416static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2417{
fc12d72e 2418 CPUState *cs = CPU(cpu);
1bc22652 2419 CPUX86State *env = &cpu->env;
076796f8 2420 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2421
2422 if (!kvm_has_vcpu_events()) {
2423 return 0;
2424 }
2425
31827373
JK		 2426 events.exception.injected = (env->exception_injected >= 0);
2427 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2428 events.exception.has_error_code = env->has_error_code;
2429 events.exception.error_code = env->error_code;
7e680753 2430 events.exception.pad = 0;
a0fb002c
JK		 2431
2432 events.interrupt.injected = (env->interrupt_injected >= 0);
2433 events.interrupt.nr = env->interrupt_injected;
2434 events.interrupt.soft = env->soft_interrupt;
2435
2436 events.nmi.injected = env->nmi_injected;
2437 events.nmi.pending = env->nmi_pending;
2438 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2439 events.nmi.pad = 0;
a0fb002c
JK		 2440
2441 events.sipi_vector = env->sipi_vector;
68c6efe0 2442 events.flags = 0;
a0fb002c 2443
fc12d72e
PB		 2444 if (has_msr_smbase) {
2445 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2446 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2447 if (kvm_irqchip_in_kernel()) {
2448 /* As soon as these are moved to the kernel, remove them
2449 * from cs->interrupt_request.
2450 */
2451 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2452 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2453 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2454 } else {
2455 /* Keep these in cs->interrupt_request. */
2456 events.smi.pending = 0;
2457 events.smi.latched_init = 0;
2458 }
2459 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2460 }
2461
ea643051
JK		 2462 if (level >= KVM_PUT_RESET_STATE) {
2463 events.flags |=
2464 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2465 }
aee028b9 2466
1bc22652 2467 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2468}
2469
1bc22652 2470static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2471{
1bc22652 2472 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2473 struct kvm_vcpu_events events;
2474 int ret;
2475
2476 if (!kvm_has_vcpu_events()) {
2477 return 0;
2478 }
2479
fc12d72e 2480 memset(&events, 0, sizeof(events));
1bc22652 2481 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2482 if (ret < 0) {
2483 return ret;
2484 }
31827373 2485 env->exception_injected =
a0fb002c
JK		 2486 events.exception.injected ? events.exception.nr : -1;
2487 env->has_error_code = events.exception.has_error_code;
2488 env->error_code = events.exception.error_code;
2489
2490 env->interrupt_injected =
2491 events.interrupt.injected ? events.interrupt.nr : -1;
2492 env->soft_interrupt = events.interrupt.soft;
2493
2494 env->nmi_injected = events.nmi.injected;
2495 env->nmi_pending = events.nmi.pending;
2496 if (events.nmi.masked) {
2497 env->hflags2 |= HF2_NMI_MASK;
2498 } else {
2499 env->hflags2 &= ~HF2_NMI_MASK;
2500 }
2501
fc12d72e
PB		 2502 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2503 if (events.smi.smm) {
2504 env->hflags |= HF_SMM_MASK;
2505 } else {
2506 env->hflags &= ~HF_SMM_MASK;
2507 }
2508 if (events.smi.pending) {
2509 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2510 } else {
2511 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2512 }
2513 if (events.smi.smm_inside_nmi) {
2514 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2515 } else {
2516 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2517 }
2518 if (events.smi.latched_init) {
2519 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2520 } else {
2521 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2522 }
2523 }
2524
a0fb002c 2525 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2526
2527 return 0;
2528}
2529
1bc22652 2530static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2531{
ed2803da 2532 CPUState *cs = CPU(cpu);
1bc22652 2533 CPUX86State *env = &cpu->env;
b0b1d690 2534 int ret = 0;
b0b1d690
JK		 2535 unsigned long reinject_trap = 0;
2536
2537 if (!kvm_has_vcpu_events()) {
2538 if (env->exception_injected == 1) {
2539 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2540 } else if (env->exception_injected == 3) {
2541 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2542 }
2543 env->exception_injected = -1;
2544 }
2545
2546 /*
2547 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2548 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2549 * by updating the debug state once again if single-stepping is on.
2550 * Another reason to call kvm_update_guest_debug here is a pending debug
2551 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2552 * reinject them via SET_GUEST_DEBUG.
2553 */
2554 if (reinject_trap ||
ed2803da 2555 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2556 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2557 }
b0b1d690
JK		 2558 return ret;
2559}
2560
1bc22652 2561static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2562{
1bc22652 2563 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2564 struct kvm_debugregs dbgregs;
2565 int i;
2566
2567 if (!kvm_has_debugregs()) {
2568 return 0;
2569 }
2570
2571 for (i = 0; i < 4; i++) {
2572 dbgregs.db[i] = env->dr[i];
2573 }
2574 dbgregs.dr6 = env->dr[6];
2575 dbgregs.dr7 = env->dr[7];
2576 dbgregs.flags = 0;
2577
1bc22652 2578 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2579}
2580
1bc22652 2581static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2582{
1bc22652 2583 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2584 struct kvm_debugregs dbgregs;
2585 int i, ret;
2586
2587 if (!kvm_has_debugregs()) {
2588 return 0;
2589 }
2590
1bc22652 2591 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2592 if (ret < 0) {
b9bec74b 2593 return ret;
ff44f1a3
JK		 2594 }
2595 for (i = 0; i < 4; i++) {
2596 env->dr[i] = dbgregs.db[i];
2597 }
2598 env->dr[4] = env->dr[6] = dbgregs.dr6;
2599 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2600
2601 return 0;
2602}
2603
20d695a9 2604int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2605{
20d695a9 2606 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2607 int ret;
2608
2fa45344 2609 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2610
48e1a45c 2611 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2612 ret = kvm_put_msr_feature_control(x86_cpu);
2613 if (ret < 0) {
2614 return ret;
2615 }
2616 }
2617
36f96c4b
HZ		 2618 if (level == KVM_PUT_FULL_STATE) {
2619 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2620 * because TSC frequency mismatch shouldn't abort migration,
2621 * unless the user explicitly asked for a more strict TSC
2622 * setting (e.g. using an explicit "tsc-freq" option).
2623 */
2624 kvm_arch_set_tsc_khz(cpu);
2625 }
2626
1bc22652 2627 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2628 if (ret < 0) {
05330448 2629 return ret;
b9bec74b 2630 }
1bc22652 2631 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2632 if (ret < 0) {
f1665b21 2633 return ret;
b9bec74b 2634 }
1bc22652 2635 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2636 if (ret < 0) {
05330448 2637 return ret;
b9bec74b 2638 }
1bc22652 2639 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2640 if (ret < 0) {
05330448 2641 return ret;
b9bec74b 2642 }
ab443475 2643 /* must be before kvm_put_msrs */
1bc22652 2644 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2645 if (ret < 0) {
2646 return ret;
2647 }
1bc22652 2648 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2649 if (ret < 0) {
05330448 2650 return ret;
b9bec74b 2651 }
ea643051 2652 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2653 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2654 if (ret < 0) {
680c1c6f
JK		 2655 return ret;
2656 }
ea643051 2657 }
7477cd38
MT		 2658
2659 ret = kvm_put_tscdeadline_msr(x86_cpu);
2660 if (ret < 0) {
2661 return ret;
2662 }
2663
1bc22652 2664 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2665 if (ret < 0) {
a0fb002c 2666 return ret;
b9bec74b 2667 }
1bc22652 2668 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2669 if (ret < 0) {
b0b1d690 2670 return ret;
b9bec74b 2671 }
b0b1d690 2672 /* must be last */
1bc22652 2673 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2674 if (ret < 0) {
ff44f1a3 2675 return ret;
b9bec74b 2676 }
05330448
AL		 2677 return 0;
2678}
2679
20d695a9 2680int kvm_arch_get_registers(CPUState *cs)
05330448 2681{
20d695a9 2682 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2683 int ret;
2684
20d695a9 2685 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2686
1bc22652 2687 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2688 if (ret < 0) {
f4f1110e 2689 goto out;
b9bec74b 2690 }
1bc22652 2691 ret = kvm_get_xsave(cpu);
b9bec74b 2692 if (ret < 0) {
f4f1110e 2693 goto out;
b9bec74b 2694 }
1bc22652 2695 ret = kvm_get_xcrs(cpu);
b9bec74b 2696 if (ret < 0) {
f4f1110e 2697 goto out;
b9bec74b 2698 }
1bc22652 2699 ret = kvm_get_sregs(cpu);
b9bec74b 2700 if (ret < 0) {
f4f1110e 2701 goto out;
b9bec74b 2702 }
1bc22652 2703 ret = kvm_get_msrs(cpu);
b9bec74b 2704 if (ret < 0) {
f4f1110e 2705 goto out;
b9bec74b 2706 }
23d02d9b 2707 ret = kvm_get_mp_state(cpu);
b9bec74b 2708 if (ret < 0) {
f4f1110e 2709 goto out;
b9bec74b 2710 }
1bc22652 2711 ret = kvm_get_apic(cpu);
680c1c6f 2712 if (ret < 0) {
f4f1110e 2713 goto out;
680c1c6f 2714 }
1bc22652 2715 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2716 if (ret < 0) {
f4f1110e 2717 goto out;
b9bec74b 2718 }
1bc22652 2719 ret = kvm_get_debugregs(cpu);
b9bec74b 2720 if (ret < 0) {
f4f1110e 2721 goto out;
b9bec74b 2722 }
f4f1110e
RH		 2723 ret = 0;
2724 out:
2725 cpu_sync_bndcs_hflags(&cpu->env);
2726 return ret;
05330448
AL		 2727}
2728
20d695a9 2729void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2730{
20d695a9
AF		 2731 X86CPU *x86_cpu = X86_CPU(cpu);
2732 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2733 int ret;
2734
276ce815 2735 /* Inject NMI */
fc12d72e
PB		 2736 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2737 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2738 qemu_mutex_lock_iothread();
2739 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2740 qemu_mutex_unlock_iothread();
2741 DPRINTF("injected NMI\n");
2742 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2743 if (ret < 0) {
2744 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2745 strerror(-ret));
2746 }
2747 }
2748 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2749 qemu_mutex_lock_iothread();
2750 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2751 qemu_mutex_unlock_iothread();
2752 DPRINTF("injected SMI\n");
2753 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2754 if (ret < 0) {
2755 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2756 strerror(-ret));
2757 }
ce377af3 2758 }
276ce815
LJ		 2759 }
2760
15eafc2e 2761 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2762 qemu_mutex_lock_iothread();
2763 }
2764
e0723c45
PB		 2765 /* Force the VCPU out of its inner loop to process any INIT requests
2766 * or (for userspace APIC, but it is cheap to combine the checks here)
2767 * pending TPR access reports.
2768 */
2769 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2770 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2771 !(env->hflags & HF_SMM_MASK)) {
2772 cpu->exit_request = 1;
2773 }
2774 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2775 cpu->exit_request = 1;
2776 }
e0723c45 2777 }
05330448 2778
15eafc2e 2779 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2780 /* Try to inject an interrupt if the guest can accept it */
2781 if (run->ready_for_interrupt_injection &&
259186a7 2782 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2783 (env->eflags & IF_MASK)) {
2784 int irq;
2785
259186a7 2786 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2787 irq = cpu_get_pic_interrupt(env);
2788 if (irq >= 0) {
2789 struct kvm_interrupt intr;
2790
2791 intr.irq = irq;
db1669bc 2792 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2793 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2794 if (ret < 0) {
2795 fprintf(stderr,
2796 "KVM: injection failed, interrupt lost (%s)\n",
2797 strerror(-ret));
2798 }
db1669bc
JK		 2799 }
2800 }
05330448 2801
db1669bc
JK		 2802 /* If we have an interrupt but the guest is not ready to receive an
2803 * interrupt, request an interrupt window exit. This will
2804 * cause a return to userspace as soon as the guest is ready to
2805 * receive interrupts. */
259186a7 2806 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2807 run->request_interrupt_window = 1;
2808 } else {
2809 run->request_interrupt_window = 0;
2810 }
2811
2812 DPRINTF("setting tpr\n");
02e51483 2813 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2814
2815 qemu_mutex_unlock_iothread();
db1669bc 2816 }
05330448
AL		 2817}
2818
4c663752 2819MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2820{
20d695a9
AF		 2821 X86CPU *x86_cpu = X86_CPU(cpu);
2822 CPUX86State *env = &x86_cpu->env;
2823
fc12d72e
PB		 2824 if (run->flags & KVM_RUN_X86_SMM) {
2825 env->hflags |= HF_SMM_MASK;
2826 } else {
2827 env->hflags &= HF_SMM_MASK;
2828 }
b9bec74b 2829 if (run->if_flag) {
05330448 2830 env->eflags |= IF_MASK;
b9bec74b 2831 } else {
05330448 2832 env->eflags &= ~IF_MASK;
b9bec74b 2833 }
4b8523ee
JK		 2834
2835 /* We need to protect the apic state against concurrent accesses from
2836 * different threads in case the userspace irqchip is used. */
2837 if (!kvm_irqchip_in_kernel()) {
2838 qemu_mutex_lock_iothread();
2839 }
02e51483
CF		 2840 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2841 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2842 if (!kvm_irqchip_in_kernel()) {
2843 qemu_mutex_unlock_iothread();
2844 }
f794aa4a 2845 return cpu_get_mem_attrs(env);
05330448
AL		 2846}
2847
20d695a9 2848int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2849{
20d695a9
AF		 2850 X86CPU *cpu = X86_CPU(cs);
2851 CPUX86State *env = &cpu->env;
232fc23b 2852
259186a7 2853 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2854 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2855 assert(env->mcg_cap);
2856
259186a7 2857 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2858
dd1750d7 2859 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2860
2861 if (env->exception_injected == EXCP08_DBLE) {
2862 /* this means triple fault */
2863 qemu_system_reset_request();
fcd7d003 2864 cs->exit_request = 1;
ab443475
JK		 2865 return 0;
2866 }
2867 env->exception_injected = EXCP12_MCHK;
2868 env->has_error_code = 0;
2869
259186a7 2870 cs->halted = 0;
ab443475
JK		 2871 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2872 env->mp_state = KVM_MP_STATE_RUNNABLE;
2873 }
2874 }
2875
fc12d72e
PB		 2876 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2877 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2878 kvm_cpu_synchronize_state(cs);
2879 do_cpu_init(cpu);
2880 }
2881
db1669bc
JK		 2882 if (kvm_irqchip_in_kernel()) {
2883 return 0;
2884 }
2885
259186a7
AF		 2886 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2887 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2888 apic_poll_irq(cpu->apic_state);
5d62c43a 2889 }
259186a7 2890 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2891 (env->eflags & IF_MASK)) ||
259186a7
AF		 2892 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2893 cs->halted = 0;
6792a57b 2894 }
259186a7 2895 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2896 kvm_cpu_synchronize_state(cs);
232fc23b 2897 do_cpu_sipi(cpu);
0af691d7 2898 }
259186a7
AF		 2899 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2900 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2901 kvm_cpu_synchronize_state(cs);
02e51483 2902 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2903 env->tpr_access_type);
2904 }
0af691d7 2905
259186a7 2906 return cs->halted;
0af691d7
MT		 2907}
2908
839b5630 2909static int kvm_handle_halt(X86CPU *cpu)
05330448 2910{
259186a7 2911 CPUState *cs = CPU(cpu);
839b5630
AF		 2912 CPUX86State *env = &cpu->env;
2913
259186a7 2914 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2915 (env->eflags & IF_MASK)) &&
259186a7
AF		 2916 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2917 cs->halted = 1;
bb4ea393 2918 return EXCP_HLT;
05330448
AL		 2919 }
2920
bb4ea393 2921 return 0;
05330448
AL		 2922}
2923
f7575c96 2924static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2925{
f7575c96
AF		 2926 CPUState *cs = CPU(cpu);
2927 struct kvm_run *run = cs->kvm_run;
d362e757 2928
02e51483 2929 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2930 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2931 : TPR_ACCESS_READ);
2932 return 1;
2933}
2934
f17ec444 2935int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2936{
38972938 2937 static const uint8_t int3 = 0xcc;
64bf3f4e 2938
f17ec444
AF		 2939 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2940 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2941 return -EINVAL;
b9bec74b 2942 }
e22a25c9
AL		 2943 return 0;
2944}
2945
f17ec444 2946int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2947{
2948 uint8_t int3;
2949
f17ec444
AF		 2950 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2951 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2952 return -EINVAL;
b9bec74b 2953 }
e22a25c9
AL		 2954 return 0;
2955}
2956
2957static struct {
2958 target_ulong addr;
2959 int len;
2960 int type;
2961} hw_breakpoint[4];
2962
2963static int nb_hw_breakpoint;
2964
2965static int find_hw_breakpoint(target_ulong addr, int len, int type)
2966{
2967 int n;
2968
b9bec74b 2969 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2970 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2971 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2972 return n;
b9bec74b
JK		 2973 }
2974 }
e22a25c9
AL		 2975 return -1;
2976}
2977
2978int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2979 target_ulong len, int type)
2980{
2981 switch (type) {
2982 case GDB_BREAKPOINT_HW:
2983 len = 1;
2984 break;
2985 case GDB_WATCHPOINT_WRITE:
2986 case GDB_WATCHPOINT_ACCESS:
2987 switch (len) {
2988 case 1:
2989 break;
2990 case 2:
2991 case 4:
2992 case 8:
b9bec74b 2993 if (addr & (len - 1)) {
e22a25c9 2994 return -EINVAL;
b9bec74b 2995 }
e22a25c9
AL		 2996 break;
2997 default:
2998 return -EINVAL;
2999 }
3000 break;
3001 default:
3002 return -ENOSYS;
3003 }
3004
b9bec74b 3005 if (nb_hw_breakpoint == 4) {
e22a25c9 3006 return -ENOBUFS;
b9bec74b
JK		 3007 }
3008 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3009 return -EEXIST;
b9bec74b 3010 }
e22a25c9
AL		 3011 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3012 hw_breakpoint[nb_hw_breakpoint].len = len;
3013 hw_breakpoint[nb_hw_breakpoint].type = type;
3014 nb_hw_breakpoint++;
3015
3016 return 0;
3017}
3018
3019int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3020 target_ulong len, int type)
3021{
3022 int n;
3023
3024 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3025 if (n < 0) {
e22a25c9 3026 return -ENOENT;
b9bec74b 3027 }
e22a25c9
AL		 3028 nb_hw_breakpoint--;
3029 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3030
3031 return 0;
3032}
3033
3034void kvm_arch_remove_all_hw_breakpoints(void)
3035{
3036 nb_hw_breakpoint = 0;
3037}
3038
3039static CPUWatchpoint hw_watchpoint;
3040
a60f24b5 3041static int kvm_handle_debug(X86CPU *cpu,
48405526 3042 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3043{
ed2803da 3044 CPUState *cs = CPU(cpu);
a60f24b5 3045 CPUX86State *env = &cpu->env;
f2574737 3046 int ret = 0;
e22a25c9
AL		 3047 int n;
3048
3049 if (arch_info->exception == 1) {
3050 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3051 if (cs->singlestep_enabled) {
f2574737 3052 ret = EXCP_DEBUG;
b9bec74b 3053 }
e22a25c9 3054 } else {
b9bec74b
JK		 3055 for (n = 0; n < 4; n++) {
3056 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3057 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3058 case 0x0:
f2574737 3059 ret = EXCP_DEBUG;
e22a25c9
AL		 3060 break;
3061 case 0x1:
f2574737 3062 ret = EXCP_DEBUG;
ff4700b0 3063 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3064 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3065 hw_watchpoint.flags = BP_MEM_WRITE;
3066 break;
3067 case 0x3:
f2574737 3068 ret = EXCP_DEBUG;
ff4700b0 3069 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3070 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3071 hw_watchpoint.flags = BP_MEM_ACCESS;
3072 break;
3073 }
b9bec74b
JK		 3074 }
3075 }
e22a25c9 3076 }
ff4700b0 3077 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3078 ret = EXCP_DEBUG;
b9bec74b 3079 }
f2574737 3080 if (ret == 0) {
ff4700b0 3081 cpu_synchronize_state(cs);
48405526 3082 assert(env->exception_injected == -1);
b0b1d690 3083
f2574737 3084 /* pass to guest */
48405526
BS		 3085 env->exception_injected = arch_info->exception;
3086 env->has_error_code = 0;
b0b1d690 3087 }
e22a25c9 3088
f2574737 3089 return ret;
e22a25c9
AL		 3090}
3091
20d695a9 3092void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3093{
3094 const uint8_t type_code[] = {
3095 [GDB_BREAKPOINT_HW] = 0x0,
3096 [GDB_WATCHPOINT_WRITE] = 0x1,
3097 [GDB_WATCHPOINT_ACCESS] = 0x3
3098 };
3099 const uint8_t len_code[] = {
3100 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3101 };
3102 int n;
3103
a60f24b5 3104 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3105 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3106 }
e22a25c9
AL		 3107 if (nb_hw_breakpoint > 0) {
3108 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3109 dbg->arch.debugreg[7] = 0x0600;
3110 for (n = 0; n < nb_hw_breakpoint; n++) {
3111 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3112 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3113 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3114 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3115 }
3116 }
3117}
4513d923 3118
2a4dac83
JK		 3119static bool host_supports_vmx(void)
3120{
3121 uint32_t ecx, unused;
3122
3123 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3124 return ecx & CPUID_EXT_VMX;
3125}
3126
3127#define VMX_INVALID_GUEST_STATE 0x80000021
3128
20d695a9 3129int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3130{
20d695a9 3131 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3132 uint64_t code;
3133 int ret;
3134
3135 switch (run->exit_reason) {
3136 case KVM_EXIT_HLT:
3137 DPRINTF("handle_hlt\n");
4b8523ee 3138 qemu_mutex_lock_iothread();
839b5630 3139 ret = kvm_handle_halt(cpu);
4b8523ee 3140 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3141 break;
3142 case KVM_EXIT_SET_TPR:
3143 ret = 0;
3144 break;
d362e757 3145 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3146 qemu_mutex_lock_iothread();
f7575c96 3147 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3148 qemu_mutex_unlock_iothread();
d362e757 3149 break;
2a4dac83
JK		 3150 case KVM_EXIT_FAIL_ENTRY:
3151 code = run->fail_entry.hardware_entry_failure_reason;
3152 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3153 code);
3154 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3155 fprintf(stderr,
12619721 3156 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3157 "unrestricted mode\n"
3158 "support, the failure can be most likely due to the guest "
3159 "entering an invalid\n"
3160 "state for Intel VT. For example, the guest maybe running "
3161 "in big real mode\n"
3162 "which is not supported on less recent Intel processors."
3163 "\n\n");
3164 }
3165 ret = -1;
3166 break;
3167 case KVM_EXIT_EXCEPTION:
3168 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3169 run->ex.exception, run->ex.error_code);
3170 ret = -1;
3171 break;
f2574737
JK		 3172 case KVM_EXIT_DEBUG:
3173 DPRINTF("kvm_exit_debug\n");
4b8523ee 3174 qemu_mutex_lock_iothread();
a60f24b5 3175 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3176 qemu_mutex_unlock_iothread();
f2574737 3177 break;
50efe82c
AS		 3178 case KVM_EXIT_HYPERV:
3179 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3180 break;
15eafc2e
PB		 3181 case KVM_EXIT_IOAPIC_EOI:
3182 ioapic_eoi_broadcast(run->eoi.vector);
3183 ret = 0;
3184 break;
2a4dac83
JK		 3185 default:
3186 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3187 ret = -1;
3188 break;
3189 }
3190
3191 return ret;
3192}
3193
20d695a9 3194bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3195{
20d695a9
AF		 3196 X86CPU *cpu = X86_CPU(cs);
3197 CPUX86State *env = &cpu->env;
3198
dd1750d7 3199 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3200 return !(env->cr[0] & CR0_PE_MASK) ||
3201 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3202}
84b058d7
JK		 3203
3204void kvm_arch_init_irq_routing(KVMState *s)
3205{
3206 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3207 /* If kernel can't do irq routing, interrupt source
3208 * override 0->2 cannot be set up as required by HPET.
3209 * So we have to disable it.
3210 */
3211 no_hpet = 1;
3212 }
cc7e0ddf 3213 /* We know at this point that we're using the in-kernel
614e41bc 3214 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3215 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3216 */
614e41bc 3217 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3218 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3219
3220 if (kvm_irqchip_is_split()) {
3221 int i;
3222
3223 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3224 MSI routes for signaling interrupts to the local apics. */
3225 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3226 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3227 error_report("Could not enable split IRQ mode.");
3228 exit(1);
3229 }
3230 }
3231 }
3232}
3233
3234int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3235{
3236 int ret;
3237 if (machine_kernel_irqchip_split(ms)) {
3238 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3239 if (ret) {
df3c286c 3240 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3241 strerror(-ret));
3242 exit(1);
3243 } else {
3244 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3245 kvm_split_irqchip = true;
3246 return 1;
3247 }
3248 } else {
3249 return 0;
3250 }
84b058d7 3251}
b139bd30
JK		 3252
3253/* Classic KVM device assignment interface. Will remain x86 only. */
3254int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3255 uint32_t flags, uint32_t *dev_id)
3256{
3257 struct kvm_assigned_pci_dev dev_data = {
3258 .segnr = dev_addr->domain,
3259 .busnr = dev_addr->bus,
3260 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3261 .flags = flags,
3262 };
3263 int ret;
3264
3265 dev_data.assigned_dev_id =
3266 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3267
3268 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3269 if (ret < 0) {
3270 return ret;
3271 }
3272
3273 *dev_id = dev_data.assigned_dev_id;
3274
3275 return 0;
3276}
3277
3278int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3279{
3280 struct kvm_assigned_pci_dev dev_data = {
3281 .assigned_dev_id = dev_id,
3282 };
3283
3284 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3285}
3286
3287static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3288 uint32_t irq_type, uint32_t guest_irq)
3289{
3290 struct kvm_assigned_irq assigned_irq = {
3291 .assigned_dev_id = dev_id,
3292 .guest_irq = guest_irq,
3293 .flags = irq_type,
3294 };
3295
3296 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3297 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3298 } else {
3299 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3300 }
3301}
3302
3303int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3304 uint32_t guest_irq)
3305{
3306 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3307 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3308
3309 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3310}
3311
3312int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3313{
3314 struct kvm_assigned_pci_dev dev_data = {
3315 .assigned_dev_id = dev_id,
3316 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3317 };
3318
3319 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3320}
3321
3322static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3323 uint32_t type)
3324{
3325 struct kvm_assigned_irq assigned_irq = {
3326 .assigned_dev_id = dev_id,
3327 .flags = type,
3328 };
3329
3330 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3331}
3332
3333int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3334{
3335 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3336 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3337}
3338
3339int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3340{
3341 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3342 KVM_DEV_IRQ_GUEST_MSI, virq);
3343}
3344
3345int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3346{
3347 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3348 KVM_DEV_IRQ_HOST_MSI);
3349}
3350
3351bool kvm_device_msix_supported(KVMState *s)
3352{
3353 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3354 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3355 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3356}
3357
3358int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3359 uint32_t nr_vectors)
3360{
3361 struct kvm_assigned_msix_nr msix_nr = {
3362 .assigned_dev_id = dev_id,
3363 .entry_nr = nr_vectors,
3364 };
3365
3366 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3367}
3368
3369int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3370 int virq)
3371{
3372 struct kvm_assigned_msix_entry msix_entry = {
3373 .assigned_dev_id = dev_id,
3374 .gsi = virq,
3375 .entry = vector,
3376 };
3377
3378 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3379}
3380
3381int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3382{
3383 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3384 KVM_DEV_IRQ_GUEST_MSIX, 0);
3385}
3386
3387int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3388{
3389 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3390 KVM_DEV_IRQ_HOST_MSIX);
3391}
9e03a040
FB		 3392
3393int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3394 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3395{
8b5ed7df
PX		 3396 X86IOMMUState *iommu = x86_iommu_get_default();
3397
3398 if (iommu) {
3399 int ret;
3400 MSIMessage src, dst;
3401 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3402
3403 src.address = route->u.msi.address_hi;
3404 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3405 src.address |= route->u.msi.address_lo;
3406 src.data = route->u.msi.data;
3407
3408 ret = class->int_remap(iommu, &src, &dst, dev ? \
3409 pci_requester_id(dev) : \
3410 X86_IOMMU_SID_INVALID);
3411 if (ret) {
3412 trace_kvm_x86_fixup_msi_error(route->gsi);
3413 return 1;
3414 }
3415
3416 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3417 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3418 route->u.msi.data = dst.data;
3419 }
3420
9e03a040
FB		 3421 return 0;
3422}
1850b6b7 3423
38d87493
PX		 3424typedef struct MSIRouteEntry MSIRouteEntry;
3425
3426struct MSIRouteEntry {
3427 PCIDevice *dev; /* Device pointer */
3428 int vector; /* MSI/MSIX vector index */
3429 int virq; /* Virtual IRQ index */
3430 QLIST_ENTRY(MSIRouteEntry) list;
3431};
3432
3433/* List of used GSI routes */
3434static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3435 QLIST_HEAD_INITIALIZER(msi_route_list);
3436
e1d4fb2d
PX		 3437static void kvm_update_msi_routes_all(void *private, bool global,
3438 uint32_t index, uint32_t mask)
3439{
3440 int cnt = 0;
3441 MSIRouteEntry *entry;
3442 MSIMessage msg;
3443 /* TODO: explicit route update */
3444 QLIST_FOREACH(entry, &msi_route_list, list) {
3445 cnt++;
3446 msg = pci_get_msi_message(entry->dev, entry->vector);
3447 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3448 msg, entry->dev);
3449 }
3f1fea0f 3450 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3451 trace_kvm_x86_update_msi_routes(cnt);
3452}
3453
38d87493
PX		 3454int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3455 int vector, PCIDevice *dev)
3456{
e1d4fb2d 3457 static bool notify_list_inited = false;
38d87493
PX		 3458 MSIRouteEntry *entry;
3459
3460 if (!dev) {
3461 /* These are (possibly) IOAPIC routes only used for split
3462 * kernel irqchip mode, while what we are housekeeping are
3463 * PCI devices only. */
3464 return 0;
3465 }
3466
3467 entry = g_new0(MSIRouteEntry, 1);
3468 entry->dev = dev;
3469 entry->vector = vector;
3470 entry->virq = route->gsi;
3471 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3472
3473 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3474
3475 if (!notify_list_inited) {
3476 /* For the first time we do add route, add ourselves into
3477 * IOMMU's IEC notify list if needed. */
3478 X86IOMMUState *iommu = x86_iommu_get_default();
3479 if (iommu) {
3480 x86_iommu_iec_register_notifier(iommu,
3481 kvm_update_msi_routes_all,
3482 NULL);
3483 }
3484 notify_list_inited = true;
3485 }
38d87493
PX		 3486 return 0;
3487}
3488
3489int kvm_arch_release_virq_post(int virq)
3490{
3491 MSIRouteEntry *entry, *next;
3492 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3493 if (entry->virq == virq) {
3494 trace_kvm_x86_remove_msi_route(virq);
3495 QLIST_REMOVE(entry, list);
3496 break;
3497 }
3498 }
9e03a040
FB		 3499 return 0;
3500}
1850b6b7
EA		 3501
3502int kvm_arch_msi_data_to_gsi(uint32_t data)
3503{
3504 abort();
3505}
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