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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
5802e066 | 21 | #include <linux/kvm_para.h> |
05330448 AL |
22 | |
23 | #include "qemu-common.h" | |
9c17d615 PB |
24 | #include "sysemu/sysemu.h" |
25 | #include "sysemu/kvm.h" | |
1d31f66b | 26 | #include "kvm_i386.h" |
05330448 | 27 | #include "cpu.h" |
022c62cb | 28 | #include "exec/gdbstub.h" |
1de7afc9 PB |
29 | #include "qemu/host-utils.h" |
30 | #include "qemu/config-file.h" | |
4c5b10b7 | 31 | #include "hw/pc.h" |
408392b3 | 32 | #include "hw/apic.h" |
022c62cb | 33 | #include "exec/ioport.h" |
eab70139 | 34 | #include "hyperv.h" |
a2cb15b0 | 35 | #include "hw/pci/pci.h" |
05330448 AL |
36 | |
37 | //#define DEBUG_KVM | |
38 | ||
39 | #ifdef DEBUG_KVM | |
8c0d577e | 40 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
41 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
42 | #else | |
8c0d577e | 43 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
44 | do { } while (0) |
45 | #endif | |
46 | ||
1a03675d GC |
47 | #define MSR_KVM_WALL_CLOCK 0x11 |
48 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
49 | ||
c0532a76 MT |
50 | #ifndef BUS_MCEERR_AR |
51 | #define BUS_MCEERR_AR 4 | |
52 | #endif | |
53 | #ifndef BUS_MCEERR_AO | |
54 | #define BUS_MCEERR_AO 5 | |
55 | #endif | |
56 | ||
94a8d39a JK |
57 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
58 | KVM_CAP_INFO(SET_TSS_ADDR), | |
59 | KVM_CAP_INFO(EXT_CPUID), | |
60 | KVM_CAP_INFO(MP_STATE), | |
61 | KVM_CAP_LAST_INFO | |
62 | }; | |
25d2e361 | 63 | |
c3a3a7d3 JK |
64 | static bool has_msr_star; |
65 | static bool has_msr_hsave_pa; | |
aa82ba54 | 66 | static bool has_msr_tsc_deadline; |
c5999bfc | 67 | static bool has_msr_async_pf_en; |
bc9a839d | 68 | static bool has_msr_pv_eoi_en; |
21e87c46 | 69 | static bool has_msr_misc_enable; |
25d2e361 | 70 | static int lm_capable_kernel; |
b827df58 | 71 | |
1d31f66b PM |
72 | bool kvm_allows_irq0_override(void) |
73 | { | |
74 | return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing(); | |
75 | } | |
76 | ||
b827df58 AK |
77 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) |
78 | { | |
79 | struct kvm_cpuid2 *cpuid; | |
80 | int r, size; | |
81 | ||
82 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
7267c094 | 83 | cpuid = (struct kvm_cpuid2 *)g_malloc0(size); |
b827df58 AK |
84 | cpuid->nent = max; |
85 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
86 | if (r == 0 && cpuid->nent >= max) { |
87 | r = -E2BIG; | |
88 | } | |
b827df58 AK |
89 | if (r < 0) { |
90 | if (r == -E2BIG) { | |
7267c094 | 91 | g_free(cpuid); |
b827df58 AK |
92 | return NULL; |
93 | } else { | |
94 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
95 | strerror(-r)); | |
96 | exit(1); | |
97 | } | |
98 | } | |
99 | return cpuid; | |
100 | } | |
101 | ||
dd87f8a6 EH |
102 | /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough |
103 | * for all entries. | |
104 | */ | |
105 | static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) | |
106 | { | |
107 | struct kvm_cpuid2 *cpuid; | |
108 | int max = 1; | |
109 | while ((cpuid = try_get_cpuid(s, max)) == NULL) { | |
110 | max *= 2; | |
111 | } | |
112 | return cpuid; | |
113 | } | |
114 | ||
0c31b744 GC |
115 | struct kvm_para_features { |
116 | int cap; | |
117 | int feature; | |
118 | } para_features[] = { | |
119 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
120 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
121 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
0c31b744 | 122 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
0c31b744 GC |
123 | { -1, -1 } |
124 | }; | |
125 | ||
ba9bc59e | 126 | static int get_para_features(KVMState *s) |
0c31b744 GC |
127 | { |
128 | int i, features = 0; | |
129 | ||
130 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
ba9bc59e | 131 | if (kvm_check_extension(s, para_features[i].cap)) { |
0c31b744 GC |
132 | features |= (1 << para_features[i].feature); |
133 | } | |
134 | } | |
135 | ||
136 | return features; | |
137 | } | |
0c31b744 GC |
138 | |
139 | ||
829ae2f9 EH |
140 | /* Returns the value for a specific register on the cpuid entry |
141 | */ | |
142 | static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) | |
143 | { | |
144 | uint32_t ret = 0; | |
145 | switch (reg) { | |
146 | case R_EAX: | |
147 | ret = entry->eax; | |
148 | break; | |
149 | case R_EBX: | |
150 | ret = entry->ebx; | |
151 | break; | |
152 | case R_ECX: | |
153 | ret = entry->ecx; | |
154 | break; | |
155 | case R_EDX: | |
156 | ret = entry->edx; | |
157 | break; | |
158 | } | |
159 | return ret; | |
160 | } | |
161 | ||
4fb73f1d EH |
162 | /* Find matching entry for function/index on kvm_cpuid2 struct |
163 | */ | |
164 | static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, | |
165 | uint32_t function, | |
166 | uint32_t index) | |
167 | { | |
168 | int i; | |
169 | for (i = 0; i < cpuid->nent; ++i) { | |
170 | if (cpuid->entries[i].function == function && | |
171 | cpuid->entries[i].index == index) { | |
172 | return &cpuid->entries[i]; | |
173 | } | |
174 | } | |
175 | /* not found: */ | |
176 | return NULL; | |
177 | } | |
178 | ||
ba9bc59e | 179 | uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, |
c958a8bd | 180 | uint32_t index, int reg) |
b827df58 AK |
181 | { |
182 | struct kvm_cpuid2 *cpuid; | |
b827df58 AK |
183 | uint32_t ret = 0; |
184 | uint32_t cpuid_1_edx; | |
8c723b79 | 185 | bool found = false; |
b827df58 | 186 | |
dd87f8a6 | 187 | cpuid = get_supported_cpuid(s); |
b827df58 | 188 | |
4fb73f1d EH |
189 | struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); |
190 | if (entry) { | |
191 | found = true; | |
192 | ret = cpuid_entry_get_reg(entry, reg); | |
b827df58 AK |
193 | } |
194 | ||
7b46e5ce EH |
195 | /* Fixups for the data returned by KVM, below */ |
196 | ||
c2acb022 EH |
197 | if (function == 1 && reg == R_EDX) { |
198 | /* KVM before 2.6.30 misreports the following features */ | |
199 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
84bd945c EH |
200 | } else if (function == 1 && reg == R_ECX) { |
201 | /* We can set the hypervisor flag, even if KVM does not return it on | |
202 | * GET_SUPPORTED_CPUID | |
203 | */ | |
204 | ret |= CPUID_EXT_HYPERVISOR; | |
ac67ee26 EH |
205 | /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it |
206 | * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, | |
207 | * and the irqchip is in the kernel. | |
208 | */ | |
209 | if (kvm_irqchip_in_kernel() && | |
210 | kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { | |
211 | ret |= CPUID_EXT_TSC_DEADLINE_TIMER; | |
212 | } | |
41e5e76d EH |
213 | |
214 | /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled | |
215 | * without the in-kernel irqchip | |
216 | */ | |
217 | if (!kvm_irqchip_in_kernel()) { | |
218 | ret &= ~CPUID_EXT_X2APIC; | |
b827df58 | 219 | } |
c2acb022 EH |
220 | } else if (function == 0x80000001 && reg == R_EDX) { |
221 | /* On Intel, kvm returns cpuid according to the Intel spec, | |
222 | * so add missing bits according to the AMD spec: | |
223 | */ | |
224 | cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); | |
225 | ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; | |
b827df58 AK |
226 | } |
227 | ||
7267c094 | 228 | g_free(cpuid); |
b827df58 | 229 | |
0c31b744 | 230 | /* fallback for older kernels */ |
8c723b79 | 231 | if ((function == KVM_CPUID_FEATURES) && !found) { |
ba9bc59e | 232 | ret = get_para_features(s); |
b9bec74b | 233 | } |
0c31b744 GC |
234 | |
235 | return ret; | |
bb0300dc | 236 | } |
bb0300dc | 237 | |
3c85e74f HY |
238 | typedef struct HWPoisonPage { |
239 | ram_addr_t ram_addr; | |
240 | QLIST_ENTRY(HWPoisonPage) list; | |
241 | } HWPoisonPage; | |
242 | ||
243 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
244 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
245 | ||
246 | static void kvm_unpoison_all(void *param) | |
247 | { | |
248 | HWPoisonPage *page, *next_page; | |
249 | ||
250 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
251 | QLIST_REMOVE(page, list); | |
252 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
7267c094 | 253 | g_free(page); |
3c85e74f HY |
254 | } |
255 | } | |
256 | ||
3c85e74f HY |
257 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) |
258 | { | |
259 | HWPoisonPage *page; | |
260 | ||
261 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
262 | if (page->ram_addr == ram_addr) { | |
263 | return; | |
264 | } | |
265 | } | |
7267c094 | 266 | page = g_malloc(sizeof(HWPoisonPage)); |
3c85e74f HY |
267 | page->ram_addr = ram_addr; |
268 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
269 | } | |
270 | ||
e7701825 MT |
271 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
272 | int *max_banks) | |
273 | { | |
274 | int r; | |
275 | ||
14a09518 | 276 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
277 | if (r > 0) { |
278 | *max_banks = r; | |
279 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
280 | } | |
281 | return -ENOSYS; | |
282 | } | |
283 | ||
bee615d4 | 284 | static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) |
e7701825 | 285 | { |
bee615d4 | 286 | CPUX86State *env = &cpu->env; |
c34d440a JK |
287 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
288 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
289 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
e7701825 | 290 | |
c34d440a JK |
291 | if (code == BUS_MCEERR_AR) { |
292 | status |= MCI_STATUS_AR | 0x134; | |
293 | mcg_status |= MCG_STATUS_EIPV; | |
294 | } else { | |
295 | status |= 0xc0; | |
296 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 297 | } |
8c5cf3b6 | 298 | cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, |
c34d440a JK |
299 | (MCM_ADDR_PHYS << 6) | 0xc, |
300 | cpu_x86_support_mca_broadcast(env) ? | |
301 | MCE_INJECT_BROADCAST : 0); | |
419fb20a | 302 | } |
419fb20a JK |
303 | |
304 | static void hardware_memory_error(void) | |
305 | { | |
306 | fprintf(stderr, "Hardware memory error!\n"); | |
307 | exit(1); | |
308 | } | |
309 | ||
20d695a9 | 310 | int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) |
419fb20a | 311 | { |
20d695a9 AF |
312 | X86CPU *cpu = X86_CPU(c); |
313 | CPUX86State *env = &cpu->env; | |
419fb20a | 314 | ram_addr_t ram_addr; |
a8170e5e | 315 | hwaddr paddr; |
419fb20a JK |
316 | |
317 | if ((env->mcg_cap & MCG_SER_P) && addr | |
c34d440a JK |
318 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
319 | if (qemu_ram_addr_from_host(addr, &ram_addr) || | |
a60f24b5 | 320 | !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { |
419fb20a JK |
321 | fprintf(stderr, "Hardware memory error for memory used by " |
322 | "QEMU itself instead of guest system!\n"); | |
323 | /* Hope we are lucky for AO MCE */ | |
324 | if (code == BUS_MCEERR_AO) { | |
325 | return 0; | |
326 | } else { | |
327 | hardware_memory_error(); | |
328 | } | |
329 | } | |
3c85e74f | 330 | kvm_hwpoison_page_add(ram_addr); |
bee615d4 | 331 | kvm_mce_inject(cpu, paddr, code); |
e56ff191 | 332 | } else { |
419fb20a JK |
333 | if (code == BUS_MCEERR_AO) { |
334 | return 0; | |
335 | } else if (code == BUS_MCEERR_AR) { | |
336 | hardware_memory_error(); | |
337 | } else { | |
338 | return 1; | |
339 | } | |
340 | } | |
341 | return 0; | |
342 | } | |
343 | ||
344 | int kvm_arch_on_sigbus(int code, void *addr) | |
345 | { | |
419fb20a | 346 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { |
419fb20a | 347 | ram_addr_t ram_addr; |
a8170e5e | 348 | hwaddr paddr; |
419fb20a JK |
349 | |
350 | /* Hope we are lucky for AO MCE */ | |
c34d440a | 351 | if (qemu_ram_addr_from_host(addr, &ram_addr) || |
a60f24b5 AF |
352 | !kvm_physical_memory_addr_from_host(CPU(first_cpu)->kvm_state, |
353 | addr, &paddr)) { | |
419fb20a JK |
354 | fprintf(stderr, "Hardware memory error for memory used by " |
355 | "QEMU itself instead of guest system!: %p\n", addr); | |
356 | return 0; | |
357 | } | |
3c85e74f | 358 | kvm_hwpoison_page_add(ram_addr); |
bee615d4 | 359 | kvm_mce_inject(x86_env_get_cpu(first_cpu), paddr, code); |
e56ff191 | 360 | } else { |
419fb20a JK |
361 | if (code == BUS_MCEERR_AO) { |
362 | return 0; | |
363 | } else if (code == BUS_MCEERR_AR) { | |
364 | hardware_memory_error(); | |
365 | } else { | |
366 | return 1; | |
367 | } | |
368 | } | |
369 | return 0; | |
370 | } | |
e7701825 | 371 | |
1bc22652 | 372 | static int kvm_inject_mce_oldstyle(X86CPU *cpu) |
ab443475 | 373 | { |
1bc22652 AF |
374 | CPUX86State *env = &cpu->env; |
375 | ||
ab443475 JK |
376 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { |
377 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
378 | struct kvm_x86_mce mce; | |
379 | ||
380 | env->exception_injected = -1; | |
381 | ||
382 | /* | |
383 | * There must be at least one bank in use if an MCE is pending. | |
384 | * Find it and use its values for the event injection. | |
385 | */ | |
386 | for (bank = 0; bank < bank_num; bank++) { | |
387 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
388 | break; | |
389 | } | |
390 | } | |
391 | assert(bank < bank_num); | |
392 | ||
393 | mce.bank = bank; | |
394 | mce.status = env->mce_banks[bank * 4 + 1]; | |
395 | mce.mcg_status = env->mcg_status; | |
396 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
397 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
398 | ||
1bc22652 | 399 | return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce); |
ab443475 | 400 | } |
ab443475 JK |
401 | return 0; |
402 | } | |
403 | ||
1dfb4dd9 | 404 | static void cpu_update_state(void *opaque, int running, RunState state) |
b8cc45d6 | 405 | { |
317ac620 | 406 | CPUX86State *env = opaque; |
b8cc45d6 GC |
407 | |
408 | if (running) { | |
409 | env->tsc_valid = false; | |
410 | } | |
411 | } | |
412 | ||
20d695a9 | 413 | int kvm_arch_init_vcpu(CPUState *cs) |
05330448 AL |
414 | { |
415 | struct { | |
486bd5a2 AL |
416 | struct kvm_cpuid2 cpuid; |
417 | struct kvm_cpuid_entry2 entries[100]; | |
541dc0d4 | 418 | } QEMU_PACKED cpuid_data; |
20d695a9 AF |
419 | X86CPU *cpu = X86_CPU(cs); |
420 | CPUX86State *env = &cpu->env; | |
486bd5a2 | 421 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 422 | uint32_t unused; |
bb0300dc | 423 | struct kvm_cpuid_entry2 *c; |
bb0300dc | 424 | uint32_t signature[3]; |
e7429073 | 425 | int r; |
05330448 AL |
426 | |
427 | cpuid_i = 0; | |
428 | ||
bb0300dc | 429 | /* Paravirtualization CPUIDs */ |
bb0300dc GN |
430 | c = &cpuid_data.entries[cpuid_i++]; |
431 | memset(c, 0, sizeof(*c)); | |
432 | c->function = KVM_CPUID_SIGNATURE; | |
eab70139 VR |
433 | if (!hyperv_enabled()) { |
434 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
435 | c->eax = 0; | |
436 | } else { | |
437 | memcpy(signature, "Microsoft Hv", 12); | |
438 | c->eax = HYPERV_CPUID_MIN; | |
439 | } | |
bb0300dc GN |
440 | c->ebx = signature[0]; |
441 | c->ecx = signature[1]; | |
442 | c->edx = signature[2]; | |
443 | ||
444 | c = &cpuid_data.entries[cpuid_i++]; | |
445 | memset(c, 0, sizeof(*c)); | |
446 | c->function = KVM_CPUID_FEATURES; | |
ea85c9e4 | 447 | c->eax = env->cpuid_kvm_features; |
0c31b744 | 448 | |
eab70139 VR |
449 | if (hyperv_enabled()) { |
450 | memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); | |
451 | c->eax = signature[0]; | |
452 | ||
453 | c = &cpuid_data.entries[cpuid_i++]; | |
454 | memset(c, 0, sizeof(*c)); | |
455 | c->function = HYPERV_CPUID_VERSION; | |
456 | c->eax = 0x00001bbc; | |
457 | c->ebx = 0x00060001; | |
458 | ||
459 | c = &cpuid_data.entries[cpuid_i++]; | |
460 | memset(c, 0, sizeof(*c)); | |
461 | c->function = HYPERV_CPUID_FEATURES; | |
462 | if (hyperv_relaxed_timing_enabled()) { | |
463 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
464 | } | |
465 | if (hyperv_vapic_recommended()) { | |
466 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
467 | c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE; | |
468 | } | |
469 | ||
470 | c = &cpuid_data.entries[cpuid_i++]; | |
471 | memset(c, 0, sizeof(*c)); | |
472 | c->function = HYPERV_CPUID_ENLIGHTMENT_INFO; | |
473 | if (hyperv_relaxed_timing_enabled()) { | |
474 | c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED; | |
475 | } | |
476 | if (hyperv_vapic_recommended()) { | |
477 | c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED; | |
478 | } | |
479 | c->ebx = hyperv_get_spinlock_retries(); | |
480 | ||
481 | c = &cpuid_data.entries[cpuid_i++]; | |
482 | memset(c, 0, sizeof(*c)); | |
483 | c->function = HYPERV_CPUID_IMPLEMENT_LIMITS; | |
484 | c->eax = 0x40; | |
485 | c->ebx = 0x40; | |
486 | ||
487 | c = &cpuid_data.entries[cpuid_i++]; | |
488 | memset(c, 0, sizeof(*c)); | |
489 | c->function = KVM_CPUID_SIGNATURE_NEXT; | |
490 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
491 | c->eax = 0; | |
492 | c->ebx = signature[0]; | |
493 | c->ecx = signature[1]; | |
494 | c->edx = signature[2]; | |
495 | } | |
496 | ||
0c31b744 | 497 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); |
bb0300dc | 498 | |
bc9a839d MT |
499 | has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI); |
500 | ||
a33609ca | 501 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
502 | |
503 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 504 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
505 | |
506 | switch (i) { | |
a36b1029 AL |
507 | case 2: { |
508 | /* Keep reading function 2 till all the input is received */ | |
509 | int times; | |
510 | ||
a36b1029 | 511 | c->function = i; |
a33609ca AL |
512 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
513 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
514 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
515 | times = c->eax & 0xff; | |
a36b1029 AL |
516 | |
517 | for (j = 1; j < times; ++j) { | |
a33609ca | 518 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 519 | c->function = i; |
a33609ca AL |
520 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
521 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
522 | } |
523 | break; | |
524 | } | |
486bd5a2 AL |
525 | case 4: |
526 | case 0xb: | |
527 | case 0xd: | |
528 | for (j = 0; ; j++) { | |
31e8c696 AP |
529 | if (i == 0xd && j == 64) { |
530 | break; | |
531 | } | |
486bd5a2 AL |
532 | c->function = i; |
533 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
534 | c->index = j; | |
a33609ca | 535 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 536 | |
b9bec74b | 537 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 538 | break; |
b9bec74b JK |
539 | } |
540 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 541 | break; |
b9bec74b JK |
542 | } |
543 | if (i == 0xd && c->eax == 0) { | |
31e8c696 | 544 | continue; |
b9bec74b | 545 | } |
a33609ca | 546 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
547 | } |
548 | break; | |
549 | default: | |
486bd5a2 | 550 | c->function = i; |
a33609ca AL |
551 | c->flags = 0; |
552 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
553 | break; |
554 | } | |
05330448 | 555 | } |
a33609ca | 556 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
557 | |
558 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 559 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 560 | |
05330448 | 561 | c->function = i; |
a33609ca AL |
562 | c->flags = 0; |
563 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
564 | } |
565 | ||
b3baa152 BW |
566 | /* Call Centaur's CPUID instructions they are supported. */ |
567 | if (env->cpuid_xlevel2 > 0) { | |
b3baa152 BW |
568 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); |
569 | ||
570 | for (i = 0xC0000000; i <= limit; i++) { | |
571 | c = &cpuid_data.entries[cpuid_i++]; | |
572 | ||
573 | c->function = i; | |
574 | c->flags = 0; | |
575 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
576 | } | |
577 | } | |
578 | ||
05330448 AL |
579 | cpuid_data.cpuid.nent = cpuid_i; |
580 | ||
e7701825 MT |
581 | if (((env->cpuid_version >> 8)&0xF) >= 6 |
582 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
a60f24b5 | 583 | && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) { |
e7701825 MT |
584 | uint64_t mcg_cap; |
585 | int banks; | |
32a42024 | 586 | int ret; |
e7701825 | 587 | |
a60f24b5 | 588 | ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); |
75d49497 JK |
589 | if (ret < 0) { |
590 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
591 | return ret; | |
e7701825 | 592 | } |
75d49497 JK |
593 | |
594 | if (banks > MCE_BANKS_DEF) { | |
595 | banks = MCE_BANKS_DEF; | |
596 | } | |
597 | mcg_cap &= MCE_CAP_DEF; | |
598 | mcg_cap |= banks; | |
1bc22652 | 599 | ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap); |
75d49497 JK |
600 | if (ret < 0) { |
601 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
602 | return ret; | |
603 | } | |
604 | ||
605 | env->mcg_cap = mcg_cap; | |
e7701825 | 606 | } |
e7701825 | 607 | |
b8cc45d6 GC |
608 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
609 | ||
7e680753 | 610 | cpuid_data.cpuid.padding = 0; |
1bc22652 | 611 | r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); |
fdc9c41a JK |
612 | if (r) { |
613 | return r; | |
614 | } | |
e7429073 | 615 | |
a60f24b5 | 616 | r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL); |
e7429073 | 617 | if (r && env->tsc_khz) { |
1bc22652 | 618 | r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz); |
e7429073 JR |
619 | if (r < 0) { |
620 | fprintf(stderr, "KVM_SET_TSC_KHZ failed\n"); | |
621 | return r; | |
622 | } | |
623 | } | |
e7429073 | 624 | |
fabacc0f JK |
625 | if (kvm_has_xsave()) { |
626 | env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
627 | } | |
628 | ||
e7429073 | 629 | return 0; |
05330448 AL |
630 | } |
631 | ||
20d695a9 | 632 | void kvm_arch_reset_vcpu(CPUState *cs) |
caa5af0f | 633 | { |
20d695a9 AF |
634 | X86CPU *cpu = X86_CPU(cs); |
635 | CPUX86State *env = &cpu->env; | |
dd673288 | 636 | |
e73223a5 | 637 | env->exception_injected = -1; |
0e607a80 | 638 | env->interrupt_injected = -1; |
1a5e9d2f | 639 | env->xcr0 = 1; |
ddced198 | 640 | if (kvm_irqchip_in_kernel()) { |
dd673288 | 641 | env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : |
ddced198 MT |
642 | KVM_MP_STATE_UNINITIALIZED; |
643 | } else { | |
644 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
645 | } | |
caa5af0f JK |
646 | } |
647 | ||
c3a3a7d3 | 648 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 649 | { |
75b10c43 | 650 | static int kvm_supported_msrs; |
c3a3a7d3 | 651 | int ret = 0; |
05330448 AL |
652 | |
653 | /* first time */ | |
75b10c43 | 654 | if (kvm_supported_msrs == 0) { |
05330448 AL |
655 | struct kvm_msr_list msr_list, *kvm_msr_list; |
656 | ||
75b10c43 | 657 | kvm_supported_msrs = -1; |
05330448 AL |
658 | |
659 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
660 | * save/restore */ | |
4c9f7372 | 661 | msr_list.nmsrs = 0; |
c3a3a7d3 | 662 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 663 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 664 | return ret; |
6fb6d245 | 665 | } |
d9db889f JK |
666 | /* Old kernel modules had a bug and could write beyond the provided |
667 | memory. Allocate at least a safe amount of 1K. */ | |
7267c094 | 668 | kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + |
d9db889f JK |
669 | msr_list.nmsrs * |
670 | sizeof(msr_list.indices[0]))); | |
05330448 | 671 | |
55308450 | 672 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 673 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
674 | if (ret >= 0) { |
675 | int i; | |
676 | ||
677 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
678 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 679 | has_msr_star = true; |
75b10c43 MT |
680 | continue; |
681 | } | |
682 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 683 | has_msr_hsave_pa = true; |
75b10c43 | 684 | continue; |
05330448 | 685 | } |
aa82ba54 LJ |
686 | if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { |
687 | has_msr_tsc_deadline = true; | |
688 | continue; | |
689 | } | |
21e87c46 AK |
690 | if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) { |
691 | has_msr_misc_enable = true; | |
692 | continue; | |
693 | } | |
05330448 AL |
694 | } |
695 | } | |
696 | ||
7267c094 | 697 | g_free(kvm_msr_list); |
05330448 AL |
698 | } |
699 | ||
c3a3a7d3 | 700 | return ret; |
05330448 AL |
701 | } |
702 | ||
cad1e282 | 703 | int kvm_arch_init(KVMState *s) |
20420430 | 704 | { |
39d6960a | 705 | QemuOptsList *list = qemu_find_opts("machine"); |
11076198 | 706 | uint64_t identity_base = 0xfffbc000; |
39d6960a | 707 | uint64_t shadow_mem; |
20420430 | 708 | int ret; |
25d2e361 | 709 | struct utsname utsname; |
20420430 | 710 | |
c3a3a7d3 | 711 | ret = kvm_get_supported_msrs(s); |
20420430 | 712 | if (ret < 0) { |
20420430 SY |
713 | return ret; |
714 | } | |
25d2e361 MT |
715 | |
716 | uname(&utsname); | |
717 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
718 | ||
4c5b10b7 | 719 | /* |
11076198 JK |
720 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
721 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
722 | * Since these must be part of guest physical memory, we need to allocate | |
723 | * them, both by setting their start addresses in the kernel and by | |
724 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
725 | * | |
726 | * Older KVM versions may not support setting the identity map base. In | |
727 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
728 | * size. | |
4c5b10b7 | 729 | */ |
11076198 JK |
730 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { |
731 | /* Allows up to 16M BIOSes. */ | |
732 | identity_base = 0xfeffc000; | |
733 | ||
734 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
735 | if (ret < 0) { | |
736 | return ret; | |
737 | } | |
4c5b10b7 | 738 | } |
e56ff191 | 739 | |
11076198 JK |
740 | /* Set TSS base one page after EPT identity map. */ |
741 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
742 | if (ret < 0) { |
743 | return ret; | |
744 | } | |
745 | ||
11076198 JK |
746 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
747 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 748 | if (ret < 0) { |
11076198 | 749 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
750 | return ret; |
751 | } | |
3c85e74f | 752 | qemu_register_reset(kvm_unpoison_all, NULL); |
20420430 | 753 | |
39d6960a JK |
754 | if (!QTAILQ_EMPTY(&list->head)) { |
755 | shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head), | |
756 | "kvm_shadow_mem", -1); | |
757 | if (shadow_mem != -1) { | |
758 | shadow_mem /= 4096; | |
759 | ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); | |
760 | if (ret < 0) { | |
761 | return ret; | |
762 | } | |
763 | } | |
764 | } | |
11076198 | 765 | return 0; |
05330448 | 766 | } |
b9bec74b | 767 | |
05330448 AL |
768 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
769 | { | |
770 | lhs->selector = rhs->selector; | |
771 | lhs->base = rhs->base; | |
772 | lhs->limit = rhs->limit; | |
773 | lhs->type = 3; | |
774 | lhs->present = 1; | |
775 | lhs->dpl = 3; | |
776 | lhs->db = 0; | |
777 | lhs->s = 1; | |
778 | lhs->l = 0; | |
779 | lhs->g = 0; | |
780 | lhs->avl = 0; | |
781 | lhs->unusable = 0; | |
782 | } | |
783 | ||
784 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
785 | { | |
786 | unsigned flags = rhs->flags; | |
787 | lhs->selector = rhs->selector; | |
788 | lhs->base = rhs->base; | |
789 | lhs->limit = rhs->limit; | |
790 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
791 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 792 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
793 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
794 | lhs->s = (flags & DESC_S_MASK) != 0; | |
795 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
796 | lhs->g = (flags & DESC_G_MASK) != 0; | |
797 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
798 | lhs->unusable = 0; | |
7e680753 | 799 | lhs->padding = 0; |
05330448 AL |
800 | } |
801 | ||
802 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
803 | { | |
804 | lhs->selector = rhs->selector; | |
805 | lhs->base = rhs->base; | |
806 | lhs->limit = rhs->limit; | |
b9bec74b JK |
807 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
808 | (rhs->present * DESC_P_MASK) | | |
809 | (rhs->dpl << DESC_DPL_SHIFT) | | |
810 | (rhs->db << DESC_B_SHIFT) | | |
811 | (rhs->s * DESC_S_MASK) | | |
812 | (rhs->l << DESC_L_SHIFT) | | |
813 | (rhs->g * DESC_G_MASK) | | |
814 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
815 | } |
816 | ||
817 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
818 | { | |
b9bec74b | 819 | if (set) { |
05330448 | 820 | *kvm_reg = *qemu_reg; |
b9bec74b | 821 | } else { |
05330448 | 822 | *qemu_reg = *kvm_reg; |
b9bec74b | 823 | } |
05330448 AL |
824 | } |
825 | ||
1bc22652 | 826 | static int kvm_getput_regs(X86CPU *cpu, int set) |
05330448 | 827 | { |
1bc22652 | 828 | CPUX86State *env = &cpu->env; |
05330448 AL |
829 | struct kvm_regs regs; |
830 | int ret = 0; | |
831 | ||
832 | if (!set) { | |
1bc22652 | 833 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); |
b9bec74b | 834 | if (ret < 0) { |
05330448 | 835 | return ret; |
b9bec74b | 836 | } |
05330448 AL |
837 | } |
838 | ||
839 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
840 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
841 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
842 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
843 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
844 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
845 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
846 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
847 | #ifdef TARGET_X86_64 | |
848 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
849 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
850 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
851 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
852 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
853 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
854 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
855 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
856 | #endif | |
857 | ||
858 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
859 | kvm_getput_reg(®s.rip, &env->eip, set); | |
860 | ||
b9bec74b | 861 | if (set) { |
1bc22652 | 862 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); |
b9bec74b | 863 | } |
05330448 AL |
864 | |
865 | return ret; | |
866 | } | |
867 | ||
1bc22652 | 868 | static int kvm_put_fpu(X86CPU *cpu) |
05330448 | 869 | { |
1bc22652 | 870 | CPUX86State *env = &cpu->env; |
05330448 AL |
871 | struct kvm_fpu fpu; |
872 | int i; | |
873 | ||
874 | memset(&fpu, 0, sizeof fpu); | |
875 | fpu.fsw = env->fpus & ~(7 << 11); | |
876 | fpu.fsw |= (env->fpstt & 7) << 11; | |
877 | fpu.fcw = env->fpuc; | |
42cc8fa6 JK |
878 | fpu.last_opcode = env->fpop; |
879 | fpu.last_ip = env->fpip; | |
880 | fpu.last_dp = env->fpdp; | |
b9bec74b JK |
881 | for (i = 0; i < 8; ++i) { |
882 | fpu.ftwx |= (!env->fptags[i]) << i; | |
883 | } | |
05330448 AL |
884 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
885 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
886 | fpu.mxcsr = env->mxcsr; | |
887 | ||
1bc22652 | 888 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu); |
05330448 AL |
889 | } |
890 | ||
6b42494b JK |
891 | #define XSAVE_FCW_FSW 0 |
892 | #define XSAVE_FTW_FOP 1 | |
f1665b21 SY |
893 | #define XSAVE_CWD_RIP 2 |
894 | #define XSAVE_CWD_RDP 4 | |
895 | #define XSAVE_MXCSR 6 | |
896 | #define XSAVE_ST_SPACE 8 | |
897 | #define XSAVE_XMM_SPACE 40 | |
898 | #define XSAVE_XSTATE_BV 128 | |
899 | #define XSAVE_YMMH_SPACE 144 | |
f1665b21 | 900 | |
1bc22652 | 901 | static int kvm_put_xsave(X86CPU *cpu) |
f1665b21 | 902 | { |
1bc22652 | 903 | CPUX86State *env = &cpu->env; |
fabacc0f | 904 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
42cc8fa6 | 905 | uint16_t cwd, swd, twd; |
fabacc0f | 906 | int i, r; |
f1665b21 | 907 | |
b9bec74b | 908 | if (!kvm_has_xsave()) { |
1bc22652 | 909 | return kvm_put_fpu(cpu); |
b9bec74b | 910 | } |
f1665b21 | 911 | |
f1665b21 | 912 | memset(xsave, 0, sizeof(struct kvm_xsave)); |
6115c0a8 | 913 | twd = 0; |
f1665b21 SY |
914 | swd = env->fpus & ~(7 << 11); |
915 | swd |= (env->fpstt & 7) << 11; | |
916 | cwd = env->fpuc; | |
b9bec74b | 917 | for (i = 0; i < 8; ++i) { |
f1665b21 | 918 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 919 | } |
6b42494b JK |
920 | xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd; |
921 | xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd; | |
42cc8fa6 JK |
922 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); |
923 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
f1665b21 SY |
924 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
925 | sizeof env->fpregs); | |
926 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
927 | sizeof env->xmm_regs); | |
928 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
929 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
930 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
931 | sizeof env->ymmh_regs); | |
1bc22652 | 932 | r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); |
0f53994f | 933 | return r; |
f1665b21 SY |
934 | } |
935 | ||
1bc22652 | 936 | static int kvm_put_xcrs(X86CPU *cpu) |
f1665b21 | 937 | { |
1bc22652 | 938 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
939 | struct kvm_xcrs xcrs; |
940 | ||
b9bec74b | 941 | if (!kvm_has_xcrs()) { |
f1665b21 | 942 | return 0; |
b9bec74b | 943 | } |
f1665b21 SY |
944 | |
945 | xcrs.nr_xcrs = 1; | |
946 | xcrs.flags = 0; | |
947 | xcrs.xcrs[0].xcr = 0; | |
948 | xcrs.xcrs[0].value = env->xcr0; | |
1bc22652 | 949 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); |
f1665b21 SY |
950 | } |
951 | ||
1bc22652 | 952 | static int kvm_put_sregs(X86CPU *cpu) |
05330448 | 953 | { |
1bc22652 | 954 | CPUX86State *env = &cpu->env; |
05330448 AL |
955 | struct kvm_sregs sregs; |
956 | ||
0e607a80 JK |
957 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
958 | if (env->interrupt_injected >= 0) { | |
959 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
960 | (uint64_t)1 << (env->interrupt_injected % 64); | |
961 | } | |
05330448 AL |
962 | |
963 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
964 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
965 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
966 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
967 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
968 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
969 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 970 | } else { |
b9bec74b JK |
971 | set_seg(&sregs.cs, &env->segs[R_CS]); |
972 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
973 | set_seg(&sregs.es, &env->segs[R_ES]); | |
974 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
975 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
976 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
977 | } |
978 | ||
979 | set_seg(&sregs.tr, &env->tr); | |
980 | set_seg(&sregs.ldt, &env->ldt); | |
981 | ||
982 | sregs.idt.limit = env->idt.limit; | |
983 | sregs.idt.base = env->idt.base; | |
7e680753 | 984 | memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); |
05330448 AL |
985 | sregs.gdt.limit = env->gdt.limit; |
986 | sregs.gdt.base = env->gdt.base; | |
7e680753 | 987 | memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); |
05330448 AL |
988 | |
989 | sregs.cr0 = env->cr[0]; | |
990 | sregs.cr2 = env->cr[2]; | |
991 | sregs.cr3 = env->cr[3]; | |
992 | sregs.cr4 = env->cr[4]; | |
993 | ||
4a942cea BS |
994 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
995 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
996 | |
997 | sregs.efer = env->efer; | |
998 | ||
1bc22652 | 999 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); |
05330448 AL |
1000 | } |
1001 | ||
1002 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
1003 | uint32_t index, uint64_t value) | |
1004 | { | |
1005 | entry->index = index; | |
1006 | entry->data = value; | |
1007 | } | |
1008 | ||
1bc22652 | 1009 | static int kvm_put_msrs(X86CPU *cpu, int level) |
05330448 | 1010 | { |
1bc22652 | 1011 | CPUX86State *env = &cpu->env; |
05330448 AL |
1012 | struct { |
1013 | struct kvm_msrs info; | |
1014 | struct kvm_msr_entry entries[100]; | |
1015 | } msr_data; | |
1016 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 1017 | int n = 0; |
05330448 AL |
1018 | |
1019 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
1020 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
1021 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
0c03266a | 1022 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); |
c3a3a7d3 | 1023 | if (has_msr_star) { |
b9bec74b JK |
1024 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
1025 | } | |
c3a3a7d3 | 1026 | if (has_msr_hsave_pa) { |
75b10c43 | 1027 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 1028 | } |
aa82ba54 LJ |
1029 | if (has_msr_tsc_deadline) { |
1030 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); | |
1031 | } | |
21e87c46 AK |
1032 | if (has_msr_misc_enable) { |
1033 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, | |
1034 | env->msr_ia32_misc_enable); | |
1035 | } | |
05330448 | 1036 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1037 | if (lm_capable_kernel) { |
1038 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
1039 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
1040 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
1041 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
1042 | } | |
05330448 | 1043 | #endif |
ea643051 | 1044 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
1045 | /* |
1046 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
1047 | * writeback. Until this is fixed, we only write the offset to SMP | |
1048 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
1049 | * huge jump-backs that would occur without any writeback at all. | |
1050 | */ | |
1051 | if (smp_cpus == 1 || env->tsc != 0) { | |
1052 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
1053 | } | |
ff5c186b JK |
1054 | } |
1055 | /* | |
1056 | * The following paravirtual MSRs have side effects on the guest or are | |
1057 | * too heavy for normal writeback. Limit them to reset or full state | |
1058 | * updates. | |
1059 | */ | |
1060 | if (level >= KVM_PUT_RESET_STATE) { | |
ea643051 JK |
1061 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
1062 | env->system_time_msr); | |
1063 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
c5999bfc JK |
1064 | if (has_msr_async_pf_en) { |
1065 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
1066 | env->async_pf_en_msr); | |
1067 | } | |
bc9a839d MT |
1068 | if (has_msr_pv_eoi_en) { |
1069 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN, | |
1070 | env->pv_eoi_en_msr); | |
1071 | } | |
eab70139 VR |
1072 | if (hyperv_hypercall_available()) { |
1073 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0); | |
1074 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0); | |
1075 | } | |
1076 | if (hyperv_vapic_recommended()) { | |
1077 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0); | |
1078 | } | |
ea643051 | 1079 | } |
57780495 | 1080 | if (env->mcg_cap) { |
d8da8574 | 1081 | int i; |
b9bec74b | 1082 | |
c34d440a JK |
1083 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
1084 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
1085 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
1086 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
57780495 MT |
1087 | } |
1088 | } | |
1a03675d | 1089 | |
05330448 AL |
1090 | msr_data.info.nmsrs = n; |
1091 | ||
1bc22652 | 1092 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); |
05330448 AL |
1093 | |
1094 | } | |
1095 | ||
1096 | ||
1bc22652 | 1097 | static int kvm_get_fpu(X86CPU *cpu) |
05330448 | 1098 | { |
1bc22652 | 1099 | CPUX86State *env = &cpu->env; |
05330448 AL |
1100 | struct kvm_fpu fpu; |
1101 | int i, ret; | |
1102 | ||
1bc22652 | 1103 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu); |
b9bec74b | 1104 | if (ret < 0) { |
05330448 | 1105 | return ret; |
b9bec74b | 1106 | } |
05330448 AL |
1107 | |
1108 | env->fpstt = (fpu.fsw >> 11) & 7; | |
1109 | env->fpus = fpu.fsw; | |
1110 | env->fpuc = fpu.fcw; | |
42cc8fa6 JK |
1111 | env->fpop = fpu.last_opcode; |
1112 | env->fpip = fpu.last_ip; | |
1113 | env->fpdp = fpu.last_dp; | |
b9bec74b JK |
1114 | for (i = 0; i < 8; ++i) { |
1115 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
1116 | } | |
05330448 AL |
1117 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
1118 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
1119 | env->mxcsr = fpu.mxcsr; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1bc22652 | 1124 | static int kvm_get_xsave(X86CPU *cpu) |
f1665b21 | 1125 | { |
1bc22652 | 1126 | CPUX86State *env = &cpu->env; |
fabacc0f | 1127 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
f1665b21 | 1128 | int ret, i; |
42cc8fa6 | 1129 | uint16_t cwd, swd, twd; |
f1665b21 | 1130 | |
b9bec74b | 1131 | if (!kvm_has_xsave()) { |
1bc22652 | 1132 | return kvm_get_fpu(cpu); |
b9bec74b | 1133 | } |
f1665b21 | 1134 | |
1bc22652 | 1135 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); |
0f53994f | 1136 | if (ret < 0) { |
f1665b21 | 1137 | return ret; |
0f53994f | 1138 | } |
f1665b21 | 1139 | |
6b42494b JK |
1140 | cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW]; |
1141 | swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16); | |
1142 | twd = (uint16_t)xsave->region[XSAVE_FTW_FOP]; | |
1143 | env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16); | |
f1665b21 SY |
1144 | env->fpstt = (swd >> 11) & 7; |
1145 | env->fpus = swd; | |
1146 | env->fpuc = cwd; | |
b9bec74b | 1147 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1148 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 1149 | } |
42cc8fa6 JK |
1150 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); |
1151 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
f1665b21 SY |
1152 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
1153 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
1154 | sizeof env->fpregs); | |
1155 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
1156 | sizeof env->xmm_regs); | |
1157 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
1158 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
1159 | sizeof env->ymmh_regs); | |
1160 | return 0; | |
f1665b21 SY |
1161 | } |
1162 | ||
1bc22652 | 1163 | static int kvm_get_xcrs(X86CPU *cpu) |
f1665b21 | 1164 | { |
1bc22652 | 1165 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
1166 | int i, ret; |
1167 | struct kvm_xcrs xcrs; | |
1168 | ||
b9bec74b | 1169 | if (!kvm_has_xcrs()) { |
f1665b21 | 1170 | return 0; |
b9bec74b | 1171 | } |
f1665b21 | 1172 | |
1bc22652 | 1173 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); |
b9bec74b | 1174 | if (ret < 0) { |
f1665b21 | 1175 | return ret; |
b9bec74b | 1176 | } |
f1665b21 | 1177 | |
b9bec74b | 1178 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
1179 | /* Only support xcr0 now */ |
1180 | if (xcrs.xcrs[0].xcr == 0) { | |
1181 | env->xcr0 = xcrs.xcrs[0].value; | |
1182 | break; | |
1183 | } | |
b9bec74b | 1184 | } |
f1665b21 | 1185 | return 0; |
f1665b21 SY |
1186 | } |
1187 | ||
1bc22652 | 1188 | static int kvm_get_sregs(X86CPU *cpu) |
05330448 | 1189 | { |
1bc22652 | 1190 | CPUX86State *env = &cpu->env; |
05330448 AL |
1191 | struct kvm_sregs sregs; |
1192 | uint32_t hflags; | |
0e607a80 | 1193 | int bit, i, ret; |
05330448 | 1194 | |
1bc22652 | 1195 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); |
b9bec74b | 1196 | if (ret < 0) { |
05330448 | 1197 | return ret; |
b9bec74b | 1198 | } |
05330448 | 1199 | |
0e607a80 JK |
1200 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
1201 | to find it and save its number instead (-1 for none). */ | |
1202 | env->interrupt_injected = -1; | |
1203 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1204 | if (sregs.interrupt_bitmap[i]) { | |
1205 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1206 | env->interrupt_injected = i * 64 + bit; | |
1207 | break; | |
1208 | } | |
1209 | } | |
05330448 AL |
1210 | |
1211 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1212 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1213 | get_seg(&env->segs[R_ES], &sregs.es); | |
1214 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1215 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1216 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1217 | ||
1218 | get_seg(&env->tr, &sregs.tr); | |
1219 | get_seg(&env->ldt, &sregs.ldt); | |
1220 | ||
1221 | env->idt.limit = sregs.idt.limit; | |
1222 | env->idt.base = sregs.idt.base; | |
1223 | env->gdt.limit = sregs.gdt.limit; | |
1224 | env->gdt.base = sregs.gdt.base; | |
1225 | ||
1226 | env->cr[0] = sregs.cr0; | |
1227 | env->cr[2] = sregs.cr2; | |
1228 | env->cr[3] = sregs.cr3; | |
1229 | env->cr[4] = sregs.cr4; | |
1230 | ||
05330448 | 1231 | env->efer = sregs.efer; |
cce47516 JK |
1232 | |
1233 | /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ | |
05330448 | 1234 | |
b9bec74b JK |
1235 | #define HFLAG_COPY_MASK \ |
1236 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1237 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1238 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1239 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1240 | |
1241 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1242 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1243 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1244 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1245 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1246 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1247 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1248 | |
1249 | if (env->efer & MSR_EFER_LMA) { | |
1250 | hflags |= HF_LMA_MASK; | |
1251 | } | |
1252 | ||
1253 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1254 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1255 | } else { | |
1256 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1257 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1258 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1259 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1260 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1261 | !(hflags & HF_CS32_MASK)) { | |
1262 | hflags |= HF_ADDSEG_MASK; | |
1263 | } else { | |
1264 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1265 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1266 | } | |
05330448 AL |
1267 | } |
1268 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1269 | |
1270 | return 0; | |
1271 | } | |
1272 | ||
1bc22652 | 1273 | static int kvm_get_msrs(X86CPU *cpu) |
05330448 | 1274 | { |
1bc22652 | 1275 | CPUX86State *env = &cpu->env; |
05330448 AL |
1276 | struct { |
1277 | struct kvm_msrs info; | |
1278 | struct kvm_msr_entry entries[100]; | |
1279 | } msr_data; | |
1280 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1281 | int ret, i, n; | |
1282 | ||
1283 | n = 0; | |
1284 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1285 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1286 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
0c03266a | 1287 | msrs[n++].index = MSR_PAT; |
c3a3a7d3 | 1288 | if (has_msr_star) { |
b9bec74b JK |
1289 | msrs[n++].index = MSR_STAR; |
1290 | } | |
c3a3a7d3 | 1291 | if (has_msr_hsave_pa) { |
75b10c43 | 1292 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1293 | } |
aa82ba54 LJ |
1294 | if (has_msr_tsc_deadline) { |
1295 | msrs[n++].index = MSR_IA32_TSCDEADLINE; | |
1296 | } | |
21e87c46 AK |
1297 | if (has_msr_misc_enable) { |
1298 | msrs[n++].index = MSR_IA32_MISC_ENABLE; | |
1299 | } | |
b8cc45d6 GC |
1300 | |
1301 | if (!env->tsc_valid) { | |
1302 | msrs[n++].index = MSR_IA32_TSC; | |
1354869c | 1303 | env->tsc_valid = !runstate_is_running(); |
b8cc45d6 GC |
1304 | } |
1305 | ||
05330448 | 1306 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1307 | if (lm_capable_kernel) { |
1308 | msrs[n++].index = MSR_CSTAR; | |
1309 | msrs[n++].index = MSR_KERNELGSBASE; | |
1310 | msrs[n++].index = MSR_FMASK; | |
1311 | msrs[n++].index = MSR_LSTAR; | |
1312 | } | |
05330448 | 1313 | #endif |
1a03675d GC |
1314 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1315 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
c5999bfc JK |
1316 | if (has_msr_async_pf_en) { |
1317 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1318 | } | |
bc9a839d MT |
1319 | if (has_msr_pv_eoi_en) { |
1320 | msrs[n++].index = MSR_KVM_PV_EOI_EN; | |
1321 | } | |
1a03675d | 1322 | |
57780495 MT |
1323 | if (env->mcg_cap) { |
1324 | msrs[n++].index = MSR_MCG_STATUS; | |
1325 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1326 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1327 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1328 | } |
57780495 | 1329 | } |
57780495 | 1330 | |
05330448 | 1331 | msr_data.info.nmsrs = n; |
1bc22652 | 1332 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); |
b9bec74b | 1333 | if (ret < 0) { |
05330448 | 1334 | return ret; |
b9bec74b | 1335 | } |
05330448 AL |
1336 | |
1337 | for (i = 0; i < ret; i++) { | |
1338 | switch (msrs[i].index) { | |
1339 | case MSR_IA32_SYSENTER_CS: | |
1340 | env->sysenter_cs = msrs[i].data; | |
1341 | break; | |
1342 | case MSR_IA32_SYSENTER_ESP: | |
1343 | env->sysenter_esp = msrs[i].data; | |
1344 | break; | |
1345 | case MSR_IA32_SYSENTER_EIP: | |
1346 | env->sysenter_eip = msrs[i].data; | |
1347 | break; | |
0c03266a JK |
1348 | case MSR_PAT: |
1349 | env->pat = msrs[i].data; | |
1350 | break; | |
05330448 AL |
1351 | case MSR_STAR: |
1352 | env->star = msrs[i].data; | |
1353 | break; | |
1354 | #ifdef TARGET_X86_64 | |
1355 | case MSR_CSTAR: | |
1356 | env->cstar = msrs[i].data; | |
1357 | break; | |
1358 | case MSR_KERNELGSBASE: | |
1359 | env->kernelgsbase = msrs[i].data; | |
1360 | break; | |
1361 | case MSR_FMASK: | |
1362 | env->fmask = msrs[i].data; | |
1363 | break; | |
1364 | case MSR_LSTAR: | |
1365 | env->lstar = msrs[i].data; | |
1366 | break; | |
1367 | #endif | |
1368 | case MSR_IA32_TSC: | |
1369 | env->tsc = msrs[i].data; | |
1370 | break; | |
aa82ba54 LJ |
1371 | case MSR_IA32_TSCDEADLINE: |
1372 | env->tsc_deadline = msrs[i].data; | |
1373 | break; | |
aa851e36 MT |
1374 | case MSR_VM_HSAVE_PA: |
1375 | env->vm_hsave = msrs[i].data; | |
1376 | break; | |
1a03675d GC |
1377 | case MSR_KVM_SYSTEM_TIME: |
1378 | env->system_time_msr = msrs[i].data; | |
1379 | break; | |
1380 | case MSR_KVM_WALL_CLOCK: | |
1381 | env->wall_clock_msr = msrs[i].data; | |
1382 | break; | |
57780495 MT |
1383 | case MSR_MCG_STATUS: |
1384 | env->mcg_status = msrs[i].data; | |
1385 | break; | |
1386 | case MSR_MCG_CTL: | |
1387 | env->mcg_ctl = msrs[i].data; | |
1388 | break; | |
21e87c46 AK |
1389 | case MSR_IA32_MISC_ENABLE: |
1390 | env->msr_ia32_misc_enable = msrs[i].data; | |
1391 | break; | |
57780495 | 1392 | default: |
57780495 MT |
1393 | if (msrs[i].index >= MSR_MC0_CTL && |
1394 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1395 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 | 1396 | } |
d8da8574 | 1397 | break; |
f6584ee2 GN |
1398 | case MSR_KVM_ASYNC_PF_EN: |
1399 | env->async_pf_en_msr = msrs[i].data; | |
1400 | break; | |
bc9a839d MT |
1401 | case MSR_KVM_PV_EOI_EN: |
1402 | env->pv_eoi_en_msr = msrs[i].data; | |
1403 | break; | |
05330448 AL |
1404 | } |
1405 | } | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
1bc22652 | 1410 | static int kvm_put_mp_state(X86CPU *cpu) |
9bdbe550 | 1411 | { |
1bc22652 | 1412 | struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; |
9bdbe550 | 1413 | |
1bc22652 | 1414 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); |
9bdbe550 HB |
1415 | } |
1416 | ||
23d02d9b | 1417 | static int kvm_get_mp_state(X86CPU *cpu) |
9bdbe550 | 1418 | { |
23d02d9b | 1419 | CPUX86State *env = &cpu->env; |
9bdbe550 HB |
1420 | struct kvm_mp_state mp_state; |
1421 | int ret; | |
1422 | ||
1bc22652 | 1423 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); |
9bdbe550 HB |
1424 | if (ret < 0) { |
1425 | return ret; | |
1426 | } | |
1427 | env->mp_state = mp_state.mp_state; | |
c14750e8 JK |
1428 | if (kvm_irqchip_in_kernel()) { |
1429 | env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
1430 | } | |
9bdbe550 HB |
1431 | return 0; |
1432 | } | |
1433 | ||
1bc22652 | 1434 | static int kvm_get_apic(X86CPU *cpu) |
680c1c6f | 1435 | { |
1bc22652 | 1436 | CPUX86State *env = &cpu->env; |
680c1c6f JK |
1437 | DeviceState *apic = env->apic_state; |
1438 | struct kvm_lapic_state kapic; | |
1439 | int ret; | |
1440 | ||
3d4b2649 | 1441 | if (apic && kvm_irqchip_in_kernel()) { |
1bc22652 | 1442 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); |
680c1c6f JK |
1443 | if (ret < 0) { |
1444 | return ret; | |
1445 | } | |
1446 | ||
1447 | kvm_get_apic_state(apic, &kapic); | |
1448 | } | |
1449 | return 0; | |
1450 | } | |
1451 | ||
1bc22652 | 1452 | static int kvm_put_apic(X86CPU *cpu) |
680c1c6f | 1453 | { |
1bc22652 | 1454 | CPUX86State *env = &cpu->env; |
680c1c6f JK |
1455 | DeviceState *apic = env->apic_state; |
1456 | struct kvm_lapic_state kapic; | |
1457 | ||
3d4b2649 | 1458 | if (apic && kvm_irqchip_in_kernel()) { |
680c1c6f JK |
1459 | kvm_put_apic_state(apic, &kapic); |
1460 | ||
1bc22652 | 1461 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic); |
680c1c6f JK |
1462 | } |
1463 | return 0; | |
1464 | } | |
1465 | ||
1bc22652 | 1466 | static int kvm_put_vcpu_events(X86CPU *cpu, int level) |
a0fb002c | 1467 | { |
1bc22652 | 1468 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
1469 | struct kvm_vcpu_events events; |
1470 | ||
1471 | if (!kvm_has_vcpu_events()) { | |
1472 | return 0; | |
1473 | } | |
1474 | ||
31827373 JK |
1475 | events.exception.injected = (env->exception_injected >= 0); |
1476 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1477 | events.exception.has_error_code = env->has_error_code; |
1478 | events.exception.error_code = env->error_code; | |
7e680753 | 1479 | events.exception.pad = 0; |
a0fb002c JK |
1480 | |
1481 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1482 | events.interrupt.nr = env->interrupt_injected; | |
1483 | events.interrupt.soft = env->soft_interrupt; | |
1484 | ||
1485 | events.nmi.injected = env->nmi_injected; | |
1486 | events.nmi.pending = env->nmi_pending; | |
1487 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
7e680753 | 1488 | events.nmi.pad = 0; |
a0fb002c JK |
1489 | |
1490 | events.sipi_vector = env->sipi_vector; | |
1491 | ||
ea643051 JK |
1492 | events.flags = 0; |
1493 | if (level >= KVM_PUT_RESET_STATE) { | |
1494 | events.flags |= | |
1495 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1496 | } | |
aee028b9 | 1497 | |
1bc22652 | 1498 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); |
a0fb002c JK |
1499 | } |
1500 | ||
1bc22652 | 1501 | static int kvm_get_vcpu_events(X86CPU *cpu) |
a0fb002c | 1502 | { |
1bc22652 | 1503 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
1504 | struct kvm_vcpu_events events; |
1505 | int ret; | |
1506 | ||
1507 | if (!kvm_has_vcpu_events()) { | |
1508 | return 0; | |
1509 | } | |
1510 | ||
1bc22652 | 1511 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); |
a0fb002c JK |
1512 | if (ret < 0) { |
1513 | return ret; | |
1514 | } | |
31827373 | 1515 | env->exception_injected = |
a0fb002c JK |
1516 | events.exception.injected ? events.exception.nr : -1; |
1517 | env->has_error_code = events.exception.has_error_code; | |
1518 | env->error_code = events.exception.error_code; | |
1519 | ||
1520 | env->interrupt_injected = | |
1521 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1522 | env->soft_interrupt = events.interrupt.soft; | |
1523 | ||
1524 | env->nmi_injected = events.nmi.injected; | |
1525 | env->nmi_pending = events.nmi.pending; | |
1526 | if (events.nmi.masked) { | |
1527 | env->hflags2 |= HF2_NMI_MASK; | |
1528 | } else { | |
1529 | env->hflags2 &= ~HF2_NMI_MASK; | |
1530 | } | |
1531 | ||
1532 | env->sipi_vector = events.sipi_vector; | |
a0fb002c JK |
1533 | |
1534 | return 0; | |
1535 | } | |
1536 | ||
1bc22652 | 1537 | static int kvm_guest_debug_workarounds(X86CPU *cpu) |
b0b1d690 | 1538 | { |
1bc22652 | 1539 | CPUX86State *env = &cpu->env; |
b0b1d690 | 1540 | int ret = 0; |
b0b1d690 JK |
1541 | unsigned long reinject_trap = 0; |
1542 | ||
1543 | if (!kvm_has_vcpu_events()) { | |
1544 | if (env->exception_injected == 1) { | |
1545 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1546 | } else if (env->exception_injected == 3) { | |
1547 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1548 | } | |
1549 | env->exception_injected = -1; | |
1550 | } | |
1551 | ||
1552 | /* | |
1553 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1554 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1555 | * by updating the debug state once again if single-stepping is on. | |
1556 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1557 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1558 | * reinject them via SET_GUEST_DEBUG. | |
1559 | */ | |
1560 | if (reinject_trap || | |
1561 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1562 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1563 | } | |
b0b1d690 JK |
1564 | return ret; |
1565 | } | |
1566 | ||
1bc22652 | 1567 | static int kvm_put_debugregs(X86CPU *cpu) |
ff44f1a3 | 1568 | { |
1bc22652 | 1569 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
1570 | struct kvm_debugregs dbgregs; |
1571 | int i; | |
1572 | ||
1573 | if (!kvm_has_debugregs()) { | |
1574 | return 0; | |
1575 | } | |
1576 | ||
1577 | for (i = 0; i < 4; i++) { | |
1578 | dbgregs.db[i] = env->dr[i]; | |
1579 | } | |
1580 | dbgregs.dr6 = env->dr[6]; | |
1581 | dbgregs.dr7 = env->dr[7]; | |
1582 | dbgregs.flags = 0; | |
1583 | ||
1bc22652 | 1584 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); |
ff44f1a3 JK |
1585 | } |
1586 | ||
1bc22652 | 1587 | static int kvm_get_debugregs(X86CPU *cpu) |
ff44f1a3 | 1588 | { |
1bc22652 | 1589 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
1590 | struct kvm_debugregs dbgregs; |
1591 | int i, ret; | |
1592 | ||
1593 | if (!kvm_has_debugregs()) { | |
1594 | return 0; | |
1595 | } | |
1596 | ||
1bc22652 | 1597 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); |
ff44f1a3 | 1598 | if (ret < 0) { |
b9bec74b | 1599 | return ret; |
ff44f1a3 JK |
1600 | } |
1601 | for (i = 0; i < 4; i++) { | |
1602 | env->dr[i] = dbgregs.db[i]; | |
1603 | } | |
1604 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1605 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
ff44f1a3 JK |
1606 | |
1607 | return 0; | |
1608 | } | |
1609 | ||
20d695a9 | 1610 | int kvm_arch_put_registers(CPUState *cpu, int level) |
05330448 | 1611 | { |
20d695a9 | 1612 | X86CPU *x86_cpu = X86_CPU(cpu); |
05330448 AL |
1613 | int ret; |
1614 | ||
2fa45344 | 1615 | assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); |
dbaa07c4 | 1616 | |
1bc22652 | 1617 | ret = kvm_getput_regs(x86_cpu, 1); |
b9bec74b | 1618 | if (ret < 0) { |
05330448 | 1619 | return ret; |
b9bec74b | 1620 | } |
1bc22652 | 1621 | ret = kvm_put_xsave(x86_cpu); |
b9bec74b | 1622 | if (ret < 0) { |
f1665b21 | 1623 | return ret; |
b9bec74b | 1624 | } |
1bc22652 | 1625 | ret = kvm_put_xcrs(x86_cpu); |
b9bec74b | 1626 | if (ret < 0) { |
05330448 | 1627 | return ret; |
b9bec74b | 1628 | } |
1bc22652 | 1629 | ret = kvm_put_sregs(x86_cpu); |
b9bec74b | 1630 | if (ret < 0) { |
05330448 | 1631 | return ret; |
b9bec74b | 1632 | } |
ab443475 | 1633 | /* must be before kvm_put_msrs */ |
1bc22652 | 1634 | ret = kvm_inject_mce_oldstyle(x86_cpu); |
ab443475 JK |
1635 | if (ret < 0) { |
1636 | return ret; | |
1637 | } | |
1bc22652 | 1638 | ret = kvm_put_msrs(x86_cpu, level); |
b9bec74b | 1639 | if (ret < 0) { |
05330448 | 1640 | return ret; |
b9bec74b | 1641 | } |
ea643051 | 1642 | if (level >= KVM_PUT_RESET_STATE) { |
1bc22652 | 1643 | ret = kvm_put_mp_state(x86_cpu); |
b9bec74b | 1644 | if (ret < 0) { |
ea643051 | 1645 | return ret; |
b9bec74b | 1646 | } |
1bc22652 | 1647 | ret = kvm_put_apic(x86_cpu); |
680c1c6f JK |
1648 | if (ret < 0) { |
1649 | return ret; | |
1650 | } | |
ea643051 | 1651 | } |
1bc22652 | 1652 | ret = kvm_put_vcpu_events(x86_cpu, level); |
b9bec74b | 1653 | if (ret < 0) { |
a0fb002c | 1654 | return ret; |
b9bec74b | 1655 | } |
1bc22652 | 1656 | ret = kvm_put_debugregs(x86_cpu); |
b9bec74b | 1657 | if (ret < 0) { |
b0b1d690 | 1658 | return ret; |
b9bec74b | 1659 | } |
b0b1d690 | 1660 | /* must be last */ |
1bc22652 | 1661 | ret = kvm_guest_debug_workarounds(x86_cpu); |
b9bec74b | 1662 | if (ret < 0) { |
ff44f1a3 | 1663 | return ret; |
b9bec74b | 1664 | } |
05330448 AL |
1665 | return 0; |
1666 | } | |
1667 | ||
20d695a9 | 1668 | int kvm_arch_get_registers(CPUState *cs) |
05330448 | 1669 | { |
20d695a9 | 1670 | X86CPU *cpu = X86_CPU(cs); |
05330448 AL |
1671 | int ret; |
1672 | ||
20d695a9 | 1673 | assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); |
dbaa07c4 | 1674 | |
1bc22652 | 1675 | ret = kvm_getput_regs(cpu, 0); |
b9bec74b | 1676 | if (ret < 0) { |
05330448 | 1677 | return ret; |
b9bec74b | 1678 | } |
1bc22652 | 1679 | ret = kvm_get_xsave(cpu); |
b9bec74b | 1680 | if (ret < 0) { |
f1665b21 | 1681 | return ret; |
b9bec74b | 1682 | } |
1bc22652 | 1683 | ret = kvm_get_xcrs(cpu); |
b9bec74b | 1684 | if (ret < 0) { |
05330448 | 1685 | return ret; |
b9bec74b | 1686 | } |
1bc22652 | 1687 | ret = kvm_get_sregs(cpu); |
b9bec74b | 1688 | if (ret < 0) { |
05330448 | 1689 | return ret; |
b9bec74b | 1690 | } |
1bc22652 | 1691 | ret = kvm_get_msrs(cpu); |
b9bec74b | 1692 | if (ret < 0) { |
05330448 | 1693 | return ret; |
b9bec74b | 1694 | } |
23d02d9b | 1695 | ret = kvm_get_mp_state(cpu); |
b9bec74b | 1696 | if (ret < 0) { |
5a2e3c2e | 1697 | return ret; |
b9bec74b | 1698 | } |
1bc22652 | 1699 | ret = kvm_get_apic(cpu); |
680c1c6f JK |
1700 | if (ret < 0) { |
1701 | return ret; | |
1702 | } | |
1bc22652 | 1703 | ret = kvm_get_vcpu_events(cpu); |
b9bec74b | 1704 | if (ret < 0) { |
a0fb002c | 1705 | return ret; |
b9bec74b | 1706 | } |
1bc22652 | 1707 | ret = kvm_get_debugregs(cpu); |
b9bec74b | 1708 | if (ret < 0) { |
ff44f1a3 | 1709 | return ret; |
b9bec74b | 1710 | } |
05330448 AL |
1711 | return 0; |
1712 | } | |
1713 | ||
20d695a9 | 1714 | void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 1715 | { |
20d695a9 AF |
1716 | X86CPU *x86_cpu = X86_CPU(cpu); |
1717 | CPUX86State *env = &x86_cpu->env; | |
ce377af3 JK |
1718 | int ret; |
1719 | ||
276ce815 LJ |
1720 | /* Inject NMI */ |
1721 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1722 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1723 | DPRINTF("injected NMI\n"); | |
1bc22652 | 1724 | ret = kvm_vcpu_ioctl(cpu, KVM_NMI); |
ce377af3 JK |
1725 | if (ret < 0) { |
1726 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
1727 | strerror(-ret)); | |
1728 | } | |
276ce815 LJ |
1729 | } |
1730 | ||
db1669bc | 1731 | if (!kvm_irqchip_in_kernel()) { |
d362e757 JK |
1732 | /* Force the VCPU out of its inner loop to process any INIT requests |
1733 | * or pending TPR access reports. */ | |
1734 | if (env->interrupt_request & | |
1735 | (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { | |
db1669bc | 1736 | env->exit_request = 1; |
05330448 | 1737 | } |
05330448 | 1738 | |
db1669bc JK |
1739 | /* Try to inject an interrupt if the guest can accept it */ |
1740 | if (run->ready_for_interrupt_injection && | |
1741 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1742 | (env->eflags & IF_MASK)) { | |
1743 | int irq; | |
1744 | ||
1745 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1746 | irq = cpu_get_pic_interrupt(env); | |
1747 | if (irq >= 0) { | |
1748 | struct kvm_interrupt intr; | |
1749 | ||
1750 | intr.irq = irq; | |
db1669bc | 1751 | DPRINTF("injected interrupt %d\n", irq); |
1bc22652 | 1752 | ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); |
ce377af3 JK |
1753 | if (ret < 0) { |
1754 | fprintf(stderr, | |
1755 | "KVM: injection failed, interrupt lost (%s)\n", | |
1756 | strerror(-ret)); | |
1757 | } | |
db1669bc JK |
1758 | } |
1759 | } | |
05330448 | 1760 | |
db1669bc JK |
1761 | /* If we have an interrupt but the guest is not ready to receive an |
1762 | * interrupt, request an interrupt window exit. This will | |
1763 | * cause a return to userspace as soon as the guest is ready to | |
1764 | * receive interrupts. */ | |
1765 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { | |
1766 | run->request_interrupt_window = 1; | |
1767 | } else { | |
1768 | run->request_interrupt_window = 0; | |
1769 | } | |
1770 | ||
1771 | DPRINTF("setting tpr\n"); | |
1772 | run->cr8 = cpu_get_apic_tpr(env->apic_state); | |
1773 | } | |
05330448 AL |
1774 | } |
1775 | ||
20d695a9 | 1776 | void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 1777 | { |
20d695a9 AF |
1778 | X86CPU *x86_cpu = X86_CPU(cpu); |
1779 | CPUX86State *env = &x86_cpu->env; | |
1780 | ||
b9bec74b | 1781 | if (run->if_flag) { |
05330448 | 1782 | env->eflags |= IF_MASK; |
b9bec74b | 1783 | } else { |
05330448 | 1784 | env->eflags &= ~IF_MASK; |
b9bec74b | 1785 | } |
4a942cea BS |
1786 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1787 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1788 | } |
1789 | ||
20d695a9 | 1790 | int kvm_arch_process_async_events(CPUState *cs) |
0af691d7 | 1791 | { |
20d695a9 AF |
1792 | X86CPU *cpu = X86_CPU(cs); |
1793 | CPUX86State *env = &cpu->env; | |
232fc23b | 1794 | |
ab443475 JK |
1795 | if (env->interrupt_request & CPU_INTERRUPT_MCE) { |
1796 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ | |
1797 | assert(env->mcg_cap); | |
1798 | ||
1799 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
1800 | ||
1801 | kvm_cpu_synchronize_state(env); | |
1802 | ||
1803 | if (env->exception_injected == EXCP08_DBLE) { | |
1804 | /* this means triple fault */ | |
1805 | qemu_system_reset_request(); | |
1806 | env->exit_request = 1; | |
1807 | return 0; | |
1808 | } | |
1809 | env->exception_injected = EXCP12_MCHK; | |
1810 | env->has_error_code = 0; | |
1811 | ||
1812 | env->halted = 0; | |
1813 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { | |
1814 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
1815 | } | |
1816 | } | |
1817 | ||
db1669bc JK |
1818 | if (kvm_irqchip_in_kernel()) { |
1819 | return 0; | |
1820 | } | |
1821 | ||
5d62c43a JK |
1822 | if (env->interrupt_request & CPU_INTERRUPT_POLL) { |
1823 | env->interrupt_request &= ~CPU_INTERRUPT_POLL; | |
1824 | apic_poll_irq(env->apic_state); | |
1825 | } | |
4601f7b0 JK |
1826 | if (((env->interrupt_request & CPU_INTERRUPT_HARD) && |
1827 | (env->eflags & IF_MASK)) || | |
1828 | (env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
6792a57b JK |
1829 | env->halted = 0; |
1830 | } | |
0af691d7 MT |
1831 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { |
1832 | kvm_cpu_synchronize_state(env); | |
232fc23b | 1833 | do_cpu_init(cpu); |
0af691d7 | 1834 | } |
0af691d7 MT |
1835 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { |
1836 | kvm_cpu_synchronize_state(env); | |
232fc23b | 1837 | do_cpu_sipi(cpu); |
0af691d7 | 1838 | } |
d362e757 JK |
1839 | if (env->interrupt_request & CPU_INTERRUPT_TPR) { |
1840 | env->interrupt_request &= ~CPU_INTERRUPT_TPR; | |
1841 | kvm_cpu_synchronize_state(env); | |
1842 | apic_handle_tpr_access_report(env->apic_state, env->eip, | |
1843 | env->tpr_access_type); | |
1844 | } | |
0af691d7 MT |
1845 | |
1846 | return env->halted; | |
1847 | } | |
1848 | ||
839b5630 | 1849 | static int kvm_handle_halt(X86CPU *cpu) |
05330448 | 1850 | { |
839b5630 AF |
1851 | CPUX86State *env = &cpu->env; |
1852 | ||
05330448 AL |
1853 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && |
1854 | (env->eflags & IF_MASK)) && | |
1855 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1856 | env->halted = 1; | |
bb4ea393 | 1857 | return EXCP_HLT; |
05330448 AL |
1858 | } |
1859 | ||
bb4ea393 | 1860 | return 0; |
05330448 AL |
1861 | } |
1862 | ||
f7575c96 | 1863 | static int kvm_handle_tpr_access(X86CPU *cpu) |
d362e757 | 1864 | { |
f7575c96 AF |
1865 | CPUX86State *env = &cpu->env; |
1866 | CPUState *cs = CPU(cpu); | |
1867 | struct kvm_run *run = cs->kvm_run; | |
d362e757 JK |
1868 | |
1869 | apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip, | |
1870 | run->tpr_access.is_write ? TPR_ACCESS_WRITE | |
1871 | : TPR_ACCESS_READ); | |
1872 | return 1; | |
1873 | } | |
1874 | ||
20d695a9 | 1875 | int kvm_arch_insert_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp) |
e22a25c9 | 1876 | { |
20d695a9 | 1877 | CPUX86State *env = &X86_CPU(cpu)->env; |
38972938 | 1878 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1879 | |
e22a25c9 | 1880 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
b9bec74b | 1881 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
e22a25c9 | 1882 | return -EINVAL; |
b9bec74b | 1883 | } |
e22a25c9 AL |
1884 | return 0; |
1885 | } | |
1886 | ||
20d695a9 | 1887 | int kvm_arch_remove_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp) |
e22a25c9 | 1888 | { |
20d695a9 | 1889 | CPUX86State *env = &X86_CPU(cpu)->env; |
e22a25c9 AL |
1890 | uint8_t int3; |
1891 | ||
1892 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
b9bec74b | 1893 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
e22a25c9 | 1894 | return -EINVAL; |
b9bec74b | 1895 | } |
e22a25c9 AL |
1896 | return 0; |
1897 | } | |
1898 | ||
1899 | static struct { | |
1900 | target_ulong addr; | |
1901 | int len; | |
1902 | int type; | |
1903 | } hw_breakpoint[4]; | |
1904 | ||
1905 | static int nb_hw_breakpoint; | |
1906 | ||
1907 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1908 | { | |
1909 | int n; | |
1910 | ||
b9bec74b | 1911 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1912 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1913 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1914 | return n; |
b9bec74b JK |
1915 | } |
1916 | } | |
e22a25c9 AL |
1917 | return -1; |
1918 | } | |
1919 | ||
1920 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1921 | target_ulong len, int type) | |
1922 | { | |
1923 | switch (type) { | |
1924 | case GDB_BREAKPOINT_HW: | |
1925 | len = 1; | |
1926 | break; | |
1927 | case GDB_WATCHPOINT_WRITE: | |
1928 | case GDB_WATCHPOINT_ACCESS: | |
1929 | switch (len) { | |
1930 | case 1: | |
1931 | break; | |
1932 | case 2: | |
1933 | case 4: | |
1934 | case 8: | |
b9bec74b | 1935 | if (addr & (len - 1)) { |
e22a25c9 | 1936 | return -EINVAL; |
b9bec74b | 1937 | } |
e22a25c9 AL |
1938 | break; |
1939 | default: | |
1940 | return -EINVAL; | |
1941 | } | |
1942 | break; | |
1943 | default: | |
1944 | return -ENOSYS; | |
1945 | } | |
1946 | ||
b9bec74b | 1947 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 1948 | return -ENOBUFS; |
b9bec74b JK |
1949 | } |
1950 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 1951 | return -EEXIST; |
b9bec74b | 1952 | } |
e22a25c9 AL |
1953 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1954 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1955 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1956 | nb_hw_breakpoint++; | |
1957 | ||
1958 | return 0; | |
1959 | } | |
1960 | ||
1961 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1962 | target_ulong len, int type) | |
1963 | { | |
1964 | int n; | |
1965 | ||
1966 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 1967 | if (n < 0) { |
e22a25c9 | 1968 | return -ENOENT; |
b9bec74b | 1969 | } |
e22a25c9 AL |
1970 | nb_hw_breakpoint--; |
1971 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1972 | ||
1973 | return 0; | |
1974 | } | |
1975 | ||
1976 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1977 | { | |
1978 | nb_hw_breakpoint = 0; | |
1979 | } | |
1980 | ||
1981 | static CPUWatchpoint hw_watchpoint; | |
1982 | ||
a60f24b5 | 1983 | static int kvm_handle_debug(X86CPU *cpu, |
48405526 | 1984 | struct kvm_debug_exit_arch *arch_info) |
e22a25c9 | 1985 | { |
a60f24b5 | 1986 | CPUX86State *env = &cpu->env; |
f2574737 | 1987 | int ret = 0; |
e22a25c9 AL |
1988 | int n; |
1989 | ||
1990 | if (arch_info->exception == 1) { | |
1991 | if (arch_info->dr6 & (1 << 14)) { | |
48405526 | 1992 | if (env->singlestep_enabled) { |
f2574737 | 1993 | ret = EXCP_DEBUG; |
b9bec74b | 1994 | } |
e22a25c9 | 1995 | } else { |
b9bec74b JK |
1996 | for (n = 0; n < 4; n++) { |
1997 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
1998 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1999 | case 0x0: | |
f2574737 | 2000 | ret = EXCP_DEBUG; |
e22a25c9 AL |
2001 | break; |
2002 | case 0x1: | |
f2574737 | 2003 | ret = EXCP_DEBUG; |
48405526 | 2004 | env->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2005 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2006 | hw_watchpoint.flags = BP_MEM_WRITE; | |
2007 | break; | |
2008 | case 0x3: | |
f2574737 | 2009 | ret = EXCP_DEBUG; |
48405526 | 2010 | env->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2011 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2012 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
2013 | break; | |
2014 | } | |
b9bec74b JK |
2015 | } |
2016 | } | |
e22a25c9 | 2017 | } |
a60f24b5 | 2018 | } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) { |
f2574737 | 2019 | ret = EXCP_DEBUG; |
b9bec74b | 2020 | } |
f2574737 | 2021 | if (ret == 0) { |
48405526 BS |
2022 | cpu_synchronize_state(env); |
2023 | assert(env->exception_injected == -1); | |
b0b1d690 | 2024 | |
f2574737 | 2025 | /* pass to guest */ |
48405526 BS |
2026 | env->exception_injected = arch_info->exception; |
2027 | env->has_error_code = 0; | |
b0b1d690 | 2028 | } |
e22a25c9 | 2029 | |
f2574737 | 2030 | return ret; |
e22a25c9 AL |
2031 | } |
2032 | ||
20d695a9 | 2033 | void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) |
e22a25c9 AL |
2034 | { |
2035 | const uint8_t type_code[] = { | |
2036 | [GDB_BREAKPOINT_HW] = 0x0, | |
2037 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
2038 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
2039 | }; | |
2040 | const uint8_t len_code[] = { | |
2041 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
2042 | }; | |
2043 | int n; | |
2044 | ||
a60f24b5 | 2045 | if (kvm_sw_breakpoints_active(cpu)) { |
e22a25c9 | 2046 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 2047 | } |
e22a25c9 AL |
2048 | if (nb_hw_breakpoint > 0) { |
2049 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
2050 | dbg->arch.debugreg[7] = 0x0600; | |
2051 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
2052 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
2053 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
2054 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 2055 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
2056 | } |
2057 | } | |
2058 | } | |
4513d923 | 2059 | |
2a4dac83 JK |
2060 | static bool host_supports_vmx(void) |
2061 | { | |
2062 | uint32_t ecx, unused; | |
2063 | ||
2064 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
2065 | return ecx & CPUID_EXT_VMX; | |
2066 | } | |
2067 | ||
2068 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
2069 | ||
20d695a9 | 2070 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
2a4dac83 | 2071 | { |
20d695a9 | 2072 | X86CPU *cpu = X86_CPU(cs); |
2a4dac83 JK |
2073 | uint64_t code; |
2074 | int ret; | |
2075 | ||
2076 | switch (run->exit_reason) { | |
2077 | case KVM_EXIT_HLT: | |
2078 | DPRINTF("handle_hlt\n"); | |
839b5630 | 2079 | ret = kvm_handle_halt(cpu); |
2a4dac83 JK |
2080 | break; |
2081 | case KVM_EXIT_SET_TPR: | |
2082 | ret = 0; | |
2083 | break; | |
d362e757 | 2084 | case KVM_EXIT_TPR_ACCESS: |
f7575c96 | 2085 | ret = kvm_handle_tpr_access(cpu); |
d362e757 | 2086 | break; |
2a4dac83 JK |
2087 | case KVM_EXIT_FAIL_ENTRY: |
2088 | code = run->fail_entry.hardware_entry_failure_reason; | |
2089 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
2090 | code); | |
2091 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
2092 | fprintf(stderr, | |
12619721 | 2093 | "\nIf you're running a guest on an Intel machine without " |
2a4dac83 JK |
2094 | "unrestricted mode\n" |
2095 | "support, the failure can be most likely due to the guest " | |
2096 | "entering an invalid\n" | |
2097 | "state for Intel VT. For example, the guest maybe running " | |
2098 | "in big real mode\n" | |
2099 | "which is not supported on less recent Intel processors." | |
2100 | "\n\n"); | |
2101 | } | |
2102 | ret = -1; | |
2103 | break; | |
2104 | case KVM_EXIT_EXCEPTION: | |
2105 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
2106 | run->ex.exception, run->ex.error_code); | |
2107 | ret = -1; | |
2108 | break; | |
f2574737 JK |
2109 | case KVM_EXIT_DEBUG: |
2110 | DPRINTF("kvm_exit_debug\n"); | |
a60f24b5 | 2111 | ret = kvm_handle_debug(cpu, &run->debug.arch); |
f2574737 | 2112 | break; |
2a4dac83 JK |
2113 | default: |
2114 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
2115 | ret = -1; | |
2116 | break; | |
2117 | } | |
2118 | ||
2119 | return ret; | |
2120 | } | |
2121 | ||
20d695a9 | 2122 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) |
4513d923 | 2123 | { |
20d695a9 AF |
2124 | X86CPU *cpu = X86_CPU(cs); |
2125 | CPUX86State *env = &cpu->env; | |
2126 | ||
d1f86636 | 2127 | kvm_cpu_synchronize_state(env); |
b9bec74b JK |
2128 | return !(env->cr[0] & CR0_PE_MASK) || |
2129 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 2130 | } |
84b058d7 JK |
2131 | |
2132 | void kvm_arch_init_irq_routing(KVMState *s) | |
2133 | { | |
2134 | if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { | |
2135 | /* If kernel can't do irq routing, interrupt source | |
2136 | * override 0->2 cannot be set up as required by HPET. | |
2137 | * So we have to disable it. | |
2138 | */ | |
2139 | no_hpet = 1; | |
2140 | } | |
cc7e0ddf | 2141 | /* We know at this point that we're using the in-kernel |
614e41bc | 2142 | * irqchip, so we can use irqfds, and on x86 we know |
f3e1bed8 | 2143 | * we can use msi via irqfd and GSI routing. |
cc7e0ddf PM |
2144 | */ |
2145 | kvm_irqfds_allowed = true; | |
614e41bc | 2146 | kvm_msi_via_irqfd_allowed = true; |
f3e1bed8 | 2147 | kvm_gsi_routing_allowed = true; |
84b058d7 | 2148 | } |
b139bd30 JK |
2149 | |
2150 | /* Classic KVM device assignment interface. Will remain x86 only. */ | |
2151 | int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr, | |
2152 | uint32_t flags, uint32_t *dev_id) | |
2153 | { | |
2154 | struct kvm_assigned_pci_dev dev_data = { | |
2155 | .segnr = dev_addr->domain, | |
2156 | .busnr = dev_addr->bus, | |
2157 | .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function), | |
2158 | .flags = flags, | |
2159 | }; | |
2160 | int ret; | |
2161 | ||
2162 | dev_data.assigned_dev_id = | |
2163 | (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn; | |
2164 | ||
2165 | ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data); | |
2166 | if (ret < 0) { | |
2167 | return ret; | |
2168 | } | |
2169 | ||
2170 | *dev_id = dev_data.assigned_dev_id; | |
2171 | ||
2172 | return 0; | |
2173 | } | |
2174 | ||
2175 | int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id) | |
2176 | { | |
2177 | struct kvm_assigned_pci_dev dev_data = { | |
2178 | .assigned_dev_id = dev_id, | |
2179 | }; | |
2180 | ||
2181 | return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data); | |
2182 | } | |
2183 | ||
2184 | static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id, | |
2185 | uint32_t irq_type, uint32_t guest_irq) | |
2186 | { | |
2187 | struct kvm_assigned_irq assigned_irq = { | |
2188 | .assigned_dev_id = dev_id, | |
2189 | .guest_irq = guest_irq, | |
2190 | .flags = irq_type, | |
2191 | }; | |
2192 | ||
2193 | if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) { | |
2194 | return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq); | |
2195 | } else { | |
2196 | return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq); | |
2197 | } | |
2198 | } | |
2199 | ||
2200 | int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi, | |
2201 | uint32_t guest_irq) | |
2202 | { | |
2203 | uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX | | |
2204 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX); | |
2205 | ||
2206 | return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq); | |
2207 | } | |
2208 | ||
2209 | int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked) | |
2210 | { | |
2211 | struct kvm_assigned_pci_dev dev_data = { | |
2212 | .assigned_dev_id = dev_id, | |
2213 | .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0, | |
2214 | }; | |
2215 | ||
2216 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data); | |
2217 | } | |
2218 | ||
2219 | static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id, | |
2220 | uint32_t type) | |
2221 | { | |
2222 | struct kvm_assigned_irq assigned_irq = { | |
2223 | .assigned_dev_id = dev_id, | |
2224 | .flags = type, | |
2225 | }; | |
2226 | ||
2227 | return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq); | |
2228 | } | |
2229 | ||
2230 | int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi) | |
2231 | { | |
2232 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX | | |
2233 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX)); | |
2234 | } | |
2235 | ||
2236 | int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq) | |
2237 | { | |
2238 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI | | |
2239 | KVM_DEV_IRQ_GUEST_MSI, virq); | |
2240 | } | |
2241 | ||
2242 | int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id) | |
2243 | { | |
2244 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI | | |
2245 | KVM_DEV_IRQ_HOST_MSI); | |
2246 | } | |
2247 | ||
2248 | bool kvm_device_msix_supported(KVMState *s) | |
2249 | { | |
2250 | /* The kernel lacks a corresponding KVM_CAP, so we probe by calling | |
2251 | * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */ | |
2252 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT; | |
2253 | } | |
2254 | ||
2255 | int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id, | |
2256 | uint32_t nr_vectors) | |
2257 | { | |
2258 | struct kvm_assigned_msix_nr msix_nr = { | |
2259 | .assigned_dev_id = dev_id, | |
2260 | .entry_nr = nr_vectors, | |
2261 | }; | |
2262 | ||
2263 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr); | |
2264 | } | |
2265 | ||
2266 | int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector, | |
2267 | int virq) | |
2268 | { | |
2269 | struct kvm_assigned_msix_entry msix_entry = { | |
2270 | .assigned_dev_id = dev_id, | |
2271 | .gsi = virq, | |
2272 | .entry = vector, | |
2273 | }; | |
2274 | ||
2275 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry); | |
2276 | } | |
2277 | ||
2278 | int kvm_device_msix_assign(KVMState *s, uint32_t dev_id) | |
2279 | { | |
2280 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX | | |
2281 | KVM_DEV_IRQ_GUEST_MSIX, 0); | |
2282 | } | |
2283 | ||
2284 | int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id) | |
2285 | { | |
2286 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX | | |
2287 | KVM_DEV_IRQ_HOST_MSIX); | |
2288 | } |