]>
Commit | Line | Data |
---|---|---|
05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
21 | ||
22 | #include "qemu-common.h" | |
23 | #include "sysemu.h" | |
24 | #include "kvm.h" | |
25 | #include "cpu.h" | |
e22a25c9 | 26 | #include "gdbstub.h" |
0e607a80 | 27 | #include "host-utils.h" |
4c5b10b7 | 28 | #include "hw/pc.h" |
408392b3 | 29 | #include "hw/apic.h" |
35bed8ee | 30 | #include "ioport.h" |
e7701825 | 31 | #include "kvm_x86.h" |
05330448 | 32 | |
bb0300dc GN |
33 | #ifdef CONFIG_KVM_PARA |
34 | #include <linux/kvm_para.h> | |
35 | #endif | |
36 | // | |
05330448 AL |
37 | //#define DEBUG_KVM |
38 | ||
39 | #ifdef DEBUG_KVM | |
8c0d577e | 40 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
41 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
42 | #else | |
8c0d577e | 43 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
44 | do { } while (0) |
45 | #endif | |
46 | ||
1a03675d GC |
47 | #define MSR_KVM_WALL_CLOCK 0x11 |
48 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
49 | ||
c0532a76 MT |
50 | #ifndef BUS_MCEERR_AR |
51 | #define BUS_MCEERR_AR 4 | |
52 | #endif | |
53 | #ifndef BUS_MCEERR_AO | |
54 | #define BUS_MCEERR_AO 5 | |
55 | #endif | |
56 | ||
25d2e361 MT |
57 | static int lm_capable_kernel; |
58 | ||
b827df58 AK |
59 | #ifdef KVM_CAP_EXT_CPUID |
60 | ||
61 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
62 | { | |
63 | struct kvm_cpuid2 *cpuid; | |
64 | int r, size; | |
65 | ||
66 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
67 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
68 | cpuid->nent = max; | |
69 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
70 | if (r == 0 && cpuid->nent >= max) { |
71 | r = -E2BIG; | |
72 | } | |
b827df58 AK |
73 | if (r < 0) { |
74 | if (r == -E2BIG) { | |
75 | qemu_free(cpuid); | |
76 | return NULL; | |
77 | } else { | |
78 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
79 | strerror(-r)); | |
80 | exit(1); | |
81 | } | |
82 | } | |
83 | return cpuid; | |
84 | } | |
85 | ||
c958a8bd SY |
86 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
87 | uint32_t index, int reg) | |
b827df58 AK |
88 | { |
89 | struct kvm_cpuid2 *cpuid; | |
90 | int i, max; | |
91 | uint32_t ret = 0; | |
92 | uint32_t cpuid_1_edx; | |
93 | ||
94 | if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) { | |
95 | return -1U; | |
96 | } | |
97 | ||
98 | max = 1; | |
99 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
100 | max *= 2; | |
101 | } | |
102 | ||
103 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
104 | if (cpuid->entries[i].function == function && |
105 | cpuid->entries[i].index == index) { | |
b827df58 AK |
106 | switch (reg) { |
107 | case R_EAX: | |
108 | ret = cpuid->entries[i].eax; | |
109 | break; | |
110 | case R_EBX: | |
111 | ret = cpuid->entries[i].ebx; | |
112 | break; | |
113 | case R_ECX: | |
114 | ret = cpuid->entries[i].ecx; | |
115 | break; | |
116 | case R_EDX: | |
117 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
118 | switch (function) { |
119 | case 1: | |
120 | /* KVM before 2.6.30 misreports the following features */ | |
121 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
122 | break; | |
123 | case 0x80000001: | |
b827df58 AK |
124 | /* On Intel, kvm returns cpuid according to the Intel spec, |
125 | * so add missing bits according to the AMD spec: | |
126 | */ | |
c958a8bd | 127 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 128 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 129 | break; |
b827df58 AK |
130 | } |
131 | break; | |
132 | } | |
133 | } | |
134 | } | |
135 | ||
136 | qemu_free(cpuid); | |
137 | ||
138 | return ret; | |
139 | } | |
140 | ||
141 | #else | |
142 | ||
c958a8bd SY |
143 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
144 | uint32_t index, int reg) | |
b827df58 AK |
145 | { |
146 | return -1U; | |
147 | } | |
148 | ||
149 | #endif | |
150 | ||
bb0300dc GN |
151 | #ifdef CONFIG_KVM_PARA |
152 | struct kvm_para_features { | |
153 | int cap; | |
154 | int feature; | |
155 | } para_features[] = { | |
156 | #ifdef KVM_CAP_CLOCKSOURCE | |
157 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
158 | #endif | |
159 | #ifdef KVM_CAP_NOP_IO_DELAY | |
160 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
161 | #endif | |
162 | #ifdef KVM_CAP_PV_MMU | |
163 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
f6584ee2 GN |
164 | #endif |
165 | #ifdef KVM_CAP_ASYNC_PF | |
166 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, | |
bb0300dc GN |
167 | #endif |
168 | { -1, -1 } | |
169 | }; | |
170 | ||
171 | static int get_para_features(CPUState *env) | |
172 | { | |
173 | int i, features = 0; | |
174 | ||
175 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
176 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) | |
177 | features |= (1 << para_features[i].feature); | |
178 | } | |
179 | ||
180 | return features; | |
181 | } | |
182 | #endif | |
183 | ||
e7701825 MT |
184 | #ifdef KVM_CAP_MCE |
185 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, | |
186 | int *max_banks) | |
187 | { | |
188 | int r; | |
189 | ||
14a09518 | 190 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
191 | if (r > 0) { |
192 | *max_banks = r; | |
193 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
194 | } | |
195 | return -ENOSYS; | |
196 | } | |
197 | ||
198 | static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap) | |
199 | { | |
200 | return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap); | |
201 | } | |
202 | ||
203 | static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m) | |
204 | { | |
205 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m); | |
206 | } | |
207 | ||
c0532a76 MT |
208 | static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n) |
209 | { | |
210 | struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs); | |
211 | int r; | |
212 | ||
213 | kmsrs->nmsrs = n; | |
214 | memcpy(kmsrs->entries, msrs, n * sizeof *msrs); | |
215 | r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs); | |
216 | memcpy(msrs, kmsrs->entries, n * sizeof *msrs); | |
217 | free(kmsrs); | |
218 | return r; | |
219 | } | |
220 | ||
221 | /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */ | |
222 | static int kvm_mce_in_exception(CPUState *env) | |
223 | { | |
224 | struct kvm_msr_entry msr_mcg_status = { | |
225 | .index = MSR_MCG_STATUS, | |
226 | }; | |
227 | int r; | |
228 | ||
229 | r = kvm_get_msr(env, &msr_mcg_status, 1); | |
230 | if (r == -1 || r == 0) { | |
231 | return -1; | |
232 | } | |
233 | return !!(msr_mcg_status.data & MCG_STATUS_MCIP); | |
234 | } | |
235 | ||
e7701825 MT |
236 | struct kvm_x86_mce_data |
237 | { | |
238 | CPUState *env; | |
239 | struct kvm_x86_mce *mce; | |
c0532a76 | 240 | int abort_on_error; |
e7701825 MT |
241 | }; |
242 | ||
243 | static void kvm_do_inject_x86_mce(void *_data) | |
244 | { | |
245 | struct kvm_x86_mce_data *data = _data; | |
246 | int r; | |
247 | ||
f8502cfb HS |
248 | /* If there is an MCE exception being processed, ignore this SRAO MCE */ |
249 | if ((data->env->mcg_cap & MCG_SER_P) && | |
250 | !(data->mce->status & MCI_STATUS_AR)) { | |
251 | r = kvm_mce_in_exception(data->env); | |
252 | if (r == -1) { | |
253 | fprintf(stderr, "Failed to get MCE status\n"); | |
254 | } else if (r) { | |
255 | return; | |
256 | } | |
257 | } | |
c0532a76 | 258 | |
e7701825 | 259 | r = kvm_set_mce(data->env, data->mce); |
c0532a76 | 260 | if (r < 0) { |
e7701825 | 261 | perror("kvm_set_mce FAILED"); |
c0532a76 MT |
262 | if (data->abort_on_error) { |
263 | abort(); | |
264 | } | |
265 | } | |
e7701825 MT |
266 | } |
267 | #endif | |
268 | ||
269 | void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, | |
c0532a76 MT |
270 | uint64_t mcg_status, uint64_t addr, uint64_t misc, |
271 | int abort_on_error) | |
e7701825 MT |
272 | { |
273 | #ifdef KVM_CAP_MCE | |
274 | struct kvm_x86_mce mce = { | |
275 | .bank = bank, | |
276 | .status = status, | |
277 | .mcg_status = mcg_status, | |
278 | .addr = addr, | |
279 | .misc = misc, | |
280 | }; | |
281 | struct kvm_x86_mce_data data = { | |
282 | .env = cenv, | |
283 | .mce = &mce, | |
284 | }; | |
285 | ||
c0532a76 MT |
286 | if (!cenv->mcg_cap) { |
287 | fprintf(stderr, "MCE support is not enabled!\n"); | |
288 | return; | |
289 | } | |
290 | ||
e7701825 | 291 | run_on_cpu(cenv, kvm_do_inject_x86_mce, &data); |
c0532a76 MT |
292 | #else |
293 | if (abort_on_error) | |
294 | abort(); | |
e7701825 MT |
295 | #endif |
296 | } | |
297 | ||
05330448 AL |
298 | int kvm_arch_init_vcpu(CPUState *env) |
299 | { | |
300 | struct { | |
486bd5a2 AL |
301 | struct kvm_cpuid2 cpuid; |
302 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 303 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 304 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 305 | uint32_t unused; |
bb0300dc GN |
306 | struct kvm_cpuid_entry2 *c; |
307 | #ifdef KVM_CPUID_SIGNATURE | |
308 | uint32_t signature[3]; | |
309 | #endif | |
05330448 | 310 | |
f8d926e9 JK |
311 | env->mp_state = KVM_MP_STATE_RUNNABLE; |
312 | ||
c958a8bd | 313 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
314 | |
315 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 316 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
317 | env->cpuid_ext_features |= i; |
318 | ||
457dfed6 | 319 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 320 | 0, R_EDX); |
457dfed6 | 321 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 322 | 0, R_ECX); |
296acb64 JR |
323 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A, |
324 | 0, R_EDX); | |
325 | ||
6c1f42fe | 326 | |
05330448 AL |
327 | cpuid_i = 0; |
328 | ||
bb0300dc GN |
329 | #ifdef CONFIG_KVM_PARA |
330 | /* Paravirtualization CPUIDs */ | |
331 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
332 | c = &cpuid_data.entries[cpuid_i++]; | |
333 | memset(c, 0, sizeof(*c)); | |
334 | c->function = KVM_CPUID_SIGNATURE; | |
335 | c->eax = 0; | |
336 | c->ebx = signature[0]; | |
337 | c->ecx = signature[1]; | |
338 | c->edx = signature[2]; | |
339 | ||
340 | c = &cpuid_data.entries[cpuid_i++]; | |
341 | memset(c, 0, sizeof(*c)); | |
342 | c->function = KVM_CPUID_FEATURES; | |
343 | c->eax = env->cpuid_kvm_features & get_para_features(env); | |
344 | #endif | |
345 | ||
a33609ca | 346 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
347 | |
348 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 349 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
350 | |
351 | switch (i) { | |
a36b1029 AL |
352 | case 2: { |
353 | /* Keep reading function 2 till all the input is received */ | |
354 | int times; | |
355 | ||
a36b1029 | 356 | c->function = i; |
a33609ca AL |
357 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
358 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
359 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
360 | times = c->eax & 0xff; | |
a36b1029 AL |
361 | |
362 | for (j = 1; j < times; ++j) { | |
a33609ca | 363 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 364 | c->function = i; |
a33609ca AL |
365 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
366 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
367 | } |
368 | break; | |
369 | } | |
486bd5a2 AL |
370 | case 4: |
371 | case 0xb: | |
372 | case 0xd: | |
373 | for (j = 0; ; j++) { | |
486bd5a2 AL |
374 | c->function = i; |
375 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
376 | c->index = j; | |
a33609ca | 377 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 378 | |
a33609ca | 379 | if (i == 4 && c->eax == 0) |
486bd5a2 | 380 | break; |
a33609ca | 381 | if (i == 0xb && !(c->ecx & 0xff00)) |
486bd5a2 | 382 | break; |
a33609ca | 383 | if (i == 0xd && c->eax == 0) |
486bd5a2 | 384 | break; |
a33609ca AL |
385 | |
386 | c = &cpuid_data.entries[cpuid_i++]; | |
486bd5a2 AL |
387 | } |
388 | break; | |
389 | default: | |
486bd5a2 | 390 | c->function = i; |
a33609ca AL |
391 | c->flags = 0; |
392 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
393 | break; |
394 | } | |
05330448 | 395 | } |
a33609ca | 396 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
397 | |
398 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 399 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 400 | |
05330448 | 401 | c->function = i; |
a33609ca AL |
402 | c->flags = 0; |
403 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
404 | } |
405 | ||
406 | cpuid_data.cpuid.nent = cpuid_i; | |
407 | ||
e7701825 MT |
408 | #ifdef KVM_CAP_MCE |
409 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
410 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
411 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
412 | uint64_t mcg_cap; | |
413 | int banks; | |
414 | ||
415 | if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) | |
416 | perror("kvm_get_mce_cap_supported FAILED"); | |
417 | else { | |
418 | if (banks > MCE_BANKS_DEF) | |
419 | banks = MCE_BANKS_DEF; | |
420 | mcg_cap &= MCE_CAP_DEF; | |
421 | mcg_cap |= banks; | |
422 | if (kvm_setup_mce(env, &mcg_cap)) | |
423 | perror("kvm_setup_mce FAILED"); | |
424 | else | |
425 | env->mcg_cap = mcg_cap; | |
426 | } | |
427 | } | |
428 | #endif | |
429 | ||
486bd5a2 | 430 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
431 | } |
432 | ||
caa5af0f JK |
433 | void kvm_arch_reset_vcpu(CPUState *env) |
434 | { | |
e73223a5 | 435 | env->exception_injected = -1; |
0e607a80 | 436 | env->interrupt_injected = -1; |
a0fb002c JK |
437 | env->nmi_injected = 0; |
438 | env->nmi_pending = 0; | |
ddced198 MT |
439 | if (kvm_irqchip_in_kernel()) { |
440 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
441 | KVM_MP_STATE_UNINITIALIZED; | |
442 | } else { | |
443 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
444 | } | |
caa5af0f JK |
445 | } |
446 | ||
75b10c43 MT |
447 | int has_msr_star; |
448 | int has_msr_hsave_pa; | |
449 | ||
450 | static void kvm_supported_msrs(CPUState *env) | |
05330448 | 451 | { |
75b10c43 | 452 | static int kvm_supported_msrs; |
05330448 AL |
453 | int ret; |
454 | ||
455 | /* first time */ | |
75b10c43 | 456 | if (kvm_supported_msrs == 0) { |
05330448 AL |
457 | struct kvm_msr_list msr_list, *kvm_msr_list; |
458 | ||
75b10c43 | 459 | kvm_supported_msrs = -1; |
05330448 AL |
460 | |
461 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
462 | * save/restore */ | |
4c9f7372 | 463 | msr_list.nmsrs = 0; |
05330448 | 464 | ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 465 | if (ret < 0 && ret != -E2BIG) { |
75b10c43 | 466 | return; |
6fb6d245 | 467 | } |
d9db889f JK |
468 | /* Old kernel modules had a bug and could write beyond the provided |
469 | memory. Allocate at least a safe amount of 1K. */ | |
470 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
471 | msr_list.nmsrs * | |
472 | sizeof(msr_list.indices[0]))); | |
05330448 | 473 | |
55308450 | 474 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
05330448 AL |
475 | ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
476 | if (ret >= 0) { | |
477 | int i; | |
478 | ||
479 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
480 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
481 | has_msr_star = 1; | |
75b10c43 MT |
482 | continue; |
483 | } | |
484 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
485 | has_msr_hsave_pa = 1; | |
486 | continue; | |
05330448 AL |
487 | } |
488 | } | |
489 | } | |
490 | ||
491 | free(kvm_msr_list); | |
492 | } | |
493 | ||
75b10c43 MT |
494 | return; |
495 | } | |
496 | ||
497 | static int kvm_has_msr_hsave_pa(CPUState *env) | |
498 | { | |
499 | kvm_supported_msrs(env); | |
500 | return has_msr_hsave_pa; | |
501 | } | |
502 | ||
503 | static int kvm_has_msr_star(CPUState *env) | |
504 | { | |
505 | kvm_supported_msrs(env); | |
506 | return has_msr_star; | |
05330448 AL |
507 | } |
508 | ||
20420430 SY |
509 | static int kvm_init_identity_map_page(KVMState *s) |
510 | { | |
511 | #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR | |
512 | int ret; | |
513 | uint64_t addr = 0xfffbc000; | |
514 | ||
515 | if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
516 | return 0; | |
517 | } | |
518 | ||
519 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr); | |
520 | if (ret < 0) { | |
521 | fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret)); | |
522 | return ret; | |
523 | } | |
524 | #endif | |
525 | return 0; | |
526 | } | |
527 | ||
05330448 AL |
528 | int kvm_arch_init(KVMState *s, int smp_cpus) |
529 | { | |
530 | int ret; | |
531 | ||
25d2e361 MT |
532 | struct utsname utsname; |
533 | ||
534 | uname(&utsname); | |
535 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
536 | ||
05330448 AL |
537 | /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code |
538 | * directly. In order to use vm86 mode, a TSS is needed. Since this | |
539 | * must be part of guest physical memory, we need to allocate it. Older | |
540 | * versions of KVM just assumed that it would be at the end of physical | |
541 | * memory but that doesn't work with more than 4GB of memory. We simply | |
542 | * refuse to work with those older versions of KVM. */ | |
14a09518 | 543 | ret = kvm_check_extension(s, KVM_CAP_SET_TSS_ADDR); |
05330448 AL |
544 | if (ret <= 0) { |
545 | fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n"); | |
546 | return ret; | |
547 | } | |
548 | ||
549 | /* this address is 3 pages before the bios, and the bios should present | |
550 | * as unavaible memory. FIXME, need to ensure the e820 map deals with | |
551 | * this? | |
552 | */ | |
4c5b10b7 JS |
553 | /* |
554 | * Tell fw_cfg to notify the BIOS to reserve the range. | |
555 | */ | |
556 | if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) { | |
557 | perror("e820_add_entry() table is full"); | |
558 | exit(1); | |
559 | } | |
20420430 SY |
560 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000); |
561 | if (ret < 0) { | |
562 | return ret; | |
563 | } | |
564 | ||
565 | return kvm_init_identity_map_page(s); | |
05330448 AL |
566 | } |
567 | ||
568 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
569 | { | |
570 | lhs->selector = rhs->selector; | |
571 | lhs->base = rhs->base; | |
572 | lhs->limit = rhs->limit; | |
573 | lhs->type = 3; | |
574 | lhs->present = 1; | |
575 | lhs->dpl = 3; | |
576 | lhs->db = 0; | |
577 | lhs->s = 1; | |
578 | lhs->l = 0; | |
579 | lhs->g = 0; | |
580 | lhs->avl = 0; | |
581 | lhs->unusable = 0; | |
582 | } | |
583 | ||
584 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
585 | { | |
586 | unsigned flags = rhs->flags; | |
587 | lhs->selector = rhs->selector; | |
588 | lhs->base = rhs->base; | |
589 | lhs->limit = rhs->limit; | |
590 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
591 | lhs->present = (flags & DESC_P_MASK) != 0; | |
592 | lhs->dpl = rhs->selector & 3; | |
593 | lhs->db = (flags >> DESC_B_SHIFT) & 1; | |
594 | lhs->s = (flags & DESC_S_MASK) != 0; | |
595 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
596 | lhs->g = (flags & DESC_G_MASK) != 0; | |
597 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
598 | lhs->unusable = 0; | |
599 | } | |
600 | ||
601 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
602 | { | |
603 | lhs->selector = rhs->selector; | |
604 | lhs->base = rhs->base; | |
605 | lhs->limit = rhs->limit; | |
606 | lhs->flags = | |
607 | (rhs->type << DESC_TYPE_SHIFT) | |
608 | | (rhs->present * DESC_P_MASK) | |
609 | | (rhs->dpl << DESC_DPL_SHIFT) | |
610 | | (rhs->db << DESC_B_SHIFT) | |
611 | | (rhs->s * DESC_S_MASK) | |
612 | | (rhs->l << DESC_L_SHIFT) | |
613 | | (rhs->g * DESC_G_MASK) | |
614 | | (rhs->avl * DESC_AVL_MASK); | |
615 | } | |
616 | ||
617 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
618 | { | |
619 | if (set) | |
620 | *kvm_reg = *qemu_reg; | |
621 | else | |
622 | *qemu_reg = *kvm_reg; | |
623 | } | |
624 | ||
625 | static int kvm_getput_regs(CPUState *env, int set) | |
626 | { | |
627 | struct kvm_regs regs; | |
628 | int ret = 0; | |
629 | ||
630 | if (!set) { | |
631 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
632 | if (ret < 0) | |
633 | return ret; | |
634 | } | |
635 | ||
636 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
637 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
638 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
639 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
640 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
641 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
642 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
643 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
644 | #ifdef TARGET_X86_64 | |
645 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
646 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
647 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
648 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
649 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
650 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
651 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
652 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
653 | #endif | |
654 | ||
655 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
656 | kvm_getput_reg(®s.rip, &env->eip, set); | |
657 | ||
658 | if (set) | |
659 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); | |
660 | ||
661 | return ret; | |
662 | } | |
663 | ||
664 | static int kvm_put_fpu(CPUState *env) | |
665 | { | |
666 | struct kvm_fpu fpu; | |
667 | int i; | |
668 | ||
669 | memset(&fpu, 0, sizeof fpu); | |
670 | fpu.fsw = env->fpus & ~(7 << 11); | |
671 | fpu.fsw |= (env->fpstt & 7) << 11; | |
672 | fpu.fcw = env->fpuc; | |
673 | for (i = 0; i < 8; ++i) | |
674 | fpu.ftwx |= (!env->fptags[i]) << i; | |
675 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); | |
676 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
677 | fpu.mxcsr = env->mxcsr; | |
678 | ||
679 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
680 | } | |
681 | ||
f1665b21 SY |
682 | #ifdef KVM_CAP_XSAVE |
683 | #define XSAVE_CWD_RIP 2 | |
684 | #define XSAVE_CWD_RDP 4 | |
685 | #define XSAVE_MXCSR 6 | |
686 | #define XSAVE_ST_SPACE 8 | |
687 | #define XSAVE_XMM_SPACE 40 | |
688 | #define XSAVE_XSTATE_BV 128 | |
689 | #define XSAVE_YMMH_SPACE 144 | |
690 | #endif | |
691 | ||
692 | static int kvm_put_xsave(CPUState *env) | |
693 | { | |
694 | #ifdef KVM_CAP_XSAVE | |
0f53994f | 695 | int i, r; |
f1665b21 SY |
696 | struct kvm_xsave* xsave; |
697 | uint16_t cwd, swd, twd, fop; | |
698 | ||
699 | if (!kvm_has_xsave()) | |
700 | return kvm_put_fpu(env); | |
701 | ||
702 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
703 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
704 | cwd = swd = twd = fop = 0; | |
705 | swd = env->fpus & ~(7 << 11); | |
706 | swd |= (env->fpstt & 7) << 11; | |
707 | cwd = env->fpuc; | |
708 | for (i = 0; i < 8; ++i) | |
709 | twd |= (!env->fptags[i]) << i; | |
710 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; | |
711 | xsave->region[1] = (uint32_t)(fop << 16) + twd; | |
712 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
713 | sizeof env->fpregs); | |
714 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
715 | sizeof env->xmm_regs); | |
716 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
717 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
718 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
719 | sizeof env->ymmh_regs); | |
0f53994f MT |
720 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
721 | qemu_free(xsave); | |
722 | return r; | |
f1665b21 SY |
723 | #else |
724 | return kvm_put_fpu(env); | |
725 | #endif | |
726 | } | |
727 | ||
728 | static int kvm_put_xcrs(CPUState *env) | |
729 | { | |
730 | #ifdef KVM_CAP_XCRS | |
731 | struct kvm_xcrs xcrs; | |
732 | ||
733 | if (!kvm_has_xcrs()) | |
734 | return 0; | |
735 | ||
736 | xcrs.nr_xcrs = 1; | |
737 | xcrs.flags = 0; | |
738 | xcrs.xcrs[0].xcr = 0; | |
739 | xcrs.xcrs[0].value = env->xcr0; | |
740 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
741 | #else | |
742 | return 0; | |
743 | #endif | |
744 | } | |
745 | ||
05330448 AL |
746 | static int kvm_put_sregs(CPUState *env) |
747 | { | |
748 | struct kvm_sregs sregs; | |
749 | ||
0e607a80 JK |
750 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
751 | if (env->interrupt_injected >= 0) { | |
752 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
753 | (uint64_t)1 << (env->interrupt_injected % 64); | |
754 | } | |
05330448 AL |
755 | |
756 | if ((env->eflags & VM_MASK)) { | |
757 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); | |
758 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
759 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
760 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
761 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
762 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
763 | } else { | |
764 | set_seg(&sregs.cs, &env->segs[R_CS]); | |
765 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
766 | set_seg(&sregs.es, &env->segs[R_ES]); | |
767 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
768 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
769 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
770 | ||
771 | if (env->cr[0] & CR0_PE_MASK) { | |
772 | /* force ss cpl to cs cpl */ | |
773 | sregs.ss.selector = (sregs.ss.selector & ~3) | | |
774 | (sregs.cs.selector & 3); | |
775 | sregs.ss.dpl = sregs.ss.selector & 3; | |
776 | } | |
777 | } | |
778 | ||
779 | set_seg(&sregs.tr, &env->tr); | |
780 | set_seg(&sregs.ldt, &env->ldt); | |
781 | ||
782 | sregs.idt.limit = env->idt.limit; | |
783 | sregs.idt.base = env->idt.base; | |
784 | sregs.gdt.limit = env->gdt.limit; | |
785 | sregs.gdt.base = env->gdt.base; | |
786 | ||
787 | sregs.cr0 = env->cr[0]; | |
788 | sregs.cr2 = env->cr[2]; | |
789 | sregs.cr3 = env->cr[3]; | |
790 | sregs.cr4 = env->cr[4]; | |
791 | ||
4a942cea BS |
792 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
793 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
794 | |
795 | sregs.efer = env->efer; | |
796 | ||
797 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
798 | } | |
799 | ||
800 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
801 | uint32_t index, uint64_t value) | |
802 | { | |
803 | entry->index = index; | |
804 | entry->data = value; | |
805 | } | |
806 | ||
ea643051 | 807 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
808 | { |
809 | struct { | |
810 | struct kvm_msrs info; | |
811 | struct kvm_msr_entry entries[100]; | |
812 | } msr_data; | |
813 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 814 | int n = 0; |
05330448 AL |
815 | |
816 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
817 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
818 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
819 | if (kvm_has_msr_star(env)) | |
820 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); | |
75b10c43 MT |
821 | if (kvm_has_msr_hsave_pa(env)) |
822 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); | |
05330448 | 823 | #ifdef TARGET_X86_64 |
25d2e361 MT |
824 | if (lm_capable_kernel) { |
825 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
826 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
827 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
828 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
829 | } | |
05330448 | 830 | #endif |
ea643051 | 831 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
832 | /* |
833 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
834 | * writeback. Until this is fixed, we only write the offset to SMP | |
835 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
836 | * huge jump-backs that would occur without any writeback at all. | |
837 | */ | |
838 | if (smp_cpus == 1 || env->tsc != 0) { | |
839 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
840 | } | |
ea643051 JK |
841 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
842 | env->system_time_msr); | |
843 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
f6584ee2 GN |
844 | #ifdef KVM_CAP_ASYNC_PF |
845 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr); | |
846 | #endif | |
ea643051 | 847 | } |
57780495 MT |
848 | #ifdef KVM_CAP_MCE |
849 | if (env->mcg_cap) { | |
d8da8574 | 850 | int i; |
57780495 MT |
851 | if (level == KVM_PUT_RESET_STATE) |
852 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); | |
853 | else if (level == KVM_PUT_FULL_STATE) { | |
854 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); | |
855 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
856 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) | |
857 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
858 | } | |
859 | } | |
860 | #endif | |
1a03675d | 861 | |
05330448 AL |
862 | msr_data.info.nmsrs = n; |
863 | ||
864 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
865 | ||
866 | } | |
867 | ||
868 | ||
869 | static int kvm_get_fpu(CPUState *env) | |
870 | { | |
871 | struct kvm_fpu fpu; | |
872 | int i, ret; | |
873 | ||
874 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
875 | if (ret < 0) | |
876 | return ret; | |
877 | ||
878 | env->fpstt = (fpu.fsw >> 11) & 7; | |
879 | env->fpus = fpu.fsw; | |
880 | env->fpuc = fpu.fcw; | |
881 | for (i = 0; i < 8; ++i) | |
882 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
883 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); | |
884 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
885 | env->mxcsr = fpu.mxcsr; | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
f1665b21 SY |
890 | static int kvm_get_xsave(CPUState *env) |
891 | { | |
892 | #ifdef KVM_CAP_XSAVE | |
893 | struct kvm_xsave* xsave; | |
894 | int ret, i; | |
895 | uint16_t cwd, swd, twd, fop; | |
896 | ||
897 | if (!kvm_has_xsave()) | |
898 | return kvm_get_fpu(env); | |
899 | ||
900 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
901 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
0f53994f MT |
902 | if (ret < 0) { |
903 | qemu_free(xsave); | |
f1665b21 | 904 | return ret; |
0f53994f | 905 | } |
f1665b21 SY |
906 | |
907 | cwd = (uint16_t)xsave->region[0]; | |
908 | swd = (uint16_t)(xsave->region[0] >> 16); | |
909 | twd = (uint16_t)xsave->region[1]; | |
910 | fop = (uint16_t)(xsave->region[1] >> 16); | |
911 | env->fpstt = (swd >> 11) & 7; | |
912 | env->fpus = swd; | |
913 | env->fpuc = cwd; | |
914 | for (i = 0; i < 8; ++i) | |
915 | env->fptags[i] = !((twd >> i) & 1); | |
916 | env->mxcsr = xsave->region[XSAVE_MXCSR]; | |
917 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
918 | sizeof env->fpregs); | |
919 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
920 | sizeof env->xmm_regs); | |
921 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
922 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
923 | sizeof env->ymmh_regs); | |
0f53994f | 924 | qemu_free(xsave); |
f1665b21 SY |
925 | return 0; |
926 | #else | |
927 | return kvm_get_fpu(env); | |
928 | #endif | |
929 | } | |
930 | ||
931 | static int kvm_get_xcrs(CPUState *env) | |
932 | { | |
933 | #ifdef KVM_CAP_XCRS | |
934 | int i, ret; | |
935 | struct kvm_xcrs xcrs; | |
936 | ||
937 | if (!kvm_has_xcrs()) | |
938 | return 0; | |
939 | ||
940 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
941 | if (ret < 0) | |
942 | return ret; | |
943 | ||
944 | for (i = 0; i < xcrs.nr_xcrs; i++) | |
945 | /* Only support xcr0 now */ | |
946 | if (xcrs.xcrs[0].xcr == 0) { | |
947 | env->xcr0 = xcrs.xcrs[0].value; | |
948 | break; | |
949 | } | |
950 | return 0; | |
951 | #else | |
952 | return 0; | |
953 | #endif | |
954 | } | |
955 | ||
05330448 AL |
956 | static int kvm_get_sregs(CPUState *env) |
957 | { | |
958 | struct kvm_sregs sregs; | |
959 | uint32_t hflags; | |
0e607a80 | 960 | int bit, i, ret; |
05330448 AL |
961 | |
962 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
963 | if (ret < 0) | |
964 | return ret; | |
965 | ||
0e607a80 JK |
966 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
967 | to find it and save its number instead (-1 for none). */ | |
968 | env->interrupt_injected = -1; | |
969 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
970 | if (sregs.interrupt_bitmap[i]) { | |
971 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
972 | env->interrupt_injected = i * 64 + bit; | |
973 | break; | |
974 | } | |
975 | } | |
05330448 AL |
976 | |
977 | get_seg(&env->segs[R_CS], &sregs.cs); | |
978 | get_seg(&env->segs[R_DS], &sregs.ds); | |
979 | get_seg(&env->segs[R_ES], &sregs.es); | |
980 | get_seg(&env->segs[R_FS], &sregs.fs); | |
981 | get_seg(&env->segs[R_GS], &sregs.gs); | |
982 | get_seg(&env->segs[R_SS], &sregs.ss); | |
983 | ||
984 | get_seg(&env->tr, &sregs.tr); | |
985 | get_seg(&env->ldt, &sregs.ldt); | |
986 | ||
987 | env->idt.limit = sregs.idt.limit; | |
988 | env->idt.base = sregs.idt.base; | |
989 | env->gdt.limit = sregs.gdt.limit; | |
990 | env->gdt.base = sregs.gdt.base; | |
991 | ||
992 | env->cr[0] = sregs.cr0; | |
993 | env->cr[2] = sregs.cr2; | |
994 | env->cr[3] = sregs.cr3; | |
995 | env->cr[4] = sregs.cr4; | |
996 | ||
4a942cea | 997 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
998 | |
999 | env->efer = sregs.efer; | |
4a942cea | 1000 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 AL |
1001 | |
1002 | #define HFLAG_COPY_MASK ~( \ | |
1003 | HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1004 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1005 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1006 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
1007 | ||
1008 | ||
1009 | ||
1010 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1011 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1012 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
1013 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); | |
1014 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); | |
1015 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
1016 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); | |
1017 | ||
1018 | if (env->efer & MSR_EFER_LMA) { | |
1019 | hflags |= HF_LMA_MASK; | |
1020 | } | |
1021 | ||
1022 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1023 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1024 | } else { | |
1025 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
1026 | (DESC_B_SHIFT - HF_CS32_SHIFT); | |
1027 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> | |
1028 | (DESC_B_SHIFT - HF_SS32_SHIFT); | |
1029 | if (!(env->cr[0] & CR0_PE_MASK) || | |
1030 | (env->eflags & VM_MASK) || | |
1031 | !(hflags & HF_CS32_MASK)) { | |
1032 | hflags |= HF_ADDSEG_MASK; | |
1033 | } else { | |
1034 | hflags |= ((env->segs[R_DS].base | | |
1035 | env->segs[R_ES].base | | |
1036 | env->segs[R_SS].base) != 0) << | |
1037 | HF_ADDSEG_SHIFT; | |
1038 | } | |
1039 | } | |
1040 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1041 | |
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static int kvm_get_msrs(CPUState *env) | |
1046 | { | |
1047 | struct { | |
1048 | struct kvm_msrs info; | |
1049 | struct kvm_msr_entry entries[100]; | |
1050 | } msr_data; | |
1051 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1052 | int ret, i, n; | |
1053 | ||
1054 | n = 0; | |
1055 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1056 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1057 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
1058 | if (kvm_has_msr_star(env)) | |
1059 | msrs[n++].index = MSR_STAR; | |
75b10c43 MT |
1060 | if (kvm_has_msr_hsave_pa(env)) |
1061 | msrs[n++].index = MSR_VM_HSAVE_PA; | |
05330448 AL |
1062 | msrs[n++].index = MSR_IA32_TSC; |
1063 | #ifdef TARGET_X86_64 | |
25d2e361 MT |
1064 | if (lm_capable_kernel) { |
1065 | msrs[n++].index = MSR_CSTAR; | |
1066 | msrs[n++].index = MSR_KERNELGSBASE; | |
1067 | msrs[n++].index = MSR_FMASK; | |
1068 | msrs[n++].index = MSR_LSTAR; | |
1069 | } | |
05330448 | 1070 | #endif |
1a03675d GC |
1071 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1072 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
f6584ee2 GN |
1073 | #ifdef KVM_CAP_ASYNC_PF |
1074 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1075 | #endif | |
1a03675d | 1076 | |
57780495 MT |
1077 | #ifdef KVM_CAP_MCE |
1078 | if (env->mcg_cap) { | |
1079 | msrs[n++].index = MSR_MCG_STATUS; | |
1080 | msrs[n++].index = MSR_MCG_CTL; | |
1081 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) | |
1082 | msrs[n++].index = MSR_MC0_CTL + i; | |
1083 | } | |
1084 | #endif | |
1085 | ||
05330448 AL |
1086 | msr_data.info.nmsrs = n; |
1087 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
1088 | if (ret < 0) | |
1089 | return ret; | |
1090 | ||
1091 | for (i = 0; i < ret; i++) { | |
1092 | switch (msrs[i].index) { | |
1093 | case MSR_IA32_SYSENTER_CS: | |
1094 | env->sysenter_cs = msrs[i].data; | |
1095 | break; | |
1096 | case MSR_IA32_SYSENTER_ESP: | |
1097 | env->sysenter_esp = msrs[i].data; | |
1098 | break; | |
1099 | case MSR_IA32_SYSENTER_EIP: | |
1100 | env->sysenter_eip = msrs[i].data; | |
1101 | break; | |
1102 | case MSR_STAR: | |
1103 | env->star = msrs[i].data; | |
1104 | break; | |
1105 | #ifdef TARGET_X86_64 | |
1106 | case MSR_CSTAR: | |
1107 | env->cstar = msrs[i].data; | |
1108 | break; | |
1109 | case MSR_KERNELGSBASE: | |
1110 | env->kernelgsbase = msrs[i].data; | |
1111 | break; | |
1112 | case MSR_FMASK: | |
1113 | env->fmask = msrs[i].data; | |
1114 | break; | |
1115 | case MSR_LSTAR: | |
1116 | env->lstar = msrs[i].data; | |
1117 | break; | |
1118 | #endif | |
1119 | case MSR_IA32_TSC: | |
1120 | env->tsc = msrs[i].data; | |
1121 | break; | |
aa851e36 MT |
1122 | case MSR_VM_HSAVE_PA: |
1123 | env->vm_hsave = msrs[i].data; | |
1124 | break; | |
1a03675d GC |
1125 | case MSR_KVM_SYSTEM_TIME: |
1126 | env->system_time_msr = msrs[i].data; | |
1127 | break; | |
1128 | case MSR_KVM_WALL_CLOCK: | |
1129 | env->wall_clock_msr = msrs[i].data; | |
1130 | break; | |
57780495 MT |
1131 | #ifdef KVM_CAP_MCE |
1132 | case MSR_MCG_STATUS: | |
1133 | env->mcg_status = msrs[i].data; | |
1134 | break; | |
1135 | case MSR_MCG_CTL: | |
1136 | env->mcg_ctl = msrs[i].data; | |
1137 | break; | |
1138 | #endif | |
1139 | default: | |
1140 | #ifdef KVM_CAP_MCE | |
1141 | if (msrs[i].index >= MSR_MC0_CTL && | |
1142 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1143 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 MT |
1144 | } |
1145 | #endif | |
d8da8574 | 1146 | break; |
f6584ee2 GN |
1147 | #ifdef KVM_CAP_ASYNC_PF |
1148 | case MSR_KVM_ASYNC_PF_EN: | |
1149 | env->async_pf_en_msr = msrs[i].data; | |
1150 | break; | |
1151 | #endif | |
05330448 AL |
1152 | } |
1153 | } | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
9bdbe550 HB |
1158 | static int kvm_put_mp_state(CPUState *env) |
1159 | { | |
1160 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1161 | ||
1162 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1163 | } | |
1164 | ||
1165 | static int kvm_get_mp_state(CPUState *env) | |
1166 | { | |
1167 | struct kvm_mp_state mp_state; | |
1168 | int ret; | |
1169 | ||
1170 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1171 | if (ret < 0) { | |
1172 | return ret; | |
1173 | } | |
1174 | env->mp_state = mp_state.mp_state; | |
1175 | return 0; | |
1176 | } | |
1177 | ||
ea643051 | 1178 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c JK |
1179 | { |
1180 | #ifdef KVM_CAP_VCPU_EVENTS | |
1181 | struct kvm_vcpu_events events; | |
1182 | ||
1183 | if (!kvm_has_vcpu_events()) { | |
1184 | return 0; | |
1185 | } | |
1186 | ||
31827373 JK |
1187 | events.exception.injected = (env->exception_injected >= 0); |
1188 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1189 | events.exception.has_error_code = env->has_error_code; |
1190 | events.exception.error_code = env->error_code; | |
1191 | ||
1192 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1193 | events.interrupt.nr = env->interrupt_injected; | |
1194 | events.interrupt.soft = env->soft_interrupt; | |
1195 | ||
1196 | events.nmi.injected = env->nmi_injected; | |
1197 | events.nmi.pending = env->nmi_pending; | |
1198 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1199 | ||
1200 | events.sipi_vector = env->sipi_vector; | |
1201 | ||
ea643051 JK |
1202 | events.flags = 0; |
1203 | if (level >= KVM_PUT_RESET_STATE) { | |
1204 | events.flags |= | |
1205 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1206 | } | |
aee028b9 | 1207 | |
a0fb002c JK |
1208 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
1209 | #else | |
1210 | return 0; | |
1211 | #endif | |
1212 | } | |
1213 | ||
1214 | static int kvm_get_vcpu_events(CPUState *env) | |
1215 | { | |
1216 | #ifdef KVM_CAP_VCPU_EVENTS | |
1217 | struct kvm_vcpu_events events; | |
1218 | int ret; | |
1219 | ||
1220 | if (!kvm_has_vcpu_events()) { | |
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1225 | if (ret < 0) { | |
1226 | return ret; | |
1227 | } | |
31827373 | 1228 | env->exception_injected = |
a0fb002c JK |
1229 | events.exception.injected ? events.exception.nr : -1; |
1230 | env->has_error_code = events.exception.has_error_code; | |
1231 | env->error_code = events.exception.error_code; | |
1232 | ||
1233 | env->interrupt_injected = | |
1234 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1235 | env->soft_interrupt = events.interrupt.soft; | |
1236 | ||
1237 | env->nmi_injected = events.nmi.injected; | |
1238 | env->nmi_pending = events.nmi.pending; | |
1239 | if (events.nmi.masked) { | |
1240 | env->hflags2 |= HF2_NMI_MASK; | |
1241 | } else { | |
1242 | env->hflags2 &= ~HF2_NMI_MASK; | |
1243 | } | |
1244 | ||
1245 | env->sipi_vector = events.sipi_vector; | |
1246 | #endif | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
b0b1d690 JK |
1251 | static int kvm_guest_debug_workarounds(CPUState *env) |
1252 | { | |
1253 | int ret = 0; | |
1254 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
1255 | unsigned long reinject_trap = 0; | |
1256 | ||
1257 | if (!kvm_has_vcpu_events()) { | |
1258 | if (env->exception_injected == 1) { | |
1259 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1260 | } else if (env->exception_injected == 3) { | |
1261 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1262 | } | |
1263 | env->exception_injected = -1; | |
1264 | } | |
1265 | ||
1266 | /* | |
1267 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1268 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1269 | * by updating the debug state once again if single-stepping is on. | |
1270 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1271 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1272 | * reinject them via SET_GUEST_DEBUG. | |
1273 | */ | |
1274 | if (reinject_trap || | |
1275 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1276 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1277 | } | |
1278 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
1279 | return ret; | |
1280 | } | |
1281 | ||
ff44f1a3 JK |
1282 | static int kvm_put_debugregs(CPUState *env) |
1283 | { | |
1284 | #ifdef KVM_CAP_DEBUGREGS | |
1285 | struct kvm_debugregs dbgregs; | |
1286 | int i; | |
1287 | ||
1288 | if (!kvm_has_debugregs()) { | |
1289 | return 0; | |
1290 | } | |
1291 | ||
1292 | for (i = 0; i < 4; i++) { | |
1293 | dbgregs.db[i] = env->dr[i]; | |
1294 | } | |
1295 | dbgregs.dr6 = env->dr[6]; | |
1296 | dbgregs.dr7 = env->dr[7]; | |
1297 | dbgregs.flags = 0; | |
1298 | ||
1299 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1300 | #else | |
1301 | return 0; | |
1302 | #endif | |
1303 | } | |
1304 | ||
1305 | static int kvm_get_debugregs(CPUState *env) | |
1306 | { | |
1307 | #ifdef KVM_CAP_DEBUGREGS | |
1308 | struct kvm_debugregs dbgregs; | |
1309 | int i, ret; | |
1310 | ||
1311 | if (!kvm_has_debugregs()) { | |
1312 | return 0; | |
1313 | } | |
1314 | ||
1315 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1316 | if (ret < 0) { | |
1317 | return ret; | |
1318 | } | |
1319 | for (i = 0; i < 4; i++) { | |
1320 | env->dr[i] = dbgregs.db[i]; | |
1321 | } | |
1322 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1323 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1324 | #endif | |
1325 | ||
1326 | return 0; | |
1327 | } | |
1328 | ||
ea375f9a | 1329 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1330 | { |
1331 | int ret; | |
1332 | ||
dbaa07c4 JK |
1333 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1334 | ||
05330448 AL |
1335 | ret = kvm_getput_regs(env, 1); |
1336 | if (ret < 0) | |
1337 | return ret; | |
1338 | ||
f1665b21 SY |
1339 | ret = kvm_put_xsave(env); |
1340 | if (ret < 0) | |
1341 | return ret; | |
1342 | ||
1343 | ret = kvm_put_xcrs(env); | |
05330448 AL |
1344 | if (ret < 0) |
1345 | return ret; | |
1346 | ||
1347 | ret = kvm_put_sregs(env); | |
1348 | if (ret < 0) | |
1349 | return ret; | |
1350 | ||
ea643051 | 1351 | ret = kvm_put_msrs(env, level); |
05330448 AL |
1352 | if (ret < 0) |
1353 | return ret; | |
1354 | ||
ea643051 JK |
1355 | if (level >= KVM_PUT_RESET_STATE) { |
1356 | ret = kvm_put_mp_state(env); | |
1357 | if (ret < 0) | |
1358 | return ret; | |
1359 | } | |
f8d926e9 | 1360 | |
ea643051 | 1361 | ret = kvm_put_vcpu_events(env, level); |
a0fb002c JK |
1362 | if (ret < 0) |
1363 | return ret; | |
1364 | ||
b0b1d690 JK |
1365 | /* must be last */ |
1366 | ret = kvm_guest_debug_workarounds(env); | |
1367 | if (ret < 0) | |
1368 | return ret; | |
1369 | ||
ff44f1a3 JK |
1370 | ret = kvm_put_debugregs(env); |
1371 | if (ret < 0) | |
1372 | return ret; | |
1373 | ||
05330448 AL |
1374 | return 0; |
1375 | } | |
1376 | ||
1377 | int kvm_arch_get_registers(CPUState *env) | |
1378 | { | |
1379 | int ret; | |
1380 | ||
dbaa07c4 JK |
1381 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1382 | ||
05330448 AL |
1383 | ret = kvm_getput_regs(env, 0); |
1384 | if (ret < 0) | |
1385 | return ret; | |
1386 | ||
f1665b21 SY |
1387 | ret = kvm_get_xsave(env); |
1388 | if (ret < 0) | |
1389 | return ret; | |
1390 | ||
1391 | ret = kvm_get_xcrs(env); | |
05330448 AL |
1392 | if (ret < 0) |
1393 | return ret; | |
1394 | ||
1395 | ret = kvm_get_sregs(env); | |
1396 | if (ret < 0) | |
1397 | return ret; | |
1398 | ||
1399 | ret = kvm_get_msrs(env); | |
1400 | if (ret < 0) | |
1401 | return ret; | |
1402 | ||
5a2e3c2e JK |
1403 | ret = kvm_get_mp_state(env); |
1404 | if (ret < 0) | |
1405 | return ret; | |
1406 | ||
a0fb002c JK |
1407 | ret = kvm_get_vcpu_events(env); |
1408 | if (ret < 0) | |
1409 | return ret; | |
1410 | ||
ff44f1a3 JK |
1411 | ret = kvm_get_debugregs(env); |
1412 | if (ret < 0) | |
1413 | return ret; | |
1414 | ||
05330448 AL |
1415 | return 0; |
1416 | } | |
1417 | ||
1418 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) | |
1419 | { | |
276ce815 LJ |
1420 | /* Inject NMI */ |
1421 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1422 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1423 | DPRINTF("injected NMI\n"); | |
1424 | kvm_vcpu_ioctl(env, KVM_NMI); | |
1425 | } | |
1426 | ||
05330448 AL |
1427 | /* Try to inject an interrupt if the guest can accept it */ |
1428 | if (run->ready_for_interrupt_injection && | |
1429 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1430 | (env->eflags & IF_MASK)) { | |
1431 | int irq; | |
1432 | ||
1433 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1434 | irq = cpu_get_pic_interrupt(env); | |
1435 | if (irq >= 0) { | |
1436 | struct kvm_interrupt intr; | |
1437 | intr.irq = irq; | |
1438 | /* FIXME: errors */ | |
8c0d577e | 1439 | DPRINTF("injected interrupt %d\n", irq); |
05330448 AL |
1440 | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1441 | } | |
1442 | } | |
1443 | ||
1444 | /* If we have an interrupt but the guest is not ready to receive an | |
1445 | * interrupt, request an interrupt window exit. This will | |
1446 | * cause a return to userspace as soon as the guest is ready to | |
1447 | * receive interrupts. */ | |
1448 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) | |
1449 | run->request_interrupt_window = 1; | |
1450 | else | |
1451 | run->request_interrupt_window = 0; | |
1452 | ||
8c0d577e | 1453 | DPRINTF("setting tpr\n"); |
4a942cea | 1454 | run->cr8 = cpu_get_apic_tpr(env->apic_state); |
05330448 AL |
1455 | |
1456 | return 0; | |
1457 | } | |
1458 | ||
1459 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) | |
1460 | { | |
1461 | if (run->if_flag) | |
1462 | env->eflags |= IF_MASK; | |
1463 | else | |
1464 | env->eflags &= ~IF_MASK; | |
1465 | ||
4a942cea BS |
1466 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1467 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1468 | |
1469 | return 0; | |
1470 | } | |
1471 | ||
0af691d7 MT |
1472 | int kvm_arch_process_irqchip_events(CPUState *env) |
1473 | { | |
1474 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1475 | kvm_cpu_synchronize_state(env); | |
1476 | do_cpu_init(env); | |
1477 | env->exception_index = EXCP_HALTED; | |
1478 | } | |
1479 | ||
1480 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { | |
1481 | kvm_cpu_synchronize_state(env); | |
1482 | do_cpu_sipi(env); | |
1483 | } | |
1484 | ||
1485 | return env->halted; | |
1486 | } | |
1487 | ||
05330448 AL |
1488 | static int kvm_handle_halt(CPUState *env) |
1489 | { | |
1490 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1491 | (env->eflags & IF_MASK)) && | |
1492 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1493 | env->halted = 1; | |
1494 | env->exception_index = EXCP_HLT; | |
1495 | return 0; | |
1496 | } | |
1497 | ||
1498 | return 1; | |
1499 | } | |
1500 | ||
1501 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
1502 | { | |
1503 | int ret = 0; | |
1504 | ||
1505 | switch (run->exit_reason) { | |
1506 | case KVM_EXIT_HLT: | |
8c0d577e | 1507 | DPRINTF("handle_hlt\n"); |
05330448 AL |
1508 | ret = kvm_handle_halt(env); |
1509 | break; | |
1510 | } | |
1511 | ||
1512 | return ret; | |
1513 | } | |
e22a25c9 AL |
1514 | |
1515 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
e22a25c9 AL |
1516 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1517 | { | |
38972938 | 1518 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1519 | |
e22a25c9 | 1520 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
64bf3f4e | 1521 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) |
e22a25c9 AL |
1522 | return -EINVAL; |
1523 | return 0; | |
1524 | } | |
1525 | ||
1526 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1527 | { | |
1528 | uint8_t int3; | |
1529 | ||
1530 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
64bf3f4e | 1531 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) |
e22a25c9 AL |
1532 | return -EINVAL; |
1533 | return 0; | |
1534 | } | |
1535 | ||
1536 | static struct { | |
1537 | target_ulong addr; | |
1538 | int len; | |
1539 | int type; | |
1540 | } hw_breakpoint[4]; | |
1541 | ||
1542 | static int nb_hw_breakpoint; | |
1543 | ||
1544 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1545 | { | |
1546 | int n; | |
1547 | ||
1548 | for (n = 0; n < nb_hw_breakpoint; n++) | |
1549 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && | |
1550 | (hw_breakpoint[n].len == len || len == -1)) | |
1551 | return n; | |
1552 | return -1; | |
1553 | } | |
1554 | ||
1555 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1556 | target_ulong len, int type) | |
1557 | { | |
1558 | switch (type) { | |
1559 | case GDB_BREAKPOINT_HW: | |
1560 | len = 1; | |
1561 | break; | |
1562 | case GDB_WATCHPOINT_WRITE: | |
1563 | case GDB_WATCHPOINT_ACCESS: | |
1564 | switch (len) { | |
1565 | case 1: | |
1566 | break; | |
1567 | case 2: | |
1568 | case 4: | |
1569 | case 8: | |
1570 | if (addr & (len - 1)) | |
1571 | return -EINVAL; | |
1572 | break; | |
1573 | default: | |
1574 | return -EINVAL; | |
1575 | } | |
1576 | break; | |
1577 | default: | |
1578 | return -ENOSYS; | |
1579 | } | |
1580 | ||
1581 | if (nb_hw_breakpoint == 4) | |
1582 | return -ENOBUFS; | |
1583 | ||
1584 | if (find_hw_breakpoint(addr, len, type) >= 0) | |
1585 | return -EEXIST; | |
1586 | ||
1587 | hw_breakpoint[nb_hw_breakpoint].addr = addr; | |
1588 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1589 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1590 | nb_hw_breakpoint++; | |
1591 | ||
1592 | return 0; | |
1593 | } | |
1594 | ||
1595 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1596 | target_ulong len, int type) | |
1597 | { | |
1598 | int n; | |
1599 | ||
1600 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
1601 | if (n < 0) | |
1602 | return -ENOENT; | |
1603 | ||
1604 | nb_hw_breakpoint--; | |
1605 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1606 | ||
1607 | return 0; | |
1608 | } | |
1609 | ||
1610 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1611 | { | |
1612 | nb_hw_breakpoint = 0; | |
1613 | } | |
1614 | ||
1615 | static CPUWatchpoint hw_watchpoint; | |
1616 | ||
1617 | int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) | |
1618 | { | |
1619 | int handle = 0; | |
1620 | int n; | |
1621 | ||
1622 | if (arch_info->exception == 1) { | |
1623 | if (arch_info->dr6 & (1 << 14)) { | |
1624 | if (cpu_single_env->singlestep_enabled) | |
1625 | handle = 1; | |
1626 | } else { | |
1627 | for (n = 0; n < 4; n++) | |
1628 | if (arch_info->dr6 & (1 << n)) | |
1629 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { | |
1630 | case 0x0: | |
1631 | handle = 1; | |
1632 | break; | |
1633 | case 0x1: | |
1634 | handle = 1; | |
1635 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1636 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1637 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1638 | break; | |
1639 | case 0x3: | |
1640 | handle = 1; | |
1641 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1642 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1643 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1644 | break; | |
1645 | } | |
1646 | } | |
1647 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) | |
1648 | handle = 1; | |
1649 | ||
b0b1d690 JK |
1650 | if (!handle) { |
1651 | cpu_synchronize_state(cpu_single_env); | |
1652 | assert(cpu_single_env->exception_injected == -1); | |
1653 | ||
1654 | cpu_single_env->exception_injected = arch_info->exception; | |
1655 | cpu_single_env->has_error_code = 0; | |
1656 | } | |
e22a25c9 AL |
1657 | |
1658 | return handle; | |
1659 | } | |
1660 | ||
1661 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1662 | { | |
1663 | const uint8_t type_code[] = { | |
1664 | [GDB_BREAKPOINT_HW] = 0x0, | |
1665 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1666 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1667 | }; | |
1668 | const uint8_t len_code[] = { | |
1669 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1670 | }; | |
1671 | int n; | |
1672 | ||
1673 | if (kvm_sw_breakpoints_active(env)) | |
1674 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; | |
1675 | ||
1676 | if (nb_hw_breakpoint > 0) { | |
1677 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1678 | dbg->arch.debugreg[7] = 0x0600; | |
1679 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1680 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1681 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1682 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
1683 | (len_code[hw_breakpoint[n].len] << (18 + n*4)); | |
1684 | } | |
1685 | } | |
f1665b21 SY |
1686 | /* Legal xcr0 for loading */ |
1687 | env->xcr0 = 1; | |
e22a25c9 AL |
1688 | } |
1689 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
4513d923 GN |
1690 | |
1691 | bool kvm_arch_stop_on_emulation_error(CPUState *env) | |
1692 | { | |
1693 | return !(env->cr[0] & CR0_PE_MASK) || | |
1694 | ((env->segs[R_CS].selector & 3) != 3); | |
1695 | } | |
1696 | ||
c0532a76 MT |
1697 | static void hardware_memory_error(void) |
1698 | { | |
1699 | fprintf(stderr, "Hardware memory error!\n"); | |
1700 | exit(1); | |
1701 | } | |
1702 | ||
f71ac88f HS |
1703 | #ifdef KVM_CAP_MCE |
1704 | static void kvm_mce_broadcast_rest(CPUState *env) | |
1705 | { | |
1706 | CPUState *cenv; | |
1707 | int family, model, cpuver = env->cpuid_version; | |
1708 | ||
1709 | family = (cpuver >> 8) & 0xf; | |
1710 | model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0xf); | |
1711 | ||
1712 | /* Broadcast MCA signal for processor version 06H_EH and above */ | |
1713 | if ((family == 6 && model >= 14) || family > 6) { | |
1714 | for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) { | |
1715 | if (cenv == env) { | |
1716 | continue; | |
1717 | } | |
1718 | kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC, | |
1719 | MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1); | |
1720 | } | |
1721 | } | |
1722 | } | |
1723 | #endif | |
1724 | ||
c0532a76 MT |
1725 | int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr) |
1726 | { | |
1727 | #if defined(KVM_CAP_MCE) | |
1728 | struct kvm_x86_mce mce = { | |
1729 | .bank = 9, | |
1730 | }; | |
1731 | void *vaddr; | |
1732 | ram_addr_t ram_addr; | |
1733 | target_phys_addr_t paddr; | |
1734 | int r; | |
1735 | ||
1736 | if ((env->mcg_cap & MCG_SER_P) && addr | |
1737 | && (code == BUS_MCEERR_AR | |
1738 | || code == BUS_MCEERR_AO)) { | |
1739 | if (code == BUS_MCEERR_AR) { | |
1740 | /* Fake an Intel architectural Data Load SRAR UCR */ | |
1741 | mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1742 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1743 | | MCI_STATUS_AR | 0x134; | |
1744 | mce.misc = (MCM_ADDR_PHYS << 6) | 0xc; | |
1745 | mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV; | |
1746 | } else { | |
1747 | /* | |
1748 | * If there is an MCE excpetion being processed, ignore | |
1749 | * this SRAO MCE | |
1750 | */ | |
1751 | r = kvm_mce_in_exception(env); | |
1752 | if (r == -1) { | |
1753 | fprintf(stderr, "Failed to get MCE status\n"); | |
1754 | } else if (r) { | |
1755 | return 0; | |
1756 | } | |
1757 | /* Fake an Intel architectural Memory scrubbing UCR */ | |
1758 | mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1759 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1760 | | 0xc0; | |
1761 | mce.misc = (MCM_ADDR_PHYS << 6) | 0xc; | |
1762 | mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV; | |
1763 | } | |
1764 | vaddr = (void *)addr; | |
1765 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1766 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) { | |
1767 | fprintf(stderr, "Hardware memory error for memory used by " | |
1768 | "QEMU itself instead of guest system!\n"); | |
1769 | /* Hope we are lucky for AO MCE */ | |
1770 | if (code == BUS_MCEERR_AO) { | |
1771 | return 0; | |
1772 | } else { | |
1773 | hardware_memory_error(); | |
1774 | } | |
1775 | } | |
1776 | mce.addr = paddr; | |
1777 | r = kvm_set_mce(env, &mce); | |
1778 | if (r < 0) { | |
1779 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
1780 | abort(); | |
1781 | } | |
f71ac88f | 1782 | kvm_mce_broadcast_rest(env); |
c0532a76 MT |
1783 | } else |
1784 | #endif | |
1785 | { | |
1786 | if (code == BUS_MCEERR_AO) { | |
1787 | return 0; | |
1788 | } else if (code == BUS_MCEERR_AR) { | |
1789 | hardware_memory_error(); | |
1790 | } else { | |
1791 | return 1; | |
1792 | } | |
1793 | } | |
1794 | return 0; | |
1795 | } | |
1796 | ||
1797 | int kvm_on_sigbus(int code, void *addr) | |
1798 | { | |
1799 | #if defined(KVM_CAP_MCE) | |
1800 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
1801 | uint64_t status; | |
1802 | void *vaddr; | |
1803 | ram_addr_t ram_addr; | |
1804 | target_phys_addr_t paddr; | |
c0532a76 MT |
1805 | |
1806 | /* Hope we are lucky for AO MCE */ | |
1807 | vaddr = addr; | |
1808 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1809 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) { | |
1810 | fprintf(stderr, "Hardware memory error for memory used by " | |
1811 | "QEMU itself instead of guest system!: %p\n", addr); | |
1812 | return 0; | |
1813 | } | |
1814 | status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1815 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1816 | | 0xc0; | |
1817 | kvm_inject_x86_mce(first_cpu, 9, status, | |
1818 | MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr, | |
1819 | (MCM_ADDR_PHYS << 6) | 0xc, 1); | |
f71ac88f | 1820 | kvm_mce_broadcast_rest(first_cpu); |
c0532a76 MT |
1821 | } else |
1822 | #endif | |
1823 | { | |
1824 | if (code == BUS_MCEERR_AO) { | |
1825 | return 0; | |
1826 | } else if (code == BUS_MCEERR_AR) { | |
1827 | hardware_memory_error(); | |
1828 | } else { | |
1829 | return 1; | |
1830 | } | |
1831 | } | |
1832 | return 0; | |
1833 | } |