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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
5802e066 | 21 | #include <linux/kvm_para.h> |
05330448 AL |
22 | |
23 | #include "qemu-common.h" | |
24 | #include "sysemu.h" | |
25 | #include "kvm.h" | |
26 | #include "cpu.h" | |
e22a25c9 | 27 | #include "gdbstub.h" |
0e607a80 | 28 | #include "host-utils.h" |
4c5b10b7 | 29 | #include "hw/pc.h" |
408392b3 | 30 | #include "hw/apic.h" |
35bed8ee | 31 | #include "ioport.h" |
05330448 AL |
32 | |
33 | //#define DEBUG_KVM | |
34 | ||
35 | #ifdef DEBUG_KVM | |
8c0d577e | 36 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
37 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
38 | #else | |
8c0d577e | 39 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
40 | do { } while (0) |
41 | #endif | |
42 | ||
1a03675d GC |
43 | #define MSR_KVM_WALL_CLOCK 0x11 |
44 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
45 | ||
c0532a76 MT |
46 | #ifndef BUS_MCEERR_AR |
47 | #define BUS_MCEERR_AR 4 | |
48 | #endif | |
49 | #ifndef BUS_MCEERR_AO | |
50 | #define BUS_MCEERR_AO 5 | |
51 | #endif | |
52 | ||
94a8d39a JK |
53 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
54 | KVM_CAP_INFO(SET_TSS_ADDR), | |
55 | KVM_CAP_INFO(EXT_CPUID), | |
56 | KVM_CAP_INFO(MP_STATE), | |
57 | KVM_CAP_LAST_INFO | |
58 | }; | |
25d2e361 | 59 | |
c3a3a7d3 JK |
60 | static bool has_msr_star; |
61 | static bool has_msr_hsave_pa; | |
c5999bfc | 62 | static bool has_msr_async_pf_en; |
25d2e361 | 63 | static int lm_capable_kernel; |
b827df58 AK |
64 | |
65 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
66 | { | |
67 | struct kvm_cpuid2 *cpuid; | |
68 | int r, size; | |
69 | ||
70 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
71 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
72 | cpuid->nent = max; | |
73 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
74 | if (r == 0 && cpuid->nent >= max) { |
75 | r = -E2BIG; | |
76 | } | |
b827df58 AK |
77 | if (r < 0) { |
78 | if (r == -E2BIG) { | |
79 | qemu_free(cpuid); | |
80 | return NULL; | |
81 | } else { | |
82 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
83 | strerror(-r)); | |
84 | exit(1); | |
85 | } | |
86 | } | |
87 | return cpuid; | |
88 | } | |
89 | ||
0c31b744 GC |
90 | struct kvm_para_features { |
91 | int cap; | |
92 | int feature; | |
93 | } para_features[] = { | |
94 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
95 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
96 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
0c31b744 | 97 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
0c31b744 GC |
98 | { -1, -1 } |
99 | }; | |
100 | ||
101 | static int get_para_features(CPUState *env) | |
102 | { | |
103 | int i, features = 0; | |
104 | ||
105 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
106 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) { | |
107 | features |= (1 << para_features[i].feature); | |
108 | } | |
109 | } | |
110 | ||
111 | return features; | |
112 | } | |
0c31b744 GC |
113 | |
114 | ||
c958a8bd SY |
115 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
116 | uint32_t index, int reg) | |
b827df58 AK |
117 | { |
118 | struct kvm_cpuid2 *cpuid; | |
119 | int i, max; | |
120 | uint32_t ret = 0; | |
121 | uint32_t cpuid_1_edx; | |
0c31b744 | 122 | int has_kvm_features = 0; |
b827df58 | 123 | |
b827df58 AK |
124 | max = 1; |
125 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
126 | max *= 2; | |
127 | } | |
128 | ||
129 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
130 | if (cpuid->entries[i].function == function && |
131 | cpuid->entries[i].index == index) { | |
0c31b744 GC |
132 | if (cpuid->entries[i].function == KVM_CPUID_FEATURES) { |
133 | has_kvm_features = 1; | |
134 | } | |
b827df58 AK |
135 | switch (reg) { |
136 | case R_EAX: | |
137 | ret = cpuid->entries[i].eax; | |
138 | break; | |
139 | case R_EBX: | |
140 | ret = cpuid->entries[i].ebx; | |
141 | break; | |
142 | case R_ECX: | |
143 | ret = cpuid->entries[i].ecx; | |
144 | break; | |
145 | case R_EDX: | |
146 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
147 | switch (function) { |
148 | case 1: | |
149 | /* KVM before 2.6.30 misreports the following features */ | |
150 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
151 | break; | |
152 | case 0x80000001: | |
b827df58 AK |
153 | /* On Intel, kvm returns cpuid according to the Intel spec, |
154 | * so add missing bits according to the AMD spec: | |
155 | */ | |
c958a8bd | 156 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 157 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 158 | break; |
b827df58 AK |
159 | } |
160 | break; | |
161 | } | |
162 | } | |
163 | } | |
164 | ||
165 | qemu_free(cpuid); | |
166 | ||
0c31b744 GC |
167 | /* fallback for older kernels */ |
168 | if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) { | |
169 | ret = get_para_features(env); | |
b9bec74b | 170 | } |
0c31b744 GC |
171 | |
172 | return ret; | |
bb0300dc | 173 | } |
bb0300dc | 174 | |
3c85e74f HY |
175 | typedef struct HWPoisonPage { |
176 | ram_addr_t ram_addr; | |
177 | QLIST_ENTRY(HWPoisonPage) list; | |
178 | } HWPoisonPage; | |
179 | ||
180 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
181 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
182 | ||
183 | static void kvm_unpoison_all(void *param) | |
184 | { | |
185 | HWPoisonPage *page, *next_page; | |
186 | ||
187 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
188 | QLIST_REMOVE(page, list); | |
189 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
190 | qemu_free(page); | |
191 | } | |
192 | } | |
193 | ||
3c85e74f HY |
194 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) |
195 | { | |
196 | HWPoisonPage *page; | |
197 | ||
198 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
199 | if (page->ram_addr == ram_addr) { | |
200 | return; | |
201 | } | |
202 | } | |
203 | page = qemu_malloc(sizeof(HWPoisonPage)); | |
204 | page->ram_addr = ram_addr; | |
205 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
206 | } | |
207 | ||
e7701825 MT |
208 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
209 | int *max_banks) | |
210 | { | |
211 | int r; | |
212 | ||
14a09518 | 213 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
214 | if (r > 0) { |
215 | *max_banks = r; | |
216 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
217 | } | |
218 | return -ENOSYS; | |
219 | } | |
220 | ||
c34d440a | 221 | static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code) |
e7701825 | 222 | { |
c34d440a JK |
223 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
224 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
225 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
e7701825 | 226 | |
c34d440a JK |
227 | if (code == BUS_MCEERR_AR) { |
228 | status |= MCI_STATUS_AR | 0x134; | |
229 | mcg_status |= MCG_STATUS_EIPV; | |
230 | } else { | |
231 | status |= 0xc0; | |
232 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 233 | } |
c34d440a JK |
234 | cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr, |
235 | (MCM_ADDR_PHYS << 6) | 0xc, | |
236 | cpu_x86_support_mca_broadcast(env) ? | |
237 | MCE_INJECT_BROADCAST : 0); | |
419fb20a | 238 | } |
419fb20a JK |
239 | |
240 | static void hardware_memory_error(void) | |
241 | { | |
242 | fprintf(stderr, "Hardware memory error!\n"); | |
243 | exit(1); | |
244 | } | |
245 | ||
246 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) | |
247 | { | |
419fb20a JK |
248 | ram_addr_t ram_addr; |
249 | target_phys_addr_t paddr; | |
250 | ||
251 | if ((env->mcg_cap & MCG_SER_P) && addr | |
c34d440a JK |
252 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
253 | if (qemu_ram_addr_from_host(addr, &ram_addr) || | |
254 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, | |
255 | &paddr)) { | |
419fb20a JK |
256 | fprintf(stderr, "Hardware memory error for memory used by " |
257 | "QEMU itself instead of guest system!\n"); | |
258 | /* Hope we are lucky for AO MCE */ | |
259 | if (code == BUS_MCEERR_AO) { | |
260 | return 0; | |
261 | } else { | |
262 | hardware_memory_error(); | |
263 | } | |
264 | } | |
3c85e74f | 265 | kvm_hwpoison_page_add(ram_addr); |
c34d440a | 266 | kvm_mce_inject(env, paddr, code); |
e56ff191 | 267 | } else { |
419fb20a JK |
268 | if (code == BUS_MCEERR_AO) { |
269 | return 0; | |
270 | } else if (code == BUS_MCEERR_AR) { | |
271 | hardware_memory_error(); | |
272 | } else { | |
273 | return 1; | |
274 | } | |
275 | } | |
276 | return 0; | |
277 | } | |
278 | ||
279 | int kvm_arch_on_sigbus(int code, void *addr) | |
280 | { | |
419fb20a | 281 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { |
419fb20a JK |
282 | ram_addr_t ram_addr; |
283 | target_phys_addr_t paddr; | |
284 | ||
285 | /* Hope we are lucky for AO MCE */ | |
c34d440a | 286 | if (qemu_ram_addr_from_host(addr, &ram_addr) || |
419fb20a JK |
287 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, |
288 | &paddr)) { | |
289 | fprintf(stderr, "Hardware memory error for memory used by " | |
290 | "QEMU itself instead of guest system!: %p\n", addr); | |
291 | return 0; | |
292 | } | |
3c85e74f | 293 | kvm_hwpoison_page_add(ram_addr); |
c34d440a | 294 | kvm_mce_inject(first_cpu, paddr, code); |
e56ff191 | 295 | } else { |
419fb20a JK |
296 | if (code == BUS_MCEERR_AO) { |
297 | return 0; | |
298 | } else if (code == BUS_MCEERR_AR) { | |
299 | hardware_memory_error(); | |
300 | } else { | |
301 | return 1; | |
302 | } | |
303 | } | |
304 | return 0; | |
305 | } | |
e7701825 | 306 | |
ab443475 JK |
307 | static int kvm_inject_mce_oldstyle(CPUState *env) |
308 | { | |
ab443475 JK |
309 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { |
310 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
311 | struct kvm_x86_mce mce; | |
312 | ||
313 | env->exception_injected = -1; | |
314 | ||
315 | /* | |
316 | * There must be at least one bank in use if an MCE is pending. | |
317 | * Find it and use its values for the event injection. | |
318 | */ | |
319 | for (bank = 0; bank < bank_num; bank++) { | |
320 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
321 | break; | |
322 | } | |
323 | } | |
324 | assert(bank < bank_num); | |
325 | ||
326 | mce.bank = bank; | |
327 | mce.status = env->mce_banks[bank * 4 + 1]; | |
328 | mce.mcg_status = env->mcg_status; | |
329 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
330 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
331 | ||
332 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce); | |
333 | } | |
ab443475 JK |
334 | return 0; |
335 | } | |
336 | ||
b8cc45d6 GC |
337 | static void cpu_update_state(void *opaque, int running, int reason) |
338 | { | |
339 | CPUState *env = opaque; | |
340 | ||
341 | if (running) { | |
342 | env->tsc_valid = false; | |
343 | } | |
344 | } | |
345 | ||
05330448 AL |
346 | int kvm_arch_init_vcpu(CPUState *env) |
347 | { | |
348 | struct { | |
486bd5a2 AL |
349 | struct kvm_cpuid2 cpuid; |
350 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 351 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 352 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 353 | uint32_t unused; |
bb0300dc | 354 | struct kvm_cpuid_entry2 *c; |
bb0300dc | 355 | uint32_t signature[3]; |
05330448 | 356 | |
c958a8bd | 357 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
358 | |
359 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 360 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
361 | env->cpuid_ext_features |= i; |
362 | ||
457dfed6 | 363 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 364 | 0, R_EDX); |
457dfed6 | 365 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 366 | 0, R_ECX); |
296acb64 JR |
367 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A, |
368 | 0, R_EDX); | |
369 | ||
6c1f42fe | 370 | |
05330448 AL |
371 | cpuid_i = 0; |
372 | ||
bb0300dc GN |
373 | /* Paravirtualization CPUIDs */ |
374 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
375 | c = &cpuid_data.entries[cpuid_i++]; | |
376 | memset(c, 0, sizeof(*c)); | |
377 | c->function = KVM_CPUID_SIGNATURE; | |
378 | c->eax = 0; | |
379 | c->ebx = signature[0]; | |
380 | c->ecx = signature[1]; | |
381 | c->edx = signature[2]; | |
382 | ||
383 | c = &cpuid_data.entries[cpuid_i++]; | |
384 | memset(c, 0, sizeof(*c)); | |
385 | c->function = KVM_CPUID_FEATURES; | |
0c31b744 GC |
386 | c->eax = env->cpuid_kvm_features & kvm_arch_get_supported_cpuid(env, |
387 | KVM_CPUID_FEATURES, 0, R_EAX); | |
388 | ||
0c31b744 | 389 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); |
bb0300dc | 390 | |
a33609ca | 391 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
392 | |
393 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 394 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
395 | |
396 | switch (i) { | |
a36b1029 AL |
397 | case 2: { |
398 | /* Keep reading function 2 till all the input is received */ | |
399 | int times; | |
400 | ||
a36b1029 | 401 | c->function = i; |
a33609ca AL |
402 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
403 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
404 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
405 | times = c->eax & 0xff; | |
a36b1029 AL |
406 | |
407 | for (j = 1; j < times; ++j) { | |
a33609ca | 408 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 409 | c->function = i; |
a33609ca AL |
410 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
411 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
412 | } |
413 | break; | |
414 | } | |
486bd5a2 AL |
415 | case 4: |
416 | case 0xb: | |
417 | case 0xd: | |
418 | for (j = 0; ; j++) { | |
486bd5a2 AL |
419 | c->function = i; |
420 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
421 | c->index = j; | |
a33609ca | 422 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 423 | |
b9bec74b | 424 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 425 | break; |
b9bec74b JK |
426 | } |
427 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 428 | break; |
b9bec74b JK |
429 | } |
430 | if (i == 0xd && c->eax == 0) { | |
486bd5a2 | 431 | break; |
b9bec74b | 432 | } |
a33609ca | 433 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
434 | } |
435 | break; | |
436 | default: | |
486bd5a2 | 437 | c->function = i; |
a33609ca AL |
438 | c->flags = 0; |
439 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
440 | break; |
441 | } | |
05330448 | 442 | } |
a33609ca | 443 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
444 | |
445 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 446 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 447 | |
05330448 | 448 | c->function = i; |
a33609ca AL |
449 | c->flags = 0; |
450 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
451 | } |
452 | ||
b3baa152 | 453 | /* Call Centaur's CPUID instructions they are supported. */ |
454 | if (env->cpuid_xlevel2 > 0) { | |
455 | env->cpuid_ext4_features &= | |
456 | kvm_arch_get_supported_cpuid(env, 0xC0000001, 0, R_EDX); | |
457 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); | |
458 | ||
459 | for (i = 0xC0000000; i <= limit; i++) { | |
460 | c = &cpuid_data.entries[cpuid_i++]; | |
461 | ||
462 | c->function = i; | |
463 | c->flags = 0; | |
464 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
465 | } | |
466 | } | |
467 | ||
05330448 AL |
468 | cpuid_data.cpuid.nent = cpuid_i; |
469 | ||
e7701825 MT |
470 | if (((env->cpuid_version >> 8)&0xF) >= 6 |
471 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
472 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
473 | uint64_t mcg_cap; | |
474 | int banks; | |
32a42024 | 475 | int ret; |
e7701825 | 476 | |
75d49497 JK |
477 | ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks); |
478 | if (ret < 0) { | |
479 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
480 | return ret; | |
e7701825 | 481 | } |
75d49497 JK |
482 | |
483 | if (banks > MCE_BANKS_DEF) { | |
484 | banks = MCE_BANKS_DEF; | |
485 | } | |
486 | mcg_cap &= MCE_CAP_DEF; | |
487 | mcg_cap |= banks; | |
488 | ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap); | |
489 | if (ret < 0) { | |
490 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
491 | return ret; | |
492 | } | |
493 | ||
494 | env->mcg_cap = mcg_cap; | |
e7701825 | 495 | } |
e7701825 | 496 | |
b8cc45d6 GC |
497 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
498 | ||
486bd5a2 | 499 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
500 | } |
501 | ||
caa5af0f JK |
502 | void kvm_arch_reset_vcpu(CPUState *env) |
503 | { | |
e73223a5 | 504 | env->exception_injected = -1; |
0e607a80 | 505 | env->interrupt_injected = -1; |
1a5e9d2f | 506 | env->xcr0 = 1; |
ddced198 MT |
507 | if (kvm_irqchip_in_kernel()) { |
508 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
509 | KVM_MP_STATE_UNINITIALIZED; | |
510 | } else { | |
511 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
512 | } | |
caa5af0f JK |
513 | } |
514 | ||
c3a3a7d3 | 515 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 516 | { |
75b10c43 | 517 | static int kvm_supported_msrs; |
c3a3a7d3 | 518 | int ret = 0; |
05330448 AL |
519 | |
520 | /* first time */ | |
75b10c43 | 521 | if (kvm_supported_msrs == 0) { |
05330448 AL |
522 | struct kvm_msr_list msr_list, *kvm_msr_list; |
523 | ||
75b10c43 | 524 | kvm_supported_msrs = -1; |
05330448 AL |
525 | |
526 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
527 | * save/restore */ | |
4c9f7372 | 528 | msr_list.nmsrs = 0; |
c3a3a7d3 | 529 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 530 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 531 | return ret; |
6fb6d245 | 532 | } |
d9db889f JK |
533 | /* Old kernel modules had a bug and could write beyond the provided |
534 | memory. Allocate at least a safe amount of 1K. */ | |
535 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
536 | msr_list.nmsrs * | |
537 | sizeof(msr_list.indices[0]))); | |
05330448 | 538 | |
55308450 | 539 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 540 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
541 | if (ret >= 0) { |
542 | int i; | |
543 | ||
544 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
545 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 546 | has_msr_star = true; |
75b10c43 MT |
547 | continue; |
548 | } | |
549 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 550 | has_msr_hsave_pa = true; |
75b10c43 | 551 | continue; |
05330448 AL |
552 | } |
553 | } | |
554 | } | |
555 | ||
4a043713 | 556 | qemu_free(kvm_msr_list); |
05330448 AL |
557 | } |
558 | ||
c3a3a7d3 | 559 | return ret; |
05330448 AL |
560 | } |
561 | ||
cad1e282 | 562 | int kvm_arch_init(KVMState *s) |
20420430 | 563 | { |
11076198 | 564 | uint64_t identity_base = 0xfffbc000; |
20420430 | 565 | int ret; |
25d2e361 | 566 | struct utsname utsname; |
20420430 | 567 | |
c3a3a7d3 | 568 | ret = kvm_get_supported_msrs(s); |
20420430 | 569 | if (ret < 0) { |
20420430 SY |
570 | return ret; |
571 | } | |
25d2e361 MT |
572 | |
573 | uname(&utsname); | |
574 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
575 | ||
4c5b10b7 | 576 | /* |
11076198 JK |
577 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
578 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
579 | * Since these must be part of guest physical memory, we need to allocate | |
580 | * them, both by setting their start addresses in the kernel and by | |
581 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
582 | * | |
583 | * Older KVM versions may not support setting the identity map base. In | |
584 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
585 | * size. | |
4c5b10b7 | 586 | */ |
11076198 JK |
587 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { |
588 | /* Allows up to 16M BIOSes. */ | |
589 | identity_base = 0xfeffc000; | |
590 | ||
591 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
592 | if (ret < 0) { | |
593 | return ret; | |
594 | } | |
4c5b10b7 | 595 | } |
e56ff191 | 596 | |
11076198 JK |
597 | /* Set TSS base one page after EPT identity map. */ |
598 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
599 | if (ret < 0) { |
600 | return ret; | |
601 | } | |
602 | ||
11076198 JK |
603 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
604 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 605 | if (ret < 0) { |
11076198 | 606 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
607 | return ret; |
608 | } | |
3c85e74f | 609 | qemu_register_reset(kvm_unpoison_all, NULL); |
20420430 | 610 | |
11076198 | 611 | return 0; |
05330448 | 612 | } |
b9bec74b | 613 | |
05330448 AL |
614 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
615 | { | |
616 | lhs->selector = rhs->selector; | |
617 | lhs->base = rhs->base; | |
618 | lhs->limit = rhs->limit; | |
619 | lhs->type = 3; | |
620 | lhs->present = 1; | |
621 | lhs->dpl = 3; | |
622 | lhs->db = 0; | |
623 | lhs->s = 1; | |
624 | lhs->l = 0; | |
625 | lhs->g = 0; | |
626 | lhs->avl = 0; | |
627 | lhs->unusable = 0; | |
628 | } | |
629 | ||
630 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
631 | { | |
632 | unsigned flags = rhs->flags; | |
633 | lhs->selector = rhs->selector; | |
634 | lhs->base = rhs->base; | |
635 | lhs->limit = rhs->limit; | |
636 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
637 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 638 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
639 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
640 | lhs->s = (flags & DESC_S_MASK) != 0; | |
641 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
642 | lhs->g = (flags & DESC_G_MASK) != 0; | |
643 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
644 | lhs->unusable = 0; | |
645 | } | |
646 | ||
647 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
648 | { | |
649 | lhs->selector = rhs->selector; | |
650 | lhs->base = rhs->base; | |
651 | lhs->limit = rhs->limit; | |
b9bec74b JK |
652 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
653 | (rhs->present * DESC_P_MASK) | | |
654 | (rhs->dpl << DESC_DPL_SHIFT) | | |
655 | (rhs->db << DESC_B_SHIFT) | | |
656 | (rhs->s * DESC_S_MASK) | | |
657 | (rhs->l << DESC_L_SHIFT) | | |
658 | (rhs->g * DESC_G_MASK) | | |
659 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
660 | } |
661 | ||
662 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
663 | { | |
b9bec74b | 664 | if (set) { |
05330448 | 665 | *kvm_reg = *qemu_reg; |
b9bec74b | 666 | } else { |
05330448 | 667 | *qemu_reg = *kvm_reg; |
b9bec74b | 668 | } |
05330448 AL |
669 | } |
670 | ||
671 | static int kvm_getput_regs(CPUState *env, int set) | |
672 | { | |
673 | struct kvm_regs regs; | |
674 | int ret = 0; | |
675 | ||
676 | if (!set) { | |
677 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
b9bec74b | 678 | if (ret < 0) { |
05330448 | 679 | return ret; |
b9bec74b | 680 | } |
05330448 AL |
681 | } |
682 | ||
683 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
684 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
685 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
686 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
687 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
688 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
689 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
690 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
691 | #ifdef TARGET_X86_64 | |
692 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
693 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
694 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
695 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
696 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
697 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
698 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
699 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
700 | #endif | |
701 | ||
702 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
703 | kvm_getput_reg(®s.rip, &env->eip, set); | |
704 | ||
b9bec74b | 705 | if (set) { |
05330448 | 706 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
b9bec74b | 707 | } |
05330448 AL |
708 | |
709 | return ret; | |
710 | } | |
711 | ||
712 | static int kvm_put_fpu(CPUState *env) | |
713 | { | |
714 | struct kvm_fpu fpu; | |
715 | int i; | |
716 | ||
717 | memset(&fpu, 0, sizeof fpu); | |
718 | fpu.fsw = env->fpus & ~(7 << 11); | |
719 | fpu.fsw |= (env->fpstt & 7) << 11; | |
720 | fpu.fcw = env->fpuc; | |
42cc8fa6 JK |
721 | fpu.last_opcode = env->fpop; |
722 | fpu.last_ip = env->fpip; | |
723 | fpu.last_dp = env->fpdp; | |
b9bec74b JK |
724 | for (i = 0; i < 8; ++i) { |
725 | fpu.ftwx |= (!env->fptags[i]) << i; | |
726 | } | |
05330448 AL |
727 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
728 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
729 | fpu.mxcsr = env->mxcsr; | |
730 | ||
731 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
732 | } | |
733 | ||
f1665b21 SY |
734 | #define XSAVE_CWD_RIP 2 |
735 | #define XSAVE_CWD_RDP 4 | |
736 | #define XSAVE_MXCSR 6 | |
737 | #define XSAVE_ST_SPACE 8 | |
738 | #define XSAVE_XMM_SPACE 40 | |
739 | #define XSAVE_XSTATE_BV 128 | |
740 | #define XSAVE_YMMH_SPACE 144 | |
f1665b21 SY |
741 | |
742 | static int kvm_put_xsave(CPUState *env) | |
743 | { | |
0f53994f | 744 | int i, r; |
f1665b21 | 745 | struct kvm_xsave* xsave; |
42cc8fa6 | 746 | uint16_t cwd, swd, twd; |
f1665b21 | 747 | |
b9bec74b | 748 | if (!kvm_has_xsave()) { |
f1665b21 | 749 | return kvm_put_fpu(env); |
b9bec74b | 750 | } |
f1665b21 SY |
751 | |
752 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
753 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
42cc8fa6 | 754 | cwd = swd = twd = 0; |
f1665b21 SY |
755 | swd = env->fpus & ~(7 << 11); |
756 | swd |= (env->fpstt & 7) << 11; | |
757 | cwd = env->fpuc; | |
b9bec74b | 758 | for (i = 0; i < 8; ++i) { |
f1665b21 | 759 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 760 | } |
f1665b21 | 761 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; |
42cc8fa6 JK |
762 | xsave->region[1] = (uint32_t)(env->fpop << 16) + twd; |
763 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); | |
764 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
f1665b21 SY |
765 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
766 | sizeof env->fpregs); | |
767 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
768 | sizeof env->xmm_regs); | |
769 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
770 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
771 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
772 | sizeof env->ymmh_regs); | |
0f53994f MT |
773 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
774 | qemu_free(xsave); | |
775 | return r; | |
f1665b21 SY |
776 | } |
777 | ||
778 | static int kvm_put_xcrs(CPUState *env) | |
779 | { | |
f1665b21 SY |
780 | struct kvm_xcrs xcrs; |
781 | ||
b9bec74b | 782 | if (!kvm_has_xcrs()) { |
f1665b21 | 783 | return 0; |
b9bec74b | 784 | } |
f1665b21 SY |
785 | |
786 | xcrs.nr_xcrs = 1; | |
787 | xcrs.flags = 0; | |
788 | xcrs.xcrs[0].xcr = 0; | |
789 | xcrs.xcrs[0].value = env->xcr0; | |
790 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
f1665b21 SY |
791 | } |
792 | ||
05330448 AL |
793 | static int kvm_put_sregs(CPUState *env) |
794 | { | |
795 | struct kvm_sregs sregs; | |
796 | ||
0e607a80 JK |
797 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
798 | if (env->interrupt_injected >= 0) { | |
799 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
800 | (uint64_t)1 << (env->interrupt_injected % 64); | |
801 | } | |
05330448 AL |
802 | |
803 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
804 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
805 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
806 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
807 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
808 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
809 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 810 | } else { |
b9bec74b JK |
811 | set_seg(&sregs.cs, &env->segs[R_CS]); |
812 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
813 | set_seg(&sregs.es, &env->segs[R_ES]); | |
814 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
815 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
816 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
817 | } |
818 | ||
819 | set_seg(&sregs.tr, &env->tr); | |
820 | set_seg(&sregs.ldt, &env->ldt); | |
821 | ||
822 | sregs.idt.limit = env->idt.limit; | |
823 | sregs.idt.base = env->idt.base; | |
824 | sregs.gdt.limit = env->gdt.limit; | |
825 | sregs.gdt.base = env->gdt.base; | |
826 | ||
827 | sregs.cr0 = env->cr[0]; | |
828 | sregs.cr2 = env->cr[2]; | |
829 | sregs.cr3 = env->cr[3]; | |
830 | sregs.cr4 = env->cr[4]; | |
831 | ||
4a942cea BS |
832 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
833 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
834 | |
835 | sregs.efer = env->efer; | |
836 | ||
837 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
838 | } | |
839 | ||
840 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
841 | uint32_t index, uint64_t value) | |
842 | { | |
843 | entry->index = index; | |
844 | entry->data = value; | |
845 | } | |
846 | ||
ea643051 | 847 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
848 | { |
849 | struct { | |
850 | struct kvm_msrs info; | |
851 | struct kvm_msr_entry entries[100]; | |
852 | } msr_data; | |
853 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 854 | int n = 0; |
05330448 AL |
855 | |
856 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
857 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
858 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
0c03266a | 859 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); |
c3a3a7d3 | 860 | if (has_msr_star) { |
b9bec74b JK |
861 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
862 | } | |
c3a3a7d3 | 863 | if (has_msr_hsave_pa) { |
75b10c43 | 864 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 865 | } |
05330448 | 866 | #ifdef TARGET_X86_64 |
25d2e361 MT |
867 | if (lm_capable_kernel) { |
868 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
869 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
870 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
871 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
872 | } | |
05330448 | 873 | #endif |
ea643051 | 874 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
875 | /* |
876 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
877 | * writeback. Until this is fixed, we only write the offset to SMP | |
878 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
879 | * huge jump-backs that would occur without any writeback at all. | |
880 | */ | |
881 | if (smp_cpus == 1 || env->tsc != 0) { | |
882 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
883 | } | |
ff5c186b JK |
884 | } |
885 | /* | |
886 | * The following paravirtual MSRs have side effects on the guest or are | |
887 | * too heavy for normal writeback. Limit them to reset or full state | |
888 | * updates. | |
889 | */ | |
890 | if (level >= KVM_PUT_RESET_STATE) { | |
ea643051 JK |
891 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
892 | env->system_time_msr); | |
893 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
c5999bfc JK |
894 | if (has_msr_async_pf_en) { |
895 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
896 | env->async_pf_en_msr); | |
897 | } | |
ea643051 | 898 | } |
57780495 | 899 | if (env->mcg_cap) { |
d8da8574 | 900 | int i; |
b9bec74b | 901 | |
c34d440a JK |
902 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
903 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
904 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
905 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
57780495 MT |
906 | } |
907 | } | |
1a03675d | 908 | |
05330448 AL |
909 | msr_data.info.nmsrs = n; |
910 | ||
911 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
912 | ||
913 | } | |
914 | ||
915 | ||
916 | static int kvm_get_fpu(CPUState *env) | |
917 | { | |
918 | struct kvm_fpu fpu; | |
919 | int i, ret; | |
920 | ||
921 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
b9bec74b | 922 | if (ret < 0) { |
05330448 | 923 | return ret; |
b9bec74b | 924 | } |
05330448 AL |
925 | |
926 | env->fpstt = (fpu.fsw >> 11) & 7; | |
927 | env->fpus = fpu.fsw; | |
928 | env->fpuc = fpu.fcw; | |
42cc8fa6 JK |
929 | env->fpop = fpu.last_opcode; |
930 | env->fpip = fpu.last_ip; | |
931 | env->fpdp = fpu.last_dp; | |
b9bec74b JK |
932 | for (i = 0; i < 8; ++i) { |
933 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
934 | } | |
05330448 AL |
935 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
936 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
937 | env->mxcsr = fpu.mxcsr; | |
938 | ||
939 | return 0; | |
940 | } | |
941 | ||
f1665b21 SY |
942 | static int kvm_get_xsave(CPUState *env) |
943 | { | |
f1665b21 SY |
944 | struct kvm_xsave* xsave; |
945 | int ret, i; | |
42cc8fa6 | 946 | uint16_t cwd, swd, twd; |
f1665b21 | 947 | |
b9bec74b | 948 | if (!kvm_has_xsave()) { |
f1665b21 | 949 | return kvm_get_fpu(env); |
b9bec74b | 950 | } |
f1665b21 SY |
951 | |
952 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
953 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
0f53994f MT |
954 | if (ret < 0) { |
955 | qemu_free(xsave); | |
f1665b21 | 956 | return ret; |
0f53994f | 957 | } |
f1665b21 SY |
958 | |
959 | cwd = (uint16_t)xsave->region[0]; | |
960 | swd = (uint16_t)(xsave->region[0] >> 16); | |
961 | twd = (uint16_t)xsave->region[1]; | |
42cc8fa6 | 962 | env->fpop = (uint16_t)(xsave->region[1] >> 16); |
f1665b21 SY |
963 | env->fpstt = (swd >> 11) & 7; |
964 | env->fpus = swd; | |
965 | env->fpuc = cwd; | |
b9bec74b | 966 | for (i = 0; i < 8; ++i) { |
f1665b21 | 967 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 968 | } |
42cc8fa6 JK |
969 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); |
970 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
f1665b21 SY |
971 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
972 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
973 | sizeof env->fpregs); | |
974 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
975 | sizeof env->xmm_regs); | |
976 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
977 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
978 | sizeof env->ymmh_regs); | |
0f53994f | 979 | qemu_free(xsave); |
f1665b21 | 980 | return 0; |
f1665b21 SY |
981 | } |
982 | ||
983 | static int kvm_get_xcrs(CPUState *env) | |
984 | { | |
f1665b21 SY |
985 | int i, ret; |
986 | struct kvm_xcrs xcrs; | |
987 | ||
b9bec74b | 988 | if (!kvm_has_xcrs()) { |
f1665b21 | 989 | return 0; |
b9bec74b | 990 | } |
f1665b21 SY |
991 | |
992 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
b9bec74b | 993 | if (ret < 0) { |
f1665b21 | 994 | return ret; |
b9bec74b | 995 | } |
f1665b21 | 996 | |
b9bec74b | 997 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
998 | /* Only support xcr0 now */ |
999 | if (xcrs.xcrs[0].xcr == 0) { | |
1000 | env->xcr0 = xcrs.xcrs[0].value; | |
1001 | break; | |
1002 | } | |
b9bec74b | 1003 | } |
f1665b21 | 1004 | return 0; |
f1665b21 SY |
1005 | } |
1006 | ||
05330448 AL |
1007 | static int kvm_get_sregs(CPUState *env) |
1008 | { | |
1009 | struct kvm_sregs sregs; | |
1010 | uint32_t hflags; | |
0e607a80 | 1011 | int bit, i, ret; |
05330448 AL |
1012 | |
1013 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
b9bec74b | 1014 | if (ret < 0) { |
05330448 | 1015 | return ret; |
b9bec74b | 1016 | } |
05330448 | 1017 | |
0e607a80 JK |
1018 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
1019 | to find it and save its number instead (-1 for none). */ | |
1020 | env->interrupt_injected = -1; | |
1021 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1022 | if (sregs.interrupt_bitmap[i]) { | |
1023 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1024 | env->interrupt_injected = i * 64 + bit; | |
1025 | break; | |
1026 | } | |
1027 | } | |
05330448 AL |
1028 | |
1029 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1030 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1031 | get_seg(&env->segs[R_ES], &sregs.es); | |
1032 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1033 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1034 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1035 | ||
1036 | get_seg(&env->tr, &sregs.tr); | |
1037 | get_seg(&env->ldt, &sregs.ldt); | |
1038 | ||
1039 | env->idt.limit = sregs.idt.limit; | |
1040 | env->idt.base = sregs.idt.base; | |
1041 | env->gdt.limit = sregs.gdt.limit; | |
1042 | env->gdt.base = sregs.gdt.base; | |
1043 | ||
1044 | env->cr[0] = sregs.cr0; | |
1045 | env->cr[2] = sregs.cr2; | |
1046 | env->cr[3] = sregs.cr3; | |
1047 | env->cr[4] = sregs.cr4; | |
1048 | ||
4a942cea | 1049 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
1050 | |
1051 | env->efer = sregs.efer; | |
4a942cea | 1052 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 | 1053 | |
b9bec74b JK |
1054 | #define HFLAG_COPY_MASK \ |
1055 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1056 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1057 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1058 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1059 | |
1060 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1061 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1062 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1063 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1064 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1065 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1066 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1067 | |
1068 | if (env->efer & MSR_EFER_LMA) { | |
1069 | hflags |= HF_LMA_MASK; | |
1070 | } | |
1071 | ||
1072 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1073 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1074 | } else { | |
1075 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1076 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1077 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1078 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1079 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1080 | !(hflags & HF_CS32_MASK)) { | |
1081 | hflags |= HF_ADDSEG_MASK; | |
1082 | } else { | |
1083 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1084 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1085 | } | |
05330448 AL |
1086 | } |
1087 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1088 | |
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | static int kvm_get_msrs(CPUState *env) | |
1093 | { | |
1094 | struct { | |
1095 | struct kvm_msrs info; | |
1096 | struct kvm_msr_entry entries[100]; | |
1097 | } msr_data; | |
1098 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1099 | int ret, i, n; | |
1100 | ||
1101 | n = 0; | |
1102 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1103 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1104 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
0c03266a | 1105 | msrs[n++].index = MSR_PAT; |
c3a3a7d3 | 1106 | if (has_msr_star) { |
b9bec74b JK |
1107 | msrs[n++].index = MSR_STAR; |
1108 | } | |
c3a3a7d3 | 1109 | if (has_msr_hsave_pa) { |
75b10c43 | 1110 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1111 | } |
b8cc45d6 GC |
1112 | |
1113 | if (!env->tsc_valid) { | |
1114 | msrs[n++].index = MSR_IA32_TSC; | |
1115 | env->tsc_valid = !vm_running; | |
1116 | } | |
1117 | ||
05330448 | 1118 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1119 | if (lm_capable_kernel) { |
1120 | msrs[n++].index = MSR_CSTAR; | |
1121 | msrs[n++].index = MSR_KERNELGSBASE; | |
1122 | msrs[n++].index = MSR_FMASK; | |
1123 | msrs[n++].index = MSR_LSTAR; | |
1124 | } | |
05330448 | 1125 | #endif |
1a03675d GC |
1126 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1127 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
c5999bfc JK |
1128 | if (has_msr_async_pf_en) { |
1129 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1130 | } | |
1a03675d | 1131 | |
57780495 MT |
1132 | if (env->mcg_cap) { |
1133 | msrs[n++].index = MSR_MCG_STATUS; | |
1134 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1135 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1136 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1137 | } |
57780495 | 1138 | } |
57780495 | 1139 | |
05330448 AL |
1140 | msr_data.info.nmsrs = n; |
1141 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
b9bec74b | 1142 | if (ret < 0) { |
05330448 | 1143 | return ret; |
b9bec74b | 1144 | } |
05330448 AL |
1145 | |
1146 | for (i = 0; i < ret; i++) { | |
1147 | switch (msrs[i].index) { | |
1148 | case MSR_IA32_SYSENTER_CS: | |
1149 | env->sysenter_cs = msrs[i].data; | |
1150 | break; | |
1151 | case MSR_IA32_SYSENTER_ESP: | |
1152 | env->sysenter_esp = msrs[i].data; | |
1153 | break; | |
1154 | case MSR_IA32_SYSENTER_EIP: | |
1155 | env->sysenter_eip = msrs[i].data; | |
1156 | break; | |
0c03266a JK |
1157 | case MSR_PAT: |
1158 | env->pat = msrs[i].data; | |
1159 | break; | |
05330448 AL |
1160 | case MSR_STAR: |
1161 | env->star = msrs[i].data; | |
1162 | break; | |
1163 | #ifdef TARGET_X86_64 | |
1164 | case MSR_CSTAR: | |
1165 | env->cstar = msrs[i].data; | |
1166 | break; | |
1167 | case MSR_KERNELGSBASE: | |
1168 | env->kernelgsbase = msrs[i].data; | |
1169 | break; | |
1170 | case MSR_FMASK: | |
1171 | env->fmask = msrs[i].data; | |
1172 | break; | |
1173 | case MSR_LSTAR: | |
1174 | env->lstar = msrs[i].data; | |
1175 | break; | |
1176 | #endif | |
1177 | case MSR_IA32_TSC: | |
1178 | env->tsc = msrs[i].data; | |
1179 | break; | |
aa851e36 MT |
1180 | case MSR_VM_HSAVE_PA: |
1181 | env->vm_hsave = msrs[i].data; | |
1182 | break; | |
1a03675d GC |
1183 | case MSR_KVM_SYSTEM_TIME: |
1184 | env->system_time_msr = msrs[i].data; | |
1185 | break; | |
1186 | case MSR_KVM_WALL_CLOCK: | |
1187 | env->wall_clock_msr = msrs[i].data; | |
1188 | break; | |
57780495 MT |
1189 | case MSR_MCG_STATUS: |
1190 | env->mcg_status = msrs[i].data; | |
1191 | break; | |
1192 | case MSR_MCG_CTL: | |
1193 | env->mcg_ctl = msrs[i].data; | |
1194 | break; | |
57780495 | 1195 | default: |
57780495 MT |
1196 | if (msrs[i].index >= MSR_MC0_CTL && |
1197 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1198 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 | 1199 | } |
d8da8574 | 1200 | break; |
f6584ee2 GN |
1201 | case MSR_KVM_ASYNC_PF_EN: |
1202 | env->async_pf_en_msr = msrs[i].data; | |
1203 | break; | |
05330448 AL |
1204 | } |
1205 | } | |
1206 | ||
1207 | return 0; | |
1208 | } | |
1209 | ||
9bdbe550 HB |
1210 | static int kvm_put_mp_state(CPUState *env) |
1211 | { | |
1212 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1213 | ||
1214 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1215 | } | |
1216 | ||
1217 | static int kvm_get_mp_state(CPUState *env) | |
1218 | { | |
1219 | struct kvm_mp_state mp_state; | |
1220 | int ret; | |
1221 | ||
1222 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1223 | if (ret < 0) { | |
1224 | return ret; | |
1225 | } | |
1226 | env->mp_state = mp_state.mp_state; | |
c14750e8 JK |
1227 | if (kvm_irqchip_in_kernel()) { |
1228 | env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
1229 | } | |
9bdbe550 HB |
1230 | return 0; |
1231 | } | |
1232 | ||
ea643051 | 1233 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c | 1234 | { |
a0fb002c JK |
1235 | struct kvm_vcpu_events events; |
1236 | ||
1237 | if (!kvm_has_vcpu_events()) { | |
1238 | return 0; | |
1239 | } | |
1240 | ||
31827373 JK |
1241 | events.exception.injected = (env->exception_injected >= 0); |
1242 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1243 | events.exception.has_error_code = env->has_error_code; |
1244 | events.exception.error_code = env->error_code; | |
1245 | ||
1246 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1247 | events.interrupt.nr = env->interrupt_injected; | |
1248 | events.interrupt.soft = env->soft_interrupt; | |
1249 | ||
1250 | events.nmi.injected = env->nmi_injected; | |
1251 | events.nmi.pending = env->nmi_pending; | |
1252 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1253 | ||
1254 | events.sipi_vector = env->sipi_vector; | |
1255 | ||
ea643051 JK |
1256 | events.flags = 0; |
1257 | if (level >= KVM_PUT_RESET_STATE) { | |
1258 | events.flags |= | |
1259 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1260 | } | |
aee028b9 | 1261 | |
a0fb002c | 1262 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
a0fb002c JK |
1263 | } |
1264 | ||
1265 | static int kvm_get_vcpu_events(CPUState *env) | |
1266 | { | |
a0fb002c JK |
1267 | struct kvm_vcpu_events events; |
1268 | int ret; | |
1269 | ||
1270 | if (!kvm_has_vcpu_events()) { | |
1271 | return 0; | |
1272 | } | |
1273 | ||
1274 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1275 | if (ret < 0) { | |
1276 | return ret; | |
1277 | } | |
31827373 | 1278 | env->exception_injected = |
a0fb002c JK |
1279 | events.exception.injected ? events.exception.nr : -1; |
1280 | env->has_error_code = events.exception.has_error_code; | |
1281 | env->error_code = events.exception.error_code; | |
1282 | ||
1283 | env->interrupt_injected = | |
1284 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1285 | env->soft_interrupt = events.interrupt.soft; | |
1286 | ||
1287 | env->nmi_injected = events.nmi.injected; | |
1288 | env->nmi_pending = events.nmi.pending; | |
1289 | if (events.nmi.masked) { | |
1290 | env->hflags2 |= HF2_NMI_MASK; | |
1291 | } else { | |
1292 | env->hflags2 &= ~HF2_NMI_MASK; | |
1293 | } | |
1294 | ||
1295 | env->sipi_vector = events.sipi_vector; | |
a0fb002c JK |
1296 | |
1297 | return 0; | |
1298 | } | |
1299 | ||
b0b1d690 JK |
1300 | static int kvm_guest_debug_workarounds(CPUState *env) |
1301 | { | |
1302 | int ret = 0; | |
b0b1d690 JK |
1303 | unsigned long reinject_trap = 0; |
1304 | ||
1305 | if (!kvm_has_vcpu_events()) { | |
1306 | if (env->exception_injected == 1) { | |
1307 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1308 | } else if (env->exception_injected == 3) { | |
1309 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1310 | } | |
1311 | env->exception_injected = -1; | |
1312 | } | |
1313 | ||
1314 | /* | |
1315 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1316 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1317 | * by updating the debug state once again if single-stepping is on. | |
1318 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1319 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1320 | * reinject them via SET_GUEST_DEBUG. | |
1321 | */ | |
1322 | if (reinject_trap || | |
1323 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1324 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1325 | } | |
b0b1d690 JK |
1326 | return ret; |
1327 | } | |
1328 | ||
ff44f1a3 JK |
1329 | static int kvm_put_debugregs(CPUState *env) |
1330 | { | |
ff44f1a3 JK |
1331 | struct kvm_debugregs dbgregs; |
1332 | int i; | |
1333 | ||
1334 | if (!kvm_has_debugregs()) { | |
1335 | return 0; | |
1336 | } | |
1337 | ||
1338 | for (i = 0; i < 4; i++) { | |
1339 | dbgregs.db[i] = env->dr[i]; | |
1340 | } | |
1341 | dbgregs.dr6 = env->dr[6]; | |
1342 | dbgregs.dr7 = env->dr[7]; | |
1343 | dbgregs.flags = 0; | |
1344 | ||
1345 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
ff44f1a3 JK |
1346 | } |
1347 | ||
1348 | static int kvm_get_debugregs(CPUState *env) | |
1349 | { | |
ff44f1a3 JK |
1350 | struct kvm_debugregs dbgregs; |
1351 | int i, ret; | |
1352 | ||
1353 | if (!kvm_has_debugregs()) { | |
1354 | return 0; | |
1355 | } | |
1356 | ||
1357 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1358 | if (ret < 0) { | |
b9bec74b | 1359 | return ret; |
ff44f1a3 JK |
1360 | } |
1361 | for (i = 0; i < 4; i++) { | |
1362 | env->dr[i] = dbgregs.db[i]; | |
1363 | } | |
1364 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1365 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
ff44f1a3 JK |
1366 | |
1367 | return 0; | |
1368 | } | |
1369 | ||
ea375f9a | 1370 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1371 | { |
1372 | int ret; | |
1373 | ||
b7680cb6 | 1374 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1375 | |
05330448 | 1376 | ret = kvm_getput_regs(env, 1); |
b9bec74b | 1377 | if (ret < 0) { |
05330448 | 1378 | return ret; |
b9bec74b | 1379 | } |
f1665b21 | 1380 | ret = kvm_put_xsave(env); |
b9bec74b | 1381 | if (ret < 0) { |
f1665b21 | 1382 | return ret; |
b9bec74b | 1383 | } |
f1665b21 | 1384 | ret = kvm_put_xcrs(env); |
b9bec74b | 1385 | if (ret < 0) { |
05330448 | 1386 | return ret; |
b9bec74b | 1387 | } |
05330448 | 1388 | ret = kvm_put_sregs(env); |
b9bec74b | 1389 | if (ret < 0) { |
05330448 | 1390 | return ret; |
b9bec74b | 1391 | } |
ab443475 JK |
1392 | /* must be before kvm_put_msrs */ |
1393 | ret = kvm_inject_mce_oldstyle(env); | |
1394 | if (ret < 0) { | |
1395 | return ret; | |
1396 | } | |
ea643051 | 1397 | ret = kvm_put_msrs(env, level); |
b9bec74b | 1398 | if (ret < 0) { |
05330448 | 1399 | return ret; |
b9bec74b | 1400 | } |
ea643051 JK |
1401 | if (level >= KVM_PUT_RESET_STATE) { |
1402 | ret = kvm_put_mp_state(env); | |
b9bec74b | 1403 | if (ret < 0) { |
ea643051 | 1404 | return ret; |
b9bec74b | 1405 | } |
ea643051 | 1406 | } |
ea643051 | 1407 | ret = kvm_put_vcpu_events(env, level); |
b9bec74b | 1408 | if (ret < 0) { |
a0fb002c | 1409 | return ret; |
b9bec74b | 1410 | } |
0d75a9ec | 1411 | ret = kvm_put_debugregs(env); |
b9bec74b | 1412 | if (ret < 0) { |
b0b1d690 | 1413 | return ret; |
b9bec74b | 1414 | } |
b0b1d690 JK |
1415 | /* must be last */ |
1416 | ret = kvm_guest_debug_workarounds(env); | |
b9bec74b | 1417 | if (ret < 0) { |
ff44f1a3 | 1418 | return ret; |
b9bec74b | 1419 | } |
05330448 AL |
1420 | return 0; |
1421 | } | |
1422 | ||
1423 | int kvm_arch_get_registers(CPUState *env) | |
1424 | { | |
1425 | int ret; | |
1426 | ||
b7680cb6 | 1427 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1428 | |
05330448 | 1429 | ret = kvm_getput_regs(env, 0); |
b9bec74b | 1430 | if (ret < 0) { |
05330448 | 1431 | return ret; |
b9bec74b | 1432 | } |
f1665b21 | 1433 | ret = kvm_get_xsave(env); |
b9bec74b | 1434 | if (ret < 0) { |
f1665b21 | 1435 | return ret; |
b9bec74b | 1436 | } |
f1665b21 | 1437 | ret = kvm_get_xcrs(env); |
b9bec74b | 1438 | if (ret < 0) { |
05330448 | 1439 | return ret; |
b9bec74b | 1440 | } |
05330448 | 1441 | ret = kvm_get_sregs(env); |
b9bec74b | 1442 | if (ret < 0) { |
05330448 | 1443 | return ret; |
b9bec74b | 1444 | } |
05330448 | 1445 | ret = kvm_get_msrs(env); |
b9bec74b | 1446 | if (ret < 0) { |
05330448 | 1447 | return ret; |
b9bec74b | 1448 | } |
5a2e3c2e | 1449 | ret = kvm_get_mp_state(env); |
b9bec74b | 1450 | if (ret < 0) { |
5a2e3c2e | 1451 | return ret; |
b9bec74b | 1452 | } |
a0fb002c | 1453 | ret = kvm_get_vcpu_events(env); |
b9bec74b | 1454 | if (ret < 0) { |
a0fb002c | 1455 | return ret; |
b9bec74b | 1456 | } |
ff44f1a3 | 1457 | ret = kvm_get_debugregs(env); |
b9bec74b | 1458 | if (ret < 0) { |
ff44f1a3 | 1459 | return ret; |
b9bec74b | 1460 | } |
05330448 AL |
1461 | return 0; |
1462 | } | |
1463 | ||
7a39fe58 | 1464 | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
05330448 | 1465 | { |
ce377af3 JK |
1466 | int ret; |
1467 | ||
276ce815 LJ |
1468 | /* Inject NMI */ |
1469 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1470 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1471 | DPRINTF("injected NMI\n"); | |
ce377af3 JK |
1472 | ret = kvm_vcpu_ioctl(env, KVM_NMI); |
1473 | if (ret < 0) { | |
1474 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
1475 | strerror(-ret)); | |
1476 | } | |
276ce815 LJ |
1477 | } |
1478 | ||
db1669bc JK |
1479 | if (!kvm_irqchip_in_kernel()) { |
1480 | /* Force the VCPU out of its inner loop to process the INIT request */ | |
1481 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1482 | env->exit_request = 1; | |
05330448 | 1483 | } |
05330448 | 1484 | |
db1669bc JK |
1485 | /* Try to inject an interrupt if the guest can accept it */ |
1486 | if (run->ready_for_interrupt_injection && | |
1487 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1488 | (env->eflags & IF_MASK)) { | |
1489 | int irq; | |
1490 | ||
1491 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1492 | irq = cpu_get_pic_interrupt(env); | |
1493 | if (irq >= 0) { | |
1494 | struct kvm_interrupt intr; | |
1495 | ||
1496 | intr.irq = irq; | |
db1669bc | 1497 | DPRINTF("injected interrupt %d\n", irq); |
ce377af3 JK |
1498 | ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1499 | if (ret < 0) { | |
1500 | fprintf(stderr, | |
1501 | "KVM: injection failed, interrupt lost (%s)\n", | |
1502 | strerror(-ret)); | |
1503 | } | |
db1669bc JK |
1504 | } |
1505 | } | |
05330448 | 1506 | |
db1669bc JK |
1507 | /* If we have an interrupt but the guest is not ready to receive an |
1508 | * interrupt, request an interrupt window exit. This will | |
1509 | * cause a return to userspace as soon as the guest is ready to | |
1510 | * receive interrupts. */ | |
1511 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { | |
1512 | run->request_interrupt_window = 1; | |
1513 | } else { | |
1514 | run->request_interrupt_window = 0; | |
1515 | } | |
1516 | ||
1517 | DPRINTF("setting tpr\n"); | |
1518 | run->cr8 = cpu_get_apic_tpr(env->apic_state); | |
1519 | } | |
05330448 AL |
1520 | } |
1521 | ||
7a39fe58 | 1522 | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
05330448 | 1523 | { |
b9bec74b | 1524 | if (run->if_flag) { |
05330448 | 1525 | env->eflags |= IF_MASK; |
b9bec74b | 1526 | } else { |
05330448 | 1527 | env->eflags &= ~IF_MASK; |
b9bec74b | 1528 | } |
4a942cea BS |
1529 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1530 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1531 | } |
1532 | ||
99036865 | 1533 | int kvm_arch_process_async_events(CPUState *env) |
0af691d7 | 1534 | { |
ab443475 JK |
1535 | if (env->interrupt_request & CPU_INTERRUPT_MCE) { |
1536 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ | |
1537 | assert(env->mcg_cap); | |
1538 | ||
1539 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
1540 | ||
1541 | kvm_cpu_synchronize_state(env); | |
1542 | ||
1543 | if (env->exception_injected == EXCP08_DBLE) { | |
1544 | /* this means triple fault */ | |
1545 | qemu_system_reset_request(); | |
1546 | env->exit_request = 1; | |
1547 | return 0; | |
1548 | } | |
1549 | env->exception_injected = EXCP12_MCHK; | |
1550 | env->has_error_code = 0; | |
1551 | ||
1552 | env->halted = 0; | |
1553 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { | |
1554 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
1555 | } | |
1556 | } | |
1557 | ||
db1669bc JK |
1558 | if (kvm_irqchip_in_kernel()) { |
1559 | return 0; | |
1560 | } | |
1561 | ||
4601f7b0 JK |
1562 | if (((env->interrupt_request & CPU_INTERRUPT_HARD) && |
1563 | (env->eflags & IF_MASK)) || | |
1564 | (env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
6792a57b JK |
1565 | env->halted = 0; |
1566 | } | |
0af691d7 MT |
1567 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { |
1568 | kvm_cpu_synchronize_state(env); | |
1569 | do_cpu_init(env); | |
0af691d7 | 1570 | } |
0af691d7 MT |
1571 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { |
1572 | kvm_cpu_synchronize_state(env); | |
1573 | do_cpu_sipi(env); | |
1574 | } | |
1575 | ||
1576 | return env->halted; | |
1577 | } | |
1578 | ||
05330448 AL |
1579 | static int kvm_handle_halt(CPUState *env) |
1580 | { | |
1581 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1582 | (env->eflags & IF_MASK)) && | |
1583 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1584 | env->halted = 1; | |
bb4ea393 | 1585 | return EXCP_HLT; |
05330448 AL |
1586 | } |
1587 | ||
bb4ea393 | 1588 | return 0; |
05330448 AL |
1589 | } |
1590 | ||
e22a25c9 AL |
1591 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1592 | { | |
38972938 | 1593 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1594 | |
e22a25c9 | 1595 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
b9bec74b | 1596 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
e22a25c9 | 1597 | return -EINVAL; |
b9bec74b | 1598 | } |
e22a25c9 AL |
1599 | return 0; |
1600 | } | |
1601 | ||
1602 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1603 | { | |
1604 | uint8_t int3; | |
1605 | ||
1606 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
b9bec74b | 1607 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
e22a25c9 | 1608 | return -EINVAL; |
b9bec74b | 1609 | } |
e22a25c9 AL |
1610 | return 0; |
1611 | } | |
1612 | ||
1613 | static struct { | |
1614 | target_ulong addr; | |
1615 | int len; | |
1616 | int type; | |
1617 | } hw_breakpoint[4]; | |
1618 | ||
1619 | static int nb_hw_breakpoint; | |
1620 | ||
1621 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1622 | { | |
1623 | int n; | |
1624 | ||
b9bec74b | 1625 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1626 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1627 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1628 | return n; |
b9bec74b JK |
1629 | } |
1630 | } | |
e22a25c9 AL |
1631 | return -1; |
1632 | } | |
1633 | ||
1634 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1635 | target_ulong len, int type) | |
1636 | { | |
1637 | switch (type) { | |
1638 | case GDB_BREAKPOINT_HW: | |
1639 | len = 1; | |
1640 | break; | |
1641 | case GDB_WATCHPOINT_WRITE: | |
1642 | case GDB_WATCHPOINT_ACCESS: | |
1643 | switch (len) { | |
1644 | case 1: | |
1645 | break; | |
1646 | case 2: | |
1647 | case 4: | |
1648 | case 8: | |
b9bec74b | 1649 | if (addr & (len - 1)) { |
e22a25c9 | 1650 | return -EINVAL; |
b9bec74b | 1651 | } |
e22a25c9 AL |
1652 | break; |
1653 | default: | |
1654 | return -EINVAL; | |
1655 | } | |
1656 | break; | |
1657 | default: | |
1658 | return -ENOSYS; | |
1659 | } | |
1660 | ||
b9bec74b | 1661 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 1662 | return -ENOBUFS; |
b9bec74b JK |
1663 | } |
1664 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 1665 | return -EEXIST; |
b9bec74b | 1666 | } |
e22a25c9 AL |
1667 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1668 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1669 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1670 | nb_hw_breakpoint++; | |
1671 | ||
1672 | return 0; | |
1673 | } | |
1674 | ||
1675 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1676 | target_ulong len, int type) | |
1677 | { | |
1678 | int n; | |
1679 | ||
1680 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 1681 | if (n < 0) { |
e22a25c9 | 1682 | return -ENOENT; |
b9bec74b | 1683 | } |
e22a25c9 AL |
1684 | nb_hw_breakpoint--; |
1685 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1686 | ||
1687 | return 0; | |
1688 | } | |
1689 | ||
1690 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1691 | { | |
1692 | nb_hw_breakpoint = 0; | |
1693 | } | |
1694 | ||
1695 | static CPUWatchpoint hw_watchpoint; | |
1696 | ||
f2574737 | 1697 | static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) |
e22a25c9 | 1698 | { |
f2574737 | 1699 | int ret = 0; |
e22a25c9 AL |
1700 | int n; |
1701 | ||
1702 | if (arch_info->exception == 1) { | |
1703 | if (arch_info->dr6 & (1 << 14)) { | |
b9bec74b | 1704 | if (cpu_single_env->singlestep_enabled) { |
f2574737 | 1705 | ret = EXCP_DEBUG; |
b9bec74b | 1706 | } |
e22a25c9 | 1707 | } else { |
b9bec74b JK |
1708 | for (n = 0; n < 4; n++) { |
1709 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
1710 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1711 | case 0x0: | |
f2574737 | 1712 | ret = EXCP_DEBUG; |
e22a25c9 AL |
1713 | break; |
1714 | case 0x1: | |
f2574737 | 1715 | ret = EXCP_DEBUG; |
e22a25c9 AL |
1716 | cpu_single_env->watchpoint_hit = &hw_watchpoint; |
1717 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1718 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1719 | break; | |
1720 | case 0x3: | |
f2574737 | 1721 | ret = EXCP_DEBUG; |
e22a25c9 AL |
1722 | cpu_single_env->watchpoint_hit = &hw_watchpoint; |
1723 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1724 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1725 | break; | |
1726 | } | |
b9bec74b JK |
1727 | } |
1728 | } | |
e22a25c9 | 1729 | } |
b9bec74b | 1730 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
f2574737 | 1731 | ret = EXCP_DEBUG; |
b9bec74b | 1732 | } |
f2574737 | 1733 | if (ret == 0) { |
b0b1d690 JK |
1734 | cpu_synchronize_state(cpu_single_env); |
1735 | assert(cpu_single_env->exception_injected == -1); | |
1736 | ||
f2574737 | 1737 | /* pass to guest */ |
b0b1d690 JK |
1738 | cpu_single_env->exception_injected = arch_info->exception; |
1739 | cpu_single_env->has_error_code = 0; | |
1740 | } | |
e22a25c9 | 1741 | |
f2574737 | 1742 | return ret; |
e22a25c9 AL |
1743 | } |
1744 | ||
1745 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1746 | { | |
1747 | const uint8_t type_code[] = { | |
1748 | [GDB_BREAKPOINT_HW] = 0x0, | |
1749 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1750 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1751 | }; | |
1752 | const uint8_t len_code[] = { | |
1753 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1754 | }; | |
1755 | int n; | |
1756 | ||
b9bec74b | 1757 | if (kvm_sw_breakpoints_active(env)) { |
e22a25c9 | 1758 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 1759 | } |
e22a25c9 AL |
1760 | if (nb_hw_breakpoint > 0) { |
1761 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1762 | dbg->arch.debugreg[7] = 0x0600; | |
1763 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1764 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1765 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1766 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 1767 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
1768 | } |
1769 | } | |
1770 | } | |
4513d923 | 1771 | |
2a4dac83 JK |
1772 | static bool host_supports_vmx(void) |
1773 | { | |
1774 | uint32_t ecx, unused; | |
1775 | ||
1776 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
1777 | return ecx & CPUID_EXT_VMX; | |
1778 | } | |
1779 | ||
1780 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
1781 | ||
1782 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
1783 | { | |
1784 | uint64_t code; | |
1785 | int ret; | |
1786 | ||
1787 | switch (run->exit_reason) { | |
1788 | case KVM_EXIT_HLT: | |
1789 | DPRINTF("handle_hlt\n"); | |
1790 | ret = kvm_handle_halt(env); | |
1791 | break; | |
1792 | case KVM_EXIT_SET_TPR: | |
1793 | ret = 0; | |
1794 | break; | |
1795 | case KVM_EXIT_FAIL_ENTRY: | |
1796 | code = run->fail_entry.hardware_entry_failure_reason; | |
1797 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
1798 | code); | |
1799 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
1800 | fprintf(stderr, | |
1801 | "\nIf you're runnning a guest on an Intel machine without " | |
1802 | "unrestricted mode\n" | |
1803 | "support, the failure can be most likely due to the guest " | |
1804 | "entering an invalid\n" | |
1805 | "state for Intel VT. For example, the guest maybe running " | |
1806 | "in big real mode\n" | |
1807 | "which is not supported on less recent Intel processors." | |
1808 | "\n\n"); | |
1809 | } | |
1810 | ret = -1; | |
1811 | break; | |
1812 | case KVM_EXIT_EXCEPTION: | |
1813 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
1814 | run->ex.exception, run->ex.error_code); | |
1815 | ret = -1; | |
1816 | break; | |
f2574737 JK |
1817 | case KVM_EXIT_DEBUG: |
1818 | DPRINTF("kvm_exit_debug\n"); | |
1819 | ret = kvm_handle_debug(&run->debug.arch); | |
1820 | break; | |
2a4dac83 JK |
1821 | default: |
1822 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
1823 | ret = -1; | |
1824 | break; | |
1825 | } | |
1826 | ||
1827 | return ret; | |
1828 | } | |
1829 | ||
4513d923 GN |
1830 | bool kvm_arch_stop_on_emulation_error(CPUState *env) |
1831 | { | |
b9bec74b JK |
1832 | return !(env->cr[0] & CR0_PE_MASK) || |
1833 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 1834 | } |