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Commit | Line | Data |
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8dd3dca3 AJ |
1 | #include "hw/hw.h" |
2 | #include "hw/boards.h" | |
0d09e41a PB |
3 | #include "hw/i386/pc.h" |
4 | #include "hw/isa/isa.h" | |
8dd3dca3 | 5 | |
2b41f10e | 6 | #include "cpu.h" |
9c17d615 | 7 | #include "sysemu/kvm.h" |
8dd3dca3 | 8 | |
66e6d55b JQ |
9 | static const VMStateDescription vmstate_segment = { |
10 | .name = "segment", | |
11 | .version_id = 1, | |
12 | .minimum_version_id = 1, | |
13 | .minimum_version_id_old = 1, | |
14 | .fields = (VMStateField []) { | |
15 | VMSTATE_UINT32(selector, SegmentCache), | |
16 | VMSTATE_UINTTL(base, SegmentCache), | |
17 | VMSTATE_UINT32(limit, SegmentCache), | |
18 | VMSTATE_UINT32(flags, SegmentCache), | |
19 | VMSTATE_END_OF_LIST() | |
20 | } | |
21 | }; | |
22 | ||
0cb892aa JQ |
23 | #define VMSTATE_SEGMENT(_field, _state) { \ |
24 | .name = (stringify(_field)), \ | |
25 | .size = sizeof(SegmentCache), \ | |
26 | .vmsd = &vmstate_segment, \ | |
27 | .flags = VMS_STRUCT, \ | |
28 | .offset = offsetof(_state, _field) \ | |
29 | + type_check(SegmentCache,typeof_field(_state, _field)) \ | |
8dd3dca3 AJ |
30 | } |
31 | ||
0cb892aa JQ |
32 | #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \ |
33 | VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache) | |
8dd3dca3 | 34 | |
fc3b0aa2 JQ |
35 | static const VMStateDescription vmstate_xmm_reg = { |
36 | .name = "xmm_reg", | |
37 | .version_id = 1, | |
38 | .minimum_version_id = 1, | |
39 | .minimum_version_id_old = 1, | |
40 | .fields = (VMStateField []) { | |
41 | VMSTATE_UINT64(XMM_Q(0), XMMReg), | |
42 | VMSTATE_UINT64(XMM_Q(1), XMMReg), | |
43 | VMSTATE_END_OF_LIST() | |
44 | } | |
45 | }; | |
46 | ||
0cb892aa JQ |
47 | #define VMSTATE_XMM_REGS(_field, _state, _n) \ |
48 | VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg) | |
fc3b0aa2 | 49 | |
f1665b21 SY |
50 | /* YMMH format is the same as XMM */ |
51 | static const VMStateDescription vmstate_ymmh_reg = { | |
52 | .name = "ymmh_reg", | |
53 | .version_id = 1, | |
54 | .minimum_version_id = 1, | |
55 | .minimum_version_id_old = 1, | |
56 | .fields = (VMStateField []) { | |
57 | VMSTATE_UINT64(XMM_Q(0), XMMReg), | |
58 | VMSTATE_UINT64(XMM_Q(1), XMMReg), | |
59 | VMSTATE_END_OF_LIST() | |
60 | } | |
61 | }; | |
62 | ||
63 | #define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v) \ | |
64 | VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg) | |
65 | ||
216c07c3 JQ |
66 | static const VMStateDescription vmstate_mtrr_var = { |
67 | .name = "mtrr_var", | |
68 | .version_id = 1, | |
69 | .minimum_version_id = 1, | |
70 | .minimum_version_id_old = 1, | |
71 | .fields = (VMStateField []) { | |
72 | VMSTATE_UINT64(base, MTRRVar), | |
73 | VMSTATE_UINT64(mask, MTRRVar), | |
74 | VMSTATE_END_OF_LIST() | |
75 | } | |
76 | }; | |
77 | ||
0cb892aa JQ |
78 | #define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \ |
79 | VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar) | |
216c07c3 | 80 | |
0cb892aa | 81 | static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size) |
216c07c3 | 82 | { |
0cb892aa JQ |
83 | fprintf(stderr, "call put_fpreg() with invalid arguments\n"); |
84 | exit(0); | |
216c07c3 JQ |
85 | } |
86 | ||
3c8ce630 JQ |
87 | /* XXX: add that in a FPU generic layer */ |
88 | union x86_longdouble { | |
89 | uint64_t mant; | |
90 | uint16_t exp; | |
91 | }; | |
92 | ||
93 | #define MANTD1(fp) (fp & ((1LL << 52) - 1)) | |
94 | #define EXPBIAS1 1023 | |
95 | #define EXPD1(fp) ((fp >> 52) & 0x7FF) | |
96 | #define SIGND1(fp) ((fp >> 32) & 0x80000000) | |
97 | ||
98 | static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp) | |
99 | { | |
100 | int e; | |
101 | /* mantissa */ | |
102 | p->mant = (MANTD1(temp) << 11) | (1LL << 63); | |
103 | /* exponent + sign */ | |
104 | e = EXPD1(temp) - EXPBIAS1 + 16383; | |
105 | e |= SIGND1(temp) >> 16; | |
106 | p->exp = e; | |
107 | } | |
108 | ||
109 | static int get_fpreg(QEMUFile *f, void *opaque, size_t size) | |
110 | { | |
111 | FPReg *fp_reg = opaque; | |
112 | uint64_t mant; | |
113 | uint16_t exp; | |
114 | ||
115 | qemu_get_be64s(f, &mant); | |
116 | qemu_get_be16s(f, &exp); | |
117 | fp_reg->d = cpu_set_fp80(mant, exp); | |
118 | return 0; | |
119 | } | |
120 | ||
121 | static void put_fpreg(QEMUFile *f, void *opaque, size_t size) | |
122 | { | |
123 | FPReg *fp_reg = opaque; | |
124 | uint64_t mant; | |
125 | uint16_t exp; | |
126 | /* we save the real CPU data (in case of MMX usage only 'mant' | |
127 | contains the MMX register */ | |
128 | cpu_get_fp80(&mant, &exp, fp_reg->d); | |
129 | qemu_put_be64s(f, &mant); | |
130 | qemu_put_be16s(f, &exp); | |
131 | } | |
132 | ||
976b2037 | 133 | static const VMStateInfo vmstate_fpreg = { |
0cb892aa JQ |
134 | .name = "fpreg", |
135 | .get = get_fpreg, | |
136 | .put = put_fpreg, | |
137 | }; | |
138 | ||
3c8ce630 JQ |
139 | static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size) |
140 | { | |
141 | union x86_longdouble *p = opaque; | |
142 | uint64_t mant; | |
143 | ||
144 | qemu_get_be64s(f, &mant); | |
145 | p->mant = mant; | |
146 | p->exp = 0xffff; | |
147 | return 0; | |
148 | } | |
149 | ||
976b2037 | 150 | static const VMStateInfo vmstate_fpreg_1_mmx = { |
0cb892aa JQ |
151 | .name = "fpreg_1_mmx", |
152 | .get = get_fpreg_1_mmx, | |
153 | .put = put_fpreg_error, | |
154 | }; | |
155 | ||
3c8ce630 JQ |
156 | static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size) |
157 | { | |
158 | union x86_longdouble *p = opaque; | |
159 | uint64_t mant; | |
160 | ||
161 | qemu_get_be64s(f, &mant); | |
162 | fp64_to_fp80(p, mant); | |
163 | return 0; | |
164 | } | |
165 | ||
976b2037 | 166 | static const VMStateInfo vmstate_fpreg_1_no_mmx = { |
0cb892aa JQ |
167 | .name = "fpreg_1_no_mmx", |
168 | .get = get_fpreg_1_no_mmx, | |
169 | .put = put_fpreg_error, | |
170 | }; | |
171 | ||
172 | static bool fpregs_is_0(void *opaque, int version_id) | |
173 | { | |
f56e3a14 AF |
174 | X86CPU *cpu = opaque; |
175 | CPUX86State *env = &cpu->env; | |
0cb892aa JQ |
176 | |
177 | return (env->fpregs_format_vmstate == 0); | |
178 | } | |
179 | ||
180 | static bool fpregs_is_1_mmx(void *opaque, int version_id) | |
181 | { | |
f56e3a14 AF |
182 | X86CPU *cpu = opaque; |
183 | CPUX86State *env = &cpu->env; | |
0cb892aa JQ |
184 | int guess_mmx; |
185 | ||
186 | guess_mmx = ((env->fptag_vmstate == 0xff) && | |
187 | (env->fpus_vmstate & 0x3800) == 0); | |
188 | return (guess_mmx && (env->fpregs_format_vmstate == 1)); | |
189 | } | |
190 | ||
191 | static bool fpregs_is_1_no_mmx(void *opaque, int version_id) | |
192 | { | |
f56e3a14 AF |
193 | X86CPU *cpu = opaque; |
194 | CPUX86State *env = &cpu->env; | |
0cb892aa JQ |
195 | int guess_mmx; |
196 | ||
197 | guess_mmx = ((env->fptag_vmstate == 0xff) && | |
198 | (env->fpus_vmstate & 0x3800) == 0); | |
199 | return (!guess_mmx && (env->fpregs_format_vmstate == 1)); | |
200 | } | |
201 | ||
202 | #define VMSTATE_FP_REGS(_field, _state, _n) \ | |
203 | VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \ | |
204 | VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \ | |
205 | VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg) | |
206 | ||
0cb892aa JQ |
207 | static bool version_is_5(void *opaque, int version_id) |
208 | { | |
209 | return version_id == 5; | |
210 | } | |
211 | ||
212 | #ifdef TARGET_X86_64 | |
213 | static bool less_than_7(void *opaque, int version_id) | |
214 | { | |
215 | return version_id < 7; | |
216 | } | |
217 | ||
218 | static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size) | |
219 | { | |
220 | uint64_t *v = pv; | |
221 | *v = qemu_get_be32(f); | |
222 | return 0; | |
223 | } | |
224 | ||
225 | static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size) | |
226 | { | |
227 | uint64_t *v = pv; | |
228 | qemu_put_be32(f, *v); | |
229 | } | |
230 | ||
976b2037 | 231 | static const VMStateInfo vmstate_hack_uint64_as_uint32 = { |
0cb892aa JQ |
232 | .name = "uint64_as_uint32", |
233 | .get = get_uint64_as_uint32, | |
234 | .put = put_uint64_as_uint32, | |
235 | }; | |
236 | ||
237 | #define VMSTATE_HACK_UINT32(_f, _s, _t) \ | |
d4829d49 | 238 | VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t) |
0cb892aa JQ |
239 | #endif |
240 | ||
c4c38c8c | 241 | static void cpu_pre_save(void *opaque) |
8dd3dca3 | 242 | { |
f56e3a14 AF |
243 | X86CPU *cpu = opaque; |
244 | CPUX86State *env = &cpu->env; | |
0e607a80 | 245 | int i; |
8dd3dca3 | 246 | |
8dd3dca3 | 247 | /* FPU */ |
67b8f419 | 248 | env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
cdc0c58f | 249 | env->fptag_vmstate = 0; |
8dd3dca3 | 250 | for(i = 0; i < 8; i++) { |
cdc0c58f | 251 | env->fptag_vmstate |= ((!env->fptags[i]) << i); |
8dd3dca3 AJ |
252 | } |
253 | ||
60a902f1 | 254 | env->fpregs_format_vmstate = 0; |
c4c38c8c JQ |
255 | } |
256 | ||
468f6581 JQ |
257 | static int cpu_post_load(void *opaque, int version_id) |
258 | { | |
f56e3a14 AF |
259 | X86CPU *cpu = opaque; |
260 | CPUX86State *env = &cpu->env; | |
468f6581 JQ |
261 | int i; |
262 | ||
263 | /* XXX: restore FPU round state */ | |
264 | env->fpstt = (env->fpus_vmstate >> 11) & 7; | |
265 | env->fpus = env->fpus_vmstate & ~0x3800; | |
266 | env->fptag_vmstate ^= 0xff; | |
267 | for(i = 0; i < 8; i++) { | |
268 | env->fptags[i] = (env->fptag_vmstate >> i) & 1; | |
269 | } | |
270 | ||
271 | cpu_breakpoint_remove_all(env, BP_CPU); | |
272 | cpu_watchpoint_remove_all(env, BP_CPU); | |
428065ce | 273 | for (i = 0; i < DR7_MAX_BP; i++) { |
468f6581 | 274 | hw_breakpoint_insert(env, i); |
428065ce | 275 | } |
1e7fbc6d | 276 | tlb_flush(env, 1); |
428065ce | 277 | |
1e7fbc6d | 278 | return 0; |
468f6581 JQ |
279 | } |
280 | ||
f6584ee2 GN |
281 | static bool async_pf_msr_needed(void *opaque) |
282 | { | |
f56e3a14 | 283 | X86CPU *cpu = opaque; |
f6584ee2 | 284 | |
f56e3a14 | 285 | return cpu->env.async_pf_en_msr != 0; |
f6584ee2 GN |
286 | } |
287 | ||
bc9a839d MT |
288 | static bool pv_eoi_msr_needed(void *opaque) |
289 | { | |
f56e3a14 | 290 | X86CPU *cpu = opaque; |
bc9a839d | 291 | |
f56e3a14 | 292 | return cpu->env.pv_eoi_en_msr != 0; |
bc9a839d MT |
293 | } |
294 | ||
917367aa MT |
295 | static bool steal_time_msr_needed(void *opaque) |
296 | { | |
297 | CPUX86State *cpu = opaque; | |
298 | ||
299 | return cpu->steal_time_msr != 0; | |
300 | } | |
301 | ||
302 | static const VMStateDescription vmstate_steal_time_msr = { | |
303 | .name = "cpu/steal_time_msr", | |
304 | .version_id = 1, | |
305 | .minimum_version_id = 1, | |
306 | .minimum_version_id_old = 1, | |
307 | .fields = (VMStateField []) { | |
308 | VMSTATE_UINT64(steal_time_msr, CPUX86State), | |
309 | VMSTATE_END_OF_LIST() | |
310 | } | |
311 | }; | |
312 | ||
f6584ee2 GN |
313 | static const VMStateDescription vmstate_async_pf_msr = { |
314 | .name = "cpu/async_pf_msr", | |
315 | .version_id = 1, | |
316 | .minimum_version_id = 1, | |
317 | .minimum_version_id_old = 1, | |
318 | .fields = (VMStateField []) { | |
f56e3a14 | 319 | VMSTATE_UINT64(env.async_pf_en_msr, X86CPU), |
f6584ee2 GN |
320 | VMSTATE_END_OF_LIST() |
321 | } | |
322 | }; | |
323 | ||
bc9a839d MT |
324 | static const VMStateDescription vmstate_pv_eoi_msr = { |
325 | .name = "cpu/async_pv_eoi_msr", | |
326 | .version_id = 1, | |
327 | .minimum_version_id = 1, | |
328 | .minimum_version_id_old = 1, | |
329 | .fields = (VMStateField []) { | |
f56e3a14 | 330 | VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU), |
bc9a839d MT |
331 | VMSTATE_END_OF_LIST() |
332 | } | |
333 | }; | |
334 | ||
42cc8fa6 JK |
335 | static bool fpop_ip_dp_needed(void *opaque) |
336 | { | |
f56e3a14 AF |
337 | X86CPU *cpu = opaque; |
338 | CPUX86State *env = &cpu->env; | |
42cc8fa6 JK |
339 | |
340 | return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0; | |
341 | } | |
342 | ||
343 | static const VMStateDescription vmstate_fpop_ip_dp = { | |
344 | .name = "cpu/fpop_ip_dp", | |
345 | .version_id = 1, | |
346 | .minimum_version_id = 1, | |
347 | .minimum_version_id_old = 1, | |
348 | .fields = (VMStateField []) { | |
f56e3a14 AF |
349 | VMSTATE_UINT16(env.fpop, X86CPU), |
350 | VMSTATE_UINT64(env.fpip, X86CPU), | |
351 | VMSTATE_UINT64(env.fpdp, X86CPU), | |
42cc8fa6 JK |
352 | VMSTATE_END_OF_LIST() |
353 | } | |
354 | }; | |
355 | ||
f28558d3 WA |
356 | static bool tsc_adjust_needed(void *opaque) |
357 | { | |
f56e3a14 AF |
358 | X86CPU *cpu = opaque; |
359 | CPUX86State *env = &cpu->env; | |
f28558d3 WA |
360 | |
361 | return env->tsc_adjust != 0; | |
362 | } | |
363 | ||
364 | static const VMStateDescription vmstate_msr_tsc_adjust = { | |
365 | .name = "cpu/msr_tsc_adjust", | |
366 | .version_id = 1, | |
367 | .minimum_version_id = 1, | |
368 | .minimum_version_id_old = 1, | |
369 | .fields = (VMStateField[]) { | |
f56e3a14 | 370 | VMSTATE_UINT64(env.tsc_adjust, X86CPU), |
f28558d3 WA |
371 | VMSTATE_END_OF_LIST() |
372 | } | |
373 | }; | |
374 | ||
aa82ba54 LJ |
375 | static bool tscdeadline_needed(void *opaque) |
376 | { | |
f56e3a14 AF |
377 | X86CPU *cpu = opaque; |
378 | CPUX86State *env = &cpu->env; | |
aa82ba54 LJ |
379 | |
380 | return env->tsc_deadline != 0; | |
381 | } | |
382 | ||
383 | static const VMStateDescription vmstate_msr_tscdeadline = { | |
384 | .name = "cpu/msr_tscdeadline", | |
385 | .version_id = 1, | |
386 | .minimum_version_id = 1, | |
387 | .minimum_version_id_old = 1, | |
388 | .fields = (VMStateField []) { | |
f56e3a14 | 389 | VMSTATE_UINT64(env.tsc_deadline, X86CPU), |
aa82ba54 LJ |
390 | VMSTATE_END_OF_LIST() |
391 | } | |
392 | }; | |
393 | ||
21e87c46 AK |
394 | static bool misc_enable_needed(void *opaque) |
395 | { | |
f56e3a14 AF |
396 | X86CPU *cpu = opaque; |
397 | CPUX86State *env = &cpu->env; | |
21e87c46 AK |
398 | |
399 | return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT; | |
400 | } | |
401 | ||
402 | static const VMStateDescription vmstate_msr_ia32_misc_enable = { | |
403 | .name = "cpu/msr_ia32_misc_enable", | |
404 | .version_id = 1, | |
405 | .minimum_version_id = 1, | |
406 | .minimum_version_id_old = 1, | |
407 | .fields = (VMStateField []) { | |
f56e3a14 | 408 | VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU), |
21e87c46 AK |
409 | VMSTATE_END_OF_LIST() |
410 | } | |
411 | }; | |
412 | ||
f56e3a14 | 413 | const VMStateDescription vmstate_x86_cpu = { |
0cb892aa | 414 | .name = "cpu", |
f56e3a14 | 415 | .version_id = 12, |
0cb892aa JQ |
416 | .minimum_version_id = 3, |
417 | .minimum_version_id_old = 3, | |
418 | .pre_save = cpu_pre_save, | |
0cb892aa JQ |
419 | .post_load = cpu_post_load, |
420 | .fields = (VMStateField []) { | |
f56e3a14 AF |
421 | VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS), |
422 | VMSTATE_UINTTL(env.eip, X86CPU), | |
423 | VMSTATE_UINTTL(env.eflags, X86CPU), | |
424 | VMSTATE_UINT32(env.hflags, X86CPU), | |
0cb892aa | 425 | /* FPU */ |
f56e3a14 AF |
426 | VMSTATE_UINT16(env.fpuc, X86CPU), |
427 | VMSTATE_UINT16(env.fpus_vmstate, X86CPU), | |
428 | VMSTATE_UINT16(env.fptag_vmstate, X86CPU), | |
429 | VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU), | |
430 | VMSTATE_FP_REGS(env.fpregs, X86CPU, 8), | |
431 | ||
432 | VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6), | |
433 | VMSTATE_SEGMENT(env.ldt, X86CPU), | |
434 | VMSTATE_SEGMENT(env.tr, X86CPU), | |
435 | VMSTATE_SEGMENT(env.gdt, X86CPU), | |
436 | VMSTATE_SEGMENT(env.idt, X86CPU), | |
437 | ||
438 | VMSTATE_UINT32(env.sysenter_cs, X86CPU), | |
0cb892aa JQ |
439 | #ifdef TARGET_X86_64 |
440 | /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */ | |
f56e3a14 AF |
441 | VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7), |
442 | VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7), | |
443 | VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7), | |
444 | VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7), | |
8dd3dca3 | 445 | #else |
f56e3a14 AF |
446 | VMSTATE_UINTTL(env.sysenter_esp, X86CPU), |
447 | VMSTATE_UINTTL(env.sysenter_eip, X86CPU), | |
3c8ce630 | 448 | #endif |
8dd3dca3 | 449 | |
f56e3a14 AF |
450 | VMSTATE_UINTTL(env.cr[0], X86CPU), |
451 | VMSTATE_UINTTL(env.cr[2], X86CPU), | |
452 | VMSTATE_UINTTL(env.cr[3], X86CPU), | |
453 | VMSTATE_UINTTL(env.cr[4], X86CPU), | |
454 | VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8), | |
0cb892aa | 455 | /* MMU */ |
f56e3a14 | 456 | VMSTATE_INT32(env.a20_mask, X86CPU), |
0cb892aa | 457 | /* XMM */ |
f56e3a14 AF |
458 | VMSTATE_UINT32(env.mxcsr, X86CPU), |
459 | VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, CPU_NB_REGS), | |
8dd3dca3 AJ |
460 | |
461 | #ifdef TARGET_X86_64 | |
f56e3a14 AF |
462 | VMSTATE_UINT64(env.efer, X86CPU), |
463 | VMSTATE_UINT64(env.star, X86CPU), | |
464 | VMSTATE_UINT64(env.lstar, X86CPU), | |
465 | VMSTATE_UINT64(env.cstar, X86CPU), | |
466 | VMSTATE_UINT64(env.fmask, X86CPU), | |
467 | VMSTATE_UINT64(env.kernelgsbase, X86CPU), | |
8dd3dca3 | 468 | #endif |
f56e3a14 AF |
469 | VMSTATE_UINT32_V(env.smbase, X86CPU, 4), |
470 | ||
471 | VMSTATE_UINT64_V(env.pat, X86CPU, 5), | |
472 | VMSTATE_UINT32_V(env.hflags2, X86CPU, 5), | |
473 | ||
259186a7 | 474 | VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5), |
f56e3a14 AF |
475 | VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5), |
476 | VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5), | |
477 | VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5), | |
478 | VMSTATE_UINT64_V(env.intercept, X86CPU, 5), | |
479 | VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5), | |
480 | VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5), | |
481 | VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5), | |
482 | VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5), | |
483 | VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5), | |
484 | VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5), | |
dd5e3b17 | 485 | /* MTRRs */ |
f56e3a14 AF |
486 | VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8), |
487 | VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8), | |
488 | VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, 8, 8), | |
0cb892aa | 489 | /* KVM-related states */ |
f56e3a14 AF |
490 | VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9), |
491 | VMSTATE_UINT32_V(env.mp_state, X86CPU, 9), | |
492 | VMSTATE_UINT64_V(env.tsc, X86CPU, 9), | |
493 | VMSTATE_INT32_V(env.exception_injected, X86CPU, 11), | |
494 | VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11), | |
495 | VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11), | |
496 | VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11), | |
497 | VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11), | |
498 | VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11), | |
0cb892aa | 499 | /* MCE */ |
f56e3a14 AF |
500 | VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10), |
501 | VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10), | |
502 | VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10), | |
503 | VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10), | |
0cb892aa | 504 | /* rdtscp */ |
f56e3a14 | 505 | VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11), |
1a03675d | 506 | /* KVM pvclock msr */ |
f56e3a14 AF |
507 | VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11), |
508 | VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11), | |
f1665b21 | 509 | /* XSAVE related fields */ |
f56e3a14 AF |
510 | VMSTATE_UINT64_V(env.xcr0, X86CPU, 12), |
511 | VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12), | |
512 | VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12), | |
0cb892aa | 513 | VMSTATE_END_OF_LIST() |
a0fb002c | 514 | /* The above list is not sorted /wrt version numbers, watch out! */ |
f6584ee2 GN |
515 | }, |
516 | .subsections = (VMStateSubsection []) { | |
517 | { | |
518 | .vmsd = &vmstate_async_pf_msr, | |
519 | .needed = async_pf_msr_needed, | |
bc9a839d MT |
520 | } , { |
521 | .vmsd = &vmstate_pv_eoi_msr, | |
522 | .needed = pv_eoi_msr_needed, | |
917367aa MT |
523 | } , { |
524 | .vmsd = &vmstate_steal_time_msr, | |
525 | .needed = steal_time_msr_needed, | |
42cc8fa6 JK |
526 | } , { |
527 | .vmsd = &vmstate_fpop_ip_dp, | |
528 | .needed = fpop_ip_dp_needed, | |
f28558d3 WA |
529 | }, { |
530 | .vmsd = &vmstate_msr_tsc_adjust, | |
531 | .needed = tsc_adjust_needed, | |
aa82ba54 LJ |
532 | }, { |
533 | .vmsd = &vmstate_msr_tscdeadline, | |
534 | .needed = tscdeadline_needed, | |
21e87c46 AK |
535 | }, { |
536 | .vmsd = &vmstate_msr_ia32_misc_enable, | |
537 | .needed = misc_enable_needed, | |
f6584ee2 GN |
538 | } , { |
539 | /* empty */ | |
540 | } | |
79c4f6b0 | 541 | } |
0cb892aa | 542 | }; |