[qemu.git] / target-i386 / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/pc.h"
#include "hw/isa.h"
#include "host-utils.h"

#include "exec-all.h"
#include "kvm.h"

static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
{
    qemu_put_be32(f, dt->selector);
    qemu_put_betl(f, dt->base);
    qemu_put_be32(f, dt->limit);
    qemu_put_be32(f, dt->flags);
}

static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
{
    dt->selector = qemu_get_be32(f);
    dt->base = qemu_get_betl(f);
    dt->limit = qemu_get_be32(f);
    dt->flags = qemu_get_be32(f);
}

void cpu_save(QEMUFile *f, void *opaque)
{
    CPUState *env = opaque;
    uint16_t fptag, fpus, fpuc, fpregs_format;
    uint32_t hflags;
    int32_t a20_mask;
    int32_t pending_irq;
    int i, bit;

    cpu_synchronize_state(env, 0);

    for(i = 0; i < CPU_NB_REGS; i++)
        qemu_put_betls(f, &env->regs[i]);
    qemu_put_betls(f, &env->eip);
    qemu_put_betls(f, &env->eflags);
    hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
    qemu_put_be32s(f, &hflags);

    /* FPU */
    fpuc = env->fpuc;
    fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
    fptag = 0;
    for(i = 0; i < 8; i++) {
        fptag |= ((!env->fptags[i]) << i);
    }

    qemu_put_be16s(f, &fpuc);
    qemu_put_be16s(f, &fpus);
    qemu_put_be16s(f, &fptag);

#ifdef USE_X86LDOUBLE
    fpregs_format = 0;
#else
    fpregs_format = 1;
#endif
    qemu_put_be16s(f, &fpregs_format);

    for(i = 0; i < 8; i++) {
#ifdef USE_X86LDOUBLE
        {
            uint64_t mant;
            uint16_t exp;
            /* we save the real CPU data (in case of MMX usage only 'mant'
               contains the MMX register */
            cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
            qemu_put_be64(f, mant);
            qemu_put_be16(f, exp);
        }
#else
        /* if we use doubles for float emulation, we save the doubles to
           avoid losing information in case of MMX usage. It can give
           problems if the image is restored on a CPU where long
           doubles are used instead. */
        qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
#endif
    }

    for(i = 0; i < 6; i++)
        cpu_put_seg(f, &env->segs[i]);
    cpu_put_seg(f, &env->ldt);
    cpu_put_seg(f, &env->tr);
    cpu_put_seg(f, &env->gdt);
    cpu_put_seg(f, &env->idt);

    qemu_put_be32s(f, &env->sysenter_cs);
    qemu_put_betls(f, &env->sysenter_esp);
    qemu_put_betls(f, &env->sysenter_eip);

    qemu_put_betls(f, &env->cr[0]);
    qemu_put_betls(f, &env->cr[2]);
    qemu_put_betls(f, &env->cr[3]);
    qemu_put_betls(f, &env->cr[4]);

    for(i = 0; i < 8; i++)
        qemu_put_betls(f, &env->dr[i]);

    /* MMU */
    a20_mask = (int32_t) env->a20_mask;
    qemu_put_sbe32s(f, &a20_mask);

    /* XMM */
    qemu_put_be32s(f, &env->mxcsr);
    for(i = 0; i < CPU_NB_REGS; i++) {
        qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
        qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
    }

#ifdef TARGET_X86_64
    qemu_put_be64s(f, &env->efer);
    qemu_put_be64s(f, &env->star);
    qemu_put_be64s(f, &env->lstar);
    qemu_put_be64s(f, &env->cstar);
    qemu_put_be64s(f, &env->fmask);
    qemu_put_be64s(f, &env->kernelgsbase);
#endif
    qemu_put_be32s(f, &env->smbase);

    qemu_put_be64s(f, &env->pat);
    qemu_put_be32s(f, &env->hflags2);
    
    qemu_put_be64s(f, &env->vm_hsave);
    qemu_put_be64s(f, &env->vm_vmcb);
    qemu_put_be64s(f, &env->tsc_offset);
    qemu_put_be64s(f, &env->intercept);
    qemu_put_be16s(f, &env->intercept_cr_read);
    qemu_put_be16s(f, &env->intercept_cr_write);
    qemu_put_be16s(f, &env->intercept_dr_read);
    qemu_put_be16s(f, &env->intercept_dr_write);
    qemu_put_be32s(f, &env->intercept_exceptions);
    qemu_put_8s(f, &env->v_tpr);

    /* MTRRs */
    for(i = 0; i < 11; i++)
        qemu_put_be64s(f, &env->mtrr_fixed[i]);
    qemu_put_be64s(f, &env->mtrr_deftype);
    for(i = 0; i < 8; i++) {
        qemu_put_be64s(f, &env->mtrr_var[i].base);
        qemu_put_be64s(f, &env->mtrr_var[i].mask);
    }

    /* KVM-related states */

    /* There can only be one pending IRQ set in the bitmap at a time, so try
       to find it and save its number instead (-1 for none). */
    pending_irq = -1;
    for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) {
        if (env->interrupt_bitmap[i]) {
            bit = ctz64(env->interrupt_bitmap[i]);
            pending_irq = i * 64 + bit;
            break;
        }
    }
    qemu_put_sbe32s(f, &pending_irq);
    qemu_put_be32s(f, &env->mp_state);
    qemu_put_be64s(f, &env->tsc);
}

#ifdef USE_X86LDOUBLE
/* XXX: add that in a FPU generic layer */
union x86_longdouble {
    uint64_t mant;
    uint16_t exp;
};

#define MANTD1(fp)	(fp & ((1LL << 52) - 1))
#define EXPBIAS1 1023
#define EXPD1(fp)	((fp >> 52) & 0x7FF)
#define SIGND1(fp)	((fp >> 32) & 0x80000000)

static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
{
    int e;
    /* mantissa */
    p->mant = (MANTD1(temp) << 11) | (1LL << 63);
    /* exponent + sign */
    e = EXPD1(temp) - EXPBIAS1 + 16383;
    e |= SIGND1(temp) >> 16;
    p->exp = e;
}
#endif

int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
    CPUState *env = opaque;
    int i, guess_mmx;
    uint32_t hflags;
    uint16_t fpus, fpuc, fptag, fpregs_format;
    int32_t a20_mask;
    int32_t pending_irq;

    if (version_id < 3 || version_id > CPU_SAVE_VERSION)
        return -EINVAL;
    for(i = 0; i < CPU_NB_REGS; i++)
        qemu_get_betls(f, &env->regs[i]);
    qemu_get_betls(f, &env->eip);
    qemu_get_betls(f, &env->eflags);
    qemu_get_be32s(f, &hflags);

    qemu_get_be16s(f, &fpuc);
    qemu_get_be16s(f, &fpus);
    qemu_get_be16s(f, &fptag);
    qemu_get_be16s(f, &fpregs_format);

    /* NOTE: we cannot always restore the FPU state if the image come
       from a host with a different 'USE_X86LDOUBLE' define. We guess
       if we are in an MMX state to restore correctly in that case. */
    guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
    for(i = 0; i < 8; i++) {
        uint64_t mant;
        uint16_t exp;

        switch(fpregs_format) {
        case 0:
            mant = qemu_get_be64(f);
            exp = qemu_get_be16(f);
#ifdef USE_X86LDOUBLE
            env->fpregs[i].d = cpu_set_fp80(mant, exp);
#else
            /* difficult case */
            if (guess_mmx)
                env->fpregs[i].mmx.MMX_Q(0) = mant;
            else
                env->fpregs[i].d = cpu_set_fp80(mant, exp);
#endif
            break;
        case 1:
            mant = qemu_get_be64(f);
#ifdef USE_X86LDOUBLE
            {
                union x86_longdouble *p;
                /* difficult case */
                p = (void *)&env->fpregs[i];
                if (guess_mmx) {
                    p->mant = mant;
                    p->exp = 0xffff;
                } else {
                    fp64_to_fp80(p, mant);
                }
            }
#else
            env->fpregs[i].mmx.MMX_Q(0) = mant;
#endif
            break;
        default:
            return -EINVAL;
        }
    }

    env->fpuc = fpuc;
    /* XXX: restore FPU round state */
    env->fpstt = (fpus >> 11) & 7;
    env->fpus = fpus & ~0x3800;
    fptag ^= 0xff;
    for(i = 0; i < 8; i++) {
        env->fptags[i] = (fptag >> i) & 1;
    }

    for(i = 0; i < 6; i++)
        cpu_get_seg(f, &env->segs[i]);
    cpu_get_seg(f, &env->ldt);
    cpu_get_seg(f, &env->tr);
    cpu_get_seg(f, &env->gdt);
    cpu_get_seg(f, &env->idt);

    qemu_get_be32s(f, &env->sysenter_cs);
    if (version_id >= 7) {
        qemu_get_betls(f, &env->sysenter_esp);
        qemu_get_betls(f, &env->sysenter_eip);
    } else {
        env->sysenter_esp = qemu_get_be32(f);
        env->sysenter_eip = qemu_get_be32(f);
    }

    qemu_get_betls(f, &env->cr[0]);
    qemu_get_betls(f, &env->cr[2]);
    qemu_get_betls(f, &env->cr[3]);
    qemu_get_betls(f, &env->cr[4]);

    for(i = 0; i < 8; i++)
        qemu_get_betls(f, &env->dr[i]);
    cpu_breakpoint_remove_all(env, BP_CPU);
    cpu_watchpoint_remove_all(env, BP_CPU);
    for (i = 0; i < 4; i++)
        hw_breakpoint_insert(env, i);

    /* MMU */
    qemu_get_sbe32s(f, &a20_mask);
    env->a20_mask = a20_mask;

    qemu_get_be32s(f, &env->mxcsr);
    for(i = 0; i < CPU_NB_REGS; i++) {
        qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
        qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
    }

#ifdef TARGET_X86_64
    qemu_get_be64s(f, &env->efer);
    qemu_get_be64s(f, &env->star);
    qemu_get_be64s(f, &env->lstar);
    qemu_get_be64s(f, &env->cstar);
    qemu_get_be64s(f, &env->fmask);
    qemu_get_be64s(f, &env->kernelgsbase);
#endif
    if (version_id >= 4) {
        qemu_get_be32s(f, &env->smbase);
    }
    if (version_id >= 5) {
        qemu_get_be64s(f, &env->pat);
        qemu_get_be32s(f, &env->hflags2);
        if (version_id < 6)
            qemu_get_be32s(f, &env->halted);

        qemu_get_be64s(f, &env->vm_hsave);
        qemu_get_be64s(f, &env->vm_vmcb);
        qemu_get_be64s(f, &env->tsc_offset);
        qemu_get_be64s(f, &env->intercept);
        qemu_get_be16s(f, &env->intercept_cr_read);
        qemu_get_be16s(f, &env->intercept_cr_write);
        qemu_get_be16s(f, &env->intercept_dr_read);
        qemu_get_be16s(f, &env->intercept_dr_write);
        qemu_get_be32s(f, &env->intercept_exceptions);
        qemu_get_8s(f, &env->v_tpr);
    }

    if (version_id >= 8) {
        /* MTRRs */
        for(i = 0; i < 11; i++)
            qemu_get_be64s(f, &env->mtrr_fixed[i]);
        qemu_get_be64s(f, &env->mtrr_deftype);
        for(i = 0; i < 8; i++) {
            qemu_get_be64s(f, &env->mtrr_var[i].base);
            qemu_get_be64s(f, &env->mtrr_var[i].mask);
        }
    }

    if (version_id >= 9) {
        qemu_get_sbe32s(f, &pending_irq);
        memset(&env->interrupt_bitmap, 0, sizeof(env->interrupt_bitmap));
        if (pending_irq >= 0) {
            env->interrupt_bitmap[pending_irq / 64] |=
                (uint64_t)1 << (pending_irq % 64);
        }
        qemu_get_be32s(f, &env->mp_state);
        qemu_get_be64s(f, &env->tsc);
    }

    /* XXX: ensure compatiblity for halted bit ? */
    /* XXX: compute redundant hflags bits */
    env->hflags = hflags;
    tlb_flush(env, 1);
    cpu_synchronize_state(env, 1);
    return 0;
}
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
	2	#include "hw/boards.h"
	3	#include "hw/pc.h"
	4	#include "hw/isa.h"
6ad8702a	5	#include "host-utils.h"
8dd3dca3 AJ	6
8dd3dca3 AJ	7	#include "exec-all.h"
b0a46a33	8	#include "kvm.h"
8dd3dca3	9
8dd3dca3 AJ	10	static void cpu_put_seg(QEMUFile f, SegmentCache dt)
	11	{
	12	qemu_put_be32(f, dt->selector);
	13	qemu_put_betl(f, dt->base);
	14	qemu_put_be32(f, dt->limit);
	15	qemu_put_be32(f, dt->flags);
	16	}
	17
	18	static void cpu_get_seg(QEMUFile f, SegmentCache dt)
	19	{
	20	dt->selector = qemu_get_be32(f);
	21	dt->base = qemu_get_betl(f);
	22	dt->limit = qemu_get_be32(f);
	23	dt->flags = qemu_get_be32(f);
	24	}
	25
	26	void cpu_save(QEMUFile f, void opaque)
	27	{
	28	CPUState *env = opaque;
	29	uint16_t fptag, fpus, fpuc, fpregs_format;
	30	uint32_t hflags;
7caa33f7	31	int32_t a20_mask;
059b8b1e JK	32	int32_t pending_irq;
059b8b1e JK	33	int i, bit;
8dd3dca3	34
b0a46a33 JK	35	cpu_synchronize_state(env, 0);
b0a46a33 JK	36
8dd3dca3 AJ	37	for(i = 0; i < CPU_NB_REGS; i++)
	38	qemu_put_betls(f, &env->regs[i]);
	39	qemu_put_betls(f, &env->eip);
	40	qemu_put_betls(f, &env->eflags);
	41	hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
	42	qemu_put_be32s(f, &hflags);
	43
	44	/* FPU */
	45	fpuc = env->fpuc;
	46	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
	47	fptag = 0;
	48	for(i = 0; i < 8; i++) {
	49	fptag \|= ((!env->fptags[i]) << i);
	50	}
	51
	52	qemu_put_be16s(f, &fpuc);
	53	qemu_put_be16s(f, &fpus);
	54	qemu_put_be16s(f, &fptag);
	55
	56	#ifdef USE_X86LDOUBLE
	57	fpregs_format = 0;
	58	#else
	59	fpregs_format = 1;
	60	#endif
	61	qemu_put_be16s(f, &fpregs_format);
	62
	63	for(i = 0; i < 8; i++) {
	64	#ifdef USE_X86LDOUBLE
	65	{
	66	uint64_t mant;
	67	uint16_t exp;
	68	/* we save the real CPU data (in case of MMX usage only 'mant'
	69	contains the MMX register */
	70	cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
	71	qemu_put_be64(f, mant);
	72	qemu_put_be16(f, exp);
	73	}
	74	#else
	75	/* if we use doubles for float emulation, we save the doubles to
	76	avoid losing information in case of MMX usage. It can give
	77	problems if the image is restored on a CPU where long
	78	doubles are used instead. */
	79	qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
	80	#endif
	81	}
	82
	83	for(i = 0; i < 6; i++)
	84	cpu_put_seg(f, &env->segs[i]);
	85	cpu_put_seg(f, &env->ldt);
	86	cpu_put_seg(f, &env->tr);
	87	cpu_put_seg(f, &env->gdt);
	88	cpu_put_seg(f, &env->idt);
	89
f5049756	90	qemu_put_be32s(f, &env->sysenter_cs);
2436b61a AZ	91	qemu_put_betls(f, &env->sysenter_esp);
2436b61a AZ	92	qemu_put_betls(f, &env->sysenter_eip);
8dd3dca3 AJ	93
	94	qemu_put_betls(f, &env->cr[0]);
	95	qemu_put_betls(f, &env->cr[2]);
	96	qemu_put_betls(f, &env->cr[3]);
	97	qemu_put_betls(f, &env->cr[4]);
	98
	99	for(i = 0; i < 8; i++)
	100	qemu_put_betls(f, &env->dr[i]);
	101
	102	/* MMU */
7caa33f7	103	a20_mask = (int32_t) env->a20_mask;
b6c4f71f	104	qemu_put_sbe32s(f, &a20_mask);
8dd3dca3 AJ	105
	106	/* XMM */
	107	qemu_put_be32s(f, &env->mxcsr);
	108	for(i = 0; i < CPU_NB_REGS; i++) {
	109	qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
	110	qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
	111	}
	112
	113	#ifdef TARGET_X86_64
	114	qemu_put_be64s(f, &env->efer);
	115	qemu_put_be64s(f, &env->star);
	116	qemu_put_be64s(f, &env->lstar);
	117	qemu_put_be64s(f, &env->cstar);
	118	qemu_put_be64s(f, &env->fmask);
	119	qemu_put_be64s(f, &env->kernelgsbase);
	120	#endif
	121	qemu_put_be32s(f, &env->smbase);
5cc1d1e6 FB	122
	123	qemu_put_be64s(f, &env->pat);
	124	qemu_put_be32s(f, &env->hflags2);
5cc1d1e6 FB	125
	126	qemu_put_be64s(f, &env->vm_hsave);
	127	qemu_put_be64s(f, &env->vm_vmcb);
	128	qemu_put_be64s(f, &env->tsc_offset);
	129	qemu_put_be64s(f, &env->intercept);
	130	qemu_put_be16s(f, &env->intercept_cr_read);
	131	qemu_put_be16s(f, &env->intercept_cr_write);
	132	qemu_put_be16s(f, &env->intercept_dr_read);
	133	qemu_put_be16s(f, &env->intercept_dr_write);
	134	qemu_put_be32s(f, &env->intercept_exceptions);
	135	qemu_put_8s(f, &env->v_tpr);
dd5e3b17 AL	136
	137	/* MTRRs */
	138	for(i = 0; i < 11; i++)
	139	qemu_put_be64s(f, &env->mtrr_fixed[i]);
	140	qemu_put_be64s(f, &env->mtrr_deftype);
	141	for(i = 0; i < 8; i++) {
	142	qemu_put_be64s(f, &env->mtrr_var[i].base);
	143	qemu_put_be64s(f, &env->mtrr_var[i].mask);
	144	}
f8d926e9	145
059b8b1e JK	146	/* KVM-related states */
	147
	148	/* There can only be one pending IRQ set in the bitmap at a time, so try
	149	to find it and save its number instead (-1 for none). */
	150	pending_irq = -1;
	151	for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) {
6ad8702a JK	152	if (env->interrupt_bitmap[i]) {
	153	bit = ctz64(env->interrupt_bitmap[i]);
	154	pending_irq = i * 64 + bit;
059b8b1e JK	155	break;
059b8b1e JK	156	}
f8d926e9	157	}
059b8b1e	158	qemu_put_sbe32s(f, &pending_irq);
f8d926e9	159	qemu_put_be32s(f, &env->mp_state);
059b8b1e	160	qemu_put_be64s(f, &env->tsc);
8dd3dca3 AJ	161	}
	162
	163	#ifdef USE_X86LDOUBLE
	164	/* XXX: add that in a FPU generic layer */
	165	union x86_longdouble {
	166	uint64_t mant;
	167	uint16_t exp;
	168	};
	169
	170	#define MANTD1(fp) (fp & ((1LL << 52) - 1))
	171	#define EXPBIAS1 1023
	172	#define EXPD1(fp) ((fp >> 52) & 0x7FF)
	173	#define SIGND1(fp) ((fp >> 32) & 0x80000000)
	174
	175	static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
	176	{
	177	int e;
	178	/* mantissa */
	179	p->mant = (MANTD1(temp) << 11) \| (1LL << 63);
	180	/* exponent + sign */
	181	e = EXPD1(temp) - EXPBIAS1 + 16383;
	182	e \|= SIGND1(temp) >> 16;
	183	p->exp = e;
	184	}
	185	#endif
	186
	187	int cpu_load(QEMUFile f, void opaque, int version_id)
	188	{
	189	CPUState *env = opaque;
	190	int i, guess_mmx;
	191	uint32_t hflags;
	192	uint16_t fpus, fpuc, fptag, fpregs_format;
7caa33f7	193	int32_t a20_mask;
059b8b1e	194	int32_t pending_irq;
8dd3dca3	195
f8d926e9	196	if (version_id < 3 \|\| version_id > CPU_SAVE_VERSION)
8dd3dca3 AJ	197	return -EINVAL;
	198	for(i = 0; i < CPU_NB_REGS; i++)
	199	qemu_get_betls(f, &env->regs[i]);
	200	qemu_get_betls(f, &env->eip);
	201	qemu_get_betls(f, &env->eflags);
	202	qemu_get_be32s(f, &hflags);
	203
	204	qemu_get_be16s(f, &fpuc);
	205	qemu_get_be16s(f, &fpus);
	206	qemu_get_be16s(f, &fptag);
	207	qemu_get_be16s(f, &fpregs_format);
	208
	209	/* NOTE: we cannot always restore the FPU state if the image come
	210	from a host with a different 'USE_X86LDOUBLE' define. We guess
	211	if we are in an MMX state to restore correctly in that case. */
	212	guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
	213	for(i = 0; i < 8; i++) {
	214	uint64_t mant;
	215	uint16_t exp;
	216
	217	switch(fpregs_format) {
	218	case 0:
	219	mant = qemu_get_be64(f);
	220	exp = qemu_get_be16(f);
	221	#ifdef USE_X86LDOUBLE
	222	env->fpregs[i].d = cpu_set_fp80(mant, exp);
	223	#else
	224	/* difficult case */
	225	if (guess_mmx)
	226	env->fpregs[i].mmx.MMX_Q(0) = mant;
	227	else
	228	env->fpregs[i].d = cpu_set_fp80(mant, exp);
	229	#endif
	230	break;
	231	case 1:
	232	mant = qemu_get_be64(f);
	233	#ifdef USE_X86LDOUBLE
	234	{
	235	union x86_longdouble *p;
	236	/* difficult case */
	237	p = (void *)&env->fpregs[i];
	238	if (guess_mmx) {
	239	p->mant = mant;
	240	p->exp = 0xffff;
	241	} else {
	242	fp64_to_fp80(p, mant);
	243	}
	244	}
	245	#else
	246	env->fpregs[i].mmx.MMX_Q(0) = mant;
	247	#endif
	248	break;
	249	default:
	250	return -EINVAL;
	251	}
	252	}
	253
	254	env->fpuc = fpuc;
	255	/* XXX: restore FPU round state */
	256	env->fpstt = (fpus >> 11) & 7;
	257	env->fpus = fpus & ~0x3800;
	258	fptag ^= 0xff;
	259	for(i = 0; i < 8; i++) {
	260	env->fptags[i] = (fptag >> i) & 1;
261	}
262
263	for(i = 0; i < 6; i++)
264	cpu_get_seg(f, &env->segs[i]);
265	cpu_get_seg(f, &env->ldt);
266	cpu_get_seg(f, &env->tr);
267	cpu_get_seg(f, &env->gdt);
268	cpu_get_seg(f, &env->idt);
269
270	qemu_get_be32s(f, &env->sysenter_cs);
2436b61a AZ	271	if (version_id >= 7) {
	272	qemu_get_betls(f, &env->sysenter_esp);
	273	qemu_get_betls(f, &env->sysenter_eip);
	274	} else {
e5ceb244 AL	275	env->sysenter_esp = qemu_get_be32(f);
e5ceb244 AL	276	env->sysenter_eip = qemu_get_be32(f);
2436b61a	277	}
8dd3dca3 AJ	278
	279	qemu_get_betls(f, &env->cr[0]);
	280	qemu_get_betls(f, &env->cr[2]);
	281	qemu_get_betls(f, &env->cr[3]);
	282	qemu_get_betls(f, &env->cr[4]);
	283
	284	for(i = 0; i < 8; i++)
	285	qemu_get_betls(f, &env->dr[i]);
01df040b AL	286	cpu_breakpoint_remove_all(env, BP_CPU);
	287	cpu_watchpoint_remove_all(env, BP_CPU);
	288	for (i = 0; i < 4; i++)
	289	hw_breakpoint_insert(env, i);
8dd3dca3 AJ	290
8dd3dca3 AJ	291	/* MMU */
b6c4f71f	292	qemu_get_sbe32s(f, &a20_mask);
7caa33f7	293	env->a20_mask = a20_mask;
8dd3dca3 AJ	294
	295	qemu_get_be32s(f, &env->mxcsr);
	296	for(i = 0; i < CPU_NB_REGS; i++) {
	297	qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
	298	qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
	299	}
	300
	301	#ifdef TARGET_X86_64
	302	qemu_get_be64s(f, &env->efer);
	303	qemu_get_be64s(f, &env->star);
	304	qemu_get_be64s(f, &env->lstar);
	305	qemu_get_be64s(f, &env->cstar);
	306	qemu_get_be64s(f, &env->fmask);
	307	qemu_get_be64s(f, &env->kernelgsbase);
	308	#endif
5cc1d1e6	309	if (version_id >= 4) {
8dd3dca3	310	qemu_get_be32s(f, &env->smbase);
5cc1d1e6 FB	311	}
	312	if (version_id >= 5) {
	313	qemu_get_be64s(f, &env->pat);
	314	qemu_get_be32s(f, &env->hflags2);
9656f324 PB	315	if (version_id < 6)
9656f324 PB	316	qemu_get_be32s(f, &env->halted);
5cc1d1e6 FB	317
	318	qemu_get_be64s(f, &env->vm_hsave);
	319	qemu_get_be64s(f, &env->vm_vmcb);
	320	qemu_get_be64s(f, &env->tsc_offset);
	321	qemu_get_be64s(f, &env->intercept);
	322	qemu_get_be16s(f, &env->intercept_cr_read);
	323	qemu_get_be16s(f, &env->intercept_cr_write);
	324	qemu_get_be16s(f, &env->intercept_dr_read);
	325	qemu_get_be16s(f, &env->intercept_dr_write);
	326	qemu_get_be32s(f, &env->intercept_exceptions);
	327	qemu_get_8s(f, &env->v_tpr);
	328	}
dd5e3b17 AL	329
	330	if (version_id >= 8) {
	331	/* MTRRs */
	332	for(i = 0; i < 11; i++)
	333	qemu_get_be64s(f, &env->mtrr_fixed[i]);
	334	qemu_get_be64s(f, &env->mtrr_deftype);
	335	for(i = 0; i < 8; i++) {
	336	qemu_get_be64s(f, &env->mtrr_var[i].base);
	337	qemu_get_be64s(f, &env->mtrr_var[i].mask);
	338	}
	339	}
059b8b1e	340
f8d926e9	341	if (version_id >= 9) {
059b8b1e JK	342	qemu_get_sbe32s(f, &pending_irq);
	343	memset(&env->interrupt_bitmap, 0, sizeof(env->interrupt_bitmap));
	344	if (pending_irq >= 0) {
	345	env->interrupt_bitmap[pending_irq / 64] \|=
	346	(uint64_t)1 << (pending_irq % 64);
f8d926e9	347	}
f8d926e9	348	qemu_get_be32s(f, &env->mp_state);
059b8b1e	349	qemu_get_be64s(f, &env->tsc);
f8d926e9	350	}
dd5e3b17	351
5cc1d1e6 FB	352	/* XXX: ensure compatiblity for halted bit ? */
5cc1d1e6 FB	353	/* XXX: compute redundant hflags bits */
8dd3dca3 AJ	354	env->hflags = hflags;
8dd3dca3 AJ	355	tlb_flush(env, 1);
b0a46a33	356	cpu_synchronize_state(env, 1);
8dd3dca3 AJ	357	return 0;
8dd3dca3 AJ	358	}