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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 translation | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
2c0262af FB |
25 | |
26 | #include "cpu.h" | |
2c0262af | 27 | #include "disas.h" |
57fec1fe | 28 | #include "tcg-op.h" |
2c0262af | 29 | |
a7812ae4 PB |
30 | #include "helper.h" |
31 | #define GEN_HELPER 1 | |
32 | #include "helper.h" | |
33 | ||
2c0262af FB |
34 | #define PREFIX_REPZ 0x01 |
35 | #define PREFIX_REPNZ 0x02 | |
36 | #define PREFIX_LOCK 0x04 | |
37 | #define PREFIX_DATA 0x08 | |
38 | #define PREFIX_ADR 0x10 | |
39 | ||
14ce26e7 FB |
40 | #ifdef TARGET_X86_64 |
41 | #define X86_64_ONLY(x) x | |
001faf32 | 42 | #define X86_64_DEF(...) __VA_ARGS__ |
14ce26e7 FB |
43 | #define CODE64(s) ((s)->code64) |
44 | #define REX_X(s) ((s)->rex_x) | |
45 | #define REX_B(s) ((s)->rex_b) | |
46 | /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */ | |
47 | #if 1 | |
48 | #define BUGGY_64(x) NULL | |
49 | #endif | |
50 | #else | |
51 | #define X86_64_ONLY(x) NULL | |
001faf32 | 52 | #define X86_64_DEF(...) |
14ce26e7 FB |
53 | #define CODE64(s) 0 |
54 | #define REX_X(s) 0 | |
55 | #define REX_B(s) 0 | |
56 | #endif | |
57 | ||
57fec1fe FB |
58 | //#define MACRO_TEST 1 |
59 | ||
57fec1fe | 60 | /* global register indexes */ |
a7812ae4 PB |
61 | static TCGv_ptr cpu_env; |
62 | static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp; | |
63 | static TCGv_i32 cpu_cc_op; | |
cc739bb0 | 64 | static TCGv cpu_regs[CPU_NB_REGS]; |
1e4840bf FB |
65 | /* local temps */ |
66 | static TCGv cpu_T[2], cpu_T3; | |
57fec1fe | 67 | /* local register indexes (only used inside old micro ops) */ |
a7812ae4 PB |
68 | static TCGv cpu_tmp0, cpu_tmp4; |
69 | static TCGv_ptr cpu_ptr0, cpu_ptr1; | |
70 | static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; | |
71 | static TCGv_i64 cpu_tmp1_i64; | |
bedda79c | 72 | static TCGv cpu_tmp5; |
57fec1fe | 73 | |
1a7ff922 PB |
74 | static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
75 | ||
2e70f6ef PB |
76 | #include "gen-icount.h" |
77 | ||
57fec1fe FB |
78 | #ifdef TARGET_X86_64 |
79 | static int x86_64_hregs; | |
ae063a68 FB |
80 | #endif |
81 | ||
2c0262af FB |
82 | typedef struct DisasContext { |
83 | /* current insn context */ | |
84 | int override; /* -1 if no override */ | |
85 | int prefix; | |
86 | int aflag, dflag; | |
14ce26e7 | 87 | target_ulong pc; /* pc = eip + cs_base */ |
2c0262af FB |
88 | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
89 | static state change (stop translation) */ | |
90 | /* current block context */ | |
14ce26e7 | 91 | target_ulong cs_base; /* base of CS segment */ |
2c0262af FB |
92 | int pe; /* protected mode */ |
93 | int code32; /* 32 bit code segment */ | |
14ce26e7 FB |
94 | #ifdef TARGET_X86_64 |
95 | int lma; /* long mode active */ | |
96 | int code64; /* 64 bit code segment */ | |
97 | int rex_x, rex_b; | |
98 | #endif | |
2c0262af FB |
99 | int ss32; /* 32 bit stack segment */ |
100 | int cc_op; /* current CC operation */ | |
101 | int addseg; /* non zero if either DS/ES/SS have a non zero base */ | |
102 | int f_st; /* currently unused */ | |
103 | int vm86; /* vm86 mode */ | |
104 | int cpl; | |
105 | int iopl; | |
106 | int tf; /* TF cpu flag */ | |
34865134 | 107 | int singlestep_enabled; /* "hardware" single step enabled */ |
2c0262af FB |
108 | int jmp_opt; /* use direct block chaining for direct jumps */ |
109 | int mem_index; /* select memory access functions */ | |
c068688b | 110 | uint64_t flags; /* all execution flags */ |
2c0262af FB |
111 | struct TranslationBlock *tb; |
112 | int popl_esp_hack; /* for correct popl with esp base handling */ | |
14ce26e7 FB |
113 | int rip_offset; /* only used in x86_64, but left for simplicity */ |
114 | int cpuid_features; | |
3d7374c5 | 115 | int cpuid_ext_features; |
e771edab | 116 | int cpuid_ext2_features; |
12e26b75 | 117 | int cpuid_ext3_features; |
2c0262af FB |
118 | } DisasContext; |
119 | ||
120 | static void gen_eob(DisasContext *s); | |
14ce26e7 FB |
121 | static void gen_jmp(DisasContext *s, target_ulong eip); |
122 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); | |
2c0262af FB |
123 | |
124 | /* i386 arith/logic operations */ | |
125 | enum { | |
5fafdf24 TS |
126 | OP_ADDL, |
127 | OP_ORL, | |
128 | OP_ADCL, | |
2c0262af | 129 | OP_SBBL, |
5fafdf24 TS |
130 | OP_ANDL, |
131 | OP_SUBL, | |
132 | OP_XORL, | |
2c0262af FB |
133 | OP_CMPL, |
134 | }; | |
135 | ||
136 | /* i386 shift ops */ | |
137 | enum { | |
5fafdf24 TS |
138 | OP_ROL, |
139 | OP_ROR, | |
140 | OP_RCL, | |
141 | OP_RCR, | |
142 | OP_SHL, | |
143 | OP_SHR, | |
2c0262af FB |
144 | OP_SHL1, /* undocumented */ |
145 | OP_SAR = 7, | |
146 | }; | |
147 | ||
8e1c85e3 FB |
148 | enum { |
149 | JCC_O, | |
150 | JCC_B, | |
151 | JCC_Z, | |
152 | JCC_BE, | |
153 | JCC_S, | |
154 | JCC_P, | |
155 | JCC_L, | |
156 | JCC_LE, | |
157 | }; | |
158 | ||
2c0262af FB |
159 | /* operand size */ |
160 | enum { | |
161 | OT_BYTE = 0, | |
162 | OT_WORD, | |
5fafdf24 | 163 | OT_LONG, |
2c0262af FB |
164 | OT_QUAD, |
165 | }; | |
166 | ||
167 | enum { | |
168 | /* I386 int registers */ | |
169 | OR_EAX, /* MUST be even numbered */ | |
170 | OR_ECX, | |
171 | OR_EDX, | |
172 | OR_EBX, | |
173 | OR_ESP, | |
174 | OR_EBP, | |
175 | OR_ESI, | |
176 | OR_EDI, | |
14ce26e7 FB |
177 | |
178 | OR_TMP0 = 16, /* temporary operand register */ | |
2c0262af FB |
179 | OR_TMP1, |
180 | OR_A0, /* temporary register used when doing address evaluation */ | |
2c0262af FB |
181 | }; |
182 | ||
57fec1fe FB |
183 | static inline void gen_op_movl_T0_0(void) |
184 | { | |
185 | tcg_gen_movi_tl(cpu_T[0], 0); | |
186 | } | |
187 | ||
188 | static inline void gen_op_movl_T0_im(int32_t val) | |
189 | { | |
190 | tcg_gen_movi_tl(cpu_T[0], val); | |
191 | } | |
192 | ||
193 | static inline void gen_op_movl_T0_imu(uint32_t val) | |
194 | { | |
195 | tcg_gen_movi_tl(cpu_T[0], val); | |
196 | } | |
197 | ||
198 | static inline void gen_op_movl_T1_im(int32_t val) | |
199 | { | |
200 | tcg_gen_movi_tl(cpu_T[1], val); | |
201 | } | |
202 | ||
203 | static inline void gen_op_movl_T1_imu(uint32_t val) | |
204 | { | |
205 | tcg_gen_movi_tl(cpu_T[1], val); | |
206 | } | |
207 | ||
208 | static inline void gen_op_movl_A0_im(uint32_t val) | |
209 | { | |
210 | tcg_gen_movi_tl(cpu_A0, val); | |
211 | } | |
212 | ||
213 | #ifdef TARGET_X86_64 | |
214 | static inline void gen_op_movq_A0_im(int64_t val) | |
215 | { | |
216 | tcg_gen_movi_tl(cpu_A0, val); | |
217 | } | |
218 | #endif | |
219 | ||
220 | static inline void gen_movtl_T0_im(target_ulong val) | |
221 | { | |
222 | tcg_gen_movi_tl(cpu_T[0], val); | |
223 | } | |
224 | ||
225 | static inline void gen_movtl_T1_im(target_ulong val) | |
226 | { | |
227 | tcg_gen_movi_tl(cpu_T[1], val); | |
228 | } | |
229 | ||
230 | static inline void gen_op_andl_T0_ffff(void) | |
231 | { | |
232 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
233 | } | |
234 | ||
235 | static inline void gen_op_andl_T0_im(uint32_t val) | |
236 | { | |
237 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); | |
238 | } | |
239 | ||
240 | static inline void gen_op_movl_T0_T1(void) | |
241 | { | |
242 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); | |
243 | } | |
244 | ||
245 | static inline void gen_op_andl_A0_ffff(void) | |
246 | { | |
247 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff); | |
248 | } | |
249 | ||
14ce26e7 FB |
250 | #ifdef TARGET_X86_64 |
251 | ||
252 | #define NB_OP_SIZES 4 | |
253 | ||
14ce26e7 FB |
254 | #else /* !TARGET_X86_64 */ |
255 | ||
256 | #define NB_OP_SIZES 3 | |
257 | ||
14ce26e7 FB |
258 | #endif /* !TARGET_X86_64 */ |
259 | ||
e2542fe2 | 260 | #if defined(HOST_WORDS_BIGENDIAN) |
57fec1fe FB |
261 | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
262 | #define REG_H_OFFSET (sizeof(target_ulong) - 2) | |
263 | #define REG_W_OFFSET (sizeof(target_ulong) - 2) | |
264 | #define REG_L_OFFSET (sizeof(target_ulong) - 4) | |
265 | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) | |
14ce26e7 | 266 | #else |
57fec1fe FB |
267 | #define REG_B_OFFSET 0 |
268 | #define REG_H_OFFSET 1 | |
269 | #define REG_W_OFFSET 0 | |
270 | #define REG_L_OFFSET 0 | |
271 | #define REG_LH_OFFSET 4 | |
14ce26e7 | 272 | #endif |
57fec1fe | 273 | |
1e4840bf | 274 | static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) |
57fec1fe FB |
275 | { |
276 | switch(ot) { | |
277 | case OT_BYTE: | |
278 | if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { | |
c832e3de | 279 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); |
57fec1fe | 280 | } else { |
c832e3de | 281 | tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); |
57fec1fe FB |
282 | } |
283 | break; | |
284 | case OT_WORD: | |
c832e3de | 285 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16); |
57fec1fe | 286 | break; |
cc739bb0 | 287 | default: /* XXX this shouldn't be reached; abort? */ |
57fec1fe | 288 | case OT_LONG: |
cc739bb0 LD |
289 | /* For x86_64, this sets the higher half of register to zero. |
290 | For i386, this is equivalent to a mov. */ | |
291 | tcg_gen_ext32u_tl(cpu_regs[reg], t0); | |
57fec1fe | 292 | break; |
cc739bb0 | 293 | #ifdef TARGET_X86_64 |
57fec1fe | 294 | case OT_QUAD: |
cc739bb0 | 295 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
57fec1fe | 296 | break; |
14ce26e7 | 297 | #endif |
57fec1fe FB |
298 | } |
299 | } | |
2c0262af | 300 | |
57fec1fe FB |
301 | static inline void gen_op_mov_reg_T0(int ot, int reg) |
302 | { | |
1e4840bf | 303 | gen_op_mov_reg_v(ot, reg, cpu_T[0]); |
57fec1fe FB |
304 | } |
305 | ||
306 | static inline void gen_op_mov_reg_T1(int ot, int reg) | |
307 | { | |
1e4840bf | 308 | gen_op_mov_reg_v(ot, reg, cpu_T[1]); |
57fec1fe FB |
309 | } |
310 | ||
311 | static inline void gen_op_mov_reg_A0(int size, int reg) | |
312 | { | |
313 | switch(size) { | |
314 | case 0: | |
c832e3de | 315 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16); |
57fec1fe | 316 | break; |
cc739bb0 | 317 | default: /* XXX this shouldn't be reached; abort? */ |
57fec1fe | 318 | case 1: |
cc739bb0 LD |
319 | /* For x86_64, this sets the higher half of register to zero. |
320 | For i386, this is equivalent to a mov. */ | |
321 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0); | |
57fec1fe | 322 | break; |
cc739bb0 | 323 | #ifdef TARGET_X86_64 |
57fec1fe | 324 | case 2: |
cc739bb0 | 325 | tcg_gen_mov_tl(cpu_regs[reg], cpu_A0); |
57fec1fe | 326 | break; |
14ce26e7 | 327 | #endif |
57fec1fe FB |
328 | } |
329 | } | |
330 | ||
1e4840bf | 331 | static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) |
57fec1fe FB |
332 | { |
333 | switch(ot) { | |
334 | case OT_BYTE: | |
335 | if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { | |
336 | goto std_case; | |
337 | } else { | |
cc739bb0 LD |
338 | tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); |
339 | tcg_gen_ext8u_tl(t0, t0); | |
57fec1fe FB |
340 | } |
341 | break; | |
342 | default: | |
343 | std_case: | |
cc739bb0 | 344 | tcg_gen_mov_tl(t0, cpu_regs[reg]); |
57fec1fe FB |
345 | break; |
346 | } | |
347 | } | |
348 | ||
1e4840bf FB |
349 | static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) |
350 | { | |
351 | gen_op_mov_v_reg(ot, cpu_T[t_index], reg); | |
352 | } | |
353 | ||
57fec1fe FB |
354 | static inline void gen_op_movl_A0_reg(int reg) |
355 | { | |
cc739bb0 | 356 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
357 | } |
358 | ||
359 | static inline void gen_op_addl_A0_im(int32_t val) | |
360 | { | |
361 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
14ce26e7 | 362 | #ifdef TARGET_X86_64 |
57fec1fe | 363 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); |
14ce26e7 | 364 | #endif |
57fec1fe | 365 | } |
2c0262af | 366 | |
14ce26e7 | 367 | #ifdef TARGET_X86_64 |
57fec1fe FB |
368 | static inline void gen_op_addq_A0_im(int64_t val) |
369 | { | |
370 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
371 | } | |
14ce26e7 | 372 | #endif |
57fec1fe FB |
373 | |
374 | static void gen_add_A0_im(DisasContext *s, int val) | |
375 | { | |
376 | #ifdef TARGET_X86_64 | |
377 | if (CODE64(s)) | |
378 | gen_op_addq_A0_im(val); | |
379 | else | |
380 | #endif | |
381 | gen_op_addl_A0_im(val); | |
382 | } | |
2c0262af | 383 | |
57fec1fe | 384 | static inline void gen_op_addl_T0_T1(void) |
2c0262af | 385 | { |
57fec1fe FB |
386 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
387 | } | |
388 | ||
389 | static inline void gen_op_jmp_T0(void) | |
390 | { | |
391 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip)); | |
392 | } | |
393 | ||
6e0d8677 | 394 | static inline void gen_op_add_reg_im(int size, int reg, int32_t val) |
57fec1fe | 395 | { |
6e0d8677 FB |
396 | switch(size) { |
397 | case 0: | |
cc739bb0 | 398 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
c832e3de | 399 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 FB |
400 | break; |
401 | case 1: | |
cc739bb0 LD |
402 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
403 | /* For x86_64, this sets the higher half of register to zero. | |
404 | For i386, this is equivalent to a nop. */ | |
405 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
406 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 FB |
407 | break; |
408 | #ifdef TARGET_X86_64 | |
409 | case 2: | |
cc739bb0 | 410 | tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val); |
6e0d8677 FB |
411 | break; |
412 | #endif | |
413 | } | |
57fec1fe FB |
414 | } |
415 | ||
6e0d8677 | 416 | static inline void gen_op_add_reg_T0(int size, int reg) |
57fec1fe | 417 | { |
6e0d8677 FB |
418 | switch(size) { |
419 | case 0: | |
cc739bb0 | 420 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
c832e3de | 421 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 FB |
422 | break; |
423 | case 1: | |
cc739bb0 LD |
424 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
425 | /* For x86_64, this sets the higher half of register to zero. | |
426 | For i386, this is equivalent to a nop. */ | |
427 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
428 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 | 429 | break; |
14ce26e7 | 430 | #ifdef TARGET_X86_64 |
6e0d8677 | 431 | case 2: |
cc739bb0 | 432 | tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]); |
6e0d8677 | 433 | break; |
14ce26e7 | 434 | #endif |
6e0d8677 FB |
435 | } |
436 | } | |
57fec1fe FB |
437 | |
438 | static inline void gen_op_set_cc_op(int32_t val) | |
439 | { | |
b6abf97d | 440 | tcg_gen_movi_i32(cpu_cc_op, val); |
57fec1fe FB |
441 | } |
442 | ||
443 | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) | |
444 | { | |
cc739bb0 LD |
445 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
446 | if (shift != 0) | |
57fec1fe FB |
447 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
448 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
cc739bb0 LD |
449 | /* For x86_64, this sets the higher half of register to zero. |
450 | For i386, this is equivalent to a nop. */ | |
451 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
57fec1fe | 452 | } |
2c0262af | 453 | |
57fec1fe FB |
454 | static inline void gen_op_movl_A0_seg(int reg) |
455 | { | |
456 | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET); | |
457 | } | |
2c0262af | 458 | |
57fec1fe FB |
459 | static inline void gen_op_addl_A0_seg(int reg) |
460 | { | |
461 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); | |
462 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
463 | #ifdef TARGET_X86_64 | |
464 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
465 | #endif | |
466 | } | |
2c0262af | 467 | |
14ce26e7 | 468 | #ifdef TARGET_X86_64 |
57fec1fe FB |
469 | static inline void gen_op_movq_A0_seg(int reg) |
470 | { | |
471 | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base)); | |
472 | } | |
14ce26e7 | 473 | |
57fec1fe FB |
474 | static inline void gen_op_addq_A0_seg(int reg) |
475 | { | |
476 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base)); | |
477 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
478 | } | |
479 | ||
480 | static inline void gen_op_movq_A0_reg(int reg) | |
481 | { | |
cc739bb0 | 482 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
483 | } |
484 | ||
485 | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) | |
486 | { | |
cc739bb0 LD |
487 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
488 | if (shift != 0) | |
57fec1fe FB |
489 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
490 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
491 | } | |
14ce26e7 FB |
492 | #endif |
493 | ||
57fec1fe FB |
494 | static inline void gen_op_lds_T0_A0(int idx) |
495 | { | |
496 | int mem_index = (idx >> 2) - 1; | |
497 | switch(idx & 3) { | |
498 | case 0: | |
499 | tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index); | |
500 | break; | |
501 | case 1: | |
502 | tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index); | |
503 | break; | |
504 | default: | |
505 | case 2: | |
506 | tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index); | |
507 | break; | |
508 | } | |
509 | } | |
2c0262af | 510 | |
1e4840bf | 511 | static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) |
57fec1fe FB |
512 | { |
513 | int mem_index = (idx >> 2) - 1; | |
514 | switch(idx & 3) { | |
515 | case 0: | |
1e4840bf | 516 | tcg_gen_qemu_ld8u(t0, a0, mem_index); |
57fec1fe FB |
517 | break; |
518 | case 1: | |
1e4840bf | 519 | tcg_gen_qemu_ld16u(t0, a0, mem_index); |
57fec1fe FB |
520 | break; |
521 | case 2: | |
1e4840bf | 522 | tcg_gen_qemu_ld32u(t0, a0, mem_index); |
57fec1fe FB |
523 | break; |
524 | default: | |
525 | case 3: | |
a7812ae4 PB |
526 | /* Should never happen on 32-bit targets. */ |
527 | #ifdef TARGET_X86_64 | |
1e4840bf | 528 | tcg_gen_qemu_ld64(t0, a0, mem_index); |
a7812ae4 | 529 | #endif |
57fec1fe FB |
530 | break; |
531 | } | |
532 | } | |
2c0262af | 533 | |
1e4840bf FB |
534 | /* XXX: always use ldu or lds */ |
535 | static inline void gen_op_ld_T0_A0(int idx) | |
536 | { | |
537 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); | |
538 | } | |
539 | ||
57fec1fe FB |
540 | static inline void gen_op_ldu_T0_A0(int idx) |
541 | { | |
1e4840bf | 542 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 543 | } |
2c0262af | 544 | |
57fec1fe | 545 | static inline void gen_op_ld_T1_A0(int idx) |
1e4840bf FB |
546 | { |
547 | gen_op_ld_v(idx, cpu_T[1], cpu_A0); | |
548 | } | |
549 | ||
550 | static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) | |
57fec1fe FB |
551 | { |
552 | int mem_index = (idx >> 2) - 1; | |
553 | switch(idx & 3) { | |
554 | case 0: | |
1e4840bf | 555 | tcg_gen_qemu_st8(t0, a0, mem_index); |
57fec1fe FB |
556 | break; |
557 | case 1: | |
1e4840bf | 558 | tcg_gen_qemu_st16(t0, a0, mem_index); |
57fec1fe FB |
559 | break; |
560 | case 2: | |
1e4840bf | 561 | tcg_gen_qemu_st32(t0, a0, mem_index); |
57fec1fe FB |
562 | break; |
563 | default: | |
564 | case 3: | |
a7812ae4 PB |
565 | /* Should never happen on 32-bit targets. */ |
566 | #ifdef TARGET_X86_64 | |
1e4840bf | 567 | tcg_gen_qemu_st64(t0, a0, mem_index); |
a7812ae4 | 568 | #endif |
57fec1fe FB |
569 | break; |
570 | } | |
571 | } | |
4f31916f | 572 | |
57fec1fe FB |
573 | static inline void gen_op_st_T0_A0(int idx) |
574 | { | |
1e4840bf | 575 | gen_op_st_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 576 | } |
4f31916f | 577 | |
57fec1fe FB |
578 | static inline void gen_op_st_T1_A0(int idx) |
579 | { | |
1e4840bf | 580 | gen_op_st_v(idx, cpu_T[1], cpu_A0); |
57fec1fe | 581 | } |
4f31916f | 582 | |
14ce26e7 FB |
583 | static inline void gen_jmp_im(target_ulong pc) |
584 | { | |
57fec1fe FB |
585 | tcg_gen_movi_tl(cpu_tmp0, pc); |
586 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip)); | |
14ce26e7 FB |
587 | } |
588 | ||
2c0262af FB |
589 | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
590 | { | |
591 | int override; | |
592 | ||
593 | override = s->override; | |
14ce26e7 FB |
594 | #ifdef TARGET_X86_64 |
595 | if (s->aflag == 2) { | |
596 | if (override >= 0) { | |
57fec1fe FB |
597 | gen_op_movq_A0_seg(override); |
598 | gen_op_addq_A0_reg_sN(0, R_ESI); | |
14ce26e7 | 599 | } else { |
57fec1fe | 600 | gen_op_movq_A0_reg(R_ESI); |
14ce26e7 FB |
601 | } |
602 | } else | |
603 | #endif | |
2c0262af FB |
604 | if (s->aflag) { |
605 | /* 32 bit address */ | |
606 | if (s->addseg && override < 0) | |
607 | override = R_DS; | |
608 | if (override >= 0) { | |
57fec1fe FB |
609 | gen_op_movl_A0_seg(override); |
610 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af | 611 | } else { |
57fec1fe | 612 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
613 | } |
614 | } else { | |
615 | /* 16 address, always override */ | |
616 | if (override < 0) | |
617 | override = R_DS; | |
57fec1fe | 618 | gen_op_movl_A0_reg(R_ESI); |
2c0262af | 619 | gen_op_andl_A0_ffff(); |
57fec1fe | 620 | gen_op_addl_A0_seg(override); |
2c0262af FB |
621 | } |
622 | } | |
623 | ||
624 | static inline void gen_string_movl_A0_EDI(DisasContext *s) | |
625 | { | |
14ce26e7 FB |
626 | #ifdef TARGET_X86_64 |
627 | if (s->aflag == 2) { | |
57fec1fe | 628 | gen_op_movq_A0_reg(R_EDI); |
14ce26e7 FB |
629 | } else |
630 | #endif | |
2c0262af FB |
631 | if (s->aflag) { |
632 | if (s->addseg) { | |
57fec1fe FB |
633 | gen_op_movl_A0_seg(R_ES); |
634 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af | 635 | } else { |
57fec1fe | 636 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
637 | } |
638 | } else { | |
57fec1fe | 639 | gen_op_movl_A0_reg(R_EDI); |
2c0262af | 640 | gen_op_andl_A0_ffff(); |
57fec1fe | 641 | gen_op_addl_A0_seg(R_ES); |
2c0262af FB |
642 | } |
643 | } | |
644 | ||
6e0d8677 FB |
645 | static inline void gen_op_movl_T0_Dshift(int ot) |
646 | { | |
647 | tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df)); | |
648 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); | |
2c0262af FB |
649 | }; |
650 | ||
6e0d8677 FB |
651 | static void gen_extu(int ot, TCGv reg) |
652 | { | |
653 | switch(ot) { | |
654 | case OT_BYTE: | |
655 | tcg_gen_ext8u_tl(reg, reg); | |
656 | break; | |
657 | case OT_WORD: | |
658 | tcg_gen_ext16u_tl(reg, reg); | |
659 | break; | |
660 | case OT_LONG: | |
661 | tcg_gen_ext32u_tl(reg, reg); | |
662 | break; | |
663 | default: | |
664 | break; | |
665 | } | |
666 | } | |
3b46e624 | 667 | |
6e0d8677 FB |
668 | static void gen_exts(int ot, TCGv reg) |
669 | { | |
670 | switch(ot) { | |
671 | case OT_BYTE: | |
672 | tcg_gen_ext8s_tl(reg, reg); | |
673 | break; | |
674 | case OT_WORD: | |
675 | tcg_gen_ext16s_tl(reg, reg); | |
676 | break; | |
677 | case OT_LONG: | |
678 | tcg_gen_ext32s_tl(reg, reg); | |
679 | break; | |
680 | default: | |
681 | break; | |
682 | } | |
683 | } | |
2c0262af | 684 | |
6e0d8677 FB |
685 | static inline void gen_op_jnz_ecx(int size, int label1) |
686 | { | |
cc739bb0 | 687 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 688 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 689 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); |
6e0d8677 FB |
690 | } |
691 | ||
692 | static inline void gen_op_jz_ecx(int size, int label1) | |
693 | { | |
cc739bb0 | 694 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 695 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 696 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
6e0d8677 | 697 | } |
2c0262af | 698 | |
a7812ae4 PB |
699 | static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n) |
700 | { | |
701 | switch (ot) { | |
702 | case 0: gen_helper_inb(v, n); break; | |
703 | case 1: gen_helper_inw(v, n); break; | |
704 | case 2: gen_helper_inl(v, n); break; | |
705 | } | |
2c0262af | 706 | |
a7812ae4 | 707 | } |
2c0262af | 708 | |
a7812ae4 PB |
709 | static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n) |
710 | { | |
711 | switch (ot) { | |
712 | case 0: gen_helper_outb(v, n); break; | |
713 | case 1: gen_helper_outw(v, n); break; | |
714 | case 2: gen_helper_outl(v, n); break; | |
715 | } | |
716 | ||
717 | } | |
f115e911 | 718 | |
b8b6a50b FB |
719 | static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, |
720 | uint32_t svm_flags) | |
f115e911 | 721 | { |
b8b6a50b FB |
722 | int state_saved; |
723 | target_ulong next_eip; | |
724 | ||
725 | state_saved = 0; | |
f115e911 FB |
726 | if (s->pe && (s->cpl > s->iopl || s->vm86)) { |
727 | if (s->cc_op != CC_OP_DYNAMIC) | |
728 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 729 | gen_jmp_im(cur_eip); |
b8b6a50b | 730 | state_saved = 1; |
b6abf97d | 731 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
732 | switch (ot) { |
733 | case 0: gen_helper_check_iob(cpu_tmp2_i32); break; | |
734 | case 1: gen_helper_check_iow(cpu_tmp2_i32); break; | |
735 | case 2: gen_helper_check_iol(cpu_tmp2_i32); break; | |
736 | } | |
b8b6a50b | 737 | } |
872929aa | 738 | if(s->flags & HF_SVMI_MASK) { |
b8b6a50b FB |
739 | if (!state_saved) { |
740 | if (s->cc_op != CC_OP_DYNAMIC) | |
741 | gen_op_set_cc_op(s->cc_op); | |
742 | gen_jmp_im(cur_eip); | |
b8b6a50b FB |
743 | } |
744 | svm_flags |= (1 << (4 + ot)); | |
745 | next_eip = s->pc - s->cs_base; | |
b6abf97d | 746 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
747 | gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags), |
748 | tcg_const_i32(next_eip - cur_eip)); | |
f115e911 FB |
749 | } |
750 | } | |
751 | ||
2c0262af FB |
752 | static inline void gen_movs(DisasContext *s, int ot) |
753 | { | |
754 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 755 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 756 | gen_string_movl_A0_EDI(s); |
57fec1fe | 757 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
758 | gen_op_movl_T0_Dshift(ot); |
759 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
760 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
761 | } |
762 | ||
763 | static inline void gen_update_cc_op(DisasContext *s) | |
764 | { | |
765 | if (s->cc_op != CC_OP_DYNAMIC) { | |
766 | gen_op_set_cc_op(s->cc_op); | |
767 | s->cc_op = CC_OP_DYNAMIC; | |
768 | } | |
769 | } | |
770 | ||
b6abf97d FB |
771 | static void gen_op_update1_cc(void) |
772 | { | |
773 | tcg_gen_discard_tl(cpu_cc_src); | |
774 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
775 | } | |
776 | ||
777 | static void gen_op_update2_cc(void) | |
778 | { | |
779 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
780 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
781 | } | |
782 | ||
783 | static inline void gen_op_cmpl_T0_T1_cc(void) | |
784 | { | |
785 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
786 | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
787 | } | |
788 | ||
789 | static inline void gen_op_testl_T0_T1_cc(void) | |
790 | { | |
791 | tcg_gen_discard_tl(cpu_cc_src); | |
792 | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
793 | } | |
794 | ||
795 | static void gen_op_update_neg_cc(void) | |
796 | { | |
797 | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]); | |
798 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
799 | } | |
800 | ||
8e1c85e3 FB |
801 | /* compute eflags.C to reg */ |
802 | static void gen_compute_eflags_c(TCGv reg) | |
803 | { | |
a7812ae4 | 804 | gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op); |
8e1c85e3 FB |
805 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
806 | } | |
807 | ||
808 | /* compute all eflags to cc_src */ | |
809 | static void gen_compute_eflags(TCGv reg) | |
810 | { | |
a7812ae4 | 811 | gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op); |
8e1c85e3 FB |
812 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
813 | } | |
814 | ||
1e4840bf | 815 | static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) |
8e1c85e3 | 816 | { |
1e4840bf FB |
817 | if (s->cc_op != CC_OP_DYNAMIC) |
818 | gen_op_set_cc_op(s->cc_op); | |
819 | switch(jcc_op) { | |
8e1c85e3 FB |
820 | case JCC_O: |
821 | gen_compute_eflags(cpu_T[0]); | |
822 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11); | |
823 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
824 | break; | |
825 | case JCC_B: | |
826 | gen_compute_eflags_c(cpu_T[0]); | |
827 | break; | |
828 | case JCC_Z: | |
829 | gen_compute_eflags(cpu_T[0]); | |
830 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6); | |
831 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
832 | break; | |
833 | case JCC_BE: | |
834 | gen_compute_eflags(cpu_tmp0); | |
835 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6); | |
836 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
837 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
838 | break; | |
839 | case JCC_S: | |
840 | gen_compute_eflags(cpu_T[0]); | |
841 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7); | |
842 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
843 | break; | |
844 | case JCC_P: | |
845 | gen_compute_eflags(cpu_T[0]); | |
846 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2); | |
847 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
848 | break; | |
849 | case JCC_L: | |
850 | gen_compute_eflags(cpu_tmp0); | |
851 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ | |
852 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */ | |
853 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
854 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
855 | break; | |
856 | default: | |
857 | case JCC_LE: | |
858 | gen_compute_eflags(cpu_tmp0); | |
859 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ | |
860 | tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */ | |
861 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */ | |
862 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
863 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
864 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
865 | break; | |
866 | } | |
867 | } | |
868 | ||
869 | /* return true if setcc_slow is not needed (WARNING: must be kept in | |
870 | sync with gen_jcc1) */ | |
871 | static int is_fast_jcc_case(DisasContext *s, int b) | |
872 | { | |
873 | int jcc_op; | |
874 | jcc_op = (b >> 1) & 7; | |
875 | switch(s->cc_op) { | |
876 | /* we optimize the cmp/jcc case */ | |
877 | case CC_OP_SUBB: | |
878 | case CC_OP_SUBW: | |
879 | case CC_OP_SUBL: | |
880 | case CC_OP_SUBQ: | |
881 | if (jcc_op == JCC_O || jcc_op == JCC_P) | |
882 | goto slow_jcc; | |
883 | break; | |
884 | ||
885 | /* some jumps are easy to compute */ | |
886 | case CC_OP_ADDB: | |
887 | case CC_OP_ADDW: | |
888 | case CC_OP_ADDL: | |
889 | case CC_OP_ADDQ: | |
890 | ||
891 | case CC_OP_LOGICB: | |
892 | case CC_OP_LOGICW: | |
893 | case CC_OP_LOGICL: | |
894 | case CC_OP_LOGICQ: | |
895 | ||
896 | case CC_OP_INCB: | |
897 | case CC_OP_INCW: | |
898 | case CC_OP_INCL: | |
899 | case CC_OP_INCQ: | |
900 | ||
901 | case CC_OP_DECB: | |
902 | case CC_OP_DECW: | |
903 | case CC_OP_DECL: | |
904 | case CC_OP_DECQ: | |
905 | ||
906 | case CC_OP_SHLB: | |
907 | case CC_OP_SHLW: | |
908 | case CC_OP_SHLL: | |
909 | case CC_OP_SHLQ: | |
910 | if (jcc_op != JCC_Z && jcc_op != JCC_S) | |
911 | goto slow_jcc; | |
912 | break; | |
913 | default: | |
914 | slow_jcc: | |
915 | return 0; | |
916 | } | |
917 | return 1; | |
918 | } | |
919 | ||
920 | /* generate a conditional jump to label 'l1' according to jump opcode | |
921 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
922 | static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1) | |
923 | { | |
924 | int inv, jcc_op, size, cond; | |
925 | TCGv t0; | |
926 | ||
927 | inv = b & 1; | |
928 | jcc_op = (b >> 1) & 7; | |
929 | ||
930 | switch(cc_op) { | |
931 | /* we optimize the cmp/jcc case */ | |
932 | case CC_OP_SUBB: | |
933 | case CC_OP_SUBW: | |
934 | case CC_OP_SUBL: | |
935 | case CC_OP_SUBQ: | |
936 | ||
937 | size = cc_op - CC_OP_SUBB; | |
938 | switch(jcc_op) { | |
939 | case JCC_Z: | |
940 | fast_jcc_z: | |
941 | switch(size) { | |
942 | case 0: | |
943 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff); | |
944 | t0 = cpu_tmp0; | |
945 | break; | |
946 | case 1: | |
947 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff); | |
948 | t0 = cpu_tmp0; | |
949 | break; | |
950 | #ifdef TARGET_X86_64 | |
951 | case 2: | |
952 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff); | |
953 | t0 = cpu_tmp0; | |
954 | break; | |
955 | #endif | |
956 | default: | |
957 | t0 = cpu_cc_dst; | |
958 | break; | |
959 | } | |
cb63669a | 960 | tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1); |
8e1c85e3 FB |
961 | break; |
962 | case JCC_S: | |
963 | fast_jcc_s: | |
964 | switch(size) { | |
965 | case 0: | |
966 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80); | |
cb63669a PB |
967 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
968 | 0, l1); | |
8e1c85e3 FB |
969 | break; |
970 | case 1: | |
971 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000); | |
cb63669a PB |
972 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
973 | 0, l1); | |
8e1c85e3 FB |
974 | break; |
975 | #ifdef TARGET_X86_64 | |
976 | case 2: | |
977 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000); | |
cb63669a PB |
978 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
979 | 0, l1); | |
8e1c85e3 FB |
980 | break; |
981 | #endif | |
982 | default: | |
cb63669a PB |
983 | tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, |
984 | 0, l1); | |
8e1c85e3 FB |
985 | break; |
986 | } | |
987 | break; | |
988 | ||
989 | case JCC_B: | |
990 | cond = inv ? TCG_COND_GEU : TCG_COND_LTU; | |
991 | goto fast_jcc_b; | |
992 | case JCC_BE: | |
993 | cond = inv ? TCG_COND_GTU : TCG_COND_LEU; | |
994 | fast_jcc_b: | |
995 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
996 | switch(size) { | |
997 | case 0: | |
998 | t0 = cpu_tmp0; | |
999 | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff); | |
1000 | tcg_gen_andi_tl(t0, cpu_cc_src, 0xff); | |
1001 | break; | |
1002 | case 1: | |
1003 | t0 = cpu_tmp0; | |
1004 | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff); | |
1005 | tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff); | |
1006 | break; | |
1007 | #ifdef TARGET_X86_64 | |
1008 | case 2: | |
1009 | t0 = cpu_tmp0; | |
1010 | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff); | |
1011 | tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff); | |
1012 | break; | |
1013 | #endif | |
1014 | default: | |
1015 | t0 = cpu_cc_src; | |
1016 | break; | |
1017 | } | |
1018 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); | |
1019 | break; | |
1020 | ||
1021 | case JCC_L: | |
1022 | cond = inv ? TCG_COND_GE : TCG_COND_LT; | |
1023 | goto fast_jcc_l; | |
1024 | case JCC_LE: | |
1025 | cond = inv ? TCG_COND_GT : TCG_COND_LE; | |
1026 | fast_jcc_l: | |
1027 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
1028 | switch(size) { | |
1029 | case 0: | |
1030 | t0 = cpu_tmp0; | |
1031 | tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4); | |
1032 | tcg_gen_ext8s_tl(t0, cpu_cc_src); | |
1033 | break; | |
1034 | case 1: | |
1035 | t0 = cpu_tmp0; | |
1036 | tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4); | |
1037 | tcg_gen_ext16s_tl(t0, cpu_cc_src); | |
1038 | break; | |
1039 | #ifdef TARGET_X86_64 | |
1040 | case 2: | |
1041 | t0 = cpu_tmp0; | |
1042 | tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4); | |
1043 | tcg_gen_ext32s_tl(t0, cpu_cc_src); | |
1044 | break; | |
1045 | #endif | |
1046 | default: | |
1047 | t0 = cpu_cc_src; | |
1048 | break; | |
1049 | } | |
1050 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); | |
1051 | break; | |
1052 | ||
1053 | default: | |
1054 | goto slow_jcc; | |
1055 | } | |
1056 | break; | |
1057 | ||
1058 | /* some jumps are easy to compute */ | |
1059 | case CC_OP_ADDB: | |
1060 | case CC_OP_ADDW: | |
1061 | case CC_OP_ADDL: | |
1062 | case CC_OP_ADDQ: | |
1063 | ||
1064 | case CC_OP_ADCB: | |
1065 | case CC_OP_ADCW: | |
1066 | case CC_OP_ADCL: | |
1067 | case CC_OP_ADCQ: | |
1068 | ||
1069 | case CC_OP_SBBB: | |
1070 | case CC_OP_SBBW: | |
1071 | case CC_OP_SBBL: | |
1072 | case CC_OP_SBBQ: | |
1073 | ||
1074 | case CC_OP_LOGICB: | |
1075 | case CC_OP_LOGICW: | |
1076 | case CC_OP_LOGICL: | |
1077 | case CC_OP_LOGICQ: | |
1078 | ||
1079 | case CC_OP_INCB: | |
1080 | case CC_OP_INCW: | |
1081 | case CC_OP_INCL: | |
1082 | case CC_OP_INCQ: | |
1083 | ||
1084 | case CC_OP_DECB: | |
1085 | case CC_OP_DECW: | |
1086 | case CC_OP_DECL: | |
1087 | case CC_OP_DECQ: | |
1088 | ||
1089 | case CC_OP_SHLB: | |
1090 | case CC_OP_SHLW: | |
1091 | case CC_OP_SHLL: | |
1092 | case CC_OP_SHLQ: | |
1093 | ||
1094 | case CC_OP_SARB: | |
1095 | case CC_OP_SARW: | |
1096 | case CC_OP_SARL: | |
1097 | case CC_OP_SARQ: | |
1098 | switch(jcc_op) { | |
1099 | case JCC_Z: | |
1100 | size = (cc_op - CC_OP_ADDB) & 3; | |
1101 | goto fast_jcc_z; | |
1102 | case JCC_S: | |
1103 | size = (cc_op - CC_OP_ADDB) & 3; | |
1104 | goto fast_jcc_s; | |
1105 | default: | |
1106 | goto slow_jcc; | |
1107 | } | |
1108 | break; | |
1109 | default: | |
1110 | slow_jcc: | |
1e4840bf | 1111 | gen_setcc_slow_T0(s, jcc_op); |
cb63669a PB |
1112 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, |
1113 | cpu_T[0], 0, l1); | |
8e1c85e3 FB |
1114 | break; |
1115 | } | |
1116 | } | |
1117 | ||
14ce26e7 FB |
1118 | /* XXX: does not work with gdbstub "ice" single step - not a |
1119 | serious problem */ | |
1120 | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) | |
2c0262af | 1121 | { |
14ce26e7 FB |
1122 | int l1, l2; |
1123 | ||
1124 | l1 = gen_new_label(); | |
1125 | l2 = gen_new_label(); | |
6e0d8677 | 1126 | gen_op_jnz_ecx(s->aflag, l1); |
14ce26e7 FB |
1127 | gen_set_label(l2); |
1128 | gen_jmp_tb(s, next_eip, 1); | |
1129 | gen_set_label(l1); | |
1130 | return l2; | |
2c0262af FB |
1131 | } |
1132 | ||
1133 | static inline void gen_stos(DisasContext *s, int ot) | |
1134 | { | |
57fec1fe | 1135 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1136 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1137 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1138 | gen_op_movl_T0_Dshift(ot); |
1139 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1140 | } |
1141 | ||
1142 | static inline void gen_lods(DisasContext *s, int ot) | |
1143 | { | |
1144 | gen_string_movl_A0_ESI(s); | |
57fec1fe FB |
1145 | gen_op_ld_T0_A0(ot + s->mem_index); |
1146 | gen_op_mov_reg_T0(ot, R_EAX); | |
6e0d8677 FB |
1147 | gen_op_movl_T0_Dshift(ot); |
1148 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2c0262af FB |
1149 | } |
1150 | ||
1151 | static inline void gen_scas(DisasContext *s, int ot) | |
1152 | { | |
57fec1fe | 1153 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1154 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1155 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1156 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1157 | gen_op_movl_T0_Dshift(ot); |
1158 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1159 | } |
1160 | ||
1161 | static inline void gen_cmps(DisasContext *s, int ot) | |
1162 | { | |
1163 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 1164 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 1165 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1166 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1167 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1168 | gen_op_movl_T0_Dshift(ot); |
1169 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
1170 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1171 | } |
1172 | ||
1173 | static inline void gen_ins(DisasContext *s, int ot) | |
1174 | { | |
2e70f6ef PB |
1175 | if (use_icount) |
1176 | gen_io_start(); | |
2c0262af | 1177 | gen_string_movl_A0_EDI(s); |
6e0d8677 FB |
1178 | /* Note: we must do this dummy write first to be restartable in |
1179 | case of page fault. */ | |
9772c73b | 1180 | gen_op_movl_T0_0(); |
57fec1fe | 1181 | gen_op_st_T0_A0(ot + s->mem_index); |
b8b6a50b | 1182 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); |
b6abf97d FB |
1183 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1184 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
a7812ae4 | 1185 | gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 1186 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1187 | gen_op_movl_T0_Dshift(ot); |
1188 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2e70f6ef PB |
1189 | if (use_icount) |
1190 | gen_io_end(); | |
2c0262af FB |
1191 | } |
1192 | ||
1193 | static inline void gen_outs(DisasContext *s, int ot) | |
1194 | { | |
2e70f6ef PB |
1195 | if (use_icount) |
1196 | gen_io_start(); | |
2c0262af | 1197 | gen_string_movl_A0_ESI(s); |
57fec1fe | 1198 | gen_op_ld_T0_A0(ot + s->mem_index); |
b8b6a50b FB |
1199 | |
1200 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); | |
b6abf97d FB |
1201 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1202 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
1203 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); | |
a7812ae4 | 1204 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
b8b6a50b | 1205 | |
6e0d8677 FB |
1206 | gen_op_movl_T0_Dshift(ot); |
1207 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2e70f6ef PB |
1208 | if (use_icount) |
1209 | gen_io_end(); | |
2c0262af FB |
1210 | } |
1211 | ||
1212 | /* same method as Valgrind : we generate jumps to current or next | |
1213 | instruction */ | |
1214 | #define GEN_REPZ(op) \ | |
1215 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 | 1216 | target_ulong cur_eip, target_ulong next_eip) \ |
2c0262af | 1217 | { \ |
14ce26e7 | 1218 | int l2;\ |
2c0262af | 1219 | gen_update_cc_op(s); \ |
14ce26e7 | 1220 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1221 | gen_ ## op(s, ot); \ |
6e0d8677 | 1222 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af FB |
1223 | /* a loop would cause two single step exceptions if ECX = 1 \ |
1224 | before rep string_insn */ \ | |
1225 | if (!s->jmp_opt) \ | |
6e0d8677 | 1226 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1227 | gen_jmp(s, cur_eip); \ |
1228 | } | |
1229 | ||
1230 | #define GEN_REPZ2(op) \ | |
1231 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 FB |
1232 | target_ulong cur_eip, \ |
1233 | target_ulong next_eip, \ | |
2c0262af FB |
1234 | int nz) \ |
1235 | { \ | |
14ce26e7 | 1236 | int l2;\ |
2c0262af | 1237 | gen_update_cc_op(s); \ |
14ce26e7 | 1238 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1239 | gen_ ## op(s, ot); \ |
6e0d8677 | 1240 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af | 1241 | gen_op_set_cc_op(CC_OP_SUBB + ot); \ |
8e1c85e3 | 1242 | gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \ |
2c0262af | 1243 | if (!s->jmp_opt) \ |
6e0d8677 | 1244 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1245 | gen_jmp(s, cur_eip); \ |
1246 | } | |
1247 | ||
1248 | GEN_REPZ(movs) | |
1249 | GEN_REPZ(stos) | |
1250 | GEN_REPZ(lods) | |
1251 | GEN_REPZ(ins) | |
1252 | GEN_REPZ(outs) | |
1253 | GEN_REPZ2(scas) | |
1254 | GEN_REPZ2(cmps) | |
1255 | ||
a7812ae4 PB |
1256 | static void gen_helper_fp_arith_ST0_FT0(int op) |
1257 | { | |
1258 | switch (op) { | |
1259 | case 0: gen_helper_fadd_ST0_FT0(); break; | |
1260 | case 1: gen_helper_fmul_ST0_FT0(); break; | |
1261 | case 2: gen_helper_fcom_ST0_FT0(); break; | |
1262 | case 3: gen_helper_fcom_ST0_FT0(); break; | |
1263 | case 4: gen_helper_fsub_ST0_FT0(); break; | |
1264 | case 5: gen_helper_fsubr_ST0_FT0(); break; | |
1265 | case 6: gen_helper_fdiv_ST0_FT0(); break; | |
1266 | case 7: gen_helper_fdivr_ST0_FT0(); break; | |
1267 | } | |
1268 | } | |
2c0262af FB |
1269 | |
1270 | /* NOTE the exception in "r" op ordering */ | |
a7812ae4 PB |
1271 | static void gen_helper_fp_arith_STN_ST0(int op, int opreg) |
1272 | { | |
1273 | TCGv_i32 tmp = tcg_const_i32(opreg); | |
1274 | switch (op) { | |
1275 | case 0: gen_helper_fadd_STN_ST0(tmp); break; | |
1276 | case 1: gen_helper_fmul_STN_ST0(tmp); break; | |
1277 | case 4: gen_helper_fsubr_STN_ST0(tmp); break; | |
1278 | case 5: gen_helper_fsub_STN_ST0(tmp); break; | |
1279 | case 6: gen_helper_fdivr_STN_ST0(tmp); break; | |
1280 | case 7: gen_helper_fdiv_STN_ST0(tmp); break; | |
1281 | } | |
1282 | } | |
2c0262af FB |
1283 | |
1284 | /* if d == OR_TMP0, it means memory operand (address in A0) */ | |
1285 | static void gen_op(DisasContext *s1, int op, int ot, int d) | |
1286 | { | |
2c0262af | 1287 | if (d != OR_TMP0) { |
57fec1fe | 1288 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1289 | } else { |
57fec1fe | 1290 | gen_op_ld_T0_A0(ot + s1->mem_index); |
2c0262af FB |
1291 | } |
1292 | switch(op) { | |
1293 | case OP_ADCL: | |
cad3a37d FB |
1294 | if (s1->cc_op != CC_OP_DYNAMIC) |
1295 | gen_op_set_cc_op(s1->cc_op); | |
1296 | gen_compute_eflags_c(cpu_tmp4); | |
1297 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1298 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1299 | if (d != OR_TMP0) | |
1300 | gen_op_mov_reg_T0(ot, d); | |
1301 | else | |
1302 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1303 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1304 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1305 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1306 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1307 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot); | |
1308 | s1->cc_op = CC_OP_DYNAMIC; | |
1309 | break; | |
2c0262af FB |
1310 | case OP_SBBL: |
1311 | if (s1->cc_op != CC_OP_DYNAMIC) | |
1312 | gen_op_set_cc_op(s1->cc_op); | |
cad3a37d FB |
1313 | gen_compute_eflags_c(cpu_tmp4); |
1314 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1315 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1316 | if (d != OR_TMP0) | |
57fec1fe | 1317 | gen_op_mov_reg_T0(ot, d); |
cad3a37d FB |
1318 | else |
1319 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1320 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1321 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1322 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1323 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1324 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot); | |
2c0262af | 1325 | s1->cc_op = CC_OP_DYNAMIC; |
cad3a37d | 1326 | break; |
2c0262af FB |
1327 | case OP_ADDL: |
1328 | gen_op_addl_T0_T1(); | |
cad3a37d FB |
1329 | if (d != OR_TMP0) |
1330 | gen_op_mov_reg_T0(ot, d); | |
1331 | else | |
1332 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1333 | gen_op_update2_cc(); | |
2c0262af | 1334 | s1->cc_op = CC_OP_ADDB + ot; |
2c0262af FB |
1335 | break; |
1336 | case OP_SUBL: | |
57fec1fe | 1337 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1338 | if (d != OR_TMP0) |
1339 | gen_op_mov_reg_T0(ot, d); | |
1340 | else | |
1341 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1342 | gen_op_update2_cc(); | |
2c0262af | 1343 | s1->cc_op = CC_OP_SUBB + ot; |
2c0262af FB |
1344 | break; |
1345 | default: | |
1346 | case OP_ANDL: | |
57fec1fe | 1347 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1348 | if (d != OR_TMP0) |
1349 | gen_op_mov_reg_T0(ot, d); | |
1350 | else | |
1351 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1352 | gen_op_update1_cc(); | |
57fec1fe | 1353 | s1->cc_op = CC_OP_LOGICB + ot; |
57fec1fe | 1354 | break; |
2c0262af | 1355 | case OP_ORL: |
57fec1fe | 1356 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1357 | if (d != OR_TMP0) |
1358 | gen_op_mov_reg_T0(ot, d); | |
1359 | else | |
1360 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1361 | gen_op_update1_cc(); | |
57fec1fe | 1362 | s1->cc_op = CC_OP_LOGICB + ot; |
57fec1fe | 1363 | break; |
2c0262af | 1364 | case OP_XORL: |
57fec1fe | 1365 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1366 | if (d != OR_TMP0) |
1367 | gen_op_mov_reg_T0(ot, d); | |
1368 | else | |
1369 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1370 | gen_op_update1_cc(); | |
2c0262af | 1371 | s1->cc_op = CC_OP_LOGICB + ot; |
2c0262af FB |
1372 | break; |
1373 | case OP_CMPL: | |
1374 | gen_op_cmpl_T0_T1_cc(); | |
1375 | s1->cc_op = CC_OP_SUBB + ot; | |
2c0262af FB |
1376 | break; |
1377 | } | |
b6abf97d FB |
1378 | } |
1379 | ||
2c0262af FB |
1380 | /* if d == OR_TMP0, it means memory operand (address in A0) */ |
1381 | static void gen_inc(DisasContext *s1, int ot, int d, int c) | |
1382 | { | |
1383 | if (d != OR_TMP0) | |
57fec1fe | 1384 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1385 | else |
57fec1fe | 1386 | gen_op_ld_T0_A0(ot + s1->mem_index); |
2c0262af FB |
1387 | if (s1->cc_op != CC_OP_DYNAMIC) |
1388 | gen_op_set_cc_op(s1->cc_op); | |
1389 | if (c > 0) { | |
b6abf97d | 1390 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
2c0262af FB |
1391 | s1->cc_op = CC_OP_INCB + ot; |
1392 | } else { | |
b6abf97d | 1393 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
2c0262af FB |
1394 | s1->cc_op = CC_OP_DECB + ot; |
1395 | } | |
1396 | if (d != OR_TMP0) | |
57fec1fe | 1397 | gen_op_mov_reg_T0(ot, d); |
2c0262af | 1398 | else |
57fec1fe | 1399 | gen_op_st_T0_A0(ot + s1->mem_index); |
b6abf97d | 1400 | gen_compute_eflags_c(cpu_cc_src); |
cd31fefa | 1401 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
2c0262af FB |
1402 | } |
1403 | ||
b6abf97d FB |
1404 | static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
1405 | int is_right, int is_arith) | |
2c0262af | 1406 | { |
b6abf97d FB |
1407 | target_ulong mask; |
1408 | int shift_label; | |
82786041 | 1409 | TCGv t0, t1, t2; |
1e4840bf | 1410 | |
82786041 | 1411 | if (ot == OT_QUAD) { |
b6abf97d | 1412 | mask = 0x3f; |
82786041 | 1413 | } else { |
b6abf97d | 1414 | mask = 0x1f; |
82786041 | 1415 | } |
3b46e624 | 1416 | |
b6abf97d | 1417 | /* load */ |
82786041 | 1418 | if (op1 == OR_TMP0) { |
b6abf97d | 1419 | gen_op_ld_T0_A0(ot + s->mem_index); |
82786041 | 1420 | } else { |
b6abf97d | 1421 | gen_op_mov_TN_reg(ot, 0, op1); |
82786041 | 1422 | } |
b6abf97d | 1423 | |
82786041 RH |
1424 | t0 = tcg_temp_local_new(); |
1425 | t1 = tcg_temp_local_new(); | |
1426 | t2 = tcg_temp_local_new(); | |
b6abf97d | 1427 | |
82786041 | 1428 | tcg_gen_andi_tl(t2, cpu_T[1], mask); |
b6abf97d FB |
1429 | |
1430 | if (is_right) { | |
1431 | if (is_arith) { | |
f484d386 | 1432 | gen_exts(ot, cpu_T[0]); |
82786041 RH |
1433 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1434 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d | 1435 | } else { |
cad3a37d | 1436 | gen_extu(ot, cpu_T[0]); |
82786041 RH |
1437 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1438 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1439 | } |
1440 | } else { | |
82786041 RH |
1441 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1442 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1443 | } |
1444 | ||
1445 | /* store */ | |
82786041 | 1446 | if (op1 == OR_TMP0) { |
b6abf97d | 1447 | gen_op_st_T0_A0(ot + s->mem_index); |
82786041 | 1448 | } else { |
b6abf97d | 1449 | gen_op_mov_reg_T0(ot, op1); |
82786041 RH |
1450 | } |
1451 | ||
b6abf97d | 1452 | /* update eflags if non zero shift */ |
82786041 | 1453 | if (s->cc_op != CC_OP_DYNAMIC) { |
b6abf97d | 1454 | gen_op_set_cc_op(s->cc_op); |
82786041 | 1455 | } |
b6abf97d | 1456 | |
82786041 | 1457 | tcg_gen_mov_tl(t1, cpu_T[0]); |
1e4840bf | 1458 | |
b6abf97d | 1459 | shift_label = gen_new_label(); |
82786041 RH |
1460 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label); |
1461 | ||
1462 | tcg_gen_addi_tl(t2, t2, -1); | |
1463 | tcg_gen_mov_tl(cpu_cc_dst, t1); | |
1464 | ||
1465 | if (is_right) { | |
1466 | if (is_arith) { | |
1467 | tcg_gen_sar_tl(cpu_cc_src, t0, t2); | |
1468 | } else { | |
1469 | tcg_gen_shr_tl(cpu_cc_src, t0, t2); | |
1470 | } | |
1471 | } else { | |
1472 | tcg_gen_shl_tl(cpu_cc_src, t0, t2); | |
1473 | } | |
b6abf97d | 1474 | |
82786041 | 1475 | if (is_right) { |
b6abf97d | 1476 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
82786041 | 1477 | } else { |
b6abf97d | 1478 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
82786041 RH |
1479 | } |
1480 | ||
b6abf97d FB |
1481 | gen_set_label(shift_label); |
1482 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1e4840bf FB |
1483 | |
1484 | tcg_temp_free(t0); | |
1485 | tcg_temp_free(t1); | |
82786041 | 1486 | tcg_temp_free(t2); |
b6abf97d FB |
1487 | } |
1488 | ||
c1c37968 FB |
1489 | static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, |
1490 | int is_right, int is_arith) | |
1491 | { | |
1492 | int mask; | |
1493 | ||
1494 | if (ot == OT_QUAD) | |
1495 | mask = 0x3f; | |
1496 | else | |
1497 | mask = 0x1f; | |
1498 | ||
1499 | /* load */ | |
1500 | if (op1 == OR_TMP0) | |
1501 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1502 | else | |
1503 | gen_op_mov_TN_reg(ot, 0, op1); | |
1504 | ||
1505 | op2 &= mask; | |
1506 | if (op2 != 0) { | |
1507 | if (is_right) { | |
1508 | if (is_arith) { | |
1509 | gen_exts(ot, cpu_T[0]); | |
2a449d14 | 1510 | tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1511 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
1512 | } else { | |
1513 | gen_extu(ot, cpu_T[0]); | |
2a449d14 | 1514 | tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1515 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
1516 | } | |
1517 | } else { | |
2a449d14 | 1518 | tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1519 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
1520 | } | |
1521 | } | |
1522 | ||
1523 | /* store */ | |
1524 | if (op1 == OR_TMP0) | |
1525 | gen_op_st_T0_A0(ot + s->mem_index); | |
1526 | else | |
1527 | gen_op_mov_reg_T0(ot, op1); | |
1528 | ||
1529 | /* update eflags if non zero shift */ | |
1530 | if (op2 != 0) { | |
2a449d14 | 1531 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
c1c37968 FB |
1532 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
1533 | if (is_right) | |
1534 | s->cc_op = CC_OP_SARB + ot; | |
1535 | else | |
1536 | s->cc_op = CC_OP_SHLB + ot; | |
1537 | } | |
1538 | } | |
1539 | ||
b6abf97d FB |
1540 | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1541 | { | |
1542 | if (arg2 >= 0) | |
1543 | tcg_gen_shli_tl(ret, arg1, arg2); | |
1544 | else | |
1545 | tcg_gen_shri_tl(ret, arg1, -arg2); | |
1546 | } | |
1547 | ||
b6abf97d FB |
1548 | static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, |
1549 | int is_right) | |
1550 | { | |
1551 | target_ulong mask; | |
1552 | int label1, label2, data_bits; | |
1e4840bf FB |
1553 | TCGv t0, t1, t2, a0; |
1554 | ||
1555 | /* XXX: inefficient, but we must use local temps */ | |
a7812ae4 PB |
1556 | t0 = tcg_temp_local_new(); |
1557 | t1 = tcg_temp_local_new(); | |
1558 | t2 = tcg_temp_local_new(); | |
1559 | a0 = tcg_temp_local_new(); | |
1e4840bf | 1560 | |
b6abf97d FB |
1561 | if (ot == OT_QUAD) |
1562 | mask = 0x3f; | |
1563 | else | |
1564 | mask = 0x1f; | |
1565 | ||
1566 | /* load */ | |
1e4840bf FB |
1567 | if (op1 == OR_TMP0) { |
1568 | tcg_gen_mov_tl(a0, cpu_A0); | |
1569 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1570 | } else { | |
1571 | gen_op_mov_v_reg(ot, t0, op1); | |
1572 | } | |
b6abf97d | 1573 | |
1e4840bf FB |
1574 | tcg_gen_mov_tl(t1, cpu_T[1]); |
1575 | ||
1576 | tcg_gen_andi_tl(t1, t1, mask); | |
b6abf97d FB |
1577 | |
1578 | /* Must test zero case to avoid using undefined behaviour in TCG | |
1579 | shifts. */ | |
1580 | label1 = gen_new_label(); | |
1e4840bf | 1581 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1); |
b6abf97d FB |
1582 | |
1583 | if (ot <= OT_WORD) | |
1e4840bf | 1584 | tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); |
b6abf97d | 1585 | else |
1e4840bf | 1586 | tcg_gen_mov_tl(cpu_tmp0, t1); |
b6abf97d | 1587 | |
1e4840bf FB |
1588 | gen_extu(ot, t0); |
1589 | tcg_gen_mov_tl(t2, t0); | |
b6abf97d FB |
1590 | |
1591 | data_bits = 8 << ot; | |
1592 | /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX: | |
1593 | fix TCG definition) */ | |
1594 | if (is_right) { | |
1e4840bf | 1595 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1596 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1597 | tcg_gen_shl_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1598 | } else { |
1e4840bf | 1599 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1600 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1601 | tcg_gen_shr_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1602 | } |
1e4840bf | 1603 | tcg_gen_or_tl(t0, t0, cpu_tmp4); |
b6abf97d FB |
1604 | |
1605 | gen_set_label(label1); | |
1606 | /* store */ | |
1e4840bf FB |
1607 | if (op1 == OR_TMP0) { |
1608 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1609 | } else { | |
1610 | gen_op_mov_reg_v(ot, op1, t0); | |
1611 | } | |
b6abf97d FB |
1612 | |
1613 | /* update eflags */ | |
1614 | if (s->cc_op != CC_OP_DYNAMIC) | |
1615 | gen_op_set_cc_op(s->cc_op); | |
1616 | ||
1617 | label2 = gen_new_label(); | |
1e4840bf | 1618 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2); |
b6abf97d FB |
1619 | |
1620 | gen_compute_eflags(cpu_cc_src); | |
1621 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); | |
1e4840bf | 1622 | tcg_gen_xor_tl(cpu_tmp0, t2, t0); |
b6abf97d FB |
1623 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
1624 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1625 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1626 | if (is_right) { | |
1e4840bf | 1627 | tcg_gen_shri_tl(t0, t0, data_bits - 1); |
b6abf97d | 1628 | } |
1e4840bf FB |
1629 | tcg_gen_andi_tl(t0, t0, CC_C); |
1630 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
b6abf97d FB |
1631 | |
1632 | tcg_gen_discard_tl(cpu_cc_dst); | |
1633 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); | |
1634 | ||
1635 | gen_set_label(label2); | |
1636 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1e4840bf FB |
1637 | |
1638 | tcg_temp_free(t0); | |
1639 | tcg_temp_free(t1); | |
1640 | tcg_temp_free(t2); | |
1641 | tcg_temp_free(a0); | |
b6abf97d FB |
1642 | } |
1643 | ||
8cd6345d | 1644 | static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, |
1645 | int is_right) | |
1646 | { | |
1647 | int mask; | |
1648 | int data_bits; | |
1649 | TCGv t0, t1, a0; | |
1650 | ||
1651 | /* XXX: inefficient, but we must use local temps */ | |
1652 | t0 = tcg_temp_local_new(); | |
1653 | t1 = tcg_temp_local_new(); | |
1654 | a0 = tcg_temp_local_new(); | |
1655 | ||
1656 | if (ot == OT_QUAD) | |
1657 | mask = 0x3f; | |
1658 | else | |
1659 | mask = 0x1f; | |
1660 | ||
1661 | /* load */ | |
1662 | if (op1 == OR_TMP0) { | |
1663 | tcg_gen_mov_tl(a0, cpu_A0); | |
1664 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1665 | } else { | |
1666 | gen_op_mov_v_reg(ot, t0, op1); | |
1667 | } | |
1668 | ||
1669 | gen_extu(ot, t0); | |
1670 | tcg_gen_mov_tl(t1, t0); | |
1671 | ||
1672 | op2 &= mask; | |
1673 | data_bits = 8 << ot; | |
1674 | if (op2 != 0) { | |
1675 | int shift = op2 & ((1 << (3 + ot)) - 1); | |
1676 | if (is_right) { | |
1677 | tcg_gen_shri_tl(cpu_tmp4, t0, shift); | |
1678 | tcg_gen_shli_tl(t0, t0, data_bits - shift); | |
1679 | } | |
1680 | else { | |
1681 | tcg_gen_shli_tl(cpu_tmp4, t0, shift); | |
1682 | tcg_gen_shri_tl(t0, t0, data_bits - shift); | |
1683 | } | |
1684 | tcg_gen_or_tl(t0, t0, cpu_tmp4); | |
1685 | } | |
1686 | ||
1687 | /* store */ | |
1688 | if (op1 == OR_TMP0) { | |
1689 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1690 | } else { | |
1691 | gen_op_mov_reg_v(ot, op1, t0); | |
1692 | } | |
1693 | ||
1694 | if (op2 != 0) { | |
1695 | /* update eflags */ | |
1696 | if (s->cc_op != CC_OP_DYNAMIC) | |
1697 | gen_op_set_cc_op(s->cc_op); | |
1698 | ||
1699 | gen_compute_eflags(cpu_cc_src); | |
1700 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); | |
1701 | tcg_gen_xor_tl(cpu_tmp0, t1, t0); | |
1702 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); | |
1703 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1704 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1705 | if (is_right) { | |
1706 | tcg_gen_shri_tl(t0, t0, data_bits - 1); | |
1707 | } | |
1708 | tcg_gen_andi_tl(t0, t0, CC_C); | |
1709 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
1710 | ||
1711 | tcg_gen_discard_tl(cpu_cc_dst); | |
1712 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); | |
1713 | s->cc_op = CC_OP_EFLAGS; | |
1714 | } | |
1715 | ||
1716 | tcg_temp_free(t0); | |
1717 | tcg_temp_free(t1); | |
1718 | tcg_temp_free(a0); | |
1719 | } | |
1720 | ||
b6abf97d FB |
1721 | /* XXX: add faster immediate = 1 case */ |
1722 | static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, | |
1723 | int is_right) | |
1724 | { | |
1725 | int label1; | |
1726 | ||
1727 | if (s->cc_op != CC_OP_DYNAMIC) | |
1728 | gen_op_set_cc_op(s->cc_op); | |
1729 | ||
1730 | /* load */ | |
1731 | if (op1 == OR_TMP0) | |
1732 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1733 | else | |
1734 | gen_op_mov_TN_reg(ot, 0, op1); | |
1735 | ||
a7812ae4 PB |
1736 | if (is_right) { |
1737 | switch (ot) { | |
1738 | case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1739 | case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1740 | case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1741 | #ifdef TARGET_X86_64 | |
1742 | case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1743 | #endif | |
1744 | } | |
1745 | } else { | |
1746 | switch (ot) { | |
1747 | case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1748 | case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1749 | case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1750 | #ifdef TARGET_X86_64 | |
1751 | case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break; | |
1752 | #endif | |
1753 | } | |
1754 | } | |
b6abf97d FB |
1755 | /* store */ |
1756 | if (op1 == OR_TMP0) | |
1757 | gen_op_st_T0_A0(ot + s->mem_index); | |
1758 | else | |
1759 | gen_op_mov_reg_T0(ot, op1); | |
1760 | ||
1761 | /* update eflags */ | |
1762 | label1 = gen_new_label(); | |
1e4840bf | 1763 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1); |
b6abf97d | 1764 | |
1e4840bf | 1765 | tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp); |
b6abf97d FB |
1766 | tcg_gen_discard_tl(cpu_cc_dst); |
1767 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); | |
1768 | ||
1769 | gen_set_label(label1); | |
1770 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1771 | } | |
1772 | ||
1773 | /* XXX: add faster immediate case */ | |
1774 | static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, | |
1775 | int is_right) | |
1776 | { | |
1777 | int label1, label2, data_bits; | |
1778 | target_ulong mask; | |
1e4840bf FB |
1779 | TCGv t0, t1, t2, a0; |
1780 | ||
a7812ae4 PB |
1781 | t0 = tcg_temp_local_new(); |
1782 | t1 = tcg_temp_local_new(); | |
1783 | t2 = tcg_temp_local_new(); | |
1784 | a0 = tcg_temp_local_new(); | |
b6abf97d FB |
1785 | |
1786 | if (ot == OT_QUAD) | |
1787 | mask = 0x3f; | |
1788 | else | |
1789 | mask = 0x1f; | |
1790 | ||
1791 | /* load */ | |
1e4840bf FB |
1792 | if (op1 == OR_TMP0) { |
1793 | tcg_gen_mov_tl(a0, cpu_A0); | |
1794 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1795 | } else { | |
1796 | gen_op_mov_v_reg(ot, t0, op1); | |
1797 | } | |
b6abf97d FB |
1798 | |
1799 | tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); | |
1e4840bf FB |
1800 | |
1801 | tcg_gen_mov_tl(t1, cpu_T[1]); | |
1802 | tcg_gen_mov_tl(t2, cpu_T3); | |
1803 | ||
b6abf97d FB |
1804 | /* Must test zero case to avoid using undefined behaviour in TCG |
1805 | shifts. */ | |
1806 | label1 = gen_new_label(); | |
1e4840bf | 1807 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); |
b6abf97d | 1808 | |
1e4840bf | 1809 | tcg_gen_addi_tl(cpu_tmp5, t2, -1); |
b6abf97d FB |
1810 | if (ot == OT_WORD) { |
1811 | /* Note: we implement the Intel behaviour for shift count > 16 */ | |
1812 | if (is_right) { | |
1e4840bf FB |
1813 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1814 | tcg_gen_shli_tl(cpu_tmp0, t1, 16); | |
1815 | tcg_gen_or_tl(t0, t0, cpu_tmp0); | |
1816 | tcg_gen_ext32u_tl(t0, t0); | |
b6abf97d | 1817 | |
1e4840bf | 1818 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d FB |
1819 | |
1820 | /* only needed if count > 16, but a test would complicate */ | |
5b207c00 | 1821 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf | 1822 | tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5); |
b6abf97d | 1823 | |
1e4840bf | 1824 | tcg_gen_shr_tl(t0, t0, t2); |
b6abf97d | 1825 | |
1e4840bf | 1826 | tcg_gen_or_tl(t0, t0, cpu_tmp0); |
b6abf97d FB |
1827 | } else { |
1828 | /* XXX: not optimal */ | |
1e4840bf FB |
1829 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1830 | tcg_gen_shli_tl(t1, t1, 16); | |
1831 | tcg_gen_or_tl(t1, t1, t0); | |
1832 | tcg_gen_ext32u_tl(t1, t1); | |
b6abf97d | 1833 | |
1e4840bf | 1834 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
5b207c00 | 1835 | tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5); |
bedda79c AJ |
1836 | tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0); |
1837 | tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5); | |
b6abf97d | 1838 | |
1e4840bf | 1839 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1840 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf FB |
1841 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1842 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1843 | } |
1844 | } else { | |
1845 | data_bits = 8 << ot; | |
1846 | if (is_right) { | |
1847 | if (ot == OT_LONG) | |
1e4840bf | 1848 | tcg_gen_ext32u_tl(t0, t0); |
b6abf97d | 1849 | |
1e4840bf | 1850 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1851 | |
1e4840bf | 1852 | tcg_gen_shr_tl(t0, t0, t2); |
5b207c00 | 1853 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1854 | tcg_gen_shl_tl(t1, t1, cpu_tmp5); |
1855 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1856 | |
1857 | } else { | |
1858 | if (ot == OT_LONG) | |
1e4840bf | 1859 | tcg_gen_ext32u_tl(t1, t1); |
b6abf97d | 1860 | |
1e4840bf | 1861 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1862 | |
1e4840bf | 1863 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1864 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1865 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1866 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1867 | } |
1868 | } | |
1e4840bf | 1869 | tcg_gen_mov_tl(t1, cpu_tmp4); |
b6abf97d FB |
1870 | |
1871 | gen_set_label(label1); | |
1872 | /* store */ | |
1e4840bf FB |
1873 | if (op1 == OR_TMP0) { |
1874 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1875 | } else { | |
1876 | gen_op_mov_reg_v(ot, op1, t0); | |
1877 | } | |
b6abf97d FB |
1878 | |
1879 | /* update eflags */ | |
1880 | if (s->cc_op != CC_OP_DYNAMIC) | |
1881 | gen_op_set_cc_op(s->cc_op); | |
1882 | ||
1883 | label2 = gen_new_label(); | |
1e4840bf | 1884 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2); |
b6abf97d | 1885 | |
1e4840bf FB |
1886 | tcg_gen_mov_tl(cpu_cc_src, t1); |
1887 | tcg_gen_mov_tl(cpu_cc_dst, t0); | |
b6abf97d FB |
1888 | if (is_right) { |
1889 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); | |
1890 | } else { | |
1891 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); | |
1892 | } | |
1893 | gen_set_label(label2); | |
1894 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1e4840bf FB |
1895 | |
1896 | tcg_temp_free(t0); | |
1897 | tcg_temp_free(t1); | |
1898 | tcg_temp_free(t2); | |
1899 | tcg_temp_free(a0); | |
b6abf97d FB |
1900 | } |
1901 | ||
1902 | static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) | |
1903 | { | |
1904 | if (s != OR_TMP1) | |
1905 | gen_op_mov_TN_reg(ot, 1, s); | |
1906 | switch(op) { | |
1907 | case OP_ROL: | |
1908 | gen_rot_rm_T1(s1, ot, d, 0); | |
1909 | break; | |
1910 | case OP_ROR: | |
1911 | gen_rot_rm_T1(s1, ot, d, 1); | |
1912 | break; | |
1913 | case OP_SHL: | |
1914 | case OP_SHL1: | |
1915 | gen_shift_rm_T1(s1, ot, d, 0, 0); | |
1916 | break; | |
1917 | case OP_SHR: | |
1918 | gen_shift_rm_T1(s1, ot, d, 1, 0); | |
1919 | break; | |
1920 | case OP_SAR: | |
1921 | gen_shift_rm_T1(s1, ot, d, 1, 1); | |
1922 | break; | |
1923 | case OP_RCL: | |
1924 | gen_rotc_rm_T1(s1, ot, d, 0); | |
1925 | break; | |
1926 | case OP_RCR: | |
1927 | gen_rotc_rm_T1(s1, ot, d, 1); | |
1928 | break; | |
1929 | } | |
2c0262af FB |
1930 | } |
1931 | ||
1932 | static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) | |
1933 | { | |
c1c37968 | 1934 | switch(op) { |
8cd6345d | 1935 | case OP_ROL: |
1936 | gen_rot_rm_im(s1, ot, d, c, 0); | |
1937 | break; | |
1938 | case OP_ROR: | |
1939 | gen_rot_rm_im(s1, ot, d, c, 1); | |
1940 | break; | |
c1c37968 FB |
1941 | case OP_SHL: |
1942 | case OP_SHL1: | |
1943 | gen_shift_rm_im(s1, ot, d, c, 0, 0); | |
1944 | break; | |
1945 | case OP_SHR: | |
1946 | gen_shift_rm_im(s1, ot, d, c, 1, 0); | |
1947 | break; | |
1948 | case OP_SAR: | |
1949 | gen_shift_rm_im(s1, ot, d, c, 1, 1); | |
1950 | break; | |
1951 | default: | |
1952 | /* currently not optimized */ | |
1953 | gen_op_movl_T1_im(c); | |
1954 | gen_shift(s1, op, ot, d, OR_TMP1); | |
1955 | break; | |
1956 | } | |
2c0262af FB |
1957 | } |
1958 | ||
1959 | static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr) | |
1960 | { | |
14ce26e7 | 1961 | target_long disp; |
2c0262af | 1962 | int havesib; |
14ce26e7 | 1963 | int base; |
2c0262af FB |
1964 | int index; |
1965 | int scale; | |
1966 | int opreg; | |
1967 | int mod, rm, code, override, must_add_seg; | |
1968 | ||
1969 | override = s->override; | |
1970 | must_add_seg = s->addseg; | |
1971 | if (override >= 0) | |
1972 | must_add_seg = 1; | |
1973 | mod = (modrm >> 6) & 3; | |
1974 | rm = modrm & 7; | |
1975 | ||
1976 | if (s->aflag) { | |
1977 | ||
1978 | havesib = 0; | |
1979 | base = rm; | |
1980 | index = 0; | |
1981 | scale = 0; | |
3b46e624 | 1982 | |
2c0262af FB |
1983 | if (base == 4) { |
1984 | havesib = 1; | |
61382a50 | 1985 | code = ldub_code(s->pc++); |
2c0262af | 1986 | scale = (code >> 6) & 3; |
14ce26e7 FB |
1987 | index = ((code >> 3) & 7) | REX_X(s); |
1988 | base = (code & 7); | |
2c0262af | 1989 | } |
14ce26e7 | 1990 | base |= REX_B(s); |
2c0262af FB |
1991 | |
1992 | switch (mod) { | |
1993 | case 0: | |
14ce26e7 | 1994 | if ((base & 7) == 5) { |
2c0262af | 1995 | base = -1; |
14ce26e7 | 1996 | disp = (int32_t)ldl_code(s->pc); |
2c0262af | 1997 | s->pc += 4; |
14ce26e7 FB |
1998 | if (CODE64(s) && !havesib) { |
1999 | disp += s->pc + s->rip_offset; | |
2000 | } | |
2c0262af FB |
2001 | } else { |
2002 | disp = 0; | |
2003 | } | |
2004 | break; | |
2005 | case 1: | |
61382a50 | 2006 | disp = (int8_t)ldub_code(s->pc++); |
2c0262af FB |
2007 | break; |
2008 | default: | |
2009 | case 2: | |
8c0e6340 | 2010 | disp = (int32_t)ldl_code(s->pc); |
2c0262af FB |
2011 | s->pc += 4; |
2012 | break; | |
2013 | } | |
3b46e624 | 2014 | |
2c0262af FB |
2015 | if (base >= 0) { |
2016 | /* for correct popl handling with esp */ | |
2017 | if (base == 4 && s->popl_esp_hack) | |
2018 | disp += s->popl_esp_hack; | |
14ce26e7 FB |
2019 | #ifdef TARGET_X86_64 |
2020 | if (s->aflag == 2) { | |
57fec1fe | 2021 | gen_op_movq_A0_reg(base); |
14ce26e7 | 2022 | if (disp != 0) { |
57fec1fe | 2023 | gen_op_addq_A0_im(disp); |
14ce26e7 | 2024 | } |
5fafdf24 | 2025 | } else |
14ce26e7 FB |
2026 | #endif |
2027 | { | |
57fec1fe | 2028 | gen_op_movl_A0_reg(base); |
14ce26e7 FB |
2029 | if (disp != 0) |
2030 | gen_op_addl_A0_im(disp); | |
2031 | } | |
2c0262af | 2032 | } else { |
14ce26e7 FB |
2033 | #ifdef TARGET_X86_64 |
2034 | if (s->aflag == 2) { | |
57fec1fe | 2035 | gen_op_movq_A0_im(disp); |
5fafdf24 | 2036 | } else |
14ce26e7 FB |
2037 | #endif |
2038 | { | |
2039 | gen_op_movl_A0_im(disp); | |
2040 | } | |
2c0262af | 2041 | } |
b16f827b AJ |
2042 | /* index == 4 means no index */ |
2043 | if (havesib && (index != 4)) { | |
14ce26e7 FB |
2044 | #ifdef TARGET_X86_64 |
2045 | if (s->aflag == 2) { | |
57fec1fe | 2046 | gen_op_addq_A0_reg_sN(scale, index); |
5fafdf24 | 2047 | } else |
14ce26e7 FB |
2048 | #endif |
2049 | { | |
57fec1fe | 2050 | gen_op_addl_A0_reg_sN(scale, index); |
14ce26e7 | 2051 | } |
2c0262af FB |
2052 | } |
2053 | if (must_add_seg) { | |
2054 | if (override < 0) { | |
2055 | if (base == R_EBP || base == R_ESP) | |
2056 | override = R_SS; | |
2057 | else | |
2058 | override = R_DS; | |
2059 | } | |
14ce26e7 FB |
2060 | #ifdef TARGET_X86_64 |
2061 | if (s->aflag == 2) { | |
57fec1fe | 2062 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2063 | } else |
14ce26e7 FB |
2064 | #endif |
2065 | { | |
57fec1fe | 2066 | gen_op_addl_A0_seg(override); |
14ce26e7 | 2067 | } |
2c0262af FB |
2068 | } |
2069 | } else { | |
2070 | switch (mod) { | |
2071 | case 0: | |
2072 | if (rm == 6) { | |
61382a50 | 2073 | disp = lduw_code(s->pc); |
2c0262af FB |
2074 | s->pc += 2; |
2075 | gen_op_movl_A0_im(disp); | |
2076 | rm = 0; /* avoid SS override */ | |
2077 | goto no_rm; | |
2078 | } else { | |
2079 | disp = 0; | |
2080 | } | |
2081 | break; | |
2082 | case 1: | |
61382a50 | 2083 | disp = (int8_t)ldub_code(s->pc++); |
2c0262af FB |
2084 | break; |
2085 | default: | |
2086 | case 2: | |
61382a50 | 2087 | disp = lduw_code(s->pc); |
2c0262af FB |
2088 | s->pc += 2; |
2089 | break; | |
2090 | } | |
2091 | switch(rm) { | |
2092 | case 0: | |
57fec1fe FB |
2093 | gen_op_movl_A0_reg(R_EBX); |
2094 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2095 | break; |
2096 | case 1: | |
57fec1fe FB |
2097 | gen_op_movl_A0_reg(R_EBX); |
2098 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2099 | break; |
2100 | case 2: | |
57fec1fe FB |
2101 | gen_op_movl_A0_reg(R_EBP); |
2102 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2103 | break; |
2104 | case 3: | |
57fec1fe FB |
2105 | gen_op_movl_A0_reg(R_EBP); |
2106 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2107 | break; |
2108 | case 4: | |
57fec1fe | 2109 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
2110 | break; |
2111 | case 5: | |
57fec1fe | 2112 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
2113 | break; |
2114 | case 6: | |
57fec1fe | 2115 | gen_op_movl_A0_reg(R_EBP); |
2c0262af FB |
2116 | break; |
2117 | default: | |
2118 | case 7: | |
57fec1fe | 2119 | gen_op_movl_A0_reg(R_EBX); |
2c0262af FB |
2120 | break; |
2121 | } | |
2122 | if (disp != 0) | |
2123 | gen_op_addl_A0_im(disp); | |
2124 | gen_op_andl_A0_ffff(); | |
2125 | no_rm: | |
2126 | if (must_add_seg) { | |
2127 | if (override < 0) { | |
2128 | if (rm == 2 || rm == 3 || rm == 6) | |
2129 | override = R_SS; | |
2130 | else | |
2131 | override = R_DS; | |
2132 | } | |
57fec1fe | 2133 | gen_op_addl_A0_seg(override); |
2c0262af FB |
2134 | } |
2135 | } | |
2136 | ||
2137 | opreg = OR_A0; | |
2138 | disp = 0; | |
2139 | *reg_ptr = opreg; | |
2140 | *offset_ptr = disp; | |
2141 | } | |
2142 | ||
e17a36ce FB |
2143 | static void gen_nop_modrm(DisasContext *s, int modrm) |
2144 | { | |
2145 | int mod, rm, base, code; | |
2146 | ||
2147 | mod = (modrm >> 6) & 3; | |
2148 | if (mod == 3) | |
2149 | return; | |
2150 | rm = modrm & 7; | |
2151 | ||
2152 | if (s->aflag) { | |
2153 | ||
2154 | base = rm; | |
3b46e624 | 2155 | |
e17a36ce FB |
2156 | if (base == 4) { |
2157 | code = ldub_code(s->pc++); | |
2158 | base = (code & 7); | |
2159 | } | |
3b46e624 | 2160 | |
e17a36ce FB |
2161 | switch (mod) { |
2162 | case 0: | |
2163 | if (base == 5) { | |
2164 | s->pc += 4; | |
2165 | } | |
2166 | break; | |
2167 | case 1: | |
2168 | s->pc++; | |
2169 | break; | |
2170 | default: | |
2171 | case 2: | |
2172 | s->pc += 4; | |
2173 | break; | |
2174 | } | |
2175 | } else { | |
2176 | switch (mod) { | |
2177 | case 0: | |
2178 | if (rm == 6) { | |
2179 | s->pc += 2; | |
2180 | } | |
2181 | break; | |
2182 | case 1: | |
2183 | s->pc++; | |
2184 | break; | |
2185 | default: | |
2186 | case 2: | |
2187 | s->pc += 2; | |
2188 | break; | |
2189 | } | |
2190 | } | |
2191 | } | |
2192 | ||
664e0f19 FB |
2193 | /* used for LEA and MOV AX, mem */ |
2194 | static void gen_add_A0_ds_seg(DisasContext *s) | |
2195 | { | |
2196 | int override, must_add_seg; | |
2197 | must_add_seg = s->addseg; | |
2198 | override = R_DS; | |
2199 | if (s->override >= 0) { | |
2200 | override = s->override; | |
2201 | must_add_seg = 1; | |
664e0f19 FB |
2202 | } |
2203 | if (must_add_seg) { | |
8f091a59 FB |
2204 | #ifdef TARGET_X86_64 |
2205 | if (CODE64(s)) { | |
57fec1fe | 2206 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2207 | } else |
8f091a59 FB |
2208 | #endif |
2209 | { | |
57fec1fe | 2210 | gen_op_addl_A0_seg(override); |
8f091a59 | 2211 | } |
664e0f19 FB |
2212 | } |
2213 | } | |
2214 | ||
222a3336 | 2215 | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == |
2c0262af FB |
2216 | OR_TMP0 */ |
2217 | static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store) | |
2218 | { | |
2219 | int mod, rm, opreg, disp; | |
2220 | ||
2221 | mod = (modrm >> 6) & 3; | |
14ce26e7 | 2222 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
2223 | if (mod == 3) { |
2224 | if (is_store) { | |
2225 | if (reg != OR_TMP0) | |
57fec1fe FB |
2226 | gen_op_mov_TN_reg(ot, 0, reg); |
2227 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 2228 | } else { |
57fec1fe | 2229 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 2230 | if (reg != OR_TMP0) |
57fec1fe | 2231 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2232 | } |
2233 | } else { | |
2234 | gen_lea_modrm(s, modrm, &opreg, &disp); | |
2235 | if (is_store) { | |
2236 | if (reg != OR_TMP0) | |
57fec1fe FB |
2237 | gen_op_mov_TN_reg(ot, 0, reg); |
2238 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 2239 | } else { |
57fec1fe | 2240 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 2241 | if (reg != OR_TMP0) |
57fec1fe | 2242 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2243 | } |
2244 | } | |
2245 | } | |
2246 | ||
2247 | static inline uint32_t insn_get(DisasContext *s, int ot) | |
2248 | { | |
2249 | uint32_t ret; | |
2250 | ||
2251 | switch(ot) { | |
2252 | case OT_BYTE: | |
61382a50 | 2253 | ret = ldub_code(s->pc); |
2c0262af FB |
2254 | s->pc++; |
2255 | break; | |
2256 | case OT_WORD: | |
61382a50 | 2257 | ret = lduw_code(s->pc); |
2c0262af FB |
2258 | s->pc += 2; |
2259 | break; | |
2260 | default: | |
2261 | case OT_LONG: | |
61382a50 | 2262 | ret = ldl_code(s->pc); |
2c0262af FB |
2263 | s->pc += 4; |
2264 | break; | |
2265 | } | |
2266 | return ret; | |
2267 | } | |
2268 | ||
14ce26e7 FB |
2269 | static inline int insn_const_size(unsigned int ot) |
2270 | { | |
2271 | if (ot <= OT_LONG) | |
2272 | return 1 << ot; | |
2273 | else | |
2274 | return 4; | |
2275 | } | |
2276 | ||
6e256c93 FB |
2277 | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2278 | { | |
2279 | TranslationBlock *tb; | |
2280 | target_ulong pc; | |
2281 | ||
2282 | pc = s->cs_base + eip; | |
2283 | tb = s->tb; | |
2284 | /* NOTE: we handle the case where the TB spans two pages here */ | |
2285 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) || | |
2286 | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { | |
2287 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 2288 | tcg_gen_goto_tb(tb_num); |
6e256c93 | 2289 | gen_jmp_im(eip); |
4b4a72e5 | 2290 | tcg_gen_exit_tb((tcg_target_long)tb + tb_num); |
6e256c93 FB |
2291 | } else { |
2292 | /* jump to another page: currently not optimized */ | |
2293 | gen_jmp_im(eip); | |
2294 | gen_eob(s); | |
2295 | } | |
2296 | } | |
2297 | ||
5fafdf24 | 2298 | static inline void gen_jcc(DisasContext *s, int b, |
14ce26e7 | 2299 | target_ulong val, target_ulong next_eip) |
2c0262af | 2300 | { |
8e1c85e3 | 2301 | int l1, l2, cc_op; |
3b46e624 | 2302 | |
8e1c85e3 | 2303 | cc_op = s->cc_op; |
728d803b | 2304 | gen_update_cc_op(s); |
2c0262af | 2305 | if (s->jmp_opt) { |
14ce26e7 | 2306 | l1 = gen_new_label(); |
8e1c85e3 FB |
2307 | gen_jcc1(s, cc_op, b, l1); |
2308 | ||
6e256c93 | 2309 | gen_goto_tb(s, 0, next_eip); |
14ce26e7 FB |
2310 | |
2311 | gen_set_label(l1); | |
6e256c93 | 2312 | gen_goto_tb(s, 1, val); |
5779406a | 2313 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2314 | } else { |
14ce26e7 | 2315 | |
14ce26e7 FB |
2316 | l1 = gen_new_label(); |
2317 | l2 = gen_new_label(); | |
8e1c85e3 FB |
2318 | gen_jcc1(s, cc_op, b, l1); |
2319 | ||
14ce26e7 | 2320 | gen_jmp_im(next_eip); |
8e1c85e3 FB |
2321 | tcg_gen_br(l2); |
2322 | ||
14ce26e7 FB |
2323 | gen_set_label(l1); |
2324 | gen_jmp_im(val); | |
2325 | gen_set_label(l2); | |
2c0262af FB |
2326 | gen_eob(s); |
2327 | } | |
2328 | } | |
2329 | ||
2330 | static void gen_setcc(DisasContext *s, int b) | |
2331 | { | |
8e1c85e3 | 2332 | int inv, jcc_op, l1; |
1e4840bf | 2333 | TCGv t0; |
14ce26e7 | 2334 | |
8e1c85e3 FB |
2335 | if (is_fast_jcc_case(s, b)) { |
2336 | /* nominal case: we use a jump */ | |
1e4840bf | 2337 | /* XXX: make it faster by adding new instructions in TCG */ |
a7812ae4 | 2338 | t0 = tcg_temp_local_new(); |
1e4840bf | 2339 | tcg_gen_movi_tl(t0, 0); |
8e1c85e3 FB |
2340 | l1 = gen_new_label(); |
2341 | gen_jcc1(s, s->cc_op, b ^ 1, l1); | |
1e4840bf | 2342 | tcg_gen_movi_tl(t0, 1); |
8e1c85e3 | 2343 | gen_set_label(l1); |
1e4840bf FB |
2344 | tcg_gen_mov_tl(cpu_T[0], t0); |
2345 | tcg_temp_free(t0); | |
8e1c85e3 FB |
2346 | } else { |
2347 | /* slow case: it is more efficient not to generate a jump, | |
2348 | although it is questionnable whether this optimization is | |
2349 | worth to */ | |
2350 | inv = b & 1; | |
2351 | jcc_op = (b >> 1) & 7; | |
1e4840bf | 2352 | gen_setcc_slow_T0(s, jcc_op); |
8e1c85e3 FB |
2353 | if (inv) { |
2354 | tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1); | |
2355 | } | |
2c0262af FB |
2356 | } |
2357 | } | |
2358 | ||
3bd7da9e FB |
2359 | static inline void gen_op_movl_T0_seg(int seg_reg) |
2360 | { | |
2361 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, | |
2362 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2363 | } | |
2364 | ||
2365 | static inline void gen_op_movl_seg_T0_vm(int seg_reg) | |
2366 | { | |
2367 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
2368 | tcg_gen_st32_tl(cpu_T[0], cpu_env, | |
2369 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2370 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); | |
2371 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
2372 | offsetof(CPUX86State,segs[seg_reg].base)); | |
2373 | } | |
2374 | ||
2c0262af FB |
2375 | /* move T0 to seg_reg and compute if the CPU state may change. Never |
2376 | call this function with seg_reg == R_CS */ | |
14ce26e7 | 2377 | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2c0262af | 2378 | { |
3415a4dd FB |
2379 | if (s->pe && !s->vm86) { |
2380 | /* XXX: optimize by finding processor state dynamically */ | |
2381 | if (s->cc_op != CC_OP_DYNAMIC) | |
2382 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2383 | gen_jmp_im(cur_eip); |
b6abf97d | 2384 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 2385 | gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32); |
dc196a57 FB |
2386 | /* abort translation because the addseg value may change or |
2387 | because ss32 may change. For R_SS, translation must always | |
2388 | stop as a special handling must be done to disable hardware | |
2389 | interrupts for the next instruction */ | |
2390 | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) | |
5779406a | 2391 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2392 | } else { |
3bd7da9e | 2393 | gen_op_movl_seg_T0_vm(seg_reg); |
dc196a57 | 2394 | if (seg_reg == R_SS) |
5779406a | 2395 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2396 | } |
2c0262af FB |
2397 | } |
2398 | ||
0573fbfc TS |
2399 | static inline int svm_is_rep(int prefixes) |
2400 | { | |
2401 | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); | |
2402 | } | |
2403 | ||
872929aa | 2404 | static inline void |
0573fbfc | 2405 | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
b8b6a50b | 2406 | uint32_t type, uint64_t param) |
0573fbfc | 2407 | { |
872929aa FB |
2408 | /* no SVM activated; fast case */ |
2409 | if (likely(!(s->flags & HF_SVMI_MASK))) | |
2410 | return; | |
2411 | if (s->cc_op != CC_OP_DYNAMIC) | |
2412 | gen_op_set_cc_op(s->cc_op); | |
2413 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 PB |
2414 | gen_helper_svm_check_intercept_param(tcg_const_i32(type), |
2415 | tcg_const_i64(param)); | |
0573fbfc TS |
2416 | } |
2417 | ||
872929aa | 2418 | static inline void |
0573fbfc TS |
2419 | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2420 | { | |
872929aa | 2421 | gen_svm_check_intercept_param(s, pc_start, type, 0); |
0573fbfc TS |
2422 | } |
2423 | ||
4f31916f FB |
2424 | static inline void gen_stack_update(DisasContext *s, int addend) |
2425 | { | |
14ce26e7 FB |
2426 | #ifdef TARGET_X86_64 |
2427 | if (CODE64(s)) { | |
6e0d8677 | 2428 | gen_op_add_reg_im(2, R_ESP, addend); |
14ce26e7 FB |
2429 | } else |
2430 | #endif | |
4f31916f | 2431 | if (s->ss32) { |
6e0d8677 | 2432 | gen_op_add_reg_im(1, R_ESP, addend); |
4f31916f | 2433 | } else { |
6e0d8677 | 2434 | gen_op_add_reg_im(0, R_ESP, addend); |
4f31916f FB |
2435 | } |
2436 | } | |
2437 | ||
2c0262af FB |
2438 | /* generate a push. It depends on ss32, addseg and dflag */ |
2439 | static void gen_push_T0(DisasContext *s) | |
2440 | { | |
14ce26e7 FB |
2441 | #ifdef TARGET_X86_64 |
2442 | if (CODE64(s)) { | |
57fec1fe | 2443 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2444 | if (s->dflag) { |
57fec1fe FB |
2445 | gen_op_addq_A0_im(-8); |
2446 | gen_op_st_T0_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2447 | } else { |
57fec1fe FB |
2448 | gen_op_addq_A0_im(-2); |
2449 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2450 | } |
57fec1fe | 2451 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2452 | } else |
14ce26e7 FB |
2453 | #endif |
2454 | { | |
57fec1fe | 2455 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2456 | if (!s->dflag) |
57fec1fe | 2457 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2458 | else |
57fec1fe | 2459 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2460 | if (s->ss32) { |
2461 | if (s->addseg) { | |
bbf662ee | 2462 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
57fec1fe | 2463 | gen_op_addl_A0_seg(R_SS); |
14ce26e7 FB |
2464 | } |
2465 | } else { | |
2466 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2467 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
57fec1fe | 2468 | gen_op_addl_A0_seg(R_SS); |
2c0262af | 2469 | } |
57fec1fe | 2470 | gen_op_st_T0_A0(s->dflag + 1 + s->mem_index); |
14ce26e7 | 2471 | if (s->ss32 && !s->addseg) |
57fec1fe | 2472 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 | 2473 | else |
57fec1fe | 2474 | gen_op_mov_reg_T1(s->ss32 + 1, R_ESP); |
2c0262af FB |
2475 | } |
2476 | } | |
2477 | ||
4f31916f FB |
2478 | /* generate a push. It depends on ss32, addseg and dflag */ |
2479 | /* slower version for T1, only used for call Ev */ | |
2480 | static void gen_push_T1(DisasContext *s) | |
2c0262af | 2481 | { |
14ce26e7 FB |
2482 | #ifdef TARGET_X86_64 |
2483 | if (CODE64(s)) { | |
57fec1fe | 2484 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2485 | if (s->dflag) { |
57fec1fe FB |
2486 | gen_op_addq_A0_im(-8); |
2487 | gen_op_st_T1_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2488 | } else { |
57fec1fe FB |
2489 | gen_op_addq_A0_im(-2); |
2490 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2491 | } |
57fec1fe | 2492 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2493 | } else |
14ce26e7 FB |
2494 | #endif |
2495 | { | |
57fec1fe | 2496 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2497 | if (!s->dflag) |
57fec1fe | 2498 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2499 | else |
57fec1fe | 2500 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2501 | if (s->ss32) { |
2502 | if (s->addseg) { | |
57fec1fe | 2503 | gen_op_addl_A0_seg(R_SS); |
14ce26e7 FB |
2504 | } |
2505 | } else { | |
2506 | gen_op_andl_A0_ffff(); | |
57fec1fe | 2507 | gen_op_addl_A0_seg(R_SS); |
2c0262af | 2508 | } |
57fec1fe | 2509 | gen_op_st_T1_A0(s->dflag + 1 + s->mem_index); |
3b46e624 | 2510 | |
14ce26e7 | 2511 | if (s->ss32 && !s->addseg) |
57fec1fe | 2512 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 FB |
2513 | else |
2514 | gen_stack_update(s, (-2) << s->dflag); | |
2c0262af FB |
2515 | } |
2516 | } | |
2517 | ||
4f31916f FB |
2518 | /* two step pop is necessary for precise exceptions */ |
2519 | static void gen_pop_T0(DisasContext *s) | |
2c0262af | 2520 | { |
14ce26e7 FB |
2521 | #ifdef TARGET_X86_64 |
2522 | if (CODE64(s)) { | |
57fec1fe FB |
2523 | gen_op_movq_A0_reg(R_ESP); |
2524 | gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index); | |
5fafdf24 | 2525 | } else |
14ce26e7 FB |
2526 | #endif |
2527 | { | |
57fec1fe | 2528 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 FB |
2529 | if (s->ss32) { |
2530 | if (s->addseg) | |
57fec1fe | 2531 | gen_op_addl_A0_seg(R_SS); |
14ce26e7 FB |
2532 | } else { |
2533 | gen_op_andl_A0_ffff(); | |
57fec1fe | 2534 | gen_op_addl_A0_seg(R_SS); |
14ce26e7 | 2535 | } |
57fec1fe | 2536 | gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index); |
2c0262af FB |
2537 | } |
2538 | } | |
2539 | ||
2540 | static void gen_pop_update(DisasContext *s) | |
2541 | { | |
14ce26e7 | 2542 | #ifdef TARGET_X86_64 |
8f091a59 | 2543 | if (CODE64(s) && s->dflag) { |
14ce26e7 FB |
2544 | gen_stack_update(s, 8); |
2545 | } else | |
2546 | #endif | |
2547 | { | |
2548 | gen_stack_update(s, 2 << s->dflag); | |
2549 | } | |
2c0262af FB |
2550 | } |
2551 | ||
2552 | static void gen_stack_A0(DisasContext *s) | |
2553 | { | |
57fec1fe | 2554 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2555 | if (!s->ss32) |
2556 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2557 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2558 | if (s->addseg) |
57fec1fe | 2559 | gen_op_addl_A0_seg(R_SS); |
2c0262af FB |
2560 | } |
2561 | ||
2562 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2563 | static void gen_pusha(DisasContext *s) | |
2564 | { | |
2565 | int i; | |
57fec1fe | 2566 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2567 | gen_op_addl_A0_im(-16 << s->dflag); |
2568 | if (!s->ss32) | |
2569 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2570 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2571 | if (s->addseg) |
57fec1fe | 2572 | gen_op_addl_A0_seg(R_SS); |
2c0262af | 2573 | for(i = 0;i < 8; i++) { |
57fec1fe FB |
2574 | gen_op_mov_TN_reg(OT_LONG, 0, 7 - i); |
2575 | gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index); | |
2c0262af FB |
2576 | gen_op_addl_A0_im(2 << s->dflag); |
2577 | } | |
57fec1fe | 2578 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2579 | } |
2580 | ||
2581 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2582 | static void gen_popa(DisasContext *s) | |
2583 | { | |
2584 | int i; | |
57fec1fe | 2585 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2586 | if (!s->ss32) |
2587 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
2588 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2589 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); | |
2c0262af | 2590 | if (s->addseg) |
57fec1fe | 2591 | gen_op_addl_A0_seg(R_SS); |
2c0262af FB |
2592 | for(i = 0;i < 8; i++) { |
2593 | /* ESP is not reloaded */ | |
2594 | if (i != 3) { | |
57fec1fe FB |
2595 | gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2596 | gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i); | |
2c0262af FB |
2597 | } |
2598 | gen_op_addl_A0_im(2 << s->dflag); | |
2599 | } | |
57fec1fe | 2600 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2601 | } |
2602 | ||
2c0262af FB |
2603 | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2604 | { | |
61a8c4ec | 2605 | int ot, opsize; |
2c0262af | 2606 | |
2c0262af | 2607 | level &= 0x1f; |
8f091a59 FB |
2608 | #ifdef TARGET_X86_64 |
2609 | if (CODE64(s)) { | |
2610 | ot = s->dflag ? OT_QUAD : OT_WORD; | |
2611 | opsize = 1 << ot; | |
3b46e624 | 2612 | |
57fec1fe | 2613 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 | 2614 | gen_op_addq_A0_im(-opsize); |
bbf662ee | 2615 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 FB |
2616 | |
2617 | /* push bp */ | |
57fec1fe FB |
2618 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2619 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2620 | if (level) { |
b5b38f61 | 2621 | /* XXX: must save state */ |
a7812ae4 PB |
2622 | gen_helper_enter64_level(tcg_const_i32(level), |
2623 | tcg_const_i32((ot == OT_QUAD)), | |
2624 | cpu_T[1]); | |
8f091a59 | 2625 | } |
57fec1fe | 2626 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2627 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2628 | gen_op_mov_reg_T1(OT_QUAD, R_ESP); |
5fafdf24 | 2629 | } else |
8f091a59 FB |
2630 | #endif |
2631 | { | |
2632 | ot = s->dflag + OT_WORD; | |
2633 | opsize = 2 << s->dflag; | |
3b46e624 | 2634 | |
57fec1fe | 2635 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 FB |
2636 | gen_op_addl_A0_im(-opsize); |
2637 | if (!s->ss32) | |
2638 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2639 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 | 2640 | if (s->addseg) |
57fec1fe | 2641 | gen_op_addl_A0_seg(R_SS); |
8f091a59 | 2642 | /* push bp */ |
57fec1fe FB |
2643 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2644 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2645 | if (level) { |
b5b38f61 | 2646 | /* XXX: must save state */ |
a7812ae4 PB |
2647 | gen_helper_enter_level(tcg_const_i32(level), |
2648 | tcg_const_i32(s->dflag), | |
2649 | cpu_T[1]); | |
8f091a59 | 2650 | } |
57fec1fe | 2651 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2652 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2653 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af | 2654 | } |
2c0262af FB |
2655 | } |
2656 | ||
14ce26e7 | 2657 | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2c0262af FB |
2658 | { |
2659 | if (s->cc_op != CC_OP_DYNAMIC) | |
2660 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2661 | gen_jmp_im(cur_eip); |
a7812ae4 | 2662 | gen_helper_raise_exception(tcg_const_i32(trapno)); |
5779406a | 2663 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2664 | } |
2665 | ||
2666 | /* an interrupt is different from an exception because of the | |
7f75ffd3 | 2667 | privilege checks */ |
5fafdf24 | 2668 | static void gen_interrupt(DisasContext *s, int intno, |
14ce26e7 | 2669 | target_ulong cur_eip, target_ulong next_eip) |
2c0262af FB |
2670 | { |
2671 | if (s->cc_op != CC_OP_DYNAMIC) | |
2672 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2673 | gen_jmp_im(cur_eip); |
a7812ae4 PB |
2674 | gen_helper_raise_interrupt(tcg_const_i32(intno), |
2675 | tcg_const_i32(next_eip - cur_eip)); | |
5779406a | 2676 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2677 | } |
2678 | ||
14ce26e7 | 2679 | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2c0262af FB |
2680 | { |
2681 | if (s->cc_op != CC_OP_DYNAMIC) | |
2682 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2683 | gen_jmp_im(cur_eip); |
a7812ae4 | 2684 | gen_helper_debug(); |
5779406a | 2685 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2686 | } |
2687 | ||
2688 | /* generate a generic end of block. Trace exception is also generated | |
2689 | if needed */ | |
2690 | static void gen_eob(DisasContext *s) | |
2691 | { | |
2692 | if (s->cc_op != CC_OP_DYNAMIC) | |
2693 | gen_op_set_cc_op(s->cc_op); | |
a2cc3b24 | 2694 | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { |
a7812ae4 | 2695 | gen_helper_reset_inhibit_irq(); |
a2cc3b24 | 2696 | } |
a2397807 JK |
2697 | if (s->tb->flags & HF_RF_MASK) { |
2698 | gen_helper_reset_rf(); | |
2699 | } | |
34865134 | 2700 | if (s->singlestep_enabled) { |
a7812ae4 | 2701 | gen_helper_debug(); |
34865134 | 2702 | } else if (s->tf) { |
a7812ae4 | 2703 | gen_helper_single_step(); |
2c0262af | 2704 | } else { |
57fec1fe | 2705 | tcg_gen_exit_tb(0); |
2c0262af | 2706 | } |
5779406a | 2707 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2708 | } |
2709 | ||
2710 | /* generate a jump to eip. No segment change must happen before as a | |
2711 | direct call to the next block may occur */ | |
14ce26e7 | 2712 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2c0262af | 2713 | { |
2c0262af | 2714 | if (s->jmp_opt) { |
728d803b | 2715 | gen_update_cc_op(s); |
6e256c93 | 2716 | gen_goto_tb(s, tb_num, eip); |
5779406a | 2717 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2718 | } else { |
14ce26e7 | 2719 | gen_jmp_im(eip); |
2c0262af FB |
2720 | gen_eob(s); |
2721 | } | |
2722 | } | |
2723 | ||
14ce26e7 FB |
2724 | static void gen_jmp(DisasContext *s, target_ulong eip) |
2725 | { | |
2726 | gen_jmp_tb(s, eip, 0); | |
2727 | } | |
2728 | ||
8686c490 FB |
2729 | static inline void gen_ldq_env_A0(int idx, int offset) |
2730 | { | |
2731 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2732 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2733 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); | |
8686c490 | 2734 | } |
664e0f19 | 2735 | |
8686c490 FB |
2736 | static inline void gen_stq_env_A0(int idx, int offset) |
2737 | { | |
2738 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2739 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
2740 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2741 | } |
664e0f19 | 2742 | |
8686c490 FB |
2743 | static inline void gen_ldo_env_A0(int idx, int offset) |
2744 | { | |
2745 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2746 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2747 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); | |
8686c490 | 2748 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2749 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2750 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); | |
8686c490 | 2751 | } |
14ce26e7 | 2752 | |
8686c490 FB |
2753 | static inline void gen_sto_env_A0(int idx, int offset) |
2754 | { | |
2755 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2756 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
2757 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2758 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2759 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
2760 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index); | |
8686c490 | 2761 | } |
14ce26e7 | 2762 | |
5af45186 FB |
2763 | static inline void gen_op_movo(int d_offset, int s_offset) |
2764 | { | |
b6abf97d FB |
2765 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2766 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
2767 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8); | |
2768 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8); | |
5af45186 FB |
2769 | } |
2770 | ||
2771 | static inline void gen_op_movq(int d_offset, int s_offset) | |
2772 | { | |
b6abf97d FB |
2773 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2774 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 FB |
2775 | } |
2776 | ||
2777 | static inline void gen_op_movl(int d_offset, int s_offset) | |
2778 | { | |
b6abf97d FB |
2779 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2780 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); | |
5af45186 FB |
2781 | } |
2782 | ||
2783 | static inline void gen_op_movq_env_0(int d_offset) | |
2784 | { | |
b6abf97d FB |
2785 | tcg_gen_movi_i64(cpu_tmp1_i64, 0); |
2786 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 | 2787 | } |
664e0f19 | 2788 | |
5af45186 FB |
2789 | #define SSE_SPECIAL ((void *)1) |
2790 | #define SSE_DUMMY ((void *)2) | |
664e0f19 | 2791 | |
a7812ae4 PB |
2792 | #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } |
2793 | #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ | |
2794 | gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } | |
5af45186 FB |
2795 | |
2796 | static void *sse_op_table1[256][4] = { | |
a35f3ec7 AJ |
2797 | /* 3DNow! extensions */ |
2798 | [0x0e] = { SSE_DUMMY }, /* femms */ | |
2799 | [0x0f] = { SSE_DUMMY }, /* pf... */ | |
664e0f19 FB |
2800 | /* pure SSE operations */ |
2801 | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
2802 | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
465e9838 | 2803 | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
664e0f19 | 2804 | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
a7812ae4 PB |
2805 | [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, |
2806 | [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2807 | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2808 | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ | |
2809 | ||
2810 | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2811 | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2812 | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ | |
d9f4bb27 | 2813 | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ |
664e0f19 FB |
2814 | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ |
2815 | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ | |
a7812ae4 PB |
2816 | [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, |
2817 | [0x2f] = { gen_helper_comiss, gen_helper_comisd }, | |
664e0f19 FB |
2818 | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2819 | [0x51] = SSE_FOP(sqrt), | |
a7812ae4 PB |
2820 | [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, |
2821 | [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, | |
2822 | [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ | |
2823 | [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ | |
2824 | [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ | |
2825 | [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ | |
664e0f19 FB |
2826 | [0x58] = SSE_FOP(add), |
2827 | [0x59] = SSE_FOP(mul), | |
a7812ae4 PB |
2828 | [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, |
2829 | gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, | |
2830 | [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, | |
664e0f19 FB |
2831 | [0x5c] = SSE_FOP(sub), |
2832 | [0x5d] = SSE_FOP(min), | |
2833 | [0x5e] = SSE_FOP(div), | |
2834 | [0x5f] = SSE_FOP(max), | |
2835 | ||
2836 | [0xc2] = SSE_FOP(cmpeq), | |
a7812ae4 | 2837 | [0xc6] = { gen_helper_shufps, gen_helper_shufpd }, |
664e0f19 | 2838 | |
222a3336 AZ |
2839 | [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */ |
2840 | [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */ | |
4242b1bd | 2841 | |
664e0f19 FB |
2842 | /* MMX ops and their SSE extensions */ |
2843 | [0x60] = MMX_OP2(punpcklbw), | |
2844 | [0x61] = MMX_OP2(punpcklwd), | |
2845 | [0x62] = MMX_OP2(punpckldq), | |
2846 | [0x63] = MMX_OP2(packsswb), | |
2847 | [0x64] = MMX_OP2(pcmpgtb), | |
2848 | [0x65] = MMX_OP2(pcmpgtw), | |
2849 | [0x66] = MMX_OP2(pcmpgtl), | |
2850 | [0x67] = MMX_OP2(packuswb), | |
2851 | [0x68] = MMX_OP2(punpckhbw), | |
2852 | [0x69] = MMX_OP2(punpckhwd), | |
2853 | [0x6a] = MMX_OP2(punpckhdq), | |
2854 | [0x6b] = MMX_OP2(packssdw), | |
a7812ae4 PB |
2855 | [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, |
2856 | [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2857 | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2858 | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ | |
a7812ae4 PB |
2859 | [0x70] = { gen_helper_pshufw_mmx, |
2860 | gen_helper_pshufd_xmm, | |
2861 | gen_helper_pshufhw_xmm, | |
2862 | gen_helper_pshuflw_xmm }, | |
664e0f19 FB |
2863 | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2864 | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ | |
2865 | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ | |
2866 | [0x74] = MMX_OP2(pcmpeqb), | |
2867 | [0x75] = MMX_OP2(pcmpeqw), | |
2868 | [0x76] = MMX_OP2(pcmpeql), | |
a35f3ec7 | 2869 | [0x77] = { SSE_DUMMY }, /* emms */ |
d9f4bb27 AP |
2870 | [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ |
2871 | [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, | |
a7812ae4 PB |
2872 | [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, |
2873 | [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, | |
664e0f19 FB |
2874 | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2875 | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ | |
2876 | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ | |
2877 | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ | |
a7812ae4 | 2878 | [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, |
664e0f19 FB |
2879 | [0xd1] = MMX_OP2(psrlw), |
2880 | [0xd2] = MMX_OP2(psrld), | |
2881 | [0xd3] = MMX_OP2(psrlq), | |
2882 | [0xd4] = MMX_OP2(paddq), | |
2883 | [0xd5] = MMX_OP2(pmullw), | |
2884 | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2885 | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ | |
2886 | [0xd8] = MMX_OP2(psubusb), | |
2887 | [0xd9] = MMX_OP2(psubusw), | |
2888 | [0xda] = MMX_OP2(pminub), | |
2889 | [0xdb] = MMX_OP2(pand), | |
2890 | [0xdc] = MMX_OP2(paddusb), | |
2891 | [0xdd] = MMX_OP2(paddusw), | |
2892 | [0xde] = MMX_OP2(pmaxub), | |
2893 | [0xdf] = MMX_OP2(pandn), | |
2894 | [0xe0] = MMX_OP2(pavgb), | |
2895 | [0xe1] = MMX_OP2(psraw), | |
2896 | [0xe2] = MMX_OP2(psrad), | |
2897 | [0xe3] = MMX_OP2(pavgw), | |
2898 | [0xe4] = MMX_OP2(pmulhuw), | |
2899 | [0xe5] = MMX_OP2(pmulhw), | |
a7812ae4 | 2900 | [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, |
664e0f19 FB |
2901 | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
2902 | [0xe8] = MMX_OP2(psubsb), | |
2903 | [0xe9] = MMX_OP2(psubsw), | |
2904 | [0xea] = MMX_OP2(pminsw), | |
2905 | [0xeb] = MMX_OP2(por), | |
2906 | [0xec] = MMX_OP2(paddsb), | |
2907 | [0xed] = MMX_OP2(paddsw), | |
2908 | [0xee] = MMX_OP2(pmaxsw), | |
2909 | [0xef] = MMX_OP2(pxor), | |
465e9838 | 2910 | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
664e0f19 FB |
2911 | [0xf1] = MMX_OP2(psllw), |
2912 | [0xf2] = MMX_OP2(pslld), | |
2913 | [0xf3] = MMX_OP2(psllq), | |
2914 | [0xf4] = MMX_OP2(pmuludq), | |
2915 | [0xf5] = MMX_OP2(pmaddwd), | |
2916 | [0xf6] = MMX_OP2(psadbw), | |
2917 | [0xf7] = MMX_OP2(maskmov), | |
2918 | [0xf8] = MMX_OP2(psubb), | |
2919 | [0xf9] = MMX_OP2(psubw), | |
2920 | [0xfa] = MMX_OP2(psubl), | |
2921 | [0xfb] = MMX_OP2(psubq), | |
2922 | [0xfc] = MMX_OP2(paddb), | |
2923 | [0xfd] = MMX_OP2(paddw), | |
2924 | [0xfe] = MMX_OP2(paddl), | |
2925 | }; | |
2926 | ||
5af45186 | 2927 | static void *sse_op_table2[3 * 8][2] = { |
664e0f19 FB |
2928 | [0 + 2] = MMX_OP2(psrlw), |
2929 | [0 + 4] = MMX_OP2(psraw), | |
2930 | [0 + 6] = MMX_OP2(psllw), | |
2931 | [8 + 2] = MMX_OP2(psrld), | |
2932 | [8 + 4] = MMX_OP2(psrad), | |
2933 | [8 + 6] = MMX_OP2(pslld), | |
2934 | [16 + 2] = MMX_OP2(psrlq), | |
a7812ae4 | 2935 | [16 + 3] = { NULL, gen_helper_psrldq_xmm }, |
664e0f19 | 2936 | [16 + 6] = MMX_OP2(psllq), |
a7812ae4 | 2937 | [16 + 7] = { NULL, gen_helper_pslldq_xmm }, |
664e0f19 FB |
2938 | }; |
2939 | ||
5af45186 | 2940 | static void *sse_op_table3[4 * 3] = { |
a7812ae4 PB |
2941 | gen_helper_cvtsi2ss, |
2942 | gen_helper_cvtsi2sd, | |
2943 | X86_64_ONLY(gen_helper_cvtsq2ss), | |
2944 | X86_64_ONLY(gen_helper_cvtsq2sd), | |
2945 | ||
2946 | gen_helper_cvttss2si, | |
2947 | gen_helper_cvttsd2si, | |
2948 | X86_64_ONLY(gen_helper_cvttss2sq), | |
2949 | X86_64_ONLY(gen_helper_cvttsd2sq), | |
2950 | ||
2951 | gen_helper_cvtss2si, | |
2952 | gen_helper_cvtsd2si, | |
2953 | X86_64_ONLY(gen_helper_cvtss2sq), | |
2954 | X86_64_ONLY(gen_helper_cvtsd2sq), | |
664e0f19 | 2955 | }; |
3b46e624 | 2956 | |
5af45186 | 2957 | static void *sse_op_table4[8][4] = { |
664e0f19 FB |
2958 | SSE_FOP(cmpeq), |
2959 | SSE_FOP(cmplt), | |
2960 | SSE_FOP(cmple), | |
2961 | SSE_FOP(cmpunord), | |
2962 | SSE_FOP(cmpneq), | |
2963 | SSE_FOP(cmpnlt), | |
2964 | SSE_FOP(cmpnle), | |
2965 | SSE_FOP(cmpord), | |
2966 | }; | |
3b46e624 | 2967 | |
5af45186 | 2968 | static void *sse_op_table5[256] = { |
a7812ae4 PB |
2969 | [0x0c] = gen_helper_pi2fw, |
2970 | [0x0d] = gen_helper_pi2fd, | |
2971 | [0x1c] = gen_helper_pf2iw, | |
2972 | [0x1d] = gen_helper_pf2id, | |
2973 | [0x8a] = gen_helper_pfnacc, | |
2974 | [0x8e] = gen_helper_pfpnacc, | |
2975 | [0x90] = gen_helper_pfcmpge, | |
2976 | [0x94] = gen_helper_pfmin, | |
2977 | [0x96] = gen_helper_pfrcp, | |
2978 | [0x97] = gen_helper_pfrsqrt, | |
2979 | [0x9a] = gen_helper_pfsub, | |
2980 | [0x9e] = gen_helper_pfadd, | |
2981 | [0xa0] = gen_helper_pfcmpgt, | |
2982 | [0xa4] = gen_helper_pfmax, | |
2983 | [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ | |
2984 | [0xa7] = gen_helper_movq, /* pfrsqit1 */ | |
2985 | [0xaa] = gen_helper_pfsubr, | |
2986 | [0xae] = gen_helper_pfacc, | |
2987 | [0xb0] = gen_helper_pfcmpeq, | |
2988 | [0xb4] = gen_helper_pfmul, | |
2989 | [0xb6] = gen_helper_movq, /* pfrcpit2 */ | |
2990 | [0xb7] = gen_helper_pmulhrw_mmx, | |
2991 | [0xbb] = gen_helper_pswapd, | |
2992 | [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ | |
a35f3ec7 AJ |
2993 | }; |
2994 | ||
222a3336 AZ |
2995 | struct sse_op_helper_s { |
2996 | void *op[2]; uint32_t ext_mask; | |
2997 | }; | |
2998 | #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 } | |
a7812ae4 PB |
2999 | #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } |
3000 | #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } | |
222a3336 AZ |
3001 | #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } |
3002 | static struct sse_op_helper_s sse_op_table6[256] = { | |
3003 | [0x00] = SSSE3_OP(pshufb), | |
3004 | [0x01] = SSSE3_OP(phaddw), | |
3005 | [0x02] = SSSE3_OP(phaddd), | |
3006 | [0x03] = SSSE3_OP(phaddsw), | |
3007 | [0x04] = SSSE3_OP(pmaddubsw), | |
3008 | [0x05] = SSSE3_OP(phsubw), | |
3009 | [0x06] = SSSE3_OP(phsubd), | |
3010 | [0x07] = SSSE3_OP(phsubsw), | |
3011 | [0x08] = SSSE3_OP(psignb), | |
3012 | [0x09] = SSSE3_OP(psignw), | |
3013 | [0x0a] = SSSE3_OP(psignd), | |
3014 | [0x0b] = SSSE3_OP(pmulhrsw), | |
3015 | [0x10] = SSE41_OP(pblendvb), | |
3016 | [0x14] = SSE41_OP(blendvps), | |
3017 | [0x15] = SSE41_OP(blendvpd), | |
3018 | [0x17] = SSE41_OP(ptest), | |
3019 | [0x1c] = SSSE3_OP(pabsb), | |
3020 | [0x1d] = SSSE3_OP(pabsw), | |
3021 | [0x1e] = SSSE3_OP(pabsd), | |
3022 | [0x20] = SSE41_OP(pmovsxbw), | |
3023 | [0x21] = SSE41_OP(pmovsxbd), | |
3024 | [0x22] = SSE41_OP(pmovsxbq), | |
3025 | [0x23] = SSE41_OP(pmovsxwd), | |
3026 | [0x24] = SSE41_OP(pmovsxwq), | |
3027 | [0x25] = SSE41_OP(pmovsxdq), | |
3028 | [0x28] = SSE41_OP(pmuldq), | |
3029 | [0x29] = SSE41_OP(pcmpeqq), | |
3030 | [0x2a] = SSE41_SPECIAL, /* movntqda */ | |
3031 | [0x2b] = SSE41_OP(packusdw), | |
3032 | [0x30] = SSE41_OP(pmovzxbw), | |
3033 | [0x31] = SSE41_OP(pmovzxbd), | |
3034 | [0x32] = SSE41_OP(pmovzxbq), | |
3035 | [0x33] = SSE41_OP(pmovzxwd), | |
3036 | [0x34] = SSE41_OP(pmovzxwq), | |
3037 | [0x35] = SSE41_OP(pmovzxdq), | |
3038 | [0x37] = SSE42_OP(pcmpgtq), | |
3039 | [0x38] = SSE41_OP(pminsb), | |
3040 | [0x39] = SSE41_OP(pminsd), | |
3041 | [0x3a] = SSE41_OP(pminuw), | |
3042 | [0x3b] = SSE41_OP(pminud), | |
3043 | [0x3c] = SSE41_OP(pmaxsb), | |
3044 | [0x3d] = SSE41_OP(pmaxsd), | |
3045 | [0x3e] = SSE41_OP(pmaxuw), | |
3046 | [0x3f] = SSE41_OP(pmaxud), | |
3047 | [0x40] = SSE41_OP(pmulld), | |
3048 | [0x41] = SSE41_OP(phminposuw), | |
4242b1bd AZ |
3049 | }; |
3050 | ||
222a3336 AZ |
3051 | static struct sse_op_helper_s sse_op_table7[256] = { |
3052 | [0x08] = SSE41_OP(roundps), | |
3053 | [0x09] = SSE41_OP(roundpd), | |
3054 | [0x0a] = SSE41_OP(roundss), | |
3055 | [0x0b] = SSE41_OP(roundsd), | |
3056 | [0x0c] = SSE41_OP(blendps), | |
3057 | [0x0d] = SSE41_OP(blendpd), | |
3058 | [0x0e] = SSE41_OP(pblendw), | |
3059 | [0x0f] = SSSE3_OP(palignr), | |
3060 | [0x14] = SSE41_SPECIAL, /* pextrb */ | |
3061 | [0x15] = SSE41_SPECIAL, /* pextrw */ | |
3062 | [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ | |
3063 | [0x17] = SSE41_SPECIAL, /* extractps */ | |
3064 | [0x20] = SSE41_SPECIAL, /* pinsrb */ | |
3065 | [0x21] = SSE41_SPECIAL, /* insertps */ | |
3066 | [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ | |
3067 | [0x40] = SSE41_OP(dpps), | |
3068 | [0x41] = SSE41_OP(dppd), | |
3069 | [0x42] = SSE41_OP(mpsadbw), | |
3070 | [0x60] = SSE42_OP(pcmpestrm), | |
3071 | [0x61] = SSE42_OP(pcmpestri), | |
3072 | [0x62] = SSE42_OP(pcmpistrm), | |
3073 | [0x63] = SSE42_OP(pcmpistri), | |
4242b1bd AZ |
3074 | }; |
3075 | ||
664e0f19 FB |
3076 | static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) |
3077 | { | |
3078 | int b1, op1_offset, op2_offset, is_xmm, val, ot; | |
3079 | int modrm, mod, rm, reg, reg_addr, offset_addr; | |
5af45186 | 3080 | void *sse_op2; |
664e0f19 FB |
3081 | |
3082 | b &= 0xff; | |
5fafdf24 | 3083 | if (s->prefix & PREFIX_DATA) |
664e0f19 | 3084 | b1 = 1; |
5fafdf24 | 3085 | else if (s->prefix & PREFIX_REPZ) |
664e0f19 | 3086 | b1 = 2; |
5fafdf24 | 3087 | else if (s->prefix & PREFIX_REPNZ) |
664e0f19 FB |
3088 | b1 = 3; |
3089 | else | |
3090 | b1 = 0; | |
3091 | sse_op2 = sse_op_table1[b][b1]; | |
5fafdf24 | 3092 | if (!sse_op2) |
664e0f19 | 3093 | goto illegal_op; |
a35f3ec7 | 3094 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
664e0f19 FB |
3095 | is_xmm = 1; |
3096 | } else { | |
3097 | if (b1 == 0) { | |
3098 | /* MMX case */ | |
3099 | is_xmm = 0; | |
3100 | } else { | |
3101 | is_xmm = 1; | |
3102 | } | |
3103 | } | |
3104 | /* simple MMX/SSE operation */ | |
3105 | if (s->flags & HF_TS_MASK) { | |
3106 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
3107 | return; | |
3108 | } | |
3109 | if (s->flags & HF_EM_MASK) { | |
3110 | illegal_op: | |
3111 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
3112 | return; | |
3113 | } | |
3114 | if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) | |
4242b1bd AZ |
3115 | if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) |
3116 | goto illegal_op; | |
e771edab AJ |
3117 | if (b == 0x0e) { |
3118 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) | |
3119 | goto illegal_op; | |
3120 | /* femms */ | |
a7812ae4 | 3121 | gen_helper_emms(); |
e771edab AJ |
3122 | return; |
3123 | } | |
3124 | if (b == 0x77) { | |
3125 | /* emms */ | |
a7812ae4 | 3126 | gen_helper_emms(); |
664e0f19 FB |
3127 | return; |
3128 | } | |
3129 | /* prepare MMX state (XXX: optimize by storing fptt and fptags in | |
3130 | the static cpu state) */ | |
3131 | if (!is_xmm) { | |
a7812ae4 | 3132 | gen_helper_enter_mmx(); |
664e0f19 FB |
3133 | } |
3134 | ||
3135 | modrm = ldub_code(s->pc++); | |
3136 | reg = ((modrm >> 3) & 7); | |
3137 | if (is_xmm) | |
3138 | reg |= rex_r; | |
3139 | mod = (modrm >> 6) & 3; | |
3140 | if (sse_op2 == SSE_SPECIAL) { | |
3141 | b |= (b1 << 8); | |
3142 | switch(b) { | |
3143 | case 0x0e7: /* movntq */ | |
5fafdf24 | 3144 | if (mod == 3) |
664e0f19 FB |
3145 | goto illegal_op; |
3146 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3147 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3148 | break; |
3149 | case 0x1e7: /* movntdq */ | |
3150 | case 0x02b: /* movntps */ | |
3151 | case 0x12b: /* movntps */ | |
2e21e749 T |
3152 | if (mod == 3) |
3153 | goto illegal_op; | |
3154 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3155 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); | |
3156 | break; | |
465e9838 FB |
3157 | case 0x3f0: /* lddqu */ |
3158 | if (mod == 3) | |
664e0f19 FB |
3159 | goto illegal_op; |
3160 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
c2254920 | 3161 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 | 3162 | break; |
d9f4bb27 AP |
3163 | case 0x22b: /* movntss */ |
3164 | case 0x32b: /* movntsd */ | |
3165 | if (mod == 3) | |
3166 | goto illegal_op; | |
3167 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3168 | if (b1 & 1) { | |
3169 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State, | |
3170 | xmm_regs[reg])); | |
3171 | } else { | |
3172 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3173 | xmm_regs[reg].XMM_L(0))); | |
3174 | gen_op_st_T0_A0(OT_LONG + s->mem_index); | |
3175 | } | |
3176 | break; | |
664e0f19 | 3177 | case 0x6e: /* movd mm, ea */ |
dabd98dd FB |
3178 | #ifdef TARGET_X86_64 |
3179 | if (s->dflag == 2) { | |
3180 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); | |
5af45186 | 3181 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); |
5fafdf24 | 3182 | } else |
dabd98dd FB |
3183 | #endif |
3184 | { | |
3185 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); | |
5af45186 FB |
3186 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3187 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
a7812ae4 PB |
3188 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3189 | gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); | |
dabd98dd | 3190 | } |
664e0f19 FB |
3191 | break; |
3192 | case 0x16e: /* movd xmm, ea */ | |
dabd98dd FB |
3193 | #ifdef TARGET_X86_64 |
3194 | if (s->dflag == 2) { | |
3195 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); | |
5af45186 FB |
3196 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3197 | offsetof(CPUX86State,xmm_regs[reg])); | |
a7812ae4 | 3198 | gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); |
5fafdf24 | 3199 | } else |
dabd98dd FB |
3200 | #endif |
3201 | { | |
3202 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); | |
5af45186 FB |
3203 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3204 | offsetof(CPUX86State,xmm_regs[reg])); | |
b6abf97d | 3205 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 3206 | gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); |
dabd98dd | 3207 | } |
664e0f19 FB |
3208 | break; |
3209 | case 0x6f: /* movq mm, ea */ | |
3210 | if (mod != 3) { | |
3211 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3212 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3213 | } else { |
3214 | rm = (modrm & 7); | |
b6abf97d | 3215 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3216 | offsetof(CPUX86State,fpregs[rm].mmx)); |
b6abf97d | 3217 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3218 | offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3219 | } |
3220 | break; | |
3221 | case 0x010: /* movups */ | |
3222 | case 0x110: /* movupd */ | |
3223 | case 0x028: /* movaps */ | |
3224 | case 0x128: /* movapd */ | |
3225 | case 0x16f: /* movdqa xmm, ea */ | |
3226 | case 0x26f: /* movdqu xmm, ea */ | |
3227 | if (mod != 3) { | |
3228 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3229 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3230 | } else { |
3231 | rm = (modrm & 7) | REX_B(s); | |
3232 | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), | |
3233 | offsetof(CPUX86State,xmm_regs[rm])); | |
3234 | } | |
3235 | break; | |
3236 | case 0x210: /* movss xmm, ea */ | |
3237 | if (mod != 3) { | |
3238 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 3239 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3240 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
664e0f19 | 3241 | gen_op_movl_T0_0(); |
651ba608 FB |
3242 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); |
3243 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3244 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3245 | } else { |
3246 | rm = (modrm & 7) | REX_B(s); | |
3247 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3248 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3249 | } | |
3250 | break; | |
3251 | case 0x310: /* movsd xmm, ea */ | |
3252 | if (mod != 3) { | |
3253 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3254 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 | 3255 | gen_op_movl_T0_0(); |
651ba608 FB |
3256 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3257 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3258 | } else { |
3259 | rm = (modrm & 7) | REX_B(s); | |
3260 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3261 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3262 | } | |
3263 | break; | |
3264 | case 0x012: /* movlps */ | |
3265 | case 0x112: /* movlpd */ | |
3266 | if (mod != 3) { | |
3267 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3268 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3269 | } else { |
3270 | /* movhlps */ | |
3271 | rm = (modrm & 7) | REX_B(s); | |
3272 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3273 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3274 | } | |
3275 | break; | |
465e9838 FB |
3276 | case 0x212: /* movsldup */ |
3277 | if (mod != 3) { | |
3278 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3279 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
465e9838 FB |
3280 | } else { |
3281 | rm = (modrm & 7) | REX_B(s); | |
3282 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3283 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3284 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3285 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); | |
3286 | } | |
3287 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3288 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3289 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3290 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3291 | break; | |
3292 | case 0x312: /* movddup */ | |
3293 | if (mod != 3) { | |
3294 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3295 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 FB |
3296 | } else { |
3297 | rm = (modrm & 7) | REX_B(s); | |
3298 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3299 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3300 | } | |
3301 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
ba6526df | 3302 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 | 3303 | break; |
664e0f19 FB |
3304 | case 0x016: /* movhps */ |
3305 | case 0x116: /* movhpd */ | |
3306 | if (mod != 3) { | |
3307 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3308 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3309 | } else { |
3310 | /* movlhps */ | |
3311 | rm = (modrm & 7) | REX_B(s); | |
3312 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
3313 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3314 | } | |
3315 | break; | |
3316 | case 0x216: /* movshdup */ | |
3317 | if (mod != 3) { | |
3318 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3319 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3320 | } else { |
3321 | rm = (modrm & 7) | REX_B(s); | |
3322 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3323 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); | |
3324 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3325 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); | |
3326 | } | |
3327 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3328 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); | |
3329 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3330 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
3331 | break; | |
d9f4bb27 AP |
3332 | case 0x178: |
3333 | case 0x378: | |
3334 | { | |
3335 | int bit_index, field_length; | |
3336 | ||
3337 | if (b1 == 1 && reg != 0) | |
3338 | goto illegal_op; | |
3339 | field_length = ldub_code(s->pc++) & 0x3F; | |
3340 | bit_index = ldub_code(s->pc++) & 0x3F; | |
3341 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, | |
3342 | offsetof(CPUX86State,xmm_regs[reg])); | |
3343 | if (b1 == 1) | |
3344 | gen_helper_extrq_i(cpu_ptr0, tcg_const_i32(bit_index), | |
3345 | tcg_const_i32(field_length)); | |
3346 | else | |
3347 | gen_helper_insertq_i(cpu_ptr0, tcg_const_i32(bit_index), | |
3348 | tcg_const_i32(field_length)); | |
3349 | } | |
3350 | break; | |
664e0f19 | 3351 | case 0x7e: /* movd ea, mm */ |
dabd98dd FB |
3352 | #ifdef TARGET_X86_64 |
3353 | if (s->dflag == 2) { | |
5af45186 FB |
3354 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3355 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
dabd98dd | 3356 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3357 | } else |
dabd98dd FB |
3358 | #endif |
3359 | { | |
5af45186 FB |
3360 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3361 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); | |
dabd98dd FB |
3362 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); |
3363 | } | |
664e0f19 FB |
3364 | break; |
3365 | case 0x17e: /* movd ea, xmm */ | |
dabd98dd FB |
3366 | #ifdef TARGET_X86_64 |
3367 | if (s->dflag == 2) { | |
5af45186 FB |
3368 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3369 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
dabd98dd | 3370 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3371 | } else |
dabd98dd FB |
3372 | #endif |
3373 | { | |
5af45186 FB |
3374 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3375 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
dabd98dd FB |
3376 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); |
3377 | } | |
664e0f19 FB |
3378 | break; |
3379 | case 0x27e: /* movq xmm, ea */ | |
3380 | if (mod != 3) { | |
3381 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3382 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3383 | } else { |
3384 | rm = (modrm & 7) | REX_B(s); | |
3385 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3386 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3387 | } | |
3388 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
3389 | break; | |
3390 | case 0x7f: /* movq ea, mm */ | |
3391 | if (mod != 3) { | |
3392 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3393 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3394 | } else { |
3395 | rm = (modrm & 7); | |
3396 | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), | |
3397 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
3398 | } | |
3399 | break; | |
3400 | case 0x011: /* movups */ | |
3401 | case 0x111: /* movupd */ | |
3402 | case 0x029: /* movaps */ | |
3403 | case 0x129: /* movapd */ | |
3404 | case 0x17f: /* movdqa ea, xmm */ | |
3405 | case 0x27f: /* movdqu ea, xmm */ | |
3406 | if (mod != 3) { | |
3407 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3408 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3409 | } else { |
3410 | rm = (modrm & 7) | REX_B(s); | |
3411 | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), | |
3412 | offsetof(CPUX86State,xmm_regs[reg])); | |
3413 | } | |
3414 | break; | |
3415 | case 0x211: /* movss ea, xmm */ | |
3416 | if (mod != 3) { | |
3417 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
651ba608 | 3418 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
57fec1fe | 3419 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
664e0f19 FB |
3420 | } else { |
3421 | rm = (modrm & 7) | REX_B(s); | |
3422 | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), | |
3423 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3424 | } | |
3425 | break; | |
3426 | case 0x311: /* movsd ea, xmm */ | |
3427 | if (mod != 3) { | |
3428 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3429 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3430 | } else { |
3431 | rm = (modrm & 7) | REX_B(s); | |
3432 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3433 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3434 | } | |
3435 | break; | |
3436 | case 0x013: /* movlps */ | |
3437 | case 0x113: /* movlpd */ | |
3438 | if (mod != 3) { | |
3439 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3440 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3441 | } else { |
3442 | goto illegal_op; | |
3443 | } | |
3444 | break; | |
3445 | case 0x017: /* movhps */ | |
3446 | case 0x117: /* movhpd */ | |
3447 | if (mod != 3) { | |
3448 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3449 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3450 | } else { |
3451 | goto illegal_op; | |
3452 | } | |
3453 | break; | |
3454 | case 0x71: /* shift mm, im */ | |
3455 | case 0x72: | |
3456 | case 0x73: | |
3457 | case 0x171: /* shift xmm, im */ | |
3458 | case 0x172: | |
3459 | case 0x173: | |
c045af25 AK |
3460 | if (b1 >= 2) { |
3461 | goto illegal_op; | |
3462 | } | |
664e0f19 FB |
3463 | val = ldub_code(s->pc++); |
3464 | if (is_xmm) { | |
3465 | gen_op_movl_T0_im(val); | |
651ba608 | 3466 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 | 3467 | gen_op_movl_T0_0(); |
651ba608 | 3468 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); |
664e0f19 FB |
3469 | op1_offset = offsetof(CPUX86State,xmm_t0); |
3470 | } else { | |
3471 | gen_op_movl_T0_im(val); | |
651ba608 | 3472 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); |
664e0f19 | 3473 | gen_op_movl_T0_0(); |
651ba608 | 3474 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); |
664e0f19 FB |
3475 | op1_offset = offsetof(CPUX86State,mmx_t0); |
3476 | } | |
3477 | sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1]; | |
3478 | if (!sse_op2) | |
3479 | goto illegal_op; | |
3480 | if (is_xmm) { | |
3481 | rm = (modrm & 7) | REX_B(s); | |
3482 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3483 | } else { | |
3484 | rm = (modrm & 7); | |
3485 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3486 | } | |
5af45186 FB |
3487 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3488 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); | |
a7812ae4 | 3489 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3490 | break; |
3491 | case 0x050: /* movmskps */ | |
664e0f19 | 3492 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3493 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3494 | offsetof(CPUX86State,xmm_regs[rm])); | |
a7812ae4 | 3495 | gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0); |
b6abf97d | 3496 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3497 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3498 | break; |
3499 | case 0x150: /* movmskpd */ | |
664e0f19 | 3500 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3501 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3502 | offsetof(CPUX86State,xmm_regs[rm])); | |
a7812ae4 | 3503 | gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0); |
b6abf97d | 3504 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3505 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3506 | break; |
3507 | case 0x02a: /* cvtpi2ps */ | |
3508 | case 0x12a: /* cvtpi2pd */ | |
a7812ae4 | 3509 | gen_helper_enter_mmx(); |
664e0f19 FB |
3510 | if (mod != 3) { |
3511 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3512 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
8686c490 | 3513 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3514 | } else { |
3515 | rm = (modrm & 7); | |
3516 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3517 | } | |
3518 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3519 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3520 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3521 | switch(b >> 8) { |
3522 | case 0x0: | |
a7812ae4 | 3523 | gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3524 | break; |
3525 | default: | |
3526 | case 0x1: | |
a7812ae4 | 3527 | gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3528 | break; |
3529 | } | |
3530 | break; | |
3531 | case 0x22a: /* cvtsi2ss */ | |
3532 | case 0x32a: /* cvtsi2sd */ | |
3533 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3534 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
3535 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3536 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3537 | sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)]; | |
28e10711 FB |
3538 | if (ot == OT_LONG) { |
3539 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
a7812ae4 | 3540 | ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32); |
28e10711 | 3541 | } else { |
a7812ae4 | 3542 | ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]); |
28e10711 | 3543 | } |
664e0f19 FB |
3544 | break; |
3545 | case 0x02c: /* cvttps2pi */ | |
3546 | case 0x12c: /* cvttpd2pi */ | |
3547 | case 0x02d: /* cvtps2pi */ | |
3548 | case 0x12d: /* cvtpd2pi */ | |
a7812ae4 | 3549 | gen_helper_enter_mmx(); |
664e0f19 FB |
3550 | if (mod != 3) { |
3551 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3552 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
8686c490 | 3553 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3554 | } else { |
3555 | rm = (modrm & 7) | REX_B(s); | |
3556 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3557 | } | |
3558 | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx); | |
5af45186 FB |
3559 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3560 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3561 | switch(b) { |
3562 | case 0x02c: | |
a7812ae4 | 3563 | gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3564 | break; |
3565 | case 0x12c: | |
a7812ae4 | 3566 | gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3567 | break; |
3568 | case 0x02d: | |
a7812ae4 | 3569 | gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3570 | break; |
3571 | case 0x12d: | |
a7812ae4 | 3572 | gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3573 | break; |
3574 | } | |
3575 | break; | |
3576 | case 0x22c: /* cvttss2si */ | |
3577 | case 0x32c: /* cvttsd2si */ | |
3578 | case 0x22d: /* cvtss2si */ | |
3579 | case 0x32d: /* cvtsd2si */ | |
3580 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
31313213 FB |
3581 | if (mod != 3) { |
3582 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3583 | if ((b >> 8) & 1) { | |
8686c490 | 3584 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))); |
31313213 | 3585 | } else { |
57fec1fe | 3586 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3587 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
31313213 FB |
3588 | } |
3589 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3590 | } else { | |
3591 | rm = (modrm & 7) | REX_B(s); | |
3592 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3593 | } | |
5af45186 FB |
3594 | sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 + |
3595 | (b & 1) * 4]; | |
3596 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); | |
3597 | if (ot == OT_LONG) { | |
a7812ae4 | 3598 | ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0); |
b6abf97d | 3599 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
5af45186 | 3600 | } else { |
a7812ae4 | 3601 | ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0); |
5af45186 | 3602 | } |
57fec1fe | 3603 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3604 | break; |
3605 | case 0xc4: /* pinsrw */ | |
5fafdf24 | 3606 | case 0x1c4: |
d1e42c5c | 3607 | s->rip_offset = 1; |
664e0f19 FB |
3608 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
3609 | val = ldub_code(s->pc++); | |
3610 | if (b1) { | |
3611 | val &= 7; | |
5af45186 FB |
3612 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3613 | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); | |
664e0f19 FB |
3614 | } else { |
3615 | val &= 3; | |
5af45186 FB |
3616 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3617 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); | |
664e0f19 FB |
3618 | } |
3619 | break; | |
3620 | case 0xc5: /* pextrw */ | |
5fafdf24 | 3621 | case 0x1c5: |
664e0f19 FB |
3622 | if (mod != 3) |
3623 | goto illegal_op; | |
6dc2d0da | 3624 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
664e0f19 FB |
3625 | val = ldub_code(s->pc++); |
3626 | if (b1) { | |
3627 | val &= 7; | |
3628 | rm = (modrm & 7) | REX_B(s); | |
5af45186 FB |
3629 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3630 | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); | |
664e0f19 FB |
3631 | } else { |
3632 | val &= 3; | |
3633 | rm = (modrm & 7); | |
5af45186 FB |
3634 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3635 | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); | |
664e0f19 FB |
3636 | } |
3637 | reg = ((modrm >> 3) & 7) | rex_r; | |
6dc2d0da | 3638 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3639 | break; |
3640 | case 0x1d6: /* movq ea, xmm */ | |
3641 | if (mod != 3) { | |
3642 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3643 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3644 | } else { |
3645 | rm = (modrm & 7) | REX_B(s); | |
3646 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3647 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3648 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3649 | } | |
3650 | break; | |
3651 | case 0x2d6: /* movq2dq */ | |
a7812ae4 | 3652 | gen_helper_enter_mmx(); |
480c1cdb FB |
3653 | rm = (modrm & 7); |
3654 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3655 | offsetof(CPUX86State,fpregs[rm].mmx)); | |
3656 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3657 | break; |
3658 | case 0x3d6: /* movdq2q */ | |
a7812ae4 | 3659 | gen_helper_enter_mmx(); |
480c1cdb FB |
3660 | rm = (modrm & 7) | REX_B(s); |
3661 | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), | |
3662 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
664e0f19 FB |
3663 | break; |
3664 | case 0xd7: /* pmovmskb */ | |
3665 | case 0x1d7: | |
3666 | if (mod != 3) | |
3667 | goto illegal_op; | |
3668 | if (b1) { | |
3669 | rm = (modrm & 7) | REX_B(s); | |
5af45186 | 3670 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
a7812ae4 | 3671 | gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0); |
664e0f19 FB |
3672 | } else { |
3673 | rm = (modrm & 7); | |
5af45186 | 3674 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
a7812ae4 | 3675 | gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0); |
664e0f19 | 3676 | } |
b6abf97d | 3677 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
664e0f19 | 3678 | reg = ((modrm >> 3) & 7) | rex_r; |
57fec1fe | 3679 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 | 3680 | break; |
4242b1bd | 3681 | case 0x138: |
000cacf6 AZ |
3682 | if (s->prefix & PREFIX_REPNZ) |
3683 | goto crc32; | |
3684 | case 0x038: | |
4242b1bd AZ |
3685 | b = modrm; |
3686 | modrm = ldub_code(s->pc++); | |
3687 | rm = modrm & 7; | |
3688 | reg = ((modrm >> 3) & 7) | rex_r; | |
3689 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3690 | if (b1 >= 2) { |
3691 | goto illegal_op; | |
3692 | } | |
4242b1bd | 3693 | |
222a3336 | 3694 | sse_op2 = sse_op_table6[b].op[b1]; |
4242b1bd AZ |
3695 | if (!sse_op2) |
3696 | goto illegal_op; | |
222a3336 AZ |
3697 | if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask)) |
3698 | goto illegal_op; | |
4242b1bd AZ |
3699 | |
3700 | if (b1) { | |
3701 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3702 | if (mod == 3) { | |
3703 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3704 | } else { | |
3705 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3706 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
222a3336 AZ |
3707 | switch (b) { |
3708 | case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ | |
3709 | case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ | |
3710 | case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ | |
3711 | gen_ldq_env_A0(s->mem_index, op2_offset + | |
3712 | offsetof(XMMReg, XMM_Q(0))); | |
3713 | break; | |
3714 | case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ | |
3715 | case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ | |
a7812ae4 | 3716 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3717 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3718 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3719 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + |
3720 | offsetof(XMMReg, XMM_L(0))); | |
3721 | break; | |
3722 | case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ | |
3723 | tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, | |
3724 | (s->mem_index >> 2) - 1); | |
3725 | tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + | |
3726 | offsetof(XMMReg, XMM_W(0))); | |
3727 | break; | |
3728 | case 0x2a: /* movntqda */ | |
3729 | gen_ldo_env_A0(s->mem_index, op1_offset); | |
3730 | return; | |
3731 | default: | |
3732 | gen_ldo_env_A0(s->mem_index, op2_offset); | |
3733 | } | |
4242b1bd AZ |
3734 | } |
3735 | } else { | |
3736 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3737 | if (mod == 3) { | |
3738 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3739 | } else { | |
3740 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
3741 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3742 | gen_ldq_env_A0(s->mem_index, op2_offset); | |
3743 | } | |
3744 | } | |
222a3336 AZ |
3745 | if (sse_op2 == SSE_SPECIAL) |
3746 | goto illegal_op; | |
3747 | ||
4242b1bd AZ |
3748 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3749 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 3750 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
222a3336 AZ |
3751 | |
3752 | if (b == 0x17) | |
3753 | s->cc_op = CC_OP_EFLAGS; | |
4242b1bd | 3754 | break; |
222a3336 AZ |
3755 | case 0x338: /* crc32 */ |
3756 | crc32: | |
3757 | b = modrm; | |
3758 | modrm = ldub_code(s->pc++); | |
3759 | reg = ((modrm >> 3) & 7) | rex_r; | |
3760 | ||
3761 | if (b != 0xf0 && b != 0xf1) | |
3762 | goto illegal_op; | |
3763 | if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) | |
4242b1bd AZ |
3764 | goto illegal_op; |
3765 | ||
222a3336 AZ |
3766 | if (b == 0xf0) |
3767 | ot = OT_BYTE; | |
3768 | else if (b == 0xf1 && s->dflag != 2) | |
3769 | if (s->prefix & PREFIX_DATA) | |
3770 | ot = OT_WORD; | |
3771 | else | |
3772 | ot = OT_LONG; | |
3773 | else | |
3774 | ot = OT_QUAD; | |
3775 | ||
3776 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
3777 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
3778 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
a7812ae4 PB |
3779 | gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, |
3780 | cpu_T[0], tcg_const_i32(8 << ot)); | |
222a3336 AZ |
3781 | |
3782 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3783 | gen_op_mov_reg_T0(ot, reg); | |
3784 | break; | |
3785 | case 0x03a: | |
3786 | case 0x13a: | |
4242b1bd AZ |
3787 | b = modrm; |
3788 | modrm = ldub_code(s->pc++); | |
3789 | rm = modrm & 7; | |
3790 | reg = ((modrm >> 3) & 7) | rex_r; | |
3791 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3792 | if (b1 >= 2) { |
3793 | goto illegal_op; | |
3794 | } | |
4242b1bd | 3795 | |
222a3336 | 3796 | sse_op2 = sse_op_table7[b].op[b1]; |
4242b1bd AZ |
3797 | if (!sse_op2) |
3798 | goto illegal_op; | |
222a3336 AZ |
3799 | if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) |
3800 | goto illegal_op; | |
3801 | ||
3802 | if (sse_op2 == SSE_SPECIAL) { | |
3803 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3804 | rm = (modrm & 7) | REX_B(s); | |
3805 | if (mod != 3) | |
3806 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3807 | reg = ((modrm >> 3) & 7) | rex_r; | |
3808 | val = ldub_code(s->pc++); | |
3809 | switch (b) { | |
3810 | case 0x14: /* pextrb */ | |
3811 | tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3812 | xmm_regs[reg].XMM_B(val & 15))); | |
3813 | if (mod == 3) | |
3814 | gen_op_mov_reg_T0(ot, rm); | |
3815 | else | |
3816 | tcg_gen_qemu_st8(cpu_T[0], cpu_A0, | |
3817 | (s->mem_index >> 2) - 1); | |
3818 | break; | |
3819 | case 0x15: /* pextrw */ | |
3820 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3821 | xmm_regs[reg].XMM_W(val & 7))); | |
3822 | if (mod == 3) | |
3823 | gen_op_mov_reg_T0(ot, rm); | |
3824 | else | |
3825 | tcg_gen_qemu_st16(cpu_T[0], cpu_A0, | |
3826 | (s->mem_index >> 2) - 1); | |
3827 | break; | |
3828 | case 0x16: | |
3829 | if (ot == OT_LONG) { /* pextrd */ | |
3830 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, | |
3831 | offsetof(CPUX86State, | |
3832 | xmm_regs[reg].XMM_L(val & 3))); | |
a7812ae4 | 3833 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
222a3336 | 3834 | if (mod == 3) |
a7812ae4 | 3835 | gen_op_mov_reg_v(ot, rm, cpu_T[0]); |
222a3336 | 3836 | else |
a7812ae4 | 3837 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, |
222a3336 AZ |
3838 | (s->mem_index >> 2) - 1); |
3839 | } else { /* pextrq */ | |
a7812ae4 | 3840 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3841 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
3842 | offsetof(CPUX86State, | |
3843 | xmm_regs[reg].XMM_Q(val & 1))); | |
3844 | if (mod == 3) | |
3845 | gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); | |
3846 | else | |
3847 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, | |
3848 | (s->mem_index >> 2) - 1); | |
a7812ae4 PB |
3849 | #else |
3850 | goto illegal_op; | |
3851 | #endif | |
222a3336 AZ |
3852 | } |
3853 | break; | |
3854 | case 0x17: /* extractps */ | |
3855 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3856 | xmm_regs[reg].XMM_L(val & 3))); | |
3857 | if (mod == 3) | |
3858 | gen_op_mov_reg_T0(ot, rm); | |
3859 | else | |
3860 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, | |
3861 | (s->mem_index >> 2) - 1); | |
3862 | break; | |
3863 | case 0x20: /* pinsrb */ | |
3864 | if (mod == 3) | |
3865 | gen_op_mov_TN_reg(OT_LONG, 0, rm); | |
3866 | else | |
a7812ae4 | 3867 | tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0, |
222a3336 | 3868 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3869 | tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, |
222a3336 AZ |
3870 | xmm_regs[reg].XMM_B(val & 15))); |
3871 | break; | |
3872 | case 0x21: /* insertps */ | |
a7812ae4 | 3873 | if (mod == 3) { |
222a3336 AZ |
3874 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
3875 | offsetof(CPUX86State,xmm_regs[rm] | |
3876 | .XMM_L((val >> 6) & 3))); | |
a7812ae4 PB |
3877 | } else { |
3878 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, | |
222a3336 | 3879 | (s->mem_index >> 2) - 1); |
a7812ae4 PB |
3880 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
3881 | } | |
222a3336 AZ |
3882 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3883 | offsetof(CPUX86State,xmm_regs[reg] | |
3884 | .XMM_L((val >> 4) & 3))); | |
3885 | if ((val >> 0) & 1) | |
3886 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3887 | cpu_env, offsetof(CPUX86State, | |
3888 | xmm_regs[reg].XMM_L(0))); | |
3889 | if ((val >> 1) & 1) | |
3890 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3891 | cpu_env, offsetof(CPUX86State, | |
3892 | xmm_regs[reg].XMM_L(1))); | |
3893 | if ((val >> 2) & 1) | |
3894 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3895 | cpu_env, offsetof(CPUX86State, | |
3896 | xmm_regs[reg].XMM_L(2))); | |
3897 | if ((val >> 3) & 1) | |
3898 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3899 | cpu_env, offsetof(CPUX86State, | |
3900 | xmm_regs[reg].XMM_L(3))); | |
3901 | break; | |
3902 | case 0x22: | |
3903 | if (ot == OT_LONG) { /* pinsrd */ | |
3904 | if (mod == 3) | |
a7812ae4 | 3905 | gen_op_mov_v_reg(ot, cpu_tmp0, rm); |
222a3336 | 3906 | else |
a7812ae4 | 3907 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3908 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3909 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3910 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3911 | offsetof(CPUX86State, | |
3912 | xmm_regs[reg].XMM_L(val & 3))); | |
3913 | } else { /* pinsrq */ | |
a7812ae4 | 3914 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3915 | if (mod == 3) |
3916 | gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); | |
3917 | else | |
3918 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, | |
3919 | (s->mem_index >> 2) - 1); | |
3920 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, | |
3921 | offsetof(CPUX86State, | |
3922 | xmm_regs[reg].XMM_Q(val & 1))); | |
a7812ae4 PB |
3923 | #else |
3924 | goto illegal_op; | |
3925 | #endif | |
222a3336 AZ |
3926 | } |
3927 | break; | |
3928 | } | |
3929 | return; | |
3930 | } | |
4242b1bd AZ |
3931 | |
3932 | if (b1) { | |
3933 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3934 | if (mod == 3) { | |
3935 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3936 | } else { | |
3937 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3938 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3939 | gen_ldo_env_A0(s->mem_index, op2_offset); | |
3940 | } | |
3941 | } else { | |
3942 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3943 | if (mod == 3) { | |
3944 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3945 | } else { | |
3946 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
3947 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3948 | gen_ldq_env_A0(s->mem_index, op2_offset); | |
3949 | } | |
3950 | } | |
3951 | val = ldub_code(s->pc++); | |
3952 | ||
222a3336 AZ |
3953 | if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ |
3954 | s->cc_op = CC_OP_EFLAGS; | |
3955 | ||
3956 | if (s->dflag == 2) | |
3957 | /* The helper must use entire 64-bit gp registers */ | |
3958 | val |= 1 << 8; | |
3959 | } | |
3960 | ||
4242b1bd AZ |
3961 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3962 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 3963 | ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
4242b1bd | 3964 | break; |
664e0f19 FB |
3965 | default: |
3966 | goto illegal_op; | |
3967 | } | |
3968 | } else { | |
3969 | /* generic MMX or SSE operation */ | |
d1e42c5c | 3970 | switch(b) { |
d1e42c5c FB |
3971 | case 0x70: /* pshufx insn */ |
3972 | case 0xc6: /* pshufx insn */ | |
3973 | case 0xc2: /* compare insns */ | |
3974 | s->rip_offset = 1; | |
3975 | break; | |
3976 | default: | |
3977 | break; | |
664e0f19 FB |
3978 | } |
3979 | if (is_xmm) { | |
3980 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3981 | if (mod != 3) { | |
3982 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3983 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
480c1cdb | 3984 | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
664e0f19 FB |
3985 | b == 0xc2)) { |
3986 | /* specific case for SSE single instructions */ | |
3987 | if (b1 == 2) { | |
3988 | /* 32 bit access */ | |
57fec1fe | 3989 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3990 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 FB |
3991 | } else { |
3992 | /* 64 bit access */ | |
8686c490 | 3993 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0))); |
664e0f19 FB |
3994 | } |
3995 | } else { | |
8686c490 | 3996 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3997 | } |
3998 | } else { | |
3999 | rm = (modrm & 7) | REX_B(s); | |
4000 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
4001 | } | |
4002 | } else { | |
4003 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4004 | if (mod != 3) { | |
4005 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4006 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
8686c490 | 4007 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
4008 | } else { |
4009 | rm = (modrm & 7); | |
4010 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4011 | } | |
4012 | } | |
4013 | switch(b) { | |
a35f3ec7 | 4014 | case 0x0f: /* 3DNow! data insns */ |
e771edab AJ |
4015 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) |
4016 | goto illegal_op; | |
a35f3ec7 AJ |
4017 | val = ldub_code(s->pc++); |
4018 | sse_op2 = sse_op_table5[val]; | |
4019 | if (!sse_op2) | |
4020 | goto illegal_op; | |
5af45186 FB |
4021 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4022 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 4023 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
a35f3ec7 | 4024 | break; |
664e0f19 FB |
4025 | case 0x70: /* pshufx insn */ |
4026 | case 0xc6: /* pshufx insn */ | |
4027 | val = ldub_code(s->pc++); | |
5af45186 FB |
4028 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4029 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 4030 | ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
664e0f19 FB |
4031 | break; |
4032 | case 0xc2: | |
4033 | /* compare insns */ | |
4034 | val = ldub_code(s->pc++); | |
4035 | if (val >= 8) | |
4036 | goto illegal_op; | |
4037 | sse_op2 = sse_op_table4[val][b1]; | |
5af45186 FB |
4038 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4039 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 4040 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
664e0f19 | 4041 | break; |
b8b6a50b FB |
4042 | case 0xf7: |
4043 | /* maskmov : we must prepare A0 */ | |
4044 | if (mod != 3) | |
4045 | goto illegal_op; | |
4046 | #ifdef TARGET_X86_64 | |
4047 | if (s->aflag == 2) { | |
4048 | gen_op_movq_A0_reg(R_EDI); | |
4049 | } else | |
4050 | #endif | |
4051 | { | |
4052 | gen_op_movl_A0_reg(R_EDI); | |
4053 | if (s->aflag == 0) | |
4054 | gen_op_andl_A0_ffff(); | |
4055 | } | |
4056 | gen_add_A0_ds_seg(s); | |
4057 | ||
4058 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); | |
4059 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 4060 | ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0); |
b8b6a50b | 4061 | break; |
664e0f19 | 4062 | default: |
5af45186 FB |
4063 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4064 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
a7812ae4 | 4065 | ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
4066 | break; |
4067 | } | |
4068 | if (b == 0x2e || b == 0x2f) { | |
4069 | s->cc_op = CC_OP_EFLAGS; | |
4070 | } | |
4071 | } | |
4072 | } | |
4073 | ||
2c0262af FB |
4074 | /* convert one instruction. s->is_jmp is set if the translation must |
4075 | be stopped. Return the next pc value */ | |
14ce26e7 | 4076 | static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) |
2c0262af FB |
4077 | { |
4078 | int b, prefixes, aflag, dflag; | |
4079 | int shift, ot; | |
4080 | int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val; | |
14ce26e7 FB |
4081 | target_ulong next_eip, tval; |
4082 | int rex_w, rex_r; | |
2c0262af | 4083 | |
8fec2b8c | 4084 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) |
70cff25e | 4085 | tcg_gen_debug_insn_start(pc_start); |
2c0262af FB |
4086 | s->pc = pc_start; |
4087 | prefixes = 0; | |
4088 | aflag = s->code32; | |
4089 | dflag = s->code32; | |
4090 | s->override = -1; | |
14ce26e7 FB |
4091 | rex_w = -1; |
4092 | rex_r = 0; | |
4093 | #ifdef TARGET_X86_64 | |
4094 | s->rex_x = 0; | |
4095 | s->rex_b = 0; | |
5fafdf24 | 4096 | x86_64_hregs = 0; |
14ce26e7 FB |
4097 | #endif |
4098 | s->rip_offset = 0; /* for relative ip address */ | |
2c0262af | 4099 | next_byte: |
61382a50 | 4100 | b = ldub_code(s->pc); |
2c0262af FB |
4101 | s->pc++; |
4102 | /* check prefixes */ | |
14ce26e7 FB |
4103 | #ifdef TARGET_X86_64 |
4104 | if (CODE64(s)) { | |
4105 | switch (b) { | |
4106 | case 0xf3: | |
4107 | prefixes |= PREFIX_REPZ; | |
4108 | goto next_byte; | |
4109 | case 0xf2: | |
4110 | prefixes |= PREFIX_REPNZ; | |
4111 | goto next_byte; | |
4112 | case 0xf0: | |
4113 | prefixes |= PREFIX_LOCK; | |
4114 | goto next_byte; | |
4115 | case 0x2e: | |
4116 | s->override = R_CS; | |
4117 | goto next_byte; | |
4118 | case 0x36: | |
4119 | s->override = R_SS; | |
4120 | goto next_byte; | |
4121 | case 0x3e: | |
4122 | s->override = R_DS; | |
4123 | goto next_byte; | |
4124 | case 0x26: | |
4125 | s->override = R_ES; | |
4126 | goto next_byte; | |
4127 | case 0x64: | |
4128 | s->override = R_FS; | |
4129 | goto next_byte; | |
4130 | case 0x65: | |
4131 | s->override = R_GS; | |
4132 | goto next_byte; | |
4133 | case 0x66: | |
4134 | prefixes |= PREFIX_DATA; | |
4135 | goto next_byte; | |
4136 | case 0x67: | |
4137 | prefixes |= PREFIX_ADR; | |
4138 | goto next_byte; | |
4139 | case 0x40 ... 0x4f: | |
4140 | /* REX prefix */ | |
4141 | rex_w = (b >> 3) & 1; | |
4142 | rex_r = (b & 0x4) << 1; | |
4143 | s->rex_x = (b & 0x2) << 2; | |
4144 | REX_B(s) = (b & 0x1) << 3; | |
4145 | x86_64_hregs = 1; /* select uniform byte register addressing */ | |
4146 | goto next_byte; | |
4147 | } | |
4148 | if (rex_w == 1) { | |
4149 | /* 0x66 is ignored if rex.w is set */ | |
4150 | dflag = 2; | |
4151 | } else { | |
4152 | if (prefixes & PREFIX_DATA) | |
4153 | dflag ^= 1; | |
4154 | } | |
4155 | if (!(prefixes & PREFIX_ADR)) | |
4156 | aflag = 2; | |
5fafdf24 | 4157 | } else |
14ce26e7 FB |
4158 | #endif |
4159 | { | |
4160 | switch (b) { | |
4161 | case 0xf3: | |
4162 | prefixes |= PREFIX_REPZ; | |
4163 | goto next_byte; | |
4164 | case 0xf2: | |
4165 | prefixes |= PREFIX_REPNZ; | |
4166 | goto next_byte; | |
4167 | case 0xf0: | |
4168 | prefixes |= PREFIX_LOCK; | |
4169 | goto next_byte; | |
4170 | case 0x2e: | |
4171 | s->override = R_CS; | |
4172 | goto next_byte; | |
4173 | case 0x36: | |
4174 | s->override = R_SS; | |
4175 | goto next_byte; | |
4176 | case 0x3e: | |
4177 | s->override = R_DS; | |
4178 | goto next_byte; | |
4179 | case 0x26: | |
4180 | s->override = R_ES; | |
4181 | goto next_byte; | |
4182 | case 0x64: | |
4183 | s->override = R_FS; | |
4184 | goto next_byte; | |
4185 | case 0x65: | |
4186 | s->override = R_GS; | |
4187 | goto next_byte; | |
4188 | case 0x66: | |
4189 | prefixes |= PREFIX_DATA; | |
4190 | goto next_byte; | |
4191 | case 0x67: | |
4192 | prefixes |= PREFIX_ADR; | |
4193 | goto next_byte; | |
4194 | } | |
4195 | if (prefixes & PREFIX_DATA) | |
4196 | dflag ^= 1; | |
4197 | if (prefixes & PREFIX_ADR) | |
4198 | aflag ^= 1; | |
2c0262af FB |
4199 | } |
4200 | ||
2c0262af FB |
4201 | s->prefix = prefixes; |
4202 | s->aflag = aflag; | |
4203 | s->dflag = dflag; | |
4204 | ||
4205 | /* lock generation */ | |
4206 | if (prefixes & PREFIX_LOCK) | |
a7812ae4 | 4207 | gen_helper_lock(); |
2c0262af FB |
4208 | |
4209 | /* now check op code */ | |
4210 | reswitch: | |
4211 | switch(b) { | |
4212 | case 0x0f: | |
4213 | /**************************/ | |
4214 | /* extended op code */ | |
61382a50 | 4215 | b = ldub_code(s->pc++) | 0x100; |
2c0262af | 4216 | goto reswitch; |
3b46e624 | 4217 | |
2c0262af FB |
4218 | /**************************/ |
4219 | /* arith & logic */ | |
4220 | case 0x00 ... 0x05: | |
4221 | case 0x08 ... 0x0d: | |
4222 | case 0x10 ... 0x15: | |
4223 | case 0x18 ... 0x1d: | |
4224 | case 0x20 ... 0x25: | |
4225 | case 0x28 ... 0x2d: | |
4226 | case 0x30 ... 0x35: | |
4227 | case 0x38 ... 0x3d: | |
4228 | { | |
4229 | int op, f, val; | |
4230 | op = (b >> 3) & 7; | |
4231 | f = (b >> 1) & 3; | |
4232 | ||
4233 | if ((b & 1) == 0) | |
4234 | ot = OT_BYTE; | |
4235 | else | |
14ce26e7 | 4236 | ot = dflag + OT_WORD; |
3b46e624 | 4237 | |
2c0262af FB |
4238 | switch(f) { |
4239 | case 0: /* OP Ev, Gv */ | |
61382a50 | 4240 | modrm = ldub_code(s->pc++); |
14ce26e7 | 4241 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 4242 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4243 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4244 | if (mod != 3) { |
4245 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4246 | opreg = OR_TMP0; | |
4247 | } else if (op == OP_XORL && rm == reg) { | |
4248 | xor_zero: | |
4249 | /* xor reg, reg optimisation */ | |
4250 | gen_op_movl_T0_0(); | |
4251 | s->cc_op = CC_OP_LOGICB + ot; | |
57fec1fe | 4252 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
4253 | gen_op_update1_cc(); |
4254 | break; | |
4255 | } else { | |
4256 | opreg = rm; | |
4257 | } | |
57fec1fe | 4258 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4259 | gen_op(s, op, ot, opreg); |
4260 | break; | |
4261 | case 1: /* OP Gv, Ev */ | |
61382a50 | 4262 | modrm = ldub_code(s->pc++); |
2c0262af | 4263 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
4264 | reg = ((modrm >> 3) & 7) | rex_r; |
4265 | rm = (modrm & 7) | REX_B(s); | |
2c0262af FB |
4266 | if (mod != 3) { |
4267 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 4268 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af FB |
4269 | } else if (op == OP_XORL && rm == reg) { |
4270 | goto xor_zero; | |
4271 | } else { | |
57fec1fe | 4272 | gen_op_mov_TN_reg(ot, 1, rm); |
2c0262af FB |
4273 | } |
4274 | gen_op(s, op, ot, reg); | |
4275 | break; | |
4276 | case 2: /* OP A, Iv */ | |
4277 | val = insn_get(s, ot); | |
4278 | gen_op_movl_T1_im(val); | |
4279 | gen_op(s, op, ot, OR_EAX); | |
4280 | break; | |
4281 | } | |
4282 | } | |
4283 | break; | |
4284 | ||
ec9d6075 FB |
4285 | case 0x82: |
4286 | if (CODE64(s)) | |
4287 | goto illegal_op; | |
2c0262af FB |
4288 | case 0x80: /* GRP1 */ |
4289 | case 0x81: | |
4290 | case 0x83: | |
4291 | { | |
4292 | int val; | |
4293 | ||
4294 | if ((b & 1) == 0) | |
4295 | ot = OT_BYTE; | |
4296 | else | |
14ce26e7 | 4297 | ot = dflag + OT_WORD; |
3b46e624 | 4298 | |
61382a50 | 4299 | modrm = ldub_code(s->pc++); |
2c0262af | 4300 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4301 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4302 | op = (modrm >> 3) & 7; |
3b46e624 | 4303 | |
2c0262af | 4304 | if (mod != 3) { |
14ce26e7 FB |
4305 | if (b == 0x83) |
4306 | s->rip_offset = 1; | |
4307 | else | |
4308 | s->rip_offset = insn_const_size(ot); | |
2c0262af FB |
4309 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4310 | opreg = OR_TMP0; | |
4311 | } else { | |
14ce26e7 | 4312 | opreg = rm; |
2c0262af FB |
4313 | } |
4314 | ||
4315 | switch(b) { | |
4316 | default: | |
4317 | case 0x80: | |
4318 | case 0x81: | |
d64477af | 4319 | case 0x82: |
2c0262af FB |
4320 | val = insn_get(s, ot); |
4321 | break; | |
4322 | case 0x83: | |
4323 | val = (int8_t)insn_get(s, OT_BYTE); | |
4324 | break; | |
4325 | } | |
4326 | gen_op_movl_T1_im(val); | |
4327 | gen_op(s, op, ot, opreg); | |
4328 | } | |
4329 | break; | |
4330 | ||
4331 | /**************************/ | |
4332 | /* inc, dec, and other misc arith */ | |
4333 | case 0x40 ... 0x47: /* inc Gv */ | |
4334 | ot = dflag ? OT_LONG : OT_WORD; | |
4335 | gen_inc(s, ot, OR_EAX + (b & 7), 1); | |
4336 | break; | |
4337 | case 0x48 ... 0x4f: /* dec Gv */ | |
4338 | ot = dflag ? OT_LONG : OT_WORD; | |
4339 | gen_inc(s, ot, OR_EAX + (b & 7), -1); | |
4340 | break; | |
4341 | case 0xf6: /* GRP3 */ | |
4342 | case 0xf7: | |
4343 | if ((b & 1) == 0) | |
4344 | ot = OT_BYTE; | |
4345 | else | |
14ce26e7 | 4346 | ot = dflag + OT_WORD; |
2c0262af | 4347 | |
61382a50 | 4348 | modrm = ldub_code(s->pc++); |
2c0262af | 4349 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4350 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4351 | op = (modrm >> 3) & 7; |
4352 | if (mod != 3) { | |
14ce26e7 FB |
4353 | if (op == 0) |
4354 | s->rip_offset = insn_const_size(ot); | |
2c0262af | 4355 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
57fec1fe | 4356 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4357 | } else { |
57fec1fe | 4358 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4359 | } |
4360 | ||
4361 | switch(op) { | |
4362 | case 0: /* test */ | |
4363 | val = insn_get(s, ot); | |
4364 | gen_op_movl_T1_im(val); | |
4365 | gen_op_testl_T0_T1_cc(); | |
4366 | s->cc_op = CC_OP_LOGICB + ot; | |
4367 | break; | |
4368 | case 2: /* not */ | |
b6abf97d | 4369 | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4370 | if (mod != 3) { |
57fec1fe | 4371 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4372 | } else { |
57fec1fe | 4373 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4374 | } |
4375 | break; | |
4376 | case 3: /* neg */ | |
b6abf97d | 4377 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4378 | if (mod != 3) { |
57fec1fe | 4379 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4380 | } else { |
57fec1fe | 4381 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4382 | } |
4383 | gen_op_update_neg_cc(); | |
4384 | s->cc_op = CC_OP_SUBB + ot; | |
4385 | break; | |
4386 | case 4: /* mul */ | |
4387 | switch(ot) { | |
4388 | case OT_BYTE: | |
0211e5af FB |
4389 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4390 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); | |
4391 | tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); | |
4392 | /* XXX: use 32 bit mul which could be faster */ | |
4393 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4394 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4395 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4396 | tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); | |
d36cd60e | 4397 | s->cc_op = CC_OP_MULB; |
2c0262af FB |
4398 | break; |
4399 | case OT_WORD: | |
0211e5af FB |
4400 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4401 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); | |
4402 | tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); | |
4403 | /* XXX: use 32 bit mul which could be faster */ | |
4404 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4405 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4406 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4407 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4408 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4409 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
d36cd60e | 4410 | s->cc_op = CC_OP_MULW; |
2c0262af FB |
4411 | break; |
4412 | default: | |
4413 | case OT_LONG: | |
0211e5af FB |
4414 | #ifdef TARGET_X86_64 |
4415 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4416 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); | |
4417 | tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); | |
4418 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4419 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4420 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4421 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4422 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4423 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4424 | #else | |
4425 | { | |
a7812ae4 PB |
4426 | TCGv_i64 t0, t1; |
4427 | t0 = tcg_temp_new_i64(); | |
4428 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4429 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4430 | tcg_gen_extu_i32_i64(t0, cpu_T[0]); | |
4431 | tcg_gen_extu_i32_i64(t1, cpu_T[1]); | |
4432 | tcg_gen_mul_i64(t0, t0, t1); | |
4433 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4434 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4435 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4436 | tcg_gen_shri_i64(t0, t0, 32); | |
4437 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4438 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4439 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4440 | } | |
4441 | #endif | |
d36cd60e | 4442 | s->cc_op = CC_OP_MULL; |
2c0262af | 4443 | break; |
14ce26e7 FB |
4444 | #ifdef TARGET_X86_64 |
4445 | case OT_QUAD: | |
a7812ae4 | 4446 | gen_helper_mulq_EAX_T0(cpu_T[0]); |
14ce26e7 FB |
4447 | s->cc_op = CC_OP_MULQ; |
4448 | break; | |
4449 | #endif | |
2c0262af | 4450 | } |
2c0262af FB |
4451 | break; |
4452 | case 5: /* imul */ | |
4453 | switch(ot) { | |
4454 | case OT_BYTE: | |
0211e5af FB |
4455 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4456 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4457 | tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); | |
4458 | /* XXX: use 32 bit mul which could be faster */ | |
4459 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4460 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4461 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4462 | tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]); | |
4463 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
d36cd60e | 4464 | s->cc_op = CC_OP_MULB; |
2c0262af FB |
4465 | break; |
4466 | case OT_WORD: | |
0211e5af FB |
4467 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4468 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4469 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4470 | /* XXX: use 32 bit mul which could be faster */ | |
4471 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4472 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4473 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4474 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4475 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4476 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4477 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
d36cd60e | 4478 | s->cc_op = CC_OP_MULW; |
2c0262af FB |
4479 | break; |
4480 | default: | |
4481 | case OT_LONG: | |
0211e5af FB |
4482 | #ifdef TARGET_X86_64 |
4483 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4484 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4485 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4486 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4487 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4488 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4489 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4490 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4491 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4492 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4493 | #else | |
4494 | { | |
a7812ae4 PB |
4495 | TCGv_i64 t0, t1; |
4496 | t0 = tcg_temp_new_i64(); | |
4497 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4498 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4499 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); | |
4500 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4501 | tcg_gen_mul_i64(t0, t0, t1); | |
4502 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4503 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4504 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4505 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4506 | tcg_gen_shri_i64(t0, t0, 32); | |
4507 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4508 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4509 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4510 | } | |
4511 | #endif | |
d36cd60e | 4512 | s->cc_op = CC_OP_MULL; |
2c0262af | 4513 | break; |
14ce26e7 FB |
4514 | #ifdef TARGET_X86_64 |
4515 | case OT_QUAD: | |
a7812ae4 | 4516 | gen_helper_imulq_EAX_T0(cpu_T[0]); |
14ce26e7 FB |
4517 | s->cc_op = CC_OP_MULQ; |
4518 | break; | |
4519 | #endif | |
2c0262af | 4520 | } |
2c0262af FB |
4521 | break; |
4522 | case 6: /* div */ | |
4523 | switch(ot) { | |
4524 | case OT_BYTE: | |
14ce26e7 | 4525 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4526 | gen_helper_divb_AL(cpu_T[0]); |
2c0262af FB |
4527 | break; |
4528 | case OT_WORD: | |
14ce26e7 | 4529 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4530 | gen_helper_divw_AX(cpu_T[0]); |
2c0262af FB |
4531 | break; |
4532 | default: | |
4533 | case OT_LONG: | |
14ce26e7 | 4534 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4535 | gen_helper_divl_EAX(cpu_T[0]); |
14ce26e7 FB |
4536 | break; |
4537 | #ifdef TARGET_X86_64 | |
4538 | case OT_QUAD: | |
4539 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 4540 | gen_helper_divq_EAX(cpu_T[0]); |
2c0262af | 4541 | break; |
14ce26e7 | 4542 | #endif |
2c0262af FB |
4543 | } |
4544 | break; | |
4545 | case 7: /* idiv */ | |
4546 | switch(ot) { | |
4547 | case OT_BYTE: | |
14ce26e7 | 4548 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4549 | gen_helper_idivb_AL(cpu_T[0]); |
2c0262af FB |
4550 | break; |
4551 | case OT_WORD: | |
14ce26e7 | 4552 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4553 | gen_helper_idivw_AX(cpu_T[0]); |
2c0262af FB |
4554 | break; |
4555 | default: | |
4556 | case OT_LONG: | |
14ce26e7 | 4557 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 4558 | gen_helper_idivl_EAX(cpu_T[0]); |
14ce26e7 FB |
4559 | break; |
4560 | #ifdef TARGET_X86_64 | |
4561 | case OT_QUAD: | |
4562 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 4563 | gen_helper_idivq_EAX(cpu_T[0]); |
2c0262af | 4564 | break; |
14ce26e7 | 4565 | #endif |
2c0262af FB |
4566 | } |
4567 | break; | |
4568 | default: | |
4569 | goto illegal_op; | |
4570 | } | |
4571 | break; | |
4572 | ||
4573 | case 0xfe: /* GRP4 */ | |
4574 | case 0xff: /* GRP5 */ | |
4575 | if ((b & 1) == 0) | |
4576 | ot = OT_BYTE; | |
4577 | else | |
14ce26e7 | 4578 | ot = dflag + OT_WORD; |
2c0262af | 4579 | |
61382a50 | 4580 | modrm = ldub_code(s->pc++); |
2c0262af | 4581 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4582 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4583 | op = (modrm >> 3) & 7; |
4584 | if (op >= 2 && b == 0xfe) { | |
4585 | goto illegal_op; | |
4586 | } | |
14ce26e7 | 4587 | if (CODE64(s)) { |
aba9d61e | 4588 | if (op == 2 || op == 4) { |
14ce26e7 FB |
4589 | /* operand size for jumps is 64 bit */ |
4590 | ot = OT_QUAD; | |
aba9d61e | 4591 | } else if (op == 3 || op == 5) { |
41b1e61f | 4592 | ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD; |
14ce26e7 FB |
4593 | } else if (op == 6) { |
4594 | /* default push size is 64 bit */ | |
4595 | ot = dflag ? OT_QUAD : OT_WORD; | |
4596 | } | |
4597 | } | |
2c0262af FB |
4598 | if (mod != 3) { |
4599 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4600 | if (op >= 2 && op != 3 && op != 5) | |
57fec1fe | 4601 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4602 | } else { |
57fec1fe | 4603 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4604 | } |
4605 | ||
4606 | switch(op) { | |
4607 | case 0: /* inc Ev */ | |
4608 | if (mod != 3) | |
4609 | opreg = OR_TMP0; | |
4610 | else | |
4611 | opreg = rm; | |
4612 | gen_inc(s, ot, opreg, 1); | |
4613 | break; | |
4614 | case 1: /* dec Ev */ | |
4615 | if (mod != 3) | |
4616 | opreg = OR_TMP0; | |
4617 | else | |
4618 | opreg = rm; | |
4619 | gen_inc(s, ot, opreg, -1); | |
4620 | break; | |
4621 | case 2: /* call Ev */ | |
4f31916f | 4622 | /* XXX: optimize if memory (no 'and' is necessary) */ |
2c0262af FB |
4623 | if (s->dflag == 0) |
4624 | gen_op_andl_T0_ffff(); | |
2c0262af | 4625 | next_eip = s->pc - s->cs_base; |
1ef38687 | 4626 | gen_movtl_T1_im(next_eip); |
4f31916f FB |
4627 | gen_push_T1(s); |
4628 | gen_op_jmp_T0(); | |
2c0262af FB |
4629 | gen_eob(s); |
4630 | break; | |
61382a50 | 4631 | case 3: /* lcall Ev */ |
57fec1fe | 4632 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4633 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4634 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4635 | do_lcall: |
4636 | if (s->pe && !s->vm86) { | |
4637 | if (s->cc_op != CC_OP_DYNAMIC) | |
4638 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 4639 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4640 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
4641 | gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1], |
4642 | tcg_const_i32(dflag), | |
4643 | tcg_const_i32(s->pc - pc_start)); | |
2c0262af | 4644 | } else { |
b6abf97d | 4645 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
4646 | gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1], |
4647 | tcg_const_i32(dflag), | |
4648 | tcg_const_i32(s->pc - s->cs_base)); | |
2c0262af FB |
4649 | } |
4650 | gen_eob(s); | |
4651 | break; | |
4652 | case 4: /* jmp Ev */ | |
4653 | if (s->dflag == 0) | |
4654 | gen_op_andl_T0_ffff(); | |
4655 | gen_op_jmp_T0(); | |
4656 | gen_eob(s); | |
4657 | break; | |
4658 | case 5: /* ljmp Ev */ | |
57fec1fe | 4659 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4660 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4661 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4662 | do_ljmp: |
4663 | if (s->pe && !s->vm86) { | |
4664 | if (s->cc_op != CC_OP_DYNAMIC) | |
4665 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 4666 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4667 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 PB |
4668 | gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1], |
4669 | tcg_const_i32(s->pc - pc_start)); | |
2c0262af | 4670 | } else { |
3bd7da9e | 4671 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
4672 | gen_op_movl_T0_T1(); |
4673 | gen_op_jmp_T0(); | |
4674 | } | |
4675 | gen_eob(s); | |
4676 | break; | |
4677 | case 6: /* push Ev */ | |
4678 | gen_push_T0(s); | |
4679 | break; | |
4680 | default: | |
4681 | goto illegal_op; | |
4682 | } | |
4683 | break; | |
4684 | ||
4685 | case 0x84: /* test Ev, Gv */ | |
5fafdf24 | 4686 | case 0x85: |
2c0262af FB |
4687 | if ((b & 1) == 0) |
4688 | ot = OT_BYTE; | |
4689 | else | |
14ce26e7 | 4690 | ot = dflag + OT_WORD; |
2c0262af | 4691 | |
61382a50 | 4692 | modrm = ldub_code(s->pc++); |
14ce26e7 | 4693 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 4694 | |
2c0262af | 4695 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 4696 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4697 | gen_op_testl_T0_T1_cc(); |
4698 | s->cc_op = CC_OP_LOGICB + ot; | |
4699 | break; | |
3b46e624 | 4700 | |
2c0262af FB |
4701 | case 0xa8: /* test eAX, Iv */ |
4702 | case 0xa9: | |
4703 | if ((b & 1) == 0) | |
4704 | ot = OT_BYTE; | |
4705 | else | |
14ce26e7 | 4706 | ot = dflag + OT_WORD; |
2c0262af FB |
4707 | val = insn_get(s, ot); |
4708 | ||
57fec1fe | 4709 | gen_op_mov_TN_reg(ot, 0, OR_EAX); |
2c0262af FB |
4710 | gen_op_movl_T1_im(val); |
4711 | gen_op_testl_T0_T1_cc(); | |
4712 | s->cc_op = CC_OP_LOGICB + ot; | |
4713 | break; | |
3b46e624 | 4714 | |
2c0262af | 4715 | case 0x98: /* CWDE/CBW */ |
14ce26e7 FB |
4716 | #ifdef TARGET_X86_64 |
4717 | if (dflag == 2) { | |
e108dd01 FB |
4718 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
4719 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4720 | gen_op_mov_reg_T0(OT_QUAD, R_EAX); | |
14ce26e7 FB |
4721 | } else |
4722 | #endif | |
e108dd01 FB |
4723 | if (dflag == 1) { |
4724 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4725 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4726 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4727 | } else { | |
4728 | gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX); | |
4729 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4730 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4731 | } | |
2c0262af FB |
4732 | break; |
4733 | case 0x99: /* CDQ/CWD */ | |
14ce26e7 FB |
4734 | #ifdef TARGET_X86_64 |
4735 | if (dflag == 2) { | |
e108dd01 FB |
4736 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
4737 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); | |
4738 | gen_op_mov_reg_T0(OT_QUAD, R_EDX); | |
14ce26e7 FB |
4739 | } else |
4740 | #endif | |
e108dd01 FB |
4741 | if (dflag == 1) { |
4742 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); | |
4743 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4744 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); | |
4745 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4746 | } else { | |
4747 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4748 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4749 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); | |
4750 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4751 | } | |
2c0262af FB |
4752 | break; |
4753 | case 0x1af: /* imul Gv, Ev */ | |
4754 | case 0x69: /* imul Gv, Ev, I */ | |
4755 | case 0x6b: | |
14ce26e7 | 4756 | ot = dflag + OT_WORD; |
61382a50 | 4757 | modrm = ldub_code(s->pc++); |
14ce26e7 FB |
4758 | reg = ((modrm >> 3) & 7) | rex_r; |
4759 | if (b == 0x69) | |
4760 | s->rip_offset = insn_const_size(ot); | |
4761 | else if (b == 0x6b) | |
4762 | s->rip_offset = 1; | |
2c0262af FB |
4763 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); |
4764 | if (b == 0x69) { | |
4765 | val = insn_get(s, ot); | |
4766 | gen_op_movl_T1_im(val); | |
4767 | } else if (b == 0x6b) { | |
d64477af | 4768 | val = (int8_t)insn_get(s, OT_BYTE); |
2c0262af FB |
4769 | gen_op_movl_T1_im(val); |
4770 | } else { | |
57fec1fe | 4771 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4772 | } |
4773 | ||
14ce26e7 FB |
4774 | #ifdef TARGET_X86_64 |
4775 | if (ot == OT_QUAD) { | |
a7812ae4 | 4776 | gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]); |
14ce26e7 FB |
4777 | } else |
4778 | #endif | |
2c0262af | 4779 | if (ot == OT_LONG) { |
0211e5af FB |
4780 | #ifdef TARGET_X86_64 |
4781 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4782 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4783 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4784 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4785 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4786 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4787 | #else | |
4788 | { | |
a7812ae4 PB |
4789 | TCGv_i64 t0, t1; |
4790 | t0 = tcg_temp_new_i64(); | |
4791 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4792 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); |
4793 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4794 | tcg_gen_mul_i64(t0, t0, t1); | |
4795 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4796 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4797 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4798 | tcg_gen_shri_i64(t0, t0, 32); | |
4799 | tcg_gen_trunc_i64_i32(cpu_T[1], t0); | |
4800 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0); | |
4801 | } | |
4802 | #endif | |
2c0262af | 4803 | } else { |
0211e5af FB |
4804 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4805 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4806 | /* XXX: use 32 bit mul which could be faster */ | |
4807 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4808 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4809 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4810 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
2c0262af | 4811 | } |
57fec1fe | 4812 | gen_op_mov_reg_T0(ot, reg); |
d36cd60e | 4813 | s->cc_op = CC_OP_MULB + ot; |
2c0262af FB |
4814 | break; |
4815 | case 0x1c0: | |
4816 | case 0x1c1: /* xadd Ev, Gv */ | |
4817 | if ((b & 1) == 0) | |
4818 | ot = OT_BYTE; | |
4819 | else | |
14ce26e7 | 4820 | ot = dflag + OT_WORD; |
61382a50 | 4821 | modrm = ldub_code(s->pc++); |
14ce26e7 | 4822 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
4823 | mod = (modrm >> 6) & 3; |
4824 | if (mod == 3) { | |
14ce26e7 | 4825 | rm = (modrm & 7) | REX_B(s); |
57fec1fe FB |
4826 | gen_op_mov_TN_reg(ot, 0, reg); |
4827 | gen_op_mov_TN_reg(ot, 1, rm); | |
2c0262af | 4828 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4829 | gen_op_mov_reg_T1(ot, reg); |
4830 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af FB |
4831 | } else { |
4832 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe FB |
4833 | gen_op_mov_TN_reg(ot, 0, reg); |
4834 | gen_op_ld_T1_A0(ot + s->mem_index); | |
2c0262af | 4835 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4836 | gen_op_st_T0_A0(ot + s->mem_index); |
4837 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af FB |
4838 | } |
4839 | gen_op_update2_cc(); | |
4840 | s->cc_op = CC_OP_ADDB + ot; | |
4841 | break; | |
4842 | case 0x1b0: | |
4843 | case 0x1b1: /* cmpxchg Ev, Gv */ | |
cad3a37d | 4844 | { |
1130328e | 4845 | int label1, label2; |
1e4840bf | 4846 | TCGv t0, t1, t2, a0; |
cad3a37d FB |
4847 | |
4848 | if ((b & 1) == 0) | |
4849 | ot = OT_BYTE; | |
4850 | else | |
4851 | ot = dflag + OT_WORD; | |
4852 | modrm = ldub_code(s->pc++); | |
4853 | reg = ((modrm >> 3) & 7) | rex_r; | |
4854 | mod = (modrm >> 6) & 3; | |
a7812ae4 PB |
4855 | t0 = tcg_temp_local_new(); |
4856 | t1 = tcg_temp_local_new(); | |
4857 | t2 = tcg_temp_local_new(); | |
4858 | a0 = tcg_temp_local_new(); | |
1e4840bf | 4859 | gen_op_mov_v_reg(ot, t1, reg); |
cad3a37d FB |
4860 | if (mod == 3) { |
4861 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 4862 | gen_op_mov_v_reg(ot, t0, rm); |
cad3a37d FB |
4863 | } else { |
4864 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
1e4840bf FB |
4865 | tcg_gen_mov_tl(a0, cpu_A0); |
4866 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
cad3a37d FB |
4867 | rm = 0; /* avoid warning */ |
4868 | } | |
4869 | label1 = gen_new_label(); | |
cc739bb0 | 4870 | tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0); |
1e4840bf FB |
4871 | gen_extu(ot, t2); |
4872 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); | |
cad3a37d | 4873 | if (mod == 3) { |
1130328e | 4874 | label2 = gen_new_label(); |
1e4840bf | 4875 | gen_op_mov_reg_v(ot, R_EAX, t0); |
1130328e FB |
4876 | tcg_gen_br(label2); |
4877 | gen_set_label(label1); | |
1e4840bf | 4878 | gen_op_mov_reg_v(ot, rm, t1); |
1130328e | 4879 | gen_set_label(label2); |
cad3a37d | 4880 | } else { |
1e4840bf FB |
4881 | tcg_gen_mov_tl(t1, t0); |
4882 | gen_op_mov_reg_v(ot, R_EAX, t0); | |
1130328e FB |
4883 | gen_set_label(label1); |
4884 | /* always store */ | |
1e4840bf | 4885 | gen_op_st_v(ot + s->mem_index, t1, a0); |
cad3a37d | 4886 | } |
1e4840bf FB |
4887 | tcg_gen_mov_tl(cpu_cc_src, t0); |
4888 | tcg_gen_mov_tl(cpu_cc_dst, t2); | |
cad3a37d | 4889 | s->cc_op = CC_OP_SUBB + ot; |
1e4840bf FB |
4890 | tcg_temp_free(t0); |
4891 | tcg_temp_free(t1); | |
4892 | tcg_temp_free(t2); | |
4893 | tcg_temp_free(a0); | |
2c0262af | 4894 | } |
2c0262af FB |
4895 | break; |
4896 | case 0x1c7: /* cmpxchg8b */ | |
61382a50 | 4897 | modrm = ldub_code(s->pc++); |
2c0262af | 4898 | mod = (modrm >> 6) & 3; |
71c3558e | 4899 | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
2c0262af | 4900 | goto illegal_op; |
1b9d9ebb FB |
4901 | #ifdef TARGET_X86_64 |
4902 | if (dflag == 2) { | |
4903 | if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) | |
4904 | goto illegal_op; | |
4905 | gen_jmp_im(pc_start - s->cs_base); | |
4906 | if (s->cc_op != CC_OP_DYNAMIC) | |
4907 | gen_op_set_cc_op(s->cc_op); | |
4908 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
a7812ae4 | 4909 | gen_helper_cmpxchg16b(cpu_A0); |
1b9d9ebb FB |
4910 | } else |
4911 | #endif | |
4912 | { | |
4913 | if (!(s->cpuid_features & CPUID_CX8)) | |
4914 | goto illegal_op; | |
4915 | gen_jmp_im(pc_start - s->cs_base); | |
4916 | if (s->cc_op != CC_OP_DYNAMIC) | |
4917 | gen_op_set_cc_op(s->cc_op); | |
4918 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
a7812ae4 | 4919 | gen_helper_cmpxchg8b(cpu_A0); |
1b9d9ebb | 4920 | } |
2c0262af FB |
4921 | s->cc_op = CC_OP_EFLAGS; |
4922 | break; | |
3b46e624 | 4923 | |
2c0262af FB |
4924 | /**************************/ |
4925 | /* push/pop */ | |
4926 | case 0x50 ... 0x57: /* push */ | |
57fec1fe | 4927 | gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s)); |
2c0262af FB |
4928 | gen_push_T0(s); |
4929 | break; | |
4930 | case 0x58 ... 0x5f: /* pop */ | |
14ce26e7 FB |
4931 | if (CODE64(s)) { |
4932 | ot = dflag ? OT_QUAD : OT_WORD; | |
4933 | } else { | |
4934 | ot = dflag + OT_WORD; | |
4935 | } | |
2c0262af | 4936 | gen_pop_T0(s); |
77729c24 | 4937 | /* NOTE: order is important for pop %sp */ |
2c0262af | 4938 | gen_pop_update(s); |
57fec1fe | 4939 | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s)); |
2c0262af FB |
4940 | break; |
4941 | case 0x60: /* pusha */ | |
14ce26e7 FB |
4942 | if (CODE64(s)) |
4943 | goto illegal_op; | |
2c0262af FB |
4944 | gen_pusha(s); |
4945 | break; | |
4946 | case 0x61: /* popa */ | |
14ce26e7 FB |
4947 | if (CODE64(s)) |
4948 | goto illegal_op; | |
2c0262af FB |
4949 | gen_popa(s); |
4950 | break; | |
4951 | case 0x68: /* push Iv */ | |
4952 | case 0x6a: | |
14ce26e7 FB |
4953 | if (CODE64(s)) { |
4954 | ot = dflag ? OT_QUAD : OT_WORD; | |
4955 | } else { | |
4956 | ot = dflag + OT_WORD; | |
4957 | } | |
2c0262af FB |
4958 | if (b == 0x68) |
4959 | val = insn_get(s, ot); | |
4960 | else | |
4961 | val = (int8_t)insn_get(s, OT_BYTE); | |
4962 | gen_op_movl_T0_im(val); | |
4963 | gen_push_T0(s); | |
4964 | break; | |
4965 | case 0x8f: /* pop Ev */ | |
14ce26e7 FB |
4966 | if (CODE64(s)) { |
4967 | ot = dflag ? OT_QUAD : OT_WORD; | |
4968 | } else { | |
4969 | ot = dflag + OT_WORD; | |
4970 | } | |
61382a50 | 4971 | modrm = ldub_code(s->pc++); |
77729c24 | 4972 | mod = (modrm >> 6) & 3; |
2c0262af | 4973 | gen_pop_T0(s); |
77729c24 FB |
4974 | if (mod == 3) { |
4975 | /* NOTE: order is important for pop %sp */ | |
4976 | gen_pop_update(s); | |
14ce26e7 | 4977 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 4978 | gen_op_mov_reg_T0(ot, rm); |
77729c24 FB |
4979 | } else { |
4980 | /* NOTE: order is important too for MMU exceptions */ | |
14ce26e7 | 4981 | s->popl_esp_hack = 1 << ot; |
77729c24 FB |
4982 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); |
4983 | s->popl_esp_hack = 0; | |
4984 | gen_pop_update(s); | |
4985 | } | |
2c0262af FB |
4986 | break; |
4987 | case 0xc8: /* enter */ | |
4988 | { | |
4989 | int level; | |
61382a50 | 4990 | val = lduw_code(s->pc); |
2c0262af | 4991 | s->pc += 2; |
61382a50 | 4992 | level = ldub_code(s->pc++); |
2c0262af FB |
4993 | gen_enter(s, val, level); |
4994 | } | |
4995 | break; | |
4996 | case 0xc9: /* leave */ | |
4997 | /* XXX: exception not precise (ESP is updated before potential exception) */ | |
14ce26e7 | 4998 | if (CODE64(s)) { |
57fec1fe FB |
4999 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP); |
5000 | gen_op_mov_reg_T0(OT_QUAD, R_ESP); | |
14ce26e7 | 5001 | } else if (s->ss32) { |
57fec1fe FB |
5002 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
5003 | gen_op_mov_reg_T0(OT_LONG, R_ESP); | |
2c0262af | 5004 | } else { |
57fec1fe FB |
5005 | gen_op_mov_TN_reg(OT_WORD, 0, R_EBP); |
5006 | gen_op_mov_reg_T0(OT_WORD, R_ESP); | |
2c0262af FB |
5007 | } |
5008 | gen_pop_T0(s); | |
14ce26e7 FB |
5009 | if (CODE64(s)) { |
5010 | ot = dflag ? OT_QUAD : OT_WORD; | |
5011 | } else { | |
5012 | ot = dflag + OT_WORD; | |
5013 | } | |
57fec1fe | 5014 | gen_op_mov_reg_T0(ot, R_EBP); |
2c0262af FB |
5015 | gen_pop_update(s); |
5016 | break; | |
5017 | case 0x06: /* push es */ | |
5018 | case 0x0e: /* push cs */ | |
5019 | case 0x16: /* push ss */ | |
5020 | case 0x1e: /* push ds */ | |
14ce26e7 FB |
5021 | if (CODE64(s)) |
5022 | goto illegal_op; | |
2c0262af FB |
5023 | gen_op_movl_T0_seg(b >> 3); |
5024 | gen_push_T0(s); | |
5025 | break; | |
5026 | case 0x1a0: /* push fs */ | |
5027 | case 0x1a8: /* push gs */ | |
5028 | gen_op_movl_T0_seg((b >> 3) & 7); | |
5029 | gen_push_T0(s); | |
5030 | break; | |
5031 | case 0x07: /* pop es */ | |
5032 | case 0x17: /* pop ss */ | |
5033 | case 0x1f: /* pop ds */ | |
14ce26e7 FB |
5034 | if (CODE64(s)) |
5035 | goto illegal_op; | |
2c0262af FB |
5036 | reg = b >> 3; |
5037 | gen_pop_T0(s); | |
5038 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5039 | gen_pop_update(s); | |
5040 | if (reg == R_SS) { | |
a2cc3b24 FB |
5041 | /* if reg == SS, inhibit interrupts/trace. */ |
5042 | /* If several instructions disable interrupts, only the | |
5043 | _first_ does it */ | |
5044 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
a7812ae4 | 5045 | gen_helper_set_inhibit_irq(); |
2c0262af FB |
5046 | s->tf = 0; |
5047 | } | |
5048 | if (s->is_jmp) { | |
14ce26e7 | 5049 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5050 | gen_eob(s); |
5051 | } | |
5052 | break; | |
5053 | case 0x1a1: /* pop fs */ | |
5054 | case 0x1a9: /* pop gs */ | |
5055 | gen_pop_T0(s); | |
5056 | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); | |
5057 | gen_pop_update(s); | |
5058 | if (s->is_jmp) { | |
14ce26e7 | 5059 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5060 | gen_eob(s); |
5061 | } | |
5062 | break; | |
5063 | ||
5064 | /**************************/ | |
5065 | /* mov */ | |
5066 | case 0x88: | |
5067 | case 0x89: /* mov Gv, Ev */ | |
5068 | if ((b & 1) == 0) | |
5069 | ot = OT_BYTE; | |
5070 | else | |
14ce26e7 | 5071 | ot = dflag + OT_WORD; |
61382a50 | 5072 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5073 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5074 | |
2c0262af | 5075 | /* generate a generic store */ |
14ce26e7 | 5076 | gen_ldst_modrm(s, modrm, ot, reg, 1); |
2c0262af FB |
5077 | break; |
5078 | case 0xc6: | |
5079 | case 0xc7: /* mov Ev, Iv */ | |
5080 | if ((b & 1) == 0) | |
5081 | ot = OT_BYTE; | |
5082 | else | |
14ce26e7 | 5083 | ot = dflag + OT_WORD; |
61382a50 | 5084 | modrm = ldub_code(s->pc++); |
2c0262af | 5085 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5086 | if (mod != 3) { |
5087 | s->rip_offset = insn_const_size(ot); | |
2c0262af | 5088 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 5089 | } |
2c0262af FB |
5090 | val = insn_get(s, ot); |
5091 | gen_op_movl_T0_im(val); | |
5092 | if (mod != 3) | |
57fec1fe | 5093 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 5094 | else |
57fec1fe | 5095 | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); |
2c0262af FB |
5096 | break; |
5097 | case 0x8a: | |
5098 | case 0x8b: /* mov Ev, Gv */ | |
5099 | if ((b & 1) == 0) | |
5100 | ot = OT_BYTE; | |
5101 | else | |
14ce26e7 | 5102 | ot = OT_WORD + dflag; |
61382a50 | 5103 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5104 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5105 | |
2c0262af | 5106 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5107 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
5108 | break; |
5109 | case 0x8e: /* mov seg, Gv */ | |
61382a50 | 5110 | modrm = ldub_code(s->pc++); |
2c0262af FB |
5111 | reg = (modrm >> 3) & 7; |
5112 | if (reg >= 6 || reg == R_CS) | |
5113 | goto illegal_op; | |
5114 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); | |
5115 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5116 | if (reg == R_SS) { | |
5117 | /* if reg == SS, inhibit interrupts/trace */ | |
a2cc3b24 FB |
5118 | /* If several instructions disable interrupts, only the |
5119 | _first_ does it */ | |
5120 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
a7812ae4 | 5121 | gen_helper_set_inhibit_irq(); |
2c0262af FB |
5122 | s->tf = 0; |
5123 | } | |
5124 | if (s->is_jmp) { | |
14ce26e7 | 5125 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5126 | gen_eob(s); |
5127 | } | |
5128 | break; | |
5129 | case 0x8c: /* mov Gv, seg */ | |
61382a50 | 5130 | modrm = ldub_code(s->pc++); |
2c0262af FB |
5131 | reg = (modrm >> 3) & 7; |
5132 | mod = (modrm >> 6) & 3; | |
5133 | if (reg >= 6) | |
5134 | goto illegal_op; | |
5135 | gen_op_movl_T0_seg(reg); | |
14ce26e7 FB |
5136 | if (mod == 3) |
5137 | ot = OT_WORD + dflag; | |
5138 | else | |
5139 | ot = OT_WORD; | |
2c0262af FB |
5140 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); |
5141 | break; | |
5142 | ||
5143 | case 0x1b6: /* movzbS Gv, Eb */ | |
5144 | case 0x1b7: /* movzwS Gv, Eb */ | |
5145 | case 0x1be: /* movsbS Gv, Eb */ | |
5146 | case 0x1bf: /* movswS Gv, Eb */ | |
5147 | { | |
5148 | int d_ot; | |
5149 | /* d_ot is the size of destination */ | |
5150 | d_ot = dflag + OT_WORD; | |
5151 | /* ot is the size of source */ | |
5152 | ot = (b & 1) + OT_BYTE; | |
61382a50 | 5153 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5154 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 5155 | mod = (modrm >> 6) & 3; |
14ce26e7 | 5156 | rm = (modrm & 7) | REX_B(s); |
3b46e624 | 5157 | |
2c0262af | 5158 | if (mod == 3) { |
57fec1fe | 5159 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
5160 | switch(ot | (b & 8)) { |
5161 | case OT_BYTE: | |
e108dd01 | 5162 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5163 | break; |
5164 | case OT_BYTE | 8: | |
e108dd01 | 5165 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5166 | break; |
5167 | case OT_WORD: | |
e108dd01 | 5168 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5169 | break; |
5170 | default: | |
5171 | case OT_WORD | 8: | |
e108dd01 | 5172 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5173 | break; |
5174 | } | |
57fec1fe | 5175 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5176 | } else { |
5177 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
5178 | if (b & 8) { | |
57fec1fe | 5179 | gen_op_lds_T0_A0(ot + s->mem_index); |
2c0262af | 5180 | } else { |
57fec1fe | 5181 | gen_op_ldu_T0_A0(ot + s->mem_index); |
2c0262af | 5182 | } |
57fec1fe | 5183 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5184 | } |
5185 | } | |
5186 | break; | |
5187 | ||
5188 | case 0x8d: /* lea */ | |
14ce26e7 | 5189 | ot = dflag + OT_WORD; |
61382a50 | 5190 | modrm = ldub_code(s->pc++); |
3a1d9b8b FB |
5191 | mod = (modrm >> 6) & 3; |
5192 | if (mod == 3) | |
5193 | goto illegal_op; | |
14ce26e7 | 5194 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5195 | /* we must ensure that no segment is added */ |
5196 | s->override = -1; | |
5197 | val = s->addseg; | |
5198 | s->addseg = 0; | |
5199 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
5200 | s->addseg = val; | |
57fec1fe | 5201 | gen_op_mov_reg_A0(ot - OT_WORD, reg); |
2c0262af | 5202 | break; |
3b46e624 | 5203 | |
2c0262af FB |
5204 | case 0xa0: /* mov EAX, Ov */ |
5205 | case 0xa1: | |
5206 | case 0xa2: /* mov Ov, EAX */ | |
5207 | case 0xa3: | |
2c0262af | 5208 | { |
14ce26e7 FB |
5209 | target_ulong offset_addr; |
5210 | ||
5211 | if ((b & 1) == 0) | |
5212 | ot = OT_BYTE; | |
5213 | else | |
5214 | ot = dflag + OT_WORD; | |
5215 | #ifdef TARGET_X86_64 | |
8f091a59 | 5216 | if (s->aflag == 2) { |
14ce26e7 FB |
5217 | offset_addr = ldq_code(s->pc); |
5218 | s->pc += 8; | |
57fec1fe | 5219 | gen_op_movq_A0_im(offset_addr); |
5fafdf24 | 5220 | } else |
14ce26e7 FB |
5221 | #endif |
5222 | { | |
5223 | if (s->aflag) { | |
5224 | offset_addr = insn_get(s, OT_LONG); | |
5225 | } else { | |
5226 | offset_addr = insn_get(s, OT_WORD); | |
5227 | } | |
5228 | gen_op_movl_A0_im(offset_addr); | |
5229 | } | |
664e0f19 | 5230 | gen_add_A0_ds_seg(s); |
14ce26e7 | 5231 | if ((b & 2) == 0) { |
57fec1fe FB |
5232 | gen_op_ld_T0_A0(ot + s->mem_index); |
5233 | gen_op_mov_reg_T0(ot, R_EAX); | |
14ce26e7 | 5234 | } else { |
57fec1fe FB |
5235 | gen_op_mov_TN_reg(ot, 0, R_EAX); |
5236 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af FB |
5237 | } |
5238 | } | |
2c0262af FB |
5239 | break; |
5240 | case 0xd7: /* xlat */ | |
14ce26e7 | 5241 | #ifdef TARGET_X86_64 |
8f091a59 | 5242 | if (s->aflag == 2) { |
57fec1fe | 5243 | gen_op_movq_A0_reg(R_EBX); |
bbf662ee FB |
5244 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
5245 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5246 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
5fafdf24 | 5247 | } else |
14ce26e7 FB |
5248 | #endif |
5249 | { | |
57fec1fe | 5250 | gen_op_movl_A0_reg(R_EBX); |
bbf662ee FB |
5251 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
5252 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5253 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
14ce26e7 FB |
5254 | if (s->aflag == 0) |
5255 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
5256 | else |
5257 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
14ce26e7 | 5258 | } |
664e0f19 | 5259 | gen_add_A0_ds_seg(s); |
57fec1fe FB |
5260 | gen_op_ldu_T0_A0(OT_BYTE + s->mem_index); |
5261 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
5262 | break; |
5263 | case 0xb0 ... 0xb7: /* mov R, Ib */ | |
5264 | val = insn_get(s, OT_BYTE); | |
5265 | gen_op_movl_T0_im(val); | |
57fec1fe | 5266 | gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s)); |
2c0262af FB |
5267 | break; |
5268 | case 0xb8 ... 0xbf: /* mov R, Iv */ | |
14ce26e7 FB |
5269 | #ifdef TARGET_X86_64 |
5270 | if (dflag == 2) { | |
5271 | uint64_t tmp; | |
5272 | /* 64 bit case */ | |
5273 | tmp = ldq_code(s->pc); | |
5274 | s->pc += 8; | |
5275 | reg = (b & 7) | REX_B(s); | |
5276 | gen_movtl_T0_im(tmp); | |
57fec1fe | 5277 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 5278 | } else |
14ce26e7 FB |
5279 | #endif |
5280 | { | |
5281 | ot = dflag ? OT_LONG : OT_WORD; | |
5282 | val = insn_get(s, ot); | |
5283 | reg = (b & 7) | REX_B(s); | |
5284 | gen_op_movl_T0_im(val); | |
57fec1fe | 5285 | gen_op_mov_reg_T0(ot, reg); |
14ce26e7 | 5286 | } |
2c0262af FB |
5287 | break; |
5288 | ||
5289 | case 0x91 ... 0x97: /* xchg R, EAX */ | |
7418027e | 5290 | do_xchg_reg_eax: |
14ce26e7 FB |
5291 | ot = dflag + OT_WORD; |
5292 | reg = (b & 7) | REX_B(s); | |
2c0262af FB |
5293 | rm = R_EAX; |
5294 | goto do_xchg_reg; | |
5295 | case 0x86: | |
5296 | case 0x87: /* xchg Ev, Gv */ | |
5297 | if ((b & 1) == 0) | |
5298 | ot = OT_BYTE; | |
5299 | else | |
14ce26e7 | 5300 | ot = dflag + OT_WORD; |
61382a50 | 5301 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5302 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5303 | mod = (modrm >> 6) & 3; |
5304 | if (mod == 3) { | |
14ce26e7 | 5305 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 5306 | do_xchg_reg: |
57fec1fe FB |
5307 | gen_op_mov_TN_reg(ot, 0, reg); |
5308 | gen_op_mov_TN_reg(ot, 1, rm); | |
5309 | gen_op_mov_reg_T0(ot, rm); | |
5310 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af FB |
5311 | } else { |
5312 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 5313 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af FB |
5314 | /* for xchg, lock is implicit */ |
5315 | if (!(prefixes & PREFIX_LOCK)) | |
a7812ae4 | 5316 | gen_helper_lock(); |
57fec1fe FB |
5317 | gen_op_ld_T1_A0(ot + s->mem_index); |
5318 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 5319 | if (!(prefixes & PREFIX_LOCK)) |
a7812ae4 | 5320 | gen_helper_unlock(); |
57fec1fe | 5321 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5322 | } |
5323 | break; | |
5324 | case 0xc4: /* les Gv */ | |
14ce26e7 FB |
5325 | if (CODE64(s)) |
5326 | goto illegal_op; | |
2c0262af FB |
5327 | op = R_ES; |
5328 | goto do_lxx; | |
5329 | case 0xc5: /* lds Gv */ | |
14ce26e7 FB |
5330 | if (CODE64(s)) |
5331 | goto illegal_op; | |
2c0262af FB |
5332 | op = R_DS; |
5333 | goto do_lxx; | |
5334 | case 0x1b2: /* lss Gv */ | |
5335 | op = R_SS; | |
5336 | goto do_lxx; | |
5337 | case 0x1b4: /* lfs Gv */ | |
5338 | op = R_FS; | |
5339 | goto do_lxx; | |
5340 | case 0x1b5: /* lgs Gv */ | |
5341 | op = R_GS; | |
5342 | do_lxx: | |
5343 | ot = dflag ? OT_LONG : OT_WORD; | |
61382a50 | 5344 | modrm = ldub_code(s->pc++); |
14ce26e7 | 5345 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5346 | mod = (modrm >> 6) & 3; |
5347 | if (mod == 3) | |
5348 | goto illegal_op; | |
5349 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 5350 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 5351 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
2c0262af | 5352 | /* load the segment first to handle exceptions properly */ |
57fec1fe | 5353 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5354 | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
5355 | /* then put the data */ | |
57fec1fe | 5356 | gen_op_mov_reg_T1(ot, reg); |
2c0262af | 5357 | if (s->is_jmp) { |
14ce26e7 | 5358 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5359 | gen_eob(s); |
5360 | } | |
5361 | break; | |
3b46e624 | 5362 | |
2c0262af FB |
5363 | /************************/ |
5364 | /* shifts */ | |
5365 | case 0xc0: | |
5366 | case 0xc1: | |
5367 | /* shift Ev,Ib */ | |
5368 | shift = 2; | |
5369 | grp2: | |
5370 | { | |
5371 | if ((b & 1) == 0) | |
5372 | ot = OT_BYTE; | |
5373 | else | |
14ce26e7 | 5374 | ot = dflag + OT_WORD; |
3b46e624 | 5375 | |
61382a50 | 5376 | modrm = ldub_code(s->pc++); |
2c0262af | 5377 | mod = (modrm >> 6) & 3; |
2c0262af | 5378 | op = (modrm >> 3) & 7; |
3b46e624 | 5379 | |
2c0262af | 5380 | if (mod != 3) { |
14ce26e7 FB |
5381 | if (shift == 2) { |
5382 | s->rip_offset = 1; | |
5383 | } | |
2c0262af FB |
5384 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5385 | opreg = OR_TMP0; | |
5386 | } else { | |
14ce26e7 | 5387 | opreg = (modrm & 7) | REX_B(s); |
2c0262af FB |
5388 | } |
5389 | ||
5390 | /* simpler op */ | |
5391 | if (shift == 0) { | |
5392 | gen_shift(s, op, ot, opreg, OR_ECX); | |
5393 | } else { | |
5394 | if (shift == 2) { | |
61382a50 | 5395 | shift = ldub_code(s->pc++); |
2c0262af FB |
5396 | } |
5397 | gen_shifti(s, op, ot, opreg, shift); | |
5398 | } | |
5399 | } | |
5400 | break; | |
5401 | case 0xd0: | |
5402 | case 0xd1: | |
5403 | /* shift Ev,1 */ | |
5404 | shift = 1; | |
5405 | goto grp2; | |
5406 | case 0xd2: | |
5407 | case 0xd3: | |
5408 | /* shift Ev,cl */ | |
5409 | shift = 0; | |
5410 | goto grp2; | |
5411 | ||
5412 | case 0x1a4: /* shld imm */ | |
5413 | op = 0; | |
5414 | shift = 1; | |
5415 | goto do_shiftd; | |
5416 | case 0x1a5: /* shld cl */ | |
5417 | op = 0; | |
5418 | shift = 0; | |
5419 | goto do_shiftd; | |
5420 | case 0x1ac: /* shrd imm */ | |
5421 | op = 1; | |
5422 | shift = 1; | |
5423 | goto do_shiftd; | |
5424 | case 0x1ad: /* shrd cl */ | |
5425 | op = 1; | |
5426 | shift = 0; | |
5427 | do_shiftd: | |
14ce26e7 | 5428 | ot = dflag + OT_WORD; |
61382a50 | 5429 | modrm = ldub_code(s->pc++); |
2c0262af | 5430 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5431 | rm = (modrm & 7) | REX_B(s); |
5432 | reg = ((modrm >> 3) & 7) | rex_r; | |
2c0262af FB |
5433 | if (mod != 3) { |
5434 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
b6abf97d | 5435 | opreg = OR_TMP0; |
2c0262af | 5436 | } else { |
b6abf97d | 5437 | opreg = rm; |
2c0262af | 5438 | } |
57fec1fe | 5439 | gen_op_mov_TN_reg(ot, 1, reg); |
3b46e624 | 5440 | |
2c0262af | 5441 | if (shift) { |
61382a50 | 5442 | val = ldub_code(s->pc++); |
b6abf97d | 5443 | tcg_gen_movi_tl(cpu_T3, val); |
2c0262af | 5444 | } else { |
cc739bb0 | 5445 | tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]); |
2c0262af | 5446 | } |
b6abf97d | 5447 | gen_shiftd_rm_T1_T3(s, ot, opreg, op); |
2c0262af FB |
5448 | break; |
5449 | ||
5450 | /************************/ | |
5451 | /* floats */ | |
5fafdf24 | 5452 | case 0xd8 ... 0xdf: |
7eee2a50 FB |
5453 | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { |
5454 | /* if CR0.EM or CR0.TS are set, generate an FPU exception */ | |
5455 | /* XXX: what to do if illegal op ? */ | |
5456 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
5457 | break; | |
5458 | } | |
61382a50 | 5459 | modrm = ldub_code(s->pc++); |
2c0262af FB |
5460 | mod = (modrm >> 6) & 3; |
5461 | rm = modrm & 7; | |
5462 | op = ((b & 7) << 3) | ((modrm >> 3) & 7); | |
2c0262af FB |
5463 | if (mod != 3) { |
5464 | /* memory op */ | |
5465 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
5466 | switch(op) { | |
5467 | case 0x00 ... 0x07: /* fxxxs */ | |
5468 | case 0x10 ... 0x17: /* fixxxl */ | |
5469 | case 0x20 ... 0x27: /* fxxxl */ | |
5470 | case 0x30 ... 0x37: /* fixxx */ | |
5471 | { | |
5472 | int op1; | |
5473 | op1 = op & 7; | |
5474 | ||
5475 | switch(op >> 4) { | |
5476 | case 0: | |
ba7cd150 | 5477 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5478 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5479 | gen_helper_flds_FT0(cpu_tmp2_i32); |
2c0262af FB |
5480 | break; |
5481 | case 1: | |
ba7cd150 | 5482 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5483 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5484 | gen_helper_fildl_FT0(cpu_tmp2_i32); |
2c0262af FB |
5485 | break; |
5486 | case 2: | |
b6abf97d | 5487 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5488 | (s->mem_index >> 2) - 1); |
a7812ae4 | 5489 | gen_helper_fldl_FT0(cpu_tmp1_i64); |
2c0262af FB |
5490 | break; |
5491 | case 3: | |
5492 | default: | |
ba7cd150 | 5493 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5494 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5495 | gen_helper_fildl_FT0(cpu_tmp2_i32); |
2c0262af FB |
5496 | break; |
5497 | } | |
3b46e624 | 5498 | |
a7812ae4 | 5499 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5500 | if (op1 == 3) { |
5501 | /* fcomp needs pop */ | |
a7812ae4 | 5502 | gen_helper_fpop(); |
2c0262af FB |
5503 | } |
5504 | } | |
5505 | break; | |
5506 | case 0x08: /* flds */ | |
5507 | case 0x0a: /* fsts */ | |
5508 | case 0x0b: /* fstps */ | |
465e9838 FB |
5509 | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
5510 | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ | |
5511 | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ | |
2c0262af FB |
5512 | switch(op & 7) { |
5513 | case 0: | |
5514 | switch(op >> 4) { | |
5515 | case 0: | |
ba7cd150 | 5516 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5517 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5518 | gen_helper_flds_ST0(cpu_tmp2_i32); |
2c0262af FB |
5519 | break; |
5520 | case 1: | |
ba7cd150 | 5521 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5522 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5523 | gen_helper_fildl_ST0(cpu_tmp2_i32); |
2c0262af FB |
5524 | break; |
5525 | case 2: | |
b6abf97d | 5526 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5527 | (s->mem_index >> 2) - 1); |
a7812ae4 | 5528 | gen_helper_fldl_ST0(cpu_tmp1_i64); |
2c0262af FB |
5529 | break; |
5530 | case 3: | |
5531 | default: | |
ba7cd150 | 5532 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5533 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5534 | gen_helper_fildl_ST0(cpu_tmp2_i32); |
2c0262af FB |
5535 | break; |
5536 | } | |
5537 | break; | |
465e9838 | 5538 | case 1: |
19e6c4b8 | 5539 | /* XXX: the corresponding CPUID bit must be tested ! */ |
465e9838 FB |
5540 | switch(op >> 4) { |
5541 | case 1: | |
a7812ae4 | 5542 | gen_helper_fisttl_ST0(cpu_tmp2_i32); |
b6abf97d | 5543 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5544 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
465e9838 FB |
5545 | break; |
5546 | case 2: | |
a7812ae4 | 5547 | gen_helper_fisttll_ST0(cpu_tmp1_i64); |
b6abf97d | 5548 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5549 | (s->mem_index >> 2) - 1); |
465e9838 FB |
5550 | break; |
5551 | case 3: | |
5552 | default: | |
a7812ae4 | 5553 | gen_helper_fistt_ST0(cpu_tmp2_i32); |
b6abf97d | 5554 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5555 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
19e6c4b8 | 5556 | break; |
465e9838 | 5557 | } |
a7812ae4 | 5558 | gen_helper_fpop(); |
465e9838 | 5559 | break; |
2c0262af FB |
5560 | default: |
5561 | switch(op >> 4) { | |
5562 | case 0: | |
a7812ae4 | 5563 | gen_helper_fsts_ST0(cpu_tmp2_i32); |
b6abf97d | 5564 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5565 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5566 | break; |
5567 | case 1: | |
a7812ae4 | 5568 | gen_helper_fistl_ST0(cpu_tmp2_i32); |
b6abf97d | 5569 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5570 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5571 | break; |
5572 | case 2: | |
a7812ae4 | 5573 | gen_helper_fstl_ST0(cpu_tmp1_i64); |
b6abf97d | 5574 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5575 | (s->mem_index >> 2) - 1); |
2c0262af FB |
5576 | break; |
5577 | case 3: | |
5578 | default: | |
a7812ae4 | 5579 | gen_helper_fist_ST0(cpu_tmp2_i32); |
b6abf97d | 5580 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5581 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5582 | break; |
5583 | } | |
5584 | if ((op & 7) == 3) | |
a7812ae4 | 5585 | gen_helper_fpop(); |
2c0262af FB |
5586 | break; |
5587 | } | |
5588 | break; | |
5589 | case 0x0c: /* fldenv mem */ | |
19e6c4b8 FB |
5590 | if (s->cc_op != CC_OP_DYNAMIC) |
5591 | gen_op_set_cc_op(s->cc_op); | |
5592 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5593 | gen_helper_fldenv( |
19e6c4b8 | 5594 | cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5595 | break; |
5596 | case 0x0d: /* fldcw mem */ | |
19e6c4b8 | 5597 | gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5598 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 5599 | gen_helper_fldcw(cpu_tmp2_i32); |
2c0262af FB |
5600 | break; |
5601 | case 0x0e: /* fnstenv mem */ | |
19e6c4b8 FB |
5602 | if (s->cc_op != CC_OP_DYNAMIC) |
5603 | gen_op_set_cc_op(s->cc_op); | |
5604 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5605 | gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5606 | break; |
5607 | case 0x0f: /* fnstcw mem */ | |
a7812ae4 | 5608 | gen_helper_fnstcw(cpu_tmp2_i32); |
b6abf97d | 5609 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5610 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5611 | break; |
5612 | case 0x1d: /* fldt mem */ | |
19e6c4b8 FB |
5613 | if (s->cc_op != CC_OP_DYNAMIC) |
5614 | gen_op_set_cc_op(s->cc_op); | |
5615 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5616 | gen_helper_fldt_ST0(cpu_A0); |
2c0262af FB |
5617 | break; |
5618 | case 0x1f: /* fstpt mem */ | |
19e6c4b8 FB |
5619 | if (s->cc_op != CC_OP_DYNAMIC) |
5620 | gen_op_set_cc_op(s->cc_op); | |
5621 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 PB |
5622 | gen_helper_fstt_ST0(cpu_A0); |
5623 | gen_helper_fpop(); | |
2c0262af FB |
5624 | break; |
5625 | case 0x2c: /* frstor mem */ | |
19e6c4b8 FB |
5626 | if (s->cc_op != CC_OP_DYNAMIC) |
5627 | gen_op_set_cc_op(s->cc_op); | |
5628 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5629 | gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5630 | break; |
5631 | case 0x2e: /* fnsave mem */ | |
19e6c4b8 FB |
5632 | if (s->cc_op != CC_OP_DYNAMIC) |
5633 | gen_op_set_cc_op(s->cc_op); | |
5634 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5635 | gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5636 | break; |
5637 | case 0x2f: /* fnstsw mem */ | |
a7812ae4 | 5638 | gen_helper_fnstsw(cpu_tmp2_i32); |
b6abf97d | 5639 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5640 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5641 | break; |
5642 | case 0x3c: /* fbld */ | |
19e6c4b8 FB |
5643 | if (s->cc_op != CC_OP_DYNAMIC) |
5644 | gen_op_set_cc_op(s->cc_op); | |
5645 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 5646 | gen_helper_fbld_ST0(cpu_A0); |
2c0262af FB |
5647 | break; |
5648 | case 0x3e: /* fbstp */ | |
19e6c4b8 FB |
5649 | if (s->cc_op != CC_OP_DYNAMIC) |
5650 | gen_op_set_cc_op(s->cc_op); | |
5651 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 PB |
5652 | gen_helper_fbst_ST0(cpu_A0); |
5653 | gen_helper_fpop(); | |
2c0262af FB |
5654 | break; |
5655 | case 0x3d: /* fildll */ | |
b6abf97d | 5656 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5657 | (s->mem_index >> 2) - 1); |
a7812ae4 | 5658 | gen_helper_fildll_ST0(cpu_tmp1_i64); |
2c0262af FB |
5659 | break; |
5660 | case 0x3f: /* fistpll */ | |
a7812ae4 | 5661 | gen_helper_fistll_ST0(cpu_tmp1_i64); |
b6abf97d | 5662 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5663 | (s->mem_index >> 2) - 1); |
a7812ae4 | 5664 | gen_helper_fpop(); |
2c0262af FB |
5665 | break; |
5666 | default: | |
5667 | goto illegal_op; | |
5668 | } | |
5669 | } else { | |
5670 | /* register float ops */ | |
5671 | opreg = rm; | |
5672 | ||
5673 | switch(op) { | |
5674 | case 0x08: /* fld sti */ | |
a7812ae4 PB |
5675 | gen_helper_fpush(); |
5676 | gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7)); | |
2c0262af FB |
5677 | break; |
5678 | case 0x09: /* fxchg sti */ | |
c169c906 FB |
5679 | case 0x29: /* fxchg4 sti, undocumented op */ |
5680 | case 0x39: /* fxchg7 sti, undocumented op */ | |
a7812ae4 | 5681 | gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg)); |
2c0262af FB |
5682 | break; |
5683 | case 0x0a: /* grp d9/2 */ | |
5684 | switch(rm) { | |
5685 | case 0: /* fnop */ | |
023fe10d FB |
5686 | /* check exceptions (FreeBSD FPU probe) */ |
5687 | if (s->cc_op != CC_OP_DYNAMIC) | |
5688 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 5689 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 5690 | gen_helper_fwait(); |
2c0262af FB |
5691 | break; |
5692 | default: | |
5693 | goto illegal_op; | |
5694 | } | |
5695 | break; | |
5696 | case 0x0c: /* grp d9/4 */ | |
5697 | switch(rm) { | |
5698 | case 0: /* fchs */ | |
a7812ae4 | 5699 | gen_helper_fchs_ST0(); |
2c0262af FB |
5700 | break; |
5701 | case 1: /* fabs */ | |
a7812ae4 | 5702 | gen_helper_fabs_ST0(); |
2c0262af FB |
5703 | break; |
5704 | case 4: /* ftst */ | |
a7812ae4 PB |
5705 | gen_helper_fldz_FT0(); |
5706 | gen_helper_fcom_ST0_FT0(); | |
2c0262af FB |
5707 | break; |
5708 | case 5: /* fxam */ | |
a7812ae4 | 5709 | gen_helper_fxam_ST0(); |
2c0262af FB |
5710 | break; |
5711 | default: | |
5712 | goto illegal_op; | |
5713 | } | |
5714 | break; | |
5715 | case 0x0d: /* grp d9/5 */ | |
5716 | { | |
5717 | switch(rm) { | |
5718 | case 0: | |
a7812ae4 PB |
5719 | gen_helper_fpush(); |
5720 | gen_helper_fld1_ST0(); | |
2c0262af FB |
5721 | break; |
5722 | case 1: | |
a7812ae4 PB |
5723 | gen_helper_fpush(); |
5724 | gen_helper_fldl2t_ST0(); | |
2c0262af FB |
5725 | break; |
5726 | case 2: | |
a7812ae4 PB |
5727 | gen_helper_fpush(); |
5728 | gen_helper_fldl2e_ST0(); | |
2c0262af FB |
5729 | break; |
5730 | case 3: | |
a7812ae4 PB |
5731 | gen_helper_fpush(); |
5732 | gen_helper_fldpi_ST0(); | |
2c0262af FB |
5733 | break; |
5734 | case 4: | |
a7812ae4 PB |
5735 | gen_helper_fpush(); |
5736 | gen_helper_fldlg2_ST0(); | |
2c0262af FB |
5737 | break; |
5738 | case 5: | |
a7812ae4 PB |
5739 | gen_helper_fpush(); |
5740 | gen_helper_fldln2_ST0(); | |
2c0262af FB |
5741 | break; |
5742 | case 6: | |
a7812ae4 PB |
5743 | gen_helper_fpush(); |
5744 | gen_helper_fldz_ST0(); | |
2c0262af FB |
5745 | break; |
5746 | default: | |
5747 | goto illegal_op; | |
5748 | } | |
5749 | } | |
5750 | break; | |
5751 | case 0x0e: /* grp d9/6 */ | |
5752 | switch(rm) { | |
5753 | case 0: /* f2xm1 */ | |
a7812ae4 | 5754 | gen_helper_f2xm1(); |
2c0262af FB |
5755 | break; |
5756 | case 1: /* fyl2x */ | |
a7812ae4 | 5757 | gen_helper_fyl2x(); |
2c0262af FB |
5758 | break; |
5759 | case 2: /* fptan */ | |
a7812ae4 | 5760 | gen_helper_fptan(); |
2c0262af FB |
5761 | break; |
5762 | case 3: /* fpatan */ | |
a7812ae4 | 5763 | gen_helper_fpatan(); |
2c0262af FB |
5764 | break; |
5765 | case 4: /* fxtract */ | |
a7812ae4 | 5766 | gen_helper_fxtract(); |
2c0262af FB |
5767 | break; |
5768 | case 5: /* fprem1 */ | |
a7812ae4 | 5769 | gen_helper_fprem1(); |
2c0262af FB |
5770 | break; |
5771 | case 6: /* fdecstp */ | |
a7812ae4 | 5772 | gen_helper_fdecstp(); |
2c0262af FB |
5773 | break; |
5774 | default: | |
5775 | case 7: /* fincstp */ | |
a7812ae4 | 5776 | gen_helper_fincstp(); |
2c0262af FB |
5777 | break; |
5778 | } | |
5779 | break; | |
5780 | case 0x0f: /* grp d9/7 */ | |
5781 | switch(rm) { | |
5782 | case 0: /* fprem */ | |
a7812ae4 | 5783 | gen_helper_fprem(); |
2c0262af FB |
5784 | break; |
5785 | case 1: /* fyl2xp1 */ | |
a7812ae4 | 5786 | gen_helper_fyl2xp1(); |
2c0262af FB |
5787 | break; |
5788 | case 2: /* fsqrt */ | |
a7812ae4 | 5789 | gen_helper_fsqrt(); |
2c0262af FB |
5790 | break; |
5791 | case 3: /* fsincos */ | |
a7812ae4 | 5792 | gen_helper_fsincos(); |
2c0262af FB |
5793 | break; |
5794 | case 5: /* fscale */ | |
a7812ae4 | 5795 | gen_helper_fscale(); |
2c0262af FB |
5796 | break; |
5797 | case 4: /* frndint */ | |
a7812ae4 | 5798 | gen_helper_frndint(); |
2c0262af FB |
5799 | break; |
5800 | case 6: /* fsin */ | |
a7812ae4 | 5801 | gen_helper_fsin(); |
2c0262af FB |
5802 | break; |
5803 | default: | |
5804 | case 7: /* fcos */ | |
a7812ae4 | 5805 | gen_helper_fcos(); |
2c0262af FB |
5806 | break; |
5807 | } | |
5808 | break; | |
5809 | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ | |
5810 | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ | |
5811 | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ | |
5812 | { | |
5813 | int op1; | |
3b46e624 | 5814 | |
2c0262af FB |
5815 | op1 = op & 7; |
5816 | if (op >= 0x20) { | |
a7812ae4 | 5817 | gen_helper_fp_arith_STN_ST0(op1, opreg); |
2c0262af | 5818 | if (op >= 0x30) |
a7812ae4 | 5819 | gen_helper_fpop(); |
2c0262af | 5820 | } else { |
a7812ae4 PB |
5821 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5822 | gen_helper_fp_arith_ST0_FT0(op1); | |
2c0262af FB |
5823 | } |
5824 | } | |
5825 | break; | |
5826 | case 0x02: /* fcom */ | |
c169c906 | 5827 | case 0x22: /* fcom2, undocumented op */ |
a7812ae4 PB |
5828 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5829 | gen_helper_fcom_ST0_FT0(); | |
2c0262af FB |
5830 | break; |
5831 | case 0x03: /* fcomp */ | |
c169c906 FB |
5832 | case 0x23: /* fcomp3, undocumented op */ |
5833 | case 0x32: /* fcomp5, undocumented op */ | |
a7812ae4 PB |
5834 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5835 | gen_helper_fcom_ST0_FT0(); | |
5836 | gen_helper_fpop(); | |
2c0262af FB |
5837 | break; |
5838 | case 0x15: /* da/5 */ | |
5839 | switch(rm) { | |
5840 | case 1: /* fucompp */ | |
a7812ae4 PB |
5841 | gen_helper_fmov_FT0_STN(tcg_const_i32(1)); |
5842 | gen_helper_fucom_ST0_FT0(); | |
5843 | gen_helper_fpop(); | |
5844 | gen_helper_fpop(); | |
2c0262af FB |
5845 | break; |
5846 | default: | |
5847 | goto illegal_op; | |
5848 | } | |
5849 | break; | |
5850 | case 0x1c: | |
5851 | switch(rm) { | |
5852 | case 0: /* feni (287 only, just do nop here) */ | |
5853 | break; | |
5854 | case 1: /* fdisi (287 only, just do nop here) */ | |
5855 | break; | |
5856 | case 2: /* fclex */ | |
a7812ae4 | 5857 | gen_helper_fclex(); |
2c0262af FB |
5858 | break; |
5859 | case 3: /* fninit */ | |
a7812ae4 | 5860 | gen_helper_fninit(); |
2c0262af FB |
5861 | break; |
5862 | case 4: /* fsetpm (287 only, just do nop here) */ | |
5863 | break; | |
5864 | default: | |
5865 | goto illegal_op; | |
5866 | } | |
5867 | break; | |
5868 | case 0x1d: /* fucomi */ | |
5869 | if (s->cc_op != CC_OP_DYNAMIC) | |
5870 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 PB |
5871 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5872 | gen_helper_fucomi_ST0_FT0(); | |
2c0262af FB |
5873 | s->cc_op = CC_OP_EFLAGS; |
5874 | break; | |
5875 | case 0x1e: /* fcomi */ | |
5876 | if (s->cc_op != CC_OP_DYNAMIC) | |
5877 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 PB |
5878 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5879 | gen_helper_fcomi_ST0_FT0(); | |
2c0262af FB |
5880 | s->cc_op = CC_OP_EFLAGS; |
5881 | break; | |
658c8bda | 5882 | case 0x28: /* ffree sti */ |
a7812ae4 | 5883 | gen_helper_ffree_STN(tcg_const_i32(opreg)); |
5fafdf24 | 5884 | break; |
2c0262af | 5885 | case 0x2a: /* fst sti */ |
a7812ae4 | 5886 | gen_helper_fmov_STN_ST0(tcg_const_i32(opreg)); |
2c0262af FB |
5887 | break; |
5888 | case 0x2b: /* fstp sti */ | |
c169c906 FB |
5889 | case 0x0b: /* fstp1 sti, undocumented op */ |
5890 | case 0x3a: /* fstp8 sti, undocumented op */ | |
5891 | case 0x3b: /* fstp9 sti, undocumented op */ | |
a7812ae4 PB |
5892 | gen_helper_fmov_STN_ST0(tcg_const_i32(opreg)); |
5893 | gen_helper_fpop(); | |
2c0262af FB |
5894 | break; |
5895 | case 0x2c: /* fucom st(i) */ | |
a7812ae4 PB |
5896 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5897 | gen_helper_fucom_ST0_FT0(); | |
2c0262af FB |
5898 | break; |
5899 | case 0x2d: /* fucomp st(i) */ | |
a7812ae4 PB |
5900 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5901 | gen_helper_fucom_ST0_FT0(); | |
5902 | gen_helper_fpop(); | |
2c0262af FB |
5903 | break; |
5904 | case 0x33: /* de/3 */ | |
5905 | switch(rm) { | |
5906 | case 1: /* fcompp */ | |
a7812ae4 PB |
5907 | gen_helper_fmov_FT0_STN(tcg_const_i32(1)); |
5908 | gen_helper_fcom_ST0_FT0(); | |
5909 | gen_helper_fpop(); | |
5910 | gen_helper_fpop(); | |
2c0262af FB |
5911 | break; |
5912 | default: | |
5913 | goto illegal_op; | |
5914 | } | |
5915 | break; | |
c169c906 | 5916 | case 0x38: /* ffreep sti, undocumented op */ |
a7812ae4 PB |
5917 | gen_helper_ffree_STN(tcg_const_i32(opreg)); |
5918 | gen_helper_fpop(); | |
c169c906 | 5919 | break; |
2c0262af FB |
5920 | case 0x3c: /* df/4 */ |
5921 | switch(rm) { | |
5922 | case 0: | |
a7812ae4 | 5923 | gen_helper_fnstsw(cpu_tmp2_i32); |
b6abf97d | 5924 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5925 | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
2c0262af FB |
5926 | break; |
5927 | default: | |
5928 | goto illegal_op; | |
5929 | } | |
5930 | break; | |
5931 | case 0x3d: /* fucomip */ | |
5932 | if (s->cc_op != CC_OP_DYNAMIC) | |
5933 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 PB |
5934 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5935 | gen_helper_fucomi_ST0_FT0(); | |
5936 | gen_helper_fpop(); | |
2c0262af FB |
5937 | s->cc_op = CC_OP_EFLAGS; |
5938 | break; | |
5939 | case 0x3e: /* fcomip */ | |
5940 | if (s->cc_op != CC_OP_DYNAMIC) | |
5941 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 PB |
5942 | gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); |
5943 | gen_helper_fcomi_ST0_FT0(); | |
5944 | gen_helper_fpop(); | |
2c0262af FB |
5945 | s->cc_op = CC_OP_EFLAGS; |
5946 | break; | |
a2cc3b24 FB |
5947 | case 0x10 ... 0x13: /* fcmovxx */ |
5948 | case 0x18 ... 0x1b: | |
5949 | { | |
19e6c4b8 | 5950 | int op1, l1; |
d70040bc | 5951 | static const uint8_t fcmov_cc[8] = { |
a2cc3b24 FB |
5952 | (JCC_B << 1), |
5953 | (JCC_Z << 1), | |
5954 | (JCC_BE << 1), | |
5955 | (JCC_P << 1), | |
5956 | }; | |
1e4840bf | 5957 | op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); |
19e6c4b8 | 5958 | l1 = gen_new_label(); |
1e4840bf | 5959 | gen_jcc1(s, s->cc_op, op1, l1); |
a7812ae4 | 5960 | gen_helper_fmov_ST0_STN(tcg_const_i32(opreg)); |
19e6c4b8 | 5961 | gen_set_label(l1); |
a2cc3b24 FB |
5962 | } |
5963 | break; | |
2c0262af FB |
5964 | default: |
5965 | goto illegal_op; | |
5966 | } | |
5967 | } | |
5968 | break; | |
5969 | /************************/ | |
5970 | /* string ops */ | |
5971 | ||
5972 | case 0xa4: /* movsS */ | |
5973 | case 0xa5: | |
5974 | if ((b & 1) == 0) | |
5975 | ot = OT_BYTE; | |
5976 | else | |
14ce26e7 | 5977 | ot = dflag + OT_WORD; |
2c0262af FB |
5978 | |
5979 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
5980 | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
5981 | } else { | |
5982 | gen_movs(s, ot); | |
5983 | } | |
5984 | break; | |
3b46e624 | 5985 | |
2c0262af FB |
5986 | case 0xaa: /* stosS */ |
5987 | case 0xab: | |
5988 | if ((b & 1) == 0) | |
5989 | ot = OT_BYTE; | |
5990 | else | |
14ce26e7 | 5991 | ot = dflag + OT_WORD; |
2c0262af FB |
5992 | |
5993 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
5994 | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
5995 | } else { | |
5996 | gen_stos(s, ot); | |
5997 | } | |
5998 | break; | |
5999 | case 0xac: /* lodsS */ | |
6000 | case 0xad: | |
6001 | if ((b & 1) == 0) | |
6002 | ot = OT_BYTE; | |
6003 | else | |
14ce26e7 | 6004 | ot = dflag + OT_WORD; |
2c0262af FB |
6005 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6006 | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6007 | } else { | |
6008 | gen_lods(s, ot); | |
6009 | } | |
6010 | break; | |
6011 | case 0xae: /* scasS */ | |
6012 | case 0xaf: | |
6013 | if ((b & 1) == 0) | |
6014 | ot = OT_BYTE; | |
6015 | else | |
14ce26e7 | 6016 | ot = dflag + OT_WORD; |
2c0262af FB |
6017 | if (prefixes & PREFIX_REPNZ) { |
6018 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6019 | } else if (prefixes & PREFIX_REPZ) { | |
6020 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6021 | } else { | |
6022 | gen_scas(s, ot); | |
6023 | s->cc_op = CC_OP_SUBB + ot; | |
6024 | } | |
6025 | break; | |
6026 | ||
6027 | case 0xa6: /* cmpsS */ | |
6028 | case 0xa7: | |
6029 | if ((b & 1) == 0) | |
6030 | ot = OT_BYTE; | |
6031 | else | |
14ce26e7 | 6032 | ot = dflag + OT_WORD; |
2c0262af FB |
6033 | if (prefixes & PREFIX_REPNZ) { |
6034 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6035 | } else if (prefixes & PREFIX_REPZ) { | |
6036 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6037 | } else { | |
6038 | gen_cmps(s, ot); | |
6039 | s->cc_op = CC_OP_SUBB + ot; | |
6040 | } | |
6041 | break; | |
6042 | case 0x6c: /* insS */ | |
6043 | case 0x6d: | |
f115e911 FB |
6044 | if ((b & 1) == 0) |
6045 | ot = OT_BYTE; | |
6046 | else | |
6047 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6048 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6049 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6050 | gen_check_io(s, ot, pc_start - s->cs_base, |
6051 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6052 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6053 | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6054 | } else { |
f115e911 | 6055 | gen_ins(s, ot); |
2e70f6ef PB |
6056 | if (use_icount) { |
6057 | gen_jmp(s, s->pc - s->cs_base); | |
6058 | } | |
2c0262af FB |
6059 | } |
6060 | break; | |
6061 | case 0x6e: /* outsS */ | |
6062 | case 0x6f: | |
f115e911 FB |
6063 | if ((b & 1) == 0) |
6064 | ot = OT_BYTE; | |
6065 | else | |
6066 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6067 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6068 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6069 | gen_check_io(s, ot, pc_start - s->cs_base, |
6070 | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6071 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6072 | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6073 | } else { |
f115e911 | 6074 | gen_outs(s, ot); |
2e70f6ef PB |
6075 | if (use_icount) { |
6076 | gen_jmp(s, s->pc - s->cs_base); | |
6077 | } | |
2c0262af FB |
6078 | } |
6079 | break; | |
6080 | ||
6081 | /************************/ | |
6082 | /* port I/O */ | |
0573fbfc | 6083 | |
2c0262af FB |
6084 | case 0xe4: |
6085 | case 0xe5: | |
f115e911 FB |
6086 | if ((b & 1) == 0) |
6087 | ot = OT_BYTE; | |
6088 | else | |
6089 | ot = dflag ? OT_LONG : OT_WORD; | |
6090 | val = ldub_code(s->pc++); | |
6091 | gen_op_movl_T0_im(val); | |
b8b6a50b FB |
6092 | gen_check_io(s, ot, pc_start - s->cs_base, |
6093 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6094 | if (use_icount) |
6095 | gen_io_start(); | |
b6abf97d | 6096 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6097 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6098 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6099 | if (use_icount) { |
6100 | gen_io_end(); | |
6101 | gen_jmp(s, s->pc - s->cs_base); | |
6102 | } | |
2c0262af FB |
6103 | break; |
6104 | case 0xe6: | |
6105 | case 0xe7: | |
f115e911 FB |
6106 | if ((b & 1) == 0) |
6107 | ot = OT_BYTE; | |
6108 | else | |
6109 | ot = dflag ? OT_LONG : OT_WORD; | |
6110 | val = ldub_code(s->pc++); | |
6111 | gen_op_movl_T0_im(val); | |
b8b6a50b FB |
6112 | gen_check_io(s, ot, pc_start - s->cs_base, |
6113 | svm_is_rep(prefixes)); | |
57fec1fe | 6114 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6115 | |
2e70f6ef PB |
6116 | if (use_icount) |
6117 | gen_io_start(); | |
b6abf97d | 6118 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6119 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6120 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6121 | if (use_icount) { |
6122 | gen_io_end(); | |
6123 | gen_jmp(s, s->pc - s->cs_base); | |
6124 | } | |
2c0262af FB |
6125 | break; |
6126 | case 0xec: | |
6127 | case 0xed: | |
f115e911 FB |
6128 | if ((b & 1) == 0) |
6129 | ot = OT_BYTE; | |
6130 | else | |
6131 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6132 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6133 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6134 | gen_check_io(s, ot, pc_start - s->cs_base, |
6135 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6136 | if (use_icount) |
6137 | gen_io_start(); | |
b6abf97d | 6138 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6139 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6140 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6141 | if (use_icount) { |
6142 | gen_io_end(); | |
6143 | gen_jmp(s, s->pc - s->cs_base); | |
6144 | } | |
2c0262af FB |
6145 | break; |
6146 | case 0xee: | |
6147 | case 0xef: | |
f115e911 FB |
6148 | if ((b & 1) == 0) |
6149 | ot = OT_BYTE; | |
6150 | else | |
6151 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6152 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6153 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6154 | gen_check_io(s, ot, pc_start - s->cs_base, |
6155 | svm_is_rep(prefixes)); | |
57fec1fe | 6156 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6157 | |
2e70f6ef PB |
6158 | if (use_icount) |
6159 | gen_io_start(); | |
b6abf97d | 6160 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6161 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6162 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6163 | if (use_icount) { |
6164 | gen_io_end(); | |
6165 | gen_jmp(s, s->pc - s->cs_base); | |
6166 | } | |
2c0262af FB |
6167 | break; |
6168 | ||
6169 | /************************/ | |
6170 | /* control */ | |
6171 | case 0xc2: /* ret im */ | |
61382a50 | 6172 | val = ldsw_code(s->pc); |
2c0262af FB |
6173 | s->pc += 2; |
6174 | gen_pop_T0(s); | |
8f091a59 FB |
6175 | if (CODE64(s) && s->dflag) |
6176 | s->dflag = 2; | |
2c0262af FB |
6177 | gen_stack_update(s, val + (2 << s->dflag)); |
6178 | if (s->dflag == 0) | |
6179 | gen_op_andl_T0_ffff(); | |
6180 | gen_op_jmp_T0(); | |
6181 | gen_eob(s); | |
6182 | break; | |
6183 | case 0xc3: /* ret */ | |
6184 | gen_pop_T0(s); | |
6185 | gen_pop_update(s); | |
6186 | if (s->dflag == 0) | |
6187 | gen_op_andl_T0_ffff(); | |
6188 | gen_op_jmp_T0(); | |
6189 | gen_eob(s); | |
6190 | break; | |
6191 | case 0xca: /* lret im */ | |
61382a50 | 6192 | val = ldsw_code(s->pc); |
2c0262af FB |
6193 | s->pc += 2; |
6194 | do_lret: | |
6195 | if (s->pe && !s->vm86) { | |
6196 | if (s->cc_op != CC_OP_DYNAMIC) | |
6197 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6198 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 PB |
6199 | gen_helper_lret_protected(tcg_const_i32(s->dflag), |
6200 | tcg_const_i32(val)); | |
2c0262af FB |
6201 | } else { |
6202 | gen_stack_A0(s); | |
6203 | /* pop offset */ | |
57fec1fe | 6204 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
2c0262af FB |
6205 | if (s->dflag == 0) |
6206 | gen_op_andl_T0_ffff(); | |
6207 | /* NOTE: keeping EIP updated is not a problem in case of | |
6208 | exception */ | |
6209 | gen_op_jmp_T0(); | |
6210 | /* pop selector */ | |
6211 | gen_op_addl_A0_im(2 << s->dflag); | |
57fec1fe | 6212 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
3bd7da9e | 6213 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
6214 | /* add stack offset */ |
6215 | gen_stack_update(s, val + (4 << s->dflag)); | |
6216 | } | |
6217 | gen_eob(s); | |
6218 | break; | |
6219 | case 0xcb: /* lret */ | |
6220 | val = 0; | |
6221 | goto do_lret; | |
6222 | case 0xcf: /* iret */ | |
872929aa | 6223 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); |
2c0262af FB |
6224 | if (!s->pe) { |
6225 | /* real mode */ | |
a7812ae4 | 6226 | gen_helper_iret_real(tcg_const_i32(s->dflag)); |
2c0262af | 6227 | s->cc_op = CC_OP_EFLAGS; |
f115e911 FB |
6228 | } else if (s->vm86) { |
6229 | if (s->iopl != 3) { | |
6230 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6231 | } else { | |
a7812ae4 | 6232 | gen_helper_iret_real(tcg_const_i32(s->dflag)); |
f115e911 FB |
6233 | s->cc_op = CC_OP_EFLAGS; |
6234 | } | |
2c0262af FB |
6235 | } else { |
6236 | if (s->cc_op != CC_OP_DYNAMIC) | |
6237 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6238 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 PB |
6239 | gen_helper_iret_protected(tcg_const_i32(s->dflag), |
6240 | tcg_const_i32(s->pc - s->cs_base)); | |
2c0262af FB |
6241 | s->cc_op = CC_OP_EFLAGS; |
6242 | } | |
6243 | gen_eob(s); | |
6244 | break; | |
6245 | case 0xe8: /* call im */ | |
6246 | { | |
14ce26e7 FB |
6247 | if (dflag) |
6248 | tval = (int32_t)insn_get(s, OT_LONG); | |
6249 | else | |
6250 | tval = (int16_t)insn_get(s, OT_WORD); | |
2c0262af | 6251 | next_eip = s->pc - s->cs_base; |
14ce26e7 | 6252 | tval += next_eip; |
2c0262af | 6253 | if (s->dflag == 0) |
14ce26e7 | 6254 | tval &= 0xffff; |
99596385 AJ |
6255 | else if(!CODE64(s)) |
6256 | tval &= 0xffffffff; | |
14ce26e7 | 6257 | gen_movtl_T0_im(next_eip); |
2c0262af | 6258 | gen_push_T0(s); |
14ce26e7 | 6259 | gen_jmp(s, tval); |
2c0262af FB |
6260 | } |
6261 | break; | |
6262 | case 0x9a: /* lcall im */ | |
6263 | { | |
6264 | unsigned int selector, offset; | |
3b46e624 | 6265 | |
14ce26e7 FB |
6266 | if (CODE64(s)) |
6267 | goto illegal_op; | |
2c0262af FB |
6268 | ot = dflag ? OT_LONG : OT_WORD; |
6269 | offset = insn_get(s, ot); | |
6270 | selector = insn_get(s, OT_WORD); | |
3b46e624 | 6271 | |
2c0262af | 6272 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6273 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6274 | } |
6275 | goto do_lcall; | |
ecada8a2 | 6276 | case 0xe9: /* jmp im */ |
14ce26e7 FB |
6277 | if (dflag) |
6278 | tval = (int32_t)insn_get(s, OT_LONG); | |
6279 | else | |
6280 | tval = (int16_t)insn_get(s, OT_WORD); | |
6281 | tval += s->pc - s->cs_base; | |
2c0262af | 6282 | if (s->dflag == 0) |
14ce26e7 | 6283 | tval &= 0xffff; |
32938e12 AJ |
6284 | else if(!CODE64(s)) |
6285 | tval &= 0xffffffff; | |
14ce26e7 | 6286 | gen_jmp(s, tval); |
2c0262af FB |
6287 | break; |
6288 | case 0xea: /* ljmp im */ | |
6289 | { | |
6290 | unsigned int selector, offset; | |
6291 | ||
14ce26e7 FB |
6292 | if (CODE64(s)) |
6293 | goto illegal_op; | |
2c0262af FB |
6294 | ot = dflag ? OT_LONG : OT_WORD; |
6295 | offset = insn_get(s, ot); | |
6296 | selector = insn_get(s, OT_WORD); | |
3b46e624 | 6297 | |
2c0262af | 6298 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6299 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6300 | } |
6301 | goto do_ljmp; | |
6302 | case 0xeb: /* jmp Jb */ | |
14ce26e7 FB |
6303 | tval = (int8_t)insn_get(s, OT_BYTE); |
6304 | tval += s->pc - s->cs_base; | |
2c0262af | 6305 | if (s->dflag == 0) |
14ce26e7 FB |
6306 | tval &= 0xffff; |
6307 | gen_jmp(s, tval); | |
2c0262af FB |
6308 | break; |
6309 | case 0x70 ... 0x7f: /* jcc Jb */ | |
14ce26e7 | 6310 | tval = (int8_t)insn_get(s, OT_BYTE); |
2c0262af FB |
6311 | goto do_jcc; |
6312 | case 0x180 ... 0x18f: /* jcc Jv */ | |
6313 | if (dflag) { | |
14ce26e7 | 6314 | tval = (int32_t)insn_get(s, OT_LONG); |
2c0262af | 6315 | } else { |
5fafdf24 | 6316 | tval = (int16_t)insn_get(s, OT_WORD); |
2c0262af FB |
6317 | } |
6318 | do_jcc: | |
6319 | next_eip = s->pc - s->cs_base; | |
14ce26e7 | 6320 | tval += next_eip; |
2c0262af | 6321 | if (s->dflag == 0) |
14ce26e7 FB |
6322 | tval &= 0xffff; |
6323 | gen_jcc(s, b, tval, next_eip); | |
2c0262af FB |
6324 | break; |
6325 | ||
6326 | case 0x190 ... 0x19f: /* setcc Gv */ | |
61382a50 | 6327 | modrm = ldub_code(s->pc++); |
2c0262af FB |
6328 | gen_setcc(s, b); |
6329 | gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1); | |
6330 | break; | |
6331 | case 0x140 ... 0x14f: /* cmov Gv, Ev */ | |
8e1c85e3 FB |
6332 | { |
6333 | int l1; | |
1e4840bf FB |
6334 | TCGv t0; |
6335 | ||
8e1c85e3 FB |
6336 | ot = dflag + OT_WORD; |
6337 | modrm = ldub_code(s->pc++); | |
6338 | reg = ((modrm >> 3) & 7) | rex_r; | |
6339 | mod = (modrm >> 6) & 3; | |
a7812ae4 | 6340 | t0 = tcg_temp_local_new(); |
8e1c85e3 FB |
6341 | if (mod != 3) { |
6342 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
1e4840bf | 6343 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
8e1c85e3 FB |
6344 | } else { |
6345 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 6346 | gen_op_mov_v_reg(ot, t0, rm); |
8e1c85e3 | 6347 | } |
8e1c85e3 FB |
6348 | #ifdef TARGET_X86_64 |
6349 | if (ot == OT_LONG) { | |
6350 | /* XXX: specific Intel behaviour ? */ | |
6351 | l1 = gen_new_label(); | |
6352 | gen_jcc1(s, s->cc_op, b ^ 1, l1); | |
cc739bb0 | 6353 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
8e1c85e3 | 6354 | gen_set_label(l1); |
cc739bb0 | 6355 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]); |
8e1c85e3 FB |
6356 | } else |
6357 | #endif | |
6358 | { | |
6359 | l1 = gen_new_label(); | |
6360 | gen_jcc1(s, s->cc_op, b ^ 1, l1); | |
1e4840bf | 6361 | gen_op_mov_reg_v(ot, reg, t0); |
8e1c85e3 FB |
6362 | gen_set_label(l1); |
6363 | } | |
1e4840bf | 6364 | tcg_temp_free(t0); |
2c0262af | 6365 | } |
2c0262af | 6366 | break; |
3b46e624 | 6367 | |
2c0262af FB |
6368 | /************************/ |
6369 | /* flags */ | |
6370 | case 0x9c: /* pushf */ | |
872929aa | 6371 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); |
2c0262af FB |
6372 | if (s->vm86 && s->iopl != 3) { |
6373 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6374 | } else { | |
6375 | if (s->cc_op != CC_OP_DYNAMIC) | |
6376 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6377 | gen_helper_read_eflags(cpu_T[0]); |
2c0262af FB |
6378 | gen_push_T0(s); |
6379 | } | |
6380 | break; | |
6381 | case 0x9d: /* popf */ | |
872929aa | 6382 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); |
2c0262af FB |
6383 | if (s->vm86 && s->iopl != 3) { |
6384 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6385 | } else { | |
6386 | gen_pop_T0(s); | |
6387 | if (s->cpl == 0) { | |
6388 | if (s->dflag) { | |
a7812ae4 | 6389 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6390 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK))); |
2c0262af | 6391 | } else { |
a7812ae4 | 6392 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6393 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff)); |
2c0262af FB |
6394 | } |
6395 | } else { | |
4136f33c FB |
6396 | if (s->cpl <= s->iopl) { |
6397 | if (s->dflag) { | |
a7812ae4 | 6398 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6399 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK))); |
4136f33c | 6400 | } else { |
a7812ae4 | 6401 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6402 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff)); |
4136f33c | 6403 | } |
2c0262af | 6404 | } else { |
4136f33c | 6405 | if (s->dflag) { |
a7812ae4 | 6406 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6407 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK))); |
4136f33c | 6408 | } else { |
a7812ae4 | 6409 | gen_helper_write_eflags(cpu_T[0], |
bd7a7b33 | 6410 | tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff)); |
4136f33c | 6411 | } |
2c0262af FB |
6412 | } |
6413 | } | |
6414 | gen_pop_update(s); | |
6415 | s->cc_op = CC_OP_EFLAGS; | |
6416 | /* abort translation because TF flag may change */ | |
14ce26e7 | 6417 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6418 | gen_eob(s); |
6419 | } | |
6420 | break; | |
6421 | case 0x9e: /* sahf */ | |
12e26b75 | 6422 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6423 | goto illegal_op; |
57fec1fe | 6424 | gen_op_mov_TN_reg(OT_BYTE, 0, R_AH); |
2c0262af FB |
6425 | if (s->cc_op != CC_OP_DYNAMIC) |
6426 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6427 | gen_compute_eflags(cpu_cc_src); |
6428 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); | |
6429 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); | |
6430 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); | |
2c0262af FB |
6431 | s->cc_op = CC_OP_EFLAGS; |
6432 | break; | |
6433 | case 0x9f: /* lahf */ | |
12e26b75 | 6434 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6435 | goto illegal_op; |
2c0262af FB |
6436 | if (s->cc_op != CC_OP_DYNAMIC) |
6437 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6438 | gen_compute_eflags(cpu_T[0]); |
6439 | /* Note: gen_compute_eflags() only gives the condition codes */ | |
6440 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02); | |
57fec1fe | 6441 | gen_op_mov_reg_T0(OT_BYTE, R_AH); |
2c0262af FB |
6442 | break; |
6443 | case 0xf5: /* cmc */ | |
6444 | if (s->cc_op != CC_OP_DYNAMIC) | |
6445 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6446 | gen_compute_eflags(cpu_cc_src); |
6447 | tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); | |
2c0262af FB |
6448 | s->cc_op = CC_OP_EFLAGS; |
6449 | break; | |
6450 | case 0xf8: /* clc */ | |
6451 | if (s->cc_op != CC_OP_DYNAMIC) | |
6452 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6453 | gen_compute_eflags(cpu_cc_src); |
6454 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); | |
2c0262af FB |
6455 | s->cc_op = CC_OP_EFLAGS; |
6456 | break; | |
6457 | case 0xf9: /* stc */ | |
6458 | if (s->cc_op != CC_OP_DYNAMIC) | |
6459 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6460 | gen_compute_eflags(cpu_cc_src); |
6461 | tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); | |
2c0262af FB |
6462 | s->cc_op = CC_OP_EFLAGS; |
6463 | break; | |
6464 | case 0xfc: /* cld */ | |
b6abf97d FB |
6465 | tcg_gen_movi_i32(cpu_tmp2_i32, 1); |
6466 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); | |
2c0262af FB |
6467 | break; |
6468 | case 0xfd: /* std */ | |
b6abf97d FB |
6469 | tcg_gen_movi_i32(cpu_tmp2_i32, -1); |
6470 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df)); | |
2c0262af FB |
6471 | break; |
6472 | ||
6473 | /************************/ | |
6474 | /* bit operations */ | |
6475 | case 0x1ba: /* bt/bts/btr/btc Gv, im */ | |
14ce26e7 | 6476 | ot = dflag + OT_WORD; |
61382a50 | 6477 | modrm = ldub_code(s->pc++); |
33698e5f | 6478 | op = (modrm >> 3) & 7; |
2c0262af | 6479 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6480 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 6481 | if (mod != 3) { |
14ce26e7 | 6482 | s->rip_offset = 1; |
2c0262af | 6483 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
57fec1fe | 6484 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6485 | } else { |
57fec1fe | 6486 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
6487 | } |
6488 | /* load shift */ | |
61382a50 | 6489 | val = ldub_code(s->pc++); |
2c0262af FB |
6490 | gen_op_movl_T1_im(val); |
6491 | if (op < 4) | |
6492 | goto illegal_op; | |
6493 | op -= 4; | |
f484d386 | 6494 | goto bt_op; |
2c0262af FB |
6495 | case 0x1a3: /* bt Gv, Ev */ |
6496 | op = 0; | |
6497 | goto do_btx; | |
6498 | case 0x1ab: /* bts */ | |
6499 | op = 1; | |
6500 | goto do_btx; | |
6501 | case 0x1b3: /* btr */ | |
6502 | op = 2; | |
6503 | goto do_btx; | |
6504 | case 0x1bb: /* btc */ | |
6505 | op = 3; | |
6506 | do_btx: | |
14ce26e7 | 6507 | ot = dflag + OT_WORD; |
61382a50 | 6508 | modrm = ldub_code(s->pc++); |
14ce26e7 | 6509 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 6510 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6511 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 6512 | gen_op_mov_TN_reg(OT_LONG, 1, reg); |
2c0262af FB |
6513 | if (mod != 3) { |
6514 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
6515 | /* specific case: we need to add a displacement */ | |
f484d386 FB |
6516 | gen_exts(ot, cpu_T[1]); |
6517 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); | |
6518 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); | |
6519 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe | 6520 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6521 | } else { |
57fec1fe | 6522 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 6523 | } |
f484d386 FB |
6524 | bt_op: |
6525 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); | |
6526 | switch(op) { | |
6527 | case 0: | |
6528 | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); | |
6529 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6530 | break; | |
6531 | case 1: | |
6532 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6533 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6534 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6535 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6536 | break; | |
6537 | case 2: | |
6538 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6539 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6540 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6541 | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); | |
6542 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6543 | break; | |
6544 | default: | |
6545 | case 3: | |
6546 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6547 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6548 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6549 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6550 | break; | |
6551 | } | |
2c0262af FB |
6552 | s->cc_op = CC_OP_SARB + ot; |
6553 | if (op != 0) { | |
6554 | if (mod != 3) | |
57fec1fe | 6555 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 6556 | else |
57fec1fe | 6557 | gen_op_mov_reg_T0(ot, rm); |
f484d386 FB |
6558 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
6559 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
2c0262af FB |
6560 | } |
6561 | break; | |
6562 | case 0x1bc: /* bsf */ | |
6563 | case 0x1bd: /* bsr */ | |
6191b059 FB |
6564 | { |
6565 | int label1; | |
1e4840bf FB |
6566 | TCGv t0; |
6567 | ||
6191b059 FB |
6568 | ot = dflag + OT_WORD; |
6569 | modrm = ldub_code(s->pc++); | |
6570 | reg = ((modrm >> 3) & 7) | rex_r; | |
31501a71 | 6571 | gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0); |
6191b059 | 6572 | gen_extu(ot, cpu_T[0]); |
a7812ae4 | 6573 | t0 = tcg_temp_local_new(); |
1e4840bf | 6574 | tcg_gen_mov_tl(t0, cpu_T[0]); |
31501a71 AP |
6575 | if ((b & 1) && (prefixes & PREFIX_REPZ) && |
6576 | (s->cpuid_ext3_features & CPUID_EXT3_ABM)) { | |
6577 | switch(ot) { | |
6578 | case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0, | |
6579 | tcg_const_i32(16)); break; | |
6580 | case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0, | |
6581 | tcg_const_i32(32)); break; | |
6582 | case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0, | |
6583 | tcg_const_i32(64)); break; | |
6584 | } | |
6585 | gen_op_mov_reg_T0(ot, reg); | |
6191b059 | 6586 | } else { |
31501a71 AP |
6587 | label1 = gen_new_label(); |
6588 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6589 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1); | |
6590 | if (b & 1) { | |
6591 | gen_helper_bsr(cpu_T[0], t0); | |
6592 | } else { | |
6593 | gen_helper_bsf(cpu_T[0], t0); | |
6594 | } | |
6595 | gen_op_mov_reg_T0(ot, reg); | |
6596 | tcg_gen_movi_tl(cpu_cc_dst, 1); | |
6597 | gen_set_label(label1); | |
6598 | tcg_gen_discard_tl(cpu_cc_src); | |
6599 | s->cc_op = CC_OP_LOGICB + ot; | |
6191b059 | 6600 | } |
1e4840bf | 6601 | tcg_temp_free(t0); |
6191b059 | 6602 | } |
2c0262af FB |
6603 | break; |
6604 | /************************/ | |
6605 | /* bcd */ | |
6606 | case 0x27: /* daa */ | |
14ce26e7 FB |
6607 | if (CODE64(s)) |
6608 | goto illegal_op; | |
2c0262af FB |
6609 | if (s->cc_op != CC_OP_DYNAMIC) |
6610 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6611 | gen_helper_daa(); |
2c0262af FB |
6612 | s->cc_op = CC_OP_EFLAGS; |
6613 | break; | |
6614 | case 0x2f: /* das */ | |
14ce26e7 FB |
6615 | if (CODE64(s)) |
6616 | goto illegal_op; | |
2c0262af FB |
6617 | if (s->cc_op != CC_OP_DYNAMIC) |
6618 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6619 | gen_helper_das(); |
2c0262af FB |
6620 | s->cc_op = CC_OP_EFLAGS; |
6621 | break; | |
6622 | case 0x37: /* aaa */ | |
14ce26e7 FB |
6623 | if (CODE64(s)) |
6624 | goto illegal_op; | |
2c0262af FB |
6625 | if (s->cc_op != CC_OP_DYNAMIC) |
6626 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6627 | gen_helper_aaa(); |
2c0262af FB |
6628 | s->cc_op = CC_OP_EFLAGS; |
6629 | break; | |
6630 | case 0x3f: /* aas */ | |
14ce26e7 FB |
6631 | if (CODE64(s)) |
6632 | goto illegal_op; | |
2c0262af FB |
6633 | if (s->cc_op != CC_OP_DYNAMIC) |
6634 | gen_op_set_cc_op(s->cc_op); | |
a7812ae4 | 6635 | gen_helper_aas(); |
2c0262af FB |
6636 | s->cc_op = CC_OP_EFLAGS; |
6637 | break; | |
6638 | case 0xd4: /* aam */ | |
14ce26e7 FB |
6639 | if (CODE64(s)) |
6640 | goto illegal_op; | |
61382a50 | 6641 | val = ldub_code(s->pc++); |
b6d7c3db TS |
6642 | if (val == 0) { |
6643 | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); | |
6644 | } else { | |
a7812ae4 | 6645 | gen_helper_aam(tcg_const_i32(val)); |
b6d7c3db TS |
6646 | s->cc_op = CC_OP_LOGICB; |
6647 | } | |
2c0262af FB |
6648 | break; |
6649 | case 0xd5: /* aad */ | |
14ce26e7 FB |
6650 | if (CODE64(s)) |
6651 | goto illegal_op; | |
61382a50 | 6652 | val = ldub_code(s->pc++); |
a7812ae4 | 6653 | gen_helper_aad(tcg_const_i32(val)); |
2c0262af FB |
6654 | s->cc_op = CC_OP_LOGICB; |
6655 | break; | |
6656 | /************************/ | |
6657 | /* misc */ | |
6658 | case 0x90: /* nop */ | |
ab1f142b | 6659 | /* XXX: correct lock test for all insn */ |
7418027e | 6660 | if (prefixes & PREFIX_LOCK) { |
ab1f142b | 6661 | goto illegal_op; |
7418027e RH |
6662 | } |
6663 | /* If REX_B is set, then this is xchg eax, r8d, not a nop. */ | |
6664 | if (REX_B(s)) { | |
6665 | goto do_xchg_reg_eax; | |
6666 | } | |
0573fbfc TS |
6667 | if (prefixes & PREFIX_REPZ) { |
6668 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE); | |
6669 | } | |
2c0262af FB |
6670 | break; |
6671 | case 0x9b: /* fwait */ | |
5fafdf24 | 6672 | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == |
7eee2a50 FB |
6673 | (HF_MP_MASK | HF_TS_MASK)) { |
6674 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
2ee73ac3 FB |
6675 | } else { |
6676 | if (s->cc_op != CC_OP_DYNAMIC) | |
6677 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6678 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6679 | gen_helper_fwait(); |
7eee2a50 | 6680 | } |
2c0262af FB |
6681 | break; |
6682 | case 0xcc: /* int3 */ | |
6683 | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); | |
6684 | break; | |
6685 | case 0xcd: /* int N */ | |
61382a50 | 6686 | val = ldub_code(s->pc++); |
f115e911 | 6687 | if (s->vm86 && s->iopl != 3) { |
5fafdf24 | 6688 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
f115e911 FB |
6689 | } else { |
6690 | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); | |
6691 | } | |
2c0262af FB |
6692 | break; |
6693 | case 0xce: /* into */ | |
14ce26e7 FB |
6694 | if (CODE64(s)) |
6695 | goto illegal_op; | |
2c0262af FB |
6696 | if (s->cc_op != CC_OP_DYNAMIC) |
6697 | gen_op_set_cc_op(s->cc_op); | |
a8ede8ba | 6698 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6699 | gen_helper_into(tcg_const_i32(s->pc - pc_start)); |
2c0262af | 6700 | break; |
0b97134b | 6701 | #ifdef WANT_ICEBP |
2c0262af | 6702 | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
872929aa | 6703 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); |
aba9d61e | 6704 | #if 1 |
2c0262af | 6705 | gen_debug(s, pc_start - s->cs_base); |
aba9d61e FB |
6706 | #else |
6707 | /* start debug */ | |
6708 | tb_flush(cpu_single_env); | |
6709 | cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); | |
6710 | #endif | |
2c0262af | 6711 | break; |
0b97134b | 6712 | #endif |
2c0262af FB |
6713 | case 0xfa: /* cli */ |
6714 | if (!s->vm86) { | |
6715 | if (s->cpl <= s->iopl) { | |
a7812ae4 | 6716 | gen_helper_cli(); |
2c0262af FB |
6717 | } else { |
6718 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6719 | } | |
6720 | } else { | |
6721 | if (s->iopl == 3) { | |
a7812ae4 | 6722 | gen_helper_cli(); |
2c0262af FB |
6723 | } else { |
6724 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6725 | } | |
6726 | } | |
6727 | break; | |
6728 | case 0xfb: /* sti */ | |
6729 | if (!s->vm86) { | |
6730 | if (s->cpl <= s->iopl) { | |
6731 | gen_sti: | |
a7812ae4 | 6732 | gen_helper_sti(); |
2c0262af | 6733 | /* interruptions are enabled only the first insn after sti */ |
a2cc3b24 FB |
6734 | /* If several instructions disable interrupts, only the |
6735 | _first_ does it */ | |
6736 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
a7812ae4 | 6737 | gen_helper_set_inhibit_irq(); |
2c0262af | 6738 | /* give a chance to handle pending irqs */ |
14ce26e7 | 6739 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6740 | gen_eob(s); |
6741 | } else { | |
6742 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6743 | } | |
6744 | } else { | |
6745 | if (s->iopl == 3) { | |
6746 | goto gen_sti; | |
6747 | } else { | |
6748 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6749 | } | |
6750 | } | |
6751 | break; | |
6752 | case 0x62: /* bound */ | |
14ce26e7 FB |
6753 | if (CODE64(s)) |
6754 | goto illegal_op; | |
2c0262af | 6755 | ot = dflag ? OT_LONG : OT_WORD; |
61382a50 | 6756 | modrm = ldub_code(s->pc++); |
2c0262af FB |
6757 | reg = (modrm >> 3) & 7; |
6758 | mod = (modrm >> 6) & 3; | |
6759 | if (mod == 3) | |
6760 | goto illegal_op; | |
57fec1fe | 6761 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af | 6762 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 6763 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6764 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2c0262af | 6765 | if (ot == OT_WORD) |
a7812ae4 | 6766 | gen_helper_boundw(cpu_A0, cpu_tmp2_i32); |
2c0262af | 6767 | else |
a7812ae4 | 6768 | gen_helper_boundl(cpu_A0, cpu_tmp2_i32); |
2c0262af FB |
6769 | break; |
6770 | case 0x1c8 ... 0x1cf: /* bswap reg */ | |
14ce26e7 FB |
6771 | reg = (b & 7) | REX_B(s); |
6772 | #ifdef TARGET_X86_64 | |
6773 | if (dflag == 2) { | |
57fec1fe | 6774 | gen_op_mov_TN_reg(OT_QUAD, 0, reg); |
66896cb8 | 6775 | tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); |
57fec1fe | 6776 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 6777 | } else |
8777643e | 6778 | #endif |
57fec1fe FB |
6779 | { |
6780 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
8777643e AJ |
6781 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
6782 | tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); | |
57fec1fe | 6783 | gen_op_mov_reg_T0(OT_LONG, reg); |
14ce26e7 | 6784 | } |
2c0262af FB |
6785 | break; |
6786 | case 0xd6: /* salc */ | |
14ce26e7 FB |
6787 | if (CODE64(s)) |
6788 | goto illegal_op; | |
2c0262af FB |
6789 | if (s->cc_op != CC_OP_DYNAMIC) |
6790 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6791 | gen_compute_eflags_c(cpu_T[0]); |
6792 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); | |
6793 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
6794 | break; |
6795 | case 0xe0: /* loopnz */ | |
6796 | case 0xe1: /* loopz */ | |
2c0262af FB |
6797 | case 0xe2: /* loop */ |
6798 | case 0xe3: /* jecxz */ | |
14ce26e7 | 6799 | { |
6e0d8677 | 6800 | int l1, l2, l3; |
14ce26e7 FB |
6801 | |
6802 | tval = (int8_t)insn_get(s, OT_BYTE); | |
6803 | next_eip = s->pc - s->cs_base; | |
6804 | tval += next_eip; | |
6805 | if (s->dflag == 0) | |
6806 | tval &= 0xffff; | |
3b46e624 | 6807 | |
14ce26e7 FB |
6808 | l1 = gen_new_label(); |
6809 | l2 = gen_new_label(); | |
6e0d8677 | 6810 | l3 = gen_new_label(); |
14ce26e7 | 6811 | b &= 3; |
6e0d8677 FB |
6812 | switch(b) { |
6813 | case 0: /* loopnz */ | |
6814 | case 1: /* loopz */ | |
6815 | if (s->cc_op != CC_OP_DYNAMIC) | |
6816 | gen_op_set_cc_op(s->cc_op); | |
6817 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
6818 | gen_op_jz_ecx(s->aflag, l3); | |
6819 | gen_compute_eflags(cpu_tmp0); | |
6820 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z); | |
6821 | if (b == 0) { | |
cb63669a | 6822 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
6e0d8677 | 6823 | } else { |
cb63669a | 6824 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1); |
6e0d8677 FB |
6825 | } |
6826 | break; | |
6827 | case 2: /* loop */ | |
6828 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
6829 | gen_op_jnz_ecx(s->aflag, l1); | |
6830 | break; | |
6831 | default: | |
6832 | case 3: /* jcxz */ | |
6833 | gen_op_jz_ecx(s->aflag, l1); | |
6834 | break; | |
14ce26e7 FB |
6835 | } |
6836 | ||
6e0d8677 | 6837 | gen_set_label(l3); |
14ce26e7 | 6838 | gen_jmp_im(next_eip); |
8e1c85e3 | 6839 | tcg_gen_br(l2); |
6e0d8677 | 6840 | |
14ce26e7 FB |
6841 | gen_set_label(l1); |
6842 | gen_jmp_im(tval); | |
6843 | gen_set_label(l2); | |
6844 | gen_eob(s); | |
6845 | } | |
2c0262af FB |
6846 | break; |
6847 | case 0x130: /* wrmsr */ | |
6848 | case 0x132: /* rdmsr */ | |
6849 | if (s->cpl != 0) { | |
6850 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6851 | } else { | |
872929aa FB |
6852 | if (s->cc_op != CC_OP_DYNAMIC) |
6853 | gen_op_set_cc_op(s->cc_op); | |
6854 | gen_jmp_im(pc_start - s->cs_base); | |
0573fbfc | 6855 | if (b & 2) { |
a7812ae4 | 6856 | gen_helper_rdmsr(); |
0573fbfc | 6857 | } else { |
a7812ae4 | 6858 | gen_helper_wrmsr(); |
0573fbfc | 6859 | } |
2c0262af FB |
6860 | } |
6861 | break; | |
6862 | case 0x131: /* rdtsc */ | |
872929aa FB |
6863 | if (s->cc_op != CC_OP_DYNAMIC) |
6864 | gen_op_set_cc_op(s->cc_op); | |
ecada8a2 | 6865 | gen_jmp_im(pc_start - s->cs_base); |
efade670 PB |
6866 | if (use_icount) |
6867 | gen_io_start(); | |
a7812ae4 | 6868 | gen_helper_rdtsc(); |
efade670 PB |
6869 | if (use_icount) { |
6870 | gen_io_end(); | |
6871 | gen_jmp(s, s->pc - s->cs_base); | |
6872 | } | |
2c0262af | 6873 | break; |
df01e0fc | 6874 | case 0x133: /* rdpmc */ |
872929aa FB |
6875 | if (s->cc_op != CC_OP_DYNAMIC) |
6876 | gen_op_set_cc_op(s->cc_op); | |
df01e0fc | 6877 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6878 | gen_helper_rdpmc(); |
df01e0fc | 6879 | break; |
023fe10d | 6880 | case 0x134: /* sysenter */ |
2436b61a AZ |
6881 | /* For Intel SYSENTER is valid on 64-bit */ |
6882 | if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) | |
14ce26e7 | 6883 | goto illegal_op; |
023fe10d FB |
6884 | if (!s->pe) { |
6885 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6886 | } else { | |
728d803b | 6887 | gen_update_cc_op(s); |
14ce26e7 | 6888 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6889 | gen_helper_sysenter(); |
023fe10d FB |
6890 | gen_eob(s); |
6891 | } | |
6892 | break; | |
6893 | case 0x135: /* sysexit */ | |
2436b61a AZ |
6894 | /* For Intel SYSEXIT is valid on 64-bit */ |
6895 | if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) | |
14ce26e7 | 6896 | goto illegal_op; |
023fe10d FB |
6897 | if (!s->pe) { |
6898 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6899 | } else { | |
728d803b | 6900 | gen_update_cc_op(s); |
14ce26e7 | 6901 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6902 | gen_helper_sysexit(tcg_const_i32(dflag)); |
023fe10d FB |
6903 | gen_eob(s); |
6904 | } | |
6905 | break; | |
14ce26e7 FB |
6906 | #ifdef TARGET_X86_64 |
6907 | case 0x105: /* syscall */ | |
6908 | /* XXX: is it usable in real mode ? */ | |
728d803b | 6909 | gen_update_cc_op(s); |
14ce26e7 | 6910 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6911 | gen_helper_syscall(tcg_const_i32(s->pc - pc_start)); |
14ce26e7 FB |
6912 | gen_eob(s); |
6913 | break; | |
6914 | case 0x107: /* sysret */ | |
6915 | if (!s->pe) { | |
6916 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6917 | } else { | |
728d803b | 6918 | gen_update_cc_op(s); |
14ce26e7 | 6919 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6920 | gen_helper_sysret(tcg_const_i32(s->dflag)); |
aba9d61e FB |
6921 | /* condition codes are modified only in long mode */ |
6922 | if (s->lma) | |
6923 | s->cc_op = CC_OP_EFLAGS; | |
14ce26e7 FB |
6924 | gen_eob(s); |
6925 | } | |
6926 | break; | |
6927 | #endif | |
2c0262af | 6928 | case 0x1a2: /* cpuid */ |
9575cb94 FB |
6929 | if (s->cc_op != CC_OP_DYNAMIC) |
6930 | gen_op_set_cc_op(s->cc_op); | |
6931 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 6932 | gen_helper_cpuid(); |
2c0262af FB |
6933 | break; |
6934 | case 0xf4: /* hlt */ | |
6935 | if (s->cpl != 0) { | |
6936 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6937 | } else { | |
6938 | if (s->cc_op != CC_OP_DYNAMIC) | |
6939 | gen_op_set_cc_op(s->cc_op); | |
94451178 | 6940 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 6941 | gen_helper_hlt(tcg_const_i32(s->pc - pc_start)); |
5779406a | 6942 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
6943 | } |
6944 | break; | |
6945 | case 0x100: | |
61382a50 | 6946 | modrm = ldub_code(s->pc++); |
2c0262af FB |
6947 | mod = (modrm >> 6) & 3; |
6948 | op = (modrm >> 3) & 7; | |
6949 | switch(op) { | |
6950 | case 0: /* sldt */ | |
f115e911 FB |
6951 | if (!s->pe || s->vm86) |
6952 | goto illegal_op; | |
872929aa | 6953 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); |
651ba608 | 6954 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); |
2c0262af FB |
6955 | ot = OT_WORD; |
6956 | if (mod == 3) | |
6957 | ot += s->dflag; | |
6958 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); | |
6959 | break; | |
6960 | case 2: /* lldt */ | |
f115e911 FB |
6961 | if (!s->pe || s->vm86) |
6962 | goto illegal_op; | |
2c0262af FB |
6963 | if (s->cpl != 0) { |
6964 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6965 | } else { | |
872929aa | 6966 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); |
2c0262af | 6967 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 6968 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6969 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6970 | gen_helper_lldt(cpu_tmp2_i32); |
2c0262af FB |
6971 | } |
6972 | break; | |
6973 | case 1: /* str */ | |
f115e911 FB |
6974 | if (!s->pe || s->vm86) |
6975 | goto illegal_op; | |
872929aa | 6976 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); |
651ba608 | 6977 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); |
2c0262af FB |
6978 | ot = OT_WORD; |
6979 | if (mod == 3) | |
6980 | ot += s->dflag; | |
6981 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); | |
6982 | break; | |
6983 | case 3: /* ltr */ | |
f115e911 FB |
6984 | if (!s->pe || s->vm86) |
6985 | goto illegal_op; | |
2c0262af FB |
6986 | if (s->cpl != 0) { |
6987 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6988 | } else { | |
872929aa | 6989 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); |
2c0262af | 6990 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 6991 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6992 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6993 | gen_helper_ltr(cpu_tmp2_i32); |
2c0262af FB |
6994 | } |
6995 | break; | |
6996 | case 4: /* verr */ | |
6997 | case 5: /* verw */ | |
f115e911 FB |
6998 | if (!s->pe || s->vm86) |
6999 | goto illegal_op; | |
7000 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); | |
7001 | if (s->cc_op != CC_OP_DYNAMIC) | |
7002 | gen_op_set_cc_op(s->cc_op); | |
7003 | if (op == 4) | |
a7812ae4 | 7004 | gen_helper_verr(cpu_T[0]); |
f115e911 | 7005 | else |
a7812ae4 | 7006 | gen_helper_verw(cpu_T[0]); |
f115e911 FB |
7007 | s->cc_op = CC_OP_EFLAGS; |
7008 | break; | |
2c0262af FB |
7009 | default: |
7010 | goto illegal_op; | |
7011 | } | |
7012 | break; | |
7013 | case 0x101: | |
61382a50 | 7014 | modrm = ldub_code(s->pc++); |
2c0262af FB |
7015 | mod = (modrm >> 6) & 3; |
7016 | op = (modrm >> 3) & 7; | |
3d7374c5 | 7017 | rm = modrm & 7; |
2c0262af FB |
7018 | switch(op) { |
7019 | case 0: /* sgdt */ | |
2c0262af FB |
7020 | if (mod == 3) |
7021 | goto illegal_op; | |
872929aa | 7022 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); |
2c0262af | 7023 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
651ba608 | 7024 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); |
57fec1fe | 7025 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
aba9d61e | 7026 | gen_add_A0_im(s, 2); |
651ba608 | 7027 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); |
2c0262af FB |
7028 | if (!s->dflag) |
7029 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7030 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af | 7031 | break; |
3d7374c5 FB |
7032 | case 1: |
7033 | if (mod == 3) { | |
7034 | switch (rm) { | |
7035 | case 0: /* monitor */ | |
7036 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7037 | s->cpl != 0) | |
7038 | goto illegal_op; | |
94451178 FB |
7039 | if (s->cc_op != CC_OP_DYNAMIC) |
7040 | gen_op_set_cc_op(s->cc_op); | |
3d7374c5 FB |
7041 | gen_jmp_im(pc_start - s->cs_base); |
7042 | #ifdef TARGET_X86_64 | |
7043 | if (s->aflag == 2) { | |
bbf662ee | 7044 | gen_op_movq_A0_reg(R_EAX); |
5fafdf24 | 7045 | } else |
3d7374c5 FB |
7046 | #endif |
7047 | { | |
bbf662ee | 7048 | gen_op_movl_A0_reg(R_EAX); |
3d7374c5 FB |
7049 | if (s->aflag == 0) |
7050 | gen_op_andl_A0_ffff(); | |
7051 | } | |
7052 | gen_add_A0_ds_seg(s); | |
a7812ae4 | 7053 | gen_helper_monitor(cpu_A0); |
3d7374c5 FB |
7054 | break; |
7055 | case 1: /* mwait */ | |
7056 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7057 | s->cpl != 0) | |
7058 | goto illegal_op; | |
728d803b | 7059 | gen_update_cc_op(s); |
94451178 | 7060 | gen_jmp_im(pc_start - s->cs_base); |
a7812ae4 | 7061 | gen_helper_mwait(tcg_const_i32(s->pc - pc_start)); |
3d7374c5 FB |
7062 | gen_eob(s); |
7063 | break; | |
7064 | default: | |
7065 | goto illegal_op; | |
7066 | } | |
7067 | } else { /* sidt */ | |
872929aa | 7068 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); |
3d7374c5 | 7069 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
651ba608 | 7070 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); |
57fec1fe | 7071 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
3d7374c5 | 7072 | gen_add_A0_im(s, 2); |
651ba608 | 7073 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); |
3d7374c5 FB |
7074 | if (!s->dflag) |
7075 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7076 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
3d7374c5 FB |
7077 | } |
7078 | break; | |
2c0262af FB |
7079 | case 2: /* lgdt */ |
7080 | case 3: /* lidt */ | |
0573fbfc | 7081 | if (mod == 3) { |
872929aa FB |
7082 | if (s->cc_op != CC_OP_DYNAMIC) |
7083 | gen_op_set_cc_op(s->cc_op); | |
7084 | gen_jmp_im(pc_start - s->cs_base); | |
0573fbfc TS |
7085 | switch(rm) { |
7086 | case 0: /* VMRUN */ | |
872929aa FB |
7087 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7088 | goto illegal_op; | |
7089 | if (s->cpl != 0) { | |
7090 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
0573fbfc | 7091 | break; |
872929aa | 7092 | } else { |
a7812ae4 PB |
7093 | gen_helper_vmrun(tcg_const_i32(s->aflag), |
7094 | tcg_const_i32(s->pc - pc_start)); | |
db620f46 | 7095 | tcg_gen_exit_tb(0); |
5779406a | 7096 | s->is_jmp = DISAS_TB_JUMP; |
872929aa | 7097 | } |
0573fbfc TS |
7098 | break; |
7099 | case 1: /* VMMCALL */ | |
872929aa FB |
7100 | if (!(s->flags & HF_SVME_MASK)) |
7101 | goto illegal_op; | |
a7812ae4 | 7102 | gen_helper_vmmcall(); |
0573fbfc TS |
7103 | break; |
7104 | case 2: /* VMLOAD */ | |
872929aa FB |
7105 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7106 | goto illegal_op; | |
7107 | if (s->cpl != 0) { | |
7108 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7109 | break; | |
7110 | } else { | |
a7812ae4 | 7111 | gen_helper_vmload(tcg_const_i32(s->aflag)); |
872929aa | 7112 | } |
0573fbfc TS |
7113 | break; |
7114 | case 3: /* VMSAVE */ | |
872929aa FB |
7115 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7116 | goto illegal_op; | |
7117 | if (s->cpl != 0) { | |
7118 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7119 | break; | |
7120 | } else { | |
a7812ae4 | 7121 | gen_helper_vmsave(tcg_const_i32(s->aflag)); |
872929aa | 7122 | } |
0573fbfc TS |
7123 | break; |
7124 | case 4: /* STGI */ | |
872929aa FB |
7125 | if ((!(s->flags & HF_SVME_MASK) && |
7126 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7127 | !s->pe) | |
7128 | goto illegal_op; | |
7129 | if (s->cpl != 0) { | |
7130 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7131 | break; | |
7132 | } else { | |
a7812ae4 | 7133 | gen_helper_stgi(); |
872929aa | 7134 | } |
0573fbfc TS |
7135 | break; |
7136 | case 5: /* CLGI */ | |
872929aa FB |
7137 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7138 | goto illegal_op; | |
7139 | if (s->cpl != 0) { | |
7140 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7141 | break; | |
7142 | } else { | |
a7812ae4 | 7143 | gen_helper_clgi(); |
872929aa | 7144 | } |
0573fbfc TS |
7145 | break; |
7146 | case 6: /* SKINIT */ | |
872929aa FB |
7147 | if ((!(s->flags & HF_SVME_MASK) && |
7148 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7149 | !s->pe) | |
7150 | goto illegal_op; | |
a7812ae4 | 7151 | gen_helper_skinit(); |
0573fbfc TS |
7152 | break; |
7153 | case 7: /* INVLPGA */ | |
872929aa FB |
7154 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7155 | goto illegal_op; | |
7156 | if (s->cpl != 0) { | |
7157 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7158 | break; | |
7159 | } else { | |
a7812ae4 | 7160 | gen_helper_invlpga(tcg_const_i32(s->aflag)); |
872929aa | 7161 | } |
0573fbfc TS |
7162 | break; |
7163 | default: | |
7164 | goto illegal_op; | |
7165 | } | |
7166 | } else if (s->cpl != 0) { | |
2c0262af FB |
7167 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7168 | } else { | |
872929aa FB |
7169 | gen_svm_check_intercept(s, pc_start, |
7170 | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); | |
2c0262af | 7171 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
57fec1fe | 7172 | gen_op_ld_T1_A0(OT_WORD + s->mem_index); |
aba9d61e | 7173 | gen_add_A0_im(s, 2); |
57fec1fe | 7174 | gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af FB |
7175 | if (!s->dflag) |
7176 | gen_op_andl_T0_im(0xffffff); | |
7177 | if (op == 2) { | |
651ba608 FB |
7178 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); |
7179 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); | |
2c0262af | 7180 | } else { |
651ba608 FB |
7181 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); |
7182 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); | |
2c0262af FB |
7183 | } |
7184 | } | |
7185 | break; | |
7186 | case 4: /* smsw */ | |
872929aa | 7187 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); |
e2542fe2 | 7188 | #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN |
f60d2728 | 7189 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); |
7190 | #else | |
651ba608 | 7191 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); |
f60d2728 | 7192 | #endif |
2c0262af FB |
7193 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1); |
7194 | break; | |
7195 | case 6: /* lmsw */ | |
7196 | if (s->cpl != 0) { | |
7197 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7198 | } else { | |
872929aa | 7199 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
2c0262af | 7200 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
a7812ae4 | 7201 | gen_helper_lmsw(cpu_T[0]); |
14ce26e7 | 7202 | gen_jmp_im(s->pc - s->cs_base); |
d71b9a8b | 7203 | gen_eob(s); |
2c0262af FB |
7204 | } |
7205 | break; | |
1b050077 AP |
7206 | case 7: |
7207 | if (mod != 3) { /* invlpg */ | |
7208 | if (s->cpl != 0) { | |
7209 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7210 | } else { | |
7211 | if (s->cc_op != CC_OP_DYNAMIC) | |
7212 | gen_op_set_cc_op(s->cc_op); | |
7213 | gen_jmp_im(pc_start - s->cs_base); | |
7214 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7215 | gen_helper_invlpg(cpu_A0); | |
7216 | gen_jmp_im(s->pc - s->cs_base); | |
7217 | gen_eob(s); | |
7218 | } | |
2c0262af | 7219 | } else { |
1b050077 AP |
7220 | switch (rm) { |
7221 | case 0: /* swapgs */ | |
14ce26e7 | 7222 | #ifdef TARGET_X86_64 |
1b050077 AP |
7223 | if (CODE64(s)) { |
7224 | if (s->cpl != 0) { | |
7225 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7226 | } else { | |
7227 | tcg_gen_ld_tl(cpu_T[0], cpu_env, | |
7228 | offsetof(CPUX86State,segs[R_GS].base)); | |
7229 | tcg_gen_ld_tl(cpu_T[1], cpu_env, | |
7230 | offsetof(CPUX86State,kernelgsbase)); | |
7231 | tcg_gen_st_tl(cpu_T[1], cpu_env, | |
7232 | offsetof(CPUX86State,segs[R_GS].base)); | |
7233 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
7234 | offsetof(CPUX86State,kernelgsbase)); | |
7235 | } | |
5fafdf24 | 7236 | } else |
14ce26e7 FB |
7237 | #endif |
7238 | { | |
7239 | goto illegal_op; | |
7240 | } | |
1b050077 AP |
7241 | break; |
7242 | case 1: /* rdtscp */ | |
7243 | if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) | |
7244 | goto illegal_op; | |
9575cb94 FB |
7245 | if (s->cc_op != CC_OP_DYNAMIC) |
7246 | gen_op_set_cc_op(s->cc_op); | |
7247 | gen_jmp_im(pc_start - s->cs_base); | |
1b050077 AP |
7248 | if (use_icount) |
7249 | gen_io_start(); | |
7250 | gen_helper_rdtscp(); | |
7251 | if (use_icount) { | |
7252 | gen_io_end(); | |
7253 | gen_jmp(s, s->pc - s->cs_base); | |
7254 | } | |
7255 | break; | |
7256 | default: | |
7257 | goto illegal_op; | |
14ce26e7 | 7258 | } |
2c0262af FB |
7259 | } |
7260 | break; | |
7261 | default: | |
7262 | goto illegal_op; | |
7263 | } | |
7264 | break; | |
3415a4dd FB |
7265 | case 0x108: /* invd */ |
7266 | case 0x109: /* wbinvd */ | |
7267 | if (s->cpl != 0) { | |
7268 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7269 | } else { | |
872929aa | 7270 | gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); |
3415a4dd FB |
7271 | /* nothing to do */ |
7272 | } | |
7273 | break; | |
14ce26e7 FB |
7274 | case 0x63: /* arpl or movslS (x86_64) */ |
7275 | #ifdef TARGET_X86_64 | |
7276 | if (CODE64(s)) { | |
7277 | int d_ot; | |
7278 | /* d_ot is the size of destination */ | |
7279 | d_ot = dflag + OT_WORD; | |
7280 | ||
7281 | modrm = ldub_code(s->pc++); | |
7282 | reg = ((modrm >> 3) & 7) | rex_r; | |
7283 | mod = (modrm >> 6) & 3; | |
7284 | rm = (modrm & 7) | REX_B(s); | |
3b46e624 | 7285 | |
14ce26e7 | 7286 | if (mod == 3) { |
57fec1fe | 7287 | gen_op_mov_TN_reg(OT_LONG, 0, rm); |
14ce26e7 FB |
7288 | /* sign extend */ |
7289 | if (d_ot == OT_QUAD) | |
e108dd01 | 7290 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
57fec1fe | 7291 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 FB |
7292 | } else { |
7293 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7294 | if (d_ot == OT_QUAD) { | |
57fec1fe | 7295 | gen_op_lds_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7296 | } else { |
57fec1fe | 7297 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7298 | } |
57fec1fe | 7299 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7300 | } |
5fafdf24 | 7301 | } else |
14ce26e7 FB |
7302 | #endif |
7303 | { | |
3bd7da9e | 7304 | int label1; |
49d9fdcc | 7305 | TCGv t0, t1, t2, a0; |
1e4840bf | 7306 | |
14ce26e7 FB |
7307 | if (!s->pe || s->vm86) |
7308 | goto illegal_op; | |
a7812ae4 PB |
7309 | t0 = tcg_temp_local_new(); |
7310 | t1 = tcg_temp_local_new(); | |
7311 | t2 = tcg_temp_local_new(); | |
3bd7da9e | 7312 | ot = OT_WORD; |
14ce26e7 FB |
7313 | modrm = ldub_code(s->pc++); |
7314 | reg = (modrm >> 3) & 7; | |
7315 | mod = (modrm >> 6) & 3; | |
7316 | rm = modrm & 7; | |
7317 | if (mod != 3) { | |
7318 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
1e4840bf | 7319 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
49d9fdcc LD |
7320 | a0 = tcg_temp_local_new(); |
7321 | tcg_gen_mov_tl(a0, cpu_A0); | |
14ce26e7 | 7322 | } else { |
1e4840bf | 7323 | gen_op_mov_v_reg(ot, t0, rm); |
49d9fdcc | 7324 | TCGV_UNUSED(a0); |
14ce26e7 | 7325 | } |
1e4840bf FB |
7326 | gen_op_mov_v_reg(ot, t1, reg); |
7327 | tcg_gen_andi_tl(cpu_tmp0, t0, 3); | |
7328 | tcg_gen_andi_tl(t1, t1, 3); | |
7329 | tcg_gen_movi_tl(t2, 0); | |
3bd7da9e | 7330 | label1 = gen_new_label(); |
1e4840bf FB |
7331 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); |
7332 | tcg_gen_andi_tl(t0, t0, ~3); | |
7333 | tcg_gen_or_tl(t0, t0, t1); | |
7334 | tcg_gen_movi_tl(t2, CC_Z); | |
3bd7da9e | 7335 | gen_set_label(label1); |
14ce26e7 | 7336 | if (mod != 3) { |
49d9fdcc LD |
7337 | gen_op_st_v(ot + s->mem_index, t0, a0); |
7338 | tcg_temp_free(a0); | |
7339 | } else { | |
1e4840bf | 7340 | gen_op_mov_reg_v(ot, rm, t0); |
14ce26e7 | 7341 | } |
3bd7da9e FB |
7342 | if (s->cc_op != CC_OP_DYNAMIC) |
7343 | gen_op_set_cc_op(s->cc_op); | |
7344 | gen_compute_eflags(cpu_cc_src); | |
7345 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); | |
1e4840bf | 7346 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); |
3bd7da9e | 7347 | s->cc_op = CC_OP_EFLAGS; |
1e4840bf FB |
7348 | tcg_temp_free(t0); |
7349 | tcg_temp_free(t1); | |
7350 | tcg_temp_free(t2); | |
f115e911 | 7351 | } |
f115e911 | 7352 | break; |
2c0262af FB |
7353 | case 0x102: /* lar */ |
7354 | case 0x103: /* lsl */ | |
cec6843e FB |
7355 | { |
7356 | int label1; | |
1e4840bf | 7357 | TCGv t0; |
cec6843e FB |
7358 | if (!s->pe || s->vm86) |
7359 | goto illegal_op; | |
7360 | ot = dflag ? OT_LONG : OT_WORD; | |
7361 | modrm = ldub_code(s->pc++); | |
7362 | reg = ((modrm >> 3) & 7) | rex_r; | |
7363 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); | |
a7812ae4 | 7364 | t0 = tcg_temp_local_new(); |
cec6843e FB |
7365 | if (s->cc_op != CC_OP_DYNAMIC) |
7366 | gen_op_set_cc_op(s->cc_op); | |
7367 | if (b == 0x102) | |
a7812ae4 | 7368 | gen_helper_lar(t0, cpu_T[0]); |
cec6843e | 7369 | else |
a7812ae4 | 7370 | gen_helper_lsl(t0, cpu_T[0]); |
cec6843e FB |
7371 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); |
7372 | label1 = gen_new_label(); | |
cb63669a | 7373 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
1e4840bf | 7374 | gen_op_mov_reg_v(ot, reg, t0); |
cec6843e FB |
7375 | gen_set_label(label1); |
7376 | s->cc_op = CC_OP_EFLAGS; | |
1e4840bf | 7377 | tcg_temp_free(t0); |
cec6843e | 7378 | } |
2c0262af FB |
7379 | break; |
7380 | case 0x118: | |
61382a50 | 7381 | modrm = ldub_code(s->pc++); |
2c0262af FB |
7382 | mod = (modrm >> 6) & 3; |
7383 | op = (modrm >> 3) & 7; | |
7384 | switch(op) { | |
7385 | case 0: /* prefetchnta */ | |
7386 | case 1: /* prefetchnt0 */ | |
7387 | case 2: /* prefetchnt0 */ | |
7388 | case 3: /* prefetchnt0 */ | |
7389 | if (mod == 3) | |
7390 | goto illegal_op; | |
7391 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7392 | /* nothing more to do */ | |
7393 | break; | |
e17a36ce FB |
7394 | default: /* nop (multi byte) */ |
7395 | gen_nop_modrm(s, modrm); | |
7396 | break; | |
2c0262af FB |
7397 | } |
7398 | break; | |
e17a36ce FB |
7399 | case 0x119 ... 0x11f: /* nop (multi byte) */ |
7400 | modrm = ldub_code(s->pc++); | |
7401 | gen_nop_modrm(s, modrm); | |
7402 | break; | |
2c0262af FB |
7403 | case 0x120: /* mov reg, crN */ |
7404 | case 0x122: /* mov crN, reg */ | |
7405 | if (s->cpl != 0) { | |
7406 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7407 | } else { | |
61382a50 | 7408 | modrm = ldub_code(s->pc++); |
2c0262af FB |
7409 | if ((modrm & 0xc0) != 0xc0) |
7410 | goto illegal_op; | |
14ce26e7 FB |
7411 | rm = (modrm & 7) | REX_B(s); |
7412 | reg = ((modrm >> 3) & 7) | rex_r; | |
7413 | if (CODE64(s)) | |
7414 | ot = OT_QUAD; | |
7415 | else | |
7416 | ot = OT_LONG; | |
ccd59d09 AP |
7417 | if ((prefixes & PREFIX_LOCK) && (reg == 0) && |
7418 | (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { | |
7419 | reg = 8; | |
7420 | } | |
2c0262af FB |
7421 | switch(reg) { |
7422 | case 0: | |
7423 | case 2: | |
7424 | case 3: | |
7425 | case 4: | |
9230e66e | 7426 | case 8: |
872929aa FB |
7427 | if (s->cc_op != CC_OP_DYNAMIC) |
7428 | gen_op_set_cc_op(s->cc_op); | |
7429 | gen_jmp_im(pc_start - s->cs_base); | |
2c0262af | 7430 | if (b & 2) { |
57fec1fe | 7431 | gen_op_mov_TN_reg(ot, 0, rm); |
a7812ae4 | 7432 | gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7433 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7434 | gen_eob(s); |
7435 | } else { | |
a7812ae4 | 7436 | gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg)); |
57fec1fe | 7437 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7438 | } |
7439 | break; | |
7440 | default: | |
7441 | goto illegal_op; | |
7442 | } | |
7443 | } | |
7444 | break; | |
7445 | case 0x121: /* mov reg, drN */ | |
7446 | case 0x123: /* mov drN, reg */ | |
7447 | if (s->cpl != 0) { | |
7448 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7449 | } else { | |
61382a50 | 7450 | modrm = ldub_code(s->pc++); |
2c0262af FB |
7451 | if ((modrm & 0xc0) != 0xc0) |
7452 | goto illegal_op; | |
14ce26e7 FB |
7453 | rm = (modrm & 7) | REX_B(s); |
7454 | reg = ((modrm >> 3) & 7) | rex_r; | |
7455 | if (CODE64(s)) | |
7456 | ot = OT_QUAD; | |
7457 | else | |
7458 | ot = OT_LONG; | |
2c0262af | 7459 | /* XXX: do it dynamically with CR4.DE bit */ |
14ce26e7 | 7460 | if (reg == 4 || reg == 5 || reg >= 8) |
2c0262af FB |
7461 | goto illegal_op; |
7462 | if (b & 2) { | |
0573fbfc | 7463 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
57fec1fe | 7464 | gen_op_mov_TN_reg(ot, 0, rm); |
a7812ae4 | 7465 | gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7466 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7467 | gen_eob(s); |
7468 | } else { | |
0573fbfc | 7469 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
651ba608 | 7470 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); |
57fec1fe | 7471 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7472 | } |
7473 | } | |
7474 | break; | |
7475 | case 0x106: /* clts */ | |
7476 | if (s->cpl != 0) { | |
7477 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7478 | } else { | |
0573fbfc | 7479 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
a7812ae4 | 7480 | gen_helper_clts(); |
7eee2a50 | 7481 | /* abort block because static cpu state changed */ |
14ce26e7 | 7482 | gen_jmp_im(s->pc - s->cs_base); |
7eee2a50 | 7483 | gen_eob(s); |
2c0262af FB |
7484 | } |
7485 | break; | |
222a3336 | 7486 | /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ |
664e0f19 FB |
7487 | case 0x1c3: /* MOVNTI reg, mem */ |
7488 | if (!(s->cpuid_features & CPUID_SSE2)) | |
14ce26e7 | 7489 | goto illegal_op; |
664e0f19 FB |
7490 | ot = s->dflag == 2 ? OT_QUAD : OT_LONG; |
7491 | modrm = ldub_code(s->pc++); | |
7492 | mod = (modrm >> 6) & 3; | |
7493 | if (mod == 3) | |
7494 | goto illegal_op; | |
7495 | reg = ((modrm >> 3) & 7) | rex_r; | |
7496 | /* generate a generic store */ | |
7497 | gen_ldst_modrm(s, modrm, ot, reg, 1); | |
14ce26e7 | 7498 | break; |
664e0f19 FB |
7499 | case 0x1ae: |
7500 | modrm = ldub_code(s->pc++); | |
7501 | mod = (modrm >> 6) & 3; | |
7502 | op = (modrm >> 3) & 7; | |
7503 | switch(op) { | |
7504 | case 0: /* fxsave */ | |
5fafdf24 | 7505 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7506 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7507 | goto illegal_op; |
09d85fb8 | 7508 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7509 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7510 | break; | |
7511 | } | |
664e0f19 | 7512 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
19e6c4b8 FB |
7513 | if (s->cc_op != CC_OP_DYNAMIC) |
7514 | gen_op_set_cc_op(s->cc_op); | |
7515 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 7516 | gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2))); |
664e0f19 FB |
7517 | break; |
7518 | case 1: /* fxrstor */ | |
5fafdf24 | 7519 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7520 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7521 | goto illegal_op; |
09d85fb8 | 7522 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7523 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7524 | break; | |
7525 | } | |
664e0f19 | 7526 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
19e6c4b8 FB |
7527 | if (s->cc_op != CC_OP_DYNAMIC) |
7528 | gen_op_set_cc_op(s->cc_op); | |
7529 | gen_jmp_im(pc_start - s->cs_base); | |
a7812ae4 | 7530 | gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2))); |
664e0f19 FB |
7531 | break; |
7532 | case 2: /* ldmxcsr */ | |
7533 | case 3: /* stmxcsr */ | |
7534 | if (s->flags & HF_TS_MASK) { | |
7535 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7536 | break; | |
14ce26e7 | 7537 | } |
664e0f19 FB |
7538 | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) || |
7539 | mod == 3) | |
14ce26e7 | 7540 | goto illegal_op; |
664e0f19 FB |
7541 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7542 | if (op == 2) { | |
57fec1fe | 7543 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 7544 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
14ce26e7 | 7545 | } else { |
651ba608 | 7546 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
57fec1fe | 7547 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7548 | } |
664e0f19 FB |
7549 | break; |
7550 | case 5: /* lfence */ | |
7551 | case 6: /* mfence */ | |
8001c294 | 7552 | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) |
664e0f19 FB |
7553 | goto illegal_op; |
7554 | break; | |
8f091a59 FB |
7555 | case 7: /* sfence / clflush */ |
7556 | if ((modrm & 0xc7) == 0xc0) { | |
7557 | /* sfence */ | |
a35f3ec7 | 7558 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */ |
8f091a59 FB |
7559 | if (!(s->cpuid_features & CPUID_SSE)) |
7560 | goto illegal_op; | |
7561 | } else { | |
7562 | /* clflush */ | |
7563 | if (!(s->cpuid_features & CPUID_CLFLUSH)) | |
7564 | goto illegal_op; | |
7565 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7566 | } | |
7567 | break; | |
664e0f19 | 7568 | default: |
14ce26e7 FB |
7569 | goto illegal_op; |
7570 | } | |
7571 | break; | |
a35f3ec7 | 7572 | case 0x10d: /* 3DNow! prefetch(w) */ |
8f091a59 | 7573 | modrm = ldub_code(s->pc++); |
a35f3ec7 AJ |
7574 | mod = (modrm >> 6) & 3; |
7575 | if (mod == 3) | |
7576 | goto illegal_op; | |
8f091a59 FB |
7577 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7578 | /* ignore for now */ | |
7579 | break; | |
3b21e03e | 7580 | case 0x1aa: /* rsm */ |
872929aa | 7581 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); |
3b21e03e FB |
7582 | if (!(s->flags & HF_SMM_MASK)) |
7583 | goto illegal_op; | |
728d803b | 7584 | gen_update_cc_op(s); |
3b21e03e | 7585 | gen_jmp_im(s->pc - s->cs_base); |
a7812ae4 | 7586 | gen_helper_rsm(); |
3b21e03e FB |
7587 | gen_eob(s); |
7588 | break; | |
222a3336 AZ |
7589 | case 0x1b8: /* SSE4.2 popcnt */ |
7590 | if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != | |
7591 | PREFIX_REPZ) | |
7592 | goto illegal_op; | |
7593 | if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) | |
7594 | goto illegal_op; | |
7595 | ||
7596 | modrm = ldub_code(s->pc++); | |
7597 | reg = ((modrm >> 3) & 7); | |
7598 | ||
7599 | if (s->prefix & PREFIX_DATA) | |
7600 | ot = OT_WORD; | |
7601 | else if (s->dflag != 2) | |
7602 | ot = OT_LONG; | |
7603 | else | |
7604 | ot = OT_QUAD; | |
7605 | ||
7606 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
a7812ae4 | 7607 | gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot)); |
222a3336 | 7608 | gen_op_mov_reg_T0(ot, reg); |
fdb0d09d AZ |
7609 | |
7610 | s->cc_op = CC_OP_EFLAGS; | |
222a3336 | 7611 | break; |
a35f3ec7 AJ |
7612 | case 0x10e ... 0x10f: |
7613 | /* 3DNow! instructions, ignore prefixes */ | |
7614 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); | |
664e0f19 FB |
7615 | case 0x110 ... 0x117: |
7616 | case 0x128 ... 0x12f: | |
4242b1bd | 7617 | case 0x138 ... 0x13a: |
d9f4bb27 | 7618 | case 0x150 ... 0x179: |
664e0f19 FB |
7619 | case 0x17c ... 0x17f: |
7620 | case 0x1c2: | |
7621 | case 0x1c4 ... 0x1c6: | |
7622 | case 0x1d0 ... 0x1fe: | |
7623 | gen_sse(s, b, pc_start, rex_r); | |
7624 | break; | |
2c0262af FB |
7625 | default: |
7626 | goto illegal_op; | |
7627 | } | |
7628 | /* lock generation */ | |
7629 | if (s->prefix & PREFIX_LOCK) | |
a7812ae4 | 7630 | gen_helper_unlock(); |
2c0262af FB |
7631 | return s->pc; |
7632 | illegal_op: | |
ab1f142b | 7633 | if (s->prefix & PREFIX_LOCK) |
a7812ae4 | 7634 | gen_helper_unlock(); |
2c0262af FB |
7635 | /* XXX: ensure that no lock was generated */ |
7636 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
7637 | return s->pc; | |
7638 | } | |
7639 | ||
2c0262af FB |
7640 | void optimize_flags_init(void) |
7641 | { | |
a7812ae4 PB |
7642 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7643 | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, | |
7644 | offsetof(CPUState, cc_op), "cc_op"); | |
7645 | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), | |
7646 | "cc_src"); | |
7647 | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), | |
7648 | "cc_dst"); | |
7649 | cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp), | |
7650 | "cc_tmp"); | |
437a88a5 | 7651 | |
cc739bb0 LD |
7652 | #ifdef TARGET_X86_64 |
7653 | cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0, | |
7654 | offsetof(CPUState, regs[R_EAX]), "rax"); | |
7655 | cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0, | |
7656 | offsetof(CPUState, regs[R_ECX]), "rcx"); | |
7657 | cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0, | |
7658 | offsetof(CPUState, regs[R_EDX]), "rdx"); | |
7659 | cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0, | |
7660 | offsetof(CPUState, regs[R_EBX]), "rbx"); | |
7661 | cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0, | |
7662 | offsetof(CPUState, regs[R_ESP]), "rsp"); | |
7663 | cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0, | |
7664 | offsetof(CPUState, regs[R_EBP]), "rbp"); | |
7665 | cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0, | |
7666 | offsetof(CPUState, regs[R_ESI]), "rsi"); | |
7667 | cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0, | |
7668 | offsetof(CPUState, regs[R_EDI]), "rdi"); | |
7669 | cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0, | |
7670 | offsetof(CPUState, regs[8]), "r8"); | |
7671 | cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0, | |
7672 | offsetof(CPUState, regs[9]), "r9"); | |
7673 | cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0, | |
7674 | offsetof(CPUState, regs[10]), "r10"); | |
7675 | cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0, | |
7676 | offsetof(CPUState, regs[11]), "r11"); | |
7677 | cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0, | |
7678 | offsetof(CPUState, regs[12]), "r12"); | |
7679 | cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0, | |
7680 | offsetof(CPUState, regs[13]), "r13"); | |
7681 | cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0, | |
7682 | offsetof(CPUState, regs[14]), "r14"); | |
7683 | cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0, | |
7684 | offsetof(CPUState, regs[15]), "r15"); | |
7685 | #else | |
7686 | cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0, | |
7687 | offsetof(CPUState, regs[R_EAX]), "eax"); | |
7688 | cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0, | |
7689 | offsetof(CPUState, regs[R_ECX]), "ecx"); | |
7690 | cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0, | |
7691 | offsetof(CPUState, regs[R_EDX]), "edx"); | |
7692 | cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0, | |
7693 | offsetof(CPUState, regs[R_EBX]), "ebx"); | |
7694 | cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0, | |
7695 | offsetof(CPUState, regs[R_ESP]), "esp"); | |
7696 | cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0, | |
7697 | offsetof(CPUState, regs[R_EBP]), "ebp"); | |
7698 | cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0, | |
7699 | offsetof(CPUState, regs[R_ESI]), "esi"); | |
7700 | cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, | |
7701 | offsetof(CPUState, regs[R_EDI]), "edi"); | |
7702 | #endif | |
7703 | ||
437a88a5 | 7704 | /* register helpers */ |
a7812ae4 | 7705 | #define GEN_HELPER 2 |
437a88a5 | 7706 | #include "helper.h" |
2c0262af FB |
7707 | } |
7708 | ||
7709 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for | |
7710 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
7711 | information for each intermediate instruction. */ | |
2cfc5f17 TS |
7712 | static inline void gen_intermediate_code_internal(CPUState *env, |
7713 | TranslationBlock *tb, | |
7714 | int search_pc) | |
2c0262af FB |
7715 | { |
7716 | DisasContext dc1, *dc = &dc1; | |
14ce26e7 | 7717 | target_ulong pc_ptr; |
2c0262af | 7718 | uint16_t *gen_opc_end; |
a1d1bb31 | 7719 | CPUBreakpoint *bp; |
7f5b7d3e | 7720 | int j, lj; |
c068688b | 7721 | uint64_t flags; |
14ce26e7 FB |
7722 | target_ulong pc_start; |
7723 | target_ulong cs_base; | |
2e70f6ef PB |
7724 | int num_insns; |
7725 | int max_insns; | |
3b46e624 | 7726 | |
2c0262af | 7727 | /* generate intermediate code */ |
14ce26e7 FB |
7728 | pc_start = tb->pc; |
7729 | cs_base = tb->cs_base; | |
2c0262af | 7730 | flags = tb->flags; |
3a1d9b8b | 7731 | |
4f31916f | 7732 | dc->pe = (flags >> HF_PE_SHIFT) & 1; |
2c0262af FB |
7733 | dc->code32 = (flags >> HF_CS32_SHIFT) & 1; |
7734 | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; | |
7735 | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; | |
7736 | dc->f_st = 0; | |
7737 | dc->vm86 = (flags >> VM_SHIFT) & 1; | |
7738 | dc->cpl = (flags >> HF_CPL_SHIFT) & 3; | |
7739 | dc->iopl = (flags >> IOPL_SHIFT) & 3; | |
7740 | dc->tf = (flags >> TF_SHIFT) & 1; | |
34865134 | 7741 | dc->singlestep_enabled = env->singlestep_enabled; |
2c0262af FB |
7742 | dc->cc_op = CC_OP_DYNAMIC; |
7743 | dc->cs_base = cs_base; | |
7744 | dc->tb = tb; | |
7745 | dc->popl_esp_hack = 0; | |
7746 | /* select memory access functions */ | |
7747 | dc->mem_index = 0; | |
7748 | if (flags & HF_SOFTMMU_MASK) { | |
7749 | if (dc->cpl == 3) | |
14ce26e7 | 7750 | dc->mem_index = 2 * 4; |
2c0262af | 7751 | else |
14ce26e7 | 7752 | dc->mem_index = 1 * 4; |
2c0262af | 7753 | } |
14ce26e7 | 7754 | dc->cpuid_features = env->cpuid_features; |
3d7374c5 | 7755 | dc->cpuid_ext_features = env->cpuid_ext_features; |
e771edab | 7756 | dc->cpuid_ext2_features = env->cpuid_ext2_features; |
12e26b75 | 7757 | dc->cpuid_ext3_features = env->cpuid_ext3_features; |
14ce26e7 FB |
7758 | #ifdef TARGET_X86_64 |
7759 | dc->lma = (flags >> HF_LMA_SHIFT) & 1; | |
7760 | dc->code64 = (flags >> HF_CS64_SHIFT) & 1; | |
7761 | #endif | |
7eee2a50 | 7762 | dc->flags = flags; |
a2cc3b24 FB |
7763 | dc->jmp_opt = !(dc->tf || env->singlestep_enabled || |
7764 | (flags & HF_INHIBIT_IRQ_MASK) | |
415fa2ea | 7765 | #ifndef CONFIG_SOFTMMU |
2c0262af FB |
7766 | || (flags & HF_SOFTMMU_MASK) |
7767 | #endif | |
7768 | ); | |
4f31916f FB |
7769 | #if 0 |
7770 | /* check addseg logic */ | |
dc196a57 | 7771 | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) |
4f31916f FB |
7772 | printf("ERROR addseg\n"); |
7773 | #endif | |
7774 | ||
a7812ae4 PB |
7775 | cpu_T[0] = tcg_temp_new(); |
7776 | cpu_T[1] = tcg_temp_new(); | |
7777 | cpu_A0 = tcg_temp_new(); | |
7778 | cpu_T3 = tcg_temp_new(); | |
7779 | ||
7780 | cpu_tmp0 = tcg_temp_new(); | |
7781 | cpu_tmp1_i64 = tcg_temp_new_i64(); | |
7782 | cpu_tmp2_i32 = tcg_temp_new_i32(); | |
7783 | cpu_tmp3_i32 = tcg_temp_new_i32(); | |
7784 | cpu_tmp4 = tcg_temp_new(); | |
7785 | cpu_tmp5 = tcg_temp_new(); | |
a7812ae4 PB |
7786 | cpu_ptr0 = tcg_temp_new_ptr(); |
7787 | cpu_ptr1 = tcg_temp_new_ptr(); | |
57fec1fe | 7788 | |
2c0262af | 7789 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
7790 | |
7791 | dc->is_jmp = DISAS_NEXT; | |
7792 | pc_ptr = pc_start; | |
7793 | lj = -1; | |
2e70f6ef PB |
7794 | num_insns = 0; |
7795 | max_insns = tb->cflags & CF_COUNT_MASK; | |
7796 | if (max_insns == 0) | |
7797 | max_insns = CF_COUNT_MASK; | |
2c0262af | 7798 | |
2e70f6ef | 7799 | gen_icount_start(); |
2c0262af | 7800 | for(;;) { |
72cf2d4f BS |
7801 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
7802 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a2397807 JK |
7803 | if (bp->pc == pc_ptr && |
7804 | !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { | |
2c0262af FB |
7805 | gen_debug(dc, pc_ptr - dc->cs_base); |
7806 | break; | |
7807 | } | |
7808 | } | |
7809 | } | |
7810 | if (search_pc) { | |
7811 | j = gen_opc_ptr - gen_opc_buf; | |
7812 | if (lj < j) { | |
7813 | lj++; | |
7814 | while (lj < j) | |
7815 | gen_opc_instr_start[lj++] = 0; | |
7816 | } | |
14ce26e7 | 7817 | gen_opc_pc[lj] = pc_ptr; |
2c0262af FB |
7818 | gen_opc_cc_op[lj] = dc->cc_op; |
7819 | gen_opc_instr_start[lj] = 1; | |
2e70f6ef | 7820 | gen_opc_icount[lj] = num_insns; |
2c0262af | 7821 | } |
2e70f6ef PB |
7822 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
7823 | gen_io_start(); | |
7824 | ||
2c0262af | 7825 | pc_ptr = disas_insn(dc, pc_ptr); |
2e70f6ef | 7826 | num_insns++; |
2c0262af FB |
7827 | /* stop translation if indicated */ |
7828 | if (dc->is_jmp) | |
7829 | break; | |
7830 | /* if single step mode, we generate only one instruction and | |
7831 | generate an exception */ | |
a2cc3b24 FB |
7832 | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear |
7833 | the flag and abort the translation to give the irqs a | |
7834 | change to be happen */ | |
5fafdf24 | 7835 | if (dc->tf || dc->singlestep_enabled || |
2e70f6ef | 7836 | (flags & HF_INHIBIT_IRQ_MASK)) { |
14ce26e7 | 7837 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7838 | gen_eob(dc); |
7839 | break; | |
7840 | } | |
7841 | /* if too long translation, stop generation too */ | |
7842 | if (gen_opc_ptr >= gen_opc_end || | |
2e70f6ef PB |
7843 | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || |
7844 | num_insns >= max_insns) { | |
14ce26e7 | 7845 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7846 | gen_eob(dc); |
7847 | break; | |
7848 | } | |
1b530a6d AJ |
7849 | if (singlestep) { |
7850 | gen_jmp_im(pc_ptr - dc->cs_base); | |
7851 | gen_eob(dc); | |
7852 | break; | |
7853 | } | |
2c0262af | 7854 | } |
2e70f6ef PB |
7855 | if (tb->cflags & CF_LAST_IO) |
7856 | gen_io_end(); | |
7857 | gen_icount_end(tb, num_insns); | |
2c0262af FB |
7858 | *gen_opc_ptr = INDEX_op_end; |
7859 | /* we don't forget to fill the last values */ | |
7860 | if (search_pc) { | |
7861 | j = gen_opc_ptr - gen_opc_buf; | |
7862 | lj++; | |
7863 | while (lj <= j) | |
7864 | gen_opc_instr_start[lj++] = 0; | |
7865 | } | |
3b46e624 | 7866 | |
2c0262af | 7867 | #ifdef DEBUG_DISAS |
8fec2b8c | 7868 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
14ce26e7 | 7869 | int disas_flags; |
93fcfe39 AL |
7870 | qemu_log("----------------\n"); |
7871 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
14ce26e7 FB |
7872 | #ifdef TARGET_X86_64 |
7873 | if (dc->code64) | |
7874 | disas_flags = 2; | |
7875 | else | |
7876 | #endif | |
7877 | disas_flags = !dc->code32; | |
93fcfe39 AL |
7878 | log_target_disas(pc_start, pc_ptr - pc_start, disas_flags); |
7879 | qemu_log("\n"); | |
2c0262af FB |
7880 | } |
7881 | #endif | |
7882 | ||
2e70f6ef | 7883 | if (!search_pc) { |
2c0262af | 7884 | tb->size = pc_ptr - pc_start; |
2e70f6ef PB |
7885 | tb->icount = num_insns; |
7886 | } | |
2c0262af FB |
7887 | } |
7888 | ||
2cfc5f17 | 7889 | void gen_intermediate_code(CPUState *env, TranslationBlock *tb) |
2c0262af | 7890 | { |
2cfc5f17 | 7891 | gen_intermediate_code_internal(env, tb, 0); |
2c0262af FB |
7892 | } |
7893 | ||
2cfc5f17 | 7894 | void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) |
2c0262af | 7895 | { |
2cfc5f17 | 7896 | gen_intermediate_code_internal(env, tb, 1); |
2c0262af FB |
7897 | } |
7898 | ||
e87b7cb0 | 7899 | void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a AJ |
7900 | { |
7901 | int cc_op; | |
7902 | #ifdef DEBUG_DISAS | |
8fec2b8c | 7903 | if (qemu_loglevel_mask(CPU_LOG_TB_OP)) { |
d2856f1a | 7904 | int i; |
93fcfe39 | 7905 | qemu_log("RESTORE:\n"); |
d2856f1a AJ |
7906 | for(i = 0;i <= pc_pos; i++) { |
7907 | if (gen_opc_instr_start[i]) { | |
93fcfe39 | 7908 | qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]); |
d2856f1a AJ |
7909 | } |
7910 | } | |
e87b7cb0 SW |
7911 | qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
7912 | pc_pos, gen_opc_pc[pc_pos] - tb->cs_base, | |
d2856f1a AJ |
7913 | (uint32_t)tb->cs_base); |
7914 | } | |
7915 | #endif | |
7916 | env->eip = gen_opc_pc[pc_pos] - tb->cs_base; | |
7917 | cc_op = gen_opc_cc_op[pc_pos]; | |
7918 | if (cc_op != CC_OP_DYNAMIC) | |
7919 | env->cc_op = cc_op; | |
7920 | } |