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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 translation | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
2c0262af FB |
25 | |
26 | #include "cpu.h" | |
76cad711 | 27 | #include "disas/disas.h" |
57fec1fe | 28 | #include "tcg-op.h" |
2c0262af | 29 | |
a7812ae4 PB |
30 | #include "helper.h" |
31 | #define GEN_HELPER 1 | |
32 | #include "helper.h" | |
33 | ||
2c0262af FB |
34 | #define PREFIX_REPZ 0x01 |
35 | #define PREFIX_REPNZ 0x02 | |
36 | #define PREFIX_LOCK 0x04 | |
37 | #define PREFIX_DATA 0x08 | |
38 | #define PREFIX_ADR 0x10 | |
39 | ||
14ce26e7 | 40 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
41 | #define CODE64(s) ((s)->code64) |
42 | #define REX_X(s) ((s)->rex_x) | |
43 | #define REX_B(s) ((s)->rex_b) | |
14ce26e7 | 44 | #else |
14ce26e7 FB |
45 | #define CODE64(s) 0 |
46 | #define REX_X(s) 0 | |
47 | #define REX_B(s) 0 | |
48 | #endif | |
49 | ||
57fec1fe FB |
50 | //#define MACRO_TEST 1 |
51 | ||
57fec1fe | 52 | /* global register indexes */ |
a7812ae4 | 53 | static TCGv_ptr cpu_env; |
f5847c91 | 54 | static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst; |
a7812ae4 | 55 | static TCGv_i32 cpu_cc_op; |
cc739bb0 | 56 | static TCGv cpu_regs[CPU_NB_REGS]; |
1e4840bf FB |
57 | /* local temps */ |
58 | static TCGv cpu_T[2], cpu_T3; | |
57fec1fe | 59 | /* local register indexes (only used inside old micro ops) */ |
a7812ae4 PB |
60 | static TCGv cpu_tmp0, cpu_tmp4; |
61 | static TCGv_ptr cpu_ptr0, cpu_ptr1; | |
62 | static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; | |
63 | static TCGv_i64 cpu_tmp1_i64; | |
bedda79c | 64 | static TCGv cpu_tmp5; |
57fec1fe | 65 | |
1a7ff922 PB |
66 | static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
67 | ||
022c62cb | 68 | #include "exec/gen-icount.h" |
2e70f6ef | 69 | |
57fec1fe FB |
70 | #ifdef TARGET_X86_64 |
71 | static int x86_64_hregs; | |
ae063a68 FB |
72 | #endif |
73 | ||
2c0262af FB |
74 | typedef struct DisasContext { |
75 | /* current insn context */ | |
76 | int override; /* -1 if no override */ | |
77 | int prefix; | |
78 | int aflag, dflag; | |
14ce26e7 | 79 | target_ulong pc; /* pc = eip + cs_base */ |
2c0262af FB |
80 | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
81 | static state change (stop translation) */ | |
82 | /* current block context */ | |
14ce26e7 | 83 | target_ulong cs_base; /* base of CS segment */ |
2c0262af FB |
84 | int pe; /* protected mode */ |
85 | int code32; /* 32 bit code segment */ | |
14ce26e7 FB |
86 | #ifdef TARGET_X86_64 |
87 | int lma; /* long mode active */ | |
88 | int code64; /* 64 bit code segment */ | |
89 | int rex_x, rex_b; | |
90 | #endif | |
2c0262af | 91 | int ss32; /* 32 bit stack segment */ |
fee71888 | 92 | CCOp cc_op; /* current CC operation */ |
2c0262af FB |
93 | int addseg; /* non zero if either DS/ES/SS have a non zero base */ |
94 | int f_st; /* currently unused */ | |
95 | int vm86; /* vm86 mode */ | |
96 | int cpl; | |
97 | int iopl; | |
98 | int tf; /* TF cpu flag */ | |
34865134 | 99 | int singlestep_enabled; /* "hardware" single step enabled */ |
2c0262af FB |
100 | int jmp_opt; /* use direct block chaining for direct jumps */ |
101 | int mem_index; /* select memory access functions */ | |
c068688b | 102 | uint64_t flags; /* all execution flags */ |
2c0262af FB |
103 | struct TranslationBlock *tb; |
104 | int popl_esp_hack; /* for correct popl with esp base handling */ | |
14ce26e7 FB |
105 | int rip_offset; /* only used in x86_64, but left for simplicity */ |
106 | int cpuid_features; | |
3d7374c5 | 107 | int cpuid_ext_features; |
e771edab | 108 | int cpuid_ext2_features; |
12e26b75 | 109 | int cpuid_ext3_features; |
a9321a4d | 110 | int cpuid_7_0_ebx_features; |
2c0262af FB |
111 | } DisasContext; |
112 | ||
113 | static void gen_eob(DisasContext *s); | |
14ce26e7 FB |
114 | static void gen_jmp(DisasContext *s, target_ulong eip); |
115 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); | |
2c0262af FB |
116 | |
117 | /* i386 arith/logic operations */ | |
118 | enum { | |
5fafdf24 TS |
119 | OP_ADDL, |
120 | OP_ORL, | |
121 | OP_ADCL, | |
2c0262af | 122 | OP_SBBL, |
5fafdf24 TS |
123 | OP_ANDL, |
124 | OP_SUBL, | |
125 | OP_XORL, | |
2c0262af FB |
126 | OP_CMPL, |
127 | }; | |
128 | ||
129 | /* i386 shift ops */ | |
130 | enum { | |
5fafdf24 TS |
131 | OP_ROL, |
132 | OP_ROR, | |
133 | OP_RCL, | |
134 | OP_RCR, | |
135 | OP_SHL, | |
136 | OP_SHR, | |
2c0262af FB |
137 | OP_SHL1, /* undocumented */ |
138 | OP_SAR = 7, | |
139 | }; | |
140 | ||
8e1c85e3 FB |
141 | enum { |
142 | JCC_O, | |
143 | JCC_B, | |
144 | JCC_Z, | |
145 | JCC_BE, | |
146 | JCC_S, | |
147 | JCC_P, | |
148 | JCC_L, | |
149 | JCC_LE, | |
150 | }; | |
151 | ||
2c0262af FB |
152 | /* operand size */ |
153 | enum { | |
154 | OT_BYTE = 0, | |
155 | OT_WORD, | |
5fafdf24 | 156 | OT_LONG, |
2c0262af FB |
157 | OT_QUAD, |
158 | }; | |
159 | ||
160 | enum { | |
161 | /* I386 int registers */ | |
162 | OR_EAX, /* MUST be even numbered */ | |
163 | OR_ECX, | |
164 | OR_EDX, | |
165 | OR_EBX, | |
166 | OR_ESP, | |
167 | OR_EBP, | |
168 | OR_ESI, | |
169 | OR_EDI, | |
14ce26e7 FB |
170 | |
171 | OR_TMP0 = 16, /* temporary operand register */ | |
2c0262af FB |
172 | OR_TMP1, |
173 | OR_A0, /* temporary register used when doing address evaluation */ | |
2c0262af FB |
174 | }; |
175 | ||
3ca51d07 RH |
176 | static inline void set_cc_op(DisasContext *s, CCOp op) |
177 | { | |
178 | s->cc_op = op; | |
179 | } | |
180 | ||
57fec1fe FB |
181 | static inline void gen_op_movl_T0_0(void) |
182 | { | |
183 | tcg_gen_movi_tl(cpu_T[0], 0); | |
184 | } | |
185 | ||
186 | static inline void gen_op_movl_T0_im(int32_t val) | |
187 | { | |
188 | tcg_gen_movi_tl(cpu_T[0], val); | |
189 | } | |
190 | ||
191 | static inline void gen_op_movl_T0_imu(uint32_t val) | |
192 | { | |
193 | tcg_gen_movi_tl(cpu_T[0], val); | |
194 | } | |
195 | ||
196 | static inline void gen_op_movl_T1_im(int32_t val) | |
197 | { | |
198 | tcg_gen_movi_tl(cpu_T[1], val); | |
199 | } | |
200 | ||
201 | static inline void gen_op_movl_T1_imu(uint32_t val) | |
202 | { | |
203 | tcg_gen_movi_tl(cpu_T[1], val); | |
204 | } | |
205 | ||
206 | static inline void gen_op_movl_A0_im(uint32_t val) | |
207 | { | |
208 | tcg_gen_movi_tl(cpu_A0, val); | |
209 | } | |
210 | ||
211 | #ifdef TARGET_X86_64 | |
212 | static inline void gen_op_movq_A0_im(int64_t val) | |
213 | { | |
214 | tcg_gen_movi_tl(cpu_A0, val); | |
215 | } | |
216 | #endif | |
217 | ||
218 | static inline void gen_movtl_T0_im(target_ulong val) | |
219 | { | |
220 | tcg_gen_movi_tl(cpu_T[0], val); | |
221 | } | |
222 | ||
223 | static inline void gen_movtl_T1_im(target_ulong val) | |
224 | { | |
225 | tcg_gen_movi_tl(cpu_T[1], val); | |
226 | } | |
227 | ||
228 | static inline void gen_op_andl_T0_ffff(void) | |
229 | { | |
230 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
231 | } | |
232 | ||
233 | static inline void gen_op_andl_T0_im(uint32_t val) | |
234 | { | |
235 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); | |
236 | } | |
237 | ||
238 | static inline void gen_op_movl_T0_T1(void) | |
239 | { | |
240 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); | |
241 | } | |
242 | ||
243 | static inline void gen_op_andl_A0_ffff(void) | |
244 | { | |
245 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff); | |
246 | } | |
247 | ||
14ce26e7 FB |
248 | #ifdef TARGET_X86_64 |
249 | ||
250 | #define NB_OP_SIZES 4 | |
251 | ||
14ce26e7 FB |
252 | #else /* !TARGET_X86_64 */ |
253 | ||
254 | #define NB_OP_SIZES 3 | |
255 | ||
14ce26e7 FB |
256 | #endif /* !TARGET_X86_64 */ |
257 | ||
e2542fe2 | 258 | #if defined(HOST_WORDS_BIGENDIAN) |
57fec1fe FB |
259 | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
260 | #define REG_H_OFFSET (sizeof(target_ulong) - 2) | |
261 | #define REG_W_OFFSET (sizeof(target_ulong) - 2) | |
262 | #define REG_L_OFFSET (sizeof(target_ulong) - 4) | |
263 | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) | |
14ce26e7 | 264 | #else |
57fec1fe FB |
265 | #define REG_B_OFFSET 0 |
266 | #define REG_H_OFFSET 1 | |
267 | #define REG_W_OFFSET 0 | |
268 | #define REG_L_OFFSET 0 | |
269 | #define REG_LH_OFFSET 4 | |
14ce26e7 | 270 | #endif |
57fec1fe | 271 | |
96d7073f PM |
272 | /* In instruction encodings for byte register accesses the |
273 | * register number usually indicates "low 8 bits of register N"; | |
274 | * however there are some special cases where N 4..7 indicates | |
275 | * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return | |
276 | * true for this special case, false otherwise. | |
277 | */ | |
278 | static inline bool byte_reg_is_xH(int reg) | |
279 | { | |
280 | if (reg < 4) { | |
281 | return false; | |
282 | } | |
283 | #ifdef TARGET_X86_64 | |
284 | if (reg >= 8 || x86_64_hregs) { | |
285 | return false; | |
286 | } | |
287 | #endif | |
288 | return true; | |
289 | } | |
290 | ||
1e4840bf | 291 | static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) |
57fec1fe FB |
292 | { |
293 | switch(ot) { | |
294 | case OT_BYTE: | |
96d7073f | 295 | if (!byte_reg_is_xH(reg)) { |
c832e3de | 296 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); |
57fec1fe | 297 | } else { |
c832e3de | 298 | tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); |
57fec1fe FB |
299 | } |
300 | break; | |
301 | case OT_WORD: | |
c832e3de | 302 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16); |
57fec1fe | 303 | break; |
cc739bb0 | 304 | default: /* XXX this shouldn't be reached; abort? */ |
57fec1fe | 305 | case OT_LONG: |
cc739bb0 LD |
306 | /* For x86_64, this sets the higher half of register to zero. |
307 | For i386, this is equivalent to a mov. */ | |
308 | tcg_gen_ext32u_tl(cpu_regs[reg], t0); | |
57fec1fe | 309 | break; |
cc739bb0 | 310 | #ifdef TARGET_X86_64 |
57fec1fe | 311 | case OT_QUAD: |
cc739bb0 | 312 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
57fec1fe | 313 | break; |
14ce26e7 | 314 | #endif |
57fec1fe FB |
315 | } |
316 | } | |
2c0262af | 317 | |
57fec1fe FB |
318 | static inline void gen_op_mov_reg_T0(int ot, int reg) |
319 | { | |
1e4840bf | 320 | gen_op_mov_reg_v(ot, reg, cpu_T[0]); |
57fec1fe FB |
321 | } |
322 | ||
323 | static inline void gen_op_mov_reg_T1(int ot, int reg) | |
324 | { | |
1e4840bf | 325 | gen_op_mov_reg_v(ot, reg, cpu_T[1]); |
57fec1fe FB |
326 | } |
327 | ||
328 | static inline void gen_op_mov_reg_A0(int size, int reg) | |
329 | { | |
330 | switch(size) { | |
93ab25d7 | 331 | case OT_BYTE: |
c832e3de | 332 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16); |
57fec1fe | 333 | break; |
cc739bb0 | 334 | default: /* XXX this shouldn't be reached; abort? */ |
93ab25d7 | 335 | case OT_WORD: |
cc739bb0 LD |
336 | /* For x86_64, this sets the higher half of register to zero. |
337 | For i386, this is equivalent to a mov. */ | |
338 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0); | |
57fec1fe | 339 | break; |
cc739bb0 | 340 | #ifdef TARGET_X86_64 |
93ab25d7 | 341 | case OT_LONG: |
cc739bb0 | 342 | tcg_gen_mov_tl(cpu_regs[reg], cpu_A0); |
57fec1fe | 343 | break; |
14ce26e7 | 344 | #endif |
57fec1fe FB |
345 | } |
346 | } | |
347 | ||
1e4840bf | 348 | static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) |
57fec1fe | 349 | { |
96d7073f PM |
350 | if (ot == OT_BYTE && byte_reg_is_xH(reg)) { |
351 | tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); | |
352 | tcg_gen_ext8u_tl(t0, t0); | |
353 | } else { | |
cc739bb0 | 354 | tcg_gen_mov_tl(t0, cpu_regs[reg]); |
57fec1fe FB |
355 | } |
356 | } | |
357 | ||
1e4840bf FB |
358 | static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) |
359 | { | |
360 | gen_op_mov_v_reg(ot, cpu_T[t_index], reg); | |
361 | } | |
362 | ||
57fec1fe FB |
363 | static inline void gen_op_movl_A0_reg(int reg) |
364 | { | |
cc739bb0 | 365 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
366 | } |
367 | ||
368 | static inline void gen_op_addl_A0_im(int32_t val) | |
369 | { | |
370 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
14ce26e7 | 371 | #ifdef TARGET_X86_64 |
57fec1fe | 372 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); |
14ce26e7 | 373 | #endif |
57fec1fe | 374 | } |
2c0262af | 375 | |
14ce26e7 | 376 | #ifdef TARGET_X86_64 |
57fec1fe FB |
377 | static inline void gen_op_addq_A0_im(int64_t val) |
378 | { | |
379 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
380 | } | |
14ce26e7 | 381 | #endif |
57fec1fe FB |
382 | |
383 | static void gen_add_A0_im(DisasContext *s, int val) | |
384 | { | |
385 | #ifdef TARGET_X86_64 | |
386 | if (CODE64(s)) | |
387 | gen_op_addq_A0_im(val); | |
388 | else | |
389 | #endif | |
390 | gen_op_addl_A0_im(val); | |
391 | } | |
2c0262af | 392 | |
57fec1fe | 393 | static inline void gen_op_addl_T0_T1(void) |
2c0262af | 394 | { |
57fec1fe FB |
395 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
396 | } | |
397 | ||
398 | static inline void gen_op_jmp_T0(void) | |
399 | { | |
317ac620 | 400 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip)); |
57fec1fe FB |
401 | } |
402 | ||
6e0d8677 | 403 | static inline void gen_op_add_reg_im(int size, int reg, int32_t val) |
57fec1fe | 404 | { |
6e0d8677 | 405 | switch(size) { |
93ab25d7 | 406 | case OT_BYTE: |
cc739bb0 | 407 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
c832e3de | 408 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 | 409 | break; |
93ab25d7 | 410 | case OT_WORD: |
cc739bb0 LD |
411 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
412 | /* For x86_64, this sets the higher half of register to zero. | |
413 | For i386, this is equivalent to a nop. */ | |
414 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
415 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 FB |
416 | break; |
417 | #ifdef TARGET_X86_64 | |
93ab25d7 | 418 | case OT_LONG: |
cc739bb0 | 419 | tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val); |
6e0d8677 FB |
420 | break; |
421 | #endif | |
422 | } | |
57fec1fe FB |
423 | } |
424 | ||
6e0d8677 | 425 | static inline void gen_op_add_reg_T0(int size, int reg) |
57fec1fe | 426 | { |
6e0d8677 | 427 | switch(size) { |
93ab25d7 | 428 | case OT_BYTE: |
cc739bb0 | 429 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
c832e3de | 430 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 | 431 | break; |
93ab25d7 | 432 | case OT_WORD: |
cc739bb0 LD |
433 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
434 | /* For x86_64, this sets the higher half of register to zero. | |
435 | For i386, this is equivalent to a nop. */ | |
436 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
437 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 | 438 | break; |
14ce26e7 | 439 | #ifdef TARGET_X86_64 |
93ab25d7 | 440 | case OT_LONG: |
cc739bb0 | 441 | tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]); |
6e0d8677 | 442 | break; |
14ce26e7 | 443 | #endif |
6e0d8677 FB |
444 | } |
445 | } | |
57fec1fe FB |
446 | |
447 | static inline void gen_op_set_cc_op(int32_t val) | |
448 | { | |
b6abf97d | 449 | tcg_gen_movi_i32(cpu_cc_op, val); |
57fec1fe FB |
450 | } |
451 | ||
452 | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) | |
453 | { | |
cc739bb0 LD |
454 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
455 | if (shift != 0) | |
57fec1fe FB |
456 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
457 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
cc739bb0 LD |
458 | /* For x86_64, this sets the higher half of register to zero. |
459 | For i386, this is equivalent to a nop. */ | |
460 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
57fec1fe | 461 | } |
2c0262af | 462 | |
57fec1fe FB |
463 | static inline void gen_op_movl_A0_seg(int reg) |
464 | { | |
317ac620 | 465 | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET); |
57fec1fe | 466 | } |
2c0262af | 467 | |
7162ab21 | 468 | static inline void gen_op_addl_A0_seg(DisasContext *s, int reg) |
57fec1fe | 469 | { |
317ac620 | 470 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 471 | #ifdef TARGET_X86_64 |
7162ab21 VC |
472 | if (CODE64(s)) { |
473 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
474 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
475 | } else { | |
476 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
477 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
478 | } | |
479 | #else | |
480 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe FB |
481 | #endif |
482 | } | |
2c0262af | 483 | |
14ce26e7 | 484 | #ifdef TARGET_X86_64 |
57fec1fe FB |
485 | static inline void gen_op_movq_A0_seg(int reg) |
486 | { | |
317ac620 | 487 | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 488 | } |
14ce26e7 | 489 | |
57fec1fe FB |
490 | static inline void gen_op_addq_A0_seg(int reg) |
491 | { | |
317ac620 | 492 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe FB |
493 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
494 | } | |
495 | ||
496 | static inline void gen_op_movq_A0_reg(int reg) | |
497 | { | |
cc739bb0 | 498 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
499 | } |
500 | ||
501 | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) | |
502 | { | |
cc739bb0 LD |
503 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
504 | if (shift != 0) | |
57fec1fe FB |
505 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
506 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
507 | } | |
14ce26e7 FB |
508 | #endif |
509 | ||
57fec1fe FB |
510 | static inline void gen_op_lds_T0_A0(int idx) |
511 | { | |
512 | int mem_index = (idx >> 2) - 1; | |
513 | switch(idx & 3) { | |
93ab25d7 | 514 | case OT_BYTE: |
57fec1fe FB |
515 | tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index); |
516 | break; | |
93ab25d7 | 517 | case OT_WORD: |
57fec1fe FB |
518 | tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index); |
519 | break; | |
520 | default: | |
93ab25d7 | 521 | case OT_LONG: |
57fec1fe FB |
522 | tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index); |
523 | break; | |
524 | } | |
525 | } | |
2c0262af | 526 | |
1e4840bf | 527 | static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) |
57fec1fe FB |
528 | { |
529 | int mem_index = (idx >> 2) - 1; | |
530 | switch(idx & 3) { | |
93ab25d7 | 531 | case OT_BYTE: |
1e4840bf | 532 | tcg_gen_qemu_ld8u(t0, a0, mem_index); |
57fec1fe | 533 | break; |
93ab25d7 | 534 | case OT_WORD: |
1e4840bf | 535 | tcg_gen_qemu_ld16u(t0, a0, mem_index); |
57fec1fe | 536 | break; |
93ab25d7 | 537 | case OT_LONG: |
1e4840bf | 538 | tcg_gen_qemu_ld32u(t0, a0, mem_index); |
57fec1fe FB |
539 | break; |
540 | default: | |
93ab25d7 | 541 | case OT_QUAD: |
a7812ae4 PB |
542 | /* Should never happen on 32-bit targets. */ |
543 | #ifdef TARGET_X86_64 | |
1e4840bf | 544 | tcg_gen_qemu_ld64(t0, a0, mem_index); |
a7812ae4 | 545 | #endif |
57fec1fe FB |
546 | break; |
547 | } | |
548 | } | |
2c0262af | 549 | |
1e4840bf FB |
550 | /* XXX: always use ldu or lds */ |
551 | static inline void gen_op_ld_T0_A0(int idx) | |
552 | { | |
553 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); | |
554 | } | |
555 | ||
57fec1fe FB |
556 | static inline void gen_op_ldu_T0_A0(int idx) |
557 | { | |
1e4840bf | 558 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 559 | } |
2c0262af | 560 | |
57fec1fe | 561 | static inline void gen_op_ld_T1_A0(int idx) |
1e4840bf FB |
562 | { |
563 | gen_op_ld_v(idx, cpu_T[1], cpu_A0); | |
564 | } | |
565 | ||
566 | static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) | |
57fec1fe FB |
567 | { |
568 | int mem_index = (idx >> 2) - 1; | |
569 | switch(idx & 3) { | |
93ab25d7 | 570 | case OT_BYTE: |
1e4840bf | 571 | tcg_gen_qemu_st8(t0, a0, mem_index); |
57fec1fe | 572 | break; |
93ab25d7 | 573 | case OT_WORD: |
1e4840bf | 574 | tcg_gen_qemu_st16(t0, a0, mem_index); |
57fec1fe | 575 | break; |
93ab25d7 | 576 | case OT_LONG: |
1e4840bf | 577 | tcg_gen_qemu_st32(t0, a0, mem_index); |
57fec1fe FB |
578 | break; |
579 | default: | |
93ab25d7 | 580 | case OT_QUAD: |
a7812ae4 PB |
581 | /* Should never happen on 32-bit targets. */ |
582 | #ifdef TARGET_X86_64 | |
1e4840bf | 583 | tcg_gen_qemu_st64(t0, a0, mem_index); |
a7812ae4 | 584 | #endif |
57fec1fe FB |
585 | break; |
586 | } | |
587 | } | |
4f31916f | 588 | |
57fec1fe FB |
589 | static inline void gen_op_st_T0_A0(int idx) |
590 | { | |
1e4840bf | 591 | gen_op_st_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 592 | } |
4f31916f | 593 | |
57fec1fe FB |
594 | static inline void gen_op_st_T1_A0(int idx) |
595 | { | |
1e4840bf | 596 | gen_op_st_v(idx, cpu_T[1], cpu_A0); |
57fec1fe | 597 | } |
4f31916f | 598 | |
14ce26e7 FB |
599 | static inline void gen_jmp_im(target_ulong pc) |
600 | { | |
57fec1fe | 601 | tcg_gen_movi_tl(cpu_tmp0, pc); |
317ac620 | 602 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip)); |
14ce26e7 FB |
603 | } |
604 | ||
2c0262af FB |
605 | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
606 | { | |
607 | int override; | |
608 | ||
609 | override = s->override; | |
14ce26e7 FB |
610 | #ifdef TARGET_X86_64 |
611 | if (s->aflag == 2) { | |
612 | if (override >= 0) { | |
57fec1fe FB |
613 | gen_op_movq_A0_seg(override); |
614 | gen_op_addq_A0_reg_sN(0, R_ESI); | |
14ce26e7 | 615 | } else { |
57fec1fe | 616 | gen_op_movq_A0_reg(R_ESI); |
14ce26e7 FB |
617 | } |
618 | } else | |
619 | #endif | |
2c0262af FB |
620 | if (s->aflag) { |
621 | /* 32 bit address */ | |
622 | if (s->addseg && override < 0) | |
623 | override = R_DS; | |
624 | if (override >= 0) { | |
57fec1fe FB |
625 | gen_op_movl_A0_seg(override); |
626 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af | 627 | } else { |
57fec1fe | 628 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
629 | } |
630 | } else { | |
631 | /* 16 address, always override */ | |
632 | if (override < 0) | |
633 | override = R_DS; | |
57fec1fe | 634 | gen_op_movl_A0_reg(R_ESI); |
2c0262af | 635 | gen_op_andl_A0_ffff(); |
7162ab21 | 636 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
637 | } |
638 | } | |
639 | ||
640 | static inline void gen_string_movl_A0_EDI(DisasContext *s) | |
641 | { | |
14ce26e7 FB |
642 | #ifdef TARGET_X86_64 |
643 | if (s->aflag == 2) { | |
57fec1fe | 644 | gen_op_movq_A0_reg(R_EDI); |
14ce26e7 FB |
645 | } else |
646 | #endif | |
2c0262af FB |
647 | if (s->aflag) { |
648 | if (s->addseg) { | |
57fec1fe FB |
649 | gen_op_movl_A0_seg(R_ES); |
650 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af | 651 | } else { |
57fec1fe | 652 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
653 | } |
654 | } else { | |
57fec1fe | 655 | gen_op_movl_A0_reg(R_EDI); |
2c0262af | 656 | gen_op_andl_A0_ffff(); |
7162ab21 | 657 | gen_op_addl_A0_seg(s, R_ES); |
2c0262af FB |
658 | } |
659 | } | |
660 | ||
6e0d8677 FB |
661 | static inline void gen_op_movl_T0_Dshift(int ot) |
662 | { | |
317ac620 | 663 | tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df)); |
6e0d8677 | 664 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); |
2c0262af FB |
665 | }; |
666 | ||
d824df34 | 667 | static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign) |
6e0d8677 | 668 | { |
d824df34 | 669 | switch (size) { |
6e0d8677 | 670 | case OT_BYTE: |
d824df34 PB |
671 | if (sign) { |
672 | tcg_gen_ext8s_tl(dst, src); | |
673 | } else { | |
674 | tcg_gen_ext8u_tl(dst, src); | |
675 | } | |
676 | return dst; | |
6e0d8677 | 677 | case OT_WORD: |
d824df34 PB |
678 | if (sign) { |
679 | tcg_gen_ext16s_tl(dst, src); | |
680 | } else { | |
681 | tcg_gen_ext16u_tl(dst, src); | |
682 | } | |
683 | return dst; | |
684 | #ifdef TARGET_X86_64 | |
6e0d8677 | 685 | case OT_LONG: |
d824df34 PB |
686 | if (sign) { |
687 | tcg_gen_ext32s_tl(dst, src); | |
688 | } else { | |
689 | tcg_gen_ext32u_tl(dst, src); | |
690 | } | |
691 | return dst; | |
692 | #endif | |
6e0d8677 | 693 | default: |
d824df34 | 694 | return src; |
6e0d8677 FB |
695 | } |
696 | } | |
3b46e624 | 697 | |
d824df34 PB |
698 | static void gen_extu(int ot, TCGv reg) |
699 | { | |
700 | gen_ext_tl(reg, reg, ot, false); | |
701 | } | |
702 | ||
6e0d8677 FB |
703 | static void gen_exts(int ot, TCGv reg) |
704 | { | |
d824df34 | 705 | gen_ext_tl(reg, reg, ot, true); |
6e0d8677 | 706 | } |
2c0262af | 707 | |
6e0d8677 FB |
708 | static inline void gen_op_jnz_ecx(int size, int label1) |
709 | { | |
cc739bb0 | 710 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 711 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 712 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); |
6e0d8677 FB |
713 | } |
714 | ||
715 | static inline void gen_op_jz_ecx(int size, int label1) | |
716 | { | |
cc739bb0 | 717 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 718 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 719 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
6e0d8677 | 720 | } |
2c0262af | 721 | |
a7812ae4 PB |
722 | static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n) |
723 | { | |
724 | switch (ot) { | |
93ab25d7 PB |
725 | case OT_BYTE: |
726 | gen_helper_inb(v, n); | |
727 | break; | |
728 | case OT_WORD: | |
729 | gen_helper_inw(v, n); | |
730 | break; | |
731 | case OT_LONG: | |
732 | gen_helper_inl(v, n); | |
733 | break; | |
a7812ae4 | 734 | } |
a7812ae4 | 735 | } |
2c0262af | 736 | |
a7812ae4 PB |
737 | static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n) |
738 | { | |
739 | switch (ot) { | |
93ab25d7 PB |
740 | case OT_BYTE: |
741 | gen_helper_outb(v, n); | |
742 | break; | |
743 | case OT_WORD: | |
744 | gen_helper_outw(v, n); | |
745 | break; | |
746 | case OT_LONG: | |
747 | gen_helper_outl(v, n); | |
748 | break; | |
a7812ae4 | 749 | } |
a7812ae4 | 750 | } |
f115e911 | 751 | |
b8b6a50b FB |
752 | static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, |
753 | uint32_t svm_flags) | |
f115e911 | 754 | { |
b8b6a50b FB |
755 | int state_saved; |
756 | target_ulong next_eip; | |
757 | ||
758 | state_saved = 0; | |
f115e911 FB |
759 | if (s->pe && (s->cpl > s->iopl || s->vm86)) { |
760 | if (s->cc_op != CC_OP_DYNAMIC) | |
761 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 762 | gen_jmp_im(cur_eip); |
b8b6a50b | 763 | state_saved = 1; |
b6abf97d | 764 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 765 | switch (ot) { |
93ab25d7 | 766 | case OT_BYTE: |
4a7443be BS |
767 | gen_helper_check_iob(cpu_env, cpu_tmp2_i32); |
768 | break; | |
93ab25d7 | 769 | case OT_WORD: |
4a7443be BS |
770 | gen_helper_check_iow(cpu_env, cpu_tmp2_i32); |
771 | break; | |
93ab25d7 | 772 | case OT_LONG: |
4a7443be BS |
773 | gen_helper_check_iol(cpu_env, cpu_tmp2_i32); |
774 | break; | |
a7812ae4 | 775 | } |
b8b6a50b | 776 | } |
872929aa | 777 | if(s->flags & HF_SVMI_MASK) { |
b8b6a50b FB |
778 | if (!state_saved) { |
779 | if (s->cc_op != CC_OP_DYNAMIC) | |
780 | gen_op_set_cc_op(s->cc_op); | |
781 | gen_jmp_im(cur_eip); | |
b8b6a50b FB |
782 | } |
783 | svm_flags |= (1 << (4 + ot)); | |
784 | next_eip = s->pc - s->cs_base; | |
b6abf97d | 785 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
052e80d5 BS |
786 | gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32, |
787 | tcg_const_i32(svm_flags), | |
a7812ae4 | 788 | tcg_const_i32(next_eip - cur_eip)); |
f115e911 FB |
789 | } |
790 | } | |
791 | ||
2c0262af FB |
792 | static inline void gen_movs(DisasContext *s, int ot) |
793 | { | |
794 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 795 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 796 | gen_string_movl_A0_EDI(s); |
57fec1fe | 797 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
798 | gen_op_movl_T0_Dshift(ot); |
799 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
800 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
801 | } |
802 | ||
803 | static inline void gen_update_cc_op(DisasContext *s) | |
804 | { | |
805 | if (s->cc_op != CC_OP_DYNAMIC) { | |
806 | gen_op_set_cc_op(s->cc_op); | |
3ca51d07 | 807 | set_cc_op(s, CC_OP_DYNAMIC); |
2c0262af FB |
808 | } |
809 | } | |
810 | ||
b6abf97d FB |
811 | static void gen_op_update1_cc(void) |
812 | { | |
813 | tcg_gen_discard_tl(cpu_cc_src); | |
814 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
815 | } | |
816 | ||
817 | static void gen_op_update2_cc(void) | |
818 | { | |
819 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
820 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
821 | } | |
822 | ||
823 | static inline void gen_op_cmpl_T0_T1_cc(void) | |
824 | { | |
825 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
826 | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
827 | } | |
828 | ||
829 | static inline void gen_op_testl_T0_T1_cc(void) | |
830 | { | |
831 | tcg_gen_discard_tl(cpu_cc_src); | |
832 | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
833 | } | |
834 | ||
835 | static void gen_op_update_neg_cc(void) | |
836 | { | |
837 | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]); | |
838 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
839 | } | |
840 | ||
8e1c85e3 | 841 | /* compute eflags.C to reg */ |
c7b3c873 | 842 | static void gen_compute_eflags_c(DisasContext *s, TCGv reg) |
8e1c85e3 | 843 | { |
c7b3c873 PB |
844 | if (s->cc_op != CC_OP_DYNAMIC) { |
845 | gen_op_set_cc_op(s->cc_op); | |
846 | } | |
f0967a1a | 847 | gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op); |
8e1c85e3 FB |
848 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
849 | } | |
850 | ||
c7b3c873 PB |
851 | /* compute all eflags to reg */ |
852 | static void gen_compute_eflags(DisasContext *s, TCGv reg) | |
8e1c85e3 | 853 | { |
c7b3c873 PB |
854 | if (s->cc_op != CC_OP_DYNAMIC) { |
855 | gen_op_set_cc_op(s->cc_op); | |
856 | } | |
f0967a1a | 857 | gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_env, cpu_cc_op); |
c7b3c873 PB |
858 | if (TCGV_EQUAL(reg, cpu_cc_src)) { |
859 | tcg_gen_discard_tl(cpu_cc_dst); | |
3ca51d07 | 860 | set_cc_op(s, CC_OP_EFLAGS); |
c7b3c873 | 861 | } |
8e1c85e3 FB |
862 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
863 | } | |
864 | ||
1e4840bf | 865 | static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) |
8e1c85e3 | 866 | { |
1e4840bf | 867 | switch(jcc_op) { |
8e1c85e3 | 868 | case JCC_O: |
c7b3c873 | 869 | gen_compute_eflags(s, cpu_T[0]); |
8e1c85e3 FB |
870 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11); |
871 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
872 | break; | |
873 | case JCC_B: | |
c7b3c873 | 874 | gen_compute_eflags_c(s, cpu_T[0]); |
8e1c85e3 FB |
875 | break; |
876 | case JCC_Z: | |
c7b3c873 | 877 | gen_compute_eflags(s, cpu_T[0]); |
8e1c85e3 FB |
878 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6); |
879 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
880 | break; | |
881 | case JCC_BE: | |
c7b3c873 | 882 | gen_compute_eflags(s, cpu_tmp0); |
8e1c85e3 FB |
883 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6); |
884 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
885 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
886 | break; | |
887 | case JCC_S: | |
c7b3c873 | 888 | gen_compute_eflags(s, cpu_T[0]); |
8e1c85e3 FB |
889 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7); |
890 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
891 | break; | |
892 | case JCC_P: | |
c7b3c873 | 893 | gen_compute_eflags(s, cpu_T[0]); |
8e1c85e3 FB |
894 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2); |
895 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
896 | break; | |
897 | case JCC_L: | |
c7b3c873 | 898 | gen_compute_eflags(s, cpu_tmp0); |
8e1c85e3 FB |
899 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ |
900 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */ | |
901 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
902 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
903 | break; | |
904 | default: | |
905 | case JCC_LE: | |
c7b3c873 | 906 | gen_compute_eflags(s, cpu_tmp0); |
8e1c85e3 FB |
907 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ |
908 | tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */ | |
909 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */ | |
910 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
911 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
912 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
913 | break; | |
914 | } | |
915 | } | |
916 | ||
917 | /* return true if setcc_slow is not needed (WARNING: must be kept in | |
918 | sync with gen_jcc1) */ | |
919 | static int is_fast_jcc_case(DisasContext *s, int b) | |
920 | { | |
921 | int jcc_op; | |
922 | jcc_op = (b >> 1) & 7; | |
923 | switch(s->cc_op) { | |
924 | /* we optimize the cmp/jcc case */ | |
925 | case CC_OP_SUBB: | |
926 | case CC_OP_SUBW: | |
927 | case CC_OP_SUBL: | |
928 | case CC_OP_SUBQ: | |
929 | if (jcc_op == JCC_O || jcc_op == JCC_P) | |
930 | goto slow_jcc; | |
931 | break; | |
932 | ||
933 | /* some jumps are easy to compute */ | |
934 | case CC_OP_ADDB: | |
935 | case CC_OP_ADDW: | |
936 | case CC_OP_ADDL: | |
937 | case CC_OP_ADDQ: | |
938 | ||
939 | case CC_OP_LOGICB: | |
940 | case CC_OP_LOGICW: | |
941 | case CC_OP_LOGICL: | |
942 | case CC_OP_LOGICQ: | |
943 | ||
944 | case CC_OP_INCB: | |
945 | case CC_OP_INCW: | |
946 | case CC_OP_INCL: | |
947 | case CC_OP_INCQ: | |
948 | ||
949 | case CC_OP_DECB: | |
950 | case CC_OP_DECW: | |
951 | case CC_OP_DECL: | |
952 | case CC_OP_DECQ: | |
953 | ||
954 | case CC_OP_SHLB: | |
955 | case CC_OP_SHLW: | |
956 | case CC_OP_SHLL: | |
957 | case CC_OP_SHLQ: | |
958 | if (jcc_op != JCC_Z && jcc_op != JCC_S) | |
959 | goto slow_jcc; | |
960 | break; | |
961 | default: | |
962 | slow_jcc: | |
963 | return 0; | |
964 | } | |
965 | return 1; | |
966 | } | |
967 | ||
968 | /* generate a conditional jump to label 'l1' according to jump opcode | |
969 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
b27fc131 | 970 | static inline void gen_jcc1(DisasContext *s, int b, int l1) |
8e1c85e3 FB |
971 | { |
972 | int inv, jcc_op, size, cond; | |
973 | TCGv t0; | |
974 | ||
975 | inv = b & 1; | |
976 | jcc_op = (b >> 1) & 7; | |
977 | ||
b27fc131 | 978 | switch (s->cc_op) { |
8e1c85e3 FB |
979 | /* we optimize the cmp/jcc case */ |
980 | case CC_OP_SUBB: | |
981 | case CC_OP_SUBW: | |
982 | case CC_OP_SUBL: | |
983 | case CC_OP_SUBQ: | |
984 | ||
b27fc131 | 985 | size = s->cc_op - CC_OP_SUBB; |
8e1c85e3 FB |
986 | switch(jcc_op) { |
987 | case JCC_Z: | |
988 | fast_jcc_z: | |
d824df34 | 989 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_dst, size, false); |
cb63669a | 990 | tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1); |
8e1c85e3 FB |
991 | break; |
992 | case JCC_S: | |
993 | fast_jcc_s: | |
d824df34 PB |
994 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_dst, size, true); |
995 | tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, t0, 0, l1); | |
8e1c85e3 | 996 | break; |
d824df34 | 997 | |
8e1c85e3 FB |
998 | case JCC_B: |
999 | cond = inv ? TCG_COND_GEU : TCG_COND_LTU; | |
1000 | goto fast_jcc_b; | |
1001 | case JCC_BE: | |
1002 | cond = inv ? TCG_COND_GTU : TCG_COND_LEU; | |
1003 | fast_jcc_b: | |
1004 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
d824df34 PB |
1005 | gen_extu(size, cpu_tmp4); |
1006 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); | |
8e1c85e3 FB |
1007 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); |
1008 | break; | |
1009 | ||
1010 | case JCC_L: | |
1011 | cond = inv ? TCG_COND_GE : TCG_COND_LT; | |
1012 | goto fast_jcc_l; | |
1013 | case JCC_LE: | |
1014 | cond = inv ? TCG_COND_GT : TCG_COND_LE; | |
1015 | fast_jcc_l: | |
1016 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
d824df34 PB |
1017 | gen_exts(size, cpu_tmp4); |
1018 | t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true); | |
8e1c85e3 FB |
1019 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); |
1020 | break; | |
1021 | ||
1022 | default: | |
1023 | goto slow_jcc; | |
1024 | } | |
1025 | break; | |
1026 | ||
1027 | /* some jumps are easy to compute */ | |
1028 | case CC_OP_ADDB: | |
1029 | case CC_OP_ADDW: | |
1030 | case CC_OP_ADDL: | |
1031 | case CC_OP_ADDQ: | |
1032 | ||
1033 | case CC_OP_ADCB: | |
1034 | case CC_OP_ADCW: | |
1035 | case CC_OP_ADCL: | |
1036 | case CC_OP_ADCQ: | |
1037 | ||
1038 | case CC_OP_SBBB: | |
1039 | case CC_OP_SBBW: | |
1040 | case CC_OP_SBBL: | |
1041 | case CC_OP_SBBQ: | |
1042 | ||
1043 | case CC_OP_LOGICB: | |
1044 | case CC_OP_LOGICW: | |
1045 | case CC_OP_LOGICL: | |
1046 | case CC_OP_LOGICQ: | |
1047 | ||
1048 | case CC_OP_INCB: | |
1049 | case CC_OP_INCW: | |
1050 | case CC_OP_INCL: | |
1051 | case CC_OP_INCQ: | |
1052 | ||
1053 | case CC_OP_DECB: | |
1054 | case CC_OP_DECW: | |
1055 | case CC_OP_DECL: | |
1056 | case CC_OP_DECQ: | |
1057 | ||
1058 | case CC_OP_SHLB: | |
1059 | case CC_OP_SHLW: | |
1060 | case CC_OP_SHLL: | |
1061 | case CC_OP_SHLQ: | |
1062 | ||
1063 | case CC_OP_SARB: | |
1064 | case CC_OP_SARW: | |
1065 | case CC_OP_SARL: | |
1066 | case CC_OP_SARQ: | |
1067 | switch(jcc_op) { | |
1068 | case JCC_Z: | |
b27fc131 | 1069 | size = (s->cc_op - CC_OP_ADDB) & 3; |
8e1c85e3 FB |
1070 | goto fast_jcc_z; |
1071 | case JCC_S: | |
b27fc131 | 1072 | size = (s->cc_op - CC_OP_ADDB) & 3; |
8e1c85e3 FB |
1073 | goto fast_jcc_s; |
1074 | default: | |
1075 | goto slow_jcc; | |
1076 | } | |
1077 | break; | |
1078 | default: | |
1079 | slow_jcc: | |
1e4840bf | 1080 | gen_setcc_slow_T0(s, jcc_op); |
cb63669a PB |
1081 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, |
1082 | cpu_T[0], 0, l1); | |
8e1c85e3 FB |
1083 | break; |
1084 | } | |
1085 | } | |
1086 | ||
14ce26e7 FB |
1087 | /* XXX: does not work with gdbstub "ice" single step - not a |
1088 | serious problem */ | |
1089 | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) | |
2c0262af | 1090 | { |
14ce26e7 FB |
1091 | int l1, l2; |
1092 | ||
1093 | l1 = gen_new_label(); | |
1094 | l2 = gen_new_label(); | |
6e0d8677 | 1095 | gen_op_jnz_ecx(s->aflag, l1); |
14ce26e7 FB |
1096 | gen_set_label(l2); |
1097 | gen_jmp_tb(s, next_eip, 1); | |
1098 | gen_set_label(l1); | |
1099 | return l2; | |
2c0262af FB |
1100 | } |
1101 | ||
1102 | static inline void gen_stos(DisasContext *s, int ot) | |
1103 | { | |
57fec1fe | 1104 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1105 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1106 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1107 | gen_op_movl_T0_Dshift(ot); |
1108 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1109 | } |
1110 | ||
1111 | static inline void gen_lods(DisasContext *s, int ot) | |
1112 | { | |
1113 | gen_string_movl_A0_ESI(s); | |
57fec1fe FB |
1114 | gen_op_ld_T0_A0(ot + s->mem_index); |
1115 | gen_op_mov_reg_T0(ot, R_EAX); | |
6e0d8677 FB |
1116 | gen_op_movl_T0_Dshift(ot); |
1117 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2c0262af FB |
1118 | } |
1119 | ||
1120 | static inline void gen_scas(DisasContext *s, int ot) | |
1121 | { | |
57fec1fe | 1122 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1123 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1124 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1125 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1126 | gen_op_movl_T0_Dshift(ot); |
1127 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
3ca51d07 | 1128 | set_cc_op(s, CC_OP_SUBB + ot); |
2c0262af FB |
1129 | } |
1130 | ||
1131 | static inline void gen_cmps(DisasContext *s, int ot) | |
1132 | { | |
1133 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 1134 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 1135 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1136 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1137 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1138 | gen_op_movl_T0_Dshift(ot); |
1139 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
1140 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
3ca51d07 | 1141 | set_cc_op(s, CC_OP_SUBB + ot); |
2c0262af FB |
1142 | } |
1143 | ||
1144 | static inline void gen_ins(DisasContext *s, int ot) | |
1145 | { | |
2e70f6ef PB |
1146 | if (use_icount) |
1147 | gen_io_start(); | |
2c0262af | 1148 | gen_string_movl_A0_EDI(s); |
6e0d8677 FB |
1149 | /* Note: we must do this dummy write first to be restartable in |
1150 | case of page fault. */ | |
9772c73b | 1151 | gen_op_movl_T0_0(); |
57fec1fe | 1152 | gen_op_st_T0_A0(ot + s->mem_index); |
b8b6a50b | 1153 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); |
b6abf97d FB |
1154 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1155 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
a7812ae4 | 1156 | gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 1157 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1158 | gen_op_movl_T0_Dshift(ot); |
1159 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2e70f6ef PB |
1160 | if (use_icount) |
1161 | gen_io_end(); | |
2c0262af FB |
1162 | } |
1163 | ||
1164 | static inline void gen_outs(DisasContext *s, int ot) | |
1165 | { | |
2e70f6ef PB |
1166 | if (use_icount) |
1167 | gen_io_start(); | |
2c0262af | 1168 | gen_string_movl_A0_ESI(s); |
57fec1fe | 1169 | gen_op_ld_T0_A0(ot + s->mem_index); |
b8b6a50b FB |
1170 | |
1171 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); | |
b6abf97d FB |
1172 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1173 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
1174 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); | |
a7812ae4 | 1175 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
b8b6a50b | 1176 | |
6e0d8677 FB |
1177 | gen_op_movl_T0_Dshift(ot); |
1178 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2e70f6ef PB |
1179 | if (use_icount) |
1180 | gen_io_end(); | |
2c0262af FB |
1181 | } |
1182 | ||
1183 | /* same method as Valgrind : we generate jumps to current or next | |
1184 | instruction */ | |
1185 | #define GEN_REPZ(op) \ | |
1186 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 | 1187 | target_ulong cur_eip, target_ulong next_eip) \ |
2c0262af | 1188 | { \ |
14ce26e7 | 1189 | int l2;\ |
2c0262af | 1190 | gen_update_cc_op(s); \ |
14ce26e7 | 1191 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1192 | gen_ ## op(s, ot); \ |
6e0d8677 | 1193 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af FB |
1194 | /* a loop would cause two single step exceptions if ECX = 1 \ |
1195 | before rep string_insn */ \ | |
1196 | if (!s->jmp_opt) \ | |
6e0d8677 | 1197 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1198 | gen_jmp(s, cur_eip); \ |
1199 | } | |
1200 | ||
1201 | #define GEN_REPZ2(op) \ | |
1202 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 FB |
1203 | target_ulong cur_eip, \ |
1204 | target_ulong next_eip, \ | |
2c0262af FB |
1205 | int nz) \ |
1206 | { \ | |
14ce26e7 | 1207 | int l2;\ |
2c0262af | 1208 | gen_update_cc_op(s); \ |
14ce26e7 | 1209 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1210 | gen_ ## op(s, ot); \ |
6e0d8677 | 1211 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
91642ff8 | 1212 | gen_op_set_cc_op(s->cc_op); \ |
b27fc131 | 1213 | gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \ |
2c0262af | 1214 | if (!s->jmp_opt) \ |
6e0d8677 | 1215 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af | 1216 | gen_jmp(s, cur_eip); \ |
3ca51d07 | 1217 | set_cc_op(s, CC_OP_DYNAMIC); \ |
2c0262af FB |
1218 | } |
1219 | ||
1220 | GEN_REPZ(movs) | |
1221 | GEN_REPZ(stos) | |
1222 | GEN_REPZ(lods) | |
1223 | GEN_REPZ(ins) | |
1224 | GEN_REPZ(outs) | |
1225 | GEN_REPZ2(scas) | |
1226 | GEN_REPZ2(cmps) | |
1227 | ||
a7812ae4 PB |
1228 | static void gen_helper_fp_arith_ST0_FT0(int op) |
1229 | { | |
1230 | switch (op) { | |
d3eb5eae BS |
1231 | case 0: |
1232 | gen_helper_fadd_ST0_FT0(cpu_env); | |
1233 | break; | |
1234 | case 1: | |
1235 | gen_helper_fmul_ST0_FT0(cpu_env); | |
1236 | break; | |
1237 | case 2: | |
1238 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1239 | break; | |
1240 | case 3: | |
1241 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1242 | break; | |
1243 | case 4: | |
1244 | gen_helper_fsub_ST0_FT0(cpu_env); | |
1245 | break; | |
1246 | case 5: | |
1247 | gen_helper_fsubr_ST0_FT0(cpu_env); | |
1248 | break; | |
1249 | case 6: | |
1250 | gen_helper_fdiv_ST0_FT0(cpu_env); | |
1251 | break; | |
1252 | case 7: | |
1253 | gen_helper_fdivr_ST0_FT0(cpu_env); | |
1254 | break; | |
a7812ae4 PB |
1255 | } |
1256 | } | |
2c0262af FB |
1257 | |
1258 | /* NOTE the exception in "r" op ordering */ | |
a7812ae4 PB |
1259 | static void gen_helper_fp_arith_STN_ST0(int op, int opreg) |
1260 | { | |
1261 | TCGv_i32 tmp = tcg_const_i32(opreg); | |
1262 | switch (op) { | |
d3eb5eae BS |
1263 | case 0: |
1264 | gen_helper_fadd_STN_ST0(cpu_env, tmp); | |
1265 | break; | |
1266 | case 1: | |
1267 | gen_helper_fmul_STN_ST0(cpu_env, tmp); | |
1268 | break; | |
1269 | case 4: | |
1270 | gen_helper_fsubr_STN_ST0(cpu_env, tmp); | |
1271 | break; | |
1272 | case 5: | |
1273 | gen_helper_fsub_STN_ST0(cpu_env, tmp); | |
1274 | break; | |
1275 | case 6: | |
1276 | gen_helper_fdivr_STN_ST0(cpu_env, tmp); | |
1277 | break; | |
1278 | case 7: | |
1279 | gen_helper_fdiv_STN_ST0(cpu_env, tmp); | |
1280 | break; | |
a7812ae4 PB |
1281 | } |
1282 | } | |
2c0262af FB |
1283 | |
1284 | /* if d == OR_TMP0, it means memory operand (address in A0) */ | |
1285 | static void gen_op(DisasContext *s1, int op, int ot, int d) | |
1286 | { | |
2c0262af | 1287 | if (d != OR_TMP0) { |
57fec1fe | 1288 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1289 | } else { |
57fec1fe | 1290 | gen_op_ld_T0_A0(ot + s1->mem_index); |
2c0262af FB |
1291 | } |
1292 | switch(op) { | |
1293 | case OP_ADCL: | |
c7b3c873 | 1294 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1295 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1296 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1297 | if (d != OR_TMP0) | |
1298 | gen_op_mov_reg_T0(ot, d); | |
1299 | else | |
1300 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1301 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1302 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1303 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1304 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1305 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot); | |
3ca51d07 | 1306 | set_cc_op(s1, CC_OP_DYNAMIC); |
cad3a37d | 1307 | break; |
2c0262af | 1308 | case OP_SBBL: |
c7b3c873 | 1309 | gen_compute_eflags_c(s1, cpu_tmp4); |
cad3a37d FB |
1310 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1311 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1312 | if (d != OR_TMP0) | |
57fec1fe | 1313 | gen_op_mov_reg_T0(ot, d); |
cad3a37d FB |
1314 | else |
1315 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1316 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1317 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1318 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1319 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1320 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot); | |
3ca51d07 | 1321 | set_cc_op(s1, CC_OP_DYNAMIC); |
cad3a37d | 1322 | break; |
2c0262af FB |
1323 | case OP_ADDL: |
1324 | gen_op_addl_T0_T1(); | |
cad3a37d FB |
1325 | if (d != OR_TMP0) |
1326 | gen_op_mov_reg_T0(ot, d); | |
1327 | else | |
1328 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1329 | gen_op_update2_cc(); | |
3ca51d07 | 1330 | set_cc_op(s1, CC_OP_ADDB + ot); |
2c0262af FB |
1331 | break; |
1332 | case OP_SUBL: | |
57fec1fe | 1333 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1334 | if (d != OR_TMP0) |
1335 | gen_op_mov_reg_T0(ot, d); | |
1336 | else | |
1337 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1338 | gen_op_update2_cc(); | |
3ca51d07 | 1339 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1340 | break; |
1341 | default: | |
1342 | case OP_ANDL: | |
57fec1fe | 1343 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1344 | if (d != OR_TMP0) |
1345 | gen_op_mov_reg_T0(ot, d); | |
1346 | else | |
1347 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1348 | gen_op_update1_cc(); | |
3ca51d07 | 1349 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1350 | break; |
2c0262af | 1351 | case OP_ORL: |
57fec1fe | 1352 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1353 | if (d != OR_TMP0) |
1354 | gen_op_mov_reg_T0(ot, d); | |
1355 | else | |
1356 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1357 | gen_op_update1_cc(); | |
3ca51d07 | 1358 | set_cc_op(s1, CC_OP_LOGICB + ot); |
57fec1fe | 1359 | break; |
2c0262af | 1360 | case OP_XORL: |
57fec1fe | 1361 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1362 | if (d != OR_TMP0) |
1363 | gen_op_mov_reg_T0(ot, d); | |
1364 | else | |
1365 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1366 | gen_op_update1_cc(); | |
3ca51d07 | 1367 | set_cc_op(s1, CC_OP_LOGICB + ot); |
2c0262af FB |
1368 | break; |
1369 | case OP_CMPL: | |
1370 | gen_op_cmpl_T0_T1_cc(); | |
3ca51d07 | 1371 | set_cc_op(s1, CC_OP_SUBB + ot); |
2c0262af FB |
1372 | break; |
1373 | } | |
b6abf97d FB |
1374 | } |
1375 | ||
2c0262af FB |
1376 | /* if d == OR_TMP0, it means memory operand (address in A0) */ |
1377 | static void gen_inc(DisasContext *s1, int ot, int d, int c) | |
1378 | { | |
1379 | if (d != OR_TMP0) | |
57fec1fe | 1380 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1381 | else |
57fec1fe | 1382 | gen_op_ld_T0_A0(ot + s1->mem_index); |
c7b3c873 | 1383 | gen_compute_eflags_c(s1, cpu_cc_src); |
2c0262af | 1384 | if (c > 0) { |
b6abf97d | 1385 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
3ca51d07 | 1386 | set_cc_op(s1, CC_OP_INCB + ot); |
2c0262af | 1387 | } else { |
b6abf97d | 1388 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
3ca51d07 | 1389 | set_cc_op(s1, CC_OP_DECB + ot); |
2c0262af FB |
1390 | } |
1391 | if (d != OR_TMP0) | |
57fec1fe | 1392 | gen_op_mov_reg_T0(ot, d); |
2c0262af | 1393 | else |
57fec1fe | 1394 | gen_op_st_T0_A0(ot + s1->mem_index); |
cd31fefa | 1395 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
2c0262af FB |
1396 | } |
1397 | ||
b6abf97d FB |
1398 | static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
1399 | int is_right, int is_arith) | |
2c0262af | 1400 | { |
b6abf97d FB |
1401 | target_ulong mask; |
1402 | int shift_label; | |
82786041 | 1403 | TCGv t0, t1, t2; |
1e4840bf | 1404 | |
82786041 | 1405 | if (ot == OT_QUAD) { |
b6abf97d | 1406 | mask = 0x3f; |
82786041 | 1407 | } else { |
b6abf97d | 1408 | mask = 0x1f; |
82786041 | 1409 | } |
3b46e624 | 1410 | |
b6abf97d | 1411 | /* load */ |
82786041 | 1412 | if (op1 == OR_TMP0) { |
b6abf97d | 1413 | gen_op_ld_T0_A0(ot + s->mem_index); |
82786041 | 1414 | } else { |
b6abf97d | 1415 | gen_op_mov_TN_reg(ot, 0, op1); |
82786041 | 1416 | } |
b6abf97d | 1417 | |
82786041 RH |
1418 | t0 = tcg_temp_local_new(); |
1419 | t1 = tcg_temp_local_new(); | |
1420 | t2 = tcg_temp_local_new(); | |
b6abf97d | 1421 | |
82786041 | 1422 | tcg_gen_andi_tl(t2, cpu_T[1], mask); |
b6abf97d FB |
1423 | |
1424 | if (is_right) { | |
1425 | if (is_arith) { | |
f484d386 | 1426 | gen_exts(ot, cpu_T[0]); |
82786041 RH |
1427 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1428 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d | 1429 | } else { |
cad3a37d | 1430 | gen_extu(ot, cpu_T[0]); |
82786041 RH |
1431 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1432 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1433 | } |
1434 | } else { | |
82786041 RH |
1435 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1436 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1437 | } |
1438 | ||
1439 | /* store */ | |
82786041 | 1440 | if (op1 == OR_TMP0) { |
b6abf97d | 1441 | gen_op_st_T0_A0(ot + s->mem_index); |
82786041 | 1442 | } else { |
b6abf97d | 1443 | gen_op_mov_reg_T0(ot, op1); |
82786041 RH |
1444 | } |
1445 | ||
b6abf97d | 1446 | /* update eflags if non zero shift */ |
82786041 | 1447 | if (s->cc_op != CC_OP_DYNAMIC) { |
b6abf97d | 1448 | gen_op_set_cc_op(s->cc_op); |
82786041 | 1449 | } |
b6abf97d | 1450 | |
82786041 | 1451 | tcg_gen_mov_tl(t1, cpu_T[0]); |
1e4840bf | 1452 | |
b6abf97d | 1453 | shift_label = gen_new_label(); |
82786041 RH |
1454 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label); |
1455 | ||
1456 | tcg_gen_addi_tl(t2, t2, -1); | |
1457 | tcg_gen_mov_tl(cpu_cc_dst, t1); | |
1458 | ||
1459 | if (is_right) { | |
1460 | if (is_arith) { | |
1461 | tcg_gen_sar_tl(cpu_cc_src, t0, t2); | |
1462 | } else { | |
1463 | tcg_gen_shr_tl(cpu_cc_src, t0, t2); | |
1464 | } | |
1465 | } else { | |
1466 | tcg_gen_shl_tl(cpu_cc_src, t0, t2); | |
1467 | } | |
b6abf97d | 1468 | |
82786041 | 1469 | if (is_right) { |
b6abf97d | 1470 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
82786041 | 1471 | } else { |
b6abf97d | 1472 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
82786041 RH |
1473 | } |
1474 | ||
b6abf97d | 1475 | gen_set_label(shift_label); |
3ca51d07 | 1476 | set_cc_op(s, CC_OP_DYNAMIC); /* cannot predict flags after */ |
1e4840bf FB |
1477 | |
1478 | tcg_temp_free(t0); | |
1479 | tcg_temp_free(t1); | |
82786041 | 1480 | tcg_temp_free(t2); |
b6abf97d FB |
1481 | } |
1482 | ||
c1c37968 FB |
1483 | static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, |
1484 | int is_right, int is_arith) | |
1485 | { | |
1486 | int mask; | |
1487 | ||
1488 | if (ot == OT_QUAD) | |
1489 | mask = 0x3f; | |
1490 | else | |
1491 | mask = 0x1f; | |
1492 | ||
1493 | /* load */ | |
1494 | if (op1 == OR_TMP0) | |
1495 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1496 | else | |
1497 | gen_op_mov_TN_reg(ot, 0, op1); | |
1498 | ||
1499 | op2 &= mask; | |
1500 | if (op2 != 0) { | |
1501 | if (is_right) { | |
1502 | if (is_arith) { | |
1503 | gen_exts(ot, cpu_T[0]); | |
2a449d14 | 1504 | tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1505 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
1506 | } else { | |
1507 | gen_extu(ot, cpu_T[0]); | |
2a449d14 | 1508 | tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1509 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
1510 | } | |
1511 | } else { | |
2a449d14 | 1512 | tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1513 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
1514 | } | |
1515 | } | |
1516 | ||
1517 | /* store */ | |
1518 | if (op1 == OR_TMP0) | |
1519 | gen_op_st_T0_A0(ot + s->mem_index); | |
1520 | else | |
1521 | gen_op_mov_reg_T0(ot, op1); | |
1522 | ||
1523 | /* update eflags if non zero shift */ | |
1524 | if (op2 != 0) { | |
2a449d14 | 1525 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
c1c37968 | 1526 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
3ca51d07 | 1527 | set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot); |
c1c37968 FB |
1528 | } |
1529 | } | |
1530 | ||
b6abf97d FB |
1531 | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1532 | { | |
1533 | if (arg2 >= 0) | |
1534 | tcg_gen_shli_tl(ret, arg1, arg2); | |
1535 | else | |
1536 | tcg_gen_shri_tl(ret, arg1, -arg2); | |
1537 | } | |
1538 | ||
b6abf97d FB |
1539 | static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, |
1540 | int is_right) | |
1541 | { | |
1542 | target_ulong mask; | |
1543 | int label1, label2, data_bits; | |
1e4840bf FB |
1544 | TCGv t0, t1, t2, a0; |
1545 | ||
1546 | /* XXX: inefficient, but we must use local temps */ | |
a7812ae4 PB |
1547 | t0 = tcg_temp_local_new(); |
1548 | t1 = tcg_temp_local_new(); | |
1549 | t2 = tcg_temp_local_new(); | |
1550 | a0 = tcg_temp_local_new(); | |
1e4840bf | 1551 | |
b6abf97d FB |
1552 | if (ot == OT_QUAD) |
1553 | mask = 0x3f; | |
1554 | else | |
1555 | mask = 0x1f; | |
1556 | ||
1557 | /* load */ | |
1e4840bf FB |
1558 | if (op1 == OR_TMP0) { |
1559 | tcg_gen_mov_tl(a0, cpu_A0); | |
1560 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1561 | } else { | |
1562 | gen_op_mov_v_reg(ot, t0, op1); | |
1563 | } | |
b6abf97d | 1564 | |
1e4840bf FB |
1565 | tcg_gen_mov_tl(t1, cpu_T[1]); |
1566 | ||
1567 | tcg_gen_andi_tl(t1, t1, mask); | |
b6abf97d FB |
1568 | |
1569 | /* Must test zero case to avoid using undefined behaviour in TCG | |
1570 | shifts. */ | |
1571 | label1 = gen_new_label(); | |
1e4840bf | 1572 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1); |
b6abf97d FB |
1573 | |
1574 | if (ot <= OT_WORD) | |
1e4840bf | 1575 | tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); |
b6abf97d | 1576 | else |
1e4840bf | 1577 | tcg_gen_mov_tl(cpu_tmp0, t1); |
b6abf97d | 1578 | |
1e4840bf FB |
1579 | gen_extu(ot, t0); |
1580 | tcg_gen_mov_tl(t2, t0); | |
b6abf97d FB |
1581 | |
1582 | data_bits = 8 << ot; | |
1583 | /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX: | |
1584 | fix TCG definition) */ | |
1585 | if (is_right) { | |
1e4840bf | 1586 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1587 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1588 | tcg_gen_shl_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1589 | } else { |
1e4840bf | 1590 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1591 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1592 | tcg_gen_shr_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1593 | } |
1e4840bf | 1594 | tcg_gen_or_tl(t0, t0, cpu_tmp4); |
b6abf97d FB |
1595 | |
1596 | gen_set_label(label1); | |
1597 | /* store */ | |
1e4840bf FB |
1598 | if (op1 == OR_TMP0) { |
1599 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1600 | } else { | |
1601 | gen_op_mov_reg_v(ot, op1, t0); | |
1602 | } | |
b6abf97d | 1603 | |
0ff6addd | 1604 | /* update eflags. It is needed anyway most of the time, do it always. */ |
c7b3c873 PB |
1605 | gen_compute_eflags(s, cpu_cc_src); |
1606 | assert(s->cc_op == CC_OP_EFLAGS); | |
b6abf97d FB |
1607 | |
1608 | label2 = gen_new_label(); | |
1e4840bf | 1609 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2); |
b6abf97d | 1610 | |
b6abf97d | 1611 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
1e4840bf | 1612 | tcg_gen_xor_tl(cpu_tmp0, t2, t0); |
b6abf97d FB |
1613 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
1614 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1615 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1616 | if (is_right) { | |
1e4840bf | 1617 | tcg_gen_shri_tl(t0, t0, data_bits - 1); |
b6abf97d | 1618 | } |
1e4840bf FB |
1619 | tcg_gen_andi_tl(t0, t0, CC_C); |
1620 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
0ff6addd | 1621 | |
b6abf97d | 1622 | gen_set_label(label2); |
1e4840bf FB |
1623 | |
1624 | tcg_temp_free(t0); | |
1625 | tcg_temp_free(t1); | |
1626 | tcg_temp_free(t2); | |
1627 | tcg_temp_free(a0); | |
b6abf97d FB |
1628 | } |
1629 | ||
8cd6345d | 1630 | static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, |
1631 | int is_right) | |
1632 | { | |
1633 | int mask; | |
1634 | int data_bits; | |
1635 | TCGv t0, t1, a0; | |
1636 | ||
1637 | /* XXX: inefficient, but we must use local temps */ | |
1638 | t0 = tcg_temp_local_new(); | |
1639 | t1 = tcg_temp_local_new(); | |
1640 | a0 = tcg_temp_local_new(); | |
1641 | ||
1642 | if (ot == OT_QUAD) | |
1643 | mask = 0x3f; | |
1644 | else | |
1645 | mask = 0x1f; | |
1646 | ||
1647 | /* load */ | |
1648 | if (op1 == OR_TMP0) { | |
1649 | tcg_gen_mov_tl(a0, cpu_A0); | |
1650 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1651 | } else { | |
1652 | gen_op_mov_v_reg(ot, t0, op1); | |
1653 | } | |
1654 | ||
1655 | gen_extu(ot, t0); | |
1656 | tcg_gen_mov_tl(t1, t0); | |
1657 | ||
1658 | op2 &= mask; | |
1659 | data_bits = 8 << ot; | |
1660 | if (op2 != 0) { | |
1661 | int shift = op2 & ((1 << (3 + ot)) - 1); | |
1662 | if (is_right) { | |
1663 | tcg_gen_shri_tl(cpu_tmp4, t0, shift); | |
1664 | tcg_gen_shli_tl(t0, t0, data_bits - shift); | |
1665 | } | |
1666 | else { | |
1667 | tcg_gen_shli_tl(cpu_tmp4, t0, shift); | |
1668 | tcg_gen_shri_tl(t0, t0, data_bits - shift); | |
1669 | } | |
1670 | tcg_gen_or_tl(t0, t0, cpu_tmp4); | |
1671 | } | |
1672 | ||
1673 | /* store */ | |
1674 | if (op1 == OR_TMP0) { | |
1675 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1676 | } else { | |
1677 | gen_op_mov_reg_v(ot, op1, t0); | |
1678 | } | |
1679 | ||
1680 | if (op2 != 0) { | |
1681 | /* update eflags */ | |
c7b3c873 PB |
1682 | gen_compute_eflags(s, cpu_cc_src); |
1683 | assert(s->cc_op == CC_OP_EFLAGS); | |
0ff6addd | 1684 | |
8cd6345d | 1685 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
1686 | tcg_gen_xor_tl(cpu_tmp0, t1, t0); | |
1687 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); | |
1688 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1689 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1690 | if (is_right) { | |
1691 | tcg_gen_shri_tl(t0, t0, data_bits - 1); | |
1692 | } | |
1693 | tcg_gen_andi_tl(t0, t0, CC_C); | |
1694 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
8cd6345d | 1695 | } |
1696 | ||
1697 | tcg_temp_free(t0); | |
1698 | tcg_temp_free(t1); | |
1699 | tcg_temp_free(a0); | |
1700 | } | |
1701 | ||
b6abf97d FB |
1702 | /* XXX: add faster immediate = 1 case */ |
1703 | static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, | |
1704 | int is_right) | |
1705 | { | |
b6abf97d FB |
1706 | if (s->cc_op != CC_OP_DYNAMIC) |
1707 | gen_op_set_cc_op(s->cc_op); | |
c7b3c873 PB |
1708 | gen_compute_eflags(s, cpu_cc_src); |
1709 | assert(s->cc_op == CC_OP_EFLAGS); | |
b6abf97d FB |
1710 | |
1711 | /* load */ | |
1712 | if (op1 == OR_TMP0) | |
1713 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1714 | else | |
1715 | gen_op_mov_TN_reg(ot, 0, op1); | |
1716 | ||
a7812ae4 PB |
1717 | if (is_right) { |
1718 | switch (ot) { | |
93ab25d7 | 1719 | case OT_BYTE: |
7923057b BS |
1720 | gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1721 | break; | |
93ab25d7 | 1722 | case OT_WORD: |
7923057b BS |
1723 | gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1724 | break; | |
93ab25d7 | 1725 | case OT_LONG: |
7923057b BS |
1726 | gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1727 | break; | |
a7812ae4 | 1728 | #ifdef TARGET_X86_64 |
93ab25d7 | 1729 | case OT_QUAD: |
7923057b BS |
1730 | gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1731 | break; | |
a7812ae4 PB |
1732 | #endif |
1733 | } | |
1734 | } else { | |
1735 | switch (ot) { | |
93ab25d7 | 1736 | case OT_BYTE: |
7923057b BS |
1737 | gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1738 | break; | |
93ab25d7 | 1739 | case OT_WORD: |
7923057b BS |
1740 | gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1741 | break; | |
93ab25d7 | 1742 | case OT_LONG: |
7923057b BS |
1743 | gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1744 | break; | |
a7812ae4 | 1745 | #ifdef TARGET_X86_64 |
93ab25d7 | 1746 | case OT_QUAD: |
7923057b BS |
1747 | gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
1748 | break; | |
a7812ae4 PB |
1749 | #endif |
1750 | } | |
1751 | } | |
b6abf97d FB |
1752 | /* store */ |
1753 | if (op1 == OR_TMP0) | |
1754 | gen_op_st_T0_A0(ot + s->mem_index); | |
1755 | else | |
1756 | gen_op_mov_reg_T0(ot, op1); | |
b6abf97d FB |
1757 | } |
1758 | ||
1759 | /* XXX: add faster immediate case */ | |
1760 | static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, | |
1761 | int is_right) | |
1762 | { | |
1763 | int label1, label2, data_bits; | |
1764 | target_ulong mask; | |
1e4840bf FB |
1765 | TCGv t0, t1, t2, a0; |
1766 | ||
a7812ae4 PB |
1767 | t0 = tcg_temp_local_new(); |
1768 | t1 = tcg_temp_local_new(); | |
1769 | t2 = tcg_temp_local_new(); | |
1770 | a0 = tcg_temp_local_new(); | |
b6abf97d FB |
1771 | |
1772 | if (ot == OT_QUAD) | |
1773 | mask = 0x3f; | |
1774 | else | |
1775 | mask = 0x1f; | |
1776 | ||
1777 | /* load */ | |
1e4840bf FB |
1778 | if (op1 == OR_TMP0) { |
1779 | tcg_gen_mov_tl(a0, cpu_A0); | |
1780 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1781 | } else { | |
1782 | gen_op_mov_v_reg(ot, t0, op1); | |
1783 | } | |
b6abf97d FB |
1784 | |
1785 | tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); | |
1e4840bf FB |
1786 | |
1787 | tcg_gen_mov_tl(t1, cpu_T[1]); | |
1788 | tcg_gen_mov_tl(t2, cpu_T3); | |
1789 | ||
b6abf97d FB |
1790 | /* Must test zero case to avoid using undefined behaviour in TCG |
1791 | shifts. */ | |
1792 | label1 = gen_new_label(); | |
1e4840bf | 1793 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); |
b6abf97d | 1794 | |
1e4840bf | 1795 | tcg_gen_addi_tl(cpu_tmp5, t2, -1); |
b6abf97d FB |
1796 | if (ot == OT_WORD) { |
1797 | /* Note: we implement the Intel behaviour for shift count > 16 */ | |
1798 | if (is_right) { | |
1e4840bf FB |
1799 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1800 | tcg_gen_shli_tl(cpu_tmp0, t1, 16); | |
1801 | tcg_gen_or_tl(t0, t0, cpu_tmp0); | |
1802 | tcg_gen_ext32u_tl(t0, t0); | |
b6abf97d | 1803 | |
1e4840bf | 1804 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d FB |
1805 | |
1806 | /* only needed if count > 16, but a test would complicate */ | |
5b207c00 | 1807 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf | 1808 | tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5); |
b6abf97d | 1809 | |
1e4840bf | 1810 | tcg_gen_shr_tl(t0, t0, t2); |
b6abf97d | 1811 | |
1e4840bf | 1812 | tcg_gen_or_tl(t0, t0, cpu_tmp0); |
b6abf97d FB |
1813 | } else { |
1814 | /* XXX: not optimal */ | |
1e4840bf FB |
1815 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1816 | tcg_gen_shli_tl(t1, t1, 16); | |
1817 | tcg_gen_or_tl(t1, t1, t0); | |
1818 | tcg_gen_ext32u_tl(t1, t1); | |
b6abf97d | 1819 | |
1e4840bf | 1820 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
5b207c00 | 1821 | tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5); |
bedda79c AJ |
1822 | tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0); |
1823 | tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5); | |
b6abf97d | 1824 | |
1e4840bf | 1825 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1826 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf FB |
1827 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1828 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1829 | } |
1830 | } else { | |
1831 | data_bits = 8 << ot; | |
1832 | if (is_right) { | |
1833 | if (ot == OT_LONG) | |
1e4840bf | 1834 | tcg_gen_ext32u_tl(t0, t0); |
b6abf97d | 1835 | |
1e4840bf | 1836 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1837 | |
1e4840bf | 1838 | tcg_gen_shr_tl(t0, t0, t2); |
5b207c00 | 1839 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1840 | tcg_gen_shl_tl(t1, t1, cpu_tmp5); |
1841 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1842 | |
1843 | } else { | |
1844 | if (ot == OT_LONG) | |
1e4840bf | 1845 | tcg_gen_ext32u_tl(t1, t1); |
b6abf97d | 1846 | |
1e4840bf | 1847 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1848 | |
1e4840bf | 1849 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1850 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1851 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1852 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1853 | } |
1854 | } | |
1e4840bf | 1855 | tcg_gen_mov_tl(t1, cpu_tmp4); |
b6abf97d FB |
1856 | |
1857 | gen_set_label(label1); | |
1858 | /* store */ | |
1e4840bf FB |
1859 | if (op1 == OR_TMP0) { |
1860 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1861 | } else { | |
1862 | gen_op_mov_reg_v(ot, op1, t0); | |
1863 | } | |
b6abf97d FB |
1864 | |
1865 | /* update eflags */ | |
1866 | if (s->cc_op != CC_OP_DYNAMIC) | |
1867 | gen_op_set_cc_op(s->cc_op); | |
1868 | ||
1869 | label2 = gen_new_label(); | |
1e4840bf | 1870 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2); |
b6abf97d | 1871 | |
1e4840bf FB |
1872 | tcg_gen_mov_tl(cpu_cc_src, t1); |
1873 | tcg_gen_mov_tl(cpu_cc_dst, t0); | |
b6abf97d FB |
1874 | if (is_right) { |
1875 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); | |
1876 | } else { | |
1877 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); | |
1878 | } | |
1879 | gen_set_label(label2); | |
3ca51d07 | 1880 | set_cc_op(s, CC_OP_DYNAMIC); /* cannot predict flags after */ |
1e4840bf FB |
1881 | |
1882 | tcg_temp_free(t0); | |
1883 | tcg_temp_free(t1); | |
1884 | tcg_temp_free(t2); | |
1885 | tcg_temp_free(a0); | |
b6abf97d FB |
1886 | } |
1887 | ||
1888 | static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) | |
1889 | { | |
1890 | if (s != OR_TMP1) | |
1891 | gen_op_mov_TN_reg(ot, 1, s); | |
1892 | switch(op) { | |
1893 | case OP_ROL: | |
1894 | gen_rot_rm_T1(s1, ot, d, 0); | |
1895 | break; | |
1896 | case OP_ROR: | |
1897 | gen_rot_rm_T1(s1, ot, d, 1); | |
1898 | break; | |
1899 | case OP_SHL: | |
1900 | case OP_SHL1: | |
1901 | gen_shift_rm_T1(s1, ot, d, 0, 0); | |
1902 | break; | |
1903 | case OP_SHR: | |
1904 | gen_shift_rm_T1(s1, ot, d, 1, 0); | |
1905 | break; | |
1906 | case OP_SAR: | |
1907 | gen_shift_rm_T1(s1, ot, d, 1, 1); | |
1908 | break; | |
1909 | case OP_RCL: | |
1910 | gen_rotc_rm_T1(s1, ot, d, 0); | |
1911 | break; | |
1912 | case OP_RCR: | |
1913 | gen_rotc_rm_T1(s1, ot, d, 1); | |
1914 | break; | |
1915 | } | |
2c0262af FB |
1916 | } |
1917 | ||
1918 | static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) | |
1919 | { | |
c1c37968 | 1920 | switch(op) { |
8cd6345d | 1921 | case OP_ROL: |
1922 | gen_rot_rm_im(s1, ot, d, c, 0); | |
1923 | break; | |
1924 | case OP_ROR: | |
1925 | gen_rot_rm_im(s1, ot, d, c, 1); | |
1926 | break; | |
c1c37968 FB |
1927 | case OP_SHL: |
1928 | case OP_SHL1: | |
1929 | gen_shift_rm_im(s1, ot, d, c, 0, 0); | |
1930 | break; | |
1931 | case OP_SHR: | |
1932 | gen_shift_rm_im(s1, ot, d, c, 1, 0); | |
1933 | break; | |
1934 | case OP_SAR: | |
1935 | gen_shift_rm_im(s1, ot, d, c, 1, 1); | |
1936 | break; | |
1937 | default: | |
1938 | /* currently not optimized */ | |
1939 | gen_op_movl_T1_im(c); | |
1940 | gen_shift(s1, op, ot, d, OR_TMP1); | |
1941 | break; | |
1942 | } | |
2c0262af FB |
1943 | } |
1944 | ||
0af10c86 BS |
1945 | static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm, |
1946 | int *reg_ptr, int *offset_ptr) | |
2c0262af | 1947 | { |
14ce26e7 | 1948 | target_long disp; |
2c0262af | 1949 | int havesib; |
14ce26e7 | 1950 | int base; |
2c0262af FB |
1951 | int index; |
1952 | int scale; | |
1953 | int opreg; | |
1954 | int mod, rm, code, override, must_add_seg; | |
1955 | ||
1956 | override = s->override; | |
1957 | must_add_seg = s->addseg; | |
1958 | if (override >= 0) | |
1959 | must_add_seg = 1; | |
1960 | mod = (modrm >> 6) & 3; | |
1961 | rm = modrm & 7; | |
1962 | ||
1963 | if (s->aflag) { | |
1964 | ||
1965 | havesib = 0; | |
1966 | base = rm; | |
1967 | index = 0; | |
1968 | scale = 0; | |
3b46e624 | 1969 | |
2c0262af FB |
1970 | if (base == 4) { |
1971 | havesib = 1; | |
0af10c86 | 1972 | code = cpu_ldub_code(env, s->pc++); |
2c0262af | 1973 | scale = (code >> 6) & 3; |
14ce26e7 FB |
1974 | index = ((code >> 3) & 7) | REX_X(s); |
1975 | base = (code & 7); | |
2c0262af | 1976 | } |
14ce26e7 | 1977 | base |= REX_B(s); |
2c0262af FB |
1978 | |
1979 | switch (mod) { | |
1980 | case 0: | |
14ce26e7 | 1981 | if ((base & 7) == 5) { |
2c0262af | 1982 | base = -1; |
0af10c86 | 1983 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af | 1984 | s->pc += 4; |
14ce26e7 FB |
1985 | if (CODE64(s) && !havesib) { |
1986 | disp += s->pc + s->rip_offset; | |
1987 | } | |
2c0262af FB |
1988 | } else { |
1989 | disp = 0; | |
1990 | } | |
1991 | break; | |
1992 | case 1: | |
0af10c86 | 1993 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
1994 | break; |
1995 | default: | |
1996 | case 2: | |
0af10c86 | 1997 | disp = (int32_t)cpu_ldl_code(env, s->pc); |
2c0262af FB |
1998 | s->pc += 4; |
1999 | break; | |
2000 | } | |
3b46e624 | 2001 | |
2c0262af FB |
2002 | if (base >= 0) { |
2003 | /* for correct popl handling with esp */ | |
2004 | if (base == 4 && s->popl_esp_hack) | |
2005 | disp += s->popl_esp_hack; | |
14ce26e7 FB |
2006 | #ifdef TARGET_X86_64 |
2007 | if (s->aflag == 2) { | |
57fec1fe | 2008 | gen_op_movq_A0_reg(base); |
14ce26e7 | 2009 | if (disp != 0) { |
57fec1fe | 2010 | gen_op_addq_A0_im(disp); |
14ce26e7 | 2011 | } |
5fafdf24 | 2012 | } else |
14ce26e7 FB |
2013 | #endif |
2014 | { | |
57fec1fe | 2015 | gen_op_movl_A0_reg(base); |
14ce26e7 FB |
2016 | if (disp != 0) |
2017 | gen_op_addl_A0_im(disp); | |
2018 | } | |
2c0262af | 2019 | } else { |
14ce26e7 FB |
2020 | #ifdef TARGET_X86_64 |
2021 | if (s->aflag == 2) { | |
57fec1fe | 2022 | gen_op_movq_A0_im(disp); |
5fafdf24 | 2023 | } else |
14ce26e7 FB |
2024 | #endif |
2025 | { | |
2026 | gen_op_movl_A0_im(disp); | |
2027 | } | |
2c0262af | 2028 | } |
b16f827b AJ |
2029 | /* index == 4 means no index */ |
2030 | if (havesib && (index != 4)) { | |
14ce26e7 FB |
2031 | #ifdef TARGET_X86_64 |
2032 | if (s->aflag == 2) { | |
57fec1fe | 2033 | gen_op_addq_A0_reg_sN(scale, index); |
5fafdf24 | 2034 | } else |
14ce26e7 FB |
2035 | #endif |
2036 | { | |
57fec1fe | 2037 | gen_op_addl_A0_reg_sN(scale, index); |
14ce26e7 | 2038 | } |
2c0262af FB |
2039 | } |
2040 | if (must_add_seg) { | |
2041 | if (override < 0) { | |
2042 | if (base == R_EBP || base == R_ESP) | |
2043 | override = R_SS; | |
2044 | else | |
2045 | override = R_DS; | |
2046 | } | |
14ce26e7 FB |
2047 | #ifdef TARGET_X86_64 |
2048 | if (s->aflag == 2) { | |
57fec1fe | 2049 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2050 | } else |
14ce26e7 FB |
2051 | #endif |
2052 | { | |
7162ab21 | 2053 | gen_op_addl_A0_seg(s, override); |
14ce26e7 | 2054 | } |
2c0262af FB |
2055 | } |
2056 | } else { | |
2057 | switch (mod) { | |
2058 | case 0: | |
2059 | if (rm == 6) { | |
0af10c86 | 2060 | disp = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2061 | s->pc += 2; |
2062 | gen_op_movl_A0_im(disp); | |
2063 | rm = 0; /* avoid SS override */ | |
2064 | goto no_rm; | |
2065 | } else { | |
2066 | disp = 0; | |
2067 | } | |
2068 | break; | |
2069 | case 1: | |
0af10c86 | 2070 | disp = (int8_t)cpu_ldub_code(env, s->pc++); |
2c0262af FB |
2071 | break; |
2072 | default: | |
2073 | case 2: | |
0af10c86 | 2074 | disp = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2075 | s->pc += 2; |
2076 | break; | |
2077 | } | |
2078 | switch(rm) { | |
2079 | case 0: | |
57fec1fe FB |
2080 | gen_op_movl_A0_reg(R_EBX); |
2081 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2082 | break; |
2083 | case 1: | |
57fec1fe FB |
2084 | gen_op_movl_A0_reg(R_EBX); |
2085 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2086 | break; |
2087 | case 2: | |
57fec1fe FB |
2088 | gen_op_movl_A0_reg(R_EBP); |
2089 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2090 | break; |
2091 | case 3: | |
57fec1fe FB |
2092 | gen_op_movl_A0_reg(R_EBP); |
2093 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2094 | break; |
2095 | case 4: | |
57fec1fe | 2096 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
2097 | break; |
2098 | case 5: | |
57fec1fe | 2099 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
2100 | break; |
2101 | case 6: | |
57fec1fe | 2102 | gen_op_movl_A0_reg(R_EBP); |
2c0262af FB |
2103 | break; |
2104 | default: | |
2105 | case 7: | |
57fec1fe | 2106 | gen_op_movl_A0_reg(R_EBX); |
2c0262af FB |
2107 | break; |
2108 | } | |
2109 | if (disp != 0) | |
2110 | gen_op_addl_A0_im(disp); | |
2111 | gen_op_andl_A0_ffff(); | |
2112 | no_rm: | |
2113 | if (must_add_seg) { | |
2114 | if (override < 0) { | |
2115 | if (rm == 2 || rm == 3 || rm == 6) | |
2116 | override = R_SS; | |
2117 | else | |
2118 | override = R_DS; | |
2119 | } | |
7162ab21 | 2120 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
2121 | } |
2122 | } | |
2123 | ||
2124 | opreg = OR_A0; | |
2125 | disp = 0; | |
2126 | *reg_ptr = opreg; | |
2127 | *offset_ptr = disp; | |
2128 | } | |
2129 | ||
0af10c86 | 2130 | static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) |
e17a36ce FB |
2131 | { |
2132 | int mod, rm, base, code; | |
2133 | ||
2134 | mod = (modrm >> 6) & 3; | |
2135 | if (mod == 3) | |
2136 | return; | |
2137 | rm = modrm & 7; | |
2138 | ||
2139 | if (s->aflag) { | |
2140 | ||
2141 | base = rm; | |
3b46e624 | 2142 | |
e17a36ce | 2143 | if (base == 4) { |
0af10c86 | 2144 | code = cpu_ldub_code(env, s->pc++); |
e17a36ce FB |
2145 | base = (code & 7); |
2146 | } | |
3b46e624 | 2147 | |
e17a36ce FB |
2148 | switch (mod) { |
2149 | case 0: | |
2150 | if (base == 5) { | |
2151 | s->pc += 4; | |
2152 | } | |
2153 | break; | |
2154 | case 1: | |
2155 | s->pc++; | |
2156 | break; | |
2157 | default: | |
2158 | case 2: | |
2159 | s->pc += 4; | |
2160 | break; | |
2161 | } | |
2162 | } else { | |
2163 | switch (mod) { | |
2164 | case 0: | |
2165 | if (rm == 6) { | |
2166 | s->pc += 2; | |
2167 | } | |
2168 | break; | |
2169 | case 1: | |
2170 | s->pc++; | |
2171 | break; | |
2172 | default: | |
2173 | case 2: | |
2174 | s->pc += 2; | |
2175 | break; | |
2176 | } | |
2177 | } | |
2178 | } | |
2179 | ||
664e0f19 FB |
2180 | /* used for LEA and MOV AX, mem */ |
2181 | static void gen_add_A0_ds_seg(DisasContext *s) | |
2182 | { | |
2183 | int override, must_add_seg; | |
2184 | must_add_seg = s->addseg; | |
2185 | override = R_DS; | |
2186 | if (s->override >= 0) { | |
2187 | override = s->override; | |
2188 | must_add_seg = 1; | |
664e0f19 FB |
2189 | } |
2190 | if (must_add_seg) { | |
8f091a59 FB |
2191 | #ifdef TARGET_X86_64 |
2192 | if (CODE64(s)) { | |
57fec1fe | 2193 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2194 | } else |
8f091a59 FB |
2195 | #endif |
2196 | { | |
7162ab21 | 2197 | gen_op_addl_A0_seg(s, override); |
8f091a59 | 2198 | } |
664e0f19 FB |
2199 | } |
2200 | } | |
2201 | ||
222a3336 | 2202 | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == |
2c0262af | 2203 | OR_TMP0 */ |
0af10c86 BS |
2204 | static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, |
2205 | int ot, int reg, int is_store) | |
2c0262af FB |
2206 | { |
2207 | int mod, rm, opreg, disp; | |
2208 | ||
2209 | mod = (modrm >> 6) & 3; | |
14ce26e7 | 2210 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
2211 | if (mod == 3) { |
2212 | if (is_store) { | |
2213 | if (reg != OR_TMP0) | |
57fec1fe FB |
2214 | gen_op_mov_TN_reg(ot, 0, reg); |
2215 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 2216 | } else { |
57fec1fe | 2217 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 2218 | if (reg != OR_TMP0) |
57fec1fe | 2219 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2220 | } |
2221 | } else { | |
0af10c86 | 2222 | gen_lea_modrm(env, s, modrm, &opreg, &disp); |
2c0262af FB |
2223 | if (is_store) { |
2224 | if (reg != OR_TMP0) | |
57fec1fe FB |
2225 | gen_op_mov_TN_reg(ot, 0, reg); |
2226 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 2227 | } else { |
57fec1fe | 2228 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 2229 | if (reg != OR_TMP0) |
57fec1fe | 2230 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2231 | } |
2232 | } | |
2233 | } | |
2234 | ||
0af10c86 | 2235 | static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot) |
2c0262af FB |
2236 | { |
2237 | uint32_t ret; | |
2238 | ||
2239 | switch(ot) { | |
2240 | case OT_BYTE: | |
0af10c86 | 2241 | ret = cpu_ldub_code(env, s->pc); |
2c0262af FB |
2242 | s->pc++; |
2243 | break; | |
2244 | case OT_WORD: | |
0af10c86 | 2245 | ret = cpu_lduw_code(env, s->pc); |
2c0262af FB |
2246 | s->pc += 2; |
2247 | break; | |
2248 | default: | |
2249 | case OT_LONG: | |
0af10c86 | 2250 | ret = cpu_ldl_code(env, s->pc); |
2c0262af FB |
2251 | s->pc += 4; |
2252 | break; | |
2253 | } | |
2254 | return ret; | |
2255 | } | |
2256 | ||
14ce26e7 FB |
2257 | static inline int insn_const_size(unsigned int ot) |
2258 | { | |
2259 | if (ot <= OT_LONG) | |
2260 | return 1 << ot; | |
2261 | else | |
2262 | return 4; | |
2263 | } | |
2264 | ||
6e256c93 FB |
2265 | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2266 | { | |
2267 | TranslationBlock *tb; | |
2268 | target_ulong pc; | |
2269 | ||
2270 | pc = s->cs_base + eip; | |
2271 | tb = s->tb; | |
2272 | /* NOTE: we handle the case where the TB spans two pages here */ | |
2273 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) || | |
2274 | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { | |
2275 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 2276 | tcg_gen_goto_tb(tb_num); |
6e256c93 | 2277 | gen_jmp_im(eip); |
4b4a72e5 | 2278 | tcg_gen_exit_tb((tcg_target_long)tb + tb_num); |
6e256c93 FB |
2279 | } else { |
2280 | /* jump to another page: currently not optimized */ | |
2281 | gen_jmp_im(eip); | |
2282 | gen_eob(s); | |
2283 | } | |
2284 | } | |
2285 | ||
5fafdf24 | 2286 | static inline void gen_jcc(DisasContext *s, int b, |
14ce26e7 | 2287 | target_ulong val, target_ulong next_eip) |
2c0262af | 2288 | { |
b27fc131 | 2289 | int l1, l2; |
3b46e624 | 2290 | |
b27fc131 PB |
2291 | if (s->cc_op != CC_OP_DYNAMIC) { |
2292 | gen_op_set_cc_op(s->cc_op); | |
2293 | } | |
2c0262af | 2294 | if (s->jmp_opt) { |
14ce26e7 | 2295 | l1 = gen_new_label(); |
b27fc131 | 2296 | gen_jcc1(s, b, l1); |
3ca51d07 | 2297 | set_cc_op(s, CC_OP_DYNAMIC); |
8e1c85e3 | 2298 | |
6e256c93 | 2299 | gen_goto_tb(s, 0, next_eip); |
14ce26e7 FB |
2300 | |
2301 | gen_set_label(l1); | |
6e256c93 | 2302 | gen_goto_tb(s, 1, val); |
5779406a | 2303 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2304 | } else { |
14ce26e7 | 2305 | |
14ce26e7 FB |
2306 | l1 = gen_new_label(); |
2307 | l2 = gen_new_label(); | |
b27fc131 | 2308 | gen_jcc1(s, b, l1); |
3ca51d07 | 2309 | set_cc_op(s, CC_OP_DYNAMIC); |
8e1c85e3 | 2310 | |
14ce26e7 | 2311 | gen_jmp_im(next_eip); |
8e1c85e3 FB |
2312 | tcg_gen_br(l2); |
2313 | ||
14ce26e7 FB |
2314 | gen_set_label(l1); |
2315 | gen_jmp_im(val); | |
2316 | gen_set_label(l2); | |
2c0262af FB |
2317 | gen_eob(s); |
2318 | } | |
2319 | } | |
2320 | ||
2321 | static void gen_setcc(DisasContext *s, int b) | |
2322 | { | |
8e1c85e3 | 2323 | int inv, jcc_op, l1; |
1e4840bf | 2324 | TCGv t0; |
14ce26e7 | 2325 | |
8e1c85e3 FB |
2326 | if (is_fast_jcc_case(s, b)) { |
2327 | /* nominal case: we use a jump */ | |
1e4840bf | 2328 | /* XXX: make it faster by adding new instructions in TCG */ |
a7812ae4 | 2329 | t0 = tcg_temp_local_new(); |
1e4840bf | 2330 | tcg_gen_movi_tl(t0, 0); |
8e1c85e3 | 2331 | l1 = gen_new_label(); |
b27fc131 | 2332 | gen_jcc1(s, b ^ 1, l1); |
1e4840bf | 2333 | tcg_gen_movi_tl(t0, 1); |
8e1c85e3 | 2334 | gen_set_label(l1); |
1e4840bf FB |
2335 | tcg_gen_mov_tl(cpu_T[0], t0); |
2336 | tcg_temp_free(t0); | |
8e1c85e3 FB |
2337 | } else { |
2338 | /* slow case: it is more efficient not to generate a jump, | |
2339 | although it is questionnable whether this optimization is | |
2340 | worth to */ | |
2341 | inv = b & 1; | |
2342 | jcc_op = (b >> 1) & 7; | |
1e4840bf | 2343 | gen_setcc_slow_T0(s, jcc_op); |
8e1c85e3 FB |
2344 | if (inv) { |
2345 | tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1); | |
2346 | } | |
2c0262af FB |
2347 | } |
2348 | } | |
2349 | ||
3bd7da9e FB |
2350 | static inline void gen_op_movl_T0_seg(int seg_reg) |
2351 | { | |
2352 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, | |
2353 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2354 | } | |
2355 | ||
2356 | static inline void gen_op_movl_seg_T0_vm(int seg_reg) | |
2357 | { | |
2358 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
2359 | tcg_gen_st32_tl(cpu_T[0], cpu_env, | |
2360 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2361 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); | |
2362 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
2363 | offsetof(CPUX86State,segs[seg_reg].base)); | |
2364 | } | |
2365 | ||
2c0262af FB |
2366 | /* move T0 to seg_reg and compute if the CPU state may change. Never |
2367 | call this function with seg_reg == R_CS */ | |
14ce26e7 | 2368 | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2c0262af | 2369 | { |
3415a4dd FB |
2370 | if (s->pe && !s->vm86) { |
2371 | /* XXX: optimize by finding processor state dynamically */ | |
2372 | if (s->cc_op != CC_OP_DYNAMIC) | |
2373 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2374 | gen_jmp_im(cur_eip); |
b6abf97d | 2375 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 2376 | gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32); |
dc196a57 FB |
2377 | /* abort translation because the addseg value may change or |
2378 | because ss32 may change. For R_SS, translation must always | |
2379 | stop as a special handling must be done to disable hardware | |
2380 | interrupts for the next instruction */ | |
2381 | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) | |
5779406a | 2382 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2383 | } else { |
3bd7da9e | 2384 | gen_op_movl_seg_T0_vm(seg_reg); |
dc196a57 | 2385 | if (seg_reg == R_SS) |
5779406a | 2386 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2387 | } |
2c0262af FB |
2388 | } |
2389 | ||
0573fbfc TS |
2390 | static inline int svm_is_rep(int prefixes) |
2391 | { | |
2392 | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); | |
2393 | } | |
2394 | ||
872929aa | 2395 | static inline void |
0573fbfc | 2396 | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
b8b6a50b | 2397 | uint32_t type, uint64_t param) |
0573fbfc | 2398 | { |
872929aa FB |
2399 | /* no SVM activated; fast case */ |
2400 | if (likely(!(s->flags & HF_SVMI_MASK))) | |
2401 | return; | |
2402 | if (s->cc_op != CC_OP_DYNAMIC) | |
2403 | gen_op_set_cc_op(s->cc_op); | |
2404 | gen_jmp_im(pc_start - s->cs_base); | |
052e80d5 | 2405 | gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), |
a7812ae4 | 2406 | tcg_const_i64(param)); |
0573fbfc TS |
2407 | } |
2408 | ||
872929aa | 2409 | static inline void |
0573fbfc TS |
2410 | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2411 | { | |
872929aa | 2412 | gen_svm_check_intercept_param(s, pc_start, type, 0); |
0573fbfc TS |
2413 | } |
2414 | ||
4f31916f FB |
2415 | static inline void gen_stack_update(DisasContext *s, int addend) |
2416 | { | |
14ce26e7 FB |
2417 | #ifdef TARGET_X86_64 |
2418 | if (CODE64(s)) { | |
6e0d8677 | 2419 | gen_op_add_reg_im(2, R_ESP, addend); |
14ce26e7 FB |
2420 | } else |
2421 | #endif | |
4f31916f | 2422 | if (s->ss32) { |
6e0d8677 | 2423 | gen_op_add_reg_im(1, R_ESP, addend); |
4f31916f | 2424 | } else { |
6e0d8677 | 2425 | gen_op_add_reg_im(0, R_ESP, addend); |
4f31916f FB |
2426 | } |
2427 | } | |
2428 | ||
2c0262af FB |
2429 | /* generate a push. It depends on ss32, addseg and dflag */ |
2430 | static void gen_push_T0(DisasContext *s) | |
2431 | { | |
14ce26e7 FB |
2432 | #ifdef TARGET_X86_64 |
2433 | if (CODE64(s)) { | |
57fec1fe | 2434 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2435 | if (s->dflag) { |
57fec1fe FB |
2436 | gen_op_addq_A0_im(-8); |
2437 | gen_op_st_T0_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2438 | } else { |
57fec1fe FB |
2439 | gen_op_addq_A0_im(-2); |
2440 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2441 | } |
57fec1fe | 2442 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2443 | } else |
14ce26e7 FB |
2444 | #endif |
2445 | { | |
57fec1fe | 2446 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2447 | if (!s->dflag) |
57fec1fe | 2448 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2449 | else |
57fec1fe | 2450 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2451 | if (s->ss32) { |
2452 | if (s->addseg) { | |
bbf662ee | 2453 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2454 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2455 | } |
2456 | } else { | |
2457 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2458 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2459 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2460 | } |
57fec1fe | 2461 | gen_op_st_T0_A0(s->dflag + 1 + s->mem_index); |
14ce26e7 | 2462 | if (s->ss32 && !s->addseg) |
57fec1fe | 2463 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 | 2464 | else |
57fec1fe | 2465 | gen_op_mov_reg_T1(s->ss32 + 1, R_ESP); |
2c0262af FB |
2466 | } |
2467 | } | |
2468 | ||
4f31916f FB |
2469 | /* generate a push. It depends on ss32, addseg and dflag */ |
2470 | /* slower version for T1, only used for call Ev */ | |
2471 | static void gen_push_T1(DisasContext *s) | |
2c0262af | 2472 | { |
14ce26e7 FB |
2473 | #ifdef TARGET_X86_64 |
2474 | if (CODE64(s)) { | |
57fec1fe | 2475 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2476 | if (s->dflag) { |
57fec1fe FB |
2477 | gen_op_addq_A0_im(-8); |
2478 | gen_op_st_T1_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2479 | } else { |
57fec1fe FB |
2480 | gen_op_addq_A0_im(-2); |
2481 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2482 | } |
57fec1fe | 2483 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2484 | } else |
14ce26e7 FB |
2485 | #endif |
2486 | { | |
57fec1fe | 2487 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2488 | if (!s->dflag) |
57fec1fe | 2489 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2490 | else |
57fec1fe | 2491 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2492 | if (s->ss32) { |
2493 | if (s->addseg) { | |
7162ab21 | 2494 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2495 | } |
2496 | } else { | |
2497 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2498 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2499 | } |
57fec1fe | 2500 | gen_op_st_T1_A0(s->dflag + 1 + s->mem_index); |
3b46e624 | 2501 | |
14ce26e7 | 2502 | if (s->ss32 && !s->addseg) |
57fec1fe | 2503 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 FB |
2504 | else |
2505 | gen_stack_update(s, (-2) << s->dflag); | |
2c0262af FB |
2506 | } |
2507 | } | |
2508 | ||
4f31916f FB |
2509 | /* two step pop is necessary for precise exceptions */ |
2510 | static void gen_pop_T0(DisasContext *s) | |
2c0262af | 2511 | { |
14ce26e7 FB |
2512 | #ifdef TARGET_X86_64 |
2513 | if (CODE64(s)) { | |
57fec1fe FB |
2514 | gen_op_movq_A0_reg(R_ESP); |
2515 | gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index); | |
5fafdf24 | 2516 | } else |
14ce26e7 FB |
2517 | #endif |
2518 | { | |
57fec1fe | 2519 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 FB |
2520 | if (s->ss32) { |
2521 | if (s->addseg) | |
7162ab21 | 2522 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2523 | } else { |
2524 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2525 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 | 2526 | } |
57fec1fe | 2527 | gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index); |
2c0262af FB |
2528 | } |
2529 | } | |
2530 | ||
2531 | static void gen_pop_update(DisasContext *s) | |
2532 | { | |
14ce26e7 | 2533 | #ifdef TARGET_X86_64 |
8f091a59 | 2534 | if (CODE64(s) && s->dflag) { |
14ce26e7 FB |
2535 | gen_stack_update(s, 8); |
2536 | } else | |
2537 | #endif | |
2538 | { | |
2539 | gen_stack_update(s, 2 << s->dflag); | |
2540 | } | |
2c0262af FB |
2541 | } |
2542 | ||
2543 | static void gen_stack_A0(DisasContext *s) | |
2544 | { | |
57fec1fe | 2545 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2546 | if (!s->ss32) |
2547 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2548 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2549 | if (s->addseg) |
7162ab21 | 2550 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2551 | } |
2552 | ||
2553 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2554 | static void gen_pusha(DisasContext *s) | |
2555 | { | |
2556 | int i; | |
57fec1fe | 2557 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2558 | gen_op_addl_A0_im(-16 << s->dflag); |
2559 | if (!s->ss32) | |
2560 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2561 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2562 | if (s->addseg) |
7162ab21 | 2563 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2564 | for(i = 0;i < 8; i++) { |
57fec1fe FB |
2565 | gen_op_mov_TN_reg(OT_LONG, 0, 7 - i); |
2566 | gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index); | |
2c0262af FB |
2567 | gen_op_addl_A0_im(2 << s->dflag); |
2568 | } | |
57fec1fe | 2569 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2570 | } |
2571 | ||
2572 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2573 | static void gen_popa(DisasContext *s) | |
2574 | { | |
2575 | int i; | |
57fec1fe | 2576 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2577 | if (!s->ss32) |
2578 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
2579 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2580 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); | |
2c0262af | 2581 | if (s->addseg) |
7162ab21 | 2582 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2583 | for(i = 0;i < 8; i++) { |
2584 | /* ESP is not reloaded */ | |
2585 | if (i != 3) { | |
57fec1fe FB |
2586 | gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2587 | gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i); | |
2c0262af FB |
2588 | } |
2589 | gen_op_addl_A0_im(2 << s->dflag); | |
2590 | } | |
57fec1fe | 2591 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2592 | } |
2593 | ||
2c0262af FB |
2594 | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2595 | { | |
61a8c4ec | 2596 | int ot, opsize; |
2c0262af | 2597 | |
2c0262af | 2598 | level &= 0x1f; |
8f091a59 FB |
2599 | #ifdef TARGET_X86_64 |
2600 | if (CODE64(s)) { | |
2601 | ot = s->dflag ? OT_QUAD : OT_WORD; | |
2602 | opsize = 1 << ot; | |
3b46e624 | 2603 | |
57fec1fe | 2604 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 | 2605 | gen_op_addq_A0_im(-opsize); |
bbf662ee | 2606 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 FB |
2607 | |
2608 | /* push bp */ | |
57fec1fe FB |
2609 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2610 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2611 | if (level) { |
b5b38f61 | 2612 | /* XXX: must save state */ |
2999a0b2 | 2613 | gen_helper_enter64_level(cpu_env, tcg_const_i32(level), |
a7812ae4 PB |
2614 | tcg_const_i32((ot == OT_QUAD)), |
2615 | cpu_T[1]); | |
8f091a59 | 2616 | } |
57fec1fe | 2617 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2618 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2619 | gen_op_mov_reg_T1(OT_QUAD, R_ESP); |
5fafdf24 | 2620 | } else |
8f091a59 FB |
2621 | #endif |
2622 | { | |
2623 | ot = s->dflag + OT_WORD; | |
2624 | opsize = 2 << s->dflag; | |
3b46e624 | 2625 | |
57fec1fe | 2626 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 FB |
2627 | gen_op_addl_A0_im(-opsize); |
2628 | if (!s->ss32) | |
2629 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2630 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 | 2631 | if (s->addseg) |
7162ab21 | 2632 | gen_op_addl_A0_seg(s, R_SS); |
8f091a59 | 2633 | /* push bp */ |
57fec1fe FB |
2634 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2635 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2636 | if (level) { |
b5b38f61 | 2637 | /* XXX: must save state */ |
2999a0b2 | 2638 | gen_helper_enter_level(cpu_env, tcg_const_i32(level), |
a7812ae4 PB |
2639 | tcg_const_i32(s->dflag), |
2640 | cpu_T[1]); | |
8f091a59 | 2641 | } |
57fec1fe | 2642 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2643 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2644 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af | 2645 | } |
2c0262af FB |
2646 | } |
2647 | ||
14ce26e7 | 2648 | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2c0262af FB |
2649 | { |
2650 | if (s->cc_op != CC_OP_DYNAMIC) | |
2651 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2652 | gen_jmp_im(cur_eip); |
77b2bc2c | 2653 | gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); |
5779406a | 2654 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2655 | } |
2656 | ||
2657 | /* an interrupt is different from an exception because of the | |
7f75ffd3 | 2658 | privilege checks */ |
5fafdf24 | 2659 | static void gen_interrupt(DisasContext *s, int intno, |
14ce26e7 | 2660 | target_ulong cur_eip, target_ulong next_eip) |
2c0262af FB |
2661 | { |
2662 | if (s->cc_op != CC_OP_DYNAMIC) | |
2663 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2664 | gen_jmp_im(cur_eip); |
77b2bc2c | 2665 | gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), |
a7812ae4 | 2666 | tcg_const_i32(next_eip - cur_eip)); |
5779406a | 2667 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2668 | } |
2669 | ||
14ce26e7 | 2670 | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2c0262af FB |
2671 | { |
2672 | if (s->cc_op != CC_OP_DYNAMIC) | |
2673 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2674 | gen_jmp_im(cur_eip); |
4a7443be | 2675 | gen_helper_debug(cpu_env); |
5779406a | 2676 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2677 | } |
2678 | ||
2679 | /* generate a generic end of block. Trace exception is also generated | |
2680 | if needed */ | |
2681 | static void gen_eob(DisasContext *s) | |
2682 | { | |
2683 | if (s->cc_op != CC_OP_DYNAMIC) | |
2684 | gen_op_set_cc_op(s->cc_op); | |
a2cc3b24 | 2685 | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { |
f0967a1a | 2686 | gen_helper_reset_inhibit_irq(cpu_env); |
a2cc3b24 | 2687 | } |
a2397807 | 2688 | if (s->tb->flags & HF_RF_MASK) { |
f0967a1a | 2689 | gen_helper_reset_rf(cpu_env); |
a2397807 | 2690 | } |
34865134 | 2691 | if (s->singlestep_enabled) { |
4a7443be | 2692 | gen_helper_debug(cpu_env); |
34865134 | 2693 | } else if (s->tf) { |
4a7443be | 2694 | gen_helper_single_step(cpu_env); |
2c0262af | 2695 | } else { |
57fec1fe | 2696 | tcg_gen_exit_tb(0); |
2c0262af | 2697 | } |
5779406a | 2698 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2699 | } |
2700 | ||
2701 | /* generate a jump to eip. No segment change must happen before as a | |
2702 | direct call to the next block may occur */ | |
14ce26e7 | 2703 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2c0262af | 2704 | { |
2c0262af | 2705 | if (s->jmp_opt) { |
728d803b | 2706 | gen_update_cc_op(s); |
6e256c93 | 2707 | gen_goto_tb(s, tb_num, eip); |
5779406a | 2708 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2709 | } else { |
14ce26e7 | 2710 | gen_jmp_im(eip); |
2c0262af FB |
2711 | gen_eob(s); |
2712 | } | |
2713 | } | |
2714 | ||
14ce26e7 FB |
2715 | static void gen_jmp(DisasContext *s, target_ulong eip) |
2716 | { | |
2717 | gen_jmp_tb(s, eip, 0); | |
2718 | } | |
2719 | ||
8686c490 FB |
2720 | static inline void gen_ldq_env_A0(int idx, int offset) |
2721 | { | |
2722 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2723 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2724 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); | |
8686c490 | 2725 | } |
664e0f19 | 2726 | |
8686c490 FB |
2727 | static inline void gen_stq_env_A0(int idx, int offset) |
2728 | { | |
2729 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2730 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
2731 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2732 | } |
664e0f19 | 2733 | |
8686c490 FB |
2734 | static inline void gen_ldo_env_A0(int idx, int offset) |
2735 | { | |
2736 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2737 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2738 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); | |
8686c490 | 2739 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2740 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2741 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); | |
8686c490 | 2742 | } |
14ce26e7 | 2743 | |
8686c490 FB |
2744 | static inline void gen_sto_env_A0(int idx, int offset) |
2745 | { | |
2746 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2747 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
2748 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2749 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2750 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
2751 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index); | |
8686c490 | 2752 | } |
14ce26e7 | 2753 | |
5af45186 FB |
2754 | static inline void gen_op_movo(int d_offset, int s_offset) |
2755 | { | |
b6abf97d FB |
2756 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2757 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
2758 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8); | |
2759 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8); | |
5af45186 FB |
2760 | } |
2761 | ||
2762 | static inline void gen_op_movq(int d_offset, int s_offset) | |
2763 | { | |
b6abf97d FB |
2764 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2765 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 FB |
2766 | } |
2767 | ||
2768 | static inline void gen_op_movl(int d_offset, int s_offset) | |
2769 | { | |
b6abf97d FB |
2770 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2771 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); | |
5af45186 FB |
2772 | } |
2773 | ||
2774 | static inline void gen_op_movq_env_0(int d_offset) | |
2775 | { | |
b6abf97d FB |
2776 | tcg_gen_movi_i64(cpu_tmp1_i64, 0); |
2777 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 | 2778 | } |
664e0f19 | 2779 | |
d3eb5eae BS |
2780 | typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg); |
2781 | typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg); | |
2782 | typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val); | |
2783 | typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val); | |
2784 | typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b); | |
2785 | typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, | |
2786 | TCGv_i32 val); | |
c4baa050 | 2787 | typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val); |
d3eb5eae BS |
2788 | typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, |
2789 | TCGv val); | |
c4baa050 | 2790 | |
5af45186 FB |
2791 | #define SSE_SPECIAL ((void *)1) |
2792 | #define SSE_DUMMY ((void *)2) | |
664e0f19 | 2793 | |
a7812ae4 PB |
2794 | #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } |
2795 | #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ | |
2796 | gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } | |
5af45186 | 2797 | |
d3eb5eae | 2798 | static const SSEFunc_0_epp sse_op_table1[256][4] = { |
a35f3ec7 AJ |
2799 | /* 3DNow! extensions */ |
2800 | [0x0e] = { SSE_DUMMY }, /* femms */ | |
2801 | [0x0f] = { SSE_DUMMY }, /* pf... */ | |
664e0f19 FB |
2802 | /* pure SSE operations */ |
2803 | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
2804 | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
465e9838 | 2805 | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
664e0f19 | 2806 | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
a7812ae4 PB |
2807 | [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, |
2808 | [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2809 | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2810 | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ | |
2811 | ||
2812 | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2813 | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2814 | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ | |
d9f4bb27 | 2815 | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ |
664e0f19 FB |
2816 | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ |
2817 | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ | |
a7812ae4 PB |
2818 | [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, |
2819 | [0x2f] = { gen_helper_comiss, gen_helper_comisd }, | |
664e0f19 FB |
2820 | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2821 | [0x51] = SSE_FOP(sqrt), | |
a7812ae4 PB |
2822 | [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, |
2823 | [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, | |
2824 | [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ | |
2825 | [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ | |
2826 | [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ | |
2827 | [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ | |
664e0f19 FB |
2828 | [0x58] = SSE_FOP(add), |
2829 | [0x59] = SSE_FOP(mul), | |
a7812ae4 PB |
2830 | [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, |
2831 | gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, | |
2832 | [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, | |
664e0f19 FB |
2833 | [0x5c] = SSE_FOP(sub), |
2834 | [0x5d] = SSE_FOP(min), | |
2835 | [0x5e] = SSE_FOP(div), | |
2836 | [0x5f] = SSE_FOP(max), | |
2837 | ||
2838 | [0xc2] = SSE_FOP(cmpeq), | |
d3eb5eae BS |
2839 | [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps, |
2840 | (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ | |
664e0f19 | 2841 | |
222a3336 AZ |
2842 | [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */ |
2843 | [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */ | |
4242b1bd | 2844 | |
664e0f19 FB |
2845 | /* MMX ops and their SSE extensions */ |
2846 | [0x60] = MMX_OP2(punpcklbw), | |
2847 | [0x61] = MMX_OP2(punpcklwd), | |
2848 | [0x62] = MMX_OP2(punpckldq), | |
2849 | [0x63] = MMX_OP2(packsswb), | |
2850 | [0x64] = MMX_OP2(pcmpgtb), | |
2851 | [0x65] = MMX_OP2(pcmpgtw), | |
2852 | [0x66] = MMX_OP2(pcmpgtl), | |
2853 | [0x67] = MMX_OP2(packuswb), | |
2854 | [0x68] = MMX_OP2(punpckhbw), | |
2855 | [0x69] = MMX_OP2(punpckhwd), | |
2856 | [0x6a] = MMX_OP2(punpckhdq), | |
2857 | [0x6b] = MMX_OP2(packssdw), | |
a7812ae4 PB |
2858 | [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, |
2859 | [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2860 | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2861 | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ | |
d3eb5eae BS |
2862 | [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx, |
2863 | (SSEFunc_0_epp)gen_helper_pshufd_xmm, | |
2864 | (SSEFunc_0_epp)gen_helper_pshufhw_xmm, | |
2865 | (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2866 | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2867 | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ | |
2868 | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ | |
2869 | [0x74] = MMX_OP2(pcmpeqb), | |
2870 | [0x75] = MMX_OP2(pcmpeqw), | |
2871 | [0x76] = MMX_OP2(pcmpeql), | |
a35f3ec7 | 2872 | [0x77] = { SSE_DUMMY }, /* emms */ |
d9f4bb27 AP |
2873 | [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ |
2874 | [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, | |
a7812ae4 PB |
2875 | [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, |
2876 | [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, | |
664e0f19 FB |
2877 | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2878 | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ | |
2879 | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ | |
2880 | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ | |
a7812ae4 | 2881 | [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, |
664e0f19 FB |
2882 | [0xd1] = MMX_OP2(psrlw), |
2883 | [0xd2] = MMX_OP2(psrld), | |
2884 | [0xd3] = MMX_OP2(psrlq), | |
2885 | [0xd4] = MMX_OP2(paddq), | |
2886 | [0xd5] = MMX_OP2(pmullw), | |
2887 | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2888 | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ | |
2889 | [0xd8] = MMX_OP2(psubusb), | |
2890 | [0xd9] = MMX_OP2(psubusw), | |
2891 | [0xda] = MMX_OP2(pminub), | |
2892 | [0xdb] = MMX_OP2(pand), | |
2893 | [0xdc] = MMX_OP2(paddusb), | |
2894 | [0xdd] = MMX_OP2(paddusw), | |
2895 | [0xde] = MMX_OP2(pmaxub), | |
2896 | [0xdf] = MMX_OP2(pandn), | |
2897 | [0xe0] = MMX_OP2(pavgb), | |
2898 | [0xe1] = MMX_OP2(psraw), | |
2899 | [0xe2] = MMX_OP2(psrad), | |
2900 | [0xe3] = MMX_OP2(pavgw), | |
2901 | [0xe4] = MMX_OP2(pmulhuw), | |
2902 | [0xe5] = MMX_OP2(pmulhw), | |
a7812ae4 | 2903 | [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, |
664e0f19 FB |
2904 | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
2905 | [0xe8] = MMX_OP2(psubsb), | |
2906 | [0xe9] = MMX_OP2(psubsw), | |
2907 | [0xea] = MMX_OP2(pminsw), | |
2908 | [0xeb] = MMX_OP2(por), | |
2909 | [0xec] = MMX_OP2(paddsb), | |
2910 | [0xed] = MMX_OP2(paddsw), | |
2911 | [0xee] = MMX_OP2(pmaxsw), | |
2912 | [0xef] = MMX_OP2(pxor), | |
465e9838 | 2913 | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
664e0f19 FB |
2914 | [0xf1] = MMX_OP2(psllw), |
2915 | [0xf2] = MMX_OP2(pslld), | |
2916 | [0xf3] = MMX_OP2(psllq), | |
2917 | [0xf4] = MMX_OP2(pmuludq), | |
2918 | [0xf5] = MMX_OP2(pmaddwd), | |
2919 | [0xf6] = MMX_OP2(psadbw), | |
d3eb5eae BS |
2920 | [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx, |
2921 | (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2922 | [0xf8] = MMX_OP2(psubb), |
2923 | [0xf9] = MMX_OP2(psubw), | |
2924 | [0xfa] = MMX_OP2(psubl), | |
2925 | [0xfb] = MMX_OP2(psubq), | |
2926 | [0xfc] = MMX_OP2(paddb), | |
2927 | [0xfd] = MMX_OP2(paddw), | |
2928 | [0xfe] = MMX_OP2(paddl), | |
2929 | }; | |
2930 | ||
d3eb5eae | 2931 | static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = { |
664e0f19 FB |
2932 | [0 + 2] = MMX_OP2(psrlw), |
2933 | [0 + 4] = MMX_OP2(psraw), | |
2934 | [0 + 6] = MMX_OP2(psllw), | |
2935 | [8 + 2] = MMX_OP2(psrld), | |
2936 | [8 + 4] = MMX_OP2(psrad), | |
2937 | [8 + 6] = MMX_OP2(pslld), | |
2938 | [16 + 2] = MMX_OP2(psrlq), | |
a7812ae4 | 2939 | [16 + 3] = { NULL, gen_helper_psrldq_xmm }, |
664e0f19 | 2940 | [16 + 6] = MMX_OP2(psllq), |
a7812ae4 | 2941 | [16 + 7] = { NULL, gen_helper_pslldq_xmm }, |
664e0f19 FB |
2942 | }; |
2943 | ||
d3eb5eae | 2944 | static const SSEFunc_0_epi sse_op_table3ai[] = { |
a7812ae4 | 2945 | gen_helper_cvtsi2ss, |
11f8cdbc | 2946 | gen_helper_cvtsi2sd |
c4baa050 | 2947 | }; |
a7812ae4 | 2948 | |
11f8cdbc | 2949 | #ifdef TARGET_X86_64 |
d3eb5eae | 2950 | static const SSEFunc_0_epl sse_op_table3aq[] = { |
11f8cdbc SW |
2951 | gen_helper_cvtsq2ss, |
2952 | gen_helper_cvtsq2sd | |
2953 | }; | |
2954 | #endif | |
2955 | ||
d3eb5eae | 2956 | static const SSEFunc_i_ep sse_op_table3bi[] = { |
a7812ae4 | 2957 | gen_helper_cvttss2si, |
a7812ae4 | 2958 | gen_helper_cvtss2si, |
bedc2ac1 | 2959 | gen_helper_cvttsd2si, |
11f8cdbc | 2960 | gen_helper_cvtsd2si |
664e0f19 | 2961 | }; |
3b46e624 | 2962 | |
11f8cdbc | 2963 | #ifdef TARGET_X86_64 |
d3eb5eae | 2964 | static const SSEFunc_l_ep sse_op_table3bq[] = { |
11f8cdbc | 2965 | gen_helper_cvttss2sq, |
11f8cdbc | 2966 | gen_helper_cvtss2sq, |
bedc2ac1 | 2967 | gen_helper_cvttsd2sq, |
11f8cdbc SW |
2968 | gen_helper_cvtsd2sq |
2969 | }; | |
2970 | #endif | |
2971 | ||
d3eb5eae | 2972 | static const SSEFunc_0_epp sse_op_table4[8][4] = { |
664e0f19 FB |
2973 | SSE_FOP(cmpeq), |
2974 | SSE_FOP(cmplt), | |
2975 | SSE_FOP(cmple), | |
2976 | SSE_FOP(cmpunord), | |
2977 | SSE_FOP(cmpneq), | |
2978 | SSE_FOP(cmpnlt), | |
2979 | SSE_FOP(cmpnle), | |
2980 | SSE_FOP(cmpord), | |
2981 | }; | |
3b46e624 | 2982 | |
d3eb5eae | 2983 | static const SSEFunc_0_epp sse_op_table5[256] = { |
a7812ae4 PB |
2984 | [0x0c] = gen_helper_pi2fw, |
2985 | [0x0d] = gen_helper_pi2fd, | |
2986 | [0x1c] = gen_helper_pf2iw, | |
2987 | [0x1d] = gen_helper_pf2id, | |
2988 | [0x8a] = gen_helper_pfnacc, | |
2989 | [0x8e] = gen_helper_pfpnacc, | |
2990 | [0x90] = gen_helper_pfcmpge, | |
2991 | [0x94] = gen_helper_pfmin, | |
2992 | [0x96] = gen_helper_pfrcp, | |
2993 | [0x97] = gen_helper_pfrsqrt, | |
2994 | [0x9a] = gen_helper_pfsub, | |
2995 | [0x9e] = gen_helper_pfadd, | |
2996 | [0xa0] = gen_helper_pfcmpgt, | |
2997 | [0xa4] = gen_helper_pfmax, | |
2998 | [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ | |
2999 | [0xa7] = gen_helper_movq, /* pfrsqit1 */ | |
3000 | [0xaa] = gen_helper_pfsubr, | |
3001 | [0xae] = gen_helper_pfacc, | |
3002 | [0xb0] = gen_helper_pfcmpeq, | |
3003 | [0xb4] = gen_helper_pfmul, | |
3004 | [0xb6] = gen_helper_movq, /* pfrcpit2 */ | |
3005 | [0xb7] = gen_helper_pmulhrw_mmx, | |
3006 | [0xbb] = gen_helper_pswapd, | |
3007 | [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ | |
a35f3ec7 AJ |
3008 | }; |
3009 | ||
d3eb5eae BS |
3010 | struct SSEOpHelper_epp { |
3011 | SSEFunc_0_epp op[2]; | |
c4baa050 BS |
3012 | uint32_t ext_mask; |
3013 | }; | |
3014 | ||
d3eb5eae BS |
3015 | struct SSEOpHelper_eppi { |
3016 | SSEFunc_0_eppi op[2]; | |
c4baa050 | 3017 | uint32_t ext_mask; |
222a3336 | 3018 | }; |
c4baa050 | 3019 | |
222a3336 | 3020 | #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 } |
a7812ae4 PB |
3021 | #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } |
3022 | #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } | |
222a3336 | 3023 | #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } |
c4baa050 | 3024 | |
d3eb5eae | 3025 | static const struct SSEOpHelper_epp sse_op_table6[256] = { |
222a3336 AZ |
3026 | [0x00] = SSSE3_OP(pshufb), |
3027 | [0x01] = SSSE3_OP(phaddw), | |
3028 | [0x02] = SSSE3_OP(phaddd), | |
3029 | [0x03] = SSSE3_OP(phaddsw), | |
3030 | [0x04] = SSSE3_OP(pmaddubsw), | |
3031 | [0x05] = SSSE3_OP(phsubw), | |
3032 | [0x06] = SSSE3_OP(phsubd), | |
3033 | [0x07] = SSSE3_OP(phsubsw), | |
3034 | [0x08] = SSSE3_OP(psignb), | |
3035 | [0x09] = SSSE3_OP(psignw), | |
3036 | [0x0a] = SSSE3_OP(psignd), | |
3037 | [0x0b] = SSSE3_OP(pmulhrsw), | |
3038 | [0x10] = SSE41_OP(pblendvb), | |
3039 | [0x14] = SSE41_OP(blendvps), | |
3040 | [0x15] = SSE41_OP(blendvpd), | |
3041 | [0x17] = SSE41_OP(ptest), | |
3042 | [0x1c] = SSSE3_OP(pabsb), | |
3043 | [0x1d] = SSSE3_OP(pabsw), | |
3044 | [0x1e] = SSSE3_OP(pabsd), | |
3045 | [0x20] = SSE41_OP(pmovsxbw), | |
3046 | [0x21] = SSE41_OP(pmovsxbd), | |
3047 | [0x22] = SSE41_OP(pmovsxbq), | |
3048 | [0x23] = SSE41_OP(pmovsxwd), | |
3049 | [0x24] = SSE41_OP(pmovsxwq), | |
3050 | [0x25] = SSE41_OP(pmovsxdq), | |
3051 | [0x28] = SSE41_OP(pmuldq), | |
3052 | [0x29] = SSE41_OP(pcmpeqq), | |
3053 | [0x2a] = SSE41_SPECIAL, /* movntqda */ | |
3054 | [0x2b] = SSE41_OP(packusdw), | |
3055 | [0x30] = SSE41_OP(pmovzxbw), | |
3056 | [0x31] = SSE41_OP(pmovzxbd), | |
3057 | [0x32] = SSE41_OP(pmovzxbq), | |
3058 | [0x33] = SSE41_OP(pmovzxwd), | |
3059 | [0x34] = SSE41_OP(pmovzxwq), | |
3060 | [0x35] = SSE41_OP(pmovzxdq), | |
3061 | [0x37] = SSE42_OP(pcmpgtq), | |
3062 | [0x38] = SSE41_OP(pminsb), | |
3063 | [0x39] = SSE41_OP(pminsd), | |
3064 | [0x3a] = SSE41_OP(pminuw), | |
3065 | [0x3b] = SSE41_OP(pminud), | |
3066 | [0x3c] = SSE41_OP(pmaxsb), | |
3067 | [0x3d] = SSE41_OP(pmaxsd), | |
3068 | [0x3e] = SSE41_OP(pmaxuw), | |
3069 | [0x3f] = SSE41_OP(pmaxud), | |
3070 | [0x40] = SSE41_OP(pmulld), | |
3071 | [0x41] = SSE41_OP(phminposuw), | |
4242b1bd AZ |
3072 | }; |
3073 | ||
d3eb5eae | 3074 | static const struct SSEOpHelper_eppi sse_op_table7[256] = { |
222a3336 AZ |
3075 | [0x08] = SSE41_OP(roundps), |
3076 | [0x09] = SSE41_OP(roundpd), | |
3077 | [0x0a] = SSE41_OP(roundss), | |
3078 | [0x0b] = SSE41_OP(roundsd), | |
3079 | [0x0c] = SSE41_OP(blendps), | |
3080 | [0x0d] = SSE41_OP(blendpd), | |
3081 | [0x0e] = SSE41_OP(pblendw), | |
3082 | [0x0f] = SSSE3_OP(palignr), | |
3083 | [0x14] = SSE41_SPECIAL, /* pextrb */ | |
3084 | [0x15] = SSE41_SPECIAL, /* pextrw */ | |
3085 | [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ | |
3086 | [0x17] = SSE41_SPECIAL, /* extractps */ | |
3087 | [0x20] = SSE41_SPECIAL, /* pinsrb */ | |
3088 | [0x21] = SSE41_SPECIAL, /* insertps */ | |
3089 | [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ | |
3090 | [0x40] = SSE41_OP(dpps), | |
3091 | [0x41] = SSE41_OP(dppd), | |
3092 | [0x42] = SSE41_OP(mpsadbw), | |
3093 | [0x60] = SSE42_OP(pcmpestrm), | |
3094 | [0x61] = SSE42_OP(pcmpestri), | |
3095 | [0x62] = SSE42_OP(pcmpistrm), | |
3096 | [0x63] = SSE42_OP(pcmpistri), | |
4242b1bd AZ |
3097 | }; |
3098 | ||
0af10c86 BS |
3099 | static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
3100 | target_ulong pc_start, int rex_r) | |
664e0f19 FB |
3101 | { |
3102 | int b1, op1_offset, op2_offset, is_xmm, val, ot; | |
3103 | int modrm, mod, rm, reg, reg_addr, offset_addr; | |
d3eb5eae BS |
3104 | SSEFunc_0_epp sse_fn_epp; |
3105 | SSEFunc_0_eppi sse_fn_eppi; | |
c4baa050 | 3106 | SSEFunc_0_ppi sse_fn_ppi; |
d3eb5eae | 3107 | SSEFunc_0_eppt sse_fn_eppt; |
664e0f19 FB |
3108 | |
3109 | b &= 0xff; | |
5fafdf24 | 3110 | if (s->prefix & PREFIX_DATA) |
664e0f19 | 3111 | b1 = 1; |
5fafdf24 | 3112 | else if (s->prefix & PREFIX_REPZ) |
664e0f19 | 3113 | b1 = 2; |
5fafdf24 | 3114 | else if (s->prefix & PREFIX_REPNZ) |
664e0f19 FB |
3115 | b1 = 3; |
3116 | else | |
3117 | b1 = 0; | |
d3eb5eae BS |
3118 | sse_fn_epp = sse_op_table1[b][b1]; |
3119 | if (!sse_fn_epp) { | |
664e0f19 | 3120 | goto illegal_op; |
c4baa050 | 3121 | } |
a35f3ec7 | 3122 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
664e0f19 FB |
3123 | is_xmm = 1; |
3124 | } else { | |
3125 | if (b1 == 0) { | |
3126 | /* MMX case */ | |
3127 | is_xmm = 0; | |
3128 | } else { | |
3129 | is_xmm = 1; | |
3130 | } | |
3131 | } | |
3132 | /* simple MMX/SSE operation */ | |
3133 | if (s->flags & HF_TS_MASK) { | |
3134 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
3135 | return; | |
3136 | } | |
3137 | if (s->flags & HF_EM_MASK) { | |
3138 | illegal_op: | |
3139 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
3140 | return; | |
3141 | } | |
3142 | if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) | |
4242b1bd AZ |
3143 | if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) |
3144 | goto illegal_op; | |
e771edab AJ |
3145 | if (b == 0x0e) { |
3146 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) | |
3147 | goto illegal_op; | |
3148 | /* femms */ | |
d3eb5eae | 3149 | gen_helper_emms(cpu_env); |
e771edab AJ |
3150 | return; |
3151 | } | |
3152 | if (b == 0x77) { | |
3153 | /* emms */ | |
d3eb5eae | 3154 | gen_helper_emms(cpu_env); |
664e0f19 FB |
3155 | return; |
3156 | } | |
3157 | /* prepare MMX state (XXX: optimize by storing fptt and fptags in | |
3158 | the static cpu state) */ | |
3159 | if (!is_xmm) { | |
d3eb5eae | 3160 | gen_helper_enter_mmx(cpu_env); |
664e0f19 FB |
3161 | } |
3162 | ||
0af10c86 | 3163 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3164 | reg = ((modrm >> 3) & 7); |
3165 | if (is_xmm) | |
3166 | reg |= rex_r; | |
3167 | mod = (modrm >> 6) & 3; | |
d3eb5eae | 3168 | if (sse_fn_epp == SSE_SPECIAL) { |
664e0f19 FB |
3169 | b |= (b1 << 8); |
3170 | switch(b) { | |
3171 | case 0x0e7: /* movntq */ | |
5fafdf24 | 3172 | if (mod == 3) |
664e0f19 | 3173 | goto illegal_op; |
0af10c86 | 3174 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3175 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3176 | break; |
3177 | case 0x1e7: /* movntdq */ | |
3178 | case 0x02b: /* movntps */ | |
3179 | case 0x12b: /* movntps */ | |
2e21e749 T |
3180 | if (mod == 3) |
3181 | goto illegal_op; | |
0af10c86 | 3182 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2e21e749 T |
3183 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
3184 | break; | |
465e9838 FB |
3185 | case 0x3f0: /* lddqu */ |
3186 | if (mod == 3) | |
664e0f19 | 3187 | goto illegal_op; |
0af10c86 | 3188 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
c2254920 | 3189 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 | 3190 | break; |
d9f4bb27 AP |
3191 | case 0x22b: /* movntss */ |
3192 | case 0x32b: /* movntsd */ | |
3193 | if (mod == 3) | |
3194 | goto illegal_op; | |
0af10c86 | 3195 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
d9f4bb27 AP |
3196 | if (b1 & 1) { |
3197 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State, | |
3198 | xmm_regs[reg])); | |
3199 | } else { | |
3200 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3201 | xmm_regs[reg].XMM_L(0))); | |
3202 | gen_op_st_T0_A0(OT_LONG + s->mem_index); | |
3203 | } | |
3204 | break; | |
664e0f19 | 3205 | case 0x6e: /* movd mm, ea */ |
dabd98dd FB |
3206 | #ifdef TARGET_X86_64 |
3207 | if (s->dflag == 2) { | |
0af10c86 | 3208 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0); |
5af45186 | 3209 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); |
5fafdf24 | 3210 | } else |
dabd98dd FB |
3211 | #endif |
3212 | { | |
0af10c86 | 3213 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0); |
5af45186 FB |
3214 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3215 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
a7812ae4 PB |
3216 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3217 | gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); | |
dabd98dd | 3218 | } |
664e0f19 FB |
3219 | break; |
3220 | case 0x16e: /* movd xmm, ea */ | |
dabd98dd FB |
3221 | #ifdef TARGET_X86_64 |
3222 | if (s->dflag == 2) { | |
0af10c86 | 3223 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0); |
5af45186 FB |
3224 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3225 | offsetof(CPUX86State,xmm_regs[reg])); | |
a7812ae4 | 3226 | gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); |
5fafdf24 | 3227 | } else |
dabd98dd FB |
3228 | #endif |
3229 | { | |
0af10c86 | 3230 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0); |
5af45186 FB |
3231 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3232 | offsetof(CPUX86State,xmm_regs[reg])); | |
b6abf97d | 3233 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 3234 | gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); |
dabd98dd | 3235 | } |
664e0f19 FB |
3236 | break; |
3237 | case 0x6f: /* movq mm, ea */ | |
3238 | if (mod != 3) { | |
0af10c86 | 3239 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3240 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3241 | } else { |
3242 | rm = (modrm & 7); | |
b6abf97d | 3243 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3244 | offsetof(CPUX86State,fpregs[rm].mmx)); |
b6abf97d | 3245 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3246 | offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3247 | } |
3248 | break; | |
3249 | case 0x010: /* movups */ | |
3250 | case 0x110: /* movupd */ | |
3251 | case 0x028: /* movaps */ | |
3252 | case 0x128: /* movapd */ | |
3253 | case 0x16f: /* movdqa xmm, ea */ | |
3254 | case 0x26f: /* movdqu xmm, ea */ | |
3255 | if (mod != 3) { | |
0af10c86 | 3256 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3257 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3258 | } else { |
3259 | rm = (modrm & 7) | REX_B(s); | |
3260 | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), | |
3261 | offsetof(CPUX86State,xmm_regs[rm])); | |
3262 | } | |
3263 | break; | |
3264 | case 0x210: /* movss xmm, ea */ | |
3265 | if (mod != 3) { | |
0af10c86 | 3266 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 3267 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3268 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
664e0f19 | 3269 | gen_op_movl_T0_0(); |
651ba608 FB |
3270 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); |
3271 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3272 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3273 | } else { |
3274 | rm = (modrm & 7) | REX_B(s); | |
3275 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3276 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3277 | } | |
3278 | break; | |
3279 | case 0x310: /* movsd xmm, ea */ | |
3280 | if (mod != 3) { | |
0af10c86 | 3281 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3282 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 | 3283 | gen_op_movl_T0_0(); |
651ba608 FB |
3284 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3285 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3286 | } else { |
3287 | rm = (modrm & 7) | REX_B(s); | |
3288 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3289 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3290 | } | |
3291 | break; | |
3292 | case 0x012: /* movlps */ | |
3293 | case 0x112: /* movlpd */ | |
3294 | if (mod != 3) { | |
0af10c86 | 3295 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3296 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3297 | } else { |
3298 | /* movhlps */ | |
3299 | rm = (modrm & 7) | REX_B(s); | |
3300 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3301 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3302 | } | |
3303 | break; | |
465e9838 FB |
3304 | case 0x212: /* movsldup */ |
3305 | if (mod != 3) { | |
0af10c86 | 3306 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3307 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
465e9838 FB |
3308 | } else { |
3309 | rm = (modrm & 7) | REX_B(s); | |
3310 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3311 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3312 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3313 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); | |
3314 | } | |
3315 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3316 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3317 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3318 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3319 | break; | |
3320 | case 0x312: /* movddup */ | |
3321 | if (mod != 3) { | |
0af10c86 | 3322 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3323 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 FB |
3324 | } else { |
3325 | rm = (modrm & 7) | REX_B(s); | |
3326 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3327 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3328 | } | |
3329 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
ba6526df | 3330 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 | 3331 | break; |
664e0f19 FB |
3332 | case 0x016: /* movhps */ |
3333 | case 0x116: /* movhpd */ | |
3334 | if (mod != 3) { | |
0af10c86 | 3335 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3336 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3337 | } else { |
3338 | /* movlhps */ | |
3339 | rm = (modrm & 7) | REX_B(s); | |
3340 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
3341 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3342 | } | |
3343 | break; | |
3344 | case 0x216: /* movshdup */ | |
3345 | if (mod != 3) { | |
0af10c86 | 3346 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3347 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3348 | } else { |
3349 | rm = (modrm & 7) | REX_B(s); | |
3350 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3351 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); | |
3352 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3353 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); | |
3354 | } | |
3355 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3356 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); | |
3357 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3358 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
3359 | break; | |
d9f4bb27 AP |
3360 | case 0x178: |
3361 | case 0x378: | |
3362 | { | |
3363 | int bit_index, field_length; | |
3364 | ||
3365 | if (b1 == 1 && reg != 0) | |
3366 | goto illegal_op; | |
0af10c86 BS |
3367 | field_length = cpu_ldub_code(env, s->pc++) & 0x3F; |
3368 | bit_index = cpu_ldub_code(env, s->pc++) & 0x3F; | |
d9f4bb27 AP |
3369 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3370 | offsetof(CPUX86State,xmm_regs[reg])); | |
3371 | if (b1 == 1) | |
d3eb5eae BS |
3372 | gen_helper_extrq_i(cpu_env, cpu_ptr0, |
3373 | tcg_const_i32(bit_index), | |
3374 | tcg_const_i32(field_length)); | |
d9f4bb27 | 3375 | else |
d3eb5eae BS |
3376 | gen_helper_insertq_i(cpu_env, cpu_ptr0, |
3377 | tcg_const_i32(bit_index), | |
3378 | tcg_const_i32(field_length)); | |
d9f4bb27 AP |
3379 | } |
3380 | break; | |
664e0f19 | 3381 | case 0x7e: /* movd ea, mm */ |
dabd98dd FB |
3382 | #ifdef TARGET_X86_64 |
3383 | if (s->dflag == 2) { | |
5af45186 FB |
3384 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3385 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
0af10c86 | 3386 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3387 | } else |
dabd98dd FB |
3388 | #endif |
3389 | { | |
5af45186 FB |
3390 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3391 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); | |
0af10c86 | 3392 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1); |
dabd98dd | 3393 | } |
664e0f19 FB |
3394 | break; |
3395 | case 0x17e: /* movd ea, xmm */ | |
dabd98dd FB |
3396 | #ifdef TARGET_X86_64 |
3397 | if (s->dflag == 2) { | |
5af45186 FB |
3398 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3399 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
0af10c86 | 3400 | gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3401 | } else |
dabd98dd FB |
3402 | #endif |
3403 | { | |
5af45186 FB |
3404 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3405 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
0af10c86 | 3406 | gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1); |
dabd98dd | 3407 | } |
664e0f19 FB |
3408 | break; |
3409 | case 0x27e: /* movq xmm, ea */ | |
3410 | if (mod != 3) { | |
0af10c86 | 3411 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3412 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3413 | } else { |
3414 | rm = (modrm & 7) | REX_B(s); | |
3415 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3416 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3417 | } | |
3418 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
3419 | break; | |
3420 | case 0x7f: /* movq ea, mm */ | |
3421 | if (mod != 3) { | |
0af10c86 | 3422 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3423 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3424 | } else { |
3425 | rm = (modrm & 7); | |
3426 | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), | |
3427 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
3428 | } | |
3429 | break; | |
3430 | case 0x011: /* movups */ | |
3431 | case 0x111: /* movupd */ | |
3432 | case 0x029: /* movaps */ | |
3433 | case 0x129: /* movapd */ | |
3434 | case 0x17f: /* movdqa ea, xmm */ | |
3435 | case 0x27f: /* movdqu ea, xmm */ | |
3436 | if (mod != 3) { | |
0af10c86 | 3437 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3438 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3439 | } else { |
3440 | rm = (modrm & 7) | REX_B(s); | |
3441 | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), | |
3442 | offsetof(CPUX86State,xmm_regs[reg])); | |
3443 | } | |
3444 | break; | |
3445 | case 0x211: /* movss ea, xmm */ | |
3446 | if (mod != 3) { | |
0af10c86 | 3447 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
651ba608 | 3448 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
57fec1fe | 3449 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
664e0f19 FB |
3450 | } else { |
3451 | rm = (modrm & 7) | REX_B(s); | |
3452 | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), | |
3453 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3454 | } | |
3455 | break; | |
3456 | case 0x311: /* movsd ea, xmm */ | |
3457 | if (mod != 3) { | |
0af10c86 | 3458 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3459 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3460 | } else { |
3461 | rm = (modrm & 7) | REX_B(s); | |
3462 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3463 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3464 | } | |
3465 | break; | |
3466 | case 0x013: /* movlps */ | |
3467 | case 0x113: /* movlpd */ | |
3468 | if (mod != 3) { | |
0af10c86 | 3469 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3470 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3471 | } else { |
3472 | goto illegal_op; | |
3473 | } | |
3474 | break; | |
3475 | case 0x017: /* movhps */ | |
3476 | case 0x117: /* movhpd */ | |
3477 | if (mod != 3) { | |
0af10c86 | 3478 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3479 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3480 | } else { |
3481 | goto illegal_op; | |
3482 | } | |
3483 | break; | |
3484 | case 0x71: /* shift mm, im */ | |
3485 | case 0x72: | |
3486 | case 0x73: | |
3487 | case 0x171: /* shift xmm, im */ | |
3488 | case 0x172: | |
3489 | case 0x173: | |
c045af25 AK |
3490 | if (b1 >= 2) { |
3491 | goto illegal_op; | |
3492 | } | |
0af10c86 | 3493 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3494 | if (is_xmm) { |
3495 | gen_op_movl_T0_im(val); | |
651ba608 | 3496 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 | 3497 | gen_op_movl_T0_0(); |
651ba608 | 3498 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); |
664e0f19 FB |
3499 | op1_offset = offsetof(CPUX86State,xmm_t0); |
3500 | } else { | |
3501 | gen_op_movl_T0_im(val); | |
651ba608 | 3502 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); |
664e0f19 | 3503 | gen_op_movl_T0_0(); |
651ba608 | 3504 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); |
664e0f19 FB |
3505 | op1_offset = offsetof(CPUX86State,mmx_t0); |
3506 | } | |
d3eb5eae BS |
3507 | sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + |
3508 | (((modrm >> 3)) & 7)][b1]; | |
3509 | if (!sse_fn_epp) { | |
664e0f19 | 3510 | goto illegal_op; |
c4baa050 | 3511 | } |
664e0f19 FB |
3512 | if (is_xmm) { |
3513 | rm = (modrm & 7) | REX_B(s); | |
3514 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3515 | } else { | |
3516 | rm = (modrm & 7); | |
3517 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3518 | } | |
5af45186 FB |
3519 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3520 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); | |
d3eb5eae | 3521 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3522 | break; |
3523 | case 0x050: /* movmskps */ | |
664e0f19 | 3524 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3525 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3526 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3527 | gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3528 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3529 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3530 | break; |
3531 | case 0x150: /* movmskpd */ | |
664e0f19 | 3532 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3533 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3534 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3535 | gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3536 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3537 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3538 | break; |
3539 | case 0x02a: /* cvtpi2ps */ | |
3540 | case 0x12a: /* cvtpi2pd */ | |
d3eb5eae | 3541 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3542 | if (mod != 3) { |
0af10c86 | 3543 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 3544 | op2_offset = offsetof(CPUX86State,mmx_t0); |
8686c490 | 3545 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3546 | } else { |
3547 | rm = (modrm & 7); | |
3548 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3549 | } | |
3550 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3551 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3552 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3553 | switch(b >> 8) { |
3554 | case 0x0: | |
d3eb5eae | 3555 | gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3556 | break; |
3557 | default: | |
3558 | case 0x1: | |
d3eb5eae | 3559 | gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3560 | break; |
3561 | } | |
3562 | break; | |
3563 | case 0x22a: /* cvtsi2ss */ | |
3564 | case 0x32a: /* cvtsi2sd */ | |
3565 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
0af10c86 | 3566 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
664e0f19 | 3567 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
5af45186 | 3568 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
28e10711 | 3569 | if (ot == OT_LONG) { |
d3eb5eae | 3570 | SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1]; |
28e10711 | 3571 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 3572 | sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32); |
28e10711 | 3573 | } else { |
11f8cdbc | 3574 | #ifdef TARGET_X86_64 |
d3eb5eae BS |
3575 | SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1]; |
3576 | sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]); | |
11f8cdbc SW |
3577 | #else |
3578 | goto illegal_op; | |
3579 | #endif | |
28e10711 | 3580 | } |
664e0f19 FB |
3581 | break; |
3582 | case 0x02c: /* cvttps2pi */ | |
3583 | case 0x12c: /* cvttpd2pi */ | |
3584 | case 0x02d: /* cvtps2pi */ | |
3585 | case 0x12d: /* cvtpd2pi */ | |
d3eb5eae | 3586 | gen_helper_enter_mmx(cpu_env); |
664e0f19 | 3587 | if (mod != 3) { |
0af10c86 | 3588 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 3589 | op2_offset = offsetof(CPUX86State,xmm_t0); |
8686c490 | 3590 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3591 | } else { |
3592 | rm = (modrm & 7) | REX_B(s); | |
3593 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3594 | } | |
3595 | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx); | |
5af45186 FB |
3596 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3597 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3598 | switch(b) { |
3599 | case 0x02c: | |
d3eb5eae | 3600 | gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3601 | break; |
3602 | case 0x12c: | |
d3eb5eae | 3603 | gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3604 | break; |
3605 | case 0x02d: | |
d3eb5eae | 3606 | gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3607 | break; |
3608 | case 0x12d: | |
d3eb5eae | 3609 | gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3610 | break; |
3611 | } | |
3612 | break; | |
3613 | case 0x22c: /* cvttss2si */ | |
3614 | case 0x32c: /* cvttsd2si */ | |
3615 | case 0x22d: /* cvtss2si */ | |
3616 | case 0x32d: /* cvtsd2si */ | |
3617 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
31313213 | 3618 | if (mod != 3) { |
0af10c86 | 3619 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
31313213 | 3620 | if ((b >> 8) & 1) { |
8686c490 | 3621 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))); |
31313213 | 3622 | } else { |
57fec1fe | 3623 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3624 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
31313213 FB |
3625 | } |
3626 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3627 | } else { | |
3628 | rm = (modrm & 7) | REX_B(s); | |
3629 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3630 | } | |
5af45186 FB |
3631 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3632 | if (ot == OT_LONG) { | |
d3eb5eae | 3633 | SSEFunc_i_ep sse_fn_i_ep = |
bedc2ac1 | 3634 | sse_op_table3bi[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3635 | sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3636 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
5af45186 | 3637 | } else { |
11f8cdbc | 3638 | #ifdef TARGET_X86_64 |
d3eb5eae | 3639 | SSEFunc_l_ep sse_fn_l_ep = |
bedc2ac1 | 3640 | sse_op_table3bq[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3641 | sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0); |
11f8cdbc SW |
3642 | #else |
3643 | goto illegal_op; | |
3644 | #endif | |
5af45186 | 3645 | } |
57fec1fe | 3646 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3647 | break; |
3648 | case 0xc4: /* pinsrw */ | |
5fafdf24 | 3649 | case 0x1c4: |
d1e42c5c | 3650 | s->rip_offset = 1; |
0af10c86 BS |
3651 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
3652 | val = cpu_ldub_code(env, s->pc++); | |
664e0f19 FB |
3653 | if (b1) { |
3654 | val &= 7; | |
5af45186 FB |
3655 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3656 | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); | |
664e0f19 FB |
3657 | } else { |
3658 | val &= 3; | |
5af45186 FB |
3659 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3660 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); | |
664e0f19 FB |
3661 | } |
3662 | break; | |
3663 | case 0xc5: /* pextrw */ | |
5fafdf24 | 3664 | case 0x1c5: |
664e0f19 FB |
3665 | if (mod != 3) |
3666 | goto illegal_op; | |
6dc2d0da | 3667 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
0af10c86 | 3668 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
3669 | if (b1) { |
3670 | val &= 7; | |
3671 | rm = (modrm & 7) | REX_B(s); | |
5af45186 FB |
3672 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3673 | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); | |
664e0f19 FB |
3674 | } else { |
3675 | val &= 3; | |
3676 | rm = (modrm & 7); | |
5af45186 FB |
3677 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3678 | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); | |
664e0f19 FB |
3679 | } |
3680 | reg = ((modrm >> 3) & 7) | rex_r; | |
6dc2d0da | 3681 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3682 | break; |
3683 | case 0x1d6: /* movq ea, xmm */ | |
3684 | if (mod != 3) { | |
0af10c86 | 3685 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8686c490 | 3686 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3687 | } else { |
3688 | rm = (modrm & 7) | REX_B(s); | |
3689 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3690 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3691 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3692 | } | |
3693 | break; | |
3694 | case 0x2d6: /* movq2dq */ | |
d3eb5eae | 3695 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3696 | rm = (modrm & 7); |
3697 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3698 | offsetof(CPUX86State,fpregs[rm].mmx)); | |
3699 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3700 | break; |
3701 | case 0x3d6: /* movdq2q */ | |
d3eb5eae | 3702 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3703 | rm = (modrm & 7) | REX_B(s); |
3704 | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), | |
3705 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
664e0f19 FB |
3706 | break; |
3707 | case 0xd7: /* pmovmskb */ | |
3708 | case 0x1d7: | |
3709 | if (mod != 3) | |
3710 | goto illegal_op; | |
3711 | if (b1) { | |
3712 | rm = (modrm & 7) | REX_B(s); | |
5af45186 | 3713 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
d3eb5eae | 3714 | gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 FB |
3715 | } else { |
3716 | rm = (modrm & 7); | |
5af45186 | 3717 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
d3eb5eae | 3718 | gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 | 3719 | } |
b6abf97d | 3720 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
664e0f19 | 3721 | reg = ((modrm >> 3) & 7) | rex_r; |
57fec1fe | 3722 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 | 3723 | break; |
4242b1bd | 3724 | case 0x138: |
000cacf6 AZ |
3725 | if (s->prefix & PREFIX_REPNZ) |
3726 | goto crc32; | |
3727 | case 0x038: | |
4242b1bd | 3728 | b = modrm; |
0af10c86 | 3729 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
3730 | rm = modrm & 7; |
3731 | reg = ((modrm >> 3) & 7) | rex_r; | |
3732 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3733 | if (b1 >= 2) { |
3734 | goto illegal_op; | |
3735 | } | |
4242b1bd | 3736 | |
d3eb5eae BS |
3737 | sse_fn_epp = sse_op_table6[b].op[b1]; |
3738 | if (!sse_fn_epp) { | |
4242b1bd | 3739 | goto illegal_op; |
c4baa050 | 3740 | } |
222a3336 AZ |
3741 | if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask)) |
3742 | goto illegal_op; | |
4242b1bd AZ |
3743 | |
3744 | if (b1) { | |
3745 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3746 | if (mod == 3) { | |
3747 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3748 | } else { | |
3749 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
0af10c86 | 3750 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
222a3336 AZ |
3751 | switch (b) { |
3752 | case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ | |
3753 | case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ | |
3754 | case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ | |
3755 | gen_ldq_env_A0(s->mem_index, op2_offset + | |
3756 | offsetof(XMMReg, XMM_Q(0))); | |
3757 | break; | |
3758 | case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ | |
3759 | case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ | |
a7812ae4 | 3760 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3761 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3762 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3763 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + |
3764 | offsetof(XMMReg, XMM_L(0))); | |
3765 | break; | |
3766 | case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ | |
3767 | tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, | |
3768 | (s->mem_index >> 2) - 1); | |
3769 | tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + | |
3770 | offsetof(XMMReg, XMM_W(0))); | |
3771 | break; | |
3772 | case 0x2a: /* movntqda */ | |
3773 | gen_ldo_env_A0(s->mem_index, op1_offset); | |
3774 | return; | |
3775 | default: | |
3776 | gen_ldo_env_A0(s->mem_index, op2_offset); | |
3777 | } | |
4242b1bd AZ |
3778 | } |
3779 | } else { | |
3780 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3781 | if (mod == 3) { | |
3782 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3783 | } else { | |
3784 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
0af10c86 | 3785 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4242b1bd AZ |
3786 | gen_ldq_env_A0(s->mem_index, op2_offset); |
3787 | } | |
3788 | } | |
d3eb5eae | 3789 | if (sse_fn_epp == SSE_SPECIAL) { |
222a3336 | 3790 | goto illegal_op; |
c4baa050 | 3791 | } |
222a3336 | 3792 | |
4242b1bd AZ |
3793 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3794 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 3795 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
222a3336 | 3796 | |
3ca51d07 RH |
3797 | if (b == 0x17) { |
3798 | set_cc_op(s, CC_OP_EFLAGS); | |
3799 | } | |
4242b1bd | 3800 | break; |
222a3336 AZ |
3801 | case 0x338: /* crc32 */ |
3802 | crc32: | |
3803 | b = modrm; | |
0af10c86 | 3804 | modrm = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
3805 | reg = ((modrm >> 3) & 7) | rex_r; |
3806 | ||
3807 | if (b != 0xf0 && b != 0xf1) | |
3808 | goto illegal_op; | |
3809 | if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) | |
4242b1bd AZ |
3810 | goto illegal_op; |
3811 | ||
222a3336 AZ |
3812 | if (b == 0xf0) |
3813 | ot = OT_BYTE; | |
3814 | else if (b == 0xf1 && s->dflag != 2) | |
3815 | if (s->prefix & PREFIX_DATA) | |
3816 | ot = OT_WORD; | |
3817 | else | |
3818 | ot = OT_LONG; | |
3819 | else | |
3820 | ot = OT_QUAD; | |
3821 | ||
3822 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
3823 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
0af10c86 | 3824 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
a7812ae4 PB |
3825 | gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, |
3826 | cpu_T[0], tcg_const_i32(8 << ot)); | |
222a3336 AZ |
3827 | |
3828 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3829 | gen_op_mov_reg_T0(ot, reg); | |
3830 | break; | |
3831 | case 0x03a: | |
3832 | case 0x13a: | |
4242b1bd | 3833 | b = modrm; |
0af10c86 | 3834 | modrm = cpu_ldub_code(env, s->pc++); |
4242b1bd AZ |
3835 | rm = modrm & 7; |
3836 | reg = ((modrm >> 3) & 7) | rex_r; | |
3837 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3838 | if (b1 >= 2) { |
3839 | goto illegal_op; | |
3840 | } | |
4242b1bd | 3841 | |
d3eb5eae BS |
3842 | sse_fn_eppi = sse_op_table7[b].op[b1]; |
3843 | if (!sse_fn_eppi) { | |
4242b1bd | 3844 | goto illegal_op; |
c4baa050 | 3845 | } |
222a3336 AZ |
3846 | if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) |
3847 | goto illegal_op; | |
3848 | ||
d3eb5eae | 3849 | if (sse_fn_eppi == SSE_SPECIAL) { |
222a3336 AZ |
3850 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
3851 | rm = (modrm & 7) | REX_B(s); | |
3852 | if (mod != 3) | |
0af10c86 | 3853 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
222a3336 | 3854 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 3855 | val = cpu_ldub_code(env, s->pc++); |
222a3336 AZ |
3856 | switch (b) { |
3857 | case 0x14: /* pextrb */ | |
3858 | tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3859 | xmm_regs[reg].XMM_B(val & 15))); | |
3860 | if (mod == 3) | |
3861 | gen_op_mov_reg_T0(ot, rm); | |
3862 | else | |
3863 | tcg_gen_qemu_st8(cpu_T[0], cpu_A0, | |
3864 | (s->mem_index >> 2) - 1); | |
3865 | break; | |
3866 | case 0x15: /* pextrw */ | |
3867 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3868 | xmm_regs[reg].XMM_W(val & 7))); | |
3869 | if (mod == 3) | |
3870 | gen_op_mov_reg_T0(ot, rm); | |
3871 | else | |
3872 | tcg_gen_qemu_st16(cpu_T[0], cpu_A0, | |
3873 | (s->mem_index >> 2) - 1); | |
3874 | break; | |
3875 | case 0x16: | |
3876 | if (ot == OT_LONG) { /* pextrd */ | |
3877 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, | |
3878 | offsetof(CPUX86State, | |
3879 | xmm_regs[reg].XMM_L(val & 3))); | |
a7812ae4 | 3880 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
222a3336 | 3881 | if (mod == 3) |
a7812ae4 | 3882 | gen_op_mov_reg_v(ot, rm, cpu_T[0]); |
222a3336 | 3883 | else |
a7812ae4 | 3884 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, |
222a3336 AZ |
3885 | (s->mem_index >> 2) - 1); |
3886 | } else { /* pextrq */ | |
a7812ae4 | 3887 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3888 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
3889 | offsetof(CPUX86State, | |
3890 | xmm_regs[reg].XMM_Q(val & 1))); | |
3891 | if (mod == 3) | |
3892 | gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); | |
3893 | else | |
3894 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, | |
3895 | (s->mem_index >> 2) - 1); | |
a7812ae4 PB |
3896 | #else |
3897 | goto illegal_op; | |
3898 | #endif | |
222a3336 AZ |
3899 | } |
3900 | break; | |
3901 | case 0x17: /* extractps */ | |
3902 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3903 | xmm_regs[reg].XMM_L(val & 3))); | |
3904 | if (mod == 3) | |
3905 | gen_op_mov_reg_T0(ot, rm); | |
3906 | else | |
3907 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, | |
3908 | (s->mem_index >> 2) - 1); | |
3909 | break; | |
3910 | case 0x20: /* pinsrb */ | |
3911 | if (mod == 3) | |
3912 | gen_op_mov_TN_reg(OT_LONG, 0, rm); | |
3913 | else | |
a7812ae4 | 3914 | tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0, |
222a3336 | 3915 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3916 | tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, |
222a3336 AZ |
3917 | xmm_regs[reg].XMM_B(val & 15))); |
3918 | break; | |
3919 | case 0x21: /* insertps */ | |
a7812ae4 | 3920 | if (mod == 3) { |
222a3336 AZ |
3921 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
3922 | offsetof(CPUX86State,xmm_regs[rm] | |
3923 | .XMM_L((val >> 6) & 3))); | |
a7812ae4 PB |
3924 | } else { |
3925 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, | |
222a3336 | 3926 | (s->mem_index >> 2) - 1); |
a7812ae4 PB |
3927 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
3928 | } | |
222a3336 AZ |
3929 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3930 | offsetof(CPUX86State,xmm_regs[reg] | |
3931 | .XMM_L((val >> 4) & 3))); | |
3932 | if ((val >> 0) & 1) | |
3933 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3934 | cpu_env, offsetof(CPUX86State, | |
3935 | xmm_regs[reg].XMM_L(0))); | |
3936 | if ((val >> 1) & 1) | |
3937 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3938 | cpu_env, offsetof(CPUX86State, | |
3939 | xmm_regs[reg].XMM_L(1))); | |
3940 | if ((val >> 2) & 1) | |
3941 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3942 | cpu_env, offsetof(CPUX86State, | |
3943 | xmm_regs[reg].XMM_L(2))); | |
3944 | if ((val >> 3) & 1) | |
3945 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
3946 | cpu_env, offsetof(CPUX86State, | |
3947 | xmm_regs[reg].XMM_L(3))); | |
3948 | break; | |
3949 | case 0x22: | |
3950 | if (ot == OT_LONG) { /* pinsrd */ | |
3951 | if (mod == 3) | |
a7812ae4 | 3952 | gen_op_mov_v_reg(ot, cpu_tmp0, rm); |
222a3336 | 3953 | else |
a7812ae4 | 3954 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3955 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3956 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3957 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3958 | offsetof(CPUX86State, | |
3959 | xmm_regs[reg].XMM_L(val & 3))); | |
3960 | } else { /* pinsrq */ | |
a7812ae4 | 3961 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3962 | if (mod == 3) |
3963 | gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); | |
3964 | else | |
3965 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, | |
3966 | (s->mem_index >> 2) - 1); | |
3967 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, | |
3968 | offsetof(CPUX86State, | |
3969 | xmm_regs[reg].XMM_Q(val & 1))); | |
a7812ae4 PB |
3970 | #else |
3971 | goto illegal_op; | |
3972 | #endif | |
222a3336 AZ |
3973 | } |
3974 | break; | |
3975 | } | |
3976 | return; | |
3977 | } | |
4242b1bd AZ |
3978 | |
3979 | if (b1) { | |
3980 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3981 | if (mod == 3) { | |
3982 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3983 | } else { | |
3984 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
0af10c86 | 3985 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4242b1bd AZ |
3986 | gen_ldo_env_A0(s->mem_index, op2_offset); |
3987 | } | |
3988 | } else { | |
3989 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3990 | if (mod == 3) { | |
3991 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3992 | } else { | |
3993 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
0af10c86 | 3994 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4242b1bd AZ |
3995 | gen_ldq_env_A0(s->mem_index, op2_offset); |
3996 | } | |
3997 | } | |
0af10c86 | 3998 | val = cpu_ldub_code(env, s->pc++); |
4242b1bd | 3999 | |
222a3336 | 4000 | if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ |
3ca51d07 | 4001 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 AZ |
4002 | |
4003 | if (s->dflag == 2) | |
4004 | /* The helper must use entire 64-bit gp registers */ | |
4005 | val |= 1 << 8; | |
4006 | } | |
4007 | ||
4242b1bd AZ |
4008 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4009 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4010 | sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
4242b1bd | 4011 | break; |
664e0f19 FB |
4012 | default: |
4013 | goto illegal_op; | |
4014 | } | |
4015 | } else { | |
4016 | /* generic MMX or SSE operation */ | |
d1e42c5c | 4017 | switch(b) { |
d1e42c5c FB |
4018 | case 0x70: /* pshufx insn */ |
4019 | case 0xc6: /* pshufx insn */ | |
4020 | case 0xc2: /* compare insns */ | |
4021 | s->rip_offset = 1; | |
4022 | break; | |
4023 | default: | |
4024 | break; | |
664e0f19 FB |
4025 | } |
4026 | if (is_xmm) { | |
4027 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4028 | if (mod != 3) { | |
0af10c86 | 4029 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 4030 | op2_offset = offsetof(CPUX86State,xmm_t0); |
480c1cdb | 4031 | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
664e0f19 FB |
4032 | b == 0xc2)) { |
4033 | /* specific case for SSE single instructions */ | |
4034 | if (b1 == 2) { | |
4035 | /* 32 bit access */ | |
57fec1fe | 4036 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 4037 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 FB |
4038 | } else { |
4039 | /* 64 bit access */ | |
8686c490 | 4040 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0))); |
664e0f19 FB |
4041 | } |
4042 | } else { | |
8686c490 | 4043 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
4044 | } |
4045 | } else { | |
4046 | rm = (modrm & 7) | REX_B(s); | |
4047 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
4048 | } | |
4049 | } else { | |
4050 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4051 | if (mod != 3) { | |
0af10c86 | 4052 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 4053 | op2_offset = offsetof(CPUX86State,mmx_t0); |
8686c490 | 4054 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
4055 | } else { |
4056 | rm = (modrm & 7); | |
4057 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4058 | } | |
4059 | } | |
4060 | switch(b) { | |
a35f3ec7 | 4061 | case 0x0f: /* 3DNow! data insns */ |
e771edab AJ |
4062 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) |
4063 | goto illegal_op; | |
0af10c86 | 4064 | val = cpu_ldub_code(env, s->pc++); |
d3eb5eae BS |
4065 | sse_fn_epp = sse_op_table5[val]; |
4066 | if (!sse_fn_epp) { | |
a35f3ec7 | 4067 | goto illegal_op; |
c4baa050 | 4068 | } |
5af45186 FB |
4069 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4070 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4071 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
a35f3ec7 | 4072 | break; |
664e0f19 FB |
4073 | case 0x70: /* pshufx insn */ |
4074 | case 0xc6: /* pshufx insn */ | |
0af10c86 | 4075 | val = cpu_ldub_code(env, s->pc++); |
5af45186 FB |
4076 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4077 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4078 | /* XXX: introduce a new table? */ |
d3eb5eae | 4079 | sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp; |
c4baa050 | 4080 | sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
664e0f19 FB |
4081 | break; |
4082 | case 0xc2: | |
4083 | /* compare insns */ | |
0af10c86 | 4084 | val = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
4085 | if (val >= 8) |
4086 | goto illegal_op; | |
d3eb5eae | 4087 | sse_fn_epp = sse_op_table4[val][b1]; |
c4baa050 | 4088 | |
5af45186 FB |
4089 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4090 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4091 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 | 4092 | break; |
b8b6a50b FB |
4093 | case 0xf7: |
4094 | /* maskmov : we must prepare A0 */ | |
4095 | if (mod != 3) | |
4096 | goto illegal_op; | |
4097 | #ifdef TARGET_X86_64 | |
4098 | if (s->aflag == 2) { | |
4099 | gen_op_movq_A0_reg(R_EDI); | |
4100 | } else | |
4101 | #endif | |
4102 | { | |
4103 | gen_op_movl_A0_reg(R_EDI); | |
4104 | if (s->aflag == 0) | |
4105 | gen_op_andl_A0_ffff(); | |
4106 | } | |
4107 | gen_add_A0_ds_seg(s); | |
4108 | ||
4109 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); | |
4110 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4111 | /* XXX: introduce a new table? */ |
d3eb5eae BS |
4112 | sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp; |
4113 | sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0); | |
b8b6a50b | 4114 | break; |
664e0f19 | 4115 | default: |
5af45186 FB |
4116 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4117 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4118 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
4119 | break; |
4120 | } | |
4121 | if (b == 0x2e || b == 0x2f) { | |
3ca51d07 | 4122 | set_cc_op(s, CC_OP_EFLAGS); |
664e0f19 FB |
4123 | } |
4124 | } | |
4125 | } | |
4126 | ||
2c0262af FB |
4127 | /* convert one instruction. s->is_jmp is set if the translation must |
4128 | be stopped. Return the next pc value */ | |
0af10c86 BS |
4129 | static target_ulong disas_insn(CPUX86State *env, DisasContext *s, |
4130 | target_ulong pc_start) | |
2c0262af FB |
4131 | { |
4132 | int b, prefixes, aflag, dflag; | |
4133 | int shift, ot; | |
4134 | int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val; | |
14ce26e7 FB |
4135 | target_ulong next_eip, tval; |
4136 | int rex_w, rex_r; | |
2c0262af | 4137 | |
fdefe51c | 4138 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
70cff25e | 4139 | tcg_gen_debug_insn_start(pc_start); |
fdefe51c | 4140 | } |
2c0262af FB |
4141 | s->pc = pc_start; |
4142 | prefixes = 0; | |
4143 | aflag = s->code32; | |
4144 | dflag = s->code32; | |
4145 | s->override = -1; | |
14ce26e7 FB |
4146 | rex_w = -1; |
4147 | rex_r = 0; | |
4148 | #ifdef TARGET_X86_64 | |
4149 | s->rex_x = 0; | |
4150 | s->rex_b = 0; | |
5fafdf24 | 4151 | x86_64_hregs = 0; |
14ce26e7 FB |
4152 | #endif |
4153 | s->rip_offset = 0; /* for relative ip address */ | |
2c0262af | 4154 | next_byte: |
0af10c86 | 4155 | b = cpu_ldub_code(env, s->pc); |
2c0262af FB |
4156 | s->pc++; |
4157 | /* check prefixes */ | |
14ce26e7 FB |
4158 | #ifdef TARGET_X86_64 |
4159 | if (CODE64(s)) { | |
4160 | switch (b) { | |
4161 | case 0xf3: | |
4162 | prefixes |= PREFIX_REPZ; | |
4163 | goto next_byte; | |
4164 | case 0xf2: | |
4165 | prefixes |= PREFIX_REPNZ; | |
4166 | goto next_byte; | |
4167 | case 0xf0: | |
4168 | prefixes |= PREFIX_LOCK; | |
4169 | goto next_byte; | |
4170 | case 0x2e: | |
4171 | s->override = R_CS; | |
4172 | goto next_byte; | |
4173 | case 0x36: | |
4174 | s->override = R_SS; | |
4175 | goto next_byte; | |
4176 | case 0x3e: | |
4177 | s->override = R_DS; | |
4178 | goto next_byte; | |
4179 | case 0x26: | |
4180 | s->override = R_ES; | |
4181 | goto next_byte; | |
4182 | case 0x64: | |
4183 | s->override = R_FS; | |
4184 | goto next_byte; | |
4185 | case 0x65: | |
4186 | s->override = R_GS; | |
4187 | goto next_byte; | |
4188 | case 0x66: | |
4189 | prefixes |= PREFIX_DATA; | |
4190 | goto next_byte; | |
4191 | case 0x67: | |
4192 | prefixes |= PREFIX_ADR; | |
4193 | goto next_byte; | |
4194 | case 0x40 ... 0x4f: | |
4195 | /* REX prefix */ | |
4196 | rex_w = (b >> 3) & 1; | |
4197 | rex_r = (b & 0x4) << 1; | |
4198 | s->rex_x = (b & 0x2) << 2; | |
4199 | REX_B(s) = (b & 0x1) << 3; | |
4200 | x86_64_hregs = 1; /* select uniform byte register addressing */ | |
4201 | goto next_byte; | |
4202 | } | |
4203 | if (rex_w == 1) { | |
4204 | /* 0x66 is ignored if rex.w is set */ | |
4205 | dflag = 2; | |
4206 | } else { | |
4207 | if (prefixes & PREFIX_DATA) | |
4208 | dflag ^= 1; | |
4209 | } | |
4210 | if (!(prefixes & PREFIX_ADR)) | |
4211 | aflag = 2; | |
5fafdf24 | 4212 | } else |
14ce26e7 FB |
4213 | #endif |
4214 | { | |
4215 | switch (b) { | |
4216 | case 0xf3: | |
4217 | prefixes |= PREFIX_REPZ; | |
4218 | goto next_byte; | |
4219 | case 0xf2: | |
4220 | prefixes |= PREFIX_REPNZ; | |
4221 | goto next_byte; | |
4222 | case 0xf0: | |
4223 | prefixes |= PREFIX_LOCK; | |
4224 | goto next_byte; | |
4225 | case 0x2e: | |
4226 | s->override = R_CS; | |
4227 | goto next_byte; | |
4228 | case 0x36: | |
4229 | s->override = R_SS; | |
4230 | goto next_byte; | |
4231 | case 0x3e: | |
4232 | s->override = R_DS; | |
4233 | goto next_byte; | |
4234 | case 0x26: | |
4235 | s->override = R_ES; | |
4236 | goto next_byte; | |
4237 | case 0x64: | |
4238 | s->override = R_FS; | |
4239 | goto next_byte; | |
4240 | case 0x65: | |
4241 | s->override = R_GS; | |
4242 | goto next_byte; | |
4243 | case 0x66: | |
4244 | prefixes |= PREFIX_DATA; | |
4245 | goto next_byte; | |
4246 | case 0x67: | |
4247 | prefixes |= PREFIX_ADR; | |
4248 | goto next_byte; | |
4249 | } | |
4250 | if (prefixes & PREFIX_DATA) | |
4251 | dflag ^= 1; | |
4252 | if (prefixes & PREFIX_ADR) | |
4253 | aflag ^= 1; | |
2c0262af FB |
4254 | } |
4255 | ||
2c0262af FB |
4256 | s->prefix = prefixes; |
4257 | s->aflag = aflag; | |
4258 | s->dflag = dflag; | |
4259 | ||
4260 | /* lock generation */ | |
4261 | if (prefixes & PREFIX_LOCK) | |
a7812ae4 | 4262 | gen_helper_lock(); |
2c0262af FB |
4263 | |
4264 | /* now check op code */ | |
4265 | reswitch: | |
4266 | switch(b) { | |
4267 | case 0x0f: | |
4268 | /**************************/ | |
4269 | /* extended op code */ | |
0af10c86 | 4270 | b = cpu_ldub_code(env, s->pc++) | 0x100; |
2c0262af | 4271 | goto reswitch; |
3b46e624 | 4272 | |
2c0262af FB |
4273 | /**************************/ |
4274 | /* arith & logic */ | |
4275 | case 0x00 ... 0x05: | |
4276 | case 0x08 ... 0x0d: | |
4277 | case 0x10 ... 0x15: | |
4278 | case 0x18 ... 0x1d: | |
4279 | case 0x20 ... 0x25: | |
4280 | case 0x28 ... 0x2d: | |
4281 | case 0x30 ... 0x35: | |
4282 | case 0x38 ... 0x3d: | |
4283 | { | |
4284 | int op, f, val; | |
4285 | op = (b >> 3) & 7; | |
4286 | f = (b >> 1) & 3; | |
4287 | ||
4288 | if ((b & 1) == 0) | |
4289 | ot = OT_BYTE; | |
4290 | else | |
14ce26e7 | 4291 | ot = dflag + OT_WORD; |
3b46e624 | 4292 | |
2c0262af FB |
4293 | switch(f) { |
4294 | case 0: /* OP Ev, Gv */ | |
0af10c86 | 4295 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4296 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 4297 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4298 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4299 | if (mod != 3) { |
0af10c86 | 4300 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
4301 | opreg = OR_TMP0; |
4302 | } else if (op == OP_XORL && rm == reg) { | |
4303 | xor_zero: | |
4304 | /* xor reg, reg optimisation */ | |
4305 | gen_op_movl_T0_0(); | |
3ca51d07 | 4306 | set_cc_op(s, CC_OP_LOGICB + ot); |
57fec1fe | 4307 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
4308 | gen_op_update1_cc(); |
4309 | break; | |
4310 | } else { | |
4311 | opreg = rm; | |
4312 | } | |
57fec1fe | 4313 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4314 | gen_op(s, op, ot, opreg); |
4315 | break; | |
4316 | case 1: /* OP Gv, Ev */ | |
0af10c86 | 4317 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4318 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
4319 | reg = ((modrm >> 3) & 7) | rex_r; |
4320 | rm = (modrm & 7) | REX_B(s); | |
2c0262af | 4321 | if (mod != 3) { |
0af10c86 | 4322 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 4323 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af FB |
4324 | } else if (op == OP_XORL && rm == reg) { |
4325 | goto xor_zero; | |
4326 | } else { | |
57fec1fe | 4327 | gen_op_mov_TN_reg(ot, 1, rm); |
2c0262af FB |
4328 | } |
4329 | gen_op(s, op, ot, reg); | |
4330 | break; | |
4331 | case 2: /* OP A, Iv */ | |
0af10c86 | 4332 | val = insn_get(env, s, ot); |
2c0262af FB |
4333 | gen_op_movl_T1_im(val); |
4334 | gen_op(s, op, ot, OR_EAX); | |
4335 | break; | |
4336 | } | |
4337 | } | |
4338 | break; | |
4339 | ||
ec9d6075 FB |
4340 | case 0x82: |
4341 | if (CODE64(s)) | |
4342 | goto illegal_op; | |
2c0262af FB |
4343 | case 0x80: /* GRP1 */ |
4344 | case 0x81: | |
4345 | case 0x83: | |
4346 | { | |
4347 | int val; | |
4348 | ||
4349 | if ((b & 1) == 0) | |
4350 | ot = OT_BYTE; | |
4351 | else | |
14ce26e7 | 4352 | ot = dflag + OT_WORD; |
3b46e624 | 4353 | |
0af10c86 | 4354 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4355 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4356 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4357 | op = (modrm >> 3) & 7; |
3b46e624 | 4358 | |
2c0262af | 4359 | if (mod != 3) { |
14ce26e7 FB |
4360 | if (b == 0x83) |
4361 | s->rip_offset = 1; | |
4362 | else | |
4363 | s->rip_offset = insn_const_size(ot); | |
0af10c86 | 4364 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
4365 | opreg = OR_TMP0; |
4366 | } else { | |
14ce26e7 | 4367 | opreg = rm; |
2c0262af FB |
4368 | } |
4369 | ||
4370 | switch(b) { | |
4371 | default: | |
4372 | case 0x80: | |
4373 | case 0x81: | |
d64477af | 4374 | case 0x82: |
0af10c86 | 4375 | val = insn_get(env, s, ot); |
2c0262af FB |
4376 | break; |
4377 | case 0x83: | |
0af10c86 | 4378 | val = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
4379 | break; |
4380 | } | |
4381 | gen_op_movl_T1_im(val); | |
4382 | gen_op(s, op, ot, opreg); | |
4383 | } | |
4384 | break; | |
4385 | ||
4386 | /**************************/ | |
4387 | /* inc, dec, and other misc arith */ | |
4388 | case 0x40 ... 0x47: /* inc Gv */ | |
4389 | ot = dflag ? OT_LONG : OT_WORD; | |
4390 | gen_inc(s, ot, OR_EAX + (b & 7), 1); | |
4391 | break; | |
4392 | case 0x48 ... 0x4f: /* dec Gv */ | |
4393 | ot = dflag ? OT_LONG : OT_WORD; | |
4394 | gen_inc(s, ot, OR_EAX + (b & 7), -1); | |
4395 | break; | |
4396 | case 0xf6: /* GRP3 */ | |
4397 | case 0xf7: | |
4398 | if ((b & 1) == 0) | |
4399 | ot = OT_BYTE; | |
4400 | else | |
14ce26e7 | 4401 | ot = dflag + OT_WORD; |
2c0262af | 4402 | |
0af10c86 | 4403 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4404 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4405 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4406 | op = (modrm >> 3) & 7; |
4407 | if (mod != 3) { | |
14ce26e7 FB |
4408 | if (op == 0) |
4409 | s->rip_offset = insn_const_size(ot); | |
0af10c86 | 4410 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 4411 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4412 | } else { |
57fec1fe | 4413 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4414 | } |
4415 | ||
4416 | switch(op) { | |
4417 | case 0: /* test */ | |
0af10c86 | 4418 | val = insn_get(env, s, ot); |
2c0262af FB |
4419 | gen_op_movl_T1_im(val); |
4420 | gen_op_testl_T0_T1_cc(); | |
3ca51d07 | 4421 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af FB |
4422 | break; |
4423 | case 2: /* not */ | |
b6abf97d | 4424 | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4425 | if (mod != 3) { |
57fec1fe | 4426 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4427 | } else { |
57fec1fe | 4428 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4429 | } |
4430 | break; | |
4431 | case 3: /* neg */ | |
b6abf97d | 4432 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4433 | if (mod != 3) { |
57fec1fe | 4434 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4435 | } else { |
57fec1fe | 4436 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4437 | } |
4438 | gen_op_update_neg_cc(); | |
3ca51d07 | 4439 | set_cc_op(s, CC_OP_SUBB + ot); |
2c0262af FB |
4440 | break; |
4441 | case 4: /* mul */ | |
4442 | switch(ot) { | |
4443 | case OT_BYTE: | |
0211e5af FB |
4444 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4445 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); | |
4446 | tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); | |
4447 | /* XXX: use 32 bit mul which could be faster */ | |
4448 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4449 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4450 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4451 | tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); | |
3ca51d07 | 4452 | set_cc_op(s, CC_OP_MULB); |
2c0262af FB |
4453 | break; |
4454 | case OT_WORD: | |
0211e5af FB |
4455 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4456 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); | |
4457 | tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); | |
4458 | /* XXX: use 32 bit mul which could be faster */ | |
4459 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4460 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4461 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4462 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4463 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4464 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
3ca51d07 | 4465 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4466 | break; |
4467 | default: | |
4468 | case OT_LONG: | |
0211e5af FB |
4469 | #ifdef TARGET_X86_64 |
4470 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4471 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); | |
4472 | tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); | |
4473 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4474 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4475 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4476 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4477 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4478 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4479 | #else | |
4480 | { | |
a7812ae4 PB |
4481 | TCGv_i64 t0, t1; |
4482 | t0 = tcg_temp_new_i64(); | |
4483 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4484 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4485 | tcg_gen_extu_i32_i64(t0, cpu_T[0]); | |
4486 | tcg_gen_extu_i32_i64(t1, cpu_T[1]); | |
4487 | tcg_gen_mul_i64(t0, t0, t1); | |
4488 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4489 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4490 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4491 | tcg_gen_shri_i64(t0, t0, 32); | |
4492 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4493 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4494 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4495 | } | |
4496 | #endif | |
3ca51d07 | 4497 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4498 | break; |
14ce26e7 FB |
4499 | #ifdef TARGET_X86_64 |
4500 | case OT_QUAD: | |
7923057b | 4501 | gen_helper_mulq_EAX_T0(cpu_env, cpu_T[0]); |
3ca51d07 | 4502 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4503 | break; |
4504 | #endif | |
2c0262af | 4505 | } |
2c0262af FB |
4506 | break; |
4507 | case 5: /* imul */ | |
4508 | switch(ot) { | |
4509 | case OT_BYTE: | |
0211e5af FB |
4510 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4511 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4512 | tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); | |
4513 | /* XXX: use 32 bit mul which could be faster */ | |
4514 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4515 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4516 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4517 | tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]); | |
4518 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
3ca51d07 | 4519 | set_cc_op(s, CC_OP_MULB); |
2c0262af FB |
4520 | break; |
4521 | case OT_WORD: | |
0211e5af FB |
4522 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4523 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4524 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4525 | /* XXX: use 32 bit mul which could be faster */ | |
4526 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4527 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4528 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4529 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4530 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4531 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4532 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
3ca51d07 | 4533 | set_cc_op(s, CC_OP_MULW); |
2c0262af FB |
4534 | break; |
4535 | default: | |
4536 | case OT_LONG: | |
0211e5af FB |
4537 | #ifdef TARGET_X86_64 |
4538 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4539 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4540 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4541 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4542 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4543 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4544 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4545 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4546 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4547 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4548 | #else | |
4549 | { | |
a7812ae4 PB |
4550 | TCGv_i64 t0, t1; |
4551 | t0 = tcg_temp_new_i64(); | |
4552 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4553 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4554 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); | |
4555 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4556 | tcg_gen_mul_i64(t0, t0, t1); | |
4557 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4558 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4559 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4560 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4561 | tcg_gen_shri_i64(t0, t0, 32); | |
4562 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4563 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4564 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4565 | } | |
4566 | #endif | |
3ca51d07 | 4567 | set_cc_op(s, CC_OP_MULL); |
2c0262af | 4568 | break; |
14ce26e7 FB |
4569 | #ifdef TARGET_X86_64 |
4570 | case OT_QUAD: | |
7923057b | 4571 | gen_helper_imulq_EAX_T0(cpu_env, cpu_T[0]); |
3ca51d07 | 4572 | set_cc_op(s, CC_OP_MULQ); |
14ce26e7 FB |
4573 | break; |
4574 | #endif | |
2c0262af | 4575 | } |
2c0262af FB |
4576 | break; |
4577 | case 6: /* div */ | |
4578 | switch(ot) { | |
4579 | case OT_BYTE: | |
14ce26e7 | 4580 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4581 | gen_helper_divb_AL(cpu_env, cpu_T[0]); |
2c0262af FB |
4582 | break; |
4583 | case OT_WORD: | |
14ce26e7 | 4584 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4585 | gen_helper_divw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4586 | break; |
4587 | default: | |
4588 | case OT_LONG: | |
14ce26e7 | 4589 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4590 | gen_helper_divl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4591 | break; |
4592 | #ifdef TARGET_X86_64 | |
4593 | case OT_QUAD: | |
4594 | gen_jmp_im(pc_start - s->cs_base); | |
7923057b | 4595 | gen_helper_divq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4596 | break; |
14ce26e7 | 4597 | #endif |
2c0262af FB |
4598 | } |
4599 | break; | |
4600 | case 7: /* idiv */ | |
4601 | switch(ot) { | |
4602 | case OT_BYTE: | |
14ce26e7 | 4603 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4604 | gen_helper_idivb_AL(cpu_env, cpu_T[0]); |
2c0262af FB |
4605 | break; |
4606 | case OT_WORD: | |
14ce26e7 | 4607 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4608 | gen_helper_idivw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4609 | break; |
4610 | default: | |
4611 | case OT_LONG: | |
14ce26e7 | 4612 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4613 | gen_helper_idivl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4614 | break; |
4615 | #ifdef TARGET_X86_64 | |
4616 | case OT_QUAD: | |
4617 | gen_jmp_im(pc_start - s->cs_base); | |
7923057b | 4618 | gen_helper_idivq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4619 | break; |
14ce26e7 | 4620 | #endif |
2c0262af FB |
4621 | } |
4622 | break; | |
4623 | default: | |
4624 | goto illegal_op; | |
4625 | } | |
4626 | break; | |
4627 | ||
4628 | case 0xfe: /* GRP4 */ | |
4629 | case 0xff: /* GRP5 */ | |
4630 | if ((b & 1) == 0) | |
4631 | ot = OT_BYTE; | |
4632 | else | |
14ce26e7 | 4633 | ot = dflag + OT_WORD; |
2c0262af | 4634 | |
0af10c86 | 4635 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4636 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4637 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4638 | op = (modrm >> 3) & 7; |
4639 | if (op >= 2 && b == 0xfe) { | |
4640 | goto illegal_op; | |
4641 | } | |
14ce26e7 | 4642 | if (CODE64(s)) { |
aba9d61e | 4643 | if (op == 2 || op == 4) { |
14ce26e7 FB |
4644 | /* operand size for jumps is 64 bit */ |
4645 | ot = OT_QUAD; | |
aba9d61e | 4646 | } else if (op == 3 || op == 5) { |
41b1e61f | 4647 | ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD; |
14ce26e7 FB |
4648 | } else if (op == 6) { |
4649 | /* default push size is 64 bit */ | |
4650 | ot = dflag ? OT_QUAD : OT_WORD; | |
4651 | } | |
4652 | } | |
2c0262af | 4653 | if (mod != 3) { |
0af10c86 | 4654 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 4655 | if (op >= 2 && op != 3 && op != 5) |
57fec1fe | 4656 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4657 | } else { |
57fec1fe | 4658 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4659 | } |
4660 | ||
4661 | switch(op) { | |
4662 | case 0: /* inc Ev */ | |
4663 | if (mod != 3) | |
4664 | opreg = OR_TMP0; | |
4665 | else | |
4666 | opreg = rm; | |
4667 | gen_inc(s, ot, opreg, 1); | |
4668 | break; | |
4669 | case 1: /* dec Ev */ | |
4670 | if (mod != 3) | |
4671 | opreg = OR_TMP0; | |
4672 | else | |
4673 | opreg = rm; | |
4674 | gen_inc(s, ot, opreg, -1); | |
4675 | break; | |
4676 | case 2: /* call Ev */ | |
4f31916f | 4677 | /* XXX: optimize if memory (no 'and' is necessary) */ |
2c0262af FB |
4678 | if (s->dflag == 0) |
4679 | gen_op_andl_T0_ffff(); | |
2c0262af | 4680 | next_eip = s->pc - s->cs_base; |
1ef38687 | 4681 | gen_movtl_T1_im(next_eip); |
4f31916f FB |
4682 | gen_push_T1(s); |
4683 | gen_op_jmp_T0(); | |
2c0262af FB |
4684 | gen_eob(s); |
4685 | break; | |
61382a50 | 4686 | case 3: /* lcall Ev */ |
57fec1fe | 4687 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4688 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4689 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4690 | do_lcall: |
4691 | if (s->pe && !s->vm86) { | |
4692 | if (s->cc_op != CC_OP_DYNAMIC) | |
4693 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 4694 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4695 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
4696 | gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
4697 | tcg_const_i32(dflag), | |
a7812ae4 | 4698 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 4699 | } else { |
b6abf97d | 4700 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
4701 | gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1], |
4702 | tcg_const_i32(dflag), | |
a7812ae4 | 4703 | tcg_const_i32(s->pc - s->cs_base)); |
2c0262af FB |
4704 | } |
4705 | gen_eob(s); | |
4706 | break; | |
4707 | case 4: /* jmp Ev */ | |
4708 | if (s->dflag == 0) | |
4709 | gen_op_andl_T0_ffff(); | |
4710 | gen_op_jmp_T0(); | |
4711 | gen_eob(s); | |
4712 | break; | |
4713 | case 5: /* ljmp Ev */ | |
57fec1fe | 4714 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4715 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4716 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4717 | do_ljmp: |
4718 | if (s->pe && !s->vm86) { | |
4719 | if (s->cc_op != CC_OP_DYNAMIC) | |
4720 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 4721 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4722 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 4723 | gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
a7812ae4 | 4724 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 4725 | } else { |
3bd7da9e | 4726 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
4727 | gen_op_movl_T0_T1(); |
4728 | gen_op_jmp_T0(); | |
4729 | } | |
4730 | gen_eob(s); | |
4731 | break; | |
4732 | case 6: /* push Ev */ | |
4733 | gen_push_T0(s); | |
4734 | break; | |
4735 | default: | |
4736 | goto illegal_op; | |
4737 | } | |
4738 | break; | |
4739 | ||
4740 | case 0x84: /* test Ev, Gv */ | |
5fafdf24 | 4741 | case 0x85: |
2c0262af FB |
4742 | if ((b & 1) == 0) |
4743 | ot = OT_BYTE; | |
4744 | else | |
14ce26e7 | 4745 | ot = dflag + OT_WORD; |
2c0262af | 4746 | |
0af10c86 | 4747 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4748 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 4749 | |
0af10c86 | 4750 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 4751 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af | 4752 | gen_op_testl_T0_T1_cc(); |
3ca51d07 | 4753 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 4754 | break; |
3b46e624 | 4755 | |
2c0262af FB |
4756 | case 0xa8: /* test eAX, Iv */ |
4757 | case 0xa9: | |
4758 | if ((b & 1) == 0) | |
4759 | ot = OT_BYTE; | |
4760 | else | |
14ce26e7 | 4761 | ot = dflag + OT_WORD; |
0af10c86 | 4762 | val = insn_get(env, s, ot); |
2c0262af | 4763 | |
57fec1fe | 4764 | gen_op_mov_TN_reg(ot, 0, OR_EAX); |
2c0262af FB |
4765 | gen_op_movl_T1_im(val); |
4766 | gen_op_testl_T0_T1_cc(); | |
3ca51d07 | 4767 | set_cc_op(s, CC_OP_LOGICB + ot); |
2c0262af | 4768 | break; |
3b46e624 | 4769 | |
2c0262af | 4770 | case 0x98: /* CWDE/CBW */ |
14ce26e7 FB |
4771 | #ifdef TARGET_X86_64 |
4772 | if (dflag == 2) { | |
e108dd01 FB |
4773 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
4774 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4775 | gen_op_mov_reg_T0(OT_QUAD, R_EAX); | |
14ce26e7 FB |
4776 | } else |
4777 | #endif | |
e108dd01 FB |
4778 | if (dflag == 1) { |
4779 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4780 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4781 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4782 | } else { | |
4783 | gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX); | |
4784 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4785 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4786 | } | |
2c0262af FB |
4787 | break; |
4788 | case 0x99: /* CDQ/CWD */ | |
14ce26e7 FB |
4789 | #ifdef TARGET_X86_64 |
4790 | if (dflag == 2) { | |
e108dd01 FB |
4791 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
4792 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); | |
4793 | gen_op_mov_reg_T0(OT_QUAD, R_EDX); | |
14ce26e7 FB |
4794 | } else |
4795 | #endif | |
e108dd01 FB |
4796 | if (dflag == 1) { |
4797 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); | |
4798 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4799 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); | |
4800 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4801 | } else { | |
4802 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4803 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4804 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); | |
4805 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4806 | } | |
2c0262af FB |
4807 | break; |
4808 | case 0x1af: /* imul Gv, Ev */ | |
4809 | case 0x69: /* imul Gv, Ev, I */ | |
4810 | case 0x6b: | |
14ce26e7 | 4811 | ot = dflag + OT_WORD; |
0af10c86 | 4812 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
4813 | reg = ((modrm >> 3) & 7) | rex_r; |
4814 | if (b == 0x69) | |
4815 | s->rip_offset = insn_const_size(ot); | |
4816 | else if (b == 0x6b) | |
4817 | s->rip_offset = 1; | |
0af10c86 | 4818 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
2c0262af | 4819 | if (b == 0x69) { |
0af10c86 | 4820 | val = insn_get(env, s, ot); |
2c0262af FB |
4821 | gen_op_movl_T1_im(val); |
4822 | } else if (b == 0x6b) { | |
0af10c86 | 4823 | val = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
4824 | gen_op_movl_T1_im(val); |
4825 | } else { | |
57fec1fe | 4826 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4827 | } |
4828 | ||
14ce26e7 FB |
4829 | #ifdef TARGET_X86_64 |
4830 | if (ot == OT_QUAD) { | |
7923057b | 4831 | gen_helper_imulq_T0_T1(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
14ce26e7 FB |
4832 | } else |
4833 | #endif | |
2c0262af | 4834 | if (ot == OT_LONG) { |
0211e5af FB |
4835 | #ifdef TARGET_X86_64 |
4836 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4837 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4838 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4839 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4840 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4841 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4842 | #else | |
4843 | { | |
a7812ae4 PB |
4844 | TCGv_i64 t0, t1; |
4845 | t0 = tcg_temp_new_i64(); | |
4846 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4847 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); |
4848 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4849 | tcg_gen_mul_i64(t0, t0, t1); | |
4850 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4851 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4852 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4853 | tcg_gen_shri_i64(t0, t0, 32); | |
4854 | tcg_gen_trunc_i64_i32(cpu_T[1], t0); | |
4855 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0); | |
4856 | } | |
4857 | #endif | |
2c0262af | 4858 | } else { |
0211e5af FB |
4859 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4860 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4861 | /* XXX: use 32 bit mul which could be faster */ | |
4862 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4863 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4864 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4865 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
2c0262af | 4866 | } |
57fec1fe | 4867 | gen_op_mov_reg_T0(ot, reg); |
3ca51d07 | 4868 | set_cc_op(s, CC_OP_MULB + ot); |
2c0262af FB |
4869 | break; |
4870 | case 0x1c0: | |
4871 | case 0x1c1: /* xadd Ev, Gv */ | |
4872 | if ((b & 1) == 0) | |
4873 | ot = OT_BYTE; | |
4874 | else | |
14ce26e7 | 4875 | ot = dflag + OT_WORD; |
0af10c86 | 4876 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 4877 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
4878 | mod = (modrm >> 6) & 3; |
4879 | if (mod == 3) { | |
14ce26e7 | 4880 | rm = (modrm & 7) | REX_B(s); |
57fec1fe FB |
4881 | gen_op_mov_TN_reg(ot, 0, reg); |
4882 | gen_op_mov_TN_reg(ot, 1, rm); | |
2c0262af | 4883 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4884 | gen_op_mov_reg_T1(ot, reg); |
4885 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 4886 | } else { |
0af10c86 | 4887 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe FB |
4888 | gen_op_mov_TN_reg(ot, 0, reg); |
4889 | gen_op_ld_T1_A0(ot + s->mem_index); | |
2c0262af | 4890 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4891 | gen_op_st_T0_A0(ot + s->mem_index); |
4892 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af FB |
4893 | } |
4894 | gen_op_update2_cc(); | |
3ca51d07 | 4895 | set_cc_op(s, CC_OP_ADDB + ot); |
2c0262af FB |
4896 | break; |
4897 | case 0x1b0: | |
4898 | case 0x1b1: /* cmpxchg Ev, Gv */ | |
cad3a37d | 4899 | { |
1130328e | 4900 | int label1, label2; |
1e4840bf | 4901 | TCGv t0, t1, t2, a0; |
cad3a37d FB |
4902 | |
4903 | if ((b & 1) == 0) | |
4904 | ot = OT_BYTE; | |
4905 | else | |
4906 | ot = dflag + OT_WORD; | |
0af10c86 | 4907 | modrm = cpu_ldub_code(env, s->pc++); |
cad3a37d FB |
4908 | reg = ((modrm >> 3) & 7) | rex_r; |
4909 | mod = (modrm >> 6) & 3; | |
a7812ae4 PB |
4910 | t0 = tcg_temp_local_new(); |
4911 | t1 = tcg_temp_local_new(); | |
4912 | t2 = tcg_temp_local_new(); | |
4913 | a0 = tcg_temp_local_new(); | |
1e4840bf | 4914 | gen_op_mov_v_reg(ot, t1, reg); |
cad3a37d FB |
4915 | if (mod == 3) { |
4916 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 4917 | gen_op_mov_v_reg(ot, t0, rm); |
cad3a37d | 4918 | } else { |
0af10c86 | 4919 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
1e4840bf FB |
4920 | tcg_gen_mov_tl(a0, cpu_A0); |
4921 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
cad3a37d FB |
4922 | rm = 0; /* avoid warning */ |
4923 | } | |
4924 | label1 = gen_new_label(); | |
cc739bb0 | 4925 | tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0); |
1e4840bf FB |
4926 | gen_extu(ot, t2); |
4927 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); | |
f7e80adf | 4928 | label2 = gen_new_label(); |
cad3a37d | 4929 | if (mod == 3) { |
1e4840bf | 4930 | gen_op_mov_reg_v(ot, R_EAX, t0); |
1130328e FB |
4931 | tcg_gen_br(label2); |
4932 | gen_set_label(label1); | |
1e4840bf | 4933 | gen_op_mov_reg_v(ot, rm, t1); |
cad3a37d | 4934 | } else { |
f7e80adf AG |
4935 | /* perform no-op store cycle like physical cpu; must be |
4936 | before changing accumulator to ensure idempotency if | |
4937 | the store faults and the instruction is restarted */ | |
4938 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1e4840bf | 4939 | gen_op_mov_reg_v(ot, R_EAX, t0); |
f7e80adf | 4940 | tcg_gen_br(label2); |
1130328e | 4941 | gen_set_label(label1); |
1e4840bf | 4942 | gen_op_st_v(ot + s->mem_index, t1, a0); |
cad3a37d | 4943 | } |
f7e80adf | 4944 | gen_set_label(label2); |
1e4840bf FB |
4945 | tcg_gen_mov_tl(cpu_cc_src, t0); |
4946 | tcg_gen_mov_tl(cpu_cc_dst, t2); | |
3ca51d07 | 4947 | set_cc_op(s, CC_OP_SUBB + ot); |
1e4840bf FB |
4948 | tcg_temp_free(t0); |
4949 | tcg_temp_free(t1); | |
4950 | tcg_temp_free(t2); | |
4951 | tcg_temp_free(a0); | |
2c0262af | 4952 | } |
2c0262af FB |
4953 | break; |
4954 | case 0x1c7: /* cmpxchg8b */ | |
0af10c86 | 4955 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 4956 | mod = (modrm >> 6) & 3; |
71c3558e | 4957 | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
2c0262af | 4958 | goto illegal_op; |
1b9d9ebb FB |
4959 | #ifdef TARGET_X86_64 |
4960 | if (dflag == 2) { | |
4961 | if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) | |
4962 | goto illegal_op; | |
4963 | gen_jmp_im(pc_start - s->cs_base); | |
4964 | if (s->cc_op != CC_OP_DYNAMIC) | |
4965 | gen_op_set_cc_op(s->cc_op); | |
0af10c86 | 4966 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
92fc4b58 | 4967 | gen_helper_cmpxchg16b(cpu_env, cpu_A0); |
1b9d9ebb FB |
4968 | } else |
4969 | #endif | |
4970 | { | |
4971 | if (!(s->cpuid_features & CPUID_CX8)) | |
4972 | goto illegal_op; | |
4973 | gen_jmp_im(pc_start - s->cs_base); | |
4974 | if (s->cc_op != CC_OP_DYNAMIC) | |
4975 | gen_op_set_cc_op(s->cc_op); | |
0af10c86 | 4976 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
92fc4b58 | 4977 | gen_helper_cmpxchg8b(cpu_env, cpu_A0); |
1b9d9ebb | 4978 | } |
3ca51d07 | 4979 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 4980 | break; |
3b46e624 | 4981 | |
2c0262af FB |
4982 | /**************************/ |
4983 | /* push/pop */ | |
4984 | case 0x50 ... 0x57: /* push */ | |
57fec1fe | 4985 | gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s)); |
2c0262af FB |
4986 | gen_push_T0(s); |
4987 | break; | |
4988 | case 0x58 ... 0x5f: /* pop */ | |
14ce26e7 FB |
4989 | if (CODE64(s)) { |
4990 | ot = dflag ? OT_QUAD : OT_WORD; | |
4991 | } else { | |
4992 | ot = dflag + OT_WORD; | |
4993 | } | |
2c0262af | 4994 | gen_pop_T0(s); |
77729c24 | 4995 | /* NOTE: order is important for pop %sp */ |
2c0262af | 4996 | gen_pop_update(s); |
57fec1fe | 4997 | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s)); |
2c0262af FB |
4998 | break; |
4999 | case 0x60: /* pusha */ | |
14ce26e7 FB |
5000 | if (CODE64(s)) |
5001 | goto illegal_op; | |
2c0262af FB |
5002 | gen_pusha(s); |
5003 | break; | |
5004 | case 0x61: /* popa */ | |
14ce26e7 FB |
5005 | if (CODE64(s)) |
5006 | goto illegal_op; | |
2c0262af FB |
5007 | gen_popa(s); |
5008 | break; | |
5009 | case 0x68: /* push Iv */ | |
5010 | case 0x6a: | |
14ce26e7 FB |
5011 | if (CODE64(s)) { |
5012 | ot = dflag ? OT_QUAD : OT_WORD; | |
5013 | } else { | |
5014 | ot = dflag + OT_WORD; | |
5015 | } | |
2c0262af | 5016 | if (b == 0x68) |
0af10c86 | 5017 | val = insn_get(env, s, ot); |
2c0262af | 5018 | else |
0af10c86 | 5019 | val = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
5020 | gen_op_movl_T0_im(val); |
5021 | gen_push_T0(s); | |
5022 | break; | |
5023 | case 0x8f: /* pop Ev */ | |
14ce26e7 FB |
5024 | if (CODE64(s)) { |
5025 | ot = dflag ? OT_QUAD : OT_WORD; | |
5026 | } else { | |
5027 | ot = dflag + OT_WORD; | |
5028 | } | |
0af10c86 | 5029 | modrm = cpu_ldub_code(env, s->pc++); |
77729c24 | 5030 | mod = (modrm >> 6) & 3; |
2c0262af | 5031 | gen_pop_T0(s); |
77729c24 FB |
5032 | if (mod == 3) { |
5033 | /* NOTE: order is important for pop %sp */ | |
5034 | gen_pop_update(s); | |
14ce26e7 | 5035 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 5036 | gen_op_mov_reg_T0(ot, rm); |
77729c24 FB |
5037 | } else { |
5038 | /* NOTE: order is important too for MMU exceptions */ | |
14ce26e7 | 5039 | s->popl_esp_hack = 1 << ot; |
0af10c86 | 5040 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
77729c24 FB |
5041 | s->popl_esp_hack = 0; |
5042 | gen_pop_update(s); | |
5043 | } | |
2c0262af FB |
5044 | break; |
5045 | case 0xc8: /* enter */ | |
5046 | { | |
5047 | int level; | |
0af10c86 | 5048 | val = cpu_lduw_code(env, s->pc); |
2c0262af | 5049 | s->pc += 2; |
0af10c86 | 5050 | level = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5051 | gen_enter(s, val, level); |
5052 | } | |
5053 | break; | |
5054 | case 0xc9: /* leave */ | |
5055 | /* XXX: exception not precise (ESP is updated before potential exception) */ | |
14ce26e7 | 5056 | if (CODE64(s)) { |
57fec1fe FB |
5057 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP); |
5058 | gen_op_mov_reg_T0(OT_QUAD, R_ESP); | |
14ce26e7 | 5059 | } else if (s->ss32) { |
57fec1fe FB |
5060 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
5061 | gen_op_mov_reg_T0(OT_LONG, R_ESP); | |
2c0262af | 5062 | } else { |
57fec1fe FB |
5063 | gen_op_mov_TN_reg(OT_WORD, 0, R_EBP); |
5064 | gen_op_mov_reg_T0(OT_WORD, R_ESP); | |
2c0262af FB |
5065 | } |
5066 | gen_pop_T0(s); | |
14ce26e7 FB |
5067 | if (CODE64(s)) { |
5068 | ot = dflag ? OT_QUAD : OT_WORD; | |
5069 | } else { | |
5070 | ot = dflag + OT_WORD; | |
5071 | } | |
57fec1fe | 5072 | gen_op_mov_reg_T0(ot, R_EBP); |
2c0262af FB |
5073 | gen_pop_update(s); |
5074 | break; | |
5075 | case 0x06: /* push es */ | |
5076 | case 0x0e: /* push cs */ | |
5077 | case 0x16: /* push ss */ | |
5078 | case 0x1e: /* push ds */ | |
14ce26e7 FB |
5079 | if (CODE64(s)) |
5080 | goto illegal_op; | |
2c0262af FB |
5081 | gen_op_movl_T0_seg(b >> 3); |
5082 | gen_push_T0(s); | |
5083 | break; | |
5084 | case 0x1a0: /* push fs */ | |
5085 | case 0x1a8: /* push gs */ | |
5086 | gen_op_movl_T0_seg((b >> 3) & 7); | |
5087 | gen_push_T0(s); | |
5088 | break; | |
5089 | case 0x07: /* pop es */ | |
5090 | case 0x17: /* pop ss */ | |
5091 | case 0x1f: /* pop ds */ | |
14ce26e7 FB |
5092 | if (CODE64(s)) |
5093 | goto illegal_op; | |
2c0262af FB |
5094 | reg = b >> 3; |
5095 | gen_pop_T0(s); | |
5096 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5097 | gen_pop_update(s); | |
5098 | if (reg == R_SS) { | |
a2cc3b24 FB |
5099 | /* if reg == SS, inhibit interrupts/trace. */ |
5100 | /* If several instructions disable interrupts, only the | |
5101 | _first_ does it */ | |
5102 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5103 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5104 | s->tf = 0; |
5105 | } | |
5106 | if (s->is_jmp) { | |
14ce26e7 | 5107 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5108 | gen_eob(s); |
5109 | } | |
5110 | break; | |
5111 | case 0x1a1: /* pop fs */ | |
5112 | case 0x1a9: /* pop gs */ | |
5113 | gen_pop_T0(s); | |
5114 | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); | |
5115 | gen_pop_update(s); | |
5116 | if (s->is_jmp) { | |
14ce26e7 | 5117 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5118 | gen_eob(s); |
5119 | } | |
5120 | break; | |
5121 | ||
5122 | /**************************/ | |
5123 | /* mov */ | |
5124 | case 0x88: | |
5125 | case 0x89: /* mov Gv, Ev */ | |
5126 | if ((b & 1) == 0) | |
5127 | ot = OT_BYTE; | |
5128 | else | |
14ce26e7 | 5129 | ot = dflag + OT_WORD; |
0af10c86 | 5130 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5131 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5132 | |
2c0262af | 5133 | /* generate a generic store */ |
0af10c86 | 5134 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
2c0262af FB |
5135 | break; |
5136 | case 0xc6: | |
5137 | case 0xc7: /* mov Ev, Iv */ | |
5138 | if ((b & 1) == 0) | |
5139 | ot = OT_BYTE; | |
5140 | else | |
14ce26e7 | 5141 | ot = dflag + OT_WORD; |
0af10c86 | 5142 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5143 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5144 | if (mod != 3) { |
5145 | s->rip_offset = insn_const_size(ot); | |
0af10c86 | 5146 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 5147 | } |
0af10c86 | 5148 | val = insn_get(env, s, ot); |
2c0262af FB |
5149 | gen_op_movl_T0_im(val); |
5150 | if (mod != 3) | |
57fec1fe | 5151 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 5152 | else |
57fec1fe | 5153 | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); |
2c0262af FB |
5154 | break; |
5155 | case 0x8a: | |
5156 | case 0x8b: /* mov Ev, Gv */ | |
5157 | if ((b & 1) == 0) | |
5158 | ot = OT_BYTE; | |
5159 | else | |
14ce26e7 | 5160 | ot = OT_WORD + dflag; |
0af10c86 | 5161 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5162 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5163 | |
0af10c86 | 5164 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5165 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
5166 | break; |
5167 | case 0x8e: /* mov seg, Gv */ | |
0af10c86 | 5168 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5169 | reg = (modrm >> 3) & 7; |
5170 | if (reg >= 6 || reg == R_CS) | |
5171 | goto illegal_op; | |
0af10c86 | 5172 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
2c0262af FB |
5173 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); |
5174 | if (reg == R_SS) { | |
5175 | /* if reg == SS, inhibit interrupts/trace */ | |
a2cc3b24 FB |
5176 | /* If several instructions disable interrupts, only the |
5177 | _first_ does it */ | |
5178 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5179 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5180 | s->tf = 0; |
5181 | } | |
5182 | if (s->is_jmp) { | |
14ce26e7 | 5183 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5184 | gen_eob(s); |
5185 | } | |
5186 | break; | |
5187 | case 0x8c: /* mov Gv, seg */ | |
0af10c86 | 5188 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5189 | reg = (modrm >> 3) & 7; |
5190 | mod = (modrm >> 6) & 3; | |
5191 | if (reg >= 6) | |
5192 | goto illegal_op; | |
5193 | gen_op_movl_T0_seg(reg); | |
14ce26e7 FB |
5194 | if (mod == 3) |
5195 | ot = OT_WORD + dflag; | |
5196 | else | |
5197 | ot = OT_WORD; | |
0af10c86 | 5198 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
5199 | break; |
5200 | ||
5201 | case 0x1b6: /* movzbS Gv, Eb */ | |
5202 | case 0x1b7: /* movzwS Gv, Eb */ | |
5203 | case 0x1be: /* movsbS Gv, Eb */ | |
5204 | case 0x1bf: /* movswS Gv, Eb */ | |
5205 | { | |
5206 | int d_ot; | |
5207 | /* d_ot is the size of destination */ | |
5208 | d_ot = dflag + OT_WORD; | |
5209 | /* ot is the size of source */ | |
5210 | ot = (b & 1) + OT_BYTE; | |
0af10c86 | 5211 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5212 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 5213 | mod = (modrm >> 6) & 3; |
14ce26e7 | 5214 | rm = (modrm & 7) | REX_B(s); |
3b46e624 | 5215 | |
2c0262af | 5216 | if (mod == 3) { |
57fec1fe | 5217 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
5218 | switch(ot | (b & 8)) { |
5219 | case OT_BYTE: | |
e108dd01 | 5220 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5221 | break; |
5222 | case OT_BYTE | 8: | |
e108dd01 | 5223 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5224 | break; |
5225 | case OT_WORD: | |
e108dd01 | 5226 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5227 | break; |
5228 | default: | |
5229 | case OT_WORD | 8: | |
e108dd01 | 5230 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5231 | break; |
5232 | } | |
57fec1fe | 5233 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af | 5234 | } else { |
0af10c86 | 5235 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 5236 | if (b & 8) { |
57fec1fe | 5237 | gen_op_lds_T0_A0(ot + s->mem_index); |
2c0262af | 5238 | } else { |
57fec1fe | 5239 | gen_op_ldu_T0_A0(ot + s->mem_index); |
2c0262af | 5240 | } |
57fec1fe | 5241 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5242 | } |
5243 | } | |
5244 | break; | |
5245 | ||
5246 | case 0x8d: /* lea */ | |
14ce26e7 | 5247 | ot = dflag + OT_WORD; |
0af10c86 | 5248 | modrm = cpu_ldub_code(env, s->pc++); |
3a1d9b8b FB |
5249 | mod = (modrm >> 6) & 3; |
5250 | if (mod == 3) | |
5251 | goto illegal_op; | |
14ce26e7 | 5252 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5253 | /* we must ensure that no segment is added */ |
5254 | s->override = -1; | |
5255 | val = s->addseg; | |
5256 | s->addseg = 0; | |
0af10c86 | 5257 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 5258 | s->addseg = val; |
57fec1fe | 5259 | gen_op_mov_reg_A0(ot - OT_WORD, reg); |
2c0262af | 5260 | break; |
3b46e624 | 5261 | |
2c0262af FB |
5262 | case 0xa0: /* mov EAX, Ov */ |
5263 | case 0xa1: | |
5264 | case 0xa2: /* mov Ov, EAX */ | |
5265 | case 0xa3: | |
2c0262af | 5266 | { |
14ce26e7 FB |
5267 | target_ulong offset_addr; |
5268 | ||
5269 | if ((b & 1) == 0) | |
5270 | ot = OT_BYTE; | |
5271 | else | |
5272 | ot = dflag + OT_WORD; | |
5273 | #ifdef TARGET_X86_64 | |
8f091a59 | 5274 | if (s->aflag == 2) { |
0af10c86 | 5275 | offset_addr = cpu_ldq_code(env, s->pc); |
14ce26e7 | 5276 | s->pc += 8; |
57fec1fe | 5277 | gen_op_movq_A0_im(offset_addr); |
5fafdf24 | 5278 | } else |
14ce26e7 FB |
5279 | #endif |
5280 | { | |
5281 | if (s->aflag) { | |
0af10c86 | 5282 | offset_addr = insn_get(env, s, OT_LONG); |
14ce26e7 | 5283 | } else { |
0af10c86 | 5284 | offset_addr = insn_get(env, s, OT_WORD); |
14ce26e7 FB |
5285 | } |
5286 | gen_op_movl_A0_im(offset_addr); | |
5287 | } | |
664e0f19 | 5288 | gen_add_A0_ds_seg(s); |
14ce26e7 | 5289 | if ((b & 2) == 0) { |
57fec1fe FB |
5290 | gen_op_ld_T0_A0(ot + s->mem_index); |
5291 | gen_op_mov_reg_T0(ot, R_EAX); | |
14ce26e7 | 5292 | } else { |
57fec1fe FB |
5293 | gen_op_mov_TN_reg(ot, 0, R_EAX); |
5294 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af FB |
5295 | } |
5296 | } | |
2c0262af FB |
5297 | break; |
5298 | case 0xd7: /* xlat */ | |
14ce26e7 | 5299 | #ifdef TARGET_X86_64 |
8f091a59 | 5300 | if (s->aflag == 2) { |
57fec1fe | 5301 | gen_op_movq_A0_reg(R_EBX); |
bbf662ee FB |
5302 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
5303 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5304 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
5fafdf24 | 5305 | } else |
14ce26e7 FB |
5306 | #endif |
5307 | { | |
57fec1fe | 5308 | gen_op_movl_A0_reg(R_EBX); |
bbf662ee FB |
5309 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
5310 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5311 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
14ce26e7 FB |
5312 | if (s->aflag == 0) |
5313 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
5314 | else |
5315 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
14ce26e7 | 5316 | } |
664e0f19 | 5317 | gen_add_A0_ds_seg(s); |
57fec1fe FB |
5318 | gen_op_ldu_T0_A0(OT_BYTE + s->mem_index); |
5319 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
5320 | break; |
5321 | case 0xb0 ... 0xb7: /* mov R, Ib */ | |
0af10c86 | 5322 | val = insn_get(env, s, OT_BYTE); |
2c0262af | 5323 | gen_op_movl_T0_im(val); |
57fec1fe | 5324 | gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s)); |
2c0262af FB |
5325 | break; |
5326 | case 0xb8 ... 0xbf: /* mov R, Iv */ | |
14ce26e7 FB |
5327 | #ifdef TARGET_X86_64 |
5328 | if (dflag == 2) { | |
5329 | uint64_t tmp; | |
5330 | /* 64 bit case */ | |
0af10c86 | 5331 | tmp = cpu_ldq_code(env, s->pc); |
14ce26e7 FB |
5332 | s->pc += 8; |
5333 | reg = (b & 7) | REX_B(s); | |
5334 | gen_movtl_T0_im(tmp); | |
57fec1fe | 5335 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 5336 | } else |
14ce26e7 FB |
5337 | #endif |
5338 | { | |
5339 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 5340 | val = insn_get(env, s, ot); |
14ce26e7 FB |
5341 | reg = (b & 7) | REX_B(s); |
5342 | gen_op_movl_T0_im(val); | |
57fec1fe | 5343 | gen_op_mov_reg_T0(ot, reg); |
14ce26e7 | 5344 | } |
2c0262af FB |
5345 | break; |
5346 | ||
5347 | case 0x91 ... 0x97: /* xchg R, EAX */ | |
7418027e | 5348 | do_xchg_reg_eax: |
14ce26e7 FB |
5349 | ot = dflag + OT_WORD; |
5350 | reg = (b & 7) | REX_B(s); | |
2c0262af FB |
5351 | rm = R_EAX; |
5352 | goto do_xchg_reg; | |
5353 | case 0x86: | |
5354 | case 0x87: /* xchg Ev, Gv */ | |
5355 | if ((b & 1) == 0) | |
5356 | ot = OT_BYTE; | |
5357 | else | |
14ce26e7 | 5358 | ot = dflag + OT_WORD; |
0af10c86 | 5359 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5360 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5361 | mod = (modrm >> 6) & 3; |
5362 | if (mod == 3) { | |
14ce26e7 | 5363 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 5364 | do_xchg_reg: |
57fec1fe FB |
5365 | gen_op_mov_TN_reg(ot, 0, reg); |
5366 | gen_op_mov_TN_reg(ot, 1, rm); | |
5367 | gen_op_mov_reg_T0(ot, rm); | |
5368 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af | 5369 | } else { |
0af10c86 | 5370 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 5371 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af FB |
5372 | /* for xchg, lock is implicit */ |
5373 | if (!(prefixes & PREFIX_LOCK)) | |
a7812ae4 | 5374 | gen_helper_lock(); |
57fec1fe FB |
5375 | gen_op_ld_T1_A0(ot + s->mem_index); |
5376 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 5377 | if (!(prefixes & PREFIX_LOCK)) |
a7812ae4 | 5378 | gen_helper_unlock(); |
57fec1fe | 5379 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5380 | } |
5381 | break; | |
5382 | case 0xc4: /* les Gv */ | |
14ce26e7 FB |
5383 | if (CODE64(s)) |
5384 | goto illegal_op; | |
2c0262af FB |
5385 | op = R_ES; |
5386 | goto do_lxx; | |
5387 | case 0xc5: /* lds Gv */ | |
14ce26e7 FB |
5388 | if (CODE64(s)) |
5389 | goto illegal_op; | |
2c0262af FB |
5390 | op = R_DS; |
5391 | goto do_lxx; | |
5392 | case 0x1b2: /* lss Gv */ | |
5393 | op = R_SS; | |
5394 | goto do_lxx; | |
5395 | case 0x1b4: /* lfs Gv */ | |
5396 | op = R_FS; | |
5397 | goto do_lxx; | |
5398 | case 0x1b5: /* lgs Gv */ | |
5399 | op = R_GS; | |
5400 | do_lxx: | |
5401 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 5402 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 5403 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5404 | mod = (modrm >> 6) & 3; |
5405 | if (mod == 3) | |
5406 | goto illegal_op; | |
0af10c86 | 5407 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 5408 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 5409 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
2c0262af | 5410 | /* load the segment first to handle exceptions properly */ |
57fec1fe | 5411 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5412 | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
5413 | /* then put the data */ | |
57fec1fe | 5414 | gen_op_mov_reg_T1(ot, reg); |
2c0262af | 5415 | if (s->is_jmp) { |
14ce26e7 | 5416 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5417 | gen_eob(s); |
5418 | } | |
5419 | break; | |
3b46e624 | 5420 | |
2c0262af FB |
5421 | /************************/ |
5422 | /* shifts */ | |
5423 | case 0xc0: | |
5424 | case 0xc1: | |
5425 | /* shift Ev,Ib */ | |
5426 | shift = 2; | |
5427 | grp2: | |
5428 | { | |
5429 | if ((b & 1) == 0) | |
5430 | ot = OT_BYTE; | |
5431 | else | |
14ce26e7 | 5432 | ot = dflag + OT_WORD; |
3b46e624 | 5433 | |
0af10c86 | 5434 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5435 | mod = (modrm >> 6) & 3; |
2c0262af | 5436 | op = (modrm >> 3) & 7; |
3b46e624 | 5437 | |
2c0262af | 5438 | if (mod != 3) { |
14ce26e7 FB |
5439 | if (shift == 2) { |
5440 | s->rip_offset = 1; | |
5441 | } | |
0af10c86 | 5442 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
5443 | opreg = OR_TMP0; |
5444 | } else { | |
14ce26e7 | 5445 | opreg = (modrm & 7) | REX_B(s); |
2c0262af FB |
5446 | } |
5447 | ||
5448 | /* simpler op */ | |
5449 | if (shift == 0) { | |
5450 | gen_shift(s, op, ot, opreg, OR_ECX); | |
5451 | } else { | |
5452 | if (shift == 2) { | |
0af10c86 | 5453 | shift = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5454 | } |
5455 | gen_shifti(s, op, ot, opreg, shift); | |
5456 | } | |
5457 | } | |
5458 | break; | |
5459 | case 0xd0: | |
5460 | case 0xd1: | |
5461 | /* shift Ev,1 */ | |
5462 | shift = 1; | |
5463 | goto grp2; | |
5464 | case 0xd2: | |
5465 | case 0xd3: | |
5466 | /* shift Ev,cl */ | |
5467 | shift = 0; | |
5468 | goto grp2; | |
5469 | ||
5470 | case 0x1a4: /* shld imm */ | |
5471 | op = 0; | |
5472 | shift = 1; | |
5473 | goto do_shiftd; | |
5474 | case 0x1a5: /* shld cl */ | |
5475 | op = 0; | |
5476 | shift = 0; | |
5477 | goto do_shiftd; | |
5478 | case 0x1ac: /* shrd imm */ | |
5479 | op = 1; | |
5480 | shift = 1; | |
5481 | goto do_shiftd; | |
5482 | case 0x1ad: /* shrd cl */ | |
5483 | op = 1; | |
5484 | shift = 0; | |
5485 | do_shiftd: | |
14ce26e7 | 5486 | ot = dflag + OT_WORD; |
0af10c86 | 5487 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 5488 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5489 | rm = (modrm & 7) | REX_B(s); |
5490 | reg = ((modrm >> 3) & 7) | rex_r; | |
2c0262af | 5491 | if (mod != 3) { |
0af10c86 | 5492 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
b6abf97d | 5493 | opreg = OR_TMP0; |
2c0262af | 5494 | } else { |
b6abf97d | 5495 | opreg = rm; |
2c0262af | 5496 | } |
57fec1fe | 5497 | gen_op_mov_TN_reg(ot, 1, reg); |
3b46e624 | 5498 | |
2c0262af | 5499 | if (shift) { |
0af10c86 | 5500 | val = cpu_ldub_code(env, s->pc++); |
b6abf97d | 5501 | tcg_gen_movi_tl(cpu_T3, val); |
2c0262af | 5502 | } else { |
cc739bb0 | 5503 | tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]); |
2c0262af | 5504 | } |
b6abf97d | 5505 | gen_shiftd_rm_T1_T3(s, ot, opreg, op); |
2c0262af FB |
5506 | break; |
5507 | ||
5508 | /************************/ | |
5509 | /* floats */ | |
5fafdf24 | 5510 | case 0xd8 ... 0xdf: |
7eee2a50 FB |
5511 | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { |
5512 | /* if CR0.EM or CR0.TS are set, generate an FPU exception */ | |
5513 | /* XXX: what to do if illegal op ? */ | |
5514 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
5515 | break; | |
5516 | } | |
0af10c86 | 5517 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
5518 | mod = (modrm >> 6) & 3; |
5519 | rm = modrm & 7; | |
5520 | op = ((b & 7) << 3) | ((modrm >> 3) & 7); | |
2c0262af FB |
5521 | if (mod != 3) { |
5522 | /* memory op */ | |
0af10c86 | 5523 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
5524 | switch(op) { |
5525 | case 0x00 ... 0x07: /* fxxxs */ | |
5526 | case 0x10 ... 0x17: /* fixxxl */ | |
5527 | case 0x20 ... 0x27: /* fxxxl */ | |
5528 | case 0x30 ... 0x37: /* fixxx */ | |
5529 | { | |
5530 | int op1; | |
5531 | op1 = op & 7; | |
5532 | ||
5533 | switch(op >> 4) { | |
5534 | case 0: | |
ba7cd150 | 5535 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5536 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5537 | gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5538 | break; |
5539 | case 1: | |
ba7cd150 | 5540 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5541 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5542 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5543 | break; |
5544 | case 2: | |
b6abf97d | 5545 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5546 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5547 | gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5548 | break; |
5549 | case 3: | |
5550 | default: | |
ba7cd150 | 5551 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5552 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5553 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5554 | break; |
5555 | } | |
3b46e624 | 5556 | |
a7812ae4 | 5557 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5558 | if (op1 == 3) { |
5559 | /* fcomp needs pop */ | |
d3eb5eae | 5560 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5561 | } |
5562 | } | |
5563 | break; | |
5564 | case 0x08: /* flds */ | |
5565 | case 0x0a: /* fsts */ | |
5566 | case 0x0b: /* fstps */ | |
465e9838 FB |
5567 | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
5568 | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ | |
5569 | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ | |
2c0262af FB |
5570 | switch(op & 7) { |
5571 | case 0: | |
5572 | switch(op >> 4) { | |
5573 | case 0: | |
ba7cd150 | 5574 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5575 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5576 | gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5577 | break; |
5578 | case 1: | |
ba7cd150 | 5579 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5580 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5581 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5582 | break; |
5583 | case 2: | |
b6abf97d | 5584 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5585 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5586 | gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5587 | break; |
5588 | case 3: | |
5589 | default: | |
ba7cd150 | 5590 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5591 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5592 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5593 | break; |
5594 | } | |
5595 | break; | |
465e9838 | 5596 | case 1: |
19e6c4b8 | 5597 | /* XXX: the corresponding CPUID bit must be tested ! */ |
465e9838 FB |
5598 | switch(op >> 4) { |
5599 | case 1: | |
d3eb5eae | 5600 | gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5601 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5602 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
465e9838 FB |
5603 | break; |
5604 | case 2: | |
d3eb5eae | 5605 | gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5606 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5607 | (s->mem_index >> 2) - 1); |
465e9838 FB |
5608 | break; |
5609 | case 3: | |
5610 | default: | |
d3eb5eae | 5611 | gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5612 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5613 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
19e6c4b8 | 5614 | break; |
465e9838 | 5615 | } |
d3eb5eae | 5616 | gen_helper_fpop(cpu_env); |
465e9838 | 5617 | break; |
2c0262af FB |
5618 | default: |
5619 | switch(op >> 4) { | |
5620 | case 0: | |
d3eb5eae | 5621 | gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5622 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5623 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5624 | break; |
5625 | case 1: | |
d3eb5eae | 5626 | gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5627 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5628 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5629 | break; |
5630 | case 2: | |
d3eb5eae | 5631 | gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5632 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5633 | (s->mem_index >> 2) - 1); |
2c0262af FB |
5634 | break; |
5635 | case 3: | |
5636 | default: | |
d3eb5eae | 5637 | gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5638 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5639 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5640 | break; |
5641 | } | |
5642 | if ((op & 7) == 3) | |
d3eb5eae | 5643 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5644 | break; |
5645 | } | |
5646 | break; | |
5647 | case 0x0c: /* fldenv mem */ | |
19e6c4b8 FB |
5648 | if (s->cc_op != CC_OP_DYNAMIC) |
5649 | gen_op_set_cc_op(s->cc_op); | |
5650 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5651 | gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5652 | break; |
5653 | case 0x0d: /* fldcw mem */ | |
19e6c4b8 | 5654 | gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5655 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5656 | gen_helper_fldcw(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5657 | break; |
5658 | case 0x0e: /* fnstenv mem */ | |
19e6c4b8 FB |
5659 | if (s->cc_op != CC_OP_DYNAMIC) |
5660 | gen_op_set_cc_op(s->cc_op); | |
5661 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5662 | gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5663 | break; |
5664 | case 0x0f: /* fnstcw mem */ | |
d3eb5eae | 5665 | gen_helper_fnstcw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5666 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5667 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5668 | break; |
5669 | case 0x1d: /* fldt mem */ | |
19e6c4b8 FB |
5670 | if (s->cc_op != CC_OP_DYNAMIC) |
5671 | gen_op_set_cc_op(s->cc_op); | |
5672 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5673 | gen_helper_fldt_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5674 | break; |
5675 | case 0x1f: /* fstpt mem */ | |
19e6c4b8 FB |
5676 | if (s->cc_op != CC_OP_DYNAMIC) |
5677 | gen_op_set_cc_op(s->cc_op); | |
5678 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae BS |
5679 | gen_helper_fstt_ST0(cpu_env, cpu_A0); |
5680 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5681 | break; |
5682 | case 0x2c: /* frstor mem */ | |
19e6c4b8 FB |
5683 | if (s->cc_op != CC_OP_DYNAMIC) |
5684 | gen_op_set_cc_op(s->cc_op); | |
5685 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5686 | gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5687 | break; |
5688 | case 0x2e: /* fnsave mem */ | |
19e6c4b8 FB |
5689 | if (s->cc_op != CC_OP_DYNAMIC) |
5690 | gen_op_set_cc_op(s->cc_op); | |
5691 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5692 | gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5693 | break; |
5694 | case 0x2f: /* fnstsw mem */ | |
d3eb5eae | 5695 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5696 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5697 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5698 | break; |
5699 | case 0x3c: /* fbld */ | |
19e6c4b8 FB |
5700 | if (s->cc_op != CC_OP_DYNAMIC) |
5701 | gen_op_set_cc_op(s->cc_op); | |
5702 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5703 | gen_helper_fbld_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5704 | break; |
5705 | case 0x3e: /* fbstp */ | |
19e6c4b8 FB |
5706 | if (s->cc_op != CC_OP_DYNAMIC) |
5707 | gen_op_set_cc_op(s->cc_op); | |
5708 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae BS |
5709 | gen_helper_fbst_ST0(cpu_env, cpu_A0); |
5710 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5711 | break; |
5712 | case 0x3d: /* fildll */ | |
b6abf97d | 5713 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5714 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5715 | gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5716 | break; |
5717 | case 0x3f: /* fistpll */ | |
d3eb5eae | 5718 | gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5719 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5720 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5721 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5722 | break; |
5723 | default: | |
5724 | goto illegal_op; | |
5725 | } | |
5726 | } else { | |
5727 | /* register float ops */ | |
5728 | opreg = rm; | |
5729 | ||
5730 | switch(op) { | |
5731 | case 0x08: /* fld sti */ | |
d3eb5eae BS |
5732 | gen_helper_fpush(cpu_env); |
5733 | gen_helper_fmov_ST0_STN(cpu_env, | |
5734 | tcg_const_i32((opreg + 1) & 7)); | |
2c0262af FB |
5735 | break; |
5736 | case 0x09: /* fxchg sti */ | |
c169c906 FB |
5737 | case 0x29: /* fxchg4 sti, undocumented op */ |
5738 | case 0x39: /* fxchg7 sti, undocumented op */ | |
d3eb5eae | 5739 | gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
5740 | break; |
5741 | case 0x0a: /* grp d9/2 */ | |
5742 | switch(rm) { | |
5743 | case 0: /* fnop */ | |
023fe10d FB |
5744 | /* check exceptions (FreeBSD FPU probe) */ |
5745 | if (s->cc_op != CC_OP_DYNAMIC) | |
5746 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 5747 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5748 | gen_helper_fwait(cpu_env); |
2c0262af FB |
5749 | break; |
5750 | default: | |
5751 | goto illegal_op; | |
5752 | } | |
5753 | break; | |
5754 | case 0x0c: /* grp d9/4 */ | |
5755 | switch(rm) { | |
5756 | case 0: /* fchs */ | |
d3eb5eae | 5757 | gen_helper_fchs_ST0(cpu_env); |
2c0262af FB |
5758 | break; |
5759 | case 1: /* fabs */ | |
d3eb5eae | 5760 | gen_helper_fabs_ST0(cpu_env); |
2c0262af FB |
5761 | break; |
5762 | case 4: /* ftst */ | |
d3eb5eae BS |
5763 | gen_helper_fldz_FT0(cpu_env); |
5764 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
5765 | break; |
5766 | case 5: /* fxam */ | |
d3eb5eae | 5767 | gen_helper_fxam_ST0(cpu_env); |
2c0262af FB |
5768 | break; |
5769 | default: | |
5770 | goto illegal_op; | |
5771 | } | |
5772 | break; | |
5773 | case 0x0d: /* grp d9/5 */ | |
5774 | { | |
5775 | switch(rm) { | |
5776 | case 0: | |
d3eb5eae BS |
5777 | gen_helper_fpush(cpu_env); |
5778 | gen_helper_fld1_ST0(cpu_env); | |
2c0262af FB |
5779 | break; |
5780 | case 1: | |
d3eb5eae BS |
5781 | gen_helper_fpush(cpu_env); |
5782 | gen_helper_fldl2t_ST0(cpu_env); | |
2c0262af FB |
5783 | break; |
5784 | case 2: | |
d3eb5eae BS |
5785 | gen_helper_fpush(cpu_env); |
5786 | gen_helper_fldl2e_ST0(cpu_env); | |
2c0262af FB |
5787 | break; |
5788 | case 3: | |
d3eb5eae BS |
5789 | gen_helper_fpush(cpu_env); |
5790 | gen_helper_fldpi_ST0(cpu_env); | |
2c0262af FB |
5791 | break; |
5792 | case 4: | |
d3eb5eae BS |
5793 | gen_helper_fpush(cpu_env); |
5794 | gen_helper_fldlg2_ST0(cpu_env); | |
2c0262af FB |
5795 | break; |
5796 | case 5: | |
d3eb5eae BS |
5797 | gen_helper_fpush(cpu_env); |
5798 | gen_helper_fldln2_ST0(cpu_env); | |
2c0262af FB |
5799 | break; |
5800 | case 6: | |
d3eb5eae BS |
5801 | gen_helper_fpush(cpu_env); |
5802 | gen_helper_fldz_ST0(cpu_env); | |
2c0262af FB |
5803 | break; |
5804 | default: | |
5805 | goto illegal_op; | |
5806 | } | |
5807 | } | |
5808 | break; | |
5809 | case 0x0e: /* grp d9/6 */ | |
5810 | switch(rm) { | |
5811 | case 0: /* f2xm1 */ | |
d3eb5eae | 5812 | gen_helper_f2xm1(cpu_env); |
2c0262af FB |
5813 | break; |
5814 | case 1: /* fyl2x */ | |
d3eb5eae | 5815 | gen_helper_fyl2x(cpu_env); |
2c0262af FB |
5816 | break; |
5817 | case 2: /* fptan */ | |
d3eb5eae | 5818 | gen_helper_fptan(cpu_env); |
2c0262af FB |
5819 | break; |
5820 | case 3: /* fpatan */ | |
d3eb5eae | 5821 | gen_helper_fpatan(cpu_env); |
2c0262af FB |
5822 | break; |
5823 | case 4: /* fxtract */ | |
d3eb5eae | 5824 | gen_helper_fxtract(cpu_env); |
2c0262af FB |
5825 | break; |
5826 | case 5: /* fprem1 */ | |
d3eb5eae | 5827 | gen_helper_fprem1(cpu_env); |
2c0262af FB |
5828 | break; |
5829 | case 6: /* fdecstp */ | |
d3eb5eae | 5830 | gen_helper_fdecstp(cpu_env); |
2c0262af FB |
5831 | break; |
5832 | default: | |
5833 | case 7: /* fincstp */ | |
d3eb5eae | 5834 | gen_helper_fincstp(cpu_env); |
2c0262af FB |
5835 | break; |
5836 | } | |
5837 | break; | |
5838 | case 0x0f: /* grp d9/7 */ | |
5839 | switch(rm) { | |
5840 | case 0: /* fprem */ | |
d3eb5eae | 5841 | gen_helper_fprem(cpu_env); |
2c0262af FB |
5842 | break; |
5843 | case 1: /* fyl2xp1 */ | |
d3eb5eae | 5844 | gen_helper_fyl2xp1(cpu_env); |
2c0262af FB |
5845 | break; |
5846 | case 2: /* fsqrt */ | |
d3eb5eae | 5847 | gen_helper_fsqrt(cpu_env); |
2c0262af FB |
5848 | break; |
5849 | case 3: /* fsincos */ | |
d3eb5eae | 5850 | gen_helper_fsincos(cpu_env); |
2c0262af FB |
5851 | break; |
5852 | case 5: /* fscale */ | |
d3eb5eae | 5853 | gen_helper_fscale(cpu_env); |
2c0262af FB |
5854 | break; |
5855 | case 4: /* frndint */ | |
d3eb5eae | 5856 | gen_helper_frndint(cpu_env); |
2c0262af FB |
5857 | break; |
5858 | case 6: /* fsin */ | |
d3eb5eae | 5859 | gen_helper_fsin(cpu_env); |
2c0262af FB |
5860 | break; |
5861 | default: | |
5862 | case 7: /* fcos */ | |
d3eb5eae | 5863 | gen_helper_fcos(cpu_env); |
2c0262af FB |
5864 | break; |
5865 | } | |
5866 | break; | |
5867 | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ | |
5868 | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ | |
5869 | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ | |
5870 | { | |
5871 | int op1; | |
3b46e624 | 5872 | |
2c0262af FB |
5873 | op1 = op & 7; |
5874 | if (op >= 0x20) { | |
a7812ae4 | 5875 | gen_helper_fp_arith_STN_ST0(op1, opreg); |
2c0262af | 5876 | if (op >= 0x30) |
d3eb5eae | 5877 | gen_helper_fpop(cpu_env); |
2c0262af | 5878 | } else { |
d3eb5eae | 5879 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
a7812ae4 | 5880 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5881 | } |
5882 | } | |
5883 | break; | |
5884 | case 0x02: /* fcom */ | |
c169c906 | 5885 | case 0x22: /* fcom2, undocumented op */ |
d3eb5eae BS |
5886 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5887 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
5888 | break; |
5889 | case 0x03: /* fcomp */ | |
c169c906 FB |
5890 | case 0x23: /* fcomp3, undocumented op */ |
5891 | case 0x32: /* fcomp5, undocumented op */ | |
d3eb5eae BS |
5892 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5893 | gen_helper_fcom_ST0_FT0(cpu_env); | |
5894 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5895 | break; |
5896 | case 0x15: /* da/5 */ | |
5897 | switch(rm) { | |
5898 | case 1: /* fucompp */ | |
d3eb5eae BS |
5899 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
5900 | gen_helper_fucom_ST0_FT0(cpu_env); | |
5901 | gen_helper_fpop(cpu_env); | |
5902 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5903 | break; |
5904 | default: | |
5905 | goto illegal_op; | |
5906 | } | |
5907 | break; | |
5908 | case 0x1c: | |
5909 | switch(rm) { | |
5910 | case 0: /* feni (287 only, just do nop here) */ | |
5911 | break; | |
5912 | case 1: /* fdisi (287 only, just do nop here) */ | |
5913 | break; | |
5914 | case 2: /* fclex */ | |
d3eb5eae | 5915 | gen_helper_fclex(cpu_env); |
2c0262af FB |
5916 | break; |
5917 | case 3: /* fninit */ | |
d3eb5eae | 5918 | gen_helper_fninit(cpu_env); |
2c0262af FB |
5919 | break; |
5920 | case 4: /* fsetpm (287 only, just do nop here) */ | |
5921 | break; | |
5922 | default: | |
5923 | goto illegal_op; | |
5924 | } | |
5925 | break; | |
5926 | case 0x1d: /* fucomi */ | |
5927 | if (s->cc_op != CC_OP_DYNAMIC) | |
5928 | gen_op_set_cc_op(s->cc_op); | |
d3eb5eae BS |
5929 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5930 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
3ca51d07 | 5931 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
5932 | break; |
5933 | case 0x1e: /* fcomi */ | |
5934 | if (s->cc_op != CC_OP_DYNAMIC) | |
5935 | gen_op_set_cc_op(s->cc_op); | |
d3eb5eae BS |
5936 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5937 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
3ca51d07 | 5938 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 5939 | break; |
658c8bda | 5940 | case 0x28: /* ffree sti */ |
d3eb5eae | 5941 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
5fafdf24 | 5942 | break; |
2c0262af | 5943 | case 0x2a: /* fst sti */ |
d3eb5eae | 5944 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
5945 | break; |
5946 | case 0x2b: /* fstp sti */ | |
c169c906 FB |
5947 | case 0x0b: /* fstp1 sti, undocumented op */ |
5948 | case 0x3a: /* fstp8 sti, undocumented op */ | |
5949 | case 0x3b: /* fstp9 sti, undocumented op */ | |
d3eb5eae BS |
5950 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
5951 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5952 | break; |
5953 | case 0x2c: /* fucom st(i) */ | |
d3eb5eae BS |
5954 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5955 | gen_helper_fucom_ST0_FT0(cpu_env); | |
2c0262af FB |
5956 | break; |
5957 | case 0x2d: /* fucomp st(i) */ | |
d3eb5eae BS |
5958 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5959 | gen_helper_fucom_ST0_FT0(cpu_env); | |
5960 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5961 | break; |
5962 | case 0x33: /* de/3 */ | |
5963 | switch(rm) { | |
5964 | case 1: /* fcompp */ | |
d3eb5eae BS |
5965 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
5966 | gen_helper_fcom_ST0_FT0(cpu_env); | |
5967 | gen_helper_fpop(cpu_env); | |
5968 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5969 | break; |
5970 | default: | |
5971 | goto illegal_op; | |
5972 | } | |
5973 | break; | |
c169c906 | 5974 | case 0x38: /* ffreep sti, undocumented op */ |
d3eb5eae BS |
5975 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
5976 | gen_helper_fpop(cpu_env); | |
c169c906 | 5977 | break; |
2c0262af FB |
5978 | case 0x3c: /* df/4 */ |
5979 | switch(rm) { | |
5980 | case 0: | |
d3eb5eae | 5981 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5982 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5983 | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
2c0262af FB |
5984 | break; |
5985 | default: | |
5986 | goto illegal_op; | |
5987 | } | |
5988 | break; | |
5989 | case 0x3d: /* fucomip */ | |
5990 | if (s->cc_op != CC_OP_DYNAMIC) | |
5991 | gen_op_set_cc_op(s->cc_op); | |
d3eb5eae BS |
5992 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5993 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
5994 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 5995 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
5996 | break; |
5997 | case 0x3e: /* fcomip */ | |
5998 | if (s->cc_op != CC_OP_DYNAMIC) | |
5999 | gen_op_set_cc_op(s->cc_op); | |
d3eb5eae BS |
6000 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6001 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
6002 | gen_helper_fpop(cpu_env); | |
3ca51d07 | 6003 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af | 6004 | break; |
a2cc3b24 FB |
6005 | case 0x10 ... 0x13: /* fcmovxx */ |
6006 | case 0x18 ... 0x1b: | |
6007 | { | |
19e6c4b8 | 6008 | int op1, l1; |
d70040bc | 6009 | static const uint8_t fcmov_cc[8] = { |
a2cc3b24 FB |
6010 | (JCC_B << 1), |
6011 | (JCC_Z << 1), | |
6012 | (JCC_BE << 1), | |
6013 | (JCC_P << 1), | |
6014 | }; | |
1e4840bf | 6015 | op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); |
19e6c4b8 | 6016 | l1 = gen_new_label(); |
b27fc131 | 6017 | gen_jcc1(s, op1, l1); |
d3eb5eae | 6018 | gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
19e6c4b8 | 6019 | gen_set_label(l1); |
a2cc3b24 FB |
6020 | } |
6021 | break; | |
2c0262af FB |
6022 | default: |
6023 | goto illegal_op; | |
6024 | } | |
6025 | } | |
6026 | break; | |
6027 | /************************/ | |
6028 | /* string ops */ | |
6029 | ||
6030 | case 0xa4: /* movsS */ | |
6031 | case 0xa5: | |
6032 | if ((b & 1) == 0) | |
6033 | ot = OT_BYTE; | |
6034 | else | |
14ce26e7 | 6035 | ot = dflag + OT_WORD; |
2c0262af FB |
6036 | |
6037 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6038 | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6039 | } else { | |
6040 | gen_movs(s, ot); | |
6041 | } | |
6042 | break; | |
3b46e624 | 6043 | |
2c0262af FB |
6044 | case 0xaa: /* stosS */ |
6045 | case 0xab: | |
6046 | if ((b & 1) == 0) | |
6047 | ot = OT_BYTE; | |
6048 | else | |
14ce26e7 | 6049 | ot = dflag + OT_WORD; |
2c0262af FB |
6050 | |
6051 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6052 | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6053 | } else { | |
6054 | gen_stos(s, ot); | |
6055 | } | |
6056 | break; | |
6057 | case 0xac: /* lodsS */ | |
6058 | case 0xad: | |
6059 | if ((b & 1) == 0) | |
6060 | ot = OT_BYTE; | |
6061 | else | |
14ce26e7 | 6062 | ot = dflag + OT_WORD; |
2c0262af FB |
6063 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6064 | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6065 | } else { | |
6066 | gen_lods(s, ot); | |
6067 | } | |
6068 | break; | |
6069 | case 0xae: /* scasS */ | |
6070 | case 0xaf: | |
6071 | if ((b & 1) == 0) | |
6072 | ot = OT_BYTE; | |
6073 | else | |
14ce26e7 | 6074 | ot = dflag + OT_WORD; |
2c0262af FB |
6075 | if (prefixes & PREFIX_REPNZ) { |
6076 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6077 | } else if (prefixes & PREFIX_REPZ) { | |
6078 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6079 | } else { | |
6080 | gen_scas(s, ot); | |
2c0262af FB |
6081 | } |
6082 | break; | |
6083 | ||
6084 | case 0xa6: /* cmpsS */ | |
6085 | case 0xa7: | |
6086 | if ((b & 1) == 0) | |
6087 | ot = OT_BYTE; | |
6088 | else | |
14ce26e7 | 6089 | ot = dflag + OT_WORD; |
2c0262af FB |
6090 | if (prefixes & PREFIX_REPNZ) { |
6091 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6092 | } else if (prefixes & PREFIX_REPZ) { | |
6093 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6094 | } else { | |
6095 | gen_cmps(s, ot); | |
2c0262af FB |
6096 | } |
6097 | break; | |
6098 | case 0x6c: /* insS */ | |
6099 | case 0x6d: | |
f115e911 FB |
6100 | if ((b & 1) == 0) |
6101 | ot = OT_BYTE; | |
6102 | else | |
6103 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6104 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6105 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6106 | gen_check_io(s, ot, pc_start - s->cs_base, |
6107 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6108 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6109 | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6110 | } else { |
f115e911 | 6111 | gen_ins(s, ot); |
2e70f6ef PB |
6112 | if (use_icount) { |
6113 | gen_jmp(s, s->pc - s->cs_base); | |
6114 | } | |
2c0262af FB |
6115 | } |
6116 | break; | |
6117 | case 0x6e: /* outsS */ | |
6118 | case 0x6f: | |
f115e911 FB |
6119 | if ((b & 1) == 0) |
6120 | ot = OT_BYTE; | |
6121 | else | |
6122 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6123 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6124 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6125 | gen_check_io(s, ot, pc_start - s->cs_base, |
6126 | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6127 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6128 | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6129 | } else { |
f115e911 | 6130 | gen_outs(s, ot); |
2e70f6ef PB |
6131 | if (use_icount) { |
6132 | gen_jmp(s, s->pc - s->cs_base); | |
6133 | } | |
2c0262af FB |
6134 | } |
6135 | break; | |
6136 | ||
6137 | /************************/ | |
6138 | /* port I/O */ | |
0573fbfc | 6139 | |
2c0262af FB |
6140 | case 0xe4: |
6141 | case 0xe5: | |
f115e911 FB |
6142 | if ((b & 1) == 0) |
6143 | ot = OT_BYTE; | |
6144 | else | |
6145 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 6146 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6147 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6148 | gen_check_io(s, ot, pc_start - s->cs_base, |
6149 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6150 | if (use_icount) |
6151 | gen_io_start(); | |
b6abf97d | 6152 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6153 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6154 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6155 | if (use_icount) { |
6156 | gen_io_end(); | |
6157 | gen_jmp(s, s->pc - s->cs_base); | |
6158 | } | |
2c0262af FB |
6159 | break; |
6160 | case 0xe6: | |
6161 | case 0xe7: | |
f115e911 FB |
6162 | if ((b & 1) == 0) |
6163 | ot = OT_BYTE; | |
6164 | else | |
6165 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 6166 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6167 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6168 | gen_check_io(s, ot, pc_start - s->cs_base, |
6169 | svm_is_rep(prefixes)); | |
57fec1fe | 6170 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6171 | |
2e70f6ef PB |
6172 | if (use_icount) |
6173 | gen_io_start(); | |
b6abf97d | 6174 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6175 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6176 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6177 | if (use_icount) { |
6178 | gen_io_end(); | |
6179 | gen_jmp(s, s->pc - s->cs_base); | |
6180 | } | |
2c0262af FB |
6181 | break; |
6182 | case 0xec: | |
6183 | case 0xed: | |
f115e911 FB |
6184 | if ((b & 1) == 0) |
6185 | ot = OT_BYTE; | |
6186 | else | |
6187 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6188 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6189 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6190 | gen_check_io(s, ot, pc_start - s->cs_base, |
6191 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6192 | if (use_icount) |
6193 | gen_io_start(); | |
b6abf97d | 6194 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6195 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6196 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6197 | if (use_icount) { |
6198 | gen_io_end(); | |
6199 | gen_jmp(s, s->pc - s->cs_base); | |
6200 | } | |
2c0262af FB |
6201 | break; |
6202 | case 0xee: | |
6203 | case 0xef: | |
f115e911 FB |
6204 | if ((b & 1) == 0) |
6205 | ot = OT_BYTE; | |
6206 | else | |
6207 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6208 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6209 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6210 | gen_check_io(s, ot, pc_start - s->cs_base, |
6211 | svm_is_rep(prefixes)); | |
57fec1fe | 6212 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6213 | |
2e70f6ef PB |
6214 | if (use_icount) |
6215 | gen_io_start(); | |
b6abf97d | 6216 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6217 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6218 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6219 | if (use_icount) { |
6220 | gen_io_end(); | |
6221 | gen_jmp(s, s->pc - s->cs_base); | |
6222 | } | |
2c0262af FB |
6223 | break; |
6224 | ||
6225 | /************************/ | |
6226 | /* control */ | |
6227 | case 0xc2: /* ret im */ | |
0af10c86 | 6228 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6229 | s->pc += 2; |
6230 | gen_pop_T0(s); | |
8f091a59 FB |
6231 | if (CODE64(s) && s->dflag) |
6232 | s->dflag = 2; | |
2c0262af FB |
6233 | gen_stack_update(s, val + (2 << s->dflag)); |
6234 | if (s->dflag == 0) | |
6235 | gen_op_andl_T0_ffff(); | |
6236 | gen_op_jmp_T0(); | |
6237 | gen_eob(s); | |
6238 | break; | |
6239 | case 0xc3: /* ret */ | |
6240 | gen_pop_T0(s); | |
6241 | gen_pop_update(s); | |
6242 | if (s->dflag == 0) | |
6243 | gen_op_andl_T0_ffff(); | |
6244 | gen_op_jmp_T0(); | |
6245 | gen_eob(s); | |
6246 | break; | |
6247 | case 0xca: /* lret im */ | |
0af10c86 | 6248 | val = cpu_ldsw_code(env, s->pc); |
2c0262af FB |
6249 | s->pc += 2; |
6250 | do_lret: | |
6251 | if (s->pe && !s->vm86) { | |
6252 | if (s->cc_op != CC_OP_DYNAMIC) | |
6253 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6254 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6255 | gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6256 | tcg_const_i32(val)); |
2c0262af FB |
6257 | } else { |
6258 | gen_stack_A0(s); | |
6259 | /* pop offset */ | |
57fec1fe | 6260 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
2c0262af FB |
6261 | if (s->dflag == 0) |
6262 | gen_op_andl_T0_ffff(); | |
6263 | /* NOTE: keeping EIP updated is not a problem in case of | |
6264 | exception */ | |
6265 | gen_op_jmp_T0(); | |
6266 | /* pop selector */ | |
6267 | gen_op_addl_A0_im(2 << s->dflag); | |
57fec1fe | 6268 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
3bd7da9e | 6269 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
6270 | /* add stack offset */ |
6271 | gen_stack_update(s, val + (4 << s->dflag)); | |
6272 | } | |
6273 | gen_eob(s); | |
6274 | break; | |
6275 | case 0xcb: /* lret */ | |
6276 | val = 0; | |
6277 | goto do_lret; | |
6278 | case 0xcf: /* iret */ | |
872929aa | 6279 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); |
2c0262af FB |
6280 | if (!s->pe) { |
6281 | /* real mode */ | |
2999a0b2 | 6282 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
3ca51d07 | 6283 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 FB |
6284 | } else if (s->vm86) { |
6285 | if (s->iopl != 3) { | |
6286 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6287 | } else { | |
2999a0b2 | 6288 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
3ca51d07 | 6289 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 6290 | } |
2c0262af FB |
6291 | } else { |
6292 | if (s->cc_op != CC_OP_DYNAMIC) | |
6293 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6294 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6295 | gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6296 | tcg_const_i32(s->pc - s->cs_base)); |
3ca51d07 | 6297 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6298 | } |
6299 | gen_eob(s); | |
6300 | break; | |
6301 | case 0xe8: /* call im */ | |
6302 | { | |
14ce26e7 | 6303 | if (dflag) |
0af10c86 | 6304 | tval = (int32_t)insn_get(env, s, OT_LONG); |
14ce26e7 | 6305 | else |
0af10c86 | 6306 | tval = (int16_t)insn_get(env, s, OT_WORD); |
2c0262af | 6307 | next_eip = s->pc - s->cs_base; |
14ce26e7 | 6308 | tval += next_eip; |
2c0262af | 6309 | if (s->dflag == 0) |
14ce26e7 | 6310 | tval &= 0xffff; |
99596385 AJ |
6311 | else if(!CODE64(s)) |
6312 | tval &= 0xffffffff; | |
14ce26e7 | 6313 | gen_movtl_T0_im(next_eip); |
2c0262af | 6314 | gen_push_T0(s); |
14ce26e7 | 6315 | gen_jmp(s, tval); |
2c0262af FB |
6316 | } |
6317 | break; | |
6318 | case 0x9a: /* lcall im */ | |
6319 | { | |
6320 | unsigned int selector, offset; | |
3b46e624 | 6321 | |
14ce26e7 FB |
6322 | if (CODE64(s)) |
6323 | goto illegal_op; | |
2c0262af | 6324 | ot = dflag ? OT_LONG : OT_WORD; |
0af10c86 BS |
6325 | offset = insn_get(env, s, ot); |
6326 | selector = insn_get(env, s, OT_WORD); | |
3b46e624 | 6327 | |
2c0262af | 6328 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6329 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6330 | } |
6331 | goto do_lcall; | |
ecada8a2 | 6332 | case 0xe9: /* jmp im */ |
14ce26e7 | 6333 | if (dflag) |
0af10c86 | 6334 | tval = (int32_t)insn_get(env, s, OT_LONG); |
14ce26e7 | 6335 | else |
0af10c86 | 6336 | tval = (int16_t)insn_get(env, s, OT_WORD); |
14ce26e7 | 6337 | tval += s->pc - s->cs_base; |
2c0262af | 6338 | if (s->dflag == 0) |
14ce26e7 | 6339 | tval &= 0xffff; |
32938e12 AJ |
6340 | else if(!CODE64(s)) |
6341 | tval &= 0xffffffff; | |
14ce26e7 | 6342 | gen_jmp(s, tval); |
2c0262af FB |
6343 | break; |
6344 | case 0xea: /* ljmp im */ | |
6345 | { | |
6346 | unsigned int selector, offset; | |
6347 | ||
14ce26e7 FB |
6348 | if (CODE64(s)) |
6349 | goto illegal_op; | |
2c0262af | 6350 | ot = dflag ? OT_LONG : OT_WORD; |
0af10c86 BS |
6351 | offset = insn_get(env, s, ot); |
6352 | selector = insn_get(env, s, OT_WORD); | |
3b46e624 | 6353 | |
2c0262af | 6354 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6355 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6356 | } |
6357 | goto do_ljmp; | |
6358 | case 0xeb: /* jmp Jb */ | |
0af10c86 | 6359 | tval = (int8_t)insn_get(env, s, OT_BYTE); |
14ce26e7 | 6360 | tval += s->pc - s->cs_base; |
2c0262af | 6361 | if (s->dflag == 0) |
14ce26e7 FB |
6362 | tval &= 0xffff; |
6363 | gen_jmp(s, tval); | |
2c0262af FB |
6364 | break; |
6365 | case 0x70 ... 0x7f: /* jcc Jb */ | |
0af10c86 | 6366 | tval = (int8_t)insn_get(env, s, OT_BYTE); |
2c0262af FB |
6367 | goto do_jcc; |
6368 | case 0x180 ... 0x18f: /* jcc Jv */ | |
6369 | if (dflag) { | |
0af10c86 | 6370 | tval = (int32_t)insn_get(env, s, OT_LONG); |
2c0262af | 6371 | } else { |
0af10c86 | 6372 | tval = (int16_t)insn_get(env, s, OT_WORD); |
2c0262af FB |
6373 | } |
6374 | do_jcc: | |
6375 | next_eip = s->pc - s->cs_base; | |
14ce26e7 | 6376 | tval += next_eip; |
2c0262af | 6377 | if (s->dflag == 0) |
14ce26e7 FB |
6378 | tval &= 0xffff; |
6379 | gen_jcc(s, b, tval, next_eip); | |
2c0262af FB |
6380 | break; |
6381 | ||
6382 | case 0x190 ... 0x19f: /* setcc Gv */ | |
0af10c86 | 6383 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af | 6384 | gen_setcc(s, b); |
0af10c86 | 6385 | gen_ldst_modrm(env, s, modrm, OT_BYTE, OR_TMP0, 1); |
2c0262af FB |
6386 | break; |
6387 | case 0x140 ... 0x14f: /* cmov Gv, Ev */ | |
8e1c85e3 FB |
6388 | { |
6389 | int l1; | |
1e4840bf FB |
6390 | TCGv t0; |
6391 | ||
8e1c85e3 | 6392 | ot = dflag + OT_WORD; |
0af10c86 | 6393 | modrm = cpu_ldub_code(env, s->pc++); |
8e1c85e3 FB |
6394 | reg = ((modrm >> 3) & 7) | rex_r; |
6395 | mod = (modrm >> 6) & 3; | |
a7812ae4 | 6396 | t0 = tcg_temp_local_new(); |
8e1c85e3 | 6397 | if (mod != 3) { |
0af10c86 | 6398 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
1e4840bf | 6399 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
8e1c85e3 FB |
6400 | } else { |
6401 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 6402 | gen_op_mov_v_reg(ot, t0, rm); |
8e1c85e3 | 6403 | } |
8e1c85e3 FB |
6404 | #ifdef TARGET_X86_64 |
6405 | if (ot == OT_LONG) { | |
6406 | /* XXX: specific Intel behaviour ? */ | |
6407 | l1 = gen_new_label(); | |
b27fc131 | 6408 | gen_jcc1(s, b ^ 1, l1); |
cc739bb0 | 6409 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
8e1c85e3 | 6410 | gen_set_label(l1); |
cc739bb0 | 6411 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]); |
8e1c85e3 FB |
6412 | } else |
6413 | #endif | |
6414 | { | |
6415 | l1 = gen_new_label(); | |
b27fc131 | 6416 | gen_jcc1(s, b ^ 1, l1); |
1e4840bf | 6417 | gen_op_mov_reg_v(ot, reg, t0); |
8e1c85e3 FB |
6418 | gen_set_label(l1); |
6419 | } | |
1e4840bf | 6420 | tcg_temp_free(t0); |
2c0262af | 6421 | } |
2c0262af | 6422 | break; |
3b46e624 | 6423 | |
2c0262af FB |
6424 | /************************/ |
6425 | /* flags */ | |
6426 | case 0x9c: /* pushf */ | |
872929aa | 6427 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); |
2c0262af FB |
6428 | if (s->vm86 && s->iopl != 3) { |
6429 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6430 | } else { | |
6431 | if (s->cc_op != CC_OP_DYNAMIC) | |
6432 | gen_op_set_cc_op(s->cc_op); | |
f0967a1a | 6433 | gen_helper_read_eflags(cpu_T[0], cpu_env); |
2c0262af FB |
6434 | gen_push_T0(s); |
6435 | } | |
6436 | break; | |
6437 | case 0x9d: /* popf */ | |
872929aa | 6438 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); |
2c0262af FB |
6439 | if (s->vm86 && s->iopl != 3) { |
6440 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6441 | } else { | |
6442 | gen_pop_T0(s); | |
6443 | if (s->cpl == 0) { | |
6444 | if (s->dflag) { | |
f0967a1a BS |
6445 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6446 | tcg_const_i32((TF_MASK | AC_MASK | | |
6447 | ID_MASK | NT_MASK | | |
6448 | IF_MASK | | |
6449 | IOPL_MASK))); | |
2c0262af | 6450 | } else { |
f0967a1a BS |
6451 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6452 | tcg_const_i32((TF_MASK | AC_MASK | | |
6453 | ID_MASK | NT_MASK | | |
6454 | IF_MASK | IOPL_MASK) | |
6455 | & 0xffff)); | |
2c0262af FB |
6456 | } |
6457 | } else { | |
4136f33c FB |
6458 | if (s->cpl <= s->iopl) { |
6459 | if (s->dflag) { | |
f0967a1a BS |
6460 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6461 | tcg_const_i32((TF_MASK | | |
6462 | AC_MASK | | |
6463 | ID_MASK | | |
6464 | NT_MASK | | |
6465 | IF_MASK))); | |
4136f33c | 6466 | } else { |
f0967a1a BS |
6467 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6468 | tcg_const_i32((TF_MASK | | |
6469 | AC_MASK | | |
6470 | ID_MASK | | |
6471 | NT_MASK | | |
6472 | IF_MASK) | |
6473 | & 0xffff)); | |
4136f33c | 6474 | } |
2c0262af | 6475 | } else { |
4136f33c | 6476 | if (s->dflag) { |
f0967a1a BS |
6477 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6478 | tcg_const_i32((TF_MASK | AC_MASK | | |
6479 | ID_MASK | NT_MASK))); | |
4136f33c | 6480 | } else { |
f0967a1a BS |
6481 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6482 | tcg_const_i32((TF_MASK | AC_MASK | | |
6483 | ID_MASK | NT_MASK) | |
6484 | & 0xffff)); | |
4136f33c | 6485 | } |
2c0262af FB |
6486 | } |
6487 | } | |
6488 | gen_pop_update(s); | |
3ca51d07 | 6489 | set_cc_op(s, CC_OP_EFLAGS); |
a9321a4d | 6490 | /* abort translation because TF/AC flag may change */ |
14ce26e7 | 6491 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6492 | gen_eob(s); |
6493 | } | |
6494 | break; | |
6495 | case 0x9e: /* sahf */ | |
12e26b75 | 6496 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6497 | goto illegal_op; |
57fec1fe | 6498 | gen_op_mov_TN_reg(OT_BYTE, 0, R_AH); |
c7b3c873 | 6499 | gen_compute_eflags(s, cpu_cc_src); |
bd7a7b33 FB |
6500 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); |
6501 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); | |
6502 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); | |
2c0262af FB |
6503 | break; |
6504 | case 0x9f: /* lahf */ | |
12e26b75 | 6505 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6506 | goto illegal_op; |
c7b3c873 | 6507 | gen_compute_eflags(s, cpu_T[0]); |
bd7a7b33 FB |
6508 | /* Note: gen_compute_eflags() only gives the condition codes */ |
6509 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02); | |
57fec1fe | 6510 | gen_op_mov_reg_T0(OT_BYTE, R_AH); |
2c0262af FB |
6511 | break; |
6512 | case 0xf5: /* cmc */ | |
c7b3c873 | 6513 | gen_compute_eflags(s, cpu_cc_src); |
bd7a7b33 | 6514 | tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6515 | break; |
6516 | case 0xf8: /* clc */ | |
c7b3c873 | 6517 | gen_compute_eflags(s, cpu_cc_src); |
bd7a7b33 | 6518 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); |
2c0262af FB |
6519 | break; |
6520 | case 0xf9: /* stc */ | |
c7b3c873 | 6521 | gen_compute_eflags(s, cpu_cc_src); |
bd7a7b33 | 6522 | tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); |
2c0262af FB |
6523 | break; |
6524 | case 0xfc: /* cld */ | |
b6abf97d | 6525 | tcg_gen_movi_i32(cpu_tmp2_i32, 1); |
317ac620 | 6526 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6527 | break; |
6528 | case 0xfd: /* std */ | |
b6abf97d | 6529 | tcg_gen_movi_i32(cpu_tmp2_i32, -1); |
317ac620 | 6530 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6531 | break; |
6532 | ||
6533 | /************************/ | |
6534 | /* bit operations */ | |
6535 | case 0x1ba: /* bt/bts/btr/btc Gv, im */ | |
14ce26e7 | 6536 | ot = dflag + OT_WORD; |
0af10c86 | 6537 | modrm = cpu_ldub_code(env, s->pc++); |
33698e5f | 6538 | op = (modrm >> 3) & 7; |
2c0262af | 6539 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6540 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 6541 | if (mod != 3) { |
14ce26e7 | 6542 | s->rip_offset = 1; |
0af10c86 | 6543 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 6544 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6545 | } else { |
57fec1fe | 6546 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
6547 | } |
6548 | /* load shift */ | |
0af10c86 | 6549 | val = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
6550 | gen_op_movl_T1_im(val); |
6551 | if (op < 4) | |
6552 | goto illegal_op; | |
6553 | op -= 4; | |
f484d386 | 6554 | goto bt_op; |
2c0262af FB |
6555 | case 0x1a3: /* bt Gv, Ev */ |
6556 | op = 0; | |
6557 | goto do_btx; | |
6558 | case 0x1ab: /* bts */ | |
6559 | op = 1; | |
6560 | goto do_btx; | |
6561 | case 0x1b3: /* btr */ | |
6562 | op = 2; | |
6563 | goto do_btx; | |
6564 | case 0x1bb: /* btc */ | |
6565 | op = 3; | |
6566 | do_btx: | |
14ce26e7 | 6567 | ot = dflag + OT_WORD; |
0af10c86 | 6568 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 | 6569 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 6570 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6571 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 6572 | gen_op_mov_TN_reg(OT_LONG, 1, reg); |
2c0262af | 6573 | if (mod != 3) { |
0af10c86 | 6574 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af | 6575 | /* specific case: we need to add a displacement */ |
f484d386 FB |
6576 | gen_exts(ot, cpu_T[1]); |
6577 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); | |
6578 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); | |
6579 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe | 6580 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6581 | } else { |
57fec1fe | 6582 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 6583 | } |
f484d386 FB |
6584 | bt_op: |
6585 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); | |
6586 | switch(op) { | |
6587 | case 0: | |
6588 | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); | |
6589 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6590 | break; | |
6591 | case 1: | |
6592 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6593 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6594 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6595 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6596 | break; | |
6597 | case 2: | |
6598 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6599 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6600 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6601 | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); | |
6602 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6603 | break; | |
6604 | default: | |
6605 | case 3: | |
6606 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6607 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6608 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6609 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6610 | break; | |
6611 | } | |
3ca51d07 | 6612 | set_cc_op(s, CC_OP_SARB + ot); |
2c0262af FB |
6613 | if (op != 0) { |
6614 | if (mod != 3) | |
57fec1fe | 6615 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 6616 | else |
57fec1fe | 6617 | gen_op_mov_reg_T0(ot, rm); |
f484d386 FB |
6618 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
6619 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
2c0262af FB |
6620 | } |
6621 | break; | |
6622 | case 0x1bc: /* bsf */ | |
6623 | case 0x1bd: /* bsr */ | |
6191b059 FB |
6624 | { |
6625 | int label1; | |
1e4840bf FB |
6626 | TCGv t0; |
6627 | ||
6191b059 | 6628 | ot = dflag + OT_WORD; |
0af10c86 | 6629 | modrm = cpu_ldub_code(env, s->pc++); |
6191b059 | 6630 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 6631 | gen_ldst_modrm(env, s,modrm, ot, OR_TMP0, 0); |
6191b059 | 6632 | gen_extu(ot, cpu_T[0]); |
a7812ae4 | 6633 | t0 = tcg_temp_local_new(); |
1e4840bf | 6634 | tcg_gen_mov_tl(t0, cpu_T[0]); |
31501a71 AP |
6635 | if ((b & 1) && (prefixes & PREFIX_REPZ) && |
6636 | (s->cpuid_ext3_features & CPUID_EXT3_ABM)) { | |
6637 | switch(ot) { | |
6638 | case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0, | |
6639 | tcg_const_i32(16)); break; | |
6640 | case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0, | |
6641 | tcg_const_i32(32)); break; | |
6642 | case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0, | |
6643 | tcg_const_i32(64)); break; | |
6644 | } | |
6645 | gen_op_mov_reg_T0(ot, reg); | |
6191b059 | 6646 | } else { |
31501a71 AP |
6647 | label1 = gen_new_label(); |
6648 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6649 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1); | |
6650 | if (b & 1) { | |
6651 | gen_helper_bsr(cpu_T[0], t0); | |
6652 | } else { | |
6653 | gen_helper_bsf(cpu_T[0], t0); | |
6654 | } | |
6655 | gen_op_mov_reg_T0(ot, reg); | |
6656 | tcg_gen_movi_tl(cpu_cc_dst, 1); | |
6657 | gen_set_label(label1); | |
6658 | tcg_gen_discard_tl(cpu_cc_src); | |
3ca51d07 | 6659 | set_cc_op(s, CC_OP_LOGICB + ot); |
6191b059 | 6660 | } |
1e4840bf | 6661 | tcg_temp_free(t0); |
6191b059 | 6662 | } |
2c0262af FB |
6663 | break; |
6664 | /************************/ | |
6665 | /* bcd */ | |
6666 | case 0x27: /* daa */ | |
14ce26e7 FB |
6667 | if (CODE64(s)) |
6668 | goto illegal_op; | |
2c0262af FB |
6669 | if (s->cc_op != CC_OP_DYNAMIC) |
6670 | gen_op_set_cc_op(s->cc_op); | |
7923057b | 6671 | gen_helper_daa(cpu_env); |
3ca51d07 | 6672 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6673 | break; |
6674 | case 0x2f: /* das */ | |
14ce26e7 FB |
6675 | if (CODE64(s)) |
6676 | goto illegal_op; | |
2c0262af FB |
6677 | if (s->cc_op != CC_OP_DYNAMIC) |
6678 | gen_op_set_cc_op(s->cc_op); | |
7923057b | 6679 | gen_helper_das(cpu_env); |
3ca51d07 | 6680 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6681 | break; |
6682 | case 0x37: /* aaa */ | |
14ce26e7 FB |
6683 | if (CODE64(s)) |
6684 | goto illegal_op; | |
2c0262af FB |
6685 | if (s->cc_op != CC_OP_DYNAMIC) |
6686 | gen_op_set_cc_op(s->cc_op); | |
7923057b | 6687 | gen_helper_aaa(cpu_env); |
3ca51d07 | 6688 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6689 | break; |
6690 | case 0x3f: /* aas */ | |
14ce26e7 FB |
6691 | if (CODE64(s)) |
6692 | goto illegal_op; | |
2c0262af FB |
6693 | if (s->cc_op != CC_OP_DYNAMIC) |
6694 | gen_op_set_cc_op(s->cc_op); | |
7923057b | 6695 | gen_helper_aas(cpu_env); |
3ca51d07 | 6696 | set_cc_op(s, CC_OP_EFLAGS); |
2c0262af FB |
6697 | break; |
6698 | case 0xd4: /* aam */ | |
14ce26e7 FB |
6699 | if (CODE64(s)) |
6700 | goto illegal_op; | |
0af10c86 | 6701 | val = cpu_ldub_code(env, s->pc++); |
b6d7c3db TS |
6702 | if (val == 0) { |
6703 | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); | |
6704 | } else { | |
7923057b | 6705 | gen_helper_aam(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 6706 | set_cc_op(s, CC_OP_LOGICB); |
b6d7c3db | 6707 | } |
2c0262af FB |
6708 | break; |
6709 | case 0xd5: /* aad */ | |
14ce26e7 FB |
6710 | if (CODE64(s)) |
6711 | goto illegal_op; | |
0af10c86 | 6712 | val = cpu_ldub_code(env, s->pc++); |
7923057b | 6713 | gen_helper_aad(cpu_env, tcg_const_i32(val)); |
3ca51d07 | 6714 | set_cc_op(s, CC_OP_LOGICB); |
2c0262af FB |
6715 | break; |
6716 | /************************/ | |
6717 | /* misc */ | |
6718 | case 0x90: /* nop */ | |
ab1f142b | 6719 | /* XXX: correct lock test for all insn */ |
7418027e | 6720 | if (prefixes & PREFIX_LOCK) { |
ab1f142b | 6721 | goto illegal_op; |
7418027e RH |
6722 | } |
6723 | /* If REX_B is set, then this is xchg eax, r8d, not a nop. */ | |
6724 | if (REX_B(s)) { | |
6725 | goto do_xchg_reg_eax; | |
6726 | } | |
0573fbfc TS |
6727 | if (prefixes & PREFIX_REPZ) { |
6728 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE); | |
6729 | } | |
2c0262af FB |
6730 | break; |
6731 | case 0x9b: /* fwait */ | |
5fafdf24 | 6732 | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == |
7eee2a50 FB |
6733 | (HF_MP_MASK | HF_TS_MASK)) { |
6734 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
2ee73ac3 FB |
6735 | } else { |
6736 | if (s->cc_op != CC_OP_DYNAMIC) | |
6737 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6738 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6739 | gen_helper_fwait(cpu_env); |
7eee2a50 | 6740 | } |
2c0262af FB |
6741 | break; |
6742 | case 0xcc: /* int3 */ | |
6743 | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); | |
6744 | break; | |
6745 | case 0xcd: /* int N */ | |
0af10c86 | 6746 | val = cpu_ldub_code(env, s->pc++); |
f115e911 | 6747 | if (s->vm86 && s->iopl != 3) { |
5fafdf24 | 6748 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
f115e911 FB |
6749 | } else { |
6750 | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); | |
6751 | } | |
2c0262af FB |
6752 | break; |
6753 | case 0xce: /* into */ | |
14ce26e7 FB |
6754 | if (CODE64(s)) |
6755 | goto illegal_op; | |
2c0262af FB |
6756 | if (s->cc_op != CC_OP_DYNAMIC) |
6757 | gen_op_set_cc_op(s->cc_op); | |
a8ede8ba | 6758 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6759 | gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start)); |
2c0262af | 6760 | break; |
0b97134b | 6761 | #ifdef WANT_ICEBP |
2c0262af | 6762 | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
872929aa | 6763 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); |
aba9d61e | 6764 | #if 1 |
2c0262af | 6765 | gen_debug(s, pc_start - s->cs_base); |
aba9d61e FB |
6766 | #else |
6767 | /* start debug */ | |
0af10c86 | 6768 | tb_flush(env); |
24537a01 | 6769 | qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); |
aba9d61e | 6770 | #endif |
2c0262af | 6771 | break; |
0b97134b | 6772 | #endif |
2c0262af FB |
6773 | case 0xfa: /* cli */ |
6774 | if (!s->vm86) { | |
6775 | if (s->cpl <= s->iopl) { | |
f0967a1a | 6776 | gen_helper_cli(cpu_env); |
2c0262af FB |
6777 | } else { |
6778 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6779 | } | |
6780 | } else { | |
6781 | if (s->iopl == 3) { | |
f0967a1a | 6782 | gen_helper_cli(cpu_env); |
2c0262af FB |
6783 | } else { |
6784 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6785 | } | |
6786 | } | |
6787 | break; | |
6788 | case 0xfb: /* sti */ | |
6789 | if (!s->vm86) { | |
6790 | if (s->cpl <= s->iopl) { | |
6791 | gen_sti: | |
f0967a1a | 6792 | gen_helper_sti(cpu_env); |
2c0262af | 6793 | /* interruptions are enabled only the first insn after sti */ |
a2cc3b24 FB |
6794 | /* If several instructions disable interrupts, only the |
6795 | _first_ does it */ | |
6796 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 6797 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af | 6798 | /* give a chance to handle pending irqs */ |
14ce26e7 | 6799 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6800 | gen_eob(s); |
6801 | } else { | |
6802 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6803 | } | |
6804 | } else { | |
6805 | if (s->iopl == 3) { | |
6806 | goto gen_sti; | |
6807 | } else { | |
6808 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6809 | } | |
6810 | } | |
6811 | break; | |
6812 | case 0x62: /* bound */ | |
14ce26e7 FB |
6813 | if (CODE64(s)) |
6814 | goto illegal_op; | |
2c0262af | 6815 | ot = dflag ? OT_LONG : OT_WORD; |
0af10c86 | 6816 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
6817 | reg = (modrm >> 3) & 7; |
6818 | mod = (modrm >> 6) & 3; | |
6819 | if (mod == 3) | |
6820 | goto illegal_op; | |
57fec1fe | 6821 | gen_op_mov_TN_reg(ot, 0, reg); |
0af10c86 | 6822 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 6823 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6824 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
92fc4b58 BS |
6825 | if (ot == OT_WORD) { |
6826 | gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32); | |
6827 | } else { | |
6828 | gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32); | |
6829 | } | |
2c0262af FB |
6830 | break; |
6831 | case 0x1c8 ... 0x1cf: /* bswap reg */ | |
14ce26e7 FB |
6832 | reg = (b & 7) | REX_B(s); |
6833 | #ifdef TARGET_X86_64 | |
6834 | if (dflag == 2) { | |
57fec1fe | 6835 | gen_op_mov_TN_reg(OT_QUAD, 0, reg); |
66896cb8 | 6836 | tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); |
57fec1fe | 6837 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 6838 | } else |
8777643e | 6839 | #endif |
57fec1fe FB |
6840 | { |
6841 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
8777643e AJ |
6842 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
6843 | tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); | |
57fec1fe | 6844 | gen_op_mov_reg_T0(OT_LONG, reg); |
14ce26e7 | 6845 | } |
2c0262af FB |
6846 | break; |
6847 | case 0xd6: /* salc */ | |
14ce26e7 FB |
6848 | if (CODE64(s)) |
6849 | goto illegal_op; | |
c7b3c873 | 6850 | gen_compute_eflags_c(s, cpu_T[0]); |
bd7a7b33 FB |
6851 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
6852 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
6853 | break; |
6854 | case 0xe0: /* loopnz */ | |
6855 | case 0xe1: /* loopz */ | |
2c0262af FB |
6856 | case 0xe2: /* loop */ |
6857 | case 0xe3: /* jecxz */ | |
14ce26e7 | 6858 | { |
6e0d8677 | 6859 | int l1, l2, l3; |
14ce26e7 | 6860 | |
0af10c86 | 6861 | tval = (int8_t)insn_get(env, s, OT_BYTE); |
14ce26e7 FB |
6862 | next_eip = s->pc - s->cs_base; |
6863 | tval += next_eip; | |
6864 | if (s->dflag == 0) | |
6865 | tval &= 0xffff; | |
3b46e624 | 6866 | |
14ce26e7 FB |
6867 | l1 = gen_new_label(); |
6868 | l2 = gen_new_label(); | |
6e0d8677 | 6869 | l3 = gen_new_label(); |
14ce26e7 | 6870 | b &= 3; |
6e0d8677 FB |
6871 | switch(b) { |
6872 | case 0: /* loopnz */ | |
6873 | case 1: /* loopz */ | |
6e0d8677 FB |
6874 | gen_op_add_reg_im(s->aflag, R_ECX, -1); |
6875 | gen_op_jz_ecx(s->aflag, l3); | |
5bdb91b0 | 6876 | gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1); |
6e0d8677 FB |
6877 | break; |
6878 | case 2: /* loop */ | |
6879 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
6880 | gen_op_jnz_ecx(s->aflag, l1); | |
6881 | break; | |
6882 | default: | |
6883 | case 3: /* jcxz */ | |
6884 | gen_op_jz_ecx(s->aflag, l1); | |
6885 | break; | |
14ce26e7 FB |
6886 | } |
6887 | ||
6e0d8677 | 6888 | gen_set_label(l3); |
14ce26e7 | 6889 | gen_jmp_im(next_eip); |
8e1c85e3 | 6890 | tcg_gen_br(l2); |
6e0d8677 | 6891 | |
14ce26e7 FB |
6892 | gen_set_label(l1); |
6893 | gen_jmp_im(tval); | |
6894 | gen_set_label(l2); | |
6895 | gen_eob(s); | |
6896 | } | |
2c0262af FB |
6897 | break; |
6898 | case 0x130: /* wrmsr */ | |
6899 | case 0x132: /* rdmsr */ | |
6900 | if (s->cpl != 0) { | |
6901 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6902 | } else { | |
872929aa FB |
6903 | if (s->cc_op != CC_OP_DYNAMIC) |
6904 | gen_op_set_cc_op(s->cc_op); | |
6905 | gen_jmp_im(pc_start - s->cs_base); | |
0573fbfc | 6906 | if (b & 2) { |
4a7443be | 6907 | gen_helper_rdmsr(cpu_env); |
0573fbfc | 6908 | } else { |
4a7443be | 6909 | gen_helper_wrmsr(cpu_env); |
0573fbfc | 6910 | } |
2c0262af FB |
6911 | } |
6912 | break; | |
6913 | case 0x131: /* rdtsc */ | |
872929aa FB |
6914 | if (s->cc_op != CC_OP_DYNAMIC) |
6915 | gen_op_set_cc_op(s->cc_op); | |
ecada8a2 | 6916 | gen_jmp_im(pc_start - s->cs_base); |
efade670 PB |
6917 | if (use_icount) |
6918 | gen_io_start(); | |
4a7443be | 6919 | gen_helper_rdtsc(cpu_env); |
efade670 PB |
6920 | if (use_icount) { |
6921 | gen_io_end(); | |
6922 | gen_jmp(s, s->pc - s->cs_base); | |
6923 | } | |
2c0262af | 6924 | break; |
df01e0fc | 6925 | case 0x133: /* rdpmc */ |
872929aa FB |
6926 | if (s->cc_op != CC_OP_DYNAMIC) |
6927 | gen_op_set_cc_op(s->cc_op); | |
df01e0fc | 6928 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6929 | gen_helper_rdpmc(cpu_env); |
df01e0fc | 6930 | break; |
023fe10d | 6931 | case 0x134: /* sysenter */ |
2436b61a | 6932 | /* For Intel SYSENTER is valid on 64-bit */ |
0af10c86 | 6933 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 6934 | goto illegal_op; |
023fe10d FB |
6935 | if (!s->pe) { |
6936 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6937 | } else { | |
728d803b | 6938 | gen_update_cc_op(s); |
14ce26e7 | 6939 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6940 | gen_helper_sysenter(cpu_env); |
023fe10d FB |
6941 | gen_eob(s); |
6942 | } | |
6943 | break; | |
6944 | case 0x135: /* sysexit */ | |
2436b61a | 6945 | /* For Intel SYSEXIT is valid on 64-bit */ |
0af10c86 | 6946 | if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) |
14ce26e7 | 6947 | goto illegal_op; |
023fe10d FB |
6948 | if (!s->pe) { |
6949 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6950 | } else { | |
728d803b | 6951 | gen_update_cc_op(s); |
14ce26e7 | 6952 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6953 | gen_helper_sysexit(cpu_env, tcg_const_i32(dflag)); |
023fe10d FB |
6954 | gen_eob(s); |
6955 | } | |
6956 | break; | |
14ce26e7 FB |
6957 | #ifdef TARGET_X86_64 |
6958 | case 0x105: /* syscall */ | |
6959 | /* XXX: is it usable in real mode ? */ | |
728d803b | 6960 | gen_update_cc_op(s); |
14ce26e7 | 6961 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6962 | gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start)); |
14ce26e7 FB |
6963 | gen_eob(s); |
6964 | break; | |
6965 | case 0x107: /* sysret */ | |
6966 | if (!s->pe) { | |
6967 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6968 | } else { | |
728d803b | 6969 | gen_update_cc_op(s); |
14ce26e7 | 6970 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6971 | gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag)); |
aba9d61e | 6972 | /* condition codes are modified only in long mode */ |
3ca51d07 RH |
6973 | if (s->lma) { |
6974 | set_cc_op(s, CC_OP_EFLAGS); | |
6975 | } | |
14ce26e7 FB |
6976 | gen_eob(s); |
6977 | } | |
6978 | break; | |
6979 | #endif | |
2c0262af | 6980 | case 0x1a2: /* cpuid */ |
9575cb94 FB |
6981 | if (s->cc_op != CC_OP_DYNAMIC) |
6982 | gen_op_set_cc_op(s->cc_op); | |
6983 | gen_jmp_im(pc_start - s->cs_base); | |
4a7443be | 6984 | gen_helper_cpuid(cpu_env); |
2c0262af FB |
6985 | break; |
6986 | case 0xf4: /* hlt */ | |
6987 | if (s->cpl != 0) { | |
6988 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6989 | } else { | |
6990 | if (s->cc_op != CC_OP_DYNAMIC) | |
6991 | gen_op_set_cc_op(s->cc_op); | |
94451178 | 6992 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6993 | gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); |
5779406a | 6994 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
6995 | } |
6996 | break; | |
6997 | case 0x100: | |
0af10c86 | 6998 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
6999 | mod = (modrm >> 6) & 3; |
7000 | op = (modrm >> 3) & 7; | |
7001 | switch(op) { | |
7002 | case 0: /* sldt */ | |
f115e911 FB |
7003 | if (!s->pe || s->vm86) |
7004 | goto illegal_op; | |
872929aa | 7005 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); |
651ba608 | 7006 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); |
2c0262af FB |
7007 | ot = OT_WORD; |
7008 | if (mod == 3) | |
7009 | ot += s->dflag; | |
0af10c86 | 7010 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
7011 | break; |
7012 | case 2: /* lldt */ | |
f115e911 FB |
7013 | if (!s->pe || s->vm86) |
7014 | goto illegal_op; | |
2c0262af FB |
7015 | if (s->cpl != 0) { |
7016 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7017 | } else { | |
872929aa | 7018 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); |
0af10c86 | 7019 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 7020 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7021 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7022 | gen_helper_lldt(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7023 | } |
7024 | break; | |
7025 | case 1: /* str */ | |
f115e911 FB |
7026 | if (!s->pe || s->vm86) |
7027 | goto illegal_op; | |
872929aa | 7028 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); |
651ba608 | 7029 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); |
2c0262af FB |
7030 | ot = OT_WORD; |
7031 | if (mod == 3) | |
7032 | ot += s->dflag; | |
0af10c86 | 7033 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); |
2c0262af FB |
7034 | break; |
7035 | case 3: /* ltr */ | |
f115e911 FB |
7036 | if (!s->pe || s->vm86) |
7037 | goto illegal_op; | |
2c0262af FB |
7038 | if (s->cpl != 0) { |
7039 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7040 | } else { | |
872929aa | 7041 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); |
0af10c86 | 7042 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 7043 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7044 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7045 | gen_helper_ltr(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7046 | } |
7047 | break; | |
7048 | case 4: /* verr */ | |
7049 | case 5: /* verw */ | |
f115e911 FB |
7050 | if (!s->pe || s->vm86) |
7051 | goto illegal_op; | |
0af10c86 | 7052 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
f115e911 FB |
7053 | if (s->cc_op != CC_OP_DYNAMIC) |
7054 | gen_op_set_cc_op(s->cc_op); | |
2999a0b2 BS |
7055 | if (op == 4) { |
7056 | gen_helper_verr(cpu_env, cpu_T[0]); | |
7057 | } else { | |
7058 | gen_helper_verw(cpu_env, cpu_T[0]); | |
7059 | } | |
3ca51d07 | 7060 | set_cc_op(s, CC_OP_EFLAGS); |
f115e911 | 7061 | break; |
2c0262af FB |
7062 | default: |
7063 | goto illegal_op; | |
7064 | } | |
7065 | break; | |
7066 | case 0x101: | |
0af10c86 | 7067 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7068 | mod = (modrm >> 6) & 3; |
7069 | op = (modrm >> 3) & 7; | |
3d7374c5 | 7070 | rm = modrm & 7; |
2c0262af FB |
7071 | switch(op) { |
7072 | case 0: /* sgdt */ | |
2c0262af FB |
7073 | if (mod == 3) |
7074 | goto illegal_op; | |
872929aa | 7075 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); |
0af10c86 | 7076 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
651ba608 | 7077 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); |
57fec1fe | 7078 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
aba9d61e | 7079 | gen_add_A0_im(s, 2); |
651ba608 | 7080 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); |
2c0262af FB |
7081 | if (!s->dflag) |
7082 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7083 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af | 7084 | break; |
3d7374c5 FB |
7085 | case 1: |
7086 | if (mod == 3) { | |
7087 | switch (rm) { | |
7088 | case 0: /* monitor */ | |
7089 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7090 | s->cpl != 0) | |
7091 | goto illegal_op; | |
94451178 FB |
7092 | if (s->cc_op != CC_OP_DYNAMIC) |
7093 | gen_op_set_cc_op(s->cc_op); | |
3d7374c5 FB |
7094 | gen_jmp_im(pc_start - s->cs_base); |
7095 | #ifdef TARGET_X86_64 | |
7096 | if (s->aflag == 2) { | |
bbf662ee | 7097 | gen_op_movq_A0_reg(R_EAX); |
5fafdf24 | 7098 | } else |
3d7374c5 FB |
7099 | #endif |
7100 | { | |
bbf662ee | 7101 | gen_op_movl_A0_reg(R_EAX); |
3d7374c5 FB |
7102 | if (s->aflag == 0) |
7103 | gen_op_andl_A0_ffff(); | |
7104 | } | |
7105 | gen_add_A0_ds_seg(s); | |
4a7443be | 7106 | gen_helper_monitor(cpu_env, cpu_A0); |
3d7374c5 FB |
7107 | break; |
7108 | case 1: /* mwait */ | |
7109 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7110 | s->cpl != 0) | |
7111 | goto illegal_op; | |
728d803b | 7112 | gen_update_cc_op(s); |
94451178 | 7113 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7114 | gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); |
3d7374c5 FB |
7115 | gen_eob(s); |
7116 | break; | |
a9321a4d PA |
7117 | case 2: /* clac */ |
7118 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7119 | s->cpl != 0) { | |
7120 | goto illegal_op; | |
7121 | } | |
7122 | gen_helper_clac(cpu_env); | |
7123 | gen_jmp_im(s->pc - s->cs_base); | |
7124 | gen_eob(s); | |
7125 | break; | |
7126 | case 3: /* stac */ | |
7127 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7128 | s->cpl != 0) { | |
7129 | goto illegal_op; | |
7130 | } | |
7131 | gen_helper_stac(cpu_env); | |
7132 | gen_jmp_im(s->pc - s->cs_base); | |
7133 | gen_eob(s); | |
7134 | break; | |
3d7374c5 FB |
7135 | default: |
7136 | goto illegal_op; | |
7137 | } | |
7138 | } else { /* sidt */ | |
872929aa | 7139 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); |
0af10c86 | 7140 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
651ba608 | 7141 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); |
57fec1fe | 7142 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
3d7374c5 | 7143 | gen_add_A0_im(s, 2); |
651ba608 | 7144 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); |
3d7374c5 FB |
7145 | if (!s->dflag) |
7146 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7147 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
3d7374c5 FB |
7148 | } |
7149 | break; | |
2c0262af FB |
7150 | case 2: /* lgdt */ |
7151 | case 3: /* lidt */ | |
0573fbfc | 7152 | if (mod == 3) { |
872929aa FB |
7153 | if (s->cc_op != CC_OP_DYNAMIC) |
7154 | gen_op_set_cc_op(s->cc_op); | |
7155 | gen_jmp_im(pc_start - s->cs_base); | |
0573fbfc TS |
7156 | switch(rm) { |
7157 | case 0: /* VMRUN */ | |
872929aa FB |
7158 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7159 | goto illegal_op; | |
7160 | if (s->cpl != 0) { | |
7161 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
0573fbfc | 7162 | break; |
872929aa | 7163 | } else { |
052e80d5 | 7164 | gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag), |
a7812ae4 | 7165 | tcg_const_i32(s->pc - pc_start)); |
db620f46 | 7166 | tcg_gen_exit_tb(0); |
5779406a | 7167 | s->is_jmp = DISAS_TB_JUMP; |
872929aa | 7168 | } |
0573fbfc TS |
7169 | break; |
7170 | case 1: /* VMMCALL */ | |
872929aa FB |
7171 | if (!(s->flags & HF_SVME_MASK)) |
7172 | goto illegal_op; | |
052e80d5 | 7173 | gen_helper_vmmcall(cpu_env); |
0573fbfc TS |
7174 | break; |
7175 | case 2: /* VMLOAD */ | |
872929aa FB |
7176 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7177 | goto illegal_op; | |
7178 | if (s->cpl != 0) { | |
7179 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7180 | break; | |
7181 | } else { | |
052e80d5 | 7182 | gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7183 | } |
0573fbfc TS |
7184 | break; |
7185 | case 3: /* VMSAVE */ | |
872929aa FB |
7186 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7187 | goto illegal_op; | |
7188 | if (s->cpl != 0) { | |
7189 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7190 | break; | |
7191 | } else { | |
052e80d5 | 7192 | gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7193 | } |
0573fbfc TS |
7194 | break; |
7195 | case 4: /* STGI */ | |
872929aa FB |
7196 | if ((!(s->flags & HF_SVME_MASK) && |
7197 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7198 | !s->pe) | |
7199 | goto illegal_op; | |
7200 | if (s->cpl != 0) { | |
7201 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7202 | break; | |
7203 | } else { | |
052e80d5 | 7204 | gen_helper_stgi(cpu_env); |
872929aa | 7205 | } |
0573fbfc TS |
7206 | break; |
7207 | case 5: /* CLGI */ | |
872929aa FB |
7208 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7209 | goto illegal_op; | |
7210 | if (s->cpl != 0) { | |
7211 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7212 | break; | |
7213 | } else { | |
052e80d5 | 7214 | gen_helper_clgi(cpu_env); |
872929aa | 7215 | } |
0573fbfc TS |
7216 | break; |
7217 | case 6: /* SKINIT */ | |
872929aa FB |
7218 | if ((!(s->flags & HF_SVME_MASK) && |
7219 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7220 | !s->pe) | |
7221 | goto illegal_op; | |
052e80d5 | 7222 | gen_helper_skinit(cpu_env); |
0573fbfc TS |
7223 | break; |
7224 | case 7: /* INVLPGA */ | |
872929aa FB |
7225 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7226 | goto illegal_op; | |
7227 | if (s->cpl != 0) { | |
7228 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7229 | break; | |
7230 | } else { | |
052e80d5 | 7231 | gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7232 | } |
0573fbfc TS |
7233 | break; |
7234 | default: | |
7235 | goto illegal_op; | |
7236 | } | |
7237 | } else if (s->cpl != 0) { | |
2c0262af FB |
7238 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7239 | } else { | |
872929aa FB |
7240 | gen_svm_check_intercept(s, pc_start, |
7241 | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); | |
0af10c86 | 7242 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
57fec1fe | 7243 | gen_op_ld_T1_A0(OT_WORD + s->mem_index); |
aba9d61e | 7244 | gen_add_A0_im(s, 2); |
57fec1fe | 7245 | gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af FB |
7246 | if (!s->dflag) |
7247 | gen_op_andl_T0_im(0xffffff); | |
7248 | if (op == 2) { | |
651ba608 FB |
7249 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); |
7250 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); | |
2c0262af | 7251 | } else { |
651ba608 FB |
7252 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); |
7253 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); | |
2c0262af FB |
7254 | } |
7255 | } | |
7256 | break; | |
7257 | case 4: /* smsw */ | |
872929aa | 7258 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); |
e2542fe2 | 7259 | #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN |
f60d2728 | 7260 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); |
7261 | #else | |
651ba608 | 7262 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); |
f60d2728 | 7263 | #endif |
0af10c86 | 7264 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 1); |
2c0262af FB |
7265 | break; |
7266 | case 6: /* lmsw */ | |
7267 | if (s->cpl != 0) { | |
7268 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7269 | } else { | |
872929aa | 7270 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
0af10c86 | 7271 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
4a7443be | 7272 | gen_helper_lmsw(cpu_env, cpu_T[0]); |
14ce26e7 | 7273 | gen_jmp_im(s->pc - s->cs_base); |
d71b9a8b | 7274 | gen_eob(s); |
2c0262af FB |
7275 | } |
7276 | break; | |
1b050077 AP |
7277 | case 7: |
7278 | if (mod != 3) { /* invlpg */ | |
7279 | if (s->cpl != 0) { | |
7280 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7281 | } else { | |
7282 | if (s->cc_op != CC_OP_DYNAMIC) | |
7283 | gen_op_set_cc_op(s->cc_op); | |
7284 | gen_jmp_im(pc_start - s->cs_base); | |
0af10c86 | 7285 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
4a7443be | 7286 | gen_helper_invlpg(cpu_env, cpu_A0); |
1b050077 AP |
7287 | gen_jmp_im(s->pc - s->cs_base); |
7288 | gen_eob(s); | |
7289 | } | |
2c0262af | 7290 | } else { |
1b050077 AP |
7291 | switch (rm) { |
7292 | case 0: /* swapgs */ | |
14ce26e7 | 7293 | #ifdef TARGET_X86_64 |
1b050077 AP |
7294 | if (CODE64(s)) { |
7295 | if (s->cpl != 0) { | |
7296 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7297 | } else { | |
7298 | tcg_gen_ld_tl(cpu_T[0], cpu_env, | |
7299 | offsetof(CPUX86State,segs[R_GS].base)); | |
7300 | tcg_gen_ld_tl(cpu_T[1], cpu_env, | |
7301 | offsetof(CPUX86State,kernelgsbase)); | |
7302 | tcg_gen_st_tl(cpu_T[1], cpu_env, | |
7303 | offsetof(CPUX86State,segs[R_GS].base)); | |
7304 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
7305 | offsetof(CPUX86State,kernelgsbase)); | |
7306 | } | |
5fafdf24 | 7307 | } else |
14ce26e7 FB |
7308 | #endif |
7309 | { | |
7310 | goto illegal_op; | |
7311 | } | |
1b050077 AP |
7312 | break; |
7313 | case 1: /* rdtscp */ | |
7314 | if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) | |
7315 | goto illegal_op; | |
9575cb94 FB |
7316 | if (s->cc_op != CC_OP_DYNAMIC) |
7317 | gen_op_set_cc_op(s->cc_op); | |
7318 | gen_jmp_im(pc_start - s->cs_base); | |
1b050077 AP |
7319 | if (use_icount) |
7320 | gen_io_start(); | |
4a7443be | 7321 | gen_helper_rdtscp(cpu_env); |
1b050077 AP |
7322 | if (use_icount) { |
7323 | gen_io_end(); | |
7324 | gen_jmp(s, s->pc - s->cs_base); | |
7325 | } | |
7326 | break; | |
7327 | default: | |
7328 | goto illegal_op; | |
14ce26e7 | 7329 | } |
2c0262af FB |
7330 | } |
7331 | break; | |
7332 | default: | |
7333 | goto illegal_op; | |
7334 | } | |
7335 | break; | |
3415a4dd FB |
7336 | case 0x108: /* invd */ |
7337 | case 0x109: /* wbinvd */ | |
7338 | if (s->cpl != 0) { | |
7339 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7340 | } else { | |
872929aa | 7341 | gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); |
3415a4dd FB |
7342 | /* nothing to do */ |
7343 | } | |
7344 | break; | |
14ce26e7 FB |
7345 | case 0x63: /* arpl or movslS (x86_64) */ |
7346 | #ifdef TARGET_X86_64 | |
7347 | if (CODE64(s)) { | |
7348 | int d_ot; | |
7349 | /* d_ot is the size of destination */ | |
7350 | d_ot = dflag + OT_WORD; | |
7351 | ||
0af10c86 | 7352 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7353 | reg = ((modrm >> 3) & 7) | rex_r; |
7354 | mod = (modrm >> 6) & 3; | |
7355 | rm = (modrm & 7) | REX_B(s); | |
3b46e624 | 7356 | |
14ce26e7 | 7357 | if (mod == 3) { |
57fec1fe | 7358 | gen_op_mov_TN_reg(OT_LONG, 0, rm); |
14ce26e7 FB |
7359 | /* sign extend */ |
7360 | if (d_ot == OT_QUAD) | |
e108dd01 | 7361 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
57fec1fe | 7362 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7363 | } else { |
0af10c86 | 7364 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 7365 | if (d_ot == OT_QUAD) { |
57fec1fe | 7366 | gen_op_lds_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7367 | } else { |
57fec1fe | 7368 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7369 | } |
57fec1fe | 7370 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7371 | } |
5fafdf24 | 7372 | } else |
14ce26e7 FB |
7373 | #endif |
7374 | { | |
3bd7da9e | 7375 | int label1; |
49d9fdcc | 7376 | TCGv t0, t1, t2, a0; |
1e4840bf | 7377 | |
14ce26e7 FB |
7378 | if (!s->pe || s->vm86) |
7379 | goto illegal_op; | |
a7812ae4 PB |
7380 | t0 = tcg_temp_local_new(); |
7381 | t1 = tcg_temp_local_new(); | |
7382 | t2 = tcg_temp_local_new(); | |
3bd7da9e | 7383 | ot = OT_WORD; |
0af10c86 | 7384 | modrm = cpu_ldub_code(env, s->pc++); |
14ce26e7 FB |
7385 | reg = (modrm >> 3) & 7; |
7386 | mod = (modrm >> 6) & 3; | |
7387 | rm = modrm & 7; | |
7388 | if (mod != 3) { | |
0af10c86 | 7389 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
1e4840bf | 7390 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
49d9fdcc LD |
7391 | a0 = tcg_temp_local_new(); |
7392 | tcg_gen_mov_tl(a0, cpu_A0); | |
14ce26e7 | 7393 | } else { |
1e4840bf | 7394 | gen_op_mov_v_reg(ot, t0, rm); |
49d9fdcc | 7395 | TCGV_UNUSED(a0); |
14ce26e7 | 7396 | } |
1e4840bf FB |
7397 | gen_op_mov_v_reg(ot, t1, reg); |
7398 | tcg_gen_andi_tl(cpu_tmp0, t0, 3); | |
7399 | tcg_gen_andi_tl(t1, t1, 3); | |
7400 | tcg_gen_movi_tl(t2, 0); | |
3bd7da9e | 7401 | label1 = gen_new_label(); |
1e4840bf FB |
7402 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); |
7403 | tcg_gen_andi_tl(t0, t0, ~3); | |
7404 | tcg_gen_or_tl(t0, t0, t1); | |
7405 | tcg_gen_movi_tl(t2, CC_Z); | |
3bd7da9e | 7406 | gen_set_label(label1); |
14ce26e7 | 7407 | if (mod != 3) { |
49d9fdcc LD |
7408 | gen_op_st_v(ot + s->mem_index, t0, a0); |
7409 | tcg_temp_free(a0); | |
7410 | } else { | |
1e4840bf | 7411 | gen_op_mov_reg_v(ot, rm, t0); |
14ce26e7 | 7412 | } |
c7b3c873 | 7413 | gen_compute_eflags(s, cpu_cc_src); |
3bd7da9e | 7414 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); |
1e4840bf | 7415 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); |
1e4840bf FB |
7416 | tcg_temp_free(t0); |
7417 | tcg_temp_free(t1); | |
7418 | tcg_temp_free(t2); | |
f115e911 | 7419 | } |
f115e911 | 7420 | break; |
2c0262af FB |
7421 | case 0x102: /* lar */ |
7422 | case 0x103: /* lsl */ | |
cec6843e FB |
7423 | { |
7424 | int label1; | |
1e4840bf | 7425 | TCGv t0; |
cec6843e FB |
7426 | if (!s->pe || s->vm86) |
7427 | goto illegal_op; | |
7428 | ot = dflag ? OT_LONG : OT_WORD; | |
0af10c86 | 7429 | modrm = cpu_ldub_code(env, s->pc++); |
cec6843e | 7430 | reg = ((modrm >> 3) & 7) | rex_r; |
0af10c86 | 7431 | gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); |
a7812ae4 | 7432 | t0 = tcg_temp_local_new(); |
cec6843e FB |
7433 | if (s->cc_op != CC_OP_DYNAMIC) |
7434 | gen_op_set_cc_op(s->cc_op); | |
2999a0b2 BS |
7435 | if (b == 0x102) { |
7436 | gen_helper_lar(t0, cpu_env, cpu_T[0]); | |
7437 | } else { | |
7438 | gen_helper_lsl(t0, cpu_env, cpu_T[0]); | |
7439 | } | |
cec6843e FB |
7440 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); |
7441 | label1 = gen_new_label(); | |
cb63669a | 7442 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
1e4840bf | 7443 | gen_op_mov_reg_v(ot, reg, t0); |
cec6843e | 7444 | gen_set_label(label1); |
3ca51d07 | 7445 | set_cc_op(s, CC_OP_EFLAGS); |
1e4840bf | 7446 | tcg_temp_free(t0); |
cec6843e | 7447 | } |
2c0262af FB |
7448 | break; |
7449 | case 0x118: | |
0af10c86 | 7450 | modrm = cpu_ldub_code(env, s->pc++); |
2c0262af FB |
7451 | mod = (modrm >> 6) & 3; |
7452 | op = (modrm >> 3) & 7; | |
7453 | switch(op) { | |
7454 | case 0: /* prefetchnta */ | |
7455 | case 1: /* prefetchnt0 */ | |
7456 | case 2: /* prefetchnt0 */ | |
7457 | case 3: /* prefetchnt0 */ | |
7458 | if (mod == 3) | |
7459 | goto illegal_op; | |
0af10c86 | 7460 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
2c0262af FB |
7461 | /* nothing more to do */ |
7462 | break; | |
e17a36ce | 7463 | default: /* nop (multi byte) */ |
0af10c86 | 7464 | gen_nop_modrm(env, s, modrm); |
e17a36ce | 7465 | break; |
2c0262af FB |
7466 | } |
7467 | break; | |
e17a36ce | 7468 | case 0x119 ... 0x11f: /* nop (multi byte) */ |
0af10c86 BS |
7469 | modrm = cpu_ldub_code(env, s->pc++); |
7470 | gen_nop_modrm(env, s, modrm); | |
e17a36ce | 7471 | break; |
2c0262af FB |
7472 | case 0x120: /* mov reg, crN */ |
7473 | case 0x122: /* mov crN, reg */ | |
7474 | if (s->cpl != 0) { | |
7475 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7476 | } else { | |
0af10c86 | 7477 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7478 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7479 | * AMD documentation (24594.pdf) and testing of | |
7480 | * intel 386 and 486 processors all show that the mod bits | |
7481 | * are assumed to be 1's, regardless of actual values. | |
7482 | */ | |
14ce26e7 FB |
7483 | rm = (modrm & 7) | REX_B(s); |
7484 | reg = ((modrm >> 3) & 7) | rex_r; | |
7485 | if (CODE64(s)) | |
7486 | ot = OT_QUAD; | |
7487 | else | |
7488 | ot = OT_LONG; | |
ccd59d09 AP |
7489 | if ((prefixes & PREFIX_LOCK) && (reg == 0) && |
7490 | (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { | |
7491 | reg = 8; | |
7492 | } | |
2c0262af FB |
7493 | switch(reg) { |
7494 | case 0: | |
7495 | case 2: | |
7496 | case 3: | |
7497 | case 4: | |
9230e66e | 7498 | case 8: |
872929aa FB |
7499 | if (s->cc_op != CC_OP_DYNAMIC) |
7500 | gen_op_set_cc_op(s->cc_op); | |
7501 | gen_jmp_im(pc_start - s->cs_base); | |
2c0262af | 7502 | if (b & 2) { |
57fec1fe | 7503 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be BS |
7504 | gen_helper_write_crN(cpu_env, tcg_const_i32(reg), |
7505 | cpu_T[0]); | |
14ce26e7 | 7506 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7507 | gen_eob(s); |
7508 | } else { | |
4a7443be | 7509 | gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg)); |
57fec1fe | 7510 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7511 | } |
7512 | break; | |
7513 | default: | |
7514 | goto illegal_op; | |
7515 | } | |
7516 | } | |
7517 | break; | |
7518 | case 0x121: /* mov reg, drN */ | |
7519 | case 0x123: /* mov drN, reg */ | |
7520 | if (s->cpl != 0) { | |
7521 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7522 | } else { | |
0af10c86 | 7523 | modrm = cpu_ldub_code(env, s->pc++); |
5c73b757 MO |
7524 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7525 | * AMD documentation (24594.pdf) and testing of | |
7526 | * intel 386 and 486 processors all show that the mod bits | |
7527 | * are assumed to be 1's, regardless of actual values. | |
7528 | */ | |
14ce26e7 FB |
7529 | rm = (modrm & 7) | REX_B(s); |
7530 | reg = ((modrm >> 3) & 7) | rex_r; | |
7531 | if (CODE64(s)) | |
7532 | ot = OT_QUAD; | |
7533 | else | |
7534 | ot = OT_LONG; | |
2c0262af | 7535 | /* XXX: do it dynamically with CR4.DE bit */ |
14ce26e7 | 7536 | if (reg == 4 || reg == 5 || reg >= 8) |
2c0262af FB |
7537 | goto illegal_op; |
7538 | if (b & 2) { | |
0573fbfc | 7539 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
57fec1fe | 7540 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be | 7541 | gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7542 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7543 | gen_eob(s); |
7544 | } else { | |
0573fbfc | 7545 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
651ba608 | 7546 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); |
57fec1fe | 7547 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7548 | } |
7549 | } | |
7550 | break; | |
7551 | case 0x106: /* clts */ | |
7552 | if (s->cpl != 0) { | |
7553 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7554 | } else { | |
0573fbfc | 7555 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
f0967a1a | 7556 | gen_helper_clts(cpu_env); |
7eee2a50 | 7557 | /* abort block because static cpu state changed */ |
14ce26e7 | 7558 | gen_jmp_im(s->pc - s->cs_base); |
7eee2a50 | 7559 | gen_eob(s); |
2c0262af FB |
7560 | } |
7561 | break; | |
222a3336 | 7562 | /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ |
664e0f19 FB |
7563 | case 0x1c3: /* MOVNTI reg, mem */ |
7564 | if (!(s->cpuid_features & CPUID_SSE2)) | |
14ce26e7 | 7565 | goto illegal_op; |
664e0f19 | 7566 | ot = s->dflag == 2 ? OT_QUAD : OT_LONG; |
0af10c86 | 7567 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7568 | mod = (modrm >> 6) & 3; |
7569 | if (mod == 3) | |
7570 | goto illegal_op; | |
7571 | reg = ((modrm >> 3) & 7) | rex_r; | |
7572 | /* generate a generic store */ | |
0af10c86 | 7573 | gen_ldst_modrm(env, s, modrm, ot, reg, 1); |
14ce26e7 | 7574 | break; |
664e0f19 | 7575 | case 0x1ae: |
0af10c86 | 7576 | modrm = cpu_ldub_code(env, s->pc++); |
664e0f19 FB |
7577 | mod = (modrm >> 6) & 3; |
7578 | op = (modrm >> 3) & 7; | |
7579 | switch(op) { | |
7580 | case 0: /* fxsave */ | |
5fafdf24 | 7581 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7582 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7583 | goto illegal_op; |
09d85fb8 | 7584 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7585 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7586 | break; | |
7587 | } | |
0af10c86 | 7588 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
19e6c4b8 FB |
7589 | if (s->cc_op != CC_OP_DYNAMIC) |
7590 | gen_op_set_cc_op(s->cc_op); | |
7591 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 7592 | gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2))); |
664e0f19 FB |
7593 | break; |
7594 | case 1: /* fxrstor */ | |
5fafdf24 | 7595 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7596 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7597 | goto illegal_op; |
09d85fb8 | 7598 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7599 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7600 | break; | |
7601 | } | |
0af10c86 | 7602 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
19e6c4b8 FB |
7603 | if (s->cc_op != CC_OP_DYNAMIC) |
7604 | gen_op_set_cc_op(s->cc_op); | |
7605 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae BS |
7606 | gen_helper_fxrstor(cpu_env, cpu_A0, |
7607 | tcg_const_i32((s->dflag == 2))); | |
664e0f19 FB |
7608 | break; |
7609 | case 2: /* ldmxcsr */ | |
7610 | case 3: /* stmxcsr */ | |
7611 | if (s->flags & HF_TS_MASK) { | |
7612 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7613 | break; | |
14ce26e7 | 7614 | } |
664e0f19 FB |
7615 | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) || |
7616 | mod == 3) | |
14ce26e7 | 7617 | goto illegal_op; |
0af10c86 | 7618 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
664e0f19 | 7619 | if (op == 2) { |
57fec1fe | 7620 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
20f8bd48 | 7621 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 7622 | gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); |
14ce26e7 | 7623 | } else { |
651ba608 | 7624 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
57fec1fe | 7625 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7626 | } |
664e0f19 FB |
7627 | break; |
7628 | case 5: /* lfence */ | |
7629 | case 6: /* mfence */ | |
8001c294 | 7630 | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) |
664e0f19 FB |
7631 | goto illegal_op; |
7632 | break; | |
8f091a59 FB |
7633 | case 7: /* sfence / clflush */ |
7634 | if ((modrm & 0xc7) == 0xc0) { | |
7635 | /* sfence */ | |
a35f3ec7 | 7636 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */ |
8f091a59 FB |
7637 | if (!(s->cpuid_features & CPUID_SSE)) |
7638 | goto illegal_op; | |
7639 | } else { | |
7640 | /* clflush */ | |
7641 | if (!(s->cpuid_features & CPUID_CLFLUSH)) | |
7642 | goto illegal_op; | |
0af10c86 | 7643 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8f091a59 FB |
7644 | } |
7645 | break; | |
664e0f19 | 7646 | default: |
14ce26e7 FB |
7647 | goto illegal_op; |
7648 | } | |
7649 | break; | |
a35f3ec7 | 7650 | case 0x10d: /* 3DNow! prefetch(w) */ |
0af10c86 | 7651 | modrm = cpu_ldub_code(env, s->pc++); |
a35f3ec7 AJ |
7652 | mod = (modrm >> 6) & 3; |
7653 | if (mod == 3) | |
7654 | goto illegal_op; | |
0af10c86 | 7655 | gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); |
8f091a59 FB |
7656 | /* ignore for now */ |
7657 | break; | |
3b21e03e | 7658 | case 0x1aa: /* rsm */ |
872929aa | 7659 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); |
3b21e03e FB |
7660 | if (!(s->flags & HF_SMM_MASK)) |
7661 | goto illegal_op; | |
728d803b | 7662 | gen_update_cc_op(s); |
3b21e03e | 7663 | gen_jmp_im(s->pc - s->cs_base); |
608badfc | 7664 | gen_helper_rsm(cpu_env); |
3b21e03e FB |
7665 | gen_eob(s); |
7666 | break; | |
222a3336 AZ |
7667 | case 0x1b8: /* SSE4.2 popcnt */ |
7668 | if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != | |
7669 | PREFIX_REPZ) | |
7670 | goto illegal_op; | |
7671 | if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) | |
7672 | goto illegal_op; | |
7673 | ||
0af10c86 | 7674 | modrm = cpu_ldub_code(env, s->pc++); |
8b4a3df8 | 7675 | reg = ((modrm >> 3) & 7) | rex_r; |
222a3336 AZ |
7676 | |
7677 | if (s->prefix & PREFIX_DATA) | |
7678 | ot = OT_WORD; | |
7679 | else if (s->dflag != 2) | |
7680 | ot = OT_LONG; | |
7681 | else | |
7682 | ot = OT_QUAD; | |
7683 | ||
0af10c86 | 7684 | gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); |
d3eb5eae | 7685 | gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot)); |
222a3336 | 7686 | gen_op_mov_reg_T0(ot, reg); |
fdb0d09d | 7687 | |
3ca51d07 | 7688 | set_cc_op(s, CC_OP_EFLAGS); |
222a3336 | 7689 | break; |
a35f3ec7 AJ |
7690 | case 0x10e ... 0x10f: |
7691 | /* 3DNow! instructions, ignore prefixes */ | |
7692 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); | |
664e0f19 FB |
7693 | case 0x110 ... 0x117: |
7694 | case 0x128 ... 0x12f: | |
4242b1bd | 7695 | case 0x138 ... 0x13a: |
d9f4bb27 | 7696 | case 0x150 ... 0x179: |
664e0f19 FB |
7697 | case 0x17c ... 0x17f: |
7698 | case 0x1c2: | |
7699 | case 0x1c4 ... 0x1c6: | |
7700 | case 0x1d0 ... 0x1fe: | |
0af10c86 | 7701 | gen_sse(env, s, b, pc_start, rex_r); |
664e0f19 | 7702 | break; |
2c0262af FB |
7703 | default: |
7704 | goto illegal_op; | |
7705 | } | |
7706 | /* lock generation */ | |
7707 | if (s->prefix & PREFIX_LOCK) | |
a7812ae4 | 7708 | gen_helper_unlock(); |
2c0262af FB |
7709 | return s->pc; |
7710 | illegal_op: | |
ab1f142b | 7711 | if (s->prefix & PREFIX_LOCK) |
a7812ae4 | 7712 | gen_helper_unlock(); |
2c0262af FB |
7713 | /* XXX: ensure that no lock was generated */ |
7714 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
7715 | return s->pc; | |
7716 | } | |
7717 | ||
2c0262af FB |
7718 | void optimize_flags_init(void) |
7719 | { | |
a7812ae4 PB |
7720 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7721 | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 AF |
7722 | offsetof(CPUX86State, cc_op), "cc_op"); |
7723 | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src), | |
a7812ae4 | 7724 | "cc_src"); |
317ac620 | 7725 | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst), |
a7812ae4 | 7726 | "cc_dst"); |
437a88a5 | 7727 | |
cc739bb0 LD |
7728 | #ifdef TARGET_X86_64 |
7729 | cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0, | |
317ac620 | 7730 | offsetof(CPUX86State, regs[R_EAX]), "rax"); |
cc739bb0 | 7731 | cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7732 | offsetof(CPUX86State, regs[R_ECX]), "rcx"); |
cc739bb0 | 7733 | cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7734 | offsetof(CPUX86State, regs[R_EDX]), "rdx"); |
cc739bb0 | 7735 | cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7736 | offsetof(CPUX86State, regs[R_EBX]), "rbx"); |
cc739bb0 | 7737 | cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7738 | offsetof(CPUX86State, regs[R_ESP]), "rsp"); |
cc739bb0 | 7739 | cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7740 | offsetof(CPUX86State, regs[R_EBP]), "rbp"); |
cc739bb0 | 7741 | cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7742 | offsetof(CPUX86State, regs[R_ESI]), "rsi"); |
cc739bb0 | 7743 | cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7744 | offsetof(CPUX86State, regs[R_EDI]), "rdi"); |
cc739bb0 | 7745 | cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7746 | offsetof(CPUX86State, regs[8]), "r8"); |
cc739bb0 | 7747 | cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7748 | offsetof(CPUX86State, regs[9]), "r9"); |
cc739bb0 | 7749 | cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7750 | offsetof(CPUX86State, regs[10]), "r10"); |
cc739bb0 | 7751 | cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7752 | offsetof(CPUX86State, regs[11]), "r11"); |
cc739bb0 | 7753 | cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7754 | offsetof(CPUX86State, regs[12]), "r12"); |
cc739bb0 | 7755 | cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7756 | offsetof(CPUX86State, regs[13]), "r13"); |
cc739bb0 | 7757 | cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7758 | offsetof(CPUX86State, regs[14]), "r14"); |
cc739bb0 | 7759 | cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7760 | offsetof(CPUX86State, regs[15]), "r15"); |
cc739bb0 LD |
7761 | #else |
7762 | cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 | 7763 | offsetof(CPUX86State, regs[R_EAX]), "eax"); |
cc739bb0 | 7764 | cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7765 | offsetof(CPUX86State, regs[R_ECX]), "ecx"); |
cc739bb0 | 7766 | cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7767 | offsetof(CPUX86State, regs[R_EDX]), "edx"); |
cc739bb0 | 7768 | cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7769 | offsetof(CPUX86State, regs[R_EBX]), "ebx"); |
cc739bb0 | 7770 | cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7771 | offsetof(CPUX86State, regs[R_ESP]), "esp"); |
cc739bb0 | 7772 | cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7773 | offsetof(CPUX86State, regs[R_EBP]), "ebp"); |
cc739bb0 | 7774 | cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7775 | offsetof(CPUX86State, regs[R_ESI]), "esi"); |
cc739bb0 | 7776 | cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7777 | offsetof(CPUX86State, regs[R_EDI]), "edi"); |
cc739bb0 LD |
7778 | #endif |
7779 | ||
437a88a5 | 7780 | /* register helpers */ |
a7812ae4 | 7781 | #define GEN_HELPER 2 |
437a88a5 | 7782 | #include "helper.h" |
2c0262af FB |
7783 | } |
7784 | ||
7785 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for | |
7786 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
7787 | information for each intermediate instruction. */ | |
317ac620 | 7788 | static inline void gen_intermediate_code_internal(CPUX86State *env, |
2cfc5f17 TS |
7789 | TranslationBlock *tb, |
7790 | int search_pc) | |
2c0262af FB |
7791 | { |
7792 | DisasContext dc1, *dc = &dc1; | |
14ce26e7 | 7793 | target_ulong pc_ptr; |
2c0262af | 7794 | uint16_t *gen_opc_end; |
a1d1bb31 | 7795 | CPUBreakpoint *bp; |
7f5b7d3e | 7796 | int j, lj; |
c068688b | 7797 | uint64_t flags; |
14ce26e7 FB |
7798 | target_ulong pc_start; |
7799 | target_ulong cs_base; | |
2e70f6ef PB |
7800 | int num_insns; |
7801 | int max_insns; | |
3b46e624 | 7802 | |
2c0262af | 7803 | /* generate intermediate code */ |
14ce26e7 FB |
7804 | pc_start = tb->pc; |
7805 | cs_base = tb->cs_base; | |
2c0262af | 7806 | flags = tb->flags; |
3a1d9b8b | 7807 | |
4f31916f | 7808 | dc->pe = (flags >> HF_PE_SHIFT) & 1; |
2c0262af FB |
7809 | dc->code32 = (flags >> HF_CS32_SHIFT) & 1; |
7810 | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; | |
7811 | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; | |
7812 | dc->f_st = 0; | |
7813 | dc->vm86 = (flags >> VM_SHIFT) & 1; | |
7814 | dc->cpl = (flags >> HF_CPL_SHIFT) & 3; | |
7815 | dc->iopl = (flags >> IOPL_SHIFT) & 3; | |
7816 | dc->tf = (flags >> TF_SHIFT) & 1; | |
34865134 | 7817 | dc->singlestep_enabled = env->singlestep_enabled; |
2c0262af FB |
7818 | dc->cc_op = CC_OP_DYNAMIC; |
7819 | dc->cs_base = cs_base; | |
7820 | dc->tb = tb; | |
7821 | dc->popl_esp_hack = 0; | |
7822 | /* select memory access functions */ | |
7823 | dc->mem_index = 0; | |
7824 | if (flags & HF_SOFTMMU_MASK) { | |
a9321a4d | 7825 | dc->mem_index = (cpu_mmu_index(env) + 1) << 2; |
2c0262af | 7826 | } |
14ce26e7 | 7827 | dc->cpuid_features = env->cpuid_features; |
3d7374c5 | 7828 | dc->cpuid_ext_features = env->cpuid_ext_features; |
e771edab | 7829 | dc->cpuid_ext2_features = env->cpuid_ext2_features; |
12e26b75 | 7830 | dc->cpuid_ext3_features = env->cpuid_ext3_features; |
a9321a4d | 7831 | dc->cpuid_7_0_ebx_features = env->cpuid_7_0_ebx_features; |
14ce26e7 FB |
7832 | #ifdef TARGET_X86_64 |
7833 | dc->lma = (flags >> HF_LMA_SHIFT) & 1; | |
7834 | dc->code64 = (flags >> HF_CS64_SHIFT) & 1; | |
7835 | #endif | |
7eee2a50 | 7836 | dc->flags = flags; |
a2cc3b24 FB |
7837 | dc->jmp_opt = !(dc->tf || env->singlestep_enabled || |
7838 | (flags & HF_INHIBIT_IRQ_MASK) | |
415fa2ea | 7839 | #ifndef CONFIG_SOFTMMU |
2c0262af FB |
7840 | || (flags & HF_SOFTMMU_MASK) |
7841 | #endif | |
7842 | ); | |
4f31916f FB |
7843 | #if 0 |
7844 | /* check addseg logic */ | |
dc196a57 | 7845 | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) |
4f31916f FB |
7846 | printf("ERROR addseg\n"); |
7847 | #endif | |
7848 | ||
a7812ae4 PB |
7849 | cpu_T[0] = tcg_temp_new(); |
7850 | cpu_T[1] = tcg_temp_new(); | |
7851 | cpu_A0 = tcg_temp_new(); | |
7852 | cpu_T3 = tcg_temp_new(); | |
7853 | ||
7854 | cpu_tmp0 = tcg_temp_new(); | |
7855 | cpu_tmp1_i64 = tcg_temp_new_i64(); | |
7856 | cpu_tmp2_i32 = tcg_temp_new_i32(); | |
7857 | cpu_tmp3_i32 = tcg_temp_new_i32(); | |
7858 | cpu_tmp4 = tcg_temp_new(); | |
7859 | cpu_tmp5 = tcg_temp_new(); | |
a7812ae4 PB |
7860 | cpu_ptr0 = tcg_temp_new_ptr(); |
7861 | cpu_ptr1 = tcg_temp_new_ptr(); | |
57fec1fe | 7862 | |
92414b31 | 7863 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
7864 | |
7865 | dc->is_jmp = DISAS_NEXT; | |
7866 | pc_ptr = pc_start; | |
7867 | lj = -1; | |
2e70f6ef PB |
7868 | num_insns = 0; |
7869 | max_insns = tb->cflags & CF_COUNT_MASK; | |
7870 | if (max_insns == 0) | |
7871 | max_insns = CF_COUNT_MASK; | |
2c0262af | 7872 | |
2e70f6ef | 7873 | gen_icount_start(); |
2c0262af | 7874 | for(;;) { |
72cf2d4f BS |
7875 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
7876 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a2397807 JK |
7877 | if (bp->pc == pc_ptr && |
7878 | !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { | |
2c0262af FB |
7879 | gen_debug(dc, pc_ptr - dc->cs_base); |
7880 | break; | |
7881 | } | |
7882 | } | |
7883 | } | |
7884 | if (search_pc) { | |
92414b31 | 7885 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
7886 | if (lj < j) { |
7887 | lj++; | |
7888 | while (lj < j) | |
ab1103de | 7889 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 7890 | } |
25983cad | 7891 | tcg_ctx.gen_opc_pc[lj] = pc_ptr; |
2c0262af | 7892 | gen_opc_cc_op[lj] = dc->cc_op; |
ab1103de | 7893 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 7894 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
2c0262af | 7895 | } |
2e70f6ef PB |
7896 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
7897 | gen_io_start(); | |
7898 | ||
0af10c86 | 7899 | pc_ptr = disas_insn(env, dc, pc_ptr); |
2e70f6ef | 7900 | num_insns++; |
2c0262af FB |
7901 | /* stop translation if indicated */ |
7902 | if (dc->is_jmp) | |
7903 | break; | |
7904 | /* if single step mode, we generate only one instruction and | |
7905 | generate an exception */ | |
a2cc3b24 FB |
7906 | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear |
7907 | the flag and abort the translation to give the irqs a | |
7908 | change to be happen */ | |
5fafdf24 | 7909 | if (dc->tf || dc->singlestep_enabled || |
2e70f6ef | 7910 | (flags & HF_INHIBIT_IRQ_MASK)) { |
14ce26e7 | 7911 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7912 | gen_eob(dc); |
7913 | break; | |
7914 | } | |
7915 | /* if too long translation, stop generation too */ | |
efd7f486 | 7916 | if (tcg_ctx.gen_opc_ptr >= gen_opc_end || |
2e70f6ef PB |
7917 | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || |
7918 | num_insns >= max_insns) { | |
14ce26e7 | 7919 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
7920 | gen_eob(dc); |
7921 | break; | |
7922 | } | |
1b530a6d AJ |
7923 | if (singlestep) { |
7924 | gen_jmp_im(pc_ptr - dc->cs_base); | |
7925 | gen_eob(dc); | |
7926 | break; | |
7927 | } | |
2c0262af | 7928 | } |
2e70f6ef PB |
7929 | if (tb->cflags & CF_LAST_IO) |
7930 | gen_io_end(); | |
7931 | gen_icount_end(tb, num_insns); | |
efd7f486 | 7932 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
2c0262af FB |
7933 | /* we don't forget to fill the last values */ |
7934 | if (search_pc) { | |
92414b31 | 7935 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
2c0262af FB |
7936 | lj++; |
7937 | while (lj <= j) | |
ab1103de | 7938 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
2c0262af | 7939 | } |
3b46e624 | 7940 | |
2c0262af | 7941 | #ifdef DEBUG_DISAS |
8fec2b8c | 7942 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
14ce26e7 | 7943 | int disas_flags; |
93fcfe39 AL |
7944 | qemu_log("----------------\n"); |
7945 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
14ce26e7 FB |
7946 | #ifdef TARGET_X86_64 |
7947 | if (dc->code64) | |
7948 | disas_flags = 2; | |
7949 | else | |
7950 | #endif | |
7951 | disas_flags = !dc->code32; | |
f4359b9f | 7952 | log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags); |
93fcfe39 | 7953 | qemu_log("\n"); |
2c0262af FB |
7954 | } |
7955 | #endif | |
7956 | ||
2e70f6ef | 7957 | if (!search_pc) { |
2c0262af | 7958 | tb->size = pc_ptr - pc_start; |
2e70f6ef PB |
7959 | tb->icount = num_insns; |
7960 | } | |
2c0262af FB |
7961 | } |
7962 | ||
317ac620 | 7963 | void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 7964 | { |
2cfc5f17 | 7965 | gen_intermediate_code_internal(env, tb, 0); |
2c0262af FB |
7966 | } |
7967 | ||
317ac620 | 7968 | void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 7969 | { |
2cfc5f17 | 7970 | gen_intermediate_code_internal(env, tb, 1); |
2c0262af FB |
7971 | } |
7972 | ||
317ac620 | 7973 | void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos) |
d2856f1a AJ |
7974 | { |
7975 | int cc_op; | |
7976 | #ifdef DEBUG_DISAS | |
8fec2b8c | 7977 | if (qemu_loglevel_mask(CPU_LOG_TB_OP)) { |
d2856f1a | 7978 | int i; |
93fcfe39 | 7979 | qemu_log("RESTORE:\n"); |
d2856f1a | 7980 | for(i = 0;i <= pc_pos; i++) { |
ab1103de | 7981 | if (tcg_ctx.gen_opc_instr_start[i]) { |
25983cad EV |
7982 | qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, |
7983 | tcg_ctx.gen_opc_pc[i]); | |
d2856f1a AJ |
7984 | } |
7985 | } | |
e87b7cb0 | 7986 | qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
25983cad | 7987 | pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base, |
d2856f1a AJ |
7988 | (uint32_t)tb->cs_base); |
7989 | } | |
7990 | #endif | |
25983cad | 7991 | env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base; |
d2856f1a AJ |
7992 | cc_op = gen_opc_cc_op[pc_pos]; |
7993 | if (cc_op != CC_OP_DYNAMIC) | |
7994 | env->cc_op = cc_op; | |
7995 | } |