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fc0ced2f AF |
1 | /* |
2 | * QEMU LatticeMico32 CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | ||
0347d689 | 21 | #include "cpu.h" |
fc0ced2f AF |
22 | #include "qemu-common.h" |
23 | ||
24 | ||
f45748f1 AF |
25 | static void lm32_cpu_set_pc(CPUState *cs, vaddr value) |
26 | { | |
27 | LM32CPU *cpu = LM32_CPU(cs); | |
28 | ||
29 | cpu->env.pc = value; | |
30 | } | |
31 | ||
fc0ced2f AF |
32 | /* CPUClass::reset() */ |
33 | static void lm32_cpu_reset(CPUState *s) | |
34 | { | |
35 | LM32CPU *cpu = LM32_CPU(s); | |
36 | LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu); | |
37 | CPULM32State *env = &cpu->env; | |
38 | ||
39 | lcc->parent_reset(s); | |
40 | ||
3eab1690 AF |
41 | /* reset cpu state */ |
42 | memset(env, 0, offsetof(CPULM32State, breakpoints)); | |
a5b0f6d5 MW |
43 | |
44 | tlb_flush(env, 1); | |
fc0ced2f AF |
45 | } |
46 | ||
9c23169e AF |
47 | static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) |
48 | { | |
14a10fc3 | 49 | CPUState *cs = CPU(dev); |
9c23169e AF |
50 | LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev); |
51 | ||
14a10fc3 AF |
52 | cpu_reset(cs); |
53 | ||
54 | qemu_init_vcpu(cs); | |
9c23169e | 55 | |
9c23169e AF |
56 | lcc->parent_realize(dev, errp); |
57 | } | |
58 | ||
8d7d505a AF |
59 | static void lm32_cpu_initfn(Object *obj) |
60 | { | |
c05efcb1 | 61 | CPUState *cs = CPU(obj); |
8d7d505a AF |
62 | LM32CPU *cpu = LM32_CPU(obj); |
63 | CPULM32State *env = &cpu->env; | |
868e2824 | 64 | static bool tcg_initialized; |
8d7d505a | 65 | |
c05efcb1 | 66 | cs->env_ptr = env; |
8d7d505a AF |
67 | cpu_exec_init(env); |
68 | ||
69 | env->flags = 0; | |
868e2824 AF |
70 | |
71 | if (tcg_enabled() && !tcg_initialized) { | |
72 | tcg_initialized = true; | |
73 | lm32_translate_init(); | |
74 | } | |
8d7d505a AF |
75 | } |
76 | ||
fc0ced2f AF |
77 | static void lm32_cpu_class_init(ObjectClass *oc, void *data) |
78 | { | |
79 | LM32CPUClass *lcc = LM32_CPU_CLASS(oc); | |
80 | CPUClass *cc = CPU_CLASS(oc); | |
9c23169e AF |
81 | DeviceClass *dc = DEVICE_CLASS(oc); |
82 | ||
83 | lcc->parent_realize = dc->realize; | |
84 | dc->realize = lm32_cpu_realizefn; | |
fc0ced2f AF |
85 | |
86 | lcc->parent_reset = cc->reset; | |
87 | cc->reset = lm32_cpu_reset; | |
97a8ea5a AF |
88 | |
89 | cc->do_interrupt = lm32_cpu_do_interrupt; | |
878096ee | 90 | cc->dump_state = lm32_cpu_dump_state; |
f45748f1 | 91 | cc->set_pc = lm32_cpu_set_pc; |
5b50e790 AF |
92 | cc->gdb_read_register = lm32_cpu_gdb_read_register; |
93 | cc->gdb_write_register = lm32_cpu_gdb_write_register; | |
00b941e5 AF |
94 | #ifndef CONFIG_USER_ONLY |
95 | cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug; | |
96 | cc->vmsd = &vmstate_lm32_cpu; | |
97 | #endif | |
a0e372f0 | 98 | cc->gdb_num_core_regs = 32 + 7; |
fc0ced2f AF |
99 | } |
100 | ||
101 | static const TypeInfo lm32_cpu_type_info = { | |
102 | .name = TYPE_LM32_CPU, | |
103 | .parent = TYPE_CPU, | |
104 | .instance_size = sizeof(LM32CPU), | |
8d7d505a | 105 | .instance_init = lm32_cpu_initfn, |
fc0ced2f AF |
106 | .abstract = false, |
107 | .class_size = sizeof(LM32CPUClass), | |
108 | .class_init = lm32_cpu_class_init, | |
109 | }; | |
110 | ||
111 | static void lm32_cpu_register_types(void) | |
112 | { | |
113 | type_register_static(&lm32_cpu_type_info); | |
114 | } | |
115 | ||
116 | type_init(lm32_cpu_register_types) |