[mirror_qemu.git] / target-m68k / helper.c

/*
 *  m68k op helpers
 *
 *  Copyright (c) 2006-2007 CodeSourcery
 *  Written by Paul Brook
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <stdio.h>
#include <string.h>

#include "config.h"
#include "cpu.h"
#include "exec-all.h"

enum m68k_cpuid {
    M68K_CPUID_M5206,
    M68K_CPUID_M5208,
    M68K_CPUID_CFV4E,
    M68K_CPUID_ANY,
};

typedef struct m68k_def_t m68k_def_t;

struct m68k_def_t {
    const char * name;
    enum m68k_cpuid id;
};

static m68k_def_t m68k_cpu_defs[] = {
    {"m5206", M68K_CPUID_M5206},
    {"m5208", M68K_CPUID_M5208},
    {"cfv4e", M68K_CPUID_CFV4E},
    {"any", M68K_CPUID_ANY},
    {NULL, 0},
};

static void m68k_set_feature(CPUM68KState *env, int feature)
{
    env->features |= (1u << feature);
}

static int cpu_m68k_set_model(CPUM68KState *env, const char *name)
{
    m68k_def_t *def;

    for (def = m68k_cpu_defs; def->name; def++) {
        if (strcmp(def->name, name) == 0)
            break;
    }
    if (!def->name)
        return -1;

    switch (def->id) {
    case M68K_CPUID_M5206:
        m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
        break;
    case M68K_CPUID_M5208:
        m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
        m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);
        m68k_set_feature(env, M68K_FEATURE_BRAL);
        m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
        m68k_set_feature(env, M68K_FEATURE_USP);
        break;
    case M68K_CPUID_CFV4E:
        m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
        m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
        m68k_set_feature(env, M68K_FEATURE_BRAL);
        m68k_set_feature(env, M68K_FEATURE_CF_FPU);
        m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
        m68k_set_feature(env, M68K_FEATURE_USP);
        break;
    case M68K_CPUID_ANY:
        m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
        m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
        m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);
        m68k_set_feature(env, M68K_FEATURE_BRAL);
        m68k_set_feature(env, M68K_FEATURE_CF_FPU);
        /* MAC and EMAC are mututally exclusive, so pick EMAC.
           It's mostly backwards compatible.  */
        m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
        m68k_set_feature(env, M68K_FEATURE_CF_EMAC_B);
        m68k_set_feature(env, M68K_FEATURE_USP);
        m68k_set_feature(env, M68K_FEATURE_EXT_FULL);
        m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
        break;
    }

    register_m68k_insns(env);
    return 0;
}

void cpu_reset(CPUM68KState *env)
{
    memset(env, 0, offsetof(CPUM68KState, breakpoints));
#if !defined (CONFIG_USER_ONLY)
    env->sr = 0x2700;
#endif
    m68k_switch_sp(env);
    /* ??? FP regs should be initialized to NaN.  */
    env->cc_op = CC_OP_FLAGS;
    /* TODO: We should set PC from the interrupt vector.  */
    env->pc = 0;
    tlb_flush(env, 1);
}

CPUM68KState *cpu_m68k_init(const char *cpu_model)
{
    CPUM68KState *env;

    env = malloc(sizeof(CPUM68KState));
    if (!env)
        return NULL;
    cpu_exec_init(env);

    env->cpu_model_str = cpu_model;

    if (cpu_m68k_set_model(env, cpu_model) < 0) {
        cpu_m68k_close(env);
        return NULL;
    }

    cpu_reset(env);
    return env;
}

void cpu_m68k_close(CPUM68KState *env)
{
    qemu_free(env);
}

void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
{
    int flags;
    uint32_t src;
    uint32_t dest;
    uint32_t tmp;

#define HIGHBIT 0x80000000u

#define SET_NZ(x) do { \
    if ((x) == 0) \
        flags |= CCF_Z; \
    else if ((int32_t)(x) < 0) \
        flags |= CCF_N; \
    } while (0)

#define SET_FLAGS_SUB(type, utype) do { \
    SET_NZ((type)dest); \
    tmp = dest + src; \
    if ((utype) tmp < (utype) src) \
        flags |= CCF_C; \
    if ((1u << (sizeof(type) * 8 - 1)) & (tmp ^ dest) & (tmp ^ src)) \
        flags |= CCF_V; \
    } while (0)

    flags = 0;
    src = env->cc_src;
    dest = env->cc_dest;
    switch (cc_op) {
    case CC_OP_FLAGS:
        flags = dest;
        break;
    case CC_OP_LOGIC:
        SET_NZ(dest);
        break;
    case CC_OP_ADD:
        SET_NZ(dest);
        if (dest < src)
            flags |= CCF_C;
        tmp = dest - src;
        if (HIGHBIT & (src ^ dest) & ~(tmp ^ src))
            flags |= CCF_V;
        break;
    case CC_OP_SUB:
        SET_FLAGS_SUB(int32_t, uint32_t);
        break;
    case CC_OP_CMPB:
        SET_FLAGS_SUB(int8_t, uint8_t);
        break;
    case CC_OP_CMPW:
        SET_FLAGS_SUB(int16_t, uint16_t);
        break;
    case CC_OP_ADDX:
        SET_NZ(dest);
        if (dest <= src)
            flags |= CCF_C;
        tmp = dest - src - 1;
        if (HIGHBIT & (src ^ dest) & ~(tmp ^ src))
            flags |= CCF_V;
        break;
    case CC_OP_SUBX:
        SET_NZ(dest);
        tmp = dest + src + 1;
        if (tmp <= src)
            flags |= CCF_C;
        if (HIGHBIT & (tmp ^ dest) & (tmp ^ src))
            flags |= CCF_V;
        break;
    case CC_OP_SHL:
        if (src >= 32) {
            SET_NZ(0);
        } else {
            tmp = dest << src;
            SET_NZ(tmp);
        }
        if (src && src <= 32 && (dest & (1 << (32 - src))))
            flags |= CCF_C;
        break;
    case CC_OP_SHR:
        if (src >= 32) {
            SET_NZ(0);
        } else {
            tmp = dest >> src;
            SET_NZ(tmp);
        }
        if (src && src <= 32 && ((dest >> (src - 1)) & 1))
            flags |= CCF_C;
        break;
    case CC_OP_SAR:
        if (src >= 32) {
            SET_NZ(-1);
        } else {
            tmp = (int32_t)dest >> src;
            SET_NZ(tmp);
        }
        if (src && src <= 32 && (((int32_t)dest >> (src - 1)) & 1))
            flags |= CCF_C;
        break;
    default:
        cpu_abort(env, "Bad CC_OP %d", cc_op);
    }
    env->cc_op = CC_OP_FLAGS;
    env->cc_dest = flags;
}

float64 helper_sub_cmpf64(CPUM68KState *env, float64 src0, float64 src1)
{
    /* ??? This may incorrectly raise exceptions.  */
    /* ??? Should flush denormals to zero.  */
    float64 res;
    res = float64_sub(src0, src1, &env->fp_status);
    if (float64_is_nan(res)) {
        /* +/-inf compares equal against itself, but sub returns nan.  */
        if (!float64_is_nan(src0)
            && !float64_is_nan(src1)) {
            res = float64_zero;
            if (float64_lt_quiet(src0, res, &env->fp_status))
                res = float64_chs(res);
        }
    }
    return res;
}

void helper_movec(CPUM68KState *env, int reg, uint32_t val)
{
    switch (reg) {
    case 0x02: /* CACR */
        env->cacr = val;
        m68k_switch_sp(env);
        break;
    case 0x04: case 0x05: case 0x06: case 0x07: /* ACR[0-3] */
        /* TODO: Implement Access Control Registers.  */
        break;
    case 0x801: /* VBR */
        env->vbr = val;
        break;
    /* TODO: Implement control registers.  */
    default:
        cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n",
                  reg, val);
    }
}

void m68k_set_macsr(CPUM68KState *env, uint32_t val)
{
    uint32_t acc;
    int8_t exthigh;
    uint8_t extlow;
    uint64_t regval;
    int i;
    if ((env->macsr ^ val) & (MACSR_FI | MACSR_SU)) {
        for (i = 0; i < 4; i++) {
            regval = env->macc[i];
            exthigh = regval >> 40;
            if (env->macsr & MACSR_FI) {
                acc = regval >> 8;
                extlow = regval;
            } else {
                acc = regval;
                extlow = regval >> 32;
            }
            if (env->macsr & MACSR_FI) {
                regval = (((uint64_t)acc) << 8) | extlow;
                regval |= ((int64_t)exthigh) << 40;
            } else if (env->macsr & MACSR_SU) {
                regval = acc | (((int64_t)extlow) << 32);
                regval |= ((int64_t)exthigh) << 40;
            } else {
                regval = acc | (((uint64_t)extlow) << 32);
                regval |= ((uint64_t)(uint8_t)exthigh) << 40;
            }
            env->macc[i] = regval;
        }
    }
    env->macsr = val;
}

void m68k_switch_sp(CPUM68KState *env)
{
    int new_sp;

    env->sp[env->current_sp] = env->aregs[7];
    new_sp = (env->sr & SR_S && env->cacr & M68K_CACR_EUSP)
             ? M68K_SSP : M68K_USP;
    env->aregs[7] = env->sp[new_sp];
    env->current_sp = new_sp;
}

/* MMU */

/* TODO: This will need fixing once the MMU is implemented.  */
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    return addr;
}

#if defined(CONFIG_USER_ONLY)

int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu)
{
    env->exception_index = EXCP_ACCESS;
    env->mmu.ar = address;
    return 1;
}

#else

int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu)
{
    int prot;

    address &= TARGET_PAGE_MASK;
    prot = PAGE_READ | PAGE_WRITE;
    return tlb_set_page(env, address, address, prot, mmu_idx, is_softmmu);
}

/* Notify CPU of a pending interrupt.  Prioritization and vectoring should
   be handled by the interrupt controller.  Real hardware only requests
   the vector when the interrupt is acknowledged by the CPU.  For
   simplicitly we calculate it when the interrupt is signalled.  */
void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector)
{
    env->pending_level = level;
    env->pending_vector = vector;
    if (level)
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
    else
        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}

#endif
Commit	Line	Data
e6e5906b PB	1	/*
e6e5906b PB	2	* m68k op helpers
5fafdf24	3	*
0633879f	4	* Copyright (c) 2006-2007 CodeSourcery
e6e5906b PB	5	* Written by Paul Brook
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <stdio.h>
0402f767	23	#include <string.h>
e6e5906b PB	24
	25	#include "config.h"
	26	#include "cpu.h"
	27	#include "exec-all.h"
	28
0402f767 PB	29	enum m68k_cpuid {
0402f767 PB	30	M68K_CPUID_M5206,
20dcee94	31	M68K_CPUID_M5208,
0402f767 PB	32	M68K_CPUID_CFV4E,
	33	M68K_CPUID_ANY,
	34	};
	35
aaed909a FB	36	typedef struct m68k_def_t m68k_def_t;
aaed909a FB	37
0402f767 PB	38	struct m68k_def_t {
	39	const char * name;
	40	enum m68k_cpuid id;
	41	};
	42
	43	static m68k_def_t m68k_cpu_defs[] = {
5fafdf24 TS	44	{"m5206", M68K_CPUID_M5206},
5fafdf24 TS	45	{"m5208", M68K_CPUID_M5208},
0402f767 PB	46	{"cfv4e", M68K_CPUID_CFV4E},
0402f767 PB	47	{"any", M68K_CPUID_ANY},
5fafdf24	48	{NULL, 0},
0402f767 PB	49	};
	50
	51	static void m68k_set_feature(CPUM68KState *env, int feature)
	52	{
	53	env->features \|= (1u << feature);
	54	}
	55
aaed909a	56	static int cpu_m68k_set_model(CPUM68KState env, const char name)
0402f767 PB	57	{
	58	m68k_def_t *def;
	59
	60	for (def = m68k_cpu_defs; def->name; def++) {
	61	if (strcmp(def->name, name) == 0)
	62	break;
	63	}
	64	if (!def->name)
aaed909a	65	return -1;
0402f767 PB	66
	67	switch (def->id) {
	68	case M68K_CPUID_M5206:
	69	m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
	70	break;
20dcee94 PB	71	case M68K_CPUID_M5208:
20dcee94 PB	72	m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
d315c888 PB	73	m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);
d315c888 PB	74	m68k_set_feature(env, M68K_FEATURE_BRAL);
20dcee94 PB	75	m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
	76	m68k_set_feature(env, M68K_FEATURE_USP);
	77	break;
0402f767 PB	78	case M68K_CPUID_CFV4E:
	79	m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
	80	m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
d315c888	81	m68k_set_feature(env, M68K_FEATURE_BRAL);
0402f767	82	m68k_set_feature(env, M68K_FEATURE_CF_FPU);
0402f767	83	m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
20dcee94	84	m68k_set_feature(env, M68K_FEATURE_USP);
0402f767 PB	85	break;
	86	case M68K_CPUID_ANY:
	87	m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
	88	m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
d315c888 PB	89	m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);
d315c888 PB	90	m68k_set_feature(env, M68K_FEATURE_BRAL);
0402f767	91	m68k_set_feature(env, M68K_FEATURE_CF_FPU);
acf930aa PB	92	/* MAC and EMAC are mututally exclusive, so pick EMAC.
acf930aa PB	93	It's mostly backwards compatible. */
0402f767	94	m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
d315c888	95	m68k_set_feature(env, M68K_FEATURE_CF_EMAC_B);
20dcee94	96	m68k_set_feature(env, M68K_FEATURE_USP);
0402f767	97	m68k_set_feature(env, M68K_FEATURE_EXT_FULL);
d315c888	98	m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
0402f767 PB	99	break;
	100	}
	101
	102	register_m68k_insns(env);
4f6cf9e8	103	return 0;
aaed909a FB	104	}
	105
	106	void cpu_reset(CPUM68KState *env)
	107	{
	108	memset(env, 0, offsetof(CPUM68KState, breakpoints));
	109	#if !defined (CONFIG_USER_ONLY)
	110	env->sr = 0x2700;
	111	#endif
	112	m68k_switch_sp(env);
	113	/* ??? FP regs should be initialized to NaN. */
	114	env->cc_op = CC_OP_FLAGS;
	115	/* TODO: We should set PC from the interrupt vector. */
	116	env->pc = 0;
	117	tlb_flush(env, 1);
	118	}
	119
	120	CPUM68KState cpu_m68k_init(const char cpu_model)
	121	{
	122	CPUM68KState *env;
	123
	124	env = malloc(sizeof(CPUM68KState));
	125	if (!env)
	126	return NULL;
	127	cpu_exec_init(env);
	128
01ba9816 TS	129	env->cpu_model_str = cpu_model;
01ba9816 TS	130
aaed909a FB	131	if (cpu_m68k_set_model(env, cpu_model) < 0) {
	132	cpu_m68k_close(env);
	133	return NULL;
	134	}
01ba9816	135
aaed909a FB	136	cpu_reset(env);
	137	return env;
	138	}
0402f767	139
aaed909a FB	140	void cpu_m68k_close(CPUM68KState *env)
	141	{
	142	qemu_free(env);
0402f767 PB	143	}
0402f767 PB	144
e6e5906b PB	145	void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
	146	{
	147	int flags;
	148	uint32_t src;
	149	uint32_t dest;
	150	uint32_t tmp;
	151
	152	#define HIGHBIT 0x80000000u
	153
	154	#define SET_NZ(x) do { \
	155	if ((x) == 0) \
	156	flags \|= CCF_Z; \
	157	else if ((int32_t)(x) < 0) \
	158	flags \|= CCF_N; \
	159	} while (0)
	160
	161	#define SET_FLAGS_SUB(type, utype) do { \
	162	SET_NZ((type)dest); \
	163	tmp = dest + src; \
	164	if ((utype) tmp < (utype) src) \
	165	flags \|= CCF_C; \
	166	if ((1u << (sizeof(type) * 8 - 1)) & (tmp ^ dest) & (tmp ^ src)) \
	167	flags \|= CCF_V; \
	168	} while (0)
	169
	170	flags = 0;
	171	src = env->cc_src;
	172	dest = env->cc_dest;
	173	switch (cc_op) {
	174	case CC_OP_FLAGS:
	175	flags = dest;
	176	break;
	177	case CC_OP_LOGIC:
	178	SET_NZ(dest);
	179	break;
	180	case CC_OP_ADD:
	181	SET_NZ(dest);
	182	if (dest < src)
	183	flags \|= CCF_C;
	184	tmp = dest - src;
	185	if (HIGHBIT & (src ^ dest) & ~(tmp ^ src))
	186	flags \|= CCF_V;
	187	break;
	188	case CC_OP_SUB:
	189	SET_FLAGS_SUB(int32_t, uint32_t);
	190	break;
	191	case CC_OP_CMPB:
	192	SET_FLAGS_SUB(int8_t, uint8_t);
	193	break;
	194	case CC_OP_CMPW:
	195	SET_FLAGS_SUB(int16_t, uint16_t);
	196	break;
	197	case CC_OP_ADDX:
	198	SET_NZ(dest);
	199	if (dest <= src)
	200	flags \|= CCF_C;
	201	tmp = dest - src - 1;
	202	if (HIGHBIT & (src ^ dest) & ~(tmp ^ src))
	203	flags \|= CCF_V;
	204	break;
	205	case CC_OP_SUBX:
	206	SET_NZ(dest);
	207	tmp = dest + src + 1;
	208	if (tmp <= src)
209	flags \|= CCF_C;
210	if (HIGHBIT & (tmp ^ dest) & (tmp ^ src))
211	flags \|= CCF_V;
212	break;
213	case CC_OP_SHL:
214	if (src >= 32) {
215	SET_NZ(0);
216	} else {
217	tmp = dest << src;
218	SET_NZ(tmp);
219	}
220	if (src && src <= 32 && (dest & (1 << (32 - src))))
221	flags \|= CCF_C;
222	break;
223	case CC_OP_SHR:
224	if (src >= 32) {
225	SET_NZ(0);
226	} else {
227	tmp = dest >> src;
228	SET_NZ(tmp);
229	}
230	if (src && src <= 32 && ((dest >> (src - 1)) & 1))
231	flags \|= CCF_C;
232	break;
233	case CC_OP_SAR:
234	if (src >= 32) {
235	SET_NZ(-1);
236	} else {
237	tmp = (int32_t)dest >> src;
238	SET_NZ(tmp);
239	}
240	if (src && src <= 32 && (((int32_t)dest >> (src - 1)) & 1))
241	flags \|= CCF_C;
242	break;
243	default:
244	cpu_abort(env, "Bad CC_OP %d", cc_op);
245	}
246	env->cc_op = CC_OP_FLAGS;
247	env->cc_dest = flags;
248	}
249
250	float64 helper_sub_cmpf64(CPUM68KState *env, float64 src0, float64 src1)
251	{
252	/* ??? This may incorrectly raise exceptions. */
253	/* ??? Should flush denormals to zero. */
254	float64 res;
255	res = float64_sub(src0, src1, &env->fp_status);
256	if (float64_is_nan(res)) {
257	/* +/-inf compares equal against itself, but sub returns nan. */
258	if (!float64_is_nan(src0)
259	&& !float64_is_nan(src1)) {
f090c9d4	260	res = float64_zero;
e6e5906b PB	261	if (float64_lt_quiet(src0, res, &env->fp_status))
	262	res = float64_chs(res);
	263	}
	264	}
	265	return res;
	266	}
0633879f PB	267
	268	void helper_movec(CPUM68KState *env, int reg, uint32_t val)
	269	{
	270	switch (reg) {
	271	case 0x02: /* CACR */
20dcee94 PB	272	env->cacr = val;
	273	m68k_switch_sp(env);
	274	break;
	275	case 0x04: case 0x05: case 0x06: case 0x07: /* ACR[0-3] */
	276	/* TODO: Implement Access Control Registers. */
0633879f PB	277	break;
	278	case 0x801: /* VBR */
	279	env->vbr = val;
	280	break;
	281	/* TODO: Implement control registers. */
	282	default:
	283	cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n",
	284	reg, val);
	285	}
	286	}
	287
acf930aa PB	288	void m68k_set_macsr(CPUM68KState *env, uint32_t val)
	289	{
	290	uint32_t acc;
	291	int8_t exthigh;
	292	uint8_t extlow;
	293	uint64_t regval;
	294	int i;
	295	if ((env->macsr ^ val) & (MACSR_FI \| MACSR_SU)) {
	296	for (i = 0; i < 4; i++) {
	297	regval = env->macc[i];
	298	exthigh = regval >> 40;
	299	if (env->macsr & MACSR_FI) {
	300	acc = regval >> 8;
	301	extlow = regval;
	302	} else {
	303	acc = regval;
	304	extlow = regval >> 32;
	305	}
	306	if (env->macsr & MACSR_FI) {
	307	regval = (((uint64_t)acc) << 8) \| extlow;
	308	regval \|= ((int64_t)exthigh) << 40;
	309	} else if (env->macsr & MACSR_SU) {
	310	regval = acc \| (((int64_t)extlow) << 32);
	311	regval \|= ((int64_t)exthigh) << 40;
	312	} else {
	313	regval = acc \| (((uint64_t)extlow) << 32);
	314	regval \|= ((uint64_t)(uint8_t)exthigh) << 40;
	315	}
	316	env->macc[i] = regval;
	317	}
	318	}
	319	env->macsr = val;
	320	}
	321
20dcee94 PB	322	void m68k_switch_sp(CPUM68KState *env)
	323	{
	324	int new_sp;
	325
	326	env->sp[env->current_sp] = env->aregs[7];
	327	new_sp = (env->sr & SR_S && env->cacr & M68K_CACR_EUSP)
	328	? M68K_SSP : M68K_USP;
	329	env->aregs[7] = env->sp[new_sp];
	330	env->current_sp = new_sp;
	331	}
	332
0633879f PB	333	/* MMU */
	334
	335	/* TODO: This will need fixing once the MMU is implemented. */
	336	target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
	337	{
	338	return addr;
	339	}
	340
5fafdf24	341	#if defined(CONFIG_USER_ONLY)
0633879f PB	342
0633879f PB	343	int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390	344	int mmu_idx, int is_softmmu)
0633879f PB	345	{
	346	env->exception_index = EXCP_ACCESS;
	347	env->mmu.ar = address;
	348	return 1;
	349	}
	350
	351	#else
	352
	353	int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390	354	int mmu_idx, int is_softmmu)
0633879f PB	355	{
	356	int prot;
	357
	358	address &= TARGET_PAGE_MASK;
	359	prot = PAGE_READ \| PAGE_WRITE;
6ebbf390	360	return tlb_set_page(env, address, address, prot, mmu_idx, is_softmmu);
0633879f PB	361	}
	362
	363	/* Notify CPU of a pending interrupt. Prioritization and vectoring should
	364	be handled by the interrupt controller. Real hardware only requests
	365	the vector when the interrupt is acknowledged by the CPU. For
	366	simplicitly we calculate it when the interrupt is signalled. */
	367	void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector)
	368	{
	369	env->pending_level = level;
	370	env->pending_vector = vector;
	371	if (level)
	372	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	373	else
	374	cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
	375	}
	376
	377	#endif