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0633879f PB |
1 | /* |
2 | * M68K helper routines | |
5fafdf24 | 3 | * |
0633879f PB |
4 | * Copyright (c) 2007 CodeSourcery |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
0633879f | 18 | */ |
d8416665 | 19 | #include "qemu/osdep.h" |
3e457172 | 20 | #include "cpu.h" |
2ef6175a | 21 | #include "exec/helper-proto.h" |
f08b6170 | 22 | #include "exec/cpu_ldst.h" |
cfe67cef | 23 | #include "exec/semihost.h" |
0633879f PB |
24 | |
25 | #if defined(CONFIG_USER_ONLY) | |
26 | ||
97a8ea5a | 27 | void m68k_cpu_do_interrupt(CPUState *cs) |
3c688828 | 28 | { |
27103424 | 29 | cs->exception_index = -1; |
3c688828 BS |
30 | } |
31 | ||
ab409bb3 | 32 | static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) |
0633879f | 33 | { |
0633879f PB |
34 | } |
35 | ||
36 | #else | |
37 | ||
0633879f PB |
38 | /* Try to fill the TLB and return an exception if error. If retaddr is |
39 | NULL, it means that the function was called in C code (i.e. not | |
40 | from generated code or from helper.c) */ | |
d5a11fef | 41 | void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, |
20503968 | 42 | uintptr_t retaddr) |
0633879f | 43 | { |
0633879f PB |
44 | int ret; |
45 | ||
d5a11fef | 46 | ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); |
551bd27f | 47 | if (unlikely(ret)) { |
0633879f PB |
48 | if (retaddr) { |
49 | /* now we have a real cpu fault */ | |
3f38f309 | 50 | cpu_restore_state(cs, retaddr); |
0633879f | 51 | } |
5638d180 | 52 | cpu_loop_exit(cs); |
0633879f | 53 | } |
0633879f PB |
54 | } |
55 | ||
31871141 | 56 | static void do_rte(CPUM68KState *env) |
0633879f PB |
57 | { |
58 | uint32_t sp; | |
59 | uint32_t fmt; | |
60 | ||
61 | sp = env->aregs[7]; | |
31871141 BS |
62 | fmt = cpu_ldl_kernel(env, sp); |
63 | env->pc = cpu_ldl_kernel(env, sp + 4); | |
0633879f PB |
64 | sp |= (fmt >> 28) & 3; |
65 | env->sr = fmt & 0xffff; | |
66 | env->aregs[7] = sp + 8; | |
0c8ff723 | 67 | m68k_switch_sp(env); |
0633879f PB |
68 | } |
69 | ||
31871141 | 70 | static void do_interrupt_all(CPUM68KState *env, int is_hw) |
0633879f | 71 | { |
27103424 | 72 | CPUState *cs = CPU(m68k_env_get_cpu(env)); |
0633879f PB |
73 | uint32_t sp; |
74 | uint32_t fmt; | |
75 | uint32_t retaddr; | |
76 | uint32_t vector; | |
77 | ||
78 | fmt = 0; | |
79 | retaddr = env->pc; | |
80 | ||
81 | if (!is_hw) { | |
27103424 | 82 | switch (cs->exception_index) { |
0633879f PB |
83 | case EXCP_RTE: |
84 | /* Return from an exception. */ | |
31871141 | 85 | do_rte(env); |
0633879f | 86 | return; |
a87295e8 | 87 | case EXCP_HALT_INSN: |
cfe67cef | 88 | if (semihosting_enabled() |
a87295e8 PB |
89 | && (env->sr & SR_S) != 0 |
90 | && (env->pc & 3) == 0 | |
31871141 BS |
91 | && cpu_lduw_code(env, env->pc - 4) == 0x4e71 |
92 | && cpu_ldl_code(env, env->pc) == 0x4e7bf000) { | |
a87295e8 PB |
93 | env->pc += 4; |
94 | do_m68k_semihosting(env, env->dregs[0]); | |
95 | return; | |
96 | } | |
259186a7 | 97 | cs->halted = 1; |
27103424 | 98 | cs->exception_index = EXCP_HLT; |
5638d180 | 99 | cpu_loop_exit(cs); |
a87295e8 | 100 | return; |
0633879f | 101 | } |
27103424 AF |
102 | if (cs->exception_index >= EXCP_TRAP0 |
103 | && cs->exception_index <= EXCP_TRAP15) { | |
0633879f PB |
104 | /* Move the PC after the trap instruction. */ |
105 | retaddr += 2; | |
106 | } | |
107 | } | |
108 | ||
27103424 | 109 | vector = cs->exception_index << 2; |
0633879f PB |
110 | |
111 | fmt |= 0x40000000; | |
0633879f PB |
112 | fmt |= vector << 16; |
113 | fmt |= env->sr; | |
114 | ||
20dcee94 PB |
115 | env->sr |= SR_S; |
116 | if (is_hw) { | |
117 | env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT); | |
118 | env->sr &= ~SR_M; | |
119 | } | |
120 | m68k_switch_sp(env); | |
0c8ff723 GU |
121 | sp = env->aregs[7]; |
122 | fmt |= (sp & 3) << 28; | |
20dcee94 | 123 | |
0633879f PB |
124 | /* ??? This could cause MMU faults. */ |
125 | sp &= ~3; | |
126 | sp -= 4; | |
31871141 | 127 | cpu_stl_kernel(env, sp, retaddr); |
0633879f | 128 | sp -= 4; |
31871141 | 129 | cpu_stl_kernel(env, sp, fmt); |
0633879f | 130 | env->aregs[7] = sp; |
0633879f | 131 | /* Jump to vector. */ |
31871141 | 132 | env->pc = cpu_ldl_kernel(env, env->vbr + vector); |
0633879f PB |
133 | } |
134 | ||
97a8ea5a | 135 | void m68k_cpu_do_interrupt(CPUState *cs) |
3c688828 | 136 | { |
97a8ea5a AF |
137 | M68kCPU *cpu = M68K_CPU(cs); |
138 | CPUM68KState *env = &cpu->env; | |
139 | ||
31871141 | 140 | do_interrupt_all(env, 0); |
3c688828 BS |
141 | } |
142 | ||
ab409bb3 | 143 | static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) |
3c688828 | 144 | { |
31871141 | 145 | do_interrupt_all(env, 1); |
3c688828 | 146 | } |
0633879f | 147 | #endif |
e1f3808e | 148 | |
ab409bb3 RH |
149 | bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
150 | { | |
151 | M68kCPU *cpu = M68K_CPU(cs); | |
152 | CPUM68KState *env = &cpu->env; | |
153 | ||
154 | if (interrupt_request & CPU_INTERRUPT_HARD | |
155 | && ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) { | |
156 | /* Real hardware gets the interrupt vector via an IACK cycle | |
157 | at this point. Current emulated hardware doesn't rely on | |
158 | this, so we provide/save the vector when the interrupt is | |
159 | first signalled. */ | |
160 | cs->exception_index = env->pending_vector; | |
161 | do_interrupt_m68k_hardirq(env); | |
162 | return true; | |
163 | } | |
164 | return false; | |
165 | } | |
166 | ||
31871141 | 167 | static void raise_exception(CPUM68KState *env, int tt) |
e1f3808e | 168 | { |
27103424 AF |
169 | CPUState *cs = CPU(m68k_env_get_cpu(env)); |
170 | ||
171 | cs->exception_index = tt; | |
5638d180 | 172 | cpu_loop_exit(cs); |
e1f3808e PB |
173 | } |
174 | ||
31871141 | 175 | void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt) |
e1f3808e | 176 | { |
31871141 | 177 | raise_exception(env, tt); |
e1f3808e PB |
178 | } |
179 | ||
2b3e3cfe | 180 | void HELPER(divu)(CPUM68KState *env, uint32_t word) |
e1f3808e PB |
181 | { |
182 | uint32_t num; | |
183 | uint32_t den; | |
184 | uint32_t quot; | |
185 | uint32_t rem; | |
186 | uint32_t flags; | |
187 | ||
188 | num = env->div1; | |
189 | den = env->div2; | |
190 | /* ??? This needs to make sure the throwing location is accurate. */ | |
31871141 BS |
191 | if (den == 0) { |
192 | raise_exception(env, EXCP_DIV0); | |
193 | } | |
e1f3808e PB |
194 | quot = num / den; |
195 | rem = num % den; | |
196 | flags = 0; | |
e1f3808e PB |
197 | if (word && quot > 0xffff) |
198 | flags |= CCF_V; | |
199 | if (quot == 0) | |
200 | flags |= CCF_Z; | |
201 | else if ((int32_t)quot < 0) | |
202 | flags |= CCF_N; | |
203 | env->div1 = quot; | |
204 | env->div2 = rem; | |
205 | env->cc_dest = flags; | |
206 | } | |
207 | ||
2b3e3cfe | 208 | void HELPER(divs)(CPUM68KState *env, uint32_t word) |
e1f3808e PB |
209 | { |
210 | int32_t num; | |
211 | int32_t den; | |
212 | int32_t quot; | |
213 | int32_t rem; | |
214 | int32_t flags; | |
215 | ||
216 | num = env->div1; | |
217 | den = env->div2; | |
31871141 BS |
218 | if (den == 0) { |
219 | raise_exception(env, EXCP_DIV0); | |
220 | } | |
e1f3808e PB |
221 | quot = num / den; |
222 | rem = num % den; | |
223 | flags = 0; | |
224 | if (word && quot != (int16_t)quot) | |
225 | flags |= CCF_V; | |
226 | if (quot == 0) | |
227 | flags |= CCF_Z; | |
228 | else if (quot < 0) | |
229 | flags |= CCF_N; | |
230 | env->div1 = quot; | |
231 | env->div2 = rem; | |
232 | env->cc_dest = flags; | |
233 | } |