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b77f98ca AF |
1 | /* |
2 | * QEMU MicroBlaze CPU | |
3 | * | |
61b6208f AF |
4 | * Copyright (c) 2009 Edgar E. Iglesias |
5 | * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. | |
b77f98ca AF |
6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
7 | * | |
8 | * This library is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU Lesser General Public | |
10 | * License as published by the Free Software Foundation; either | |
11 | * version 2.1 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This library is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * Lesser General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU Lesser General Public | |
19 | * License along with this library; if not, see | |
20 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
21 | */ | |
22 | ||
23 | #include "cpu.h" | |
24 | #include "qemu-common.h" | |
25 | ||
26 | ||
27 | /* CPUClass::reset() */ | |
28 | static void mb_cpu_reset(CPUState *s) | |
29 | { | |
30 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); | |
31 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); | |
32 | CPUMBState *env = &cpu->env; | |
33 | ||
61b6208f AF |
34 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { |
35 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
36 | log_cpu_state(env, 0); | |
37 | } | |
38 | ||
b77f98ca AF |
39 | mcc->parent_reset(s); |
40 | ||
61b6208f | 41 | memset(env, 0, offsetof(CPUMBState, breakpoints)); |
8cc9b43f | 42 | env->res_addr = RES_ADDR_NONE; |
61b6208f AF |
43 | tlb_flush(env, 1); |
44 | ||
45 | /* Disable stack protector. */ | |
46 | env->shr = ~0; | |
47 | ||
48 | env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ | |
49 | | PVR0_USE_BARREL_MASK \ | |
50 | | PVR0_USE_DIV_MASK \ | |
51 | | PVR0_USE_HW_MUL_MASK \ | |
52 | | PVR0_USE_EXC_MASK \ | |
53 | | PVR0_USE_ICACHE_MASK \ | |
54 | | PVR0_USE_DCACHE_MASK \ | |
55 | | PVR0_USE_MMU \ | |
56 | | (0xb << 8); | |
57 | env->pvr.regs[2] = PVR2_D_OPB_MASK \ | |
58 | | PVR2_D_LMB_MASK \ | |
59 | | PVR2_I_OPB_MASK \ | |
60 | | PVR2_I_LMB_MASK \ | |
61 | | PVR2_USE_MSR_INSTR \ | |
62 | | PVR2_USE_PCMP_INSTR \ | |
63 | | PVR2_USE_BARREL_MASK \ | |
64 | | PVR2_USE_DIV_MASK \ | |
65 | | PVR2_USE_HW_MUL_MASK \ | |
66 | | PVR2_USE_MUL64_MASK \ | |
67 | | PVR2_USE_FPU_MASK \ | |
68 | | PVR2_USE_FPU2_MASK \ | |
69 | | PVR2_FPU_EXC_MASK \ | |
70 | | 0; | |
71 | env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ | |
72 | env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); | |
73 | ||
74 | #if defined(CONFIG_USER_ONLY) | |
75 | /* start in user mode with interrupts enabled. */ | |
76 | env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; | |
77 | env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ | |
78 | #else | |
79 | env->sregs[SR_MSR] = 0; | |
80 | mmu_init(&env->mmu); | |
81 | env->mmu.c_mmu = 3; | |
82 | env->mmu.c_mmu_tlb_access = 3; | |
83 | env->mmu.c_mmu_zones = 16; | |
84 | #endif | |
b77f98ca AF |
85 | } |
86 | ||
d0e71ef5 AF |
87 | static void mb_cpu_initfn(Object *obj) |
88 | { | |
89 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); | |
90 | CPUMBState *env = &cpu->env; | |
91 | ||
92 | cpu_exec_init(env); | |
93 | ||
94 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); | |
95 | } | |
96 | ||
b77f98ca AF |
97 | static void mb_cpu_class_init(ObjectClass *oc, void *data) |
98 | { | |
99 | CPUClass *cc = CPU_CLASS(oc); | |
100 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); | |
101 | ||
102 | mcc->parent_reset = cc->reset; | |
103 | cc->reset = mb_cpu_reset; | |
104 | } | |
105 | ||
106 | static const TypeInfo mb_cpu_type_info = { | |
107 | .name = TYPE_MICROBLAZE_CPU, | |
108 | .parent = TYPE_CPU, | |
109 | .instance_size = sizeof(MicroBlazeCPU), | |
d0e71ef5 | 110 | .instance_init = mb_cpu_initfn, |
b77f98ca AF |
111 | .class_size = sizeof(MicroBlazeCPUClass), |
112 | .class_init = mb_cpu_class_init, | |
113 | }; | |
114 | ||
115 | static void mb_cpu_register_types(void) | |
116 | { | |
117 | type_register_static(&mb_cpu_type_info); | |
118 | } | |
119 | ||
120 | type_init(mb_cpu_register_types) |