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b77f98ca AF |
1 | /* |
2 | * QEMU MicroBlaze CPU | |
3 | * | |
61b6208f AF |
4 | * Copyright (c) 2009 Edgar E. Iglesias |
5 | * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. | |
b77f98ca | 6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
73c69456 | 7 | * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. |
b77f98ca AF |
8 | * |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
22 | */ | |
23 | ||
24 | #include "cpu.h" | |
25 | #include "qemu-common.h" | |
a1bff71c | 26 | #include "hw/qdev-properties.h" |
3ce8b2bc | 27 | #include "migration/vmstate.h" |
b77f98ca AF |
28 | |
29 | ||
f45748f1 AF |
30 | static void mb_cpu_set_pc(CPUState *cs, vaddr value) |
31 | { | |
32 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); | |
33 | ||
34 | cpu->env.sregs[SR_PC] = value; | |
35 | } | |
36 | ||
8c2e1b00 AF |
37 | static bool mb_cpu_has_work(CPUState *cs) |
38 | { | |
39 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); | |
40 | } | |
41 | ||
73c69456 AF |
42 | #ifndef CONFIG_USER_ONLY |
43 | static void microblaze_cpu_set_irq(void *opaque, int irq, int level) | |
44 | { | |
45 | MicroBlazeCPU *cpu = opaque; | |
46 | CPUState *cs = CPU(cpu); | |
47 | int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; | |
48 | ||
49 | if (level) { | |
50 | cpu_interrupt(cs, type); | |
51 | } else { | |
52 | cpu_reset_interrupt(cs, type); | |
53 | } | |
54 | } | |
55 | #endif | |
56 | ||
b77f98ca AF |
57 | /* CPUClass::reset() */ |
58 | static void mb_cpu_reset(CPUState *s) | |
59 | { | |
60 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); | |
61 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); | |
62 | CPUMBState *env = &cpu->env; | |
63 | ||
64 | mcc->parent_reset(s); | |
65 | ||
8bac2242 | 66 | memset(env, 0, offsetof(CPUMBState, pvr)); |
8cc9b43f | 67 | env->res_addr = RES_ADDR_NONE; |
00c8cb0a | 68 | tlb_flush(s, 1); |
61b6208f AF |
69 | |
70 | /* Disable stack protector. */ | |
71 | env->shr = ~0; | |
72 | ||
8bac2242 AF |
73 | #if defined(CONFIG_USER_ONLY) |
74 | /* start in user mode with interrupts enabled. */ | |
75 | env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; | |
76 | #else | |
77 | env->sregs[SR_MSR] = 0; | |
78 | mmu_init(&env->mmu); | |
79 | env->mmu.c_mmu = 3; | |
80 | env->mmu.c_mmu_tlb_access = 3; | |
81 | env->mmu.c_mmu_zones = 16; | |
82 | #endif | |
83 | } | |
84 | ||
85 | static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | |
86 | { | |
87 | CPUState *cs = CPU(dev); | |
88 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); | |
89 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); | |
90 | CPUMBState *env = &cpu->env; | |
91 | ||
92 | qemu_init_vcpu(cs); | |
93 | ||
61b6208f AF |
94 | env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ |
95 | | PVR0_USE_BARREL_MASK \ | |
96 | | PVR0_USE_DIV_MASK \ | |
97 | | PVR0_USE_HW_MUL_MASK \ | |
98 | | PVR0_USE_EXC_MASK \ | |
99 | | PVR0_USE_ICACHE_MASK \ | |
100 | | PVR0_USE_DCACHE_MASK \ | |
61b6208f AF |
101 | | (0xb << 8); |
102 | env->pvr.regs[2] = PVR2_D_OPB_MASK \ | |
103 | | PVR2_D_LMB_MASK \ | |
104 | | PVR2_I_OPB_MASK \ | |
105 | | PVR2_I_LMB_MASK \ | |
106 | | PVR2_USE_MSR_INSTR \ | |
107 | | PVR2_USE_PCMP_INSTR \ | |
108 | | PVR2_USE_BARREL_MASK \ | |
109 | | PVR2_USE_DIV_MASK \ | |
110 | | PVR2_USE_HW_MUL_MASK \ | |
111 | | PVR2_USE_MUL64_MASK \ | |
61b6208f AF |
112 | | PVR2_FPU_EXC_MASK \ |
113 | | 0; | |
9aaaa181 | 114 | |
4e5d45ae | 115 | env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | |
71446123 | 116 | (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | |
a88bbb00 AF |
117 | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | |
118 | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0); | |
4e5d45ae | 119 | |
be67e9ab AF |
120 | env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | |
121 | (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0); | |
9aaaa181 | 122 | |
a6c3ed24 AF |
123 | env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? |
124 | PVR5_DCACHE_WRITEBACK_MASK : 0; | |
125 | ||
61b6208f AF |
126 | env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ |
127 | env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); | |
128 | ||
f27183ab | 129 | env->sregs[SR_PC] = cpu->cfg.base_vectors; |
6d35556c | 130 | |
61b6208f | 131 | #if defined(CONFIG_USER_ONLY) |
61b6208f | 132 | env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ |
61b6208f | 133 | #endif |
746b03b2 AF |
134 | |
135 | mcc->parent_realize(dev, errp); | |
136 | } | |
137 | ||
d0e71ef5 AF |
138 | static void mb_cpu_initfn(Object *obj) |
139 | { | |
c05efcb1 | 140 | CPUState *cs = CPU(obj); |
d0e71ef5 AF |
141 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); |
142 | CPUMBState *env = &cpu->env; | |
cd0c24f9 | 143 | static bool tcg_initialized; |
d0e71ef5 | 144 | |
c05efcb1 | 145 | cs->env_ptr = env; |
d0e71ef5 AF |
146 | cpu_exec_init(env); |
147 | ||
148 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); | |
cd0c24f9 | 149 | |
73c69456 AF |
150 | #ifndef CONFIG_USER_ONLY |
151 | /* Inbound IRQ and FIR lines */ | |
152 | qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); | |
153 | #endif | |
154 | ||
cd0c24f9 AF |
155 | if (tcg_enabled() && !tcg_initialized) { |
156 | tcg_initialized = true; | |
157 | mb_tcg_init(); | |
158 | } | |
d0e71ef5 AF |
159 | } |
160 | ||
3ce8b2bc AF |
161 | static const VMStateDescription vmstate_mb_cpu = { |
162 | .name = "cpu", | |
163 | .unmigratable = 1, | |
164 | }; | |
165 | ||
a1bff71c | 166 | static Property mb_properties[] = { |
f27183ab | 167 | DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), |
9aaaa181 | 168 | DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, |
f44c475c | 169 | false), |
4e5d45ae AF |
170 | /* If use-fpu > 0 - FPU is enabled |
171 | * If use-fpu = 2 - Floating point conversion and square root instructions | |
172 | * are enabled | |
173 | */ | |
be67e9ab | 174 | DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), |
71446123 | 175 | DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), |
a6c3ed24 AF |
176 | DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, |
177 | false), | |
a88bbb00 | 178 | DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), |
a1bff71c EI |
179 | DEFINE_PROP_END_OF_LIST(), |
180 | }; | |
181 | ||
b77f98ca AF |
182 | static void mb_cpu_class_init(ObjectClass *oc, void *data) |
183 | { | |
3ce8b2bc | 184 | DeviceClass *dc = DEVICE_CLASS(oc); |
b77f98ca AF |
185 | CPUClass *cc = CPU_CLASS(oc); |
186 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); | |
187 | ||
746b03b2 AF |
188 | mcc->parent_realize = dc->realize; |
189 | dc->realize = mb_cpu_realizefn; | |
190 | ||
b77f98ca AF |
191 | mcc->parent_reset = cc->reset; |
192 | cc->reset = mb_cpu_reset; | |
3ce8b2bc | 193 | |
8c2e1b00 | 194 | cc->has_work = mb_cpu_has_work; |
97a8ea5a | 195 | cc->do_interrupt = mb_cpu_do_interrupt; |
29cd33d3 | 196 | cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; |
878096ee | 197 | cc->dump_state = mb_cpu_dump_state; |
f45748f1 | 198 | cc->set_pc = mb_cpu_set_pc; |
5b50e790 AF |
199 | cc->gdb_read_register = mb_cpu_gdb_read_register; |
200 | cc->gdb_write_register = mb_cpu_gdb_write_register; | |
7510454e AF |
201 | #ifdef CONFIG_USER_ONLY |
202 | cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; | |
203 | #else | |
00b941e5 AF |
204 | cc->do_unassigned_access = mb_cpu_unassigned_access; |
205 | cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; | |
206 | #endif | |
3ce8b2bc | 207 | dc->vmsd = &vmstate_mb_cpu; |
a1bff71c | 208 | dc->props = mb_properties; |
a0e372f0 | 209 | cc->gdb_num_core_regs = 32 + 5; |
b77f98ca AF |
210 | } |
211 | ||
212 | static const TypeInfo mb_cpu_type_info = { | |
213 | .name = TYPE_MICROBLAZE_CPU, | |
214 | .parent = TYPE_CPU, | |
215 | .instance_size = sizeof(MicroBlazeCPU), | |
d0e71ef5 | 216 | .instance_init = mb_cpu_initfn, |
b77f98ca AF |
217 | .class_size = sizeof(MicroBlazeCPUClass), |
218 | .class_init = mb_cpu_class_init, | |
219 | }; | |
220 | ||
221 | static void mb_cpu_register_types(void) | |
222 | { | |
223 | type_register_static(&mb_cpu_type_info); | |
224 | } | |
225 | ||
226 | type_init(mb_cpu_register_types) |