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4acb54ba EI |
1 | /* |
2 | * MicroBlaze virtual CPU header | |
3 | * | |
4 | * Copyright (c) 2009 Edgar E. Iglesias | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
4acb54ba | 18 | */ |
07f5a258 MA |
19 | |
20 | #ifndef MICROBLAZE_CPU_H | |
21 | #define MICROBLAZE_CPU_H | |
4acb54ba | 22 | |
94598c1d | 23 | #include "qemu-common.h" |
ffa3a3c6 | 24 | #include "cpu-qom.h" |
94598c1d | 25 | |
4acb54ba EI |
26 | #define TARGET_LONG_BITS 32 |
27 | ||
9349b4f9 | 28 | #define CPUArchState struct CPUMBState |
4acb54ba | 29 | |
022c62cb | 30 | #include "exec/cpu-defs.h" |
6b4c305c | 31 | #include "fpu/softfloat.h" |
4acb54ba | 32 | struct CPUMBState; |
9b9a970a | 33 | typedef struct CPUMBState CPUMBState; |
4acb54ba EI |
34 | #if !defined(CONFIG_USER_ONLY) |
35 | #include "mmu.h" | |
36 | #endif | |
37 | ||
2161be35 MT |
38 | #define EXCP_MMU 1 |
39 | #define EXCP_IRQ 2 | |
40 | #define EXCP_BREAK 3 | |
41 | #define EXCP_HW_BREAK 4 | |
42 | #define EXCP_HW_EXCP 5 | |
4acb54ba | 43 | |
85097db6 RH |
44 | /* MicroBlaze-specific interrupt pending bits. */ |
45 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 | |
46 | ||
73c69456 AF |
47 | /* Meanings of the MBCPU object's two inbound GPIO lines */ |
48 | #define MB_CPU_IRQ 0 | |
49 | #define MB_CPU_FIR 1 | |
50 | ||
4acb54ba EI |
51 | /* Register aliases. R0 - R15 */ |
52 | #define R_SP 1 | |
53 | #define SR_PC 0 | |
54 | #define SR_MSR 1 | |
55 | #define SR_EAR 3 | |
56 | #define SR_ESR 5 | |
57 | #define SR_FSR 7 | |
58 | #define SR_BTR 0xb | |
59 | #define SR_EDR 0xd | |
60 | ||
61 | /* MSR flags. */ | |
62 | #define MSR_BE (1<<0) /* 0x001 */ | |
63 | #define MSR_IE (1<<1) /* 0x002 */ | |
64 | #define MSR_C (1<<2) /* 0x004 */ | |
65 | #define MSR_BIP (1<<3) /* 0x008 */ | |
66 | #define MSR_FSL (1<<4) /* 0x010 */ | |
67 | #define MSR_ICE (1<<5) /* 0x020 */ | |
68 | #define MSR_DZ (1<<6) /* 0x040 */ | |
69 | #define MSR_DCE (1<<7) /* 0x080 */ | |
70 | #define MSR_EE (1<<8) /* 0x100 */ | |
71 | #define MSR_EIP (1<<9) /* 0x200 */ | |
8a84fc6b | 72 | #define MSR_PVR (1<<10) /* 0x400 */ |
4acb54ba EI |
73 | #define MSR_CC (1<<31) |
74 | ||
75 | /* Machine State Register (MSR) Fields */ | |
76 | #define MSR_UM (1<<11) /* User Mode */ | |
77 | #define MSR_UMS (1<<12) /* User Mode Save */ | |
78 | #define MSR_VM (1<<13) /* Virtual Mode */ | |
79 | #define MSR_VMS (1<<14) /* Virtual Mode Save */ | |
80 | ||
81 | #define MSR_KERNEL MSR_EE|MSR_VM | |
82 | //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE | |
83 | #define MSR_KERNEL_VMS MSR_EE|MSR_VMS | |
84 | //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE | |
85 | ||
86 | /* Exception State Register (ESR) Fields */ | |
87 | #define ESR_DIZ (1<<11) /* Zone Protection */ | |
88 | #define ESR_S (1<<10) /* Store instruction */ | |
89 | ||
85453641 EI |
90 | #define ESR_ESS_FSL_OFFSET 5 |
91 | ||
cedb936b EI |
92 | #define ESR_EC_FSL 0 |
93 | #define ESR_EC_UNALIGNED_DATA 1 | |
94 | #define ESR_EC_ILLEGAL_OP 2 | |
95 | #define ESR_EC_INSN_BUS 3 | |
96 | #define ESR_EC_DATA_BUS 4 | |
97 | #define ESR_EC_DIVZERO 5 | |
98 | #define ESR_EC_FPU 6 | |
99 | #define ESR_EC_PRIVINSN 7 | |
5818dee5 | 100 | #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ |
cedb936b EI |
101 | #define ESR_EC_DATA_STORAGE 8 |
102 | #define ESR_EC_INSN_STORAGE 9 | |
103 | #define ESR_EC_DATA_TLB 10 | |
104 | #define ESR_EC_INSN_TLB 11 | |
3b584046 | 105 | #define ESR_EC_MASK 31 |
4acb54ba | 106 | |
bdc0bf29 EI |
107 | /* Floating Point Status Register (FSR) Bits */ |
108 | #define FSR_IO (1<<4) /* Invalid operation */ | |
109 | #define FSR_DZ (1<<3) /* Divide-by-zero */ | |
110 | #define FSR_OF (1<<2) /* Overflow */ | |
111 | #define FSR_UF (1<<1) /* Underflow */ | |
112 | #define FSR_DO (1<<0) /* Denormalized operand error */ | |
113 | ||
4acb54ba EI |
114 | /* Version reg. */ |
115 | /* Basic PVR mask */ | |
116 | #define PVR0_PVR_FULL_MASK 0x80000000 | |
117 | #define PVR0_USE_BARREL_MASK 0x40000000 | |
118 | #define PVR0_USE_DIV_MASK 0x20000000 | |
119 | #define PVR0_USE_HW_MUL_MASK 0x10000000 | |
120 | #define PVR0_USE_FPU_MASK 0x08000000 | |
121 | #define PVR0_USE_EXC_MASK 0x04000000 | |
122 | #define PVR0_USE_ICACHE_MASK 0x02000000 | |
123 | #define PVR0_USE_DCACHE_MASK 0x01000000 | |
71446123 | 124 | #define PVR0_USE_MMU_MASK 0x00800000 |
c4374bb7 | 125 | #define PVR0_USE_BTC 0x00400000 |
a88bbb00 | 126 | #define PVR0_ENDI_MASK 0x00200000 |
c4374bb7 | 127 | #define PVR0_FAULT 0x00100000 |
4acb54ba EI |
128 | #define PVR0_VERSION_MASK 0x0000FF00 |
129 | #define PVR0_USER1_MASK 0x000000FF | |
9aaaa181 | 130 | #define PVR0_SPROT_MASK 0x00000001 |
4acb54ba EI |
131 | |
132 | /* User 2 PVR mask */ | |
133 | #define PVR1_USER2_MASK 0xFFFFFFFF | |
134 | ||
135 | /* Configuration PVR masks */ | |
136 | #define PVR2_D_OPB_MASK 0x80000000 | |
137 | #define PVR2_D_LMB_MASK 0x40000000 | |
138 | #define PVR2_I_OPB_MASK 0x20000000 | |
139 | #define PVR2_I_LMB_MASK 0x10000000 | |
140 | #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 | |
141 | #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 | |
142 | #define PVR2_D_PLB_MASK 0x02000000 /* new */ | |
143 | #define PVR2_I_PLB_MASK 0x01000000 /* new */ | |
144 | #define PVR2_INTERCONNECT 0x00800000 /* new */ | |
145 | #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ | |
146 | #define PVR2_USE_FSL_EXC 0x00040000 /* new */ | |
147 | #define PVR2_USE_MSR_INSTR 0x00020000 | |
148 | #define PVR2_USE_PCMP_INSTR 0x00010000 | |
149 | #define PVR2_AREA_OPTIMISED 0x00008000 | |
150 | #define PVR2_USE_BARREL_MASK 0x00004000 | |
151 | #define PVR2_USE_DIV_MASK 0x00002000 | |
152 | #define PVR2_USE_HW_MUL_MASK 0x00001000 | |
153 | #define PVR2_USE_FPU_MASK 0x00000800 | |
154 | #define PVR2_USE_MUL64_MASK 0x00000400 | |
155 | #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ | |
156 | #define PVR2_USE_IPLBEXC 0x00000100 | |
157 | #define PVR2_USE_DPLBEXC 0x00000080 | |
158 | #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 | |
159 | #define PVR2_UNALIGNED_EXC_MASK 0x00000020 | |
160 | #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 | |
161 | #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 | |
162 | #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 | |
163 | #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 | |
164 | #define PVR2_FPU_EXC_MASK 0x00000001 | |
165 | ||
166 | /* Debug and exception PVR masks */ | |
167 | #define PVR3_DEBUG_ENABLED_MASK 0x80000000 | |
168 | #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 | |
169 | #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 | |
170 | #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 | |
171 | #define PVR3_FSL_LINKS_MASK 0x00000380 | |
172 | ||
173 | /* ICache config PVR masks */ | |
174 | #define PVR4_USE_ICACHE_MASK 0x80000000 | |
175 | #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 | |
176 | #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 | |
177 | #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 | |
178 | #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 | |
179 | #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 | |
180 | ||
181 | /* DCache config PVR masks */ | |
182 | #define PVR5_USE_DCACHE_MASK 0x80000000 | |
183 | #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 | |
184 | #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 | |
185 | #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 | |
186 | #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 | |
187 | #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 | |
c4374bb7 | 188 | #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000 |
4acb54ba EI |
189 | |
190 | /* ICache base address PVR mask */ | |
191 | #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF | |
192 | ||
193 | /* ICache high address PVR mask */ | |
194 | #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF | |
195 | ||
196 | /* DCache base address PVR mask */ | |
197 | #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF | |
198 | ||
199 | /* DCache high address PVR mask */ | |
200 | #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF | |
201 | ||
202 | /* Target family PVR mask */ | |
203 | #define PVR10_TARGET_FAMILY_MASK 0xFF000000 | |
204 | ||
205 | /* MMU descrtiption */ | |
206 | #define PVR11_USE_MMU 0xC0000000 | |
207 | #define PVR11_MMU_ITLB_SIZE 0x38000000 | |
208 | #define PVR11_MMU_DTLB_SIZE 0x07000000 | |
209 | #define PVR11_MMU_TLB_ACCESS 0x00C00000 | |
7458a432 | 210 | #define PVR11_MMU_ZONES 0x003E0000 |
4acb54ba EI |
211 | /* MSR Reset value PVR mask */ |
212 | #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF | |
213 | ||
6fad9e98 AF |
214 | #define C_PVR_NONE 0 |
215 | #define C_PVR_BASIC 1 | |
216 | #define C_PVR_FULL 2 | |
4acb54ba EI |
217 | |
218 | /* CPU flags. */ | |
219 | ||
220 | /* Condition codes. */ | |
221 | #define CC_GE 5 | |
222 | #define CC_GT 4 | |
223 | #define CC_LE 3 | |
224 | #define CC_LT 2 | |
225 | #define CC_NE 1 | |
226 | #define CC_EQ 0 | |
227 | ||
228 | #define NB_MMU_MODES 3 | |
85453641 EI |
229 | |
230 | #define STREAM_EXCEPTION (1 << 0) | |
231 | #define STREAM_ATOMIC (1 << 1) | |
232 | #define STREAM_TEST (1 << 2) | |
233 | #define STREAM_CONTROL (1 << 3) | |
234 | #define STREAM_NONBLOCK (1 << 4) | |
235 | ||
ae7d54d4 | 236 | struct CPUMBState { |
4acb54ba EI |
237 | uint32_t debug; |
238 | uint32_t btaken; | |
239 | uint32_t btarget; | |
240 | uint32_t bimm; | |
241 | ||
242 | uint32_t imm; | |
243 | uint32_t regs[33]; | |
244 | uint32_t sregs[24]; | |
97694c57 | 245 | float_status fp_status; |
5818dee5 EI |
246 | /* Stack protectors. Yes, it's a hw feature. */ |
247 | uint32_t slr, shr; | |
4acb54ba | 248 | |
8cc9b43f PC |
249 | /* lwx/swx reserved address */ |
250 | #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ | |
251 | uint32_t res_addr; | |
11a76217 | 252 | uint32_t res_val; |
8cc9b43f | 253 | |
4acb54ba | 254 | /* Internal flags. */ |
cedb936b EI |
255 | #define IMM_FLAG 4 |
256 | #define MSR_EE_FLAG (1 << 8) | |
4acb54ba EI |
257 | #define DRTI_FLAG (1 << 16) |
258 | #define DRTE_FLAG (1 << 17) | |
259 | #define DRTB_FLAG (1 << 18) | |
260 | #define D_FLAG (1 << 19) /* Bit in ESR. */ | |
68cee38a | 261 | /* TB dependent CPUMBState. */ |
fd1dc858 | 262 | #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) |
4acb54ba EI |
263 | uint32_t iflags; |
264 | ||
4acb54ba EI |
265 | #if !defined(CONFIG_USER_ONLY) |
266 | /* Unified MMU. */ | |
267 | struct microblaze_mmu mmu; | |
268 | #endif | |
269 | ||
270 | CPU_COMMON | |
8bac2242 AF |
271 | |
272 | /* These fields are preserved on reset. */ | |
273 | ||
274 | struct { | |
275 | uint32_t regs[16]; | |
276 | } pvr; | |
ae7d54d4 | 277 | }; |
4acb54ba | 278 | |
ffa3a3c6 PB |
279 | /** |
280 | * MicroBlazeCPU: | |
281 | * @env: #CPUMBState | |
282 | * | |
283 | * A MicroBlaze CPU. | |
284 | */ | |
285 | struct MicroBlazeCPU { | |
286 | /*< private >*/ | |
287 | CPUState parent_obj; | |
288 | ||
289 | /*< public >*/ | |
290 | ||
291 | /* Microblaze Configuration Settings */ | |
292 | struct { | |
293 | bool stackprot; | |
294 | uint32_t base_vectors; | |
295 | uint8_t use_fpu; | |
296 | bool use_mmu; | |
297 | bool dcache_writeback; | |
298 | bool endi; | |
299 | char *version; | |
300 | uint8_t pvr; | |
301 | } cfg; | |
302 | ||
303 | CPUMBState env; | |
304 | }; | |
305 | ||
306 | static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) | |
307 | { | |
308 | return container_of(env, MicroBlazeCPU, env); | |
309 | } | |
310 | ||
311 | #define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e)) | |
312 | ||
313 | #define ENV_OFFSET offsetof(MicroBlazeCPU, env) | |
314 | ||
315 | void mb_cpu_do_interrupt(CPUState *cs); | |
316 | bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); | |
317 | void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
318 | int flags); | |
319 | hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
320 | int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
321 | int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
b77f98ca | 322 | |
cd0c24f9 | 323 | void mb_tcg_init(void); |
b33ab1f7 | 324 | MicroBlazeCPU *cpu_mb_init(const char *cpu_model); |
4acb54ba EI |
325 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
326 | signal handlers to inform the virtual CPU of exceptions. non zero | |
327 | is returned if the signal was handled by the virtual CPU. */ | |
328 | int cpu_mb_signal_handler(int host_signum, void *pinfo, | |
329 | void *puc); | |
330 | ||
4acb54ba EI |
331 | /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ |
332 | #define TARGET_PAGE_BITS 12 | |
4acb54ba | 333 | |
52705890 RH |
334 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
335 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
336 | ||
2994fd96 | 337 | #define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model)) |
b33ab1f7 | 338 | |
4acb54ba EI |
339 | #define cpu_signal_handler cpu_mb_signal_handler |
340 | ||
4acb54ba EI |
341 | /* MMU modes definitions */ |
342 | #define MMU_MODE0_SUFFIX _nommu | |
343 | #define MMU_MODE1_SUFFIX _kernel | |
344 | #define MMU_MODE2_SUFFIX _user | |
345 | #define MMU_NOMMU_IDX 0 | |
346 | #define MMU_KERNEL_IDX 1 | |
347 | #define MMU_USER_IDX 2 | |
348 | /* See NB_MMU_MODES further up the file. */ | |
349 | ||
97ed5ccd | 350 | static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) |
4acb54ba EI |
351 | { |
352 | /* Are we in nommu mode?. */ | |
353 | if (!(env->sregs[SR_MSR] & MSR_VM)) | |
354 | return MMU_NOMMU_IDX; | |
355 | ||
356 | if (env->sregs[SR_MSR] & MSR_UM) | |
357 | return MMU_USER_IDX; | |
358 | return MMU_KERNEL_IDX; | |
359 | } | |
360 | ||
7510454e | 361 | int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, |
97b348e7 | 362 | int mmu_idx); |
4acb54ba | 363 | |
022c62cb | 364 | #include "exec/cpu-all.h" |
4acb54ba | 365 | |
68cee38a | 366 | static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, |
89fee74a | 367 | target_ulong *cs_base, uint32_t *flags) |
4acb54ba EI |
368 | { |
369 | *pc = env->sregs[SR_PC]; | |
370 | *cs_base = 0; | |
fd1dc858 EI |
371 | *flags = (env->iflags & IFLAGS_TB_MASK) | |
372 | (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); | |
4acb54ba | 373 | } |
faed1c2a | 374 | |
3c7b48b7 | 375 | #if !defined(CONFIG_USER_ONLY) |
c658b94f AF |
376 | void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
377 | bool is_write, bool is_exec, int is_asi, | |
378 | unsigned size); | |
4acb54ba | 379 | #endif |
f081c76c | 380 | |
3c7b48b7 | 381 | #endif |