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afeeceb0 EI |
1 | /* |
2 | * Microblaze MMU emulation for qemu. | |
3 | * | |
4 | * Copyright (c) 2009 Edgar E. Iglesias | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
afeeceb0 EI |
18 | */ |
19 | #include <stdio.h> | |
20 | #include <stdlib.h> | |
21 | #include <assert.h> | |
22 | ||
23 | #include "config.h" | |
24 | #include "cpu.h" | |
afeeceb0 EI |
25 | |
26 | #define D(x) | |
27 | ||
28 | static unsigned int tlb_decode_size(unsigned int f) | |
29 | { | |
30 | static const unsigned int sizes[] = { | |
31 | 1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024, | |
32 | 1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024 | |
33 | }; | |
34 | assert(f < ARRAY_SIZE(sizes)); | |
35 | return sizes[f]; | |
36 | } | |
37 | ||
6b2fce90 | 38 | static void mmu_flush_idx(CPUState *env, unsigned int idx) |
afeeceb0 EI |
39 | { |
40 | struct microblaze_mmu *mmu = &env->mmu; | |
41 | unsigned int tlb_size; | |
42 | uint32_t tlb_tag, end, t; | |
43 | ||
44 | t = mmu->rams[RAM_TAG][idx]; | |
45 | if (!(t & TLB_VALID)) | |
46 | return; | |
47 | ||
48 | tlb_tag = t & TLB_EPN_MASK; | |
49 | tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7); | |
50 | end = tlb_tag + tlb_size; | |
51 | ||
52 | while (tlb_tag < end) { | |
53 | tlb_flush_page(env, tlb_tag); | |
54 | tlb_tag += TARGET_PAGE_SIZE; | |
55 | } | |
56 | } | |
57 | ||
58 | static void mmu_change_pid(CPUState *env, unsigned int newpid) | |
59 | { | |
60 | struct microblaze_mmu *mmu = &env->mmu; | |
61 | unsigned int i; | |
183aa454 | 62 | uint32_t t; |
afeeceb0 EI |
63 | |
64 | if (newpid & ~0xff) | |
65 | qemu_log("Illegal rpid=%x\n", newpid); | |
66 | ||
67 | for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { | |
68 | /* Lookup and decode. */ | |
69 | t = mmu->rams[RAM_TAG][i]; | |
70 | if (t & TLB_VALID) { | |
afeeceb0 EI |
71 | if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i])) |
72 | mmu_flush_idx(env, i); | |
73 | } | |
74 | } | |
75 | } | |
76 | ||
77 | /* rw - 0 = read, 1 = write, 2 = fetch. */ | |
78 | unsigned int mmu_translate(struct microblaze_mmu *mmu, | |
79 | struct microblaze_mmu_lookup *lu, | |
80 | target_ulong vaddr, int rw, int mmu_idx) | |
81 | { | |
82 | unsigned int i, hit = 0; | |
83 | unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel; | |
84 | unsigned int tlb_size; | |
85 | uint32_t tlb_tag, tlb_rpn, mask, t0; | |
86 | ||
87 | lu->err = ERR_MISS; | |
88 | for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { | |
89 | uint32_t t, d; | |
90 | ||
91 | /* Lookup and decode. */ | |
92 | t = mmu->rams[RAM_TAG][i]; | |
93 | D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID)); | |
94 | if (t & TLB_VALID) { | |
95 | tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7); | |
96 | if (tlb_size < TARGET_PAGE_SIZE) { | |
97 | qemu_log("%d pages not supported\n", tlb_size); | |
98 | abort(); | |
99 | } | |
100 | ||
101 | mask = ~(tlb_size - 1); | |
102 | tlb_tag = t & TLB_EPN_MASK; | |
103 | if ((vaddr & mask) != (tlb_tag & mask)) { | |
104 | D(qemu_log("TLB %d vaddr=%x != tag=%x\n", | |
105 | i, vaddr & mask, tlb_tag & mask)); | |
106 | continue; | |
107 | } | |
108 | if (mmu->tids[i] | |
109 | && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) { | |
110 | D(qemu_log("TLB %d pid=%x != tid=%x\n", | |
111 | i, mmu->regs[MMU_R_PID], mmu->tids[i])); | |
112 | continue; | |
113 | } | |
114 | ||
115 | /* Bring in the data part. */ | |
116 | d = mmu->rams[RAM_DATA][i]; | |
117 | tlb_ex = d & TLB_EX; | |
118 | tlb_wr = d & TLB_WR; | |
119 | ||
120 | /* Now lets see if there is a zone that overrides the protbits. */ | |
121 | tlb_zsel = (d >> 4) & 0xf; | |
122 | t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2)); | |
123 | t0 &= 0x3; | |
3c50a71f EI |
124 | |
125 | if (tlb_zsel > mmu->c_mmu_zones) { | |
126 | qemu_log("tlb zone select out of range! %d\n", tlb_zsel); | |
127 | t0 = 1; /* Ignore. */ | |
128 | } | |
129 | ||
130 | if (mmu->c_mmu == 1) { | |
131 | t0 = 1; /* Zones are disabled. */ | |
132 | } | |
133 | ||
afeeceb0 EI |
134 | switch (t0) { |
135 | case 0: | |
136 | if (mmu_idx == MMU_USER_IDX) | |
137 | continue; | |
138 | break; | |
139 | case 2: | |
140 | if (mmu_idx != MMU_USER_IDX) { | |
141 | tlb_ex = 1; | |
142 | tlb_wr = 1; | |
143 | } | |
144 | break; | |
145 | case 3: | |
146 | tlb_ex = 1; | |
147 | tlb_wr = 1; | |
148 | break; | |
3c50a71f | 149 | default: break; |
afeeceb0 EI |
150 | } |
151 | ||
afeeceb0 EI |
152 | lu->err = ERR_PROT; |
153 | lu->prot = PAGE_READ; | |
154 | if (tlb_wr) | |
155 | lu->prot |= PAGE_WRITE; | |
156 | else if (rw == 1) | |
157 | goto done; | |
158 | if (tlb_ex) | |
159 | lu->prot |=PAGE_EXEC; | |
160 | else if (rw == 2) { | |
161 | goto done; | |
162 | } | |
163 | ||
164 | tlb_rpn = d & TLB_RPN_MASK; | |
165 | ||
166 | lu->vaddr = tlb_tag; | |
167 | lu->paddr = tlb_rpn; | |
168 | lu->size = tlb_size; | |
169 | lu->err = ERR_HIT; | |
170 | lu->idx = i; | |
171 | hit = 1; | |
172 | goto done; | |
173 | } | |
174 | } | |
175 | done: | |
176 | D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n", | |
177 | vaddr, rw, tlb_wr, tlb_ex, hit)); | |
178 | return hit; | |
179 | } | |
180 | ||
181 | /* Writes/reads to the MMU's special regs end up here. */ | |
182 | uint32_t mmu_read(CPUState *env, uint32_t rn) | |
183 | { | |
184 | unsigned int i; | |
185 | uint32_t r; | |
186 | ||
3c50a71f EI |
187 | if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { |
188 | qemu_log("MMU access on MMU-less system\n"); | |
189 | return 0; | |
190 | } | |
191 | ||
afeeceb0 EI |
192 | switch (rn) { |
193 | /* Reads to HI/LO trig reads from the mmu rams. */ | |
194 | case MMU_R_TLBLO: | |
195 | case MMU_R_TLBHI: | |
3c50a71f EI |
196 | if (!(env->mmu.c_mmu_tlb_access & 1)) { |
197 | qemu_log("Invalid access to MMU reg %d\n", rn); | |
198 | return 0; | |
199 | } | |
200 | ||
afeeceb0 EI |
201 | i = env->mmu.regs[MMU_R_TLBX] & 0xff; |
202 | r = env->mmu.rams[rn & 1][i]; | |
203 | if (rn == MMU_R_TLBHI) | |
204 | env->mmu.regs[MMU_R_PID] = env->mmu.tids[i]; | |
205 | break; | |
3c50a71f EI |
206 | case MMU_R_PID: |
207 | case MMU_R_ZPR: | |
208 | if (!(env->mmu.c_mmu_tlb_access & 1)) { | |
209 | qemu_log("Invalid access to MMU reg %d\n", rn); | |
210 | return 0; | |
211 | } | |
212 | r = env->mmu.regs[rn]; | |
213 | break; | |
afeeceb0 EI |
214 | default: |
215 | r = env->mmu.regs[rn]; | |
216 | break; | |
217 | } | |
218 | D(qemu_log("%s rn=%d=%x\n", __func__, rn, r)); | |
219 | return r; | |
220 | } | |
221 | ||
222 | void mmu_write(CPUState *env, uint32_t rn, uint32_t v) | |
223 | { | |
224 | unsigned int i; | |
225 | D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn])); | |
226 | ||
3c50a71f EI |
227 | if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { |
228 | qemu_log("MMU access on MMU-less system\n"); | |
229 | return; | |
230 | } | |
231 | ||
afeeceb0 EI |
232 | switch (rn) { |
233 | /* Writes to HI/LO trig writes to the mmu rams. */ | |
234 | case MMU_R_TLBLO: | |
235 | case MMU_R_TLBHI: | |
236 | i = env->mmu.regs[MMU_R_TLBX] & 0xff; | |
237 | if (rn == MMU_R_TLBHI) { | |
238 | if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0)) | |
239 | qemu_log("invalidating index %x at pc=%x\n", | |
240 | i, env->sregs[SR_PC]); | |
241 | env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff; | |
242 | mmu_flush_idx(env, i); | |
243 | } | |
244 | env->mmu.rams[rn & 1][i] = v; | |
245 | ||
246 | D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v)); | |
247 | break; | |
248 | case MMU_R_ZPR: | |
3c50a71f EI |
249 | if (env->mmu.c_mmu_tlb_access <= 1) { |
250 | qemu_log("Invalid access to MMU reg %d\n", rn); | |
251 | return; | |
252 | } | |
253 | ||
d0f3654f EI |
254 | /* Changes to the zone protection reg flush the QEMU TLB. |
255 | Fortunately, these are very uncommon. */ | |
256 | if (v != env->mmu.regs[rn]) { | |
257 | tlb_flush(env, 1); | |
258 | } | |
259 | env->mmu.regs[rn] = v; | |
260 | break; | |
afeeceb0 | 261 | case MMU_R_PID: |
3c50a71f EI |
262 | if (env->mmu.c_mmu_tlb_access <= 1) { |
263 | qemu_log("Invalid access to MMU reg %d\n", rn); | |
264 | return; | |
265 | } | |
266 | ||
afeeceb0 EI |
267 | if (v != env->mmu.regs[rn]) { |
268 | mmu_change_pid(env, v); | |
269 | env->mmu.regs[rn] = v; | |
270 | } | |
271 | break; | |
272 | case MMU_R_TLBSX: | |
273 | { | |
274 | struct microblaze_mmu_lookup lu; | |
275 | int hit; | |
3c50a71f EI |
276 | |
277 | if (env->mmu.c_mmu_tlb_access <= 1) { | |
278 | qemu_log("Invalid access to MMU reg %d\n", rn); | |
279 | return; | |
280 | } | |
281 | ||
afeeceb0 EI |
282 | hit = mmu_translate(&env->mmu, &lu, |
283 | v & TLB_EPN_MASK, 0, cpu_mmu_index(env)); | |
284 | if (hit) { | |
285 | env->mmu.regs[MMU_R_TLBX] = lu.idx; | |
286 | } else | |
287 | env->mmu.regs[MMU_R_TLBX] |= 0x80000000; | |
288 | break; | |
289 | } | |
290 | default: | |
291 | env->mmu.regs[rn] = v; | |
292 | break; | |
293 | } | |
294 | } | |
295 | ||
296 | void mmu_init(struct microblaze_mmu *mmu) | |
297 | { | |
3c50a71f EI |
298 | int i; |
299 | for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) { | |
300 | mmu->regs[i] = 0; | |
301 | } | |
afeeceb0 | 302 | } |