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Commit | Line | Data |
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6af0bf9c FB |
1 | #if !defined(__QEMU_MIPS_EXEC_H__) |
2 | #define __QEMU_MIPS_EXEC_H__ | |
3 | ||
01dbbdf1 | 4 | //#define DEBUG_OP |
6af0bf9c | 5 | |
c570fd16 | 6 | #include "config.h" |
6af0bf9c FB |
7 | #include "mips-defs.h" |
8 | #include "dyngen-exec.h" | |
01179c38 | 9 | #include "cpu-defs.h" |
6af0bf9c FB |
10 | |
11 | register struct CPUMIPSState *env asm(AREG0); | |
12 | ||
6af0bf9c FB |
13 | #include "cpu.h" |
14 | #include "exec-all.h" | |
15 | ||
16 | #if !defined(CONFIG_USER_ONLY) | |
a9049a07 | 17 | #include "softmmu_exec.h" |
6af0bf9c FB |
18 | #endif /* !defined(CONFIG_USER_ONLY) */ |
19 | ||
f3e27037 | 20 | static inline bool cpu_has_work(CPUState *env) |
6a4955a8 | 21 | { |
4cdc1cd1 AJ |
22 | int has_work = 0; |
23 | ||
24 | /* It is implementation dependent if non-enabled interrupts | |
25 | wake-up the CPU, however most of the implementations only | |
26 | check for interrupts that can be taken. */ | |
27 | if ((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
28 | cpu_mips_hw_interrupts_pending(env)) { | |
29 | has_work = 1; | |
30 | } | |
6a4955a8 | 31 | |
4cdc1cd1 AJ |
32 | return has_work; |
33 | } | |
6a4955a8 | 34 | |
c904ef0e | 35 | static inline void compute_hflags(CPUState *env) |
08fa4bab | 36 | { |
b8aa4598 | 37 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
2623c1ec AJ |
38 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
39 | MIPS_HFLAG_UX); | |
08fa4bab TS |
40 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
41 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
671880e6 | 42 | !(env->hflags & MIPS_HFLAG_DM)) { |
623a930e | 43 | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
671880e6 | 44 | } |
d26bc211 | 45 | #if defined(TARGET_MIPS64) |
623a930e | 46 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || |
08fa4bab TS |
47 | (env->CP0_Status & (1 << CP0St_PX)) || |
48 | (env->CP0_Status & (1 << CP0St_UX))) | |
49 | env->hflags |= MIPS_HFLAG_64; | |
2623c1ec AJ |
50 | if (env->CP0_Status & (1 << CP0St_UX)) |
51 | env->hflags |= MIPS_HFLAG_UX; | |
08fa4bab | 52 | #endif |
671880e6 | 53 | if ((env->CP0_Status & (1 << CP0St_CU0)) || |
623a930e | 54 | !(env->hflags & MIPS_HFLAG_KSU)) |
08fa4bab TS |
55 | env->hflags |= MIPS_HFLAG_CP0; |
56 | if (env->CP0_Status & (1 << CP0St_CU1)) | |
57 | env->hflags |= MIPS_HFLAG_FPU; | |
58 | if (env->CP0_Status & (1 << CP0St_FR)) | |
59 | env->hflags |= MIPS_HFLAG_F64; | |
b8aa4598 | 60 | if (env->insn_flags & ISA_MIPS32R2) { |
f01be154 | 61 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
b8aa4598 TS |
62 | env->hflags |= MIPS_HFLAG_COP1X; |
63 | } else if (env->insn_flags & ISA_MIPS32) { | |
64 | if (env->hflags & MIPS_HFLAG_64) | |
65 | env->hflags |= MIPS_HFLAG_COP1X; | |
66 | } else if (env->insn_flags & ISA_MIPS4) { | |
67 | /* All supported MIPS IV CPUs use the XX (CU3) to enable | |
68 | and disable the MIPS IV extensions to the MIPS III ISA. | |
69 | Some other MIPS IV CPUs ignore the bit, so the check here | |
70 | would be too restrictive for them. */ | |
71 | if (env->CP0_Status & (1 << CP0St_CU3)) | |
72 | env->hflags |= MIPS_HFLAG_COP1X; | |
73 | } | |
08fa4bab TS |
74 | } |
75 | ||
10eb0cc0 PB |
76 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
77 | { | |
78 | env->active_tc.PC = tb->pc; | |
79 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
80 | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; | |
81 | } | |
82 | ||
6af0bf9c | 83 | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |