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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
6af0bf9c | 18 | */ |
e37e863f FB |
19 | #include <stdarg.h> |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
e37e863f FB |
25 | |
26 | #include "cpu.h" | |
27 | #include "exec-all.h" | |
6af0bf9c | 28 | |
43057ab1 FB |
29 | enum { |
30 | TLBRET_DIRTY = -4, | |
31 | TLBRET_INVALID = -3, | |
32 | TLBRET_NOMATCH = -2, | |
33 | TLBRET_BADADDR = -1, | |
34 | TLBRET_MATCH = 0 | |
35 | }; | |
36 | ||
3c7b48b7 PB |
37 | #if !defined(CONFIG_USER_ONLY) |
38 | ||
29929e34 | 39 | /* no MMU emulation */ |
60c9af07 | 40 | int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
6af0bf9c | 41 | target_ulong address, int rw, int access_type) |
29929e34 TS |
42 | { |
43 | *physical = address; | |
44 | *prot = PAGE_READ | PAGE_WRITE; | |
45 | return TLBRET_MATCH; | |
46 | } | |
47 | ||
48 | /* fixed mapping MMU emulation */ | |
60c9af07 | 49 | int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
29929e34 TS |
50 | target_ulong address, int rw, int access_type) |
51 | { | |
52 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
53 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
54 | *physical = address + 0x40000000UL; | |
55 | else | |
56 | *physical = address; | |
57 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
58 | *physical = address & 0x1FFFFFFF; | |
59 | else | |
60 | *physical = address; | |
61 | ||
62 | *prot = PAGE_READ | PAGE_WRITE; | |
63 | return TLBRET_MATCH; | |
64 | } | |
65 | ||
66 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
60c9af07 | 67 | int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
29929e34 | 68 | target_ulong address, int rw, int access_type) |
6af0bf9c | 69 | { |
925fd0f2 | 70 | uint8_t ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 71 | int i; |
6af0bf9c | 72 | |
ead9360e | 73 | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
c227f099 | 74 | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; |
3b1c8be4 | 75 | /* 1k pages are not supported. */ |
f2e9ebef | 76 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 77 | target_ulong tag = address & ~mask; |
f2e9ebef | 78 | target_ulong VPN = tlb->VPN & ~mask; |
d26bc211 | 79 | #if defined(TARGET_MIPS64) |
e034e2c3 | 80 | tag &= env->SEGMask; |
100ce988 | 81 | #endif |
3b1c8be4 | 82 | |
6af0bf9c | 83 | /* Check ASID, virtual page number & size */ |
f2e9ebef | 84 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
6af0bf9c | 85 | /* TLB match */ |
f2e9ebef | 86 | int n = !!(address & mask & ~(mask >> 1)); |
6af0bf9c | 87 | /* Check access rights */ |
f2e9ebef | 88 | if (!(n ? tlb->V1 : tlb->V0)) |
43057ab1 | 89 | return TLBRET_INVALID; |
f2e9ebef | 90 | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
3b1c8be4 | 91 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
9fb63ac2 | 92 | *prot = PAGE_READ; |
98c1b82b | 93 | if (n ? tlb->D1 : tlb->D0) |
9fb63ac2 | 94 | *prot |= PAGE_WRITE; |
43057ab1 | 95 | return TLBRET_MATCH; |
6af0bf9c | 96 | } |
43057ab1 | 97 | return TLBRET_DIRTY; |
6af0bf9c FB |
98 | } |
99 | } | |
43057ab1 | 100 | return TLBRET_NOMATCH; |
6af0bf9c | 101 | } |
6af0bf9c | 102 | |
60c9af07 | 103 | static int get_physical_address (CPUState *env, target_phys_addr_t *physical, |
43057ab1 FB |
104 | int *prot, target_ulong address, |
105 | int rw, int access_type) | |
6af0bf9c | 106 | { |
b4ab4b4e | 107 | /* User mode can only access useg/xuseg */ |
43057ab1 | 108 | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
671880e6 TS |
109 | int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; |
110 | int kernel_mode = !user_mode && !supervisor_mode; | |
d26bc211 | 111 | #if defined(TARGET_MIPS64) |
b4ab4b4e TS |
112 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
113 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
114 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
115 | #endif | |
43057ab1 FB |
116 | int ret = TLBRET_MATCH; |
117 | ||
6af0bf9c | 118 | #if 0 |
93fcfe39 | 119 | qemu_log("user mode %d h %08x\n", user_mode, env->hflags); |
6af0bf9c | 120 | #endif |
b4ab4b4e | 121 | |
b4ab4b4e TS |
122 | if (address <= (int32_t)0x7FFFFFFFUL) { |
123 | /* useg */ | |
996ba2cc | 124 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
29929e34 | 125 | *physical = address & 0xFFFFFFFF; |
6af0bf9c | 126 | *prot = PAGE_READ | PAGE_WRITE; |
996ba2cc | 127 | } else { |
ead9360e | 128 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
6af0bf9c | 129 | } |
d26bc211 | 130 | #if defined(TARGET_MIPS64) |
89fc88da | 131 | } else if (address < 0x4000000000000000ULL) { |
b4ab4b4e | 132 | /* xuseg */ |
6958549d | 133 | if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
ead9360e | 134 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
6958549d AJ |
135 | } else { |
136 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 137 | } |
89fc88da | 138 | } else if (address < 0x8000000000000000ULL) { |
b4ab4b4e | 139 | /* xsseg */ |
6958549d AJ |
140 | if ((supervisor_mode || kernel_mode) && |
141 | SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { | |
ead9360e | 142 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
6958549d AJ |
143 | } else { |
144 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 145 | } |
89fc88da | 146 | } else if (address < 0xC000000000000000ULL) { |
b4ab4b4e | 147 | /* xkphys */ |
671880e6 | 148 | if (kernel_mode && KX && |
6d35524c TS |
149 | (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { |
150 | *physical = address & env->PAMask; | |
b4ab4b4e | 151 | *prot = PAGE_READ | PAGE_WRITE; |
6958549d AJ |
152 | } else { |
153 | ret = TLBRET_BADADDR; | |
154 | } | |
89fc88da | 155 | } else if (address < 0xFFFFFFFF80000000ULL) { |
b4ab4b4e | 156 | /* xkseg */ |
6958549d AJ |
157 | if (kernel_mode && KX && |
158 | address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { | |
ead9360e | 159 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
6958549d AJ |
160 | } else { |
161 | ret = TLBRET_BADADDR; | |
162 | } | |
b4ab4b4e | 163 | #endif |
5dc4b744 | 164 | } else if (address < (int32_t)0xA0000000UL) { |
6af0bf9c | 165 | /* kseg0 */ |
671880e6 TS |
166 | if (kernel_mode) { |
167 | *physical = address - (int32_t)0x80000000UL; | |
168 | *prot = PAGE_READ | PAGE_WRITE; | |
169 | } else { | |
170 | ret = TLBRET_BADADDR; | |
171 | } | |
5dc4b744 | 172 | } else if (address < (int32_t)0xC0000000UL) { |
6af0bf9c | 173 | /* kseg1 */ |
671880e6 TS |
174 | if (kernel_mode) { |
175 | *physical = address - (int32_t)0xA0000000UL; | |
176 | *prot = PAGE_READ | PAGE_WRITE; | |
177 | } else { | |
178 | ret = TLBRET_BADADDR; | |
179 | } | |
5dc4b744 | 180 | } else if (address < (int32_t)0xE0000000UL) { |
89fc88da | 181 | /* sseg (kseg2) */ |
671880e6 TS |
182 | if (supervisor_mode || kernel_mode) { |
183 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
184 | } else { | |
185 | ret = TLBRET_BADADDR; | |
186 | } | |
6af0bf9c FB |
187 | } else { |
188 | /* kseg3 */ | |
6af0bf9c | 189 | /* XXX: debug segment is not emulated */ |
671880e6 TS |
190 | if (kernel_mode) { |
191 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
192 | } else { | |
193 | ret = TLBRET_BADADDR; | |
194 | } | |
6af0bf9c FB |
195 | } |
196 | #if 0 | |
93fcfe39 AL |
197 | qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n", |
198 | address, rw, access_type, *physical, *prot, ret); | |
6af0bf9c FB |
199 | #endif |
200 | ||
201 | return ret; | |
202 | } | |
932e71cd | 203 | #endif |
6af0bf9c | 204 | |
1147e189 AJ |
205 | static void raise_mmu_exception(CPUState *env, target_ulong address, |
206 | int rw, int tlb_error) | |
207 | { | |
208 | int exception = 0, error_code = 0; | |
209 | ||
210 | switch (tlb_error) { | |
211 | default: | |
212 | case TLBRET_BADADDR: | |
213 | /* Reference to kernel address from user mode or supervisor mode */ | |
214 | /* Reference to supervisor address from user mode */ | |
215 | if (rw) | |
216 | exception = EXCP_AdES; | |
217 | else | |
218 | exception = EXCP_AdEL; | |
219 | break; | |
220 | case TLBRET_NOMATCH: | |
221 | /* No TLB match for a mapped address */ | |
222 | if (rw) | |
223 | exception = EXCP_TLBS; | |
224 | else | |
225 | exception = EXCP_TLBL; | |
226 | error_code = 1; | |
227 | break; | |
228 | case TLBRET_INVALID: | |
229 | /* TLB match with no valid bit */ | |
230 | if (rw) | |
231 | exception = EXCP_TLBS; | |
232 | else | |
233 | exception = EXCP_TLBL; | |
234 | break; | |
235 | case TLBRET_DIRTY: | |
236 | /* TLB match but 'D' bit is cleared */ | |
237 | exception = EXCP_LTLBL; | |
238 | break; | |
239 | ||
240 | } | |
241 | /* Raise exception */ | |
242 | env->CP0_BadVAddr = address; | |
243 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | | |
244 | ((address >> 9) & 0x007ffff0); | |
245 | env->CP0_EntryHi = | |
246 | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); | |
247 | #if defined(TARGET_MIPS64) | |
248 | env->CP0_EntryHi &= env->SEGMask; | |
249 | env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | | |
250 | ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | | |
251 | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); | |
252 | #endif | |
253 | env->exception_index = exception; | |
254 | env->error_code = error_code; | |
255 | } | |
256 | ||
4fcc562b | 257 | #if !defined(CONFIG_USER_ONLY) |
c227f099 | 258 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
6af0bf9c | 259 | { |
60c9af07 | 260 | target_phys_addr_t phys_addr; |
932e71cd | 261 | int prot; |
6af0bf9c | 262 | |
932e71cd AJ |
263 | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
264 | return -1; | |
265 | return phys_addr; | |
6af0bf9c | 266 | } |
4fcc562b | 267 | #endif |
6af0bf9c | 268 | |
6af0bf9c | 269 | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 270 | int mmu_idx, int is_softmmu) |
6af0bf9c | 271 | { |
932e71cd | 272 | #if !defined(CONFIG_USER_ONLY) |
60c9af07 | 273 | target_phys_addr_t physical; |
6af0bf9c | 274 | int prot; |
932e71cd | 275 | #endif |
6af0bf9c FB |
276 | int access_type; |
277 | int ret = 0; | |
278 | ||
4ad40f36 | 279 | #if 0 |
93fcfe39 | 280 | log_cpu_state(env, 0); |
4ad40f36 | 281 | #endif |
93fcfe39 AL |
282 | qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", |
283 | __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu); | |
4ad40f36 FB |
284 | |
285 | rw &= 1; | |
286 | ||
6af0bf9c FB |
287 | /* data access */ |
288 | /* XXX: put correct access by using cpu_restore_state() | |
289 | correctly */ | |
290 | access_type = ACCESS_INT; | |
932e71cd AJ |
291 | #if defined(CONFIG_USER_ONLY) |
292 | ret = TLBRET_NOMATCH; | |
293 | #else | |
6af0bf9c FB |
294 | ret = get_physical_address(env, &physical, &prot, |
295 | address, rw, access_type); | |
60c9af07 | 296 | qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n", |
93fcfe39 | 297 | __func__, address, ret, physical, prot); |
43057ab1 | 298 | if (ret == TLBRET_MATCH) { |
d4c430a8 PB |
299 | tlb_set_page(env, address & TARGET_PAGE_MASK, |
300 | physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, | |
301 | mmu_idx, TARGET_PAGE_SIZE); | |
302 | ret = 0; | |
932e71cd AJ |
303 | } else if (ret < 0) |
304 | #endif | |
305 | { | |
1147e189 | 306 | raise_mmu_exception(env, address, rw, ret); |
6af0bf9c FB |
307 | ret = 1; |
308 | } | |
309 | ||
310 | return ret; | |
311 | } | |
312 | ||
25b91e32 | 313 | #if !defined(CONFIG_USER_ONLY) |
c36bbb28 | 314 | target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw) |
25b91e32 AJ |
315 | { |
316 | target_phys_addr_t physical; | |
317 | int prot; | |
318 | int access_type; | |
319 | int ret = 0; | |
320 | ||
321 | rw &= 1; | |
322 | ||
323 | /* data access */ | |
324 | access_type = ACCESS_INT; | |
325 | ret = get_physical_address(env, &physical, &prot, | |
326 | address, rw, access_type); | |
327 | if (ret != TLBRET_MATCH) { | |
328 | raise_mmu_exception(env, address, rw, ret); | |
c36bbb28 AJ |
329 | return -1LL; |
330 | } else { | |
331 | return physical; | |
25b91e32 | 332 | } |
25b91e32 AJ |
333 | } |
334 | #endif | |
335 | ||
9a5d878f TS |
336 | static const char * const excp_names[EXCP_LAST + 1] = { |
337 | [EXCP_RESET] = "reset", | |
338 | [EXCP_SRESET] = "soft reset", | |
339 | [EXCP_DSS] = "debug single step", | |
340 | [EXCP_DINT] = "debug interrupt", | |
341 | [EXCP_NMI] = "non-maskable interrupt", | |
342 | [EXCP_MCHECK] = "machine check", | |
343 | [EXCP_EXT_INTERRUPT] = "interrupt", | |
344 | [EXCP_DFWATCH] = "deferred watchpoint", | |
345 | [EXCP_DIB] = "debug instruction breakpoint", | |
346 | [EXCP_IWATCH] = "instruction fetch watchpoint", | |
347 | [EXCP_AdEL] = "address error load", | |
348 | [EXCP_AdES] = "address error store", | |
349 | [EXCP_TLBF] = "TLB refill", | |
350 | [EXCP_IBE] = "instruction bus error", | |
351 | [EXCP_DBp] = "debug breakpoint", | |
352 | [EXCP_SYSCALL] = "syscall", | |
353 | [EXCP_BREAK] = "break", | |
354 | [EXCP_CpU] = "coprocessor unusable", | |
355 | [EXCP_RI] = "reserved instruction", | |
356 | [EXCP_OVERFLOW] = "arithmetic overflow", | |
357 | [EXCP_TRAP] = "trap", | |
358 | [EXCP_FPE] = "floating point", | |
359 | [EXCP_DDBS] = "debug data break store", | |
360 | [EXCP_DWATCH] = "data watchpoint", | |
361 | [EXCP_LTLBL] = "TLB modify", | |
362 | [EXCP_TLBL] = "TLB load", | |
363 | [EXCP_TLBS] = "TLB store", | |
364 | [EXCP_DBE] = "data bus error", | |
365 | [EXCP_DDBL] = "debug data break load", | |
366 | [EXCP_THREAD] = "thread", | |
367 | [EXCP_MDMX] = "MDMX", | |
368 | [EXCP_C2E] = "precise coprocessor 2", | |
369 | [EXCP_CACHE] = "cache error", | |
14e51cc7 | 370 | }; |
14e51cc7 | 371 | |
32188a03 NF |
372 | #if !defined(CONFIG_USER_ONLY) |
373 | static target_ulong exception_resume_pc (CPUState *env) | |
374 | { | |
375 | target_ulong bad_pc; | |
376 | target_ulong isa_mode; | |
377 | ||
378 | isa_mode = !!(env->hflags & MIPS_HFLAG_M16); | |
379 | bad_pc = env->active_tc.PC | isa_mode; | |
380 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
381 | /* If the exception was raised from a delay slot, come back to | |
382 | the jump. */ | |
383 | bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); | |
384 | } | |
385 | ||
386 | return bad_pc; | |
387 | } | |
bbfa8f72 NF |
388 | |
389 | static void set_hflags_for_handler (CPUState *env) | |
390 | { | |
391 | /* Exception handlers are entered in 32-bit mode. */ | |
392 | env->hflags &= ~(MIPS_HFLAG_M16); | |
393 | /* ...except that microMIPS lets you choose. */ | |
394 | if (env->insn_flags & ASE_MICROMIPS) { | |
395 | env->hflags |= (!!(env->CP0_Config3 | |
396 | & (1 << CP0C3_ISA_ON_EXC)) | |
397 | << MIPS_HFLAG_M16_SHIFT); | |
398 | } | |
399 | } | |
32188a03 NF |
400 | #endif |
401 | ||
6af0bf9c FB |
402 | void do_interrupt (CPUState *env) |
403 | { | |
932e71cd AJ |
404 | #if !defined(CONFIG_USER_ONLY) |
405 | target_ulong offset; | |
406 | int cause = -1; | |
407 | const char *name; | |
100ce988 | 408 | |
93fcfe39 | 409 | if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { |
932e71cd AJ |
410 | if (env->exception_index < 0 || env->exception_index > EXCP_LAST) |
411 | name = "unknown"; | |
412 | else | |
413 | name = excp_names[env->exception_index]; | |
b67bfe8d | 414 | |
93fcfe39 AL |
415 | qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", |
416 | __func__, env->active_tc.PC, env->CP0_EPC, name); | |
932e71cd AJ |
417 | } |
418 | if (env->exception_index == EXCP_EXT_INTERRUPT && | |
419 | (env->hflags & MIPS_HFLAG_DM)) | |
420 | env->exception_index = EXCP_DINT; | |
421 | offset = 0x180; | |
422 | switch (env->exception_index) { | |
423 | case EXCP_DSS: | |
424 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
425 | /* Debug single step cannot be raised inside a delay slot and | |
426 | resume will always occur on the next instruction | |
427 | (but we assume the pc has always been updated during | |
428 | code translation). */ | |
32188a03 | 429 | env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); |
932e71cd AJ |
430 | goto enter_debug_mode; |
431 | case EXCP_DINT: | |
432 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
433 | goto set_DEPC; | |
434 | case EXCP_DIB: | |
435 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
436 | goto set_DEPC; | |
437 | case EXCP_DBp: | |
438 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
439 | goto set_DEPC; | |
440 | case EXCP_DDBS: | |
441 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
442 | goto set_DEPC; | |
443 | case EXCP_DDBL: | |
444 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
445 | set_DEPC: | |
32188a03 NF |
446 | env->CP0_DEPC = exception_resume_pc(env); |
447 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
0eaef5aa | 448 | enter_debug_mode: |
932e71cd AJ |
449 | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
450 | env->hflags &= ~(MIPS_HFLAG_KSU); | |
451 | /* EJTAG probe trap enable is not implemented... */ | |
452 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
453 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
454 | env->active_tc.PC = (int32_t)0xBFC00480; | |
bbfa8f72 | 455 | set_hflags_for_handler(env); |
932e71cd AJ |
456 | break; |
457 | case EXCP_RESET: | |
458 | cpu_reset(env); | |
459 | break; | |
460 | case EXCP_SRESET: | |
461 | env->CP0_Status |= (1 << CP0St_SR); | |
462 | memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); | |
463 | goto set_error_EPC; | |
464 | case EXCP_NMI: | |
465 | env->CP0_Status |= (1 << CP0St_NMI); | |
0eaef5aa | 466 | set_error_EPC: |
32188a03 NF |
467 | env->CP0_ErrorEPC = exception_resume_pc(env); |
468 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
932e71cd AJ |
469 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
470 | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; | |
471 | env->hflags &= ~(MIPS_HFLAG_KSU); | |
472 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
473 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
474 | env->active_tc.PC = (int32_t)0xBFC00000; | |
bbfa8f72 | 475 | set_hflags_for_handler(env); |
932e71cd AJ |
476 | break; |
477 | case EXCP_EXT_INTERRUPT: | |
478 | cause = 0; | |
479 | if (env->CP0_Cause & (1 << CP0Ca_IV)) | |
480 | offset = 0x200; | |
138afb02 EI |
481 | |
482 | if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) { | |
483 | /* Vectored Interrupts. */ | |
484 | unsigned int spacing; | |
485 | unsigned int vector; | |
486 | unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8; | |
487 | ||
488 | /* Compute the Vector Spacing. */ | |
489 | spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1); | |
490 | spacing <<= 5; | |
491 | ||
492 | if (env->CP0_Config3 & (1 << CP0C3_VInt)) { | |
493 | /* For VInt mode, the MIPS computes the vector internally. */ | |
494 | for (vector = 0; vector < 8; vector++) { | |
495 | if (pending & 1) { | |
496 | /* Found it. */ | |
497 | break; | |
498 | } | |
499 | pending >>= 1; | |
500 | } | |
501 | } else { | |
502 | /* For VEIC mode, the external interrupt controller feeds the | |
503 | vector throught the CP0Cause IP lines. */ | |
504 | vector = pending; | |
505 | } | |
506 | offset = 0x200 + vector * spacing; | |
507 | } | |
932e71cd AJ |
508 | goto set_EPC; |
509 | case EXCP_LTLBL: | |
510 | cause = 1; | |
511 | goto set_EPC; | |
512 | case EXCP_TLBL: | |
513 | cause = 2; | |
514 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 515 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
516 | int R = env->CP0_BadVAddr >> 62; |
517 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
518 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
519 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 520 | |
3fc00a7b AJ |
521 | if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && |
522 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) | |
932e71cd AJ |
523 | offset = 0x080; |
524 | else | |
0eaef5aa | 525 | #endif |
932e71cd AJ |
526 | offset = 0x000; |
527 | } | |
528 | goto set_EPC; | |
529 | case EXCP_TLBS: | |
530 | cause = 3; | |
531 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 532 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
533 | int R = env->CP0_BadVAddr >> 62; |
534 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
535 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
536 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 537 | |
3fc00a7b AJ |
538 | if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && |
539 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) | |
932e71cd AJ |
540 | offset = 0x080; |
541 | else | |
0eaef5aa | 542 | #endif |
932e71cd AJ |
543 | offset = 0x000; |
544 | } | |
545 | goto set_EPC; | |
546 | case EXCP_AdEL: | |
547 | cause = 4; | |
548 | goto set_EPC; | |
549 | case EXCP_AdES: | |
550 | cause = 5; | |
551 | goto set_EPC; | |
552 | case EXCP_IBE: | |
553 | cause = 6; | |
554 | goto set_EPC; | |
555 | case EXCP_DBE: | |
556 | cause = 7; | |
557 | goto set_EPC; | |
558 | case EXCP_SYSCALL: | |
559 | cause = 8; | |
560 | goto set_EPC; | |
561 | case EXCP_BREAK: | |
562 | cause = 9; | |
563 | goto set_EPC; | |
564 | case EXCP_RI: | |
565 | cause = 10; | |
566 | goto set_EPC; | |
567 | case EXCP_CpU: | |
568 | cause = 11; | |
569 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | | |
570 | (env->error_code << CP0Ca_CE); | |
571 | goto set_EPC; | |
572 | case EXCP_OVERFLOW: | |
573 | cause = 12; | |
574 | goto set_EPC; | |
575 | case EXCP_TRAP: | |
576 | cause = 13; | |
577 | goto set_EPC; | |
578 | case EXCP_FPE: | |
579 | cause = 15; | |
580 | goto set_EPC; | |
581 | case EXCP_C2E: | |
582 | cause = 18; | |
583 | goto set_EPC; | |
584 | case EXCP_MDMX: | |
585 | cause = 22; | |
586 | goto set_EPC; | |
587 | case EXCP_DWATCH: | |
588 | cause = 23; | |
589 | /* XXX: TODO: manage defered watch exceptions */ | |
590 | goto set_EPC; | |
591 | case EXCP_MCHECK: | |
592 | cause = 24; | |
593 | goto set_EPC; | |
594 | case EXCP_THREAD: | |
595 | cause = 25; | |
596 | goto set_EPC; | |
597 | case EXCP_CACHE: | |
598 | cause = 30; | |
599 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
600 | offset = 0x100; | |
601 | } else { | |
602 | offset = 0x20000100; | |
603 | } | |
0eaef5aa | 604 | set_EPC: |
932e71cd | 605 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
32188a03 | 606 | env->CP0_EPC = exception_resume_pc(env); |
932e71cd | 607 | if (env->hflags & MIPS_HFLAG_BMASK) { |
932e71cd | 608 | env->CP0_Cause |= (1 << CP0Ca_BD); |
0eaef5aa | 609 | } else { |
932e71cd | 610 | env->CP0_Cause &= ~(1 << CP0Ca_BD); |
0eaef5aa | 611 | } |
932e71cd AJ |
612 | env->CP0_Status |= (1 << CP0St_EXL); |
613 | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; | |
614 | env->hflags &= ~(MIPS_HFLAG_KSU); | |
6af0bf9c | 615 | } |
932e71cd AJ |
616 | env->hflags &= ~MIPS_HFLAG_BMASK; |
617 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
618 | env->active_tc.PC = (int32_t)0xBFC00200; | |
619 | } else { | |
620 | env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); | |
6af0bf9c | 621 | } |
932e71cd | 622 | env->active_tc.PC += offset; |
bbfa8f72 | 623 | set_hflags_for_handler(env); |
932e71cd AJ |
624 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
625 | break; | |
626 | default: | |
93fcfe39 | 627 | qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index); |
932e71cd AJ |
628 | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); |
629 | exit(1); | |
630 | } | |
93fcfe39 AL |
631 | if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { |
632 | qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" | |
932e71cd AJ |
633 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
634 | __func__, env->active_tc.PC, env->CP0_EPC, cause, | |
635 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, | |
636 | env->CP0_DEPC); | |
6af0bf9c | 637 | } |
932e71cd | 638 | #endif |
6af0bf9c FB |
639 | env->exception_index = EXCP_NONE; |
640 | } | |
2ee4aed8 | 641 | |
3c7b48b7 | 642 | #if !defined(CONFIG_USER_ONLY) |
29929e34 | 643 | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) |
2ee4aed8 | 644 | { |
c227f099 | 645 | r4k_tlb_t *tlb; |
3b1c8be4 TS |
646 | target_ulong addr; |
647 | target_ulong end; | |
648 | uint8_t ASID = env->CP0_EntryHi & 0xFF; | |
649 | target_ulong mask; | |
2ee4aed8 | 650 | |
ead9360e | 651 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 652 | /* The qemu TLB is flushed when the ASID changes, so no need to |
2ee4aed8 FB |
653 | flush these entries again. */ |
654 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
655 | return; | |
656 | } | |
657 | ||
ead9360e | 658 | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { |
2ee4aed8 | 659 | /* For tlbwr, we can shadow the discarded entry into |
6958549d AJ |
660 | a new (fake) TLB entry, as long as the guest can not |
661 | tell that it's there. */ | |
ead9360e TS |
662 | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
663 | env->tlb->tlb_in_use++; | |
2ee4aed8 FB |
664 | return; |
665 | } | |
666 | ||
3b1c8be4 | 667 | /* 1k pages are not supported. */ |
f2e9ebef | 668 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 669 | if (tlb->V0) { |
f2e9ebef | 670 | addr = tlb->VPN & ~mask; |
d26bc211 | 671 | #if defined(TARGET_MIPS64) |
e034e2c3 | 672 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
673 | addr |= 0x3FFFFF0000000000ULL; |
674 | } | |
675 | #endif | |
3b1c8be4 TS |
676 | end = addr | (mask >> 1); |
677 | while (addr < end) { | |
678 | tlb_flush_page (env, addr); | |
679 | addr += TARGET_PAGE_SIZE; | |
680 | } | |
681 | } | |
682 | if (tlb->V1) { | |
f2e9ebef | 683 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
d26bc211 | 684 | #if defined(TARGET_MIPS64) |
e034e2c3 | 685 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
686 | addr |= 0x3FFFFF0000000000ULL; |
687 | } | |
688 | #endif | |
3b1c8be4 | 689 | end = addr | mask; |
53715e48 | 690 | while (addr - 1 < end) { |
3b1c8be4 TS |
691 | tlb_flush_page (env, addr); |
692 | addr += TARGET_PAGE_SIZE; | |
693 | } | |
694 | } | |
2ee4aed8 | 695 | } |
3c7b48b7 | 696 | #endif |