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Commit | Line | Data |
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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
6af0bf9c | 18 | */ |
2d0e944d | 19 | #include <stdlib.h> |
3e457172 | 20 | #include "cpu.h" |
05f778c8 TS |
21 | #include "host-utils.h" |
22 | ||
a7812ae4 | 23 | #include "helper.h" |
83dae095 | 24 | |
3e457172 | 25 | #if !defined(CONFIG_USER_ONLY) |
022c62cb | 26 | #include "exec/softmmu_exec.h" |
3e457172 BS |
27 | #endif /* !defined(CONFIG_USER_ONLY) */ |
28 | ||
83dae095 | 29 | #ifndef CONFIG_USER_ONLY |
7db13fae | 30 | static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global); |
83dae095 PB |
31 | #endif |
32 | ||
6af0bf9c FB |
33 | /*****************************************************************************/ |
34 | /* Exceptions processing helpers */ | |
6af0bf9c | 35 | |
5f7319cd AJ |
36 | static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, |
37 | uint32_t exception, | |
38 | int error_code, | |
39 | uintptr_t pc) | |
6af0bf9c FB |
40 | { |
41 | #if 1 | |
93fcfe39 AL |
42 | if (exception < 0x100) |
43 | qemu_log("%s: %d %d\n", __func__, exception, error_code); | |
6af0bf9c FB |
44 | #endif |
45 | env->exception_index = exception; | |
46 | env->error_code = error_code; | |
5f7319cd AJ |
47 | |
48 | if (pc) { | |
49 | /* now we have a real cpu fault */ | |
a8a826a3 | 50 | cpu_restore_state(env, pc); |
5f7319cd AJ |
51 | } |
52 | ||
1162c041 | 53 | cpu_loop_exit(env); |
6af0bf9c FB |
54 | } |
55 | ||
5f7319cd AJ |
56 | static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, |
57 | uint32_t exception, | |
58 | uintptr_t pc) | |
6af0bf9c | 59 | { |
5f7319cd | 60 | do_raise_exception_err(env, exception, 0, pc); |
6af0bf9c FB |
61 | } |
62 | ||
5f7319cd AJ |
63 | void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, |
64 | int error_code) | |
4ad40f36 | 65 | { |
5f7319cd AJ |
66 | do_raise_exception_err(env, exception, error_code, 0); |
67 | } | |
20503968 | 68 | |
5f7319cd AJ |
69 | void helper_raise_exception(CPUMIPSState *env, uint32_t exception) |
70 | { | |
71 | do_raise_exception(env, exception, 0); | |
4ad40f36 FB |
72 | } |
73 | ||
0ae43045 AJ |
74 | #if defined(CONFIG_USER_ONLY) |
75 | #define HELPER_LD(name, insn, type) \ | |
895c2d04 BS |
76 | static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
77 | int mem_idx) \ | |
0ae43045 AJ |
78 | { \ |
79 | return (type) insn##_raw(addr); \ | |
80 | } | |
81 | #else | |
82 | #define HELPER_LD(name, insn, type) \ | |
895c2d04 BS |
83 | static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
84 | int mem_idx) \ | |
0ae43045 AJ |
85 | { \ |
86 | switch (mem_idx) \ | |
87 | { \ | |
895c2d04 BS |
88 | case 0: return (type) cpu_##insn##_kernel(env, addr); break; \ |
89 | case 1: return (type) cpu_##insn##_super(env, addr); break; \ | |
0ae43045 | 90 | default: \ |
895c2d04 | 91 | case 2: return (type) cpu_##insn##_user(env, addr); break; \ |
0ae43045 AJ |
92 | } \ |
93 | } | |
94 | #endif | |
95 | HELPER_LD(lbu, ldub, uint8_t) | |
96 | HELPER_LD(lw, ldl, int32_t) | |
97 | #ifdef TARGET_MIPS64 | |
98 | HELPER_LD(ld, ldq, int64_t) | |
99 | #endif | |
100 | #undef HELPER_LD | |
101 | ||
102 | #if defined(CONFIG_USER_ONLY) | |
103 | #define HELPER_ST(name, insn, type) \ | |
895c2d04 BS |
104 | static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
105 | type val, int mem_idx) \ | |
0ae43045 AJ |
106 | { \ |
107 | insn##_raw(addr, val); \ | |
108 | } | |
109 | #else | |
110 | #define HELPER_ST(name, insn, type) \ | |
895c2d04 BS |
111 | static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
112 | type val, int mem_idx) \ | |
0ae43045 AJ |
113 | { \ |
114 | switch (mem_idx) \ | |
115 | { \ | |
895c2d04 BS |
116 | case 0: cpu_##insn##_kernel(env, addr, val); break; \ |
117 | case 1: cpu_##insn##_super(env, addr, val); break; \ | |
0ae43045 | 118 | default: \ |
895c2d04 | 119 | case 2: cpu_##insn##_user(env, addr, val); break; \ |
0ae43045 AJ |
120 | } \ |
121 | } | |
122 | #endif | |
123 | HELPER_ST(sb, stb, uint8_t) | |
124 | HELPER_ST(sw, stl, uint32_t) | |
125 | #ifdef TARGET_MIPS64 | |
126 | HELPER_ST(sd, stq, uint64_t) | |
127 | #endif | |
128 | #undef HELPER_ST | |
129 | ||
d9bea114 | 130 | target_ulong helper_clo (target_ulong arg1) |
30898801 | 131 | { |
d9bea114 | 132 | return clo32(arg1); |
30898801 TS |
133 | } |
134 | ||
d9bea114 | 135 | target_ulong helper_clz (target_ulong arg1) |
30898801 | 136 | { |
d9bea114 | 137 | return clz32(arg1); |
30898801 TS |
138 | } |
139 | ||
d26bc211 | 140 | #if defined(TARGET_MIPS64) |
d9bea114 | 141 | target_ulong helper_dclo (target_ulong arg1) |
05f778c8 | 142 | { |
d9bea114 | 143 | return clo64(arg1); |
05f778c8 TS |
144 | } |
145 | ||
d9bea114 | 146 | target_ulong helper_dclz (target_ulong arg1) |
05f778c8 | 147 | { |
d9bea114 | 148 | return clz64(arg1); |
05f778c8 | 149 | } |
d26bc211 | 150 | #endif /* TARGET_MIPS64 */ |
c570fd16 | 151 | |
6af0bf9c | 152 | /* 64 bits arithmetic for 32 bits hosts */ |
895c2d04 | 153 | static inline uint64_t get_HILO(CPUMIPSState *env) |
6af0bf9c | 154 | { |
b5dc7732 | 155 | return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; |
6af0bf9c FB |
156 | } |
157 | ||
895c2d04 | 158 | static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) |
e9c71dd1 | 159 | { |
6fc97faf | 160 | target_ulong tmp; |
b5dc7732 | 161 | env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
6fc97faf SW |
162 | tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
163 | return tmp; | |
e9c71dd1 TS |
164 | } |
165 | ||
895c2d04 | 166 | static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) |
e9c71dd1 | 167 | { |
6fc97faf | 168 | target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
b5dc7732 | 169 | env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
6fc97faf | 170 | return tmp; |
e9c71dd1 TS |
171 | } |
172 | ||
e9c71dd1 | 173 | /* Multiplication variants of the vr54xx. */ |
895c2d04 BS |
174 | target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, |
175 | target_ulong arg2) | |
e9c71dd1 | 176 | { |
895c2d04 BS |
177 | return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * |
178 | (int64_t)(int32_t)arg2)); | |
e9c71dd1 TS |
179 | } |
180 | ||
895c2d04 BS |
181 | target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, |
182 | target_ulong arg2) | |
e9c71dd1 | 183 | { |
895c2d04 BS |
184 | return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * |
185 | (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
186 | } |
187 | ||
895c2d04 BS |
188 | target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, |
189 | target_ulong arg2) | |
e9c71dd1 | 190 | { |
895c2d04 BS |
191 | return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * |
192 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
193 | } |
194 | ||
895c2d04 BS |
195 | target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, |
196 | target_ulong arg2) | |
e9c71dd1 | 197 | { |
895c2d04 BS |
198 | return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * |
199 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
200 | } |
201 | ||
895c2d04 BS |
202 | target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, |
203 | target_ulong arg2) | |
e9c71dd1 | 204 | { |
895c2d04 BS |
205 | return set_HI_LOT0(env, (uint64_t)get_HILO(env) + |
206 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
207 | } |
208 | ||
895c2d04 BS |
209 | target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, |
210 | target_ulong arg2) | |
e9c71dd1 | 211 | { |
895c2d04 BS |
212 | return set_HIT0_LO(env, (uint64_t)get_HILO(env) + |
213 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
214 | } |
215 | ||
895c2d04 BS |
216 | target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, |
217 | target_ulong arg2) | |
e9c71dd1 | 218 | { |
895c2d04 BS |
219 | return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * |
220 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
221 | } |
222 | ||
895c2d04 BS |
223 | target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, |
224 | target_ulong arg2) | |
e9c71dd1 | 225 | { |
895c2d04 BS |
226 | return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * |
227 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
228 | } |
229 | ||
895c2d04 BS |
230 | target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, |
231 | target_ulong arg2) | |
e9c71dd1 | 232 | { |
895c2d04 BS |
233 | return set_HI_LOT0(env, (uint64_t)get_HILO(env) - |
234 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
235 | } |
236 | ||
895c2d04 BS |
237 | target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, |
238 | target_ulong arg2) | |
e9c71dd1 | 239 | { |
895c2d04 BS |
240 | return set_HIT0_LO(env, (uint64_t)get_HILO(env) - |
241 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
242 | } |
243 | ||
895c2d04 BS |
244 | target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, |
245 | target_ulong arg2) | |
e9c71dd1 | 246 | { |
895c2d04 | 247 | return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); |
e9c71dd1 TS |
248 | } |
249 | ||
895c2d04 BS |
250 | target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, |
251 | target_ulong arg2) | |
e9c71dd1 | 252 | { |
895c2d04 BS |
253 | return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * |
254 | (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
255 | } |
256 | ||
895c2d04 BS |
257 | target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, |
258 | target_ulong arg2) | |
e9c71dd1 | 259 | { |
895c2d04 BS |
260 | return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * |
261 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
262 | } |
263 | ||
895c2d04 BS |
264 | target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, |
265 | target_ulong arg2) | |
e9c71dd1 | 266 | { |
895c2d04 BS |
267 | return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * |
268 | (uint64_t)(uint32_t)arg2); | |
e9c71dd1 | 269 | } |
6af0bf9c | 270 | |
214c465f | 271 | #ifdef TARGET_MIPS64 |
895c2d04 | 272 | void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2) |
214c465f | 273 | { |
d9bea114 | 274 | muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
214c465f TS |
275 | } |
276 | ||
895c2d04 | 277 | void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2) |
214c465f | 278 | { |
d9bea114 | 279 | mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
214c465f TS |
280 | } |
281 | #endif | |
282 | ||
e7139c44 | 283 | #ifndef CONFIG_USER_ONLY |
c36bbb28 | 284 | |
a8170e5e | 285 | static inline hwaddr do_translate_address(CPUMIPSState *env, |
895c2d04 BS |
286 | target_ulong address, |
287 | int rw) | |
c36bbb28 | 288 | { |
a8170e5e | 289 | hwaddr lladdr; |
c36bbb28 AJ |
290 | |
291 | lladdr = cpu_mips_translate_address(env, address, rw); | |
292 | ||
293 | if (lladdr == -1LL) { | |
1162c041 | 294 | cpu_loop_exit(env); |
c36bbb28 AJ |
295 | } else { |
296 | return lladdr; | |
297 | } | |
298 | } | |
299 | ||
e7139c44 | 300 | #define HELPER_LD_ATOMIC(name, insn) \ |
895c2d04 | 301 | target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ |
e7139c44 | 302 | { \ |
895c2d04 BS |
303 | env->lladdr = do_translate_address(env, arg, 0); \ |
304 | env->llval = do_##insn(env, arg, mem_idx); \ | |
e7139c44 AJ |
305 | return env->llval; \ |
306 | } | |
307 | HELPER_LD_ATOMIC(ll, lw) | |
308 | #ifdef TARGET_MIPS64 | |
309 | HELPER_LD_ATOMIC(lld, ld) | |
310 | #endif | |
311 | #undef HELPER_LD_ATOMIC | |
312 | ||
313 | #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ | |
895c2d04 BS |
314 | target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ |
315 | target_ulong arg2, int mem_idx) \ | |
e7139c44 AJ |
316 | { \ |
317 | target_long tmp; \ | |
318 | \ | |
319 | if (arg2 & almask) { \ | |
320 | env->CP0_BadVAddr = arg2; \ | |
895c2d04 | 321 | helper_raise_exception(env, EXCP_AdES); \ |
e7139c44 | 322 | } \ |
895c2d04 BS |
323 | if (do_translate_address(env, arg2, 1) == env->lladdr) { \ |
324 | tmp = do_##ld_insn(env, arg2, mem_idx); \ | |
e7139c44 | 325 | if (tmp == env->llval) { \ |
895c2d04 | 326 | do_##st_insn(env, arg2, arg1, mem_idx); \ |
e7139c44 AJ |
327 | return 1; \ |
328 | } \ | |
329 | } \ | |
330 | return 0; \ | |
331 | } | |
332 | HELPER_ST_ATOMIC(sc, lw, sw, 0x3) | |
333 | #ifdef TARGET_MIPS64 | |
334 | HELPER_ST_ATOMIC(scd, ld, sd, 0x7) | |
335 | #endif | |
336 | #undef HELPER_ST_ATOMIC | |
337 | #endif | |
338 | ||
c8c2227e TS |
339 | #ifdef TARGET_WORDS_BIGENDIAN |
340 | #define GET_LMASK(v) ((v) & 3) | |
341 | #define GET_OFFSET(addr, offset) (addr + (offset)) | |
342 | #else | |
343 | #define GET_LMASK(v) (((v) & 3) ^ 3) | |
344 | #define GET_OFFSET(addr, offset) (addr - (offset)) | |
345 | #endif | |
346 | ||
895c2d04 BS |
347 | void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
348 | int mem_idx) | |
c8c2227e | 349 | { |
895c2d04 | 350 | do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e | 351 | |
d9bea114 | 352 | if (GET_LMASK(arg2) <= 2) |
895c2d04 | 353 | do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 354 | |
d9bea114 | 355 | if (GET_LMASK(arg2) <= 1) |
895c2d04 | 356 | do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 357 | |
d9bea114 | 358 | if (GET_LMASK(arg2) == 0) |
895c2d04 | 359 | do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); |
c8c2227e TS |
360 | } |
361 | ||
895c2d04 BS |
362 | void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
363 | int mem_idx) | |
c8c2227e | 364 | { |
895c2d04 | 365 | do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
c8c2227e | 366 | |
d9bea114 | 367 | if (GET_LMASK(arg2) >= 1) |
895c2d04 | 368 | do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 369 | |
d9bea114 | 370 | if (GET_LMASK(arg2) >= 2) |
895c2d04 | 371 | do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 372 | |
d9bea114 | 373 | if (GET_LMASK(arg2) == 3) |
895c2d04 | 374 | do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e TS |
375 | } |
376 | ||
377 | #if defined(TARGET_MIPS64) | |
378 | /* "half" load and stores. We must do the memory access inline, | |
379 | or fault handling won't work. */ | |
380 | ||
381 | #ifdef TARGET_WORDS_BIGENDIAN | |
382 | #define GET_LMASK64(v) ((v) & 7) | |
383 | #else | |
384 | #define GET_LMASK64(v) (((v) & 7) ^ 7) | |
385 | #endif | |
386 | ||
895c2d04 BS |
387 | void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
388 | int mem_idx) | |
c8c2227e | 389 | { |
895c2d04 | 390 | do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx); |
c8c2227e | 391 | |
d9bea114 | 392 | if (GET_LMASK64(arg2) <= 6) |
895c2d04 | 393 | do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); |
c8c2227e | 394 | |
d9bea114 | 395 | if (GET_LMASK64(arg2) <= 5) |
895c2d04 | 396 | do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); |
c8c2227e | 397 | |
d9bea114 | 398 | if (GET_LMASK64(arg2) <= 4) |
895c2d04 | 399 | do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); |
c8c2227e | 400 | |
d9bea114 | 401 | if (GET_LMASK64(arg2) <= 3) |
895c2d04 | 402 | do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e | 403 | |
d9bea114 | 404 | if (GET_LMASK64(arg2) <= 2) |
895c2d04 | 405 | do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 406 | |
d9bea114 | 407 | if (GET_LMASK64(arg2) <= 1) |
895c2d04 | 408 | do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 409 | |
d9bea114 | 410 | if (GET_LMASK64(arg2) <= 0) |
895c2d04 | 411 | do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); |
c8c2227e TS |
412 | } |
413 | ||
895c2d04 BS |
414 | void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
415 | int mem_idx) | |
c8c2227e | 416 | { |
895c2d04 | 417 | do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
c8c2227e | 418 | |
d9bea114 | 419 | if (GET_LMASK64(arg2) >= 1) |
895c2d04 | 420 | do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 421 | |
d9bea114 | 422 | if (GET_LMASK64(arg2) >= 2) |
895c2d04 | 423 | do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 424 | |
d9bea114 | 425 | if (GET_LMASK64(arg2) >= 3) |
895c2d04 | 426 | do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e | 427 | |
d9bea114 | 428 | if (GET_LMASK64(arg2) >= 4) |
895c2d04 | 429 | do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); |
c8c2227e | 430 | |
d9bea114 | 431 | if (GET_LMASK64(arg2) >= 5) |
895c2d04 | 432 | do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); |
c8c2227e | 433 | |
d9bea114 | 434 | if (GET_LMASK64(arg2) >= 6) |
895c2d04 | 435 | do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); |
c8c2227e | 436 | |
d9bea114 | 437 | if (GET_LMASK64(arg2) == 7) |
895c2d04 | 438 | do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); |
c8c2227e TS |
439 | } |
440 | #endif /* TARGET_MIPS64 */ | |
441 | ||
3c824109 NF |
442 | static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; |
443 | ||
895c2d04 BS |
444 | void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
445 | uint32_t mem_idx) | |
3c824109 NF |
446 | { |
447 | target_ulong base_reglist = reglist & 0xf; | |
448 | target_ulong do_r31 = reglist & 0x10; | |
3c824109 NF |
449 | |
450 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
451 | target_ulong i; | |
452 | ||
453 | for (i = 0; i < base_reglist; i++) { | |
18bba4dc AJ |
454 | env->active_tc.gpr[multiple_regs[i]] = |
455 | (target_long)do_lw(env, addr, mem_idx); | |
3c824109 NF |
456 | addr += 4; |
457 | } | |
458 | } | |
459 | ||
460 | if (do_r31) { | |
18bba4dc | 461 | env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx); |
3c824109 NF |
462 | } |
463 | } | |
464 | ||
895c2d04 BS |
465 | void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
466 | uint32_t mem_idx) | |
3c824109 NF |
467 | { |
468 | target_ulong base_reglist = reglist & 0xf; | |
469 | target_ulong do_r31 = reglist & 0x10; | |
3c824109 NF |
470 | |
471 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
472 | target_ulong i; | |
473 | ||
474 | for (i = 0; i < base_reglist; i++) { | |
18bba4dc | 475 | do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); |
3c824109 NF |
476 | addr += 4; |
477 | } | |
478 | } | |
479 | ||
480 | if (do_r31) { | |
18bba4dc | 481 | do_sw(env, addr, env->active_tc.gpr[31], mem_idx); |
3c824109 NF |
482 | } |
483 | } | |
484 | ||
485 | #if defined(TARGET_MIPS64) | |
895c2d04 BS |
486 | void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
487 | uint32_t mem_idx) | |
3c824109 NF |
488 | { |
489 | target_ulong base_reglist = reglist & 0xf; | |
490 | target_ulong do_r31 = reglist & 0x10; | |
3c824109 NF |
491 | |
492 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
493 | target_ulong i; | |
494 | ||
495 | for (i = 0; i < base_reglist; i++) { | |
18bba4dc | 496 | env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx); |
3c824109 NF |
497 | addr += 8; |
498 | } | |
499 | } | |
500 | ||
501 | if (do_r31) { | |
18bba4dc | 502 | env->active_tc.gpr[31] = do_ld(env, addr, mem_idx); |
3c824109 NF |
503 | } |
504 | } | |
505 | ||
895c2d04 BS |
506 | void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
507 | uint32_t mem_idx) | |
3c824109 NF |
508 | { |
509 | target_ulong base_reglist = reglist & 0xf; | |
510 | target_ulong do_r31 = reglist & 0x10; | |
3c824109 NF |
511 | |
512 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
513 | target_ulong i; | |
514 | ||
515 | for (i = 0; i < base_reglist; i++) { | |
18bba4dc | 516 | do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); |
3c824109 NF |
517 | addr += 8; |
518 | } | |
519 | } | |
520 | ||
521 | if (do_r31) { | |
18bba4dc | 522 | do_sd(env, addr, env->active_tc.gpr[31], mem_idx); |
3c824109 NF |
523 | } |
524 | } | |
525 | #endif | |
526 | ||
0eaef5aa | 527 | #ifndef CONFIG_USER_ONLY |
f249412c | 528 | /* SMP helpers. */ |
b35d77d7 | 529 | static bool mips_vpe_is_wfi(MIPSCPU *c) |
f249412c | 530 | { |
b35d77d7 AF |
531 | CPUMIPSState *env = &c->env; |
532 | ||
f249412c EI |
533 | /* If the VPE is halted but otherwise active, it means it's waiting for |
534 | an interrupt. */ | |
b35d77d7 | 535 | return env->halted && mips_vpe_active(env); |
f249412c EI |
536 | } |
537 | ||
7db13fae | 538 | static inline void mips_vpe_wake(CPUMIPSState *c) |
f249412c EI |
539 | { |
540 | /* Dont set ->halted = 0 directly, let it be done via cpu_has_work | |
541 | because there might be other conditions that state that c should | |
542 | be sleeping. */ | |
543 | cpu_interrupt(c, CPU_INTERRUPT_WAKE); | |
544 | } | |
545 | ||
6f4d6b09 | 546 | static inline void mips_vpe_sleep(MIPSCPU *cpu) |
f249412c | 547 | { |
6f4d6b09 AF |
548 | CPUMIPSState *c = &cpu->env; |
549 | ||
f249412c EI |
550 | /* The VPE was shut off, really go to bed. |
551 | Reset any old _WAKE requests. */ | |
552 | c->halted = 1; | |
553 | cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE); | |
554 | } | |
555 | ||
135dd63a | 556 | static inline void mips_tc_wake(MIPSCPU *cpu, int tc) |
f249412c | 557 | { |
135dd63a AF |
558 | CPUMIPSState *c = &cpu->env; |
559 | ||
f249412c | 560 | /* FIXME: TC reschedule. */ |
b35d77d7 | 561 | if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) { |
f249412c EI |
562 | mips_vpe_wake(c); |
563 | } | |
564 | } | |
565 | ||
c6679e90 | 566 | static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) |
f249412c | 567 | { |
c6679e90 AF |
568 | CPUMIPSState *c = &cpu->env; |
569 | ||
f249412c EI |
570 | /* FIXME: TC reschedule. */ |
571 | if (!mips_vpe_active(c)) { | |
6f4d6b09 | 572 | mips_vpe_sleep(cpu); |
f249412c EI |
573 | } |
574 | } | |
575 | ||
b93bbdcd EI |
576 | /* tc should point to an int with the value of the global TC index. |
577 | This function will transform it into a local index within the | |
7db13fae | 578 | returned CPUMIPSState. |
b93bbdcd EI |
579 | |
580 | FIXME: This code assumes that all VPEs have the same number of TCs, | |
581 | which depends on runtime setup. Can probably be fixed by | |
7db13fae | 582 | walking the list of CPUMIPSStates. */ |
895c2d04 | 583 | static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) |
b93bbdcd | 584 | { |
7db13fae | 585 | CPUMIPSState *other; |
b93bbdcd EI |
586 | int vpe_idx, nr_threads = env->nr_threads; |
587 | int tc_idx = *tc; | |
588 | ||
589 | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { | |
590 | /* Not allowed to address other CPUs. */ | |
591 | *tc = env->current_tc; | |
592 | return env; | |
593 | } | |
594 | ||
595 | vpe_idx = tc_idx / nr_threads; | |
596 | *tc = tc_idx % nr_threads; | |
597 | other = qemu_get_cpu(vpe_idx); | |
598 | return other ? other : env; | |
599 | } | |
600 | ||
fe8dca8c EI |
601 | /* The per VPE CP0_Status register shares some fields with the per TC |
602 | CP0_TCStatus registers. These fields are wired to the same registers, | |
603 | so changes to either of them should be reflected on both registers. | |
604 | ||
605 | Also, EntryHi shares the bottom 8 bit ASID with TCStauts. | |
606 | ||
607 | These helper call synchronizes the regs for a given cpu. */ | |
608 | ||
609 | /* Called for updates to CP0_Status. */ | |
895c2d04 | 610 | static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) |
fe8dca8c EI |
611 | { |
612 | int32_t tcstatus, *tcst; | |
613 | uint32_t v = cpu->CP0_Status; | |
614 | uint32_t cu, mx, asid, ksu; | |
615 | uint32_t mask = ((1 << CP0TCSt_TCU3) | |
616 | | (1 << CP0TCSt_TCU2) | |
617 | | (1 << CP0TCSt_TCU1) | |
618 | | (1 << CP0TCSt_TCU0) | |
619 | | (1 << CP0TCSt_TMX) | |
620 | | (3 << CP0TCSt_TKSU) | |
621 | | (0xff << CP0TCSt_TASID)); | |
622 | ||
623 | cu = (v >> CP0St_CU0) & 0xf; | |
624 | mx = (v >> CP0St_MX) & 0x1; | |
625 | ksu = (v >> CP0St_KSU) & 0x3; | |
626 | asid = env->CP0_EntryHi & 0xff; | |
627 | ||
628 | tcstatus = cu << CP0TCSt_TCU0; | |
629 | tcstatus |= mx << CP0TCSt_TMX; | |
630 | tcstatus |= ksu << CP0TCSt_TKSU; | |
631 | tcstatus |= asid; | |
632 | ||
633 | if (tc == cpu->current_tc) { | |
634 | tcst = &cpu->active_tc.CP0_TCStatus; | |
635 | } else { | |
636 | tcst = &cpu->tcs[tc].CP0_TCStatus; | |
637 | } | |
638 | ||
639 | *tcst &= ~mask; | |
640 | *tcst |= tcstatus; | |
641 | compute_hflags(cpu); | |
642 | } | |
643 | ||
644 | /* Called for updates to CP0_TCStatus. */ | |
895c2d04 BS |
645 | static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, |
646 | target_ulong v) | |
fe8dca8c EI |
647 | { |
648 | uint32_t status; | |
649 | uint32_t tcu, tmx, tasid, tksu; | |
650 | uint32_t mask = ((1 << CP0St_CU3) | |
651 | | (1 << CP0St_CU2) | |
652 | | (1 << CP0St_CU1) | |
653 | | (1 << CP0St_CU0) | |
654 | | (1 << CP0St_MX) | |
655 | | (3 << CP0St_KSU)); | |
656 | ||
657 | tcu = (v >> CP0TCSt_TCU0) & 0xf; | |
658 | tmx = (v >> CP0TCSt_TMX) & 0x1; | |
659 | tasid = v & 0xff; | |
660 | tksu = (v >> CP0TCSt_TKSU) & 0x3; | |
661 | ||
662 | status = tcu << CP0St_CU0; | |
663 | status |= tmx << CP0St_MX; | |
664 | status |= tksu << CP0St_KSU; | |
665 | ||
666 | cpu->CP0_Status &= ~mask; | |
667 | cpu->CP0_Status |= status; | |
668 | ||
669 | /* Sync the TASID with EntryHi. */ | |
670 | cpu->CP0_EntryHi &= ~0xff; | |
671 | cpu->CP0_EntryHi = tasid; | |
672 | ||
673 | compute_hflags(cpu); | |
674 | } | |
675 | ||
676 | /* Called for updates to CP0_EntryHi. */ | |
7db13fae | 677 | static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) |
fe8dca8c EI |
678 | { |
679 | int32_t *tcst; | |
680 | uint32_t asid, v = cpu->CP0_EntryHi; | |
681 | ||
682 | asid = v & 0xff; | |
683 | ||
684 | if (tc == cpu->current_tc) { | |
685 | tcst = &cpu->active_tc.CP0_TCStatus; | |
686 | } else { | |
687 | tcst = &cpu->tcs[tc].CP0_TCStatus; | |
688 | } | |
689 | ||
690 | *tcst &= ~0xff; | |
691 | *tcst |= asid; | |
692 | } | |
693 | ||
6af0bf9c | 694 | /* CP0 helpers */ |
895c2d04 | 695 | target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) |
f1aa6320 | 696 | { |
be24bb4f | 697 | return env->mvp->CP0_MVPControl; |
f1aa6320 TS |
698 | } |
699 | ||
895c2d04 | 700 | target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) |
f1aa6320 | 701 | { |
be24bb4f | 702 | return env->mvp->CP0_MVPConf0; |
f1aa6320 TS |
703 | } |
704 | ||
895c2d04 | 705 | target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) |
f1aa6320 | 706 | { |
be24bb4f | 707 | return env->mvp->CP0_MVPConf1; |
f1aa6320 TS |
708 | } |
709 | ||
895c2d04 | 710 | target_ulong helper_mfc0_random(CPUMIPSState *env) |
6af0bf9c | 711 | { |
be24bb4f | 712 | return (int32_t)cpu_mips_get_random(env); |
873eb012 | 713 | } |
6af0bf9c | 714 | |
895c2d04 | 715 | target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) |
f1aa6320 | 716 | { |
b5dc7732 | 717 | return env->active_tc.CP0_TCStatus; |
f1aa6320 TS |
718 | } |
719 | ||
895c2d04 | 720 | target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) |
f1aa6320 TS |
721 | { |
722 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 723 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 724 | |
b93bbdcd EI |
725 | if (other_tc == other->current_tc) |
726 | return other->active_tc.CP0_TCStatus; | |
b5dc7732 | 727 | else |
b93bbdcd | 728 | return other->tcs[other_tc].CP0_TCStatus; |
f1aa6320 TS |
729 | } |
730 | ||
895c2d04 | 731 | target_ulong helper_mfc0_tcbind(CPUMIPSState *env) |
f1aa6320 | 732 | { |
b5dc7732 | 733 | return env->active_tc.CP0_TCBind; |
f1aa6320 TS |
734 | } |
735 | ||
895c2d04 | 736 | target_ulong helper_mftc0_tcbind(CPUMIPSState *env) |
f1aa6320 TS |
737 | { |
738 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 739 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 740 | |
b93bbdcd EI |
741 | if (other_tc == other->current_tc) |
742 | return other->active_tc.CP0_TCBind; | |
b5dc7732 | 743 | else |
b93bbdcd | 744 | return other->tcs[other_tc].CP0_TCBind; |
f1aa6320 TS |
745 | } |
746 | ||
895c2d04 | 747 | target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) |
f1aa6320 | 748 | { |
b5dc7732 | 749 | return env->active_tc.PC; |
f1aa6320 TS |
750 | } |
751 | ||
895c2d04 | 752 | target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) |
f1aa6320 TS |
753 | { |
754 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 755 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 756 | |
b93bbdcd EI |
757 | if (other_tc == other->current_tc) |
758 | return other->active_tc.PC; | |
b5dc7732 | 759 | else |
b93bbdcd | 760 | return other->tcs[other_tc].PC; |
f1aa6320 TS |
761 | } |
762 | ||
895c2d04 | 763 | target_ulong helper_mfc0_tchalt(CPUMIPSState *env) |
f1aa6320 | 764 | { |
b5dc7732 | 765 | return env->active_tc.CP0_TCHalt; |
f1aa6320 TS |
766 | } |
767 | ||
895c2d04 | 768 | target_ulong helper_mftc0_tchalt(CPUMIPSState *env) |
f1aa6320 TS |
769 | { |
770 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 771 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 772 | |
b93bbdcd EI |
773 | if (other_tc == other->current_tc) |
774 | return other->active_tc.CP0_TCHalt; | |
b5dc7732 | 775 | else |
b93bbdcd | 776 | return other->tcs[other_tc].CP0_TCHalt; |
f1aa6320 TS |
777 | } |
778 | ||
895c2d04 | 779 | target_ulong helper_mfc0_tccontext(CPUMIPSState *env) |
f1aa6320 | 780 | { |
b5dc7732 | 781 | return env->active_tc.CP0_TCContext; |
f1aa6320 TS |
782 | } |
783 | ||
895c2d04 | 784 | target_ulong helper_mftc0_tccontext(CPUMIPSState *env) |
f1aa6320 TS |
785 | { |
786 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 787 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 788 | |
b93bbdcd EI |
789 | if (other_tc == other->current_tc) |
790 | return other->active_tc.CP0_TCContext; | |
b5dc7732 | 791 | else |
b93bbdcd | 792 | return other->tcs[other_tc].CP0_TCContext; |
f1aa6320 TS |
793 | } |
794 | ||
895c2d04 | 795 | target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) |
f1aa6320 | 796 | { |
b5dc7732 | 797 | return env->active_tc.CP0_TCSchedule; |
f1aa6320 TS |
798 | } |
799 | ||
895c2d04 | 800 | target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) |
f1aa6320 TS |
801 | { |
802 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 803 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 804 | |
b93bbdcd EI |
805 | if (other_tc == other->current_tc) |
806 | return other->active_tc.CP0_TCSchedule; | |
b5dc7732 | 807 | else |
b93bbdcd | 808 | return other->tcs[other_tc].CP0_TCSchedule; |
f1aa6320 TS |
809 | } |
810 | ||
895c2d04 | 811 | target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) |
f1aa6320 | 812 | { |
b5dc7732 | 813 | return env->active_tc.CP0_TCScheFBack; |
f1aa6320 TS |
814 | } |
815 | ||
895c2d04 | 816 | target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) |
f1aa6320 TS |
817 | { |
818 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 819 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 820 | |
b93bbdcd EI |
821 | if (other_tc == other->current_tc) |
822 | return other->active_tc.CP0_TCScheFBack; | |
b5dc7732 | 823 | else |
b93bbdcd | 824 | return other->tcs[other_tc].CP0_TCScheFBack; |
f1aa6320 TS |
825 | } |
826 | ||
895c2d04 | 827 | target_ulong helper_mfc0_count(CPUMIPSState *env) |
873eb012 | 828 | { |
be24bb4f | 829 | return (int32_t)cpu_mips_get_count(env); |
6af0bf9c FB |
830 | } |
831 | ||
895c2d04 | 832 | target_ulong helper_mftc0_entryhi(CPUMIPSState *env) |
f1aa6320 TS |
833 | { |
834 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 835 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 836 | |
fe8dca8c | 837 | return other->CP0_EntryHi; |
f1aa6320 TS |
838 | } |
839 | ||
895c2d04 | 840 | target_ulong helper_mftc0_cause(CPUMIPSState *env) |
5a25ce94 EI |
841 | { |
842 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
843 | int32_t tccause; | |
895c2d04 | 844 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
845 | |
846 | if (other_tc == other->current_tc) { | |
847 | tccause = other->CP0_Cause; | |
848 | } else { | |
849 | tccause = other->CP0_Cause; | |
850 | } | |
851 | ||
852 | return tccause; | |
853 | } | |
854 | ||
895c2d04 | 855 | target_ulong helper_mftc0_status(CPUMIPSState *env) |
f1aa6320 TS |
856 | { |
857 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 858 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
b5dc7732 | 859 | |
fe8dca8c | 860 | return other->CP0_Status; |
f1aa6320 TS |
861 | } |
862 | ||
895c2d04 | 863 | target_ulong helper_mfc0_lladdr(CPUMIPSState *env) |
f1aa6320 | 864 | { |
2a6e32dd | 865 | return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); |
f1aa6320 TS |
866 | } |
867 | ||
895c2d04 | 868 | target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
f1aa6320 | 869 | { |
be24bb4f | 870 | return (int32_t)env->CP0_WatchLo[sel]; |
f1aa6320 TS |
871 | } |
872 | ||
895c2d04 | 873 | target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) |
f1aa6320 | 874 | { |
be24bb4f | 875 | return env->CP0_WatchHi[sel]; |
f1aa6320 TS |
876 | } |
877 | ||
895c2d04 | 878 | target_ulong helper_mfc0_debug(CPUMIPSState *env) |
f1aa6320 | 879 | { |
1a3fd9c3 | 880 | target_ulong t0 = env->CP0_Debug; |
f1aa6320 | 881 | if (env->hflags & MIPS_HFLAG_DM) |
be24bb4f TS |
882 | t0 |= 1 << CP0DB_DM; |
883 | ||
884 | return t0; | |
f1aa6320 TS |
885 | } |
886 | ||
895c2d04 | 887 | target_ulong helper_mftc0_debug(CPUMIPSState *env) |
f1aa6320 TS |
888 | { |
889 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 | 890 | int32_t tcstatus; |
895c2d04 | 891 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
b5dc7732 | 892 | |
b93bbdcd EI |
893 | if (other_tc == other->current_tc) |
894 | tcstatus = other->active_tc.CP0_Debug_tcstatus; | |
b5dc7732 | 895 | else |
b93bbdcd | 896 | tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus; |
f1aa6320 TS |
897 | |
898 | /* XXX: Might be wrong, check with EJTAG spec. */ | |
b93bbdcd | 899 | return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
b5dc7732 | 900 | (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
f1aa6320 TS |
901 | } |
902 | ||
903 | #if defined(TARGET_MIPS64) | |
895c2d04 | 904 | target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) |
f1aa6320 | 905 | { |
b5dc7732 | 906 | return env->active_tc.PC; |
f1aa6320 TS |
907 | } |
908 | ||
895c2d04 | 909 | target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) |
f1aa6320 | 910 | { |
b5dc7732 | 911 | return env->active_tc.CP0_TCHalt; |
f1aa6320 TS |
912 | } |
913 | ||
895c2d04 | 914 | target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) |
f1aa6320 | 915 | { |
b5dc7732 | 916 | return env->active_tc.CP0_TCContext; |
f1aa6320 TS |
917 | } |
918 | ||
895c2d04 | 919 | target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) |
f1aa6320 | 920 | { |
b5dc7732 | 921 | return env->active_tc.CP0_TCSchedule; |
f1aa6320 TS |
922 | } |
923 | ||
895c2d04 | 924 | target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) |
f1aa6320 | 925 | { |
b5dc7732 | 926 | return env->active_tc.CP0_TCScheFBack; |
f1aa6320 TS |
927 | } |
928 | ||
895c2d04 | 929 | target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) |
f1aa6320 | 930 | { |
2a6e32dd | 931 | return env->lladdr >> env->CP0_LLAddr_shift; |
f1aa6320 TS |
932 | } |
933 | ||
895c2d04 | 934 | target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
f1aa6320 | 935 | { |
be24bb4f | 936 | return env->CP0_WatchLo[sel]; |
f1aa6320 TS |
937 | } |
938 | #endif /* TARGET_MIPS64 */ | |
939 | ||
895c2d04 | 940 | void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
941 | { |
942 | int num = 1; | |
943 | unsigned int tmp = env->tlb->nb_tlb; | |
944 | ||
945 | do { | |
946 | tmp >>= 1; | |
947 | num <<= 1; | |
948 | } while (tmp); | |
d9bea114 | 949 | env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); |
f1aa6320 TS |
950 | } |
951 | ||
895c2d04 | 952 | void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
953 | { |
954 | uint32_t mask = 0; | |
955 | uint32_t newval; | |
956 | ||
957 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) | |
958 | mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | | |
959 | (1 << CP0MVPCo_EVP); | |
960 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
961 | mask |= (1 << CP0MVPCo_STLB); | |
d9bea114 | 962 | newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); |
f1aa6320 TS |
963 | |
964 | // TODO: Enable/disable shared TLB, enable/disable VPEs. | |
965 | ||
966 | env->mvp->CP0_MVPControl = newval; | |
967 | } | |
968 | ||
895c2d04 | 969 | void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
970 | { |
971 | uint32_t mask; | |
972 | uint32_t newval; | |
973 | ||
974 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | | |
975 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); | |
d9bea114 | 976 | newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); |
f1aa6320 TS |
977 | |
978 | /* Yield scheduler intercept not implemented. */ | |
979 | /* Gating storage scheduler intercept not implemented. */ | |
980 | ||
981 | // TODO: Enable/disable TCs. | |
982 | ||
983 | env->CP0_VPEControl = newval; | |
984 | } | |
985 | ||
895c2d04 | 986 | void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
987 | { |
988 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 989 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
990 | uint32_t mask; |
991 | uint32_t newval; | |
992 | ||
993 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | | |
994 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); | |
995 | newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask); | |
996 | ||
997 | /* TODO: Enable/disable TCs. */ | |
998 | ||
999 | other->CP0_VPEControl = newval; | |
1000 | } | |
1001 | ||
895c2d04 | 1002 | target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) |
5a25ce94 EI |
1003 | { |
1004 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1005 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1006 | /* FIXME: Mask away return zero on read bits. */ |
1007 | return other->CP0_VPEControl; | |
1008 | } | |
1009 | ||
895c2d04 | 1010 | target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) |
5a25ce94 EI |
1011 | { |
1012 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1013 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1014 | |
1015 | return other->CP0_VPEConf0; | |
1016 | } | |
1017 | ||
895c2d04 | 1018 | void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1019 | { |
1020 | uint32_t mask = 0; | |
1021 | uint32_t newval; | |
1022 | ||
1023 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { | |
1024 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) | |
1025 | mask |= (0xff << CP0VPEC0_XTC); | |
1026 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); | |
1027 | } | |
d9bea114 | 1028 | newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1029 | |
1030 | // TODO: TC exclusive handling due to ERL/EXL. | |
1031 | ||
1032 | env->CP0_VPEConf0 = newval; | |
1033 | } | |
1034 | ||
895c2d04 | 1035 | void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
1036 | { |
1037 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1038 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1039 | uint32_t mask = 0; |
1040 | uint32_t newval; | |
1041 | ||
1042 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); | |
1043 | newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask); | |
1044 | ||
1045 | /* TODO: TC exclusive handling due to ERL/EXL. */ | |
1046 | other->CP0_VPEConf0 = newval; | |
1047 | } | |
1048 | ||
895c2d04 | 1049 | void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1050 | { |
1051 | uint32_t mask = 0; | |
1052 | uint32_t newval; | |
1053 | ||
1054 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
1055 | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | | |
1056 | (0xff << CP0VPEC1_NCP1); | |
d9bea114 | 1057 | newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1058 | |
1059 | /* UDI not implemented. */ | |
1060 | /* CP2 not implemented. */ | |
1061 | ||
1062 | // TODO: Handle FPU (CP1) binding. | |
1063 | ||
1064 | env->CP0_VPEConf1 = newval; | |
1065 | } | |
1066 | ||
895c2d04 | 1067 | void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1068 | { |
1069 | /* Yield qualifier inputs not implemented. */ | |
1070 | env->CP0_YQMask = 0x00000000; | |
1071 | } | |
1072 | ||
895c2d04 | 1073 | void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1074 | { |
d9bea114 | 1075 | env->CP0_VPEOpt = arg1 & 0x0000ffff; |
f1aa6320 TS |
1076 | } |
1077 | ||
895c2d04 | 1078 | void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1079 | { |
1080 | /* Large physaddr (PABITS) not implemented */ | |
1081 | /* 1k pages not implemented */ | |
d9bea114 | 1082 | env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF; |
f1aa6320 TS |
1083 | } |
1084 | ||
895c2d04 | 1085 | void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1086 | { |
1087 | uint32_t mask = env->CP0_TCStatus_rw_bitmask; | |
1088 | uint32_t newval; | |
1089 | ||
d9bea114 | 1090 | newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); |
f1aa6320 | 1091 | |
b5dc7732 | 1092 | env->active_tc.CP0_TCStatus = newval; |
fe8dca8c | 1093 | sync_c0_tcstatus(env, env->current_tc, newval); |
f1aa6320 TS |
1094 | } |
1095 | ||
895c2d04 | 1096 | void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1097 | { |
1098 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1099 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1100 | |
b93bbdcd EI |
1101 | if (other_tc == other->current_tc) |
1102 | other->active_tc.CP0_TCStatus = arg1; | |
b5dc7732 | 1103 | else |
b93bbdcd | 1104 | other->tcs[other_tc].CP0_TCStatus = arg1; |
fe8dca8c | 1105 | sync_c0_tcstatus(other, other_tc, arg1); |
f1aa6320 TS |
1106 | } |
1107 | ||
895c2d04 | 1108 | void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1109 | { |
1110 | uint32_t mask = (1 << CP0TCBd_TBE); | |
1111 | uint32_t newval; | |
1112 | ||
1113 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
1114 | mask |= (1 << CP0TCBd_CurVPE); | |
d9bea114 | 1115 | newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
b5dc7732 | 1116 | env->active_tc.CP0_TCBind = newval; |
f1aa6320 TS |
1117 | } |
1118 | ||
895c2d04 | 1119 | void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1120 | { |
1121 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1122 | uint32_t mask = (1 << CP0TCBd_TBE); | |
1123 | uint32_t newval; | |
895c2d04 | 1124 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1125 | |
b93bbdcd | 1126 | if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
f1aa6320 | 1127 | mask |= (1 << CP0TCBd_CurVPE); |
b93bbdcd EI |
1128 | if (other_tc == other->current_tc) { |
1129 | newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); | |
1130 | other->active_tc.CP0_TCBind = newval; | |
b5dc7732 | 1131 | } else { |
b93bbdcd EI |
1132 | newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); |
1133 | other->tcs[other_tc].CP0_TCBind = newval; | |
b5dc7732 | 1134 | } |
f1aa6320 TS |
1135 | } |
1136 | ||
895c2d04 | 1137 | void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1138 | { |
d9bea114 | 1139 | env->active_tc.PC = arg1; |
b5dc7732 | 1140 | env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
5499b6ff | 1141 | env->lladdr = 0ULL; |
f1aa6320 TS |
1142 | /* MIPS16 not implemented. */ |
1143 | } | |
1144 | ||
895c2d04 | 1145 | void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1146 | { |
1147 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1148 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1149 | |
b93bbdcd EI |
1150 | if (other_tc == other->current_tc) { |
1151 | other->active_tc.PC = arg1; | |
1152 | other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); | |
1153 | other->lladdr = 0ULL; | |
b5dc7732 TS |
1154 | /* MIPS16 not implemented. */ |
1155 | } else { | |
b93bbdcd EI |
1156 | other->tcs[other_tc].PC = arg1; |
1157 | other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); | |
1158 | other->lladdr = 0ULL; | |
b5dc7732 TS |
1159 | /* MIPS16 not implemented. */ |
1160 | } | |
f1aa6320 TS |
1161 | } |
1162 | ||
895c2d04 | 1163 | void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1164 | { |
135dd63a AF |
1165 | MIPSCPU *cpu = mips_env_get_cpu(env); |
1166 | ||
d9bea114 | 1167 | env->active_tc.CP0_TCHalt = arg1 & 0x1; |
f1aa6320 TS |
1168 | |
1169 | // TODO: Halt TC / Restart (if allocated+active) TC. | |
f249412c | 1170 | if (env->active_tc.CP0_TCHalt & 1) { |
c6679e90 | 1171 | mips_tc_sleep(cpu, env->current_tc); |
f249412c | 1172 | } else { |
135dd63a | 1173 | mips_tc_wake(cpu, env->current_tc); |
f249412c | 1174 | } |
f1aa6320 TS |
1175 | } |
1176 | ||
895c2d04 | 1177 | void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1178 | { |
1179 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1180 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
135dd63a | 1181 | MIPSCPU *other_cpu = mips_env_get_cpu(other); |
f1aa6320 TS |
1182 | |
1183 | // TODO: Halt TC / Restart (if allocated+active) TC. | |
1184 | ||
b93bbdcd EI |
1185 | if (other_tc == other->current_tc) |
1186 | other->active_tc.CP0_TCHalt = arg1; | |
b5dc7732 | 1187 | else |
b93bbdcd | 1188 | other->tcs[other_tc].CP0_TCHalt = arg1; |
f249412c EI |
1189 | |
1190 | if (arg1 & 1) { | |
c6679e90 | 1191 | mips_tc_sleep(other_cpu, other_tc); |
f249412c | 1192 | } else { |
135dd63a | 1193 | mips_tc_wake(other_cpu, other_tc); |
f249412c | 1194 | } |
f1aa6320 TS |
1195 | } |
1196 | ||
895c2d04 | 1197 | void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1198 | { |
d9bea114 | 1199 | env->active_tc.CP0_TCContext = arg1; |
f1aa6320 TS |
1200 | } |
1201 | ||
895c2d04 | 1202 | void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1203 | { |
1204 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1205 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1206 | |
b93bbdcd EI |
1207 | if (other_tc == other->current_tc) |
1208 | other->active_tc.CP0_TCContext = arg1; | |
b5dc7732 | 1209 | else |
b93bbdcd | 1210 | other->tcs[other_tc].CP0_TCContext = arg1; |
f1aa6320 TS |
1211 | } |
1212 | ||
895c2d04 | 1213 | void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1214 | { |
d9bea114 | 1215 | env->active_tc.CP0_TCSchedule = arg1; |
f1aa6320 TS |
1216 | } |
1217 | ||
895c2d04 | 1218 | void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1219 | { |
1220 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1221 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1222 | |
b93bbdcd EI |
1223 | if (other_tc == other->current_tc) |
1224 | other->active_tc.CP0_TCSchedule = arg1; | |
b5dc7732 | 1225 | else |
b93bbdcd | 1226 | other->tcs[other_tc].CP0_TCSchedule = arg1; |
f1aa6320 TS |
1227 | } |
1228 | ||
895c2d04 | 1229 | void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1230 | { |
d9bea114 | 1231 | env->active_tc.CP0_TCScheFBack = arg1; |
f1aa6320 TS |
1232 | } |
1233 | ||
895c2d04 | 1234 | void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1235 | { |
1236 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1237 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1238 | |
b93bbdcd EI |
1239 | if (other_tc == other->current_tc) |
1240 | other->active_tc.CP0_TCScheFBack = arg1; | |
b5dc7732 | 1241 | else |
b93bbdcd | 1242 | other->tcs[other_tc].CP0_TCScheFBack = arg1; |
f1aa6320 TS |
1243 | } |
1244 | ||
895c2d04 | 1245 | void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1246 | { |
1247 | /* Large physaddr (PABITS) not implemented */ | |
1248 | /* 1k pages not implemented */ | |
d9bea114 | 1249 | env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF; |
f1aa6320 TS |
1250 | } |
1251 | ||
895c2d04 | 1252 | void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1253 | { |
d9bea114 | 1254 | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); |
f1aa6320 TS |
1255 | } |
1256 | ||
895c2d04 | 1257 | void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1258 | { |
1259 | /* 1k pages not implemented */ | |
d9bea114 | 1260 | env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
f1aa6320 TS |
1261 | } |
1262 | ||
895c2d04 | 1263 | void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1264 | { |
1265 | /* SmartMIPS not implemented */ | |
1266 | /* Large physaddr (PABITS) not implemented */ | |
1267 | /* 1k pages not implemented */ | |
1268 | env->CP0_PageGrain = 0; | |
1269 | } | |
1270 | ||
895c2d04 | 1271 | void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1272 | { |
d9bea114 | 1273 | env->CP0_Wired = arg1 % env->tlb->nb_tlb; |
f1aa6320 TS |
1274 | } |
1275 | ||
895c2d04 | 1276 | void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1277 | { |
d9bea114 | 1278 | env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; |
f1aa6320 TS |
1279 | } |
1280 | ||
895c2d04 | 1281 | void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1282 | { |
d9bea114 | 1283 | env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; |
f1aa6320 TS |
1284 | } |
1285 | ||
895c2d04 | 1286 | void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1287 | { |
d9bea114 | 1288 | env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; |
f1aa6320 TS |
1289 | } |
1290 | ||
895c2d04 | 1291 | void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1292 | { |
d9bea114 | 1293 | env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; |
f1aa6320 TS |
1294 | } |
1295 | ||
895c2d04 | 1296 | void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1297 | { |
d9bea114 | 1298 | env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; |
f1aa6320 TS |
1299 | } |
1300 | ||
895c2d04 | 1301 | void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1302 | { |
d9bea114 | 1303 | env->CP0_HWREna = arg1 & 0x0000000F; |
f1aa6320 TS |
1304 | } |
1305 | ||
895c2d04 | 1306 | void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1307 | { |
d9bea114 | 1308 | cpu_mips_store_count(env, arg1); |
f1aa6320 TS |
1309 | } |
1310 | ||
895c2d04 | 1311 | void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1312 | { |
1313 | target_ulong old, val; | |
1314 | ||
1315 | /* 1k pages not implemented */ | |
d9bea114 | 1316 | val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
f1aa6320 TS |
1317 | #if defined(TARGET_MIPS64) |
1318 | val &= env->SEGMask; | |
1319 | #endif | |
1320 | old = env->CP0_EntryHi; | |
1321 | env->CP0_EntryHi = val; | |
1322 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { | |
fe8dca8c | 1323 | sync_c0_entryhi(env, env->current_tc); |
f1aa6320 TS |
1324 | } |
1325 | /* If the ASID changes, flush qemu's TLB. */ | |
1326 | if ((old & 0xFF) != (val & 0xFF)) | |
1327 | cpu_mips_tlb_flush(env, 1); | |
1328 | } | |
1329 | ||
895c2d04 | 1330 | void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1331 | { |
1332 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1333 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1334 | |
fe8dca8c EI |
1335 | other->CP0_EntryHi = arg1; |
1336 | sync_c0_entryhi(other, other_tc); | |
f1aa6320 TS |
1337 | } |
1338 | ||
895c2d04 | 1339 | void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1340 | { |
d9bea114 | 1341 | cpu_mips_store_compare(env, arg1); |
f1aa6320 TS |
1342 | } |
1343 | ||
895c2d04 | 1344 | void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1345 | { |
1346 | uint32_t val, old; | |
1347 | uint32_t mask = env->CP0_Status_rw_bitmask; | |
1348 | ||
d9bea114 | 1349 | val = arg1 & mask; |
f1aa6320 TS |
1350 | old = env->CP0_Status; |
1351 | env->CP0_Status = (env->CP0_Status & ~mask) | val; | |
fe8dca8c | 1352 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
895c2d04 | 1353 | sync_c0_status(env, env, env->current_tc); |
fe8dca8c EI |
1354 | } else { |
1355 | compute_hflags(env); | |
1356 | } | |
1357 | ||
c01fccd2 AJ |
1358 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
1359 | qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x", | |
1360 | old, old & env->CP0_Cause & CP0Ca_IP_mask, | |
1361 | val, val & env->CP0_Cause & CP0Ca_IP_mask, | |
1362 | env->CP0_Cause); | |
1363 | switch (env->hflags & MIPS_HFLAG_KSU) { | |
1364 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; | |
1365 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; | |
1366 | case MIPS_HFLAG_KM: qemu_log("\n"); break; | |
1367 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; | |
31e3104f | 1368 | } |
c01fccd2 | 1369 | } |
f1aa6320 TS |
1370 | } |
1371 | ||
895c2d04 | 1372 | void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1373 | { |
1374 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1375 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1376 | |
b93bbdcd | 1377 | other->CP0_Status = arg1 & ~0xf1000018; |
895c2d04 | 1378 | sync_c0_status(env, other, other_tc); |
f1aa6320 TS |
1379 | } |
1380 | ||
895c2d04 | 1381 | void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1382 | { |
1383 | /* vectored interrupts not implemented, no performance counters. */ | |
bc45a67a | 1384 | env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); |
f1aa6320 TS |
1385 | } |
1386 | ||
895c2d04 | 1387 | void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1388 | { |
1389 | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); | |
d9bea114 | 1390 | env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1391 | } |
1392 | ||
7db13fae | 1393 | static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1) |
f1aa6320 TS |
1394 | { |
1395 | uint32_t mask = 0x00C00300; | |
5a25ce94 | 1396 | uint32_t old = cpu->CP0_Cause; |
5dc5d9f0 | 1397 | int i; |
f1aa6320 | 1398 | |
5a25ce94 | 1399 | if (cpu->insn_flags & ISA_MIPS32R2) { |
f1aa6320 | 1400 | mask |= 1 << CP0Ca_DC; |
5a25ce94 | 1401 | } |
f1aa6320 | 1402 | |
5a25ce94 | 1403 | cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask); |
f1aa6320 | 1404 | |
5a25ce94 EI |
1405 | if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) { |
1406 | if (cpu->CP0_Cause & (1 << CP0Ca_DC)) { | |
1407 | cpu_mips_stop_count(cpu); | |
1408 | } else { | |
1409 | cpu_mips_start_count(cpu); | |
1410 | } | |
f1aa6320 | 1411 | } |
5dc5d9f0 AJ |
1412 | |
1413 | /* Set/reset software interrupts */ | |
1414 | for (i = 0 ; i < 2 ; i++) { | |
5a25ce94 EI |
1415 | if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) { |
1416 | cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i))); | |
5dc5d9f0 AJ |
1417 | } |
1418 | } | |
f1aa6320 TS |
1419 | } |
1420 | ||
895c2d04 | 1421 | void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
1422 | { |
1423 | mtc0_cause(env, arg1); | |
1424 | } | |
1425 | ||
895c2d04 | 1426 | void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
1427 | { |
1428 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1429 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1430 | |
1431 | mtc0_cause(other, arg1); | |
1432 | } | |
1433 | ||
895c2d04 | 1434 | target_ulong helper_mftc0_epc(CPUMIPSState *env) |
5a25ce94 EI |
1435 | { |
1436 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1437 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1438 | |
1439 | return other->CP0_EPC; | |
1440 | } | |
1441 | ||
895c2d04 | 1442 | target_ulong helper_mftc0_ebase(CPUMIPSState *env) |
5a25ce94 EI |
1443 | { |
1444 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1445 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1446 | |
1447 | return other->CP0_EBase; | |
1448 | } | |
1449 | ||
895c2d04 | 1450 | void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1451 | { |
1452 | /* vectored interrupts not implemented */ | |
671b0f36 | 1453 | env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
f1aa6320 TS |
1454 | } |
1455 | ||
895c2d04 | 1456 | void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
1457 | { |
1458 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1459 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1460 | other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
1461 | } | |
1462 | ||
895c2d04 | 1463 | target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) |
5a25ce94 EI |
1464 | { |
1465 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1466 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1467 | |
1468 | switch (idx) { | |
1469 | case 0: return other->CP0_Config0; | |
1470 | case 1: return other->CP0_Config1; | |
1471 | case 2: return other->CP0_Config2; | |
1472 | case 3: return other->CP0_Config3; | |
1473 | /* 4 and 5 are reserved. */ | |
1474 | case 6: return other->CP0_Config6; | |
1475 | case 7: return other->CP0_Config7; | |
1476 | default: | |
1477 | break; | |
1478 | } | |
1479 | return 0; | |
1480 | } | |
1481 | ||
895c2d04 | 1482 | void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1483 | { |
d9bea114 | 1484 | env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); |
f1aa6320 TS |
1485 | } |
1486 | ||
895c2d04 | 1487 | void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1488 | { |
1489 | /* tertiary/secondary caches not implemented */ | |
1490 | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); | |
1491 | } | |
1492 | ||
895c2d04 | 1493 | void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) |
2a6e32dd AJ |
1494 | { |
1495 | target_long mask = env->CP0_LLAddr_rw_bitmask; | |
1496 | arg1 = arg1 << env->CP0_LLAddr_shift; | |
1497 | env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); | |
1498 | } | |
1499 | ||
895c2d04 | 1500 | void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1501 | { |
1502 | /* Watch exceptions for instructions, data loads, data stores | |
1503 | not implemented. */ | |
d9bea114 | 1504 | env->CP0_WatchLo[sel] = (arg1 & ~0x7); |
f1aa6320 TS |
1505 | } |
1506 | ||
895c2d04 | 1507 | void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 | 1508 | { |
d9bea114 AJ |
1509 | env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); |
1510 | env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); | |
f1aa6320 TS |
1511 | } |
1512 | ||
895c2d04 | 1513 | void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1514 | { |
1515 | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; | |
d9bea114 | 1516 | env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); |
f1aa6320 TS |
1517 | } |
1518 | ||
895c2d04 | 1519 | void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1520 | { |
d9bea114 | 1521 | env->CP0_Framemask = arg1; /* XXX */ |
f1aa6320 TS |
1522 | } |
1523 | ||
895c2d04 | 1524 | void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1525 | { |
d9bea114 AJ |
1526 | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); |
1527 | if (arg1 & (1 << CP0DB_DM)) | |
f1aa6320 TS |
1528 | env->hflags |= MIPS_HFLAG_DM; |
1529 | else | |
1530 | env->hflags &= ~MIPS_HFLAG_DM; | |
1531 | } | |
1532 | ||
895c2d04 | 1533 | void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1534 | { |
1535 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
d9bea114 | 1536 | uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
895c2d04 | 1537 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 TS |
1538 | |
1539 | /* XXX: Might be wrong, check with EJTAG spec. */ | |
b93bbdcd EI |
1540 | if (other_tc == other->current_tc) |
1541 | other->active_tc.CP0_Debug_tcstatus = val; | |
b5dc7732 | 1542 | else |
b93bbdcd EI |
1543 | other->tcs[other_tc].CP0_Debug_tcstatus = val; |
1544 | other->CP0_Debug = (other->CP0_Debug & | |
1545 | ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | | |
d9bea114 | 1546 | (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
f1aa6320 TS |
1547 | } |
1548 | ||
895c2d04 | 1549 | void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1550 | { |
d9bea114 | 1551 | env->CP0_Performance0 = arg1 & 0x000007ff; |
f1aa6320 TS |
1552 | } |
1553 | ||
895c2d04 | 1554 | void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1555 | { |
d9bea114 | 1556 | env->CP0_TagLo = arg1 & 0xFFFFFCF6; |
f1aa6320 TS |
1557 | } |
1558 | ||
895c2d04 | 1559 | void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1560 | { |
d9bea114 | 1561 | env->CP0_DataLo = arg1; /* XXX */ |
f1aa6320 TS |
1562 | } |
1563 | ||
895c2d04 | 1564 | void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1565 | { |
d9bea114 | 1566 | env->CP0_TagHi = arg1; /* XXX */ |
f1aa6320 TS |
1567 | } |
1568 | ||
895c2d04 | 1569 | void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1570 | { |
d9bea114 | 1571 | env->CP0_DataHi = arg1; /* XXX */ |
f1aa6320 TS |
1572 | } |
1573 | ||
f1aa6320 | 1574 | /* MIPS MT functions */ |
895c2d04 | 1575 | target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) |
f1aa6320 TS |
1576 | { |
1577 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1578 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1579 | |
b93bbdcd EI |
1580 | if (other_tc == other->current_tc) |
1581 | return other->active_tc.gpr[sel]; | |
b5dc7732 | 1582 | else |
b93bbdcd | 1583 | return other->tcs[other_tc].gpr[sel]; |
f1aa6320 TS |
1584 | } |
1585 | ||
895c2d04 | 1586 | target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) |
f1aa6320 TS |
1587 | { |
1588 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1589 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1590 | |
b93bbdcd EI |
1591 | if (other_tc == other->current_tc) |
1592 | return other->active_tc.LO[sel]; | |
b5dc7732 | 1593 | else |
b93bbdcd | 1594 | return other->tcs[other_tc].LO[sel]; |
f1aa6320 TS |
1595 | } |
1596 | ||
895c2d04 | 1597 | target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) |
f1aa6320 TS |
1598 | { |
1599 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1600 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1601 | |
b93bbdcd EI |
1602 | if (other_tc == other->current_tc) |
1603 | return other->active_tc.HI[sel]; | |
b5dc7732 | 1604 | else |
b93bbdcd | 1605 | return other->tcs[other_tc].HI[sel]; |
f1aa6320 TS |
1606 | } |
1607 | ||
895c2d04 | 1608 | target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) |
f1aa6320 TS |
1609 | { |
1610 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1611 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1612 | |
b93bbdcd EI |
1613 | if (other_tc == other->current_tc) |
1614 | return other->active_tc.ACX[sel]; | |
b5dc7732 | 1615 | else |
b93bbdcd | 1616 | return other->tcs[other_tc].ACX[sel]; |
f1aa6320 TS |
1617 | } |
1618 | ||
895c2d04 | 1619 | target_ulong helper_mftdsp(CPUMIPSState *env) |
f1aa6320 TS |
1620 | { |
1621 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1622 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1623 | |
b93bbdcd EI |
1624 | if (other_tc == other->current_tc) |
1625 | return other->active_tc.DSPControl; | |
b5dc7732 | 1626 | else |
b93bbdcd | 1627 | return other->tcs[other_tc].DSPControl; |
f1aa6320 | 1628 | } |
6af0bf9c | 1629 | |
895c2d04 | 1630 | void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1631 | { |
1632 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1633 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1634 | |
b93bbdcd EI |
1635 | if (other_tc == other->current_tc) |
1636 | other->active_tc.gpr[sel] = arg1; | |
b5dc7732 | 1637 | else |
b93bbdcd | 1638 | other->tcs[other_tc].gpr[sel] = arg1; |
f1aa6320 TS |
1639 | } |
1640 | ||
895c2d04 | 1641 | void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1642 | { |
1643 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1644 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1645 | |
b93bbdcd EI |
1646 | if (other_tc == other->current_tc) |
1647 | other->active_tc.LO[sel] = arg1; | |
b5dc7732 | 1648 | else |
b93bbdcd | 1649 | other->tcs[other_tc].LO[sel] = arg1; |
f1aa6320 TS |
1650 | } |
1651 | ||
895c2d04 | 1652 | void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1653 | { |
1654 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1655 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1656 | |
b93bbdcd EI |
1657 | if (other_tc == other->current_tc) |
1658 | other->active_tc.HI[sel] = arg1; | |
b5dc7732 | 1659 | else |
b93bbdcd | 1660 | other->tcs[other_tc].HI[sel] = arg1; |
f1aa6320 TS |
1661 | } |
1662 | ||
895c2d04 | 1663 | void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1664 | { |
1665 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1666 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1667 | |
b93bbdcd EI |
1668 | if (other_tc == other->current_tc) |
1669 | other->active_tc.ACX[sel] = arg1; | |
b5dc7732 | 1670 | else |
b93bbdcd | 1671 | other->tcs[other_tc].ACX[sel] = arg1; |
f1aa6320 TS |
1672 | } |
1673 | ||
895c2d04 | 1674 | void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1675 | { |
1676 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1677 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1678 | |
b93bbdcd EI |
1679 | if (other_tc == other->current_tc) |
1680 | other->active_tc.DSPControl = arg1; | |
b5dc7732 | 1681 | else |
b93bbdcd | 1682 | other->tcs[other_tc].DSPControl = arg1; |
f1aa6320 TS |
1683 | } |
1684 | ||
1685 | /* MIPS MT functions */ | |
9ed5726c | 1686 | target_ulong helper_dmt(void) |
f1aa6320 TS |
1687 | { |
1688 | // TODO | |
9ed5726c | 1689 | return 0; |
f1aa6320 TS |
1690 | } |
1691 | ||
9ed5726c | 1692 | target_ulong helper_emt(void) |
f1aa6320 TS |
1693 | { |
1694 | // TODO | |
9ed5726c | 1695 | return 0; |
f1aa6320 TS |
1696 | } |
1697 | ||
895c2d04 | 1698 | target_ulong helper_dvpe(CPUMIPSState *env) |
f1aa6320 | 1699 | { |
81bad50e | 1700 | CPUMIPSState *other_cpu_env = first_cpu; |
f249412c EI |
1701 | target_ulong prev = env->mvp->CP0_MVPControl; |
1702 | ||
1703 | do { | |
1704 | /* Turn off all VPEs except the one executing the dvpe. */ | |
81bad50e | 1705 | if (other_cpu_env != env) { |
6f4d6b09 AF |
1706 | MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env); |
1707 | ||
81bad50e | 1708 | other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); |
6f4d6b09 | 1709 | mips_vpe_sleep(other_cpu); |
f249412c | 1710 | } |
81bad50e AF |
1711 | other_cpu_env = other_cpu_env->next_cpu; |
1712 | } while (other_cpu_env); | |
f249412c | 1713 | return prev; |
f1aa6320 TS |
1714 | } |
1715 | ||
895c2d04 | 1716 | target_ulong helper_evpe(CPUMIPSState *env) |
f1aa6320 | 1717 | { |
81bad50e | 1718 | CPUMIPSState *other_cpu_env = first_cpu; |
f249412c EI |
1719 | target_ulong prev = env->mvp->CP0_MVPControl; |
1720 | ||
1721 | do { | |
b35d77d7 AF |
1722 | MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env); |
1723 | ||
81bad50e AF |
1724 | if (other_cpu_env != env |
1725 | /* If the VPE is WFI, don't disturb its sleep. */ | |
b35d77d7 | 1726 | && !mips_vpe_is_wfi(other_cpu)) { |
f249412c | 1727 | /* Enable the VPE. */ |
81bad50e AF |
1728 | other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); |
1729 | mips_vpe_wake(other_cpu_env); /* And wake it up. */ | |
f249412c | 1730 | } |
81bad50e AF |
1731 | other_cpu_env = other_cpu_env->next_cpu; |
1732 | } while (other_cpu_env); | |
f249412c | 1733 | return prev; |
f1aa6320 | 1734 | } |
f9480ffc | 1735 | #endif /* !CONFIG_USER_ONLY */ |
f1aa6320 | 1736 | |
d9bea114 | 1737 | void helper_fork(target_ulong arg1, target_ulong arg2) |
f1aa6320 | 1738 | { |
d9bea114 AJ |
1739 | // arg1 = rt, arg2 = rs |
1740 | arg1 = 0; | |
f1aa6320 TS |
1741 | // TODO: store to TC register |
1742 | } | |
1743 | ||
895c2d04 | 1744 | target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) |
f1aa6320 | 1745 | { |
1c7242da BS |
1746 | target_long arg1 = arg; |
1747 | ||
d9bea114 | 1748 | if (arg1 < 0) { |
f1aa6320 | 1749 | /* No scheduling policy implemented. */ |
d9bea114 | 1750 | if (arg1 != -2) { |
f1aa6320 | 1751 | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
b5dc7732 | 1752 | env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { |
f1aa6320 TS |
1753 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
1754 | env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; | |
895c2d04 | 1755 | helper_raise_exception(env, EXCP_THREAD); |
f1aa6320 TS |
1756 | } |
1757 | } | |
d9bea114 | 1758 | } else if (arg1 == 0) { |
6958549d | 1759 | if (0 /* TODO: TC underflow */) { |
f1aa6320 | 1760 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
895c2d04 | 1761 | helper_raise_exception(env, EXCP_THREAD); |
f1aa6320 TS |
1762 | } else { |
1763 | // TODO: Deallocate TC | |
1764 | } | |
d9bea114 | 1765 | } else if (arg1 > 0) { |
f1aa6320 TS |
1766 | /* Yield qualifier inputs not implemented. */ |
1767 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); | |
1768 | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; | |
895c2d04 | 1769 | helper_raise_exception(env, EXCP_THREAD); |
f1aa6320 | 1770 | } |
be24bb4f | 1771 | return env->CP0_YQMask; |
f1aa6320 TS |
1772 | } |
1773 | ||
f1aa6320 | 1774 | #ifndef CONFIG_USER_ONLY |
6af0bf9c | 1775 | /* TLB management */ |
7db13fae | 1776 | static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global) |
814b9a47 TS |
1777 | { |
1778 | /* Flush qemu's TLB and discard all shadowed entries. */ | |
1779 | tlb_flush (env, flush_global); | |
ead9360e | 1780 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
814b9a47 TS |
1781 | } |
1782 | ||
7db13fae | 1783 | static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) |
814b9a47 TS |
1784 | { |
1785 | /* Discard entries from env->tlb[first] onwards. */ | |
ead9360e TS |
1786 | while (env->tlb->tlb_in_use > first) { |
1787 | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); | |
814b9a47 TS |
1788 | } |
1789 | } | |
1790 | ||
895c2d04 | 1791 | static void r4k_fill_tlb(CPUMIPSState *env, int idx) |
6af0bf9c | 1792 | { |
c227f099 | 1793 | r4k_tlb_t *tlb; |
6af0bf9c FB |
1794 | |
1795 | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ | |
ead9360e | 1796 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 1797 | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
d26bc211 | 1798 | #if defined(TARGET_MIPS64) |
e034e2c3 | 1799 | tlb->VPN &= env->SEGMask; |
100ce988 | 1800 | #endif |
98c1b82b | 1801 | tlb->ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 1802 | tlb->PageMask = env->CP0_PageMask; |
6af0bf9c | 1803 | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
98c1b82b PB |
1804 | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
1805 | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; | |
1806 | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; | |
6af0bf9c | 1807 | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
98c1b82b PB |
1808 | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
1809 | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; | |
1810 | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; | |
6af0bf9c FB |
1811 | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
1812 | } | |
1813 | ||
895c2d04 | 1814 | void r4k_helper_tlbwi(CPUMIPSState *env) |
6af0bf9c | 1815 | { |
286d52eb | 1816 | r4k_tlb_t *tlb; |
bbc0d79c | 1817 | int idx; |
286d52eb AJ |
1818 | target_ulong VPN; |
1819 | uint8_t ASID; | |
1820 | bool G, V0, D0, V1, D1; | |
bbc0d79c AJ |
1821 | |
1822 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; | |
286d52eb AJ |
1823 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
1824 | VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); | |
1825 | #if defined(TARGET_MIPS64) | |
1826 | VPN &= env->SEGMask; | |
1827 | #endif | |
1828 | ASID = env->CP0_EntryHi & 0xff; | |
1829 | G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; | |
1830 | V0 = (env->CP0_EntryLo0 & 2) != 0; | |
1831 | D0 = (env->CP0_EntryLo0 & 4) != 0; | |
1832 | V1 = (env->CP0_EntryLo1 & 2) != 0; | |
1833 | D1 = (env->CP0_EntryLo1 & 4) != 0; | |
1834 | ||
1835 | /* Discard cached TLB entries, unless tlbwi is just upgrading access | |
1836 | permissions on the current entry. */ | |
1837 | if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G || | |
1838 | (tlb->V0 && !V0) || (tlb->D0 && !D0) || | |
1839 | (tlb->V1 && !V1) || (tlb->D1 && !D1)) { | |
1840 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); | |
1841 | } | |
814b9a47 | 1842 | |
bbc0d79c | 1843 | r4k_invalidate_tlb(env, idx, 0); |
895c2d04 | 1844 | r4k_fill_tlb(env, idx); |
6af0bf9c FB |
1845 | } |
1846 | ||
895c2d04 | 1847 | void r4k_helper_tlbwr(CPUMIPSState *env) |
6af0bf9c FB |
1848 | { |
1849 | int r = cpu_mips_get_random(env); | |
1850 | ||
29929e34 | 1851 | r4k_invalidate_tlb(env, r, 1); |
895c2d04 | 1852 | r4k_fill_tlb(env, r); |
6af0bf9c FB |
1853 | } |
1854 | ||
895c2d04 | 1855 | void r4k_helper_tlbp(CPUMIPSState *env) |
6af0bf9c | 1856 | { |
c227f099 | 1857 | r4k_tlb_t *tlb; |
f2e9ebef | 1858 | target_ulong mask; |
6af0bf9c | 1859 | target_ulong tag; |
f2e9ebef | 1860 | target_ulong VPN; |
6af0bf9c FB |
1861 | uint8_t ASID; |
1862 | int i; | |
1863 | ||
3d9fb9fe | 1864 | ASID = env->CP0_EntryHi & 0xFF; |
ead9360e TS |
1865 | for (i = 0; i < env->tlb->nb_tlb; i++) { |
1866 | tlb = &env->tlb->mmu.r4k.tlb[i]; | |
f2e9ebef TS |
1867 | /* 1k pages are not supported. */ |
1868 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
1869 | tag = env->CP0_EntryHi & ~mask; | |
1870 | VPN = tlb->VPN & ~mask; | |
bc3e45e1 AJ |
1871 | #if defined(TARGET_MIPS64) |
1872 | tag &= env->SEGMask; | |
1873 | #endif | |
6af0bf9c | 1874 | /* Check ASID, virtual page number & size */ |
f2e9ebef | 1875 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
6af0bf9c | 1876 | /* TLB match */ |
9c2149c8 | 1877 | env->CP0_Index = i; |
6af0bf9c FB |
1878 | break; |
1879 | } | |
1880 | } | |
ead9360e | 1881 | if (i == env->tlb->nb_tlb) { |
814b9a47 | 1882 | /* No match. Discard any shadow entries, if any of them match. */ |
ead9360e | 1883 | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { |
6958549d AJ |
1884 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
1885 | /* 1k pages are not supported. */ | |
1886 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
1887 | tag = env->CP0_EntryHi & ~mask; | |
1888 | VPN = tlb->VPN & ~mask; | |
bc3e45e1 AJ |
1889 | #if defined(TARGET_MIPS64) |
1890 | tag &= env->SEGMask; | |
1891 | #endif | |
6958549d AJ |
1892 | /* Check ASID, virtual page number & size */ |
1893 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { | |
29929e34 | 1894 | r4k_mips_tlb_flush_extra (env, i); |
6958549d AJ |
1895 | break; |
1896 | } | |
1897 | } | |
814b9a47 | 1898 | |
9c2149c8 | 1899 | env->CP0_Index |= 0x80000000; |
6af0bf9c FB |
1900 | } |
1901 | } | |
1902 | ||
895c2d04 | 1903 | void r4k_helper_tlbr(CPUMIPSState *env) |
6af0bf9c | 1904 | { |
c227f099 | 1905 | r4k_tlb_t *tlb; |
09c56b84 | 1906 | uint8_t ASID; |
bbc0d79c | 1907 | int idx; |
6af0bf9c | 1908 | |
09c56b84 | 1909 | ASID = env->CP0_EntryHi & 0xFF; |
bbc0d79c AJ |
1910 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
1911 | tlb = &env->tlb->mmu.r4k.tlb[idx]; | |
4ad40f36 FB |
1912 | |
1913 | /* If this will change the current ASID, flush qemu's TLB. */ | |
814b9a47 TS |
1914 | if (ASID != tlb->ASID) |
1915 | cpu_mips_tlb_flush (env, 1); | |
1916 | ||
ead9360e | 1917 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
4ad40f36 | 1918 | |
6af0bf9c | 1919 | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
3b1c8be4 | 1920 | env->CP0_PageMask = tlb->PageMask; |
7495fd0f TS |
1921 | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
1922 | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); | |
1923 | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | | |
1924 | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); | |
6af0bf9c | 1925 | } |
6af0bf9c | 1926 | |
895c2d04 | 1927 | void helper_tlbwi(CPUMIPSState *env) |
a7812ae4 | 1928 | { |
895c2d04 | 1929 | env->tlb->helper_tlbwi(env); |
a7812ae4 PB |
1930 | } |
1931 | ||
895c2d04 | 1932 | void helper_tlbwr(CPUMIPSState *env) |
a7812ae4 | 1933 | { |
895c2d04 | 1934 | env->tlb->helper_tlbwr(env); |
a7812ae4 PB |
1935 | } |
1936 | ||
895c2d04 | 1937 | void helper_tlbp(CPUMIPSState *env) |
a7812ae4 | 1938 | { |
895c2d04 | 1939 | env->tlb->helper_tlbp(env); |
a7812ae4 PB |
1940 | } |
1941 | ||
895c2d04 | 1942 | void helper_tlbr(CPUMIPSState *env) |
a7812ae4 | 1943 | { |
895c2d04 | 1944 | env->tlb->helper_tlbr(env); |
a7812ae4 PB |
1945 | } |
1946 | ||
2b0233ab | 1947 | /* Specials */ |
895c2d04 | 1948 | target_ulong helper_di(CPUMIPSState *env) |
2b0233ab | 1949 | { |
2796188e TS |
1950 | target_ulong t0 = env->CP0_Status; |
1951 | ||
be24bb4f | 1952 | env->CP0_Status = t0 & ~(1 << CP0St_IE); |
be24bb4f | 1953 | return t0; |
2b0233ab TS |
1954 | } |
1955 | ||
895c2d04 | 1956 | target_ulong helper_ei(CPUMIPSState *env) |
2b0233ab | 1957 | { |
2796188e TS |
1958 | target_ulong t0 = env->CP0_Status; |
1959 | ||
be24bb4f | 1960 | env->CP0_Status = t0 | (1 << CP0St_IE); |
be24bb4f | 1961 | return t0; |
2b0233ab TS |
1962 | } |
1963 | ||
895c2d04 | 1964 | static void debug_pre_eret(CPUMIPSState *env) |
6af0bf9c | 1965 | { |
8fec2b8c | 1966 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
93fcfe39 AL |
1967 | qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1968 | env->active_tc.PC, env->CP0_EPC); | |
1969 | if (env->CP0_Status & (1 << CP0St_ERL)) | |
1970 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); | |
1971 | if (env->hflags & MIPS_HFLAG_DM) | |
1972 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); | |
1973 | qemu_log("\n"); | |
1974 | } | |
f41c52f1 TS |
1975 | } |
1976 | ||
895c2d04 | 1977 | static void debug_post_eret(CPUMIPSState *env) |
f41c52f1 | 1978 | { |
8fec2b8c | 1979 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
93fcfe39 AL |
1980 | qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1981 | env->active_tc.PC, env->CP0_EPC); | |
1982 | if (env->CP0_Status & (1 << CP0St_ERL)) | |
1983 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); | |
1984 | if (env->hflags & MIPS_HFLAG_DM) | |
1985 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); | |
1986 | switch (env->hflags & MIPS_HFLAG_KSU) { | |
1987 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; | |
1988 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; | |
1989 | case MIPS_HFLAG_KM: qemu_log("\n"); break; | |
1990 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; | |
1991 | } | |
623a930e | 1992 | } |
6af0bf9c FB |
1993 | } |
1994 | ||
895c2d04 | 1995 | static void set_pc(CPUMIPSState *env, target_ulong error_pc) |
32188a03 NF |
1996 | { |
1997 | env->active_tc.PC = error_pc & ~(target_ulong)1; | |
1998 | if (error_pc & 1) { | |
1999 | env->hflags |= MIPS_HFLAG_M16; | |
2000 | } else { | |
2001 | env->hflags &= ~(MIPS_HFLAG_M16); | |
2002 | } | |
2003 | } | |
2004 | ||
895c2d04 | 2005 | void helper_eret(CPUMIPSState *env) |
2b0233ab | 2006 | { |
895c2d04 | 2007 | debug_pre_eret(env); |
2b0233ab | 2008 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
895c2d04 | 2009 | set_pc(env, env->CP0_ErrorEPC); |
2b0233ab TS |
2010 | env->CP0_Status &= ~(1 << CP0St_ERL); |
2011 | } else { | |
895c2d04 | 2012 | set_pc(env, env->CP0_EPC); |
2b0233ab TS |
2013 | env->CP0_Status &= ~(1 << CP0St_EXL); |
2014 | } | |
2015 | compute_hflags(env); | |
895c2d04 | 2016 | debug_post_eret(env); |
5499b6ff | 2017 | env->lladdr = 1; |
2b0233ab TS |
2018 | } |
2019 | ||
895c2d04 | 2020 | void helper_deret(CPUMIPSState *env) |
2b0233ab | 2021 | { |
895c2d04 BS |
2022 | debug_pre_eret(env); |
2023 | set_pc(env, env->CP0_DEPC); | |
32188a03 | 2024 | |
2b0233ab TS |
2025 | env->hflags &= MIPS_HFLAG_DM; |
2026 | compute_hflags(env); | |
895c2d04 | 2027 | debug_post_eret(env); |
5499b6ff | 2028 | env->lladdr = 1; |
2b0233ab | 2029 | } |
0eaef5aa | 2030 | #endif /* !CONFIG_USER_ONLY */ |
2b0233ab | 2031 | |
895c2d04 | 2032 | target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) |
2b0233ab TS |
2033 | { |
2034 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
2035 | (env->CP0_HWREna & (1 << 0))) | |
2796188e | 2036 | return env->CP0_EBase & 0x3ff; |
2b0233ab | 2037 | else |
895c2d04 | 2038 | helper_raise_exception(env, EXCP_RI); |
be24bb4f | 2039 | |
2796188e | 2040 | return 0; |
2b0233ab TS |
2041 | } |
2042 | ||
895c2d04 | 2043 | target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) |
2b0233ab TS |
2044 | { |
2045 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
2046 | (env->CP0_HWREna & (1 << 1))) | |
2796188e | 2047 | return env->SYNCI_Step; |
2b0233ab | 2048 | else |
895c2d04 | 2049 | helper_raise_exception(env, EXCP_RI); |
be24bb4f | 2050 | |
2796188e | 2051 | return 0; |
2b0233ab TS |
2052 | } |
2053 | ||
895c2d04 | 2054 | target_ulong helper_rdhwr_cc(CPUMIPSState *env) |
2b0233ab TS |
2055 | { |
2056 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
2057 | (env->CP0_HWREna & (1 << 2))) | |
2796188e | 2058 | return env->CP0_Count; |
2b0233ab | 2059 | else |
895c2d04 | 2060 | helper_raise_exception(env, EXCP_RI); |
be24bb4f | 2061 | |
2796188e | 2062 | return 0; |
2b0233ab TS |
2063 | } |
2064 | ||
895c2d04 | 2065 | target_ulong helper_rdhwr_ccres(CPUMIPSState *env) |
2b0233ab TS |
2066 | { |
2067 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
2068 | (env->CP0_HWREna & (1 << 3))) | |
2796188e | 2069 | return env->CCRes; |
2b0233ab | 2070 | else |
895c2d04 | 2071 | helper_raise_exception(env, EXCP_RI); |
be24bb4f | 2072 | |
2796188e | 2073 | return 0; |
2b0233ab TS |
2074 | } |
2075 | ||
895c2d04 | 2076 | void helper_pmon(CPUMIPSState *env, int function) |
6af0bf9c FB |
2077 | { |
2078 | function /= 2; | |
2079 | switch (function) { | |
2080 | case 2: /* TODO: char inbyte(int waitflag); */ | |
b5dc7732 TS |
2081 | if (env->active_tc.gpr[4] == 0) |
2082 | env->active_tc.gpr[2] = -1; | |
6af0bf9c FB |
2083 | /* Fall through */ |
2084 | case 11: /* TODO: char inbyte (void); */ | |
b5dc7732 | 2085 | env->active_tc.gpr[2] = -1; |
6af0bf9c FB |
2086 | break; |
2087 | case 3: | |
2088 | case 12: | |
b5dc7732 | 2089 | printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); |
6af0bf9c FB |
2090 | break; |
2091 | case 17: | |
2092 | break; | |
2093 | case 158: | |
2094 | { | |
b69e48a8 | 2095 | unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4]; |
6af0bf9c FB |
2096 | printf("%s", fmt); |
2097 | } | |
2098 | break; | |
2099 | } | |
2100 | } | |
e37e863f | 2101 | |
895c2d04 | 2102 | void helper_wait(CPUMIPSState *env) |
08ba7963 TS |
2103 | { |
2104 | env->halted = 1; | |
f249412c | 2105 | cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE); |
895c2d04 | 2106 | helper_raise_exception(env, EXCP_HLT); |
08ba7963 TS |
2107 | } |
2108 | ||
5fafdf24 | 2109 | #if !defined(CONFIG_USER_ONLY) |
e37e863f | 2110 | |
895c2d04 BS |
2111 | static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env, |
2112 | target_ulong addr, int is_write, | |
20503968 | 2113 | int is_user, uintptr_t retaddr); |
4ad40f36 | 2114 | |
e37e863f | 2115 | #define MMUSUFFIX _mmu |
4ad40f36 | 2116 | #define ALIGNED_ONLY |
e37e863f FB |
2117 | |
2118 | #define SHIFT 0 | |
022c62cb | 2119 | #include "exec/softmmu_template.h" |
e37e863f FB |
2120 | |
2121 | #define SHIFT 1 | |
022c62cb | 2122 | #include "exec/softmmu_template.h" |
e37e863f FB |
2123 | |
2124 | #define SHIFT 2 | |
022c62cb | 2125 | #include "exec/softmmu_template.h" |
e37e863f FB |
2126 | |
2127 | #define SHIFT 3 | |
022c62cb | 2128 | #include "exec/softmmu_template.h" |
e37e863f | 2129 | |
895c2d04 BS |
2130 | static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, |
2131 | int is_write, int is_user, uintptr_t retaddr) | |
4ad40f36 FB |
2132 | { |
2133 | env->CP0_BadVAddr = addr; | |
5f7319cd | 2134 | do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr); |
4ad40f36 FB |
2135 | } |
2136 | ||
895c2d04 | 2137 | void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, |
20503968 | 2138 | uintptr_t retaddr) |
e37e863f | 2139 | { |
e37e863f FB |
2140 | int ret; |
2141 | ||
97b348e7 | 2142 | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx); |
e37e863f | 2143 | if (ret) { |
5f7319cd AJ |
2144 | do_raise_exception_err(env, env->exception_index, |
2145 | env->error_code, retaddr); | |
e37e863f | 2146 | } |
e37e863f FB |
2147 | } |
2148 | ||
a8170e5e | 2149 | void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr, |
b14ef7c9 | 2150 | int is_write, int is_exec, int unused, int size) |
647de6ca TS |
2151 | { |
2152 | if (is_exec) | |
895c2d04 | 2153 | helper_raise_exception(env, EXCP_IBE); |
647de6ca | 2154 | else |
895c2d04 | 2155 | helper_raise_exception(env, EXCP_DBE); |
647de6ca | 2156 | } |
f1aa6320 | 2157 | #endif /* !CONFIG_USER_ONLY */ |
fd4a04eb TS |
2158 | |
2159 | /* Complex FPU operations which may need stack space. */ | |
2160 | ||
f090c9d4 PB |
2161 | #define FLOAT_TWO32 make_float32(1 << 30) |
2162 | #define FLOAT_TWO64 make_float64(1ULL << 62) | |
05993cd0 AJ |
2163 | #define FP_TO_INT32_OVERFLOW 0x7fffffff |
2164 | #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL | |
8dfdb87c | 2165 | |
fd4a04eb | 2166 | /* convert MIPS rounding mode in FCR31 to IEEE library */ |
6f4fc367 | 2167 | static unsigned int ieee_rm[] = { |
fd4a04eb TS |
2168 | float_round_nearest_even, |
2169 | float_round_to_zero, | |
2170 | float_round_up, | |
2171 | float_round_down | |
2172 | }; | |
2173 | ||
2174 | #define RESTORE_ROUNDING_MODE \ | |
f01be154 | 2175 | set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status) |
fd4a04eb | 2176 | |
41e0c701 AJ |
2177 | #define RESTORE_FLUSH_MODE \ |
2178 | set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); | |
2179 | ||
895c2d04 | 2180 | target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) |
fd4a04eb | 2181 | { |
d9bea114 | 2182 | target_ulong arg1; |
6c5c1e20 | 2183 | |
ead9360e TS |
2184 | switch (reg) { |
2185 | case 0: | |
d9bea114 | 2186 | arg1 = (int32_t)env->active_fpu.fcr0; |
ead9360e TS |
2187 | break; |
2188 | case 25: | |
d9bea114 | 2189 | arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); |
ead9360e TS |
2190 | break; |
2191 | case 26: | |
d9bea114 | 2192 | arg1 = env->active_fpu.fcr31 & 0x0003f07c; |
ead9360e TS |
2193 | break; |
2194 | case 28: | |
d9bea114 | 2195 | arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); |
ead9360e TS |
2196 | break; |
2197 | default: | |
d9bea114 | 2198 | arg1 = (int32_t)env->active_fpu.fcr31; |
ead9360e TS |
2199 | break; |
2200 | } | |
be24bb4f | 2201 | |
d9bea114 | 2202 | return arg1; |
ead9360e TS |
2203 | } |
2204 | ||
895c2d04 | 2205 | void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg) |
ead9360e TS |
2206 | { |
2207 | switch(reg) { | |
fd4a04eb | 2208 | case 25: |
d9bea114 | 2209 | if (arg1 & 0xffffff00) |
fd4a04eb | 2210 | return; |
d9bea114 AJ |
2211 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | |
2212 | ((arg1 & 0x1) << 23); | |
fd4a04eb TS |
2213 | break; |
2214 | case 26: | |
d9bea114 | 2215 | if (arg1 & 0x007c0000) |
fd4a04eb | 2216 | return; |
d9bea114 | 2217 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); |
fd4a04eb TS |
2218 | break; |
2219 | case 28: | |
d9bea114 | 2220 | if (arg1 & 0x007c0000) |
fd4a04eb | 2221 | return; |
d9bea114 AJ |
2222 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | |
2223 | ((arg1 & 0x4) << 22); | |
fd4a04eb TS |
2224 | break; |
2225 | case 31: | |
d9bea114 | 2226 | if (arg1 & 0x007c0000) |
fd4a04eb | 2227 | return; |
d9bea114 | 2228 | env->active_fpu.fcr31 = arg1; |
fd4a04eb TS |
2229 | break; |
2230 | default: | |
2231 | return; | |
2232 | } | |
2233 | /* set rounding mode */ | |
2234 | RESTORE_ROUNDING_MODE; | |
41e0c701 AJ |
2235 | /* set flush-to-zero mode */ |
2236 | RESTORE_FLUSH_MODE; | |
f01be154 TS |
2237 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2238 | if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) | |
5f7319cd | 2239 | do_raise_exception(env, EXCP_FPE, GETPC()); |
fd4a04eb TS |
2240 | } |
2241 | ||
353ebb7a | 2242 | static inline int ieee_ex_to_mips(int xcpt) |
fd4a04eb | 2243 | { |
353ebb7a AJ |
2244 | int ret = 0; |
2245 | if (xcpt) { | |
2246 | if (xcpt & float_flag_invalid) { | |
2247 | ret |= FP_INVALID; | |
2248 | } | |
2249 | if (xcpt & float_flag_overflow) { | |
2250 | ret |= FP_OVERFLOW; | |
2251 | } | |
2252 | if (xcpt & float_flag_underflow) { | |
2253 | ret |= FP_UNDERFLOW; | |
2254 | } | |
2255 | if (xcpt & float_flag_divbyzero) { | |
2256 | ret |= FP_DIV0; | |
2257 | } | |
2258 | if (xcpt & float_flag_inexact) { | |
2259 | ret |= FP_INEXACT; | |
2260 | } | |
2261 | } | |
2262 | return ret; | |
fd4a04eb TS |
2263 | } |
2264 | ||
5f7319cd | 2265 | static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) |
fd4a04eb | 2266 | { |
f01be154 | 2267 | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); |
fd4a04eb | 2268 | |
f01be154 | 2269 | SET_FP_CAUSE(env->active_fpu.fcr31, tmp); |
4a587b2c AJ |
2270 | |
2271 | if (tmp) { | |
2272 | set_float_exception_flags(0, &env->active_fpu.fp_status); | |
2273 | ||
2274 | if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) { | |
5f7319cd | 2275 | do_raise_exception(env, EXCP_FPE, pc); |
4a587b2c AJ |
2276 | } else { |
2277 | UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); | |
2278 | } | |
2279 | } | |
fd4a04eb TS |
2280 | } |
2281 | ||
a16336e4 TS |
2282 | /* Float support. |
2283 | Single precition routines have a "s" suffix, double precision a | |
2284 | "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", | |
2285 | paired single lower "pl", paired single upper "pu". */ | |
2286 | ||
a16336e4 | 2287 | /* unary operations, modifying fp status */ |
895c2d04 | 2288 | uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) |
b6d96bed | 2289 | { |
5dbe90bb | 2290 | fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
5f7319cd | 2291 | update_fcr31(env, GETPC()); |
5dbe90bb | 2292 | return fdt0; |
b6d96bed TS |
2293 | } |
2294 | ||
895c2d04 | 2295 | uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) |
b6d96bed | 2296 | { |
5dbe90bb | 2297 | fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
5f7319cd | 2298 | update_fcr31(env, GETPC()); |
5dbe90bb | 2299 | return fst0; |
b6d96bed | 2300 | } |
a16336e4 | 2301 | |
895c2d04 | 2302 | uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2303 | { |
b6d96bed TS |
2304 | uint64_t fdt2; |
2305 | ||
f01be154 | 2306 | fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); |
5f7319cd | 2307 | update_fcr31(env, GETPC()); |
b6d96bed | 2308 | return fdt2; |
fd4a04eb | 2309 | } |
b6d96bed | 2310 | |
895c2d04 | 2311 | uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) |
fd4a04eb | 2312 | { |
b6d96bed TS |
2313 | uint64_t fdt2; |
2314 | ||
f01be154 | 2315 | fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); |
5f7319cd | 2316 | update_fcr31(env, GETPC()); |
b6d96bed | 2317 | return fdt2; |
fd4a04eb | 2318 | } |
b6d96bed | 2319 | |
895c2d04 | 2320 | uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) |
fd4a04eb | 2321 | { |
b6d96bed TS |
2322 | uint64_t fdt2; |
2323 | ||
f01be154 | 2324 | fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); |
5f7319cd | 2325 | update_fcr31(env, GETPC()); |
b6d96bed | 2326 | return fdt2; |
fd4a04eb | 2327 | } |
b6d96bed | 2328 | |
895c2d04 | 2329 | uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2330 | { |
b6d96bed TS |
2331 | uint64_t dt2; |
2332 | ||
f01be154 | 2333 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2334 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2335 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2336 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2337 | } |
5f7319cd | 2338 | update_fcr31(env, GETPC()); |
b6d96bed | 2339 | return dt2; |
fd4a04eb | 2340 | } |
b6d96bed | 2341 | |
895c2d04 | 2342 | uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2343 | { |
b6d96bed TS |
2344 | uint64_t dt2; |
2345 | ||
f01be154 | 2346 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2347 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2348 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2349 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2350 | } |
5f7319cd | 2351 | update_fcr31(env, GETPC()); |
b6d96bed | 2352 | return dt2; |
fd4a04eb TS |
2353 | } |
2354 | ||
895c2d04 | 2355 | uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) |
fd4a04eb | 2356 | { |
b6d96bed TS |
2357 | uint32_t fst2; |
2358 | uint32_t fsth2; | |
2359 | ||
f01be154 TS |
2360 | fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
2361 | fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); | |
5f7319cd | 2362 | update_fcr31(env, GETPC()); |
b6d96bed | 2363 | return ((uint64_t)fsth2 << 32) | fst2; |
fd4a04eb | 2364 | } |
b6d96bed | 2365 | |
895c2d04 | 2366 | uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2367 | { |
b6d96bed TS |
2368 | uint32_t wt2; |
2369 | uint32_t wth2; | |
5dbe90bb | 2370 | int excp, excph; |
b6d96bed | 2371 | |
f01be154 | 2372 | wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
5dbe90bb AJ |
2373 | excp = get_float_exception_flags(&env->active_fpu.fp_status); |
2374 | if (excp & (float_flag_overflow | float_flag_invalid)) { | |
05993cd0 | 2375 | wt2 = FP_TO_INT32_OVERFLOW; |
5dbe90bb AJ |
2376 | } |
2377 | ||
2378 | set_float_exception_flags(0, &env->active_fpu.fp_status); | |
2379 | wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); | |
2380 | excph = get_float_exception_flags(&env->active_fpu.fp_status); | |
2381 | if (excph & (float_flag_overflow | float_flag_invalid)) { | |
05993cd0 | 2382 | wth2 = FP_TO_INT32_OVERFLOW; |
b6d96bed | 2383 | } |
5dbe90bb AJ |
2384 | |
2385 | set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); | |
5f7319cd | 2386 | update_fcr31(env, GETPC()); |
5dbe90bb | 2387 | |
b6d96bed | 2388 | return ((uint64_t)wth2 << 32) | wt2; |
fd4a04eb | 2389 | } |
b6d96bed | 2390 | |
895c2d04 | 2391 | uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2392 | { |
b6d96bed TS |
2393 | uint32_t fst2; |
2394 | ||
f01be154 | 2395 | fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); |
5f7319cd | 2396 | update_fcr31(env, GETPC()); |
b6d96bed | 2397 | return fst2; |
fd4a04eb | 2398 | } |
b6d96bed | 2399 | |
895c2d04 | 2400 | uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) |
fd4a04eb | 2401 | { |
b6d96bed TS |
2402 | uint32_t fst2; |
2403 | ||
f01be154 | 2404 | fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); |
5f7319cd | 2405 | update_fcr31(env, GETPC()); |
b6d96bed | 2406 | return fst2; |
fd4a04eb | 2407 | } |
b6d96bed | 2408 | |
895c2d04 | 2409 | uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) |
fd4a04eb | 2410 | { |
b6d96bed TS |
2411 | uint32_t fst2; |
2412 | ||
f01be154 | 2413 | fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); |
5f7319cd | 2414 | update_fcr31(env, GETPC()); |
b6d96bed | 2415 | return fst2; |
fd4a04eb | 2416 | } |
b6d96bed | 2417 | |
895c2d04 | 2418 | uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) |
fd4a04eb | 2419 | { |
b6d96bed TS |
2420 | uint32_t wt2; |
2421 | ||
b6d96bed | 2422 | wt2 = wt0; |
5f7319cd | 2423 | update_fcr31(env, GETPC()); |
b6d96bed | 2424 | return wt2; |
fd4a04eb | 2425 | } |
b6d96bed | 2426 | |
895c2d04 | 2427 | uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) |
fd4a04eb | 2428 | { |
b6d96bed TS |
2429 | uint32_t wt2; |
2430 | ||
b6d96bed | 2431 | wt2 = wth0; |
5f7319cd | 2432 | update_fcr31(env, GETPC()); |
b6d96bed | 2433 | return wt2; |
fd4a04eb | 2434 | } |
b6d96bed | 2435 | |
895c2d04 | 2436 | uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2437 | { |
b6d96bed TS |
2438 | uint32_t wt2; |
2439 | ||
f01be154 | 2440 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
5f7319cd | 2441 | update_fcr31(env, GETPC()); |
4cc2e5f9 AJ |
2442 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2443 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2444 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2445 | } |
b6d96bed | 2446 | return wt2; |
fd4a04eb | 2447 | } |
b6d96bed | 2448 | |
895c2d04 | 2449 | uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2450 | { |
b6d96bed TS |
2451 | uint32_t wt2; |
2452 | ||
f01be154 | 2453 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2454 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2455 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2456 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2457 | } |
5f7319cd | 2458 | update_fcr31(env, GETPC()); |
b6d96bed | 2459 | return wt2; |
fd4a04eb TS |
2460 | } |
2461 | ||
895c2d04 | 2462 | uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2463 | { |
b6d96bed TS |
2464 | uint64_t dt2; |
2465 | ||
f01be154 TS |
2466 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2467 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2468 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2469 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2470 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2471 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2472 | } |
5f7319cd | 2473 | update_fcr31(env, GETPC()); |
b6d96bed | 2474 | return dt2; |
fd4a04eb | 2475 | } |
b6d96bed | 2476 | |
895c2d04 | 2477 | uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2478 | { |
b6d96bed TS |
2479 | uint64_t dt2; |
2480 | ||
f01be154 TS |
2481 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2482 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2483 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2484 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2485 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2486 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2487 | } |
5f7319cd | 2488 | update_fcr31(env, GETPC()); |
b6d96bed | 2489 | return dt2; |
fd4a04eb | 2490 | } |
b6d96bed | 2491 | |
895c2d04 | 2492 | uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2493 | { |
b6d96bed TS |
2494 | uint32_t wt2; |
2495 | ||
f01be154 TS |
2496 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2497 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2498 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2499 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2500 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2501 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2502 | } |
5f7319cd | 2503 | update_fcr31(env, GETPC()); |
b6d96bed | 2504 | return wt2; |
fd4a04eb | 2505 | } |
b6d96bed | 2506 | |
895c2d04 | 2507 | uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2508 | { |
b6d96bed TS |
2509 | uint32_t wt2; |
2510 | ||
f01be154 TS |
2511 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2512 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2513 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2514 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2515 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2516 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2517 | } |
5f7319cd | 2518 | update_fcr31(env, GETPC()); |
b6d96bed | 2519 | return wt2; |
fd4a04eb TS |
2520 | } |
2521 | ||
895c2d04 | 2522 | uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2523 | { |
b6d96bed TS |
2524 | uint64_t dt2; |
2525 | ||
f01be154 | 2526 | dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2527 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2528 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2529 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2530 | } |
5f7319cd | 2531 | update_fcr31(env, GETPC()); |
b6d96bed | 2532 | return dt2; |
fd4a04eb | 2533 | } |
b6d96bed | 2534 | |
895c2d04 | 2535 | uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2536 | { |
b6d96bed TS |
2537 | uint64_t dt2; |
2538 | ||
f01be154 | 2539 | dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2540 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2541 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2542 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2543 | } |
5f7319cd | 2544 | update_fcr31(env, GETPC()); |
b6d96bed | 2545 | return dt2; |
fd4a04eb | 2546 | } |
b6d96bed | 2547 | |
895c2d04 | 2548 | uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2549 | { |
b6d96bed TS |
2550 | uint32_t wt2; |
2551 | ||
f01be154 | 2552 | wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2553 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2554 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2555 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2556 | } |
5f7319cd | 2557 | update_fcr31(env, GETPC()); |
b6d96bed | 2558 | return wt2; |
fd4a04eb | 2559 | } |
b6d96bed | 2560 | |
895c2d04 | 2561 | uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2562 | { |
b6d96bed TS |
2563 | uint32_t wt2; |
2564 | ||
f01be154 | 2565 | wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2566 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2567 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2568 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2569 | } |
5f7319cd | 2570 | update_fcr31(env, GETPC()); |
b6d96bed | 2571 | return wt2; |
fd4a04eb TS |
2572 | } |
2573 | ||
895c2d04 | 2574 | uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2575 | { |
b6d96bed TS |
2576 | uint64_t dt2; |
2577 | ||
f01be154 TS |
2578 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2579 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2580 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2581 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2582 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2583 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2584 | } |
5f7319cd | 2585 | update_fcr31(env, GETPC()); |
b6d96bed | 2586 | return dt2; |
fd4a04eb | 2587 | } |
b6d96bed | 2588 | |
895c2d04 | 2589 | uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2590 | { |
b6d96bed TS |
2591 | uint64_t dt2; |
2592 | ||
f01be154 TS |
2593 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2594 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2595 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2596 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2597 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2598 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2599 | } |
5f7319cd | 2600 | update_fcr31(env, GETPC()); |
b6d96bed | 2601 | return dt2; |
fd4a04eb | 2602 | } |
b6d96bed | 2603 | |
895c2d04 | 2604 | uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2605 | { |
b6d96bed TS |
2606 | uint32_t wt2; |
2607 | ||
f01be154 TS |
2608 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2609 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2610 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2611 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2612 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2613 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2614 | } |
5f7319cd | 2615 | update_fcr31(env, GETPC()); |
b6d96bed | 2616 | return wt2; |
fd4a04eb | 2617 | } |
b6d96bed | 2618 | |
895c2d04 | 2619 | uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2620 | { |
b6d96bed TS |
2621 | uint32_t wt2; |
2622 | ||
f01be154 TS |
2623 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2624 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2625 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2626 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2627 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2628 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2629 | } |
5f7319cd | 2630 | update_fcr31(env, GETPC()); |
b6d96bed | 2631 | return wt2; |
fd4a04eb TS |
2632 | } |
2633 | ||
895c2d04 | 2634 | uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2635 | { |
b6d96bed TS |
2636 | uint64_t dt2; |
2637 | ||
f01be154 TS |
2638 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2639 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2640 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2641 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2642 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2643 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2644 | } |
5f7319cd | 2645 | update_fcr31(env, GETPC()); |
b6d96bed | 2646 | return dt2; |
fd4a04eb | 2647 | } |
b6d96bed | 2648 | |
895c2d04 | 2649 | uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2650 | { |
b6d96bed TS |
2651 | uint64_t dt2; |
2652 | ||
f01be154 TS |
2653 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2654 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2655 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2656 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2657 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2658 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2659 | } |
5f7319cd | 2660 | update_fcr31(env, GETPC()); |
b6d96bed | 2661 | return dt2; |
fd4a04eb | 2662 | } |
b6d96bed | 2663 | |
895c2d04 | 2664 | uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2665 | { |
b6d96bed TS |
2666 | uint32_t wt2; |
2667 | ||
f01be154 TS |
2668 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2669 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2670 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2671 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2672 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2673 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2674 | } |
5f7319cd | 2675 | update_fcr31(env, GETPC()); |
b6d96bed | 2676 | return wt2; |
fd4a04eb | 2677 | } |
b6d96bed | 2678 | |
895c2d04 | 2679 | uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2680 | { |
b6d96bed TS |
2681 | uint32_t wt2; |
2682 | ||
f01be154 TS |
2683 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2684 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2685 | RESTORE_ROUNDING_MODE; |
4cc2e5f9 AJ |
2686 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2687 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2688 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2689 | } |
5f7319cd | 2690 | update_fcr31(env, GETPC()); |
b6d96bed | 2691 | return wt2; |
fd4a04eb TS |
2692 | } |
2693 | ||
a16336e4 | 2694 | /* unary operations, not modifying fp status */ |
b6d96bed | 2695 | #define FLOAT_UNOP(name) \ |
c01fccd2 | 2696 | uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ |
b6d96bed TS |
2697 | { \ |
2698 | return float64_ ## name(fdt0); \ | |
2699 | } \ | |
c01fccd2 | 2700 | uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ |
b6d96bed TS |
2701 | { \ |
2702 | return float32_ ## name(fst0); \ | |
2703 | } \ | |
c01fccd2 | 2704 | uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ |
b6d96bed TS |
2705 | { \ |
2706 | uint32_t wt0; \ | |
2707 | uint32_t wth0; \ | |
2708 | \ | |
2709 | wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ | |
2710 | wth0 = float32_ ## name(fdt0 >> 32); \ | |
2711 | return ((uint64_t)wth0 << 32) | wt0; \ | |
a16336e4 TS |
2712 | } |
2713 | FLOAT_UNOP(abs) | |
2714 | FLOAT_UNOP(chs) | |
2715 | #undef FLOAT_UNOP | |
2716 | ||
8dfdb87c | 2717 | /* MIPS specific unary operations */ |
895c2d04 | 2718 | uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2719 | { |
b6d96bed TS |
2720 | uint64_t fdt2; |
2721 | ||
05993cd0 | 2722 | fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); |
5f7319cd | 2723 | update_fcr31(env, GETPC()); |
b6d96bed | 2724 | return fdt2; |
8dfdb87c | 2725 | } |
b6d96bed | 2726 | |
895c2d04 | 2727 | uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) |
8dfdb87c | 2728 | { |
b6d96bed TS |
2729 | uint32_t fst2; |
2730 | ||
05993cd0 | 2731 | fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); |
5f7319cd | 2732 | update_fcr31(env, GETPC()); |
b6d96bed | 2733 | return fst2; |
57fa1fb3 | 2734 | } |
57fa1fb3 | 2735 | |
895c2d04 | 2736 | uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2737 | { |
b6d96bed TS |
2738 | uint64_t fdt2; |
2739 | ||
f01be154 | 2740 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
05993cd0 | 2741 | fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); |
5f7319cd | 2742 | update_fcr31(env, GETPC()); |
b6d96bed | 2743 | return fdt2; |
8dfdb87c | 2744 | } |
b6d96bed | 2745 | |
895c2d04 | 2746 | uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) |
8dfdb87c | 2747 | { |
b6d96bed TS |
2748 | uint32_t fst2; |
2749 | ||
f01be154 | 2750 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
05993cd0 | 2751 | fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
5f7319cd | 2752 | update_fcr31(env, GETPC()); |
b6d96bed | 2753 | return fst2; |
8dfdb87c TS |
2754 | } |
2755 | ||
895c2d04 | 2756 | uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2757 | { |
b6d96bed TS |
2758 | uint64_t fdt2; |
2759 | ||
05993cd0 | 2760 | fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); |
5f7319cd | 2761 | update_fcr31(env, GETPC()); |
b6d96bed | 2762 | return fdt2; |
8dfdb87c | 2763 | } |
b6d96bed | 2764 | |
895c2d04 | 2765 | uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) |
8dfdb87c | 2766 | { |
b6d96bed TS |
2767 | uint32_t fst2; |
2768 | ||
05993cd0 | 2769 | fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); |
5f7319cd | 2770 | update_fcr31(env, GETPC()); |
b6d96bed | 2771 | return fst2; |
8dfdb87c | 2772 | } |
b6d96bed | 2773 | |
895c2d04 | 2774 | uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2775 | { |
b6d96bed TS |
2776 | uint32_t fst2; |
2777 | uint32_t fsth2; | |
2778 | ||
05993cd0 AJ |
2779 | fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
2780 | fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status); | |
5f7319cd | 2781 | update_fcr31(env, GETPC()); |
b6d96bed | 2782 | return ((uint64_t)fsth2 << 32) | fst2; |
8dfdb87c TS |
2783 | } |
2784 | ||
895c2d04 | 2785 | uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2786 | { |
b6d96bed TS |
2787 | uint64_t fdt2; |
2788 | ||
f01be154 | 2789 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
05993cd0 | 2790 | fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); |
5f7319cd | 2791 | update_fcr31(env, GETPC()); |
b6d96bed | 2792 | return fdt2; |
8dfdb87c | 2793 | } |
b6d96bed | 2794 | |
895c2d04 | 2795 | uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) |
8dfdb87c | 2796 | { |
b6d96bed TS |
2797 | uint32_t fst2; |
2798 | ||
f01be154 | 2799 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
05993cd0 | 2800 | fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
5f7319cd | 2801 | update_fcr31(env, GETPC()); |
b6d96bed | 2802 | return fst2; |
8dfdb87c | 2803 | } |
b6d96bed | 2804 | |
895c2d04 | 2805 | uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2806 | { |
b6d96bed TS |
2807 | uint32_t fst2; |
2808 | uint32_t fsth2; | |
2809 | ||
f01be154 TS |
2810 | fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
2811 | fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); | |
05993cd0 AJ |
2812 | fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
2813 | fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status); | |
5f7319cd | 2814 | update_fcr31(env, GETPC()); |
b6d96bed | 2815 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 | 2816 | } |
57fa1fb3 | 2817 | |
895c2d04 | 2818 | #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env) |
b6d96bed | 2819 | |
fd4a04eb | 2820 | /* binary operations */ |
b6d96bed | 2821 | #define FLOAT_BINOP(name) \ |
895c2d04 BS |
2822 | uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ |
2823 | uint64_t fdt0, uint64_t fdt1) \ | |
b6d96bed TS |
2824 | { \ |
2825 | uint64_t dt2; \ | |
2826 | \ | |
f01be154 | 2827 | dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ |
5f7319cd | 2828 | update_fcr31(env, GETPC()); \ |
b6d96bed TS |
2829 | return dt2; \ |
2830 | } \ | |
2831 | \ | |
895c2d04 BS |
2832 | uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ |
2833 | uint32_t fst0, uint32_t fst1) \ | |
b6d96bed TS |
2834 | { \ |
2835 | uint32_t wt2; \ | |
2836 | \ | |
f01be154 | 2837 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
5f7319cd | 2838 | update_fcr31(env, GETPC()); \ |
b6d96bed TS |
2839 | return wt2; \ |
2840 | } \ | |
2841 | \ | |
895c2d04 BS |
2842 | uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ |
2843 | uint64_t fdt0, \ | |
2844 | uint64_t fdt1) \ | |
b6d96bed TS |
2845 | { \ |
2846 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2847 | uint32_t fsth0 = fdt0 >> 32; \ | |
2848 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2849 | uint32_t fsth1 = fdt1 >> 32; \ | |
2850 | uint32_t wt2; \ | |
2851 | uint32_t wth2; \ | |
2852 | \ | |
f01be154 TS |
2853 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
2854 | wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ | |
5f7319cd | 2855 | update_fcr31(env, GETPC()); \ |
b6d96bed | 2856 | return ((uint64_t)wth2 << 32) | wt2; \ |
fd4a04eb | 2857 | } |
b6d96bed | 2858 | |
fd4a04eb TS |
2859 | FLOAT_BINOP(add) |
2860 | FLOAT_BINOP(sub) | |
2861 | FLOAT_BINOP(mul) | |
2862 | FLOAT_BINOP(div) | |
2863 | #undef FLOAT_BINOP | |
2864 | ||
b3d6cd44 AJ |
2865 | /* FMA based operations */ |
2866 | #define FLOAT_FMA(name, type) \ | |
2867 | uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ | |
2868 | uint64_t fdt0, uint64_t fdt1, \ | |
2869 | uint64_t fdt2) \ | |
2870 | { \ | |
b3d6cd44 AJ |
2871 | fdt0 = float64_muladd(fdt0, fdt1, fdt2, type, \ |
2872 | &env->active_fpu.fp_status); \ | |
5f7319cd | 2873 | update_fcr31(env, GETPC()); \ |
b3d6cd44 AJ |
2874 | return fdt0; \ |
2875 | } \ | |
2876 | \ | |
2877 | uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ | |
2878 | uint32_t fst0, uint32_t fst1, \ | |
2879 | uint32_t fst2) \ | |
2880 | { \ | |
b3d6cd44 AJ |
2881 | fst0 = float32_muladd(fst0, fst1, fst2, type, \ |
2882 | &env->active_fpu.fp_status); \ | |
5f7319cd | 2883 | update_fcr31(env, GETPC()); \ |
b3d6cd44 AJ |
2884 | return fst0; \ |
2885 | } \ | |
2886 | \ | |
2887 | uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ | |
2888 | uint64_t fdt0, uint64_t fdt1, \ | |
2889 | uint64_t fdt2) \ | |
2890 | { \ | |
2891 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2892 | uint32_t fsth0 = fdt0 >> 32; \ | |
2893 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2894 | uint32_t fsth1 = fdt1 >> 32; \ | |
2895 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ | |
2896 | uint32_t fsth2 = fdt2 >> 32; \ | |
2897 | \ | |
b3d6cd44 AJ |
2898 | fst0 = float32_muladd(fst0, fst1, fst2, type, \ |
2899 | &env->active_fpu.fp_status); \ | |
2900 | fsth0 = float32_muladd(fsth0, fsth1, fsth2, type, \ | |
2901 | &env->active_fpu.fp_status); \ | |
5f7319cd | 2902 | update_fcr31(env, GETPC()); \ |
b3d6cd44 AJ |
2903 | return ((uint64_t)fsth0 << 32) | fst0; \ |
2904 | } | |
2905 | FLOAT_FMA(madd, 0) | |
2906 | FLOAT_FMA(msub, float_muladd_negate_c) | |
2907 | FLOAT_FMA(nmadd, float_muladd_negate_result) | |
2908 | FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) | |
2909 | #undef FLOAT_FMA | |
a16336e4 | 2910 | |
8dfdb87c | 2911 | /* MIPS specific binary operations */ |
895c2d04 | 2912 | uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2913 | { |
f01be154 | 2914 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
05993cd0 | 2915 | fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status)); |
5f7319cd | 2916 | update_fcr31(env, GETPC()); |
b6d96bed | 2917 | return fdt2; |
8dfdb87c | 2918 | } |
b6d96bed | 2919 | |
895c2d04 | 2920 | uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
8dfdb87c | 2921 | { |
f01be154 | 2922 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
05993cd0 | 2923 | fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); |
5f7319cd | 2924 | update_fcr31(env, GETPC()); |
b6d96bed | 2925 | return fst2; |
8dfdb87c | 2926 | } |
b6d96bed | 2927 | |
895c2d04 | 2928 | uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2929 | { |
b6d96bed TS |
2930 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2931 | uint32_t fsth0 = fdt0 >> 32; | |
2932 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; | |
2933 | uint32_t fsth2 = fdt2 >> 32; | |
2934 | ||
f01be154 TS |
2935 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2936 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); | |
05993cd0 AJ |
2937 | fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); |
2938 | fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); | |
5f7319cd | 2939 | update_fcr31(env, GETPC()); |
b6d96bed | 2940 | return ((uint64_t)fsth2 << 32) | fst2; |
8dfdb87c TS |
2941 | } |
2942 | ||
895c2d04 | 2943 | uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2944 | { |
f01be154 | 2945 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
05993cd0 | 2946 | fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); |
f01be154 | 2947 | fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); |
5f7319cd | 2948 | update_fcr31(env, GETPC()); |
b6d96bed | 2949 | return fdt2; |
8dfdb87c | 2950 | } |
b6d96bed | 2951 | |
895c2d04 | 2952 | uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
8dfdb87c | 2953 | { |
f01be154 | 2954 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
05993cd0 | 2955 | fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); |
f01be154 | 2956 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
5f7319cd | 2957 | update_fcr31(env, GETPC()); |
b6d96bed | 2958 | return fst2; |
8dfdb87c | 2959 | } |
b6d96bed | 2960 | |
895c2d04 | 2961 | uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2962 | { |
b6d96bed TS |
2963 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2964 | uint32_t fsth0 = fdt0 >> 32; | |
2965 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; | |
2966 | uint32_t fsth2 = fdt2 >> 32; | |
2967 | ||
f01be154 TS |
2968 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2969 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); | |
05993cd0 AJ |
2970 | fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); |
2971 | fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); | |
f01be154 TS |
2972 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
2973 | fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); | |
5f7319cd | 2974 | update_fcr31(env, GETPC()); |
b6d96bed | 2975 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 | 2976 | } |
57fa1fb3 | 2977 | |
895c2d04 | 2978 | uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
fd4a04eb | 2979 | { |
b6d96bed TS |
2980 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2981 | uint32_t fsth0 = fdt0 >> 32; | |
2982 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; | |
2983 | uint32_t fsth1 = fdt1 >> 32; | |
2984 | uint32_t fst2; | |
2985 | uint32_t fsth2; | |
2986 | ||
f01be154 TS |
2987 | fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); |
2988 | fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); | |
5f7319cd | 2989 | update_fcr31(env, GETPC()); |
b6d96bed | 2990 | return ((uint64_t)fsth2 << 32) | fst2; |
fd4a04eb TS |
2991 | } |
2992 | ||
895c2d04 | 2993 | uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
57fa1fb3 | 2994 | { |
b6d96bed TS |
2995 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2996 | uint32_t fsth0 = fdt0 >> 32; | |
2997 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; | |
2998 | uint32_t fsth1 = fdt1 >> 32; | |
2999 | uint32_t fst2; | |
3000 | uint32_t fsth2; | |
3001 | ||
f01be154 TS |
3002 | fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); |
3003 | fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); | |
5f7319cd | 3004 | update_fcr31(env, GETPC()); |
b6d96bed | 3005 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 TS |
3006 | } |
3007 | ||
8dfdb87c | 3008 | /* compare operations */ |
b6d96bed | 3009 | #define FOP_COND_D(op, cond) \ |
895c2d04 BS |
3010 | void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3011 | uint64_t fdt1, int cc) \ | |
b6d96bed | 3012 | { \ |
6a385343 | 3013 | int c; \ |
6a385343 | 3014 | c = cond; \ |
5f7319cd | 3015 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3016 | if (c) \ |
f01be154 | 3017 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3018 | else \ |
f01be154 | 3019 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3020 | } \ |
895c2d04 BS |
3021 | void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3022 | uint64_t fdt1, int cc) \ | |
b6d96bed TS |
3023 | { \ |
3024 | int c; \ | |
3025 | fdt0 = float64_abs(fdt0); \ | |
3026 | fdt1 = float64_abs(fdt1); \ | |
3027 | c = cond; \ | |
5f7319cd | 3028 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3029 | if (c) \ |
f01be154 | 3030 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3031 | else \ |
f01be154 | 3032 | CLEAR_FP_COND(cc, env->active_fpu); \ |
fd4a04eb TS |
3033 | } |
3034 | ||
fd4a04eb | 3035 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3036 | * but float64_unordered_quiet() is still called. */ |
3037 | FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0)) | |
3038 | FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)) | |
06a0e6b1 | 3039 | FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
211315fb | 3040 | FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
06a0e6b1 AJ |
3041 | FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
3042 | FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) | |
3043 | FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) | |
3044 | FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) | |
fd4a04eb | 3045 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3046 | * but float64_unordered() is still called. */ |
3047 | FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0)) | |
3048 | FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3049 | FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
3050 | FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
3051 | FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
3a599383 | 3052 | FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
06a0e6b1 | 3053 | FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
3a599383 | 3054 | FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
b6d96bed TS |
3055 | |
3056 | #define FOP_COND_S(op, cond) \ | |
895c2d04 BS |
3057 | void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
3058 | uint32_t fst1, int cc) \ | |
b6d96bed | 3059 | { \ |
6a385343 | 3060 | int c; \ |
6a385343 | 3061 | c = cond; \ |
5f7319cd | 3062 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3063 | if (c) \ |
f01be154 | 3064 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3065 | else \ |
f01be154 | 3066 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3067 | } \ |
895c2d04 BS |
3068 | void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
3069 | uint32_t fst1, int cc) \ | |
b6d96bed TS |
3070 | { \ |
3071 | int c; \ | |
3072 | fst0 = float32_abs(fst0); \ | |
3073 | fst1 = float32_abs(fst1); \ | |
3074 | c = cond; \ | |
5f7319cd | 3075 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3076 | if (c) \ |
f01be154 | 3077 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3078 | else \ |
f01be154 | 3079 | CLEAR_FP_COND(cc, env->active_fpu); \ |
fd4a04eb TS |
3080 | } |
3081 | ||
fd4a04eb | 3082 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3083 | * but float32_unordered_quiet() is still called. */ |
3084 | FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0)) | |
3085 | FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)) | |
06a0e6b1 | 3086 | FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
211315fb | 3087 | FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
06a0e6b1 AJ |
3088 | FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
3089 | FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) | |
3090 | FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) | |
3091 | FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) | |
fd4a04eb | 3092 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3093 | * but float32_unordered() is still called. */ |
3094 | FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0)) | |
3095 | FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3096 | FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
3097 | FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
3098 | FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
3a599383 | 3099 | FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
06a0e6b1 | 3100 | FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
3a599383 | 3101 | FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
b6d96bed TS |
3102 | |
3103 | #define FOP_COND_PS(op, condl, condh) \ | |
895c2d04 BS |
3104 | void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3105 | uint64_t fdt1, int cc) \ | |
b6d96bed | 3106 | { \ |
6a385343 AJ |
3107 | uint32_t fst0, fsth0, fst1, fsth1; \ |
3108 | int ch, cl; \ | |
6a385343 AJ |
3109 | fst0 = fdt0 & 0XFFFFFFFF; \ |
3110 | fsth0 = fdt0 >> 32; \ | |
3111 | fst1 = fdt1 & 0XFFFFFFFF; \ | |
3112 | fsth1 = fdt1 >> 32; \ | |
3113 | cl = condl; \ | |
3114 | ch = condh; \ | |
5f7319cd | 3115 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3116 | if (cl) \ |
f01be154 | 3117 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3118 | else \ |
f01be154 | 3119 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3120 | if (ch) \ |
f01be154 | 3121 | SET_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 3122 | else \ |
f01be154 | 3123 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 3124 | } \ |
895c2d04 BS |
3125 | void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3126 | uint64_t fdt1, int cc) \ | |
b6d96bed | 3127 | { \ |
6a385343 AJ |
3128 | uint32_t fst0, fsth0, fst1, fsth1; \ |
3129 | int ch, cl; \ | |
3130 | fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ | |
3131 | fsth0 = float32_abs(fdt0 >> 32); \ | |
3132 | fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ | |
3133 | fsth1 = float32_abs(fdt1 >> 32); \ | |
3134 | cl = condl; \ | |
3135 | ch = condh; \ | |
5f7319cd | 3136 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3137 | if (cl) \ |
f01be154 | 3138 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3139 | else \ |
f01be154 | 3140 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3141 | if (ch) \ |
f01be154 | 3142 | SET_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 3143 | else \ |
f01be154 | 3144 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
fd4a04eb TS |
3145 | } |
3146 | ||
3147 | /* NOTE: the comma operator will make "cond" to eval to false, | |
3a599383 AJ |
3148 | * but float32_unordered_quiet() is still called. */ |
3149 | FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0), | |
3150 | (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0)) | |
3151 | FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), | |
3152 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3153 | FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3154 | float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
211315fb AJ |
3155 | FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3156 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3157 | FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3158 | float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3159 | FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), | |
3160 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3161 | FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), | |
3162 | float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3163 | FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), | |
3164 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
fd4a04eb | 3165 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3166 | * but float32_unordered() is still called. */ |
3167 | FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0), | |
3168 | (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0)) | |
3169 | FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status), | |
3170 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3171 | FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
3172 | float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3173 | FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
3174 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3175 | FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
3176 | float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3a599383 AJ |
3177 | FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
3178 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3179 | FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status), |
3180 | float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3a599383 AJ |
3181 | FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), |
3182 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |