]>
Commit | Line | Data |
---|---|---|
6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
6af0bf9c | 18 | */ |
2d0e944d | 19 | #include <stdlib.h> |
6af0bf9c FB |
20 | #include "exec.h" |
21 | ||
05f778c8 TS |
22 | #include "host-utils.h" |
23 | ||
a7812ae4 | 24 | #include "helper.h" |
83dae095 PB |
25 | |
26 | #ifndef CONFIG_USER_ONLY | |
27 | static inline void cpu_mips_tlb_flush (CPUState *env, int flush_global); | |
28 | #endif | |
29 | ||
6af0bf9c FB |
30 | /*****************************************************************************/ |
31 | /* Exceptions processing helpers */ | |
6af0bf9c | 32 | |
c01fccd2 | 33 | void helper_raise_exception_err (uint32_t exception, int error_code) |
6af0bf9c FB |
34 | { |
35 | #if 1 | |
93fcfe39 AL |
36 | if (exception < 0x100) |
37 | qemu_log("%s: %d %d\n", __func__, exception, error_code); | |
6af0bf9c FB |
38 | #endif |
39 | env->exception_index = exception; | |
40 | env->error_code = error_code; | |
6af0bf9c FB |
41 | cpu_loop_exit(); |
42 | } | |
43 | ||
c01fccd2 | 44 | void helper_raise_exception (uint32_t exception) |
6af0bf9c | 45 | { |
c01fccd2 | 46 | helper_raise_exception_err(exception, 0); |
6af0bf9c FB |
47 | } |
48 | ||
f9480ffc TS |
49 | #if !defined(CONFIG_USER_ONLY) |
50 | static void do_restore_state (void *pc_ptr) | |
4ad40f36 | 51 | { |
a607922c FB |
52 | TranslationBlock *tb; |
53 | unsigned long pc = (unsigned long) pc_ptr; | |
54 | ||
55 | tb = tb_find_pc (pc); | |
56 | if (tb) { | |
57 | cpu_restore_state (tb, env, pc, NULL); | |
58 | } | |
4ad40f36 | 59 | } |
f9480ffc | 60 | #endif |
4ad40f36 | 61 | |
0ae43045 AJ |
62 | #if defined(CONFIG_USER_ONLY) |
63 | #define HELPER_LD(name, insn, type) \ | |
64 | static inline type do_##name(target_ulong addr, int mem_idx) \ | |
65 | { \ | |
66 | return (type) insn##_raw(addr); \ | |
67 | } | |
68 | #else | |
69 | #define HELPER_LD(name, insn, type) \ | |
70 | static inline type do_##name(target_ulong addr, int mem_idx) \ | |
71 | { \ | |
72 | switch (mem_idx) \ | |
73 | { \ | |
74 | case 0: return (type) insn##_kernel(addr); break; \ | |
75 | case 1: return (type) insn##_super(addr); break; \ | |
76 | default: \ | |
77 | case 2: return (type) insn##_user(addr); break; \ | |
78 | } \ | |
79 | } | |
80 | #endif | |
81 | HELPER_LD(lbu, ldub, uint8_t) | |
82 | HELPER_LD(lw, ldl, int32_t) | |
83 | #ifdef TARGET_MIPS64 | |
84 | HELPER_LD(ld, ldq, int64_t) | |
85 | #endif | |
86 | #undef HELPER_LD | |
87 | ||
88 | #if defined(CONFIG_USER_ONLY) | |
89 | #define HELPER_ST(name, insn, type) \ | |
90 | static inline void do_##name(target_ulong addr, type val, int mem_idx) \ | |
91 | { \ | |
92 | insn##_raw(addr, val); \ | |
93 | } | |
94 | #else | |
95 | #define HELPER_ST(name, insn, type) \ | |
96 | static inline void do_##name(target_ulong addr, type val, int mem_idx) \ | |
97 | { \ | |
98 | switch (mem_idx) \ | |
99 | { \ | |
100 | case 0: insn##_kernel(addr, val); break; \ | |
101 | case 1: insn##_super(addr, val); break; \ | |
102 | default: \ | |
103 | case 2: insn##_user(addr, val); break; \ | |
104 | } \ | |
105 | } | |
106 | #endif | |
107 | HELPER_ST(sb, stb, uint8_t) | |
108 | HELPER_ST(sw, stl, uint32_t) | |
109 | #ifdef TARGET_MIPS64 | |
110 | HELPER_ST(sd, stq, uint64_t) | |
111 | #endif | |
112 | #undef HELPER_ST | |
113 | ||
d9bea114 | 114 | target_ulong helper_clo (target_ulong arg1) |
30898801 | 115 | { |
d9bea114 | 116 | return clo32(arg1); |
30898801 TS |
117 | } |
118 | ||
d9bea114 | 119 | target_ulong helper_clz (target_ulong arg1) |
30898801 | 120 | { |
d9bea114 | 121 | return clz32(arg1); |
30898801 TS |
122 | } |
123 | ||
d26bc211 | 124 | #if defined(TARGET_MIPS64) |
d9bea114 | 125 | target_ulong helper_dclo (target_ulong arg1) |
05f778c8 | 126 | { |
d9bea114 | 127 | return clo64(arg1); |
05f778c8 TS |
128 | } |
129 | ||
d9bea114 | 130 | target_ulong helper_dclz (target_ulong arg1) |
05f778c8 | 131 | { |
d9bea114 | 132 | return clz64(arg1); |
05f778c8 | 133 | } |
d26bc211 | 134 | #endif /* TARGET_MIPS64 */ |
c570fd16 | 135 | |
6af0bf9c | 136 | /* 64 bits arithmetic for 32 bits hosts */ |
c904ef0e | 137 | static inline uint64_t get_HILO (void) |
6af0bf9c | 138 | { |
b5dc7732 | 139 | return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; |
6af0bf9c FB |
140 | } |
141 | ||
c904ef0e | 142 | static inline void set_HILO (uint64_t HILO) |
6af0bf9c | 143 | { |
b5dc7732 TS |
144 | env->active_tc.LO[0] = (int32_t)HILO; |
145 | env->active_tc.HI[0] = (int32_t)(HILO >> 32); | |
6af0bf9c FB |
146 | } |
147 | ||
d9bea114 | 148 | static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO) |
e9c71dd1 | 149 | { |
b5dc7732 | 150 | env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
d9bea114 | 151 | arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
e9c71dd1 TS |
152 | } |
153 | ||
d9bea114 | 154 | static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO) |
e9c71dd1 | 155 | { |
d9bea114 | 156 | arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
b5dc7732 | 157 | env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
e9c71dd1 TS |
158 | } |
159 | ||
e9c71dd1 | 160 | /* Multiplication variants of the vr54xx. */ |
d9bea114 | 161 | target_ulong helper_muls (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 162 | { |
d9bea114 | 163 | set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
be24bb4f | 164 | |
d9bea114 | 165 | return arg1; |
e9c71dd1 TS |
166 | } |
167 | ||
d9bea114 | 168 | target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 169 | { |
d9bea114 | 170 | set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
be24bb4f | 171 | |
d9bea114 | 172 | return arg1; |
e9c71dd1 TS |
173 | } |
174 | ||
d9bea114 | 175 | target_ulong helper_macc (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 176 | { |
d9bea114 | 177 | set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
be24bb4f | 178 | |
d9bea114 | 179 | return arg1; |
e9c71dd1 TS |
180 | } |
181 | ||
d9bea114 | 182 | target_ulong helper_macchi (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 183 | { |
d9bea114 | 184 | set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
be24bb4f | 185 | |
d9bea114 | 186 | return arg1; |
e9c71dd1 TS |
187 | } |
188 | ||
d9bea114 | 189 | target_ulong helper_maccu (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 190 | { |
d9bea114 | 191 | set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
be24bb4f | 192 | |
d9bea114 | 193 | return arg1; |
e9c71dd1 TS |
194 | } |
195 | ||
d9bea114 | 196 | target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 197 | { |
d9bea114 | 198 | set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
be24bb4f | 199 | |
d9bea114 | 200 | return arg1; |
e9c71dd1 TS |
201 | } |
202 | ||
d9bea114 | 203 | target_ulong helper_msac (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 204 | { |
d9bea114 | 205 | set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
be24bb4f | 206 | |
d9bea114 | 207 | return arg1; |
e9c71dd1 TS |
208 | } |
209 | ||
d9bea114 | 210 | target_ulong helper_msachi (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 211 | { |
d9bea114 | 212 | set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
be24bb4f | 213 | |
d9bea114 | 214 | return arg1; |
e9c71dd1 TS |
215 | } |
216 | ||
d9bea114 | 217 | target_ulong helper_msacu (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 218 | { |
d9bea114 | 219 | set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
be24bb4f | 220 | |
d9bea114 | 221 | return arg1; |
e9c71dd1 TS |
222 | } |
223 | ||
d9bea114 | 224 | target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 225 | { |
d9bea114 | 226 | set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
be24bb4f | 227 | |
d9bea114 | 228 | return arg1; |
e9c71dd1 TS |
229 | } |
230 | ||
d9bea114 | 231 | target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 232 | { |
d9bea114 | 233 | set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); |
be24bb4f | 234 | |
d9bea114 | 235 | return arg1; |
e9c71dd1 TS |
236 | } |
237 | ||
d9bea114 | 238 | target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 239 | { |
d9bea114 | 240 | set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
be24bb4f | 241 | |
d9bea114 | 242 | return arg1; |
e9c71dd1 TS |
243 | } |
244 | ||
d9bea114 | 245 | target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 246 | { |
d9bea114 | 247 | set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
be24bb4f | 248 | |
d9bea114 | 249 | return arg1; |
e9c71dd1 TS |
250 | } |
251 | ||
d9bea114 | 252 | target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2) |
e9c71dd1 | 253 | { |
d9bea114 | 254 | set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
be24bb4f | 255 | |
d9bea114 | 256 | return arg1; |
e9c71dd1 | 257 | } |
6af0bf9c | 258 | |
214c465f | 259 | #ifdef TARGET_MIPS64 |
d9bea114 | 260 | void helper_dmult (target_ulong arg1, target_ulong arg2) |
214c465f | 261 | { |
d9bea114 | 262 | muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
214c465f TS |
263 | } |
264 | ||
d9bea114 | 265 | void helper_dmultu (target_ulong arg1, target_ulong arg2) |
214c465f | 266 | { |
d9bea114 | 267 | mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
214c465f TS |
268 | } |
269 | #endif | |
270 | ||
e7139c44 | 271 | #ifndef CONFIG_USER_ONLY |
c36bbb28 AJ |
272 | |
273 | static inline target_phys_addr_t do_translate_address(target_ulong address, int rw) | |
274 | { | |
275 | target_phys_addr_t lladdr; | |
276 | ||
277 | lladdr = cpu_mips_translate_address(env, address, rw); | |
278 | ||
279 | if (lladdr == -1LL) { | |
280 | cpu_loop_exit(); | |
281 | } else { | |
282 | return lladdr; | |
283 | } | |
284 | } | |
285 | ||
e7139c44 AJ |
286 | #define HELPER_LD_ATOMIC(name, insn) \ |
287 | target_ulong helper_##name(target_ulong arg, int mem_idx) \ | |
288 | { \ | |
c36bbb28 | 289 | env->lladdr = do_translate_address(arg, 0); \ |
e7139c44 AJ |
290 | env->llval = do_##insn(arg, mem_idx); \ |
291 | return env->llval; \ | |
292 | } | |
293 | HELPER_LD_ATOMIC(ll, lw) | |
294 | #ifdef TARGET_MIPS64 | |
295 | HELPER_LD_ATOMIC(lld, ld) | |
296 | #endif | |
297 | #undef HELPER_LD_ATOMIC | |
298 | ||
299 | #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ | |
300 | target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \ | |
301 | { \ | |
302 | target_long tmp; \ | |
303 | \ | |
304 | if (arg2 & almask) { \ | |
305 | env->CP0_BadVAddr = arg2; \ | |
306 | helper_raise_exception(EXCP_AdES); \ | |
307 | } \ | |
c36bbb28 | 308 | if (do_translate_address(arg2, 1) == env->lladdr) { \ |
e7139c44 AJ |
309 | tmp = do_##ld_insn(arg2, mem_idx); \ |
310 | if (tmp == env->llval) { \ | |
311 | do_##st_insn(arg2, arg1, mem_idx); \ | |
312 | return 1; \ | |
313 | } \ | |
314 | } \ | |
315 | return 0; \ | |
316 | } | |
317 | HELPER_ST_ATOMIC(sc, lw, sw, 0x3) | |
318 | #ifdef TARGET_MIPS64 | |
319 | HELPER_ST_ATOMIC(scd, ld, sd, 0x7) | |
320 | #endif | |
321 | #undef HELPER_ST_ATOMIC | |
322 | #endif | |
323 | ||
c8c2227e TS |
324 | #ifdef TARGET_WORDS_BIGENDIAN |
325 | #define GET_LMASK(v) ((v) & 3) | |
326 | #define GET_OFFSET(addr, offset) (addr + (offset)) | |
327 | #else | |
328 | #define GET_LMASK(v) (((v) & 3) ^ 3) | |
329 | #define GET_OFFSET(addr, offset) (addr - (offset)) | |
330 | #endif | |
331 | ||
d9bea114 | 332 | target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx) |
c8c2227e TS |
333 | { |
334 | target_ulong tmp; | |
335 | ||
0ae43045 | 336 | tmp = do_lbu(arg2, mem_idx); |
d9bea114 | 337 | arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); |
c8c2227e | 338 | |
d9bea114 | 339 | if (GET_LMASK(arg2) <= 2) { |
0ae43045 | 340 | tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); |
d9bea114 | 341 | arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); |
c8c2227e TS |
342 | } |
343 | ||
d9bea114 | 344 | if (GET_LMASK(arg2) <= 1) { |
0ae43045 | 345 | tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); |
d9bea114 | 346 | arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); |
c8c2227e TS |
347 | } |
348 | ||
d9bea114 | 349 | if (GET_LMASK(arg2) == 0) { |
0ae43045 | 350 | tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); |
d9bea114 | 351 | arg1 = (arg1 & 0xFFFFFF00) | tmp; |
c8c2227e | 352 | } |
d9bea114 | 353 | return (int32_t)arg1; |
c8c2227e TS |
354 | } |
355 | ||
d9bea114 | 356 | target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx) |
c8c2227e TS |
357 | { |
358 | target_ulong tmp; | |
359 | ||
0ae43045 | 360 | tmp = do_lbu(arg2, mem_idx); |
d9bea114 | 361 | arg1 = (arg1 & 0xFFFFFF00) | tmp; |
c8c2227e | 362 | |
d9bea114 | 363 | if (GET_LMASK(arg2) >= 1) { |
0ae43045 | 364 | tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); |
d9bea114 | 365 | arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); |
c8c2227e TS |
366 | } |
367 | ||
d9bea114 | 368 | if (GET_LMASK(arg2) >= 2) { |
0ae43045 | 369 | tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); |
d9bea114 | 370 | arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); |
c8c2227e TS |
371 | } |
372 | ||
d9bea114 | 373 | if (GET_LMASK(arg2) == 3) { |
0ae43045 | 374 | tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); |
d9bea114 | 375 | arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); |
c8c2227e | 376 | } |
d9bea114 | 377 | return (int32_t)arg1; |
c8c2227e TS |
378 | } |
379 | ||
d9bea114 | 380 | void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx) |
c8c2227e | 381 | { |
0ae43045 | 382 | do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e | 383 | |
d9bea114 | 384 | if (GET_LMASK(arg2) <= 2) |
0ae43045 | 385 | do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 386 | |
d9bea114 | 387 | if (GET_LMASK(arg2) <= 1) |
0ae43045 | 388 | do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 389 | |
d9bea114 | 390 | if (GET_LMASK(arg2) == 0) |
0ae43045 | 391 | do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); |
c8c2227e TS |
392 | } |
393 | ||
d9bea114 | 394 | void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx) |
c8c2227e | 395 | { |
0ae43045 | 396 | do_sb(arg2, (uint8_t)arg1, mem_idx); |
c8c2227e | 397 | |
d9bea114 | 398 | if (GET_LMASK(arg2) >= 1) |
0ae43045 | 399 | do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 400 | |
d9bea114 | 401 | if (GET_LMASK(arg2) >= 2) |
0ae43045 | 402 | do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 403 | |
d9bea114 | 404 | if (GET_LMASK(arg2) == 3) |
0ae43045 | 405 | do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e TS |
406 | } |
407 | ||
408 | #if defined(TARGET_MIPS64) | |
409 | /* "half" load and stores. We must do the memory access inline, | |
410 | or fault handling won't work. */ | |
411 | ||
412 | #ifdef TARGET_WORDS_BIGENDIAN | |
413 | #define GET_LMASK64(v) ((v) & 7) | |
414 | #else | |
415 | #define GET_LMASK64(v) (((v) & 7) ^ 7) | |
416 | #endif | |
417 | ||
d9bea114 | 418 | target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx) |
c8c2227e TS |
419 | { |
420 | uint64_t tmp; | |
421 | ||
0ae43045 | 422 | tmp = do_lbu(arg2, mem_idx); |
d9bea114 | 423 | arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
c8c2227e | 424 | |
d9bea114 | 425 | if (GET_LMASK64(arg2) <= 6) { |
0ae43045 | 426 | tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); |
d9bea114 | 427 | arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
c8c2227e TS |
428 | } |
429 | ||
d9bea114 | 430 | if (GET_LMASK64(arg2) <= 5) { |
0ae43045 | 431 | tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); |
d9bea114 | 432 | arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
c8c2227e TS |
433 | } |
434 | ||
d9bea114 | 435 | if (GET_LMASK64(arg2) <= 4) { |
0ae43045 | 436 | tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); |
d9bea114 | 437 | arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
c8c2227e TS |
438 | } |
439 | ||
d9bea114 | 440 | if (GET_LMASK64(arg2) <= 3) { |
0ae43045 | 441 | tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx); |
d9bea114 | 442 | arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
c8c2227e TS |
443 | } |
444 | ||
d9bea114 | 445 | if (GET_LMASK64(arg2) <= 2) { |
0ae43045 | 446 | tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx); |
d9bea114 | 447 | arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
c8c2227e TS |
448 | } |
449 | ||
d9bea114 | 450 | if (GET_LMASK64(arg2) <= 1) { |
0ae43045 | 451 | tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx); |
d9bea114 | 452 | arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
c8c2227e TS |
453 | } |
454 | ||
d9bea114 | 455 | if (GET_LMASK64(arg2) == 0) { |
0ae43045 | 456 | tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx); |
d9bea114 | 457 | arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; |
c8c2227e | 458 | } |
be24bb4f | 459 | |
d9bea114 | 460 | return arg1; |
c8c2227e TS |
461 | } |
462 | ||
d9bea114 | 463 | target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx) |
c8c2227e TS |
464 | { |
465 | uint64_t tmp; | |
466 | ||
0ae43045 | 467 | tmp = do_lbu(arg2, mem_idx); |
d9bea114 | 468 | arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; |
c8c2227e | 469 | |
d9bea114 | 470 | if (GET_LMASK64(arg2) >= 1) { |
0ae43045 | 471 | tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); |
d9bea114 | 472 | arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
c8c2227e TS |
473 | } |
474 | ||
d9bea114 | 475 | if (GET_LMASK64(arg2) >= 2) { |
0ae43045 | 476 | tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); |
d9bea114 | 477 | arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
c8c2227e TS |
478 | } |
479 | ||
d9bea114 | 480 | if (GET_LMASK64(arg2) >= 3) { |
0ae43045 | 481 | tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); |
d9bea114 | 482 | arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
c8c2227e TS |
483 | } |
484 | ||
d9bea114 | 485 | if (GET_LMASK64(arg2) >= 4) { |
0ae43045 | 486 | tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx); |
d9bea114 | 487 | arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
c8c2227e TS |
488 | } |
489 | ||
d9bea114 | 490 | if (GET_LMASK64(arg2) >= 5) { |
0ae43045 | 491 | tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx); |
d9bea114 | 492 | arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
c8c2227e TS |
493 | } |
494 | ||
d9bea114 | 495 | if (GET_LMASK64(arg2) >= 6) { |
0ae43045 | 496 | tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx); |
d9bea114 | 497 | arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
c8c2227e TS |
498 | } |
499 | ||
d9bea114 | 500 | if (GET_LMASK64(arg2) == 7) { |
0ae43045 | 501 | tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx); |
d9bea114 | 502 | arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
c8c2227e | 503 | } |
be24bb4f | 504 | |
d9bea114 | 505 | return arg1; |
c8c2227e TS |
506 | } |
507 | ||
d9bea114 | 508 | void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx) |
c8c2227e | 509 | { |
0ae43045 | 510 | do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx); |
c8c2227e | 511 | |
d9bea114 | 512 | if (GET_LMASK64(arg2) <= 6) |
0ae43045 | 513 | do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); |
c8c2227e | 514 | |
d9bea114 | 515 | if (GET_LMASK64(arg2) <= 5) |
0ae43045 | 516 | do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); |
c8c2227e | 517 | |
d9bea114 | 518 | if (GET_LMASK64(arg2) <= 4) |
0ae43045 | 519 | do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); |
c8c2227e | 520 | |
d9bea114 | 521 | if (GET_LMASK64(arg2) <= 3) |
0ae43045 | 522 | do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e | 523 | |
d9bea114 | 524 | if (GET_LMASK64(arg2) <= 2) |
0ae43045 | 525 | do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 526 | |
d9bea114 | 527 | if (GET_LMASK64(arg2) <= 1) |
0ae43045 | 528 | do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 529 | |
d9bea114 | 530 | if (GET_LMASK64(arg2) <= 0) |
0ae43045 | 531 | do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); |
c8c2227e TS |
532 | } |
533 | ||
d9bea114 | 534 | void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx) |
c8c2227e | 535 | { |
0ae43045 | 536 | do_sb(arg2, (uint8_t)arg1, mem_idx); |
c8c2227e | 537 | |
d9bea114 | 538 | if (GET_LMASK64(arg2) >= 1) |
0ae43045 | 539 | do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 540 | |
d9bea114 | 541 | if (GET_LMASK64(arg2) >= 2) |
0ae43045 | 542 | do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 543 | |
d9bea114 | 544 | if (GET_LMASK64(arg2) >= 3) |
0ae43045 | 545 | do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e | 546 | |
d9bea114 | 547 | if (GET_LMASK64(arg2) >= 4) |
0ae43045 | 548 | do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); |
c8c2227e | 549 | |
d9bea114 | 550 | if (GET_LMASK64(arg2) >= 5) |
0ae43045 | 551 | do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); |
c8c2227e | 552 | |
d9bea114 | 553 | if (GET_LMASK64(arg2) >= 6) |
0ae43045 | 554 | do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); |
c8c2227e | 555 | |
d9bea114 | 556 | if (GET_LMASK64(arg2) == 7) |
0ae43045 | 557 | do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); |
c8c2227e TS |
558 | } |
559 | #endif /* TARGET_MIPS64 */ | |
560 | ||
3c824109 NF |
561 | static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; |
562 | ||
563 | void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) | |
564 | { | |
565 | target_ulong base_reglist = reglist & 0xf; | |
566 | target_ulong do_r31 = reglist & 0x10; | |
567 | #ifdef CONFIG_USER_ONLY | |
568 | #undef ldfun | |
569 | #define ldfun ldl_raw | |
570 | #else | |
571 | uint32_t (*ldfun)(target_ulong); | |
572 | ||
573 | switch (mem_idx) | |
574 | { | |
575 | case 0: ldfun = ldl_kernel; break; | |
576 | case 1: ldfun = ldl_super; break; | |
577 | default: | |
578 | case 2: ldfun = ldl_user; break; | |
579 | } | |
580 | #endif | |
581 | ||
582 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
583 | target_ulong i; | |
584 | ||
585 | for (i = 0; i < base_reglist; i++) { | |
586 | env->active_tc.gpr[multiple_regs[i]] = (target_long) ldfun(addr); | |
587 | addr += 4; | |
588 | } | |
589 | } | |
590 | ||
591 | if (do_r31) { | |
592 | env->active_tc.gpr[31] = (target_long) ldfun(addr); | |
593 | } | |
594 | } | |
595 | ||
596 | void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) | |
597 | { | |
598 | target_ulong base_reglist = reglist & 0xf; | |
599 | target_ulong do_r31 = reglist & 0x10; | |
600 | #ifdef CONFIG_USER_ONLY | |
601 | #undef stfun | |
602 | #define stfun stl_raw | |
603 | #else | |
604 | void (*stfun)(target_ulong, uint32_t); | |
605 | ||
606 | switch (mem_idx) | |
607 | { | |
608 | case 0: stfun = stl_kernel; break; | |
609 | case 1: stfun = stl_super; break; | |
610 | default: | |
611 | case 2: stfun = stl_user; break; | |
612 | } | |
613 | #endif | |
614 | ||
615 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
616 | target_ulong i; | |
617 | ||
618 | for (i = 0; i < base_reglist; i++) { | |
619 | stfun(addr, env->active_tc.gpr[multiple_regs[i]]); | |
620 | addr += 4; | |
621 | } | |
622 | } | |
623 | ||
624 | if (do_r31) { | |
625 | stfun(addr, env->active_tc.gpr[31]); | |
626 | } | |
627 | } | |
628 | ||
629 | #if defined(TARGET_MIPS64) | |
630 | void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) | |
631 | { | |
632 | target_ulong base_reglist = reglist & 0xf; | |
633 | target_ulong do_r31 = reglist & 0x10; | |
634 | #ifdef CONFIG_USER_ONLY | |
635 | #undef ldfun | |
636 | #define ldfun ldq_raw | |
637 | #else | |
638 | uint64_t (*ldfun)(target_ulong); | |
639 | ||
640 | switch (mem_idx) | |
641 | { | |
642 | case 0: ldfun = ldq_kernel; break; | |
643 | case 1: ldfun = ldq_super; break; | |
644 | default: | |
645 | case 2: ldfun = ldq_user; break; | |
646 | } | |
647 | #endif | |
648 | ||
649 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
650 | target_ulong i; | |
651 | ||
652 | for (i = 0; i < base_reglist; i++) { | |
653 | env->active_tc.gpr[multiple_regs[i]] = ldfun(addr); | |
654 | addr += 8; | |
655 | } | |
656 | } | |
657 | ||
658 | if (do_r31) { | |
659 | env->active_tc.gpr[31] = ldfun(addr); | |
660 | } | |
661 | } | |
662 | ||
663 | void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) | |
664 | { | |
665 | target_ulong base_reglist = reglist & 0xf; | |
666 | target_ulong do_r31 = reglist & 0x10; | |
667 | #ifdef CONFIG_USER_ONLY | |
668 | #undef stfun | |
669 | #define stfun stq_raw | |
670 | #else | |
671 | void (*stfun)(target_ulong, uint64_t); | |
672 | ||
673 | switch (mem_idx) | |
674 | { | |
675 | case 0: stfun = stq_kernel; break; | |
676 | case 1: stfun = stq_super; break; | |
677 | default: | |
678 | case 2: stfun = stq_user; break; | |
679 | } | |
680 | #endif | |
681 | ||
682 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
683 | target_ulong i; | |
684 | ||
685 | for (i = 0; i < base_reglist; i++) { | |
686 | stfun(addr, env->active_tc.gpr[multiple_regs[i]]); | |
687 | addr += 8; | |
688 | } | |
689 | } | |
690 | ||
691 | if (do_r31) { | |
692 | stfun(addr, env->active_tc.gpr[31]); | |
693 | } | |
694 | } | |
695 | #endif | |
696 | ||
0eaef5aa | 697 | #ifndef CONFIG_USER_ONLY |
6af0bf9c | 698 | /* CP0 helpers */ |
c01fccd2 | 699 | target_ulong helper_mfc0_mvpcontrol (void) |
f1aa6320 | 700 | { |
be24bb4f | 701 | return env->mvp->CP0_MVPControl; |
f1aa6320 TS |
702 | } |
703 | ||
c01fccd2 | 704 | target_ulong helper_mfc0_mvpconf0 (void) |
f1aa6320 | 705 | { |
be24bb4f | 706 | return env->mvp->CP0_MVPConf0; |
f1aa6320 TS |
707 | } |
708 | ||
c01fccd2 | 709 | target_ulong helper_mfc0_mvpconf1 (void) |
f1aa6320 | 710 | { |
be24bb4f | 711 | return env->mvp->CP0_MVPConf1; |
f1aa6320 TS |
712 | } |
713 | ||
c01fccd2 | 714 | target_ulong helper_mfc0_random (void) |
6af0bf9c | 715 | { |
be24bb4f | 716 | return (int32_t)cpu_mips_get_random(env); |
873eb012 | 717 | } |
6af0bf9c | 718 | |
c01fccd2 | 719 | target_ulong helper_mfc0_tcstatus (void) |
f1aa6320 | 720 | { |
b5dc7732 | 721 | return env->active_tc.CP0_TCStatus; |
f1aa6320 TS |
722 | } |
723 | ||
c01fccd2 | 724 | target_ulong helper_mftc0_tcstatus(void) |
f1aa6320 TS |
725 | { |
726 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
727 | ||
b5dc7732 TS |
728 | if (other_tc == env->current_tc) |
729 | return env->active_tc.CP0_TCStatus; | |
730 | else | |
731 | return env->tcs[other_tc].CP0_TCStatus; | |
f1aa6320 TS |
732 | } |
733 | ||
c01fccd2 | 734 | target_ulong helper_mfc0_tcbind (void) |
f1aa6320 | 735 | { |
b5dc7732 | 736 | return env->active_tc.CP0_TCBind; |
f1aa6320 TS |
737 | } |
738 | ||
c01fccd2 | 739 | target_ulong helper_mftc0_tcbind(void) |
f1aa6320 TS |
740 | { |
741 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
742 | ||
b5dc7732 TS |
743 | if (other_tc == env->current_tc) |
744 | return env->active_tc.CP0_TCBind; | |
745 | else | |
746 | return env->tcs[other_tc].CP0_TCBind; | |
f1aa6320 TS |
747 | } |
748 | ||
c01fccd2 | 749 | target_ulong helper_mfc0_tcrestart (void) |
f1aa6320 | 750 | { |
b5dc7732 | 751 | return env->active_tc.PC; |
f1aa6320 TS |
752 | } |
753 | ||
c01fccd2 | 754 | target_ulong helper_mftc0_tcrestart(void) |
f1aa6320 TS |
755 | { |
756 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
757 | ||
b5dc7732 TS |
758 | if (other_tc == env->current_tc) |
759 | return env->active_tc.PC; | |
760 | else | |
761 | return env->tcs[other_tc].PC; | |
f1aa6320 TS |
762 | } |
763 | ||
c01fccd2 | 764 | target_ulong helper_mfc0_tchalt (void) |
f1aa6320 | 765 | { |
b5dc7732 | 766 | return env->active_tc.CP0_TCHalt; |
f1aa6320 TS |
767 | } |
768 | ||
c01fccd2 | 769 | target_ulong helper_mftc0_tchalt(void) |
f1aa6320 TS |
770 | { |
771 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
772 | ||
b5dc7732 TS |
773 | if (other_tc == env->current_tc) |
774 | return env->active_tc.CP0_TCHalt; | |
775 | else | |
776 | return env->tcs[other_tc].CP0_TCHalt; | |
f1aa6320 TS |
777 | } |
778 | ||
c01fccd2 | 779 | target_ulong helper_mfc0_tccontext (void) |
f1aa6320 | 780 | { |
b5dc7732 | 781 | return env->active_tc.CP0_TCContext; |
f1aa6320 TS |
782 | } |
783 | ||
c01fccd2 | 784 | target_ulong helper_mftc0_tccontext(void) |
f1aa6320 TS |
785 | { |
786 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
787 | ||
b5dc7732 TS |
788 | if (other_tc == env->current_tc) |
789 | return env->active_tc.CP0_TCContext; | |
790 | else | |
791 | return env->tcs[other_tc].CP0_TCContext; | |
f1aa6320 TS |
792 | } |
793 | ||
c01fccd2 | 794 | target_ulong helper_mfc0_tcschedule (void) |
f1aa6320 | 795 | { |
b5dc7732 | 796 | return env->active_tc.CP0_TCSchedule; |
f1aa6320 TS |
797 | } |
798 | ||
c01fccd2 | 799 | target_ulong helper_mftc0_tcschedule(void) |
f1aa6320 TS |
800 | { |
801 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
802 | ||
b5dc7732 TS |
803 | if (other_tc == env->current_tc) |
804 | return env->active_tc.CP0_TCSchedule; | |
805 | else | |
806 | return env->tcs[other_tc].CP0_TCSchedule; | |
f1aa6320 TS |
807 | } |
808 | ||
c01fccd2 | 809 | target_ulong helper_mfc0_tcschefback (void) |
f1aa6320 | 810 | { |
b5dc7732 | 811 | return env->active_tc.CP0_TCScheFBack; |
f1aa6320 TS |
812 | } |
813 | ||
c01fccd2 | 814 | target_ulong helper_mftc0_tcschefback(void) |
f1aa6320 TS |
815 | { |
816 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
817 | ||
b5dc7732 TS |
818 | if (other_tc == env->current_tc) |
819 | return env->active_tc.CP0_TCScheFBack; | |
820 | else | |
821 | return env->tcs[other_tc].CP0_TCScheFBack; | |
f1aa6320 TS |
822 | } |
823 | ||
c01fccd2 | 824 | target_ulong helper_mfc0_count (void) |
873eb012 | 825 | { |
be24bb4f | 826 | return (int32_t)cpu_mips_get_count(env); |
6af0bf9c FB |
827 | } |
828 | ||
c01fccd2 | 829 | target_ulong helper_mftc0_entryhi(void) |
f1aa6320 TS |
830 | { |
831 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 | 832 | int32_t tcstatus; |
f1aa6320 | 833 | |
b5dc7732 TS |
834 | if (other_tc == env->current_tc) |
835 | tcstatus = env->active_tc.CP0_TCStatus; | |
836 | else | |
837 | tcstatus = env->tcs[other_tc].CP0_TCStatus; | |
838 | ||
839 | return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff); | |
f1aa6320 TS |
840 | } |
841 | ||
c01fccd2 | 842 | target_ulong helper_mftc0_status(void) |
f1aa6320 TS |
843 | { |
844 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1a3fd9c3 | 845 | target_ulong t0; |
b5dc7732 TS |
846 | int32_t tcstatus; |
847 | ||
848 | if (other_tc == env->current_tc) | |
849 | tcstatus = env->active_tc.CP0_TCStatus; | |
850 | else | |
851 | tcstatus = env->tcs[other_tc].CP0_TCStatus; | |
f1aa6320 | 852 | |
be24bb4f TS |
853 | t0 = env->CP0_Status & ~0xf1000018; |
854 | t0 |= tcstatus & (0xf << CP0TCSt_TCU0); | |
855 | t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX); | |
856 | t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); | |
857 | ||
858 | return t0; | |
f1aa6320 TS |
859 | } |
860 | ||
c01fccd2 | 861 | target_ulong helper_mfc0_lladdr (void) |
f1aa6320 | 862 | { |
2a6e32dd | 863 | return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); |
f1aa6320 TS |
864 | } |
865 | ||
c01fccd2 | 866 | target_ulong helper_mfc0_watchlo (uint32_t sel) |
f1aa6320 | 867 | { |
be24bb4f | 868 | return (int32_t)env->CP0_WatchLo[sel]; |
f1aa6320 TS |
869 | } |
870 | ||
c01fccd2 | 871 | target_ulong helper_mfc0_watchhi (uint32_t sel) |
f1aa6320 | 872 | { |
be24bb4f | 873 | return env->CP0_WatchHi[sel]; |
f1aa6320 TS |
874 | } |
875 | ||
c01fccd2 | 876 | target_ulong helper_mfc0_debug (void) |
f1aa6320 | 877 | { |
1a3fd9c3 | 878 | target_ulong t0 = env->CP0_Debug; |
f1aa6320 | 879 | if (env->hflags & MIPS_HFLAG_DM) |
be24bb4f TS |
880 | t0 |= 1 << CP0DB_DM; |
881 | ||
882 | return t0; | |
f1aa6320 TS |
883 | } |
884 | ||
c01fccd2 | 885 | target_ulong helper_mftc0_debug(void) |
f1aa6320 TS |
886 | { |
887 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 TS |
888 | int32_t tcstatus; |
889 | ||
890 | if (other_tc == env->current_tc) | |
891 | tcstatus = env->active_tc.CP0_Debug_tcstatus; | |
892 | else | |
893 | tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus; | |
f1aa6320 TS |
894 | |
895 | /* XXX: Might be wrong, check with EJTAG spec. */ | |
be24bb4f | 896 | return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
b5dc7732 | 897 | (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
f1aa6320 TS |
898 | } |
899 | ||
900 | #if defined(TARGET_MIPS64) | |
c01fccd2 | 901 | target_ulong helper_dmfc0_tcrestart (void) |
f1aa6320 | 902 | { |
b5dc7732 | 903 | return env->active_tc.PC; |
f1aa6320 TS |
904 | } |
905 | ||
c01fccd2 | 906 | target_ulong helper_dmfc0_tchalt (void) |
f1aa6320 | 907 | { |
b5dc7732 | 908 | return env->active_tc.CP0_TCHalt; |
f1aa6320 TS |
909 | } |
910 | ||
c01fccd2 | 911 | target_ulong helper_dmfc0_tccontext (void) |
f1aa6320 | 912 | { |
b5dc7732 | 913 | return env->active_tc.CP0_TCContext; |
f1aa6320 TS |
914 | } |
915 | ||
c01fccd2 | 916 | target_ulong helper_dmfc0_tcschedule (void) |
f1aa6320 | 917 | { |
b5dc7732 | 918 | return env->active_tc.CP0_TCSchedule; |
f1aa6320 TS |
919 | } |
920 | ||
c01fccd2 | 921 | target_ulong helper_dmfc0_tcschefback (void) |
f1aa6320 | 922 | { |
b5dc7732 | 923 | return env->active_tc.CP0_TCScheFBack; |
f1aa6320 TS |
924 | } |
925 | ||
c01fccd2 | 926 | target_ulong helper_dmfc0_lladdr (void) |
f1aa6320 | 927 | { |
2a6e32dd | 928 | return env->lladdr >> env->CP0_LLAddr_shift; |
f1aa6320 TS |
929 | } |
930 | ||
c01fccd2 | 931 | target_ulong helper_dmfc0_watchlo (uint32_t sel) |
f1aa6320 | 932 | { |
be24bb4f | 933 | return env->CP0_WatchLo[sel]; |
f1aa6320 TS |
934 | } |
935 | #endif /* TARGET_MIPS64 */ | |
936 | ||
d9bea114 | 937 | void helper_mtc0_index (target_ulong arg1) |
f1aa6320 TS |
938 | { |
939 | int num = 1; | |
940 | unsigned int tmp = env->tlb->nb_tlb; | |
941 | ||
942 | do { | |
943 | tmp >>= 1; | |
944 | num <<= 1; | |
945 | } while (tmp); | |
d9bea114 | 946 | env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); |
f1aa6320 TS |
947 | } |
948 | ||
d9bea114 | 949 | void helper_mtc0_mvpcontrol (target_ulong arg1) |
f1aa6320 TS |
950 | { |
951 | uint32_t mask = 0; | |
952 | uint32_t newval; | |
953 | ||
954 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) | |
955 | mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | | |
956 | (1 << CP0MVPCo_EVP); | |
957 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
958 | mask |= (1 << CP0MVPCo_STLB); | |
d9bea114 | 959 | newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); |
f1aa6320 TS |
960 | |
961 | // TODO: Enable/disable shared TLB, enable/disable VPEs. | |
962 | ||
963 | env->mvp->CP0_MVPControl = newval; | |
964 | } | |
965 | ||
d9bea114 | 966 | void helper_mtc0_vpecontrol (target_ulong arg1) |
f1aa6320 TS |
967 | { |
968 | uint32_t mask; | |
969 | uint32_t newval; | |
970 | ||
971 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | | |
972 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); | |
d9bea114 | 973 | newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); |
f1aa6320 TS |
974 | |
975 | /* Yield scheduler intercept not implemented. */ | |
976 | /* Gating storage scheduler intercept not implemented. */ | |
977 | ||
978 | // TODO: Enable/disable TCs. | |
979 | ||
980 | env->CP0_VPEControl = newval; | |
981 | } | |
982 | ||
d9bea114 | 983 | void helper_mtc0_vpeconf0 (target_ulong arg1) |
f1aa6320 TS |
984 | { |
985 | uint32_t mask = 0; | |
986 | uint32_t newval; | |
987 | ||
988 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { | |
989 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) | |
990 | mask |= (0xff << CP0VPEC0_XTC); | |
991 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); | |
992 | } | |
d9bea114 | 993 | newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
f1aa6320 TS |
994 | |
995 | // TODO: TC exclusive handling due to ERL/EXL. | |
996 | ||
997 | env->CP0_VPEConf0 = newval; | |
998 | } | |
999 | ||
d9bea114 | 1000 | void helper_mtc0_vpeconf1 (target_ulong arg1) |
f1aa6320 TS |
1001 | { |
1002 | uint32_t mask = 0; | |
1003 | uint32_t newval; | |
1004 | ||
1005 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
1006 | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | | |
1007 | (0xff << CP0VPEC1_NCP1); | |
d9bea114 | 1008 | newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1009 | |
1010 | /* UDI not implemented. */ | |
1011 | /* CP2 not implemented. */ | |
1012 | ||
1013 | // TODO: Handle FPU (CP1) binding. | |
1014 | ||
1015 | env->CP0_VPEConf1 = newval; | |
1016 | } | |
1017 | ||
d9bea114 | 1018 | void helper_mtc0_yqmask (target_ulong arg1) |
f1aa6320 TS |
1019 | { |
1020 | /* Yield qualifier inputs not implemented. */ | |
1021 | env->CP0_YQMask = 0x00000000; | |
1022 | } | |
1023 | ||
d9bea114 | 1024 | void helper_mtc0_vpeopt (target_ulong arg1) |
f1aa6320 | 1025 | { |
d9bea114 | 1026 | env->CP0_VPEOpt = arg1 & 0x0000ffff; |
f1aa6320 TS |
1027 | } |
1028 | ||
d9bea114 | 1029 | void helper_mtc0_entrylo0 (target_ulong arg1) |
f1aa6320 TS |
1030 | { |
1031 | /* Large physaddr (PABITS) not implemented */ | |
1032 | /* 1k pages not implemented */ | |
d9bea114 | 1033 | env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF; |
f1aa6320 TS |
1034 | } |
1035 | ||
d9bea114 | 1036 | void helper_mtc0_tcstatus (target_ulong arg1) |
f1aa6320 TS |
1037 | { |
1038 | uint32_t mask = env->CP0_TCStatus_rw_bitmask; | |
1039 | uint32_t newval; | |
1040 | ||
d9bea114 | 1041 | newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1042 | |
1043 | // TODO: Sync with CP0_Status. | |
1044 | ||
b5dc7732 | 1045 | env->active_tc.CP0_TCStatus = newval; |
f1aa6320 TS |
1046 | } |
1047 | ||
d9bea114 | 1048 | void helper_mttc0_tcstatus (target_ulong arg1) |
f1aa6320 TS |
1049 | { |
1050 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1051 | ||
1052 | // TODO: Sync with CP0_Status. | |
1053 | ||
b5dc7732 | 1054 | if (other_tc == env->current_tc) |
d9bea114 | 1055 | env->active_tc.CP0_TCStatus = arg1; |
b5dc7732 | 1056 | else |
d9bea114 | 1057 | env->tcs[other_tc].CP0_TCStatus = arg1; |
f1aa6320 TS |
1058 | } |
1059 | ||
d9bea114 | 1060 | void helper_mtc0_tcbind (target_ulong arg1) |
f1aa6320 TS |
1061 | { |
1062 | uint32_t mask = (1 << CP0TCBd_TBE); | |
1063 | uint32_t newval; | |
1064 | ||
1065 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
1066 | mask |= (1 << CP0TCBd_CurVPE); | |
d9bea114 | 1067 | newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
b5dc7732 | 1068 | env->active_tc.CP0_TCBind = newval; |
f1aa6320 TS |
1069 | } |
1070 | ||
d9bea114 | 1071 | void helper_mttc0_tcbind (target_ulong arg1) |
f1aa6320 TS |
1072 | { |
1073 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1074 | uint32_t mask = (1 << CP0TCBd_TBE); | |
1075 | uint32_t newval; | |
1076 | ||
1077 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
1078 | mask |= (1 << CP0TCBd_CurVPE); | |
b5dc7732 | 1079 | if (other_tc == env->current_tc) { |
d9bea114 | 1080 | newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
b5dc7732 TS |
1081 | env->active_tc.CP0_TCBind = newval; |
1082 | } else { | |
d9bea114 | 1083 | newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); |
b5dc7732 TS |
1084 | env->tcs[other_tc].CP0_TCBind = newval; |
1085 | } | |
f1aa6320 TS |
1086 | } |
1087 | ||
d9bea114 | 1088 | void helper_mtc0_tcrestart (target_ulong arg1) |
f1aa6320 | 1089 | { |
d9bea114 | 1090 | env->active_tc.PC = arg1; |
b5dc7732 | 1091 | env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
5499b6ff | 1092 | env->lladdr = 0ULL; |
f1aa6320 TS |
1093 | /* MIPS16 not implemented. */ |
1094 | } | |
1095 | ||
d9bea114 | 1096 | void helper_mttc0_tcrestart (target_ulong arg1) |
f1aa6320 TS |
1097 | { |
1098 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1099 | ||
b5dc7732 | 1100 | if (other_tc == env->current_tc) { |
d9bea114 | 1101 | env->active_tc.PC = arg1; |
b5dc7732 | 1102 | env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
5499b6ff | 1103 | env->lladdr = 0ULL; |
b5dc7732 TS |
1104 | /* MIPS16 not implemented. */ |
1105 | } else { | |
d9bea114 | 1106 | env->tcs[other_tc].PC = arg1; |
b5dc7732 | 1107 | env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
5499b6ff | 1108 | env->lladdr = 0ULL; |
b5dc7732 TS |
1109 | /* MIPS16 not implemented. */ |
1110 | } | |
f1aa6320 TS |
1111 | } |
1112 | ||
d9bea114 | 1113 | void helper_mtc0_tchalt (target_ulong arg1) |
f1aa6320 | 1114 | { |
d9bea114 | 1115 | env->active_tc.CP0_TCHalt = arg1 & 0x1; |
f1aa6320 TS |
1116 | |
1117 | // TODO: Halt TC / Restart (if allocated+active) TC. | |
1118 | } | |
1119 | ||
d9bea114 | 1120 | void helper_mttc0_tchalt (target_ulong arg1) |
f1aa6320 TS |
1121 | { |
1122 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1123 | ||
1124 | // TODO: Halt TC / Restart (if allocated+active) TC. | |
1125 | ||
b5dc7732 | 1126 | if (other_tc == env->current_tc) |
d9bea114 | 1127 | env->active_tc.CP0_TCHalt = arg1; |
b5dc7732 | 1128 | else |
d9bea114 | 1129 | env->tcs[other_tc].CP0_TCHalt = arg1; |
f1aa6320 TS |
1130 | } |
1131 | ||
d9bea114 | 1132 | void helper_mtc0_tccontext (target_ulong arg1) |
f1aa6320 | 1133 | { |
d9bea114 | 1134 | env->active_tc.CP0_TCContext = arg1; |
f1aa6320 TS |
1135 | } |
1136 | ||
d9bea114 | 1137 | void helper_mttc0_tccontext (target_ulong arg1) |
f1aa6320 TS |
1138 | { |
1139 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1140 | ||
b5dc7732 | 1141 | if (other_tc == env->current_tc) |
d9bea114 | 1142 | env->active_tc.CP0_TCContext = arg1; |
b5dc7732 | 1143 | else |
d9bea114 | 1144 | env->tcs[other_tc].CP0_TCContext = arg1; |
f1aa6320 TS |
1145 | } |
1146 | ||
d9bea114 | 1147 | void helper_mtc0_tcschedule (target_ulong arg1) |
f1aa6320 | 1148 | { |
d9bea114 | 1149 | env->active_tc.CP0_TCSchedule = arg1; |
f1aa6320 TS |
1150 | } |
1151 | ||
d9bea114 | 1152 | void helper_mttc0_tcschedule (target_ulong arg1) |
f1aa6320 TS |
1153 | { |
1154 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1155 | ||
b5dc7732 | 1156 | if (other_tc == env->current_tc) |
d9bea114 | 1157 | env->active_tc.CP0_TCSchedule = arg1; |
b5dc7732 | 1158 | else |
d9bea114 | 1159 | env->tcs[other_tc].CP0_TCSchedule = arg1; |
f1aa6320 TS |
1160 | } |
1161 | ||
d9bea114 | 1162 | void helper_mtc0_tcschefback (target_ulong arg1) |
f1aa6320 | 1163 | { |
d9bea114 | 1164 | env->active_tc.CP0_TCScheFBack = arg1; |
f1aa6320 TS |
1165 | } |
1166 | ||
d9bea114 | 1167 | void helper_mttc0_tcschefback (target_ulong arg1) |
f1aa6320 TS |
1168 | { |
1169 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1170 | ||
b5dc7732 | 1171 | if (other_tc == env->current_tc) |
d9bea114 | 1172 | env->active_tc.CP0_TCScheFBack = arg1; |
b5dc7732 | 1173 | else |
d9bea114 | 1174 | env->tcs[other_tc].CP0_TCScheFBack = arg1; |
f1aa6320 TS |
1175 | } |
1176 | ||
d9bea114 | 1177 | void helper_mtc0_entrylo1 (target_ulong arg1) |
f1aa6320 TS |
1178 | { |
1179 | /* Large physaddr (PABITS) not implemented */ | |
1180 | /* 1k pages not implemented */ | |
d9bea114 | 1181 | env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF; |
f1aa6320 TS |
1182 | } |
1183 | ||
d9bea114 | 1184 | void helper_mtc0_context (target_ulong arg1) |
f1aa6320 | 1185 | { |
d9bea114 | 1186 | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); |
f1aa6320 TS |
1187 | } |
1188 | ||
d9bea114 | 1189 | void helper_mtc0_pagemask (target_ulong arg1) |
f1aa6320 TS |
1190 | { |
1191 | /* 1k pages not implemented */ | |
d9bea114 | 1192 | env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
f1aa6320 TS |
1193 | } |
1194 | ||
d9bea114 | 1195 | void helper_mtc0_pagegrain (target_ulong arg1) |
f1aa6320 TS |
1196 | { |
1197 | /* SmartMIPS not implemented */ | |
1198 | /* Large physaddr (PABITS) not implemented */ | |
1199 | /* 1k pages not implemented */ | |
1200 | env->CP0_PageGrain = 0; | |
1201 | } | |
1202 | ||
d9bea114 | 1203 | void helper_mtc0_wired (target_ulong arg1) |
f1aa6320 | 1204 | { |
d9bea114 | 1205 | env->CP0_Wired = arg1 % env->tlb->nb_tlb; |
f1aa6320 TS |
1206 | } |
1207 | ||
d9bea114 | 1208 | void helper_mtc0_srsconf0 (target_ulong arg1) |
f1aa6320 | 1209 | { |
d9bea114 | 1210 | env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; |
f1aa6320 TS |
1211 | } |
1212 | ||
d9bea114 | 1213 | void helper_mtc0_srsconf1 (target_ulong arg1) |
f1aa6320 | 1214 | { |
d9bea114 | 1215 | env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; |
f1aa6320 TS |
1216 | } |
1217 | ||
d9bea114 | 1218 | void helper_mtc0_srsconf2 (target_ulong arg1) |
f1aa6320 | 1219 | { |
d9bea114 | 1220 | env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; |
f1aa6320 TS |
1221 | } |
1222 | ||
d9bea114 | 1223 | void helper_mtc0_srsconf3 (target_ulong arg1) |
f1aa6320 | 1224 | { |
d9bea114 | 1225 | env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; |
f1aa6320 TS |
1226 | } |
1227 | ||
d9bea114 | 1228 | void helper_mtc0_srsconf4 (target_ulong arg1) |
f1aa6320 | 1229 | { |
d9bea114 | 1230 | env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; |
f1aa6320 TS |
1231 | } |
1232 | ||
d9bea114 | 1233 | void helper_mtc0_hwrena (target_ulong arg1) |
f1aa6320 | 1234 | { |
d9bea114 | 1235 | env->CP0_HWREna = arg1 & 0x0000000F; |
f1aa6320 TS |
1236 | } |
1237 | ||
d9bea114 | 1238 | void helper_mtc0_count (target_ulong arg1) |
f1aa6320 | 1239 | { |
d9bea114 | 1240 | cpu_mips_store_count(env, arg1); |
f1aa6320 TS |
1241 | } |
1242 | ||
d9bea114 | 1243 | void helper_mtc0_entryhi (target_ulong arg1) |
f1aa6320 TS |
1244 | { |
1245 | target_ulong old, val; | |
1246 | ||
1247 | /* 1k pages not implemented */ | |
d9bea114 | 1248 | val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
f1aa6320 TS |
1249 | #if defined(TARGET_MIPS64) |
1250 | val &= env->SEGMask; | |
1251 | #endif | |
1252 | old = env->CP0_EntryHi; | |
1253 | env->CP0_EntryHi = val; | |
1254 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { | |
b5dc7732 TS |
1255 | uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff; |
1256 | env->active_tc.CP0_TCStatus = tcst | (val & 0xff); | |
f1aa6320 TS |
1257 | } |
1258 | /* If the ASID changes, flush qemu's TLB. */ | |
1259 | if ((old & 0xFF) != (val & 0xFF)) | |
1260 | cpu_mips_tlb_flush(env, 1); | |
1261 | } | |
1262 | ||
d9bea114 | 1263 | void helper_mttc0_entryhi(target_ulong arg1) |
f1aa6320 TS |
1264 | { |
1265 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 | 1266 | int32_t tcstatus; |
f1aa6320 | 1267 | |
d9bea114 | 1268 | env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff); |
b5dc7732 | 1269 | if (other_tc == env->current_tc) { |
d9bea114 | 1270 | tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff); |
b5dc7732 TS |
1271 | env->active_tc.CP0_TCStatus = tcstatus; |
1272 | } else { | |
d9bea114 | 1273 | tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff); |
b5dc7732 TS |
1274 | env->tcs[other_tc].CP0_TCStatus = tcstatus; |
1275 | } | |
f1aa6320 TS |
1276 | } |
1277 | ||
d9bea114 | 1278 | void helper_mtc0_compare (target_ulong arg1) |
f1aa6320 | 1279 | { |
d9bea114 | 1280 | cpu_mips_store_compare(env, arg1); |
f1aa6320 TS |
1281 | } |
1282 | ||
d9bea114 | 1283 | void helper_mtc0_status (target_ulong arg1) |
f1aa6320 TS |
1284 | { |
1285 | uint32_t val, old; | |
1286 | uint32_t mask = env->CP0_Status_rw_bitmask; | |
1287 | ||
d9bea114 | 1288 | val = arg1 & mask; |
f1aa6320 TS |
1289 | old = env->CP0_Status; |
1290 | env->CP0_Status = (env->CP0_Status & ~mask) | val; | |
1291 | compute_hflags(env); | |
c01fccd2 AJ |
1292 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
1293 | qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x", | |
1294 | old, old & env->CP0_Cause & CP0Ca_IP_mask, | |
1295 | val, val & env->CP0_Cause & CP0Ca_IP_mask, | |
1296 | env->CP0_Cause); | |
1297 | switch (env->hflags & MIPS_HFLAG_KSU) { | |
1298 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; | |
1299 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; | |
1300 | case MIPS_HFLAG_KM: qemu_log("\n"); break; | |
1301 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; | |
31e3104f | 1302 | } |
c01fccd2 | 1303 | } |
f1aa6320 TS |
1304 | } |
1305 | ||
d9bea114 | 1306 | void helper_mttc0_status(target_ulong arg1) |
f1aa6320 TS |
1307 | { |
1308 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 | 1309 | int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus; |
f1aa6320 | 1310 | |
d9bea114 AJ |
1311 | env->CP0_Status = arg1 & ~0xf1000018; |
1312 | tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0)); | |
1313 | tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); | |
1314 | tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); | |
b5dc7732 TS |
1315 | if (other_tc == env->current_tc) |
1316 | env->active_tc.CP0_TCStatus = tcstatus; | |
1317 | else | |
1318 | env->tcs[other_tc].CP0_TCStatus = tcstatus; | |
f1aa6320 TS |
1319 | } |
1320 | ||
d9bea114 | 1321 | void helper_mtc0_intctl (target_ulong arg1) |
f1aa6320 TS |
1322 | { |
1323 | /* vectored interrupts not implemented, no performance counters. */ | |
d9bea114 | 1324 | env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0); |
f1aa6320 TS |
1325 | } |
1326 | ||
d9bea114 | 1327 | void helper_mtc0_srsctl (target_ulong arg1) |
f1aa6320 TS |
1328 | { |
1329 | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); | |
d9bea114 | 1330 | env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1331 | } |
1332 | ||
d9bea114 | 1333 | void helper_mtc0_cause (target_ulong arg1) |
f1aa6320 TS |
1334 | { |
1335 | uint32_t mask = 0x00C00300; | |
1336 | uint32_t old = env->CP0_Cause; | |
5dc5d9f0 | 1337 | int i; |
f1aa6320 TS |
1338 | |
1339 | if (env->insn_flags & ISA_MIPS32R2) | |
1340 | mask |= 1 << CP0Ca_DC; | |
1341 | ||
d9bea114 | 1342 | env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1343 | |
1344 | if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { | |
1345 | if (env->CP0_Cause & (1 << CP0Ca_DC)) | |
1346 | cpu_mips_stop_count(env); | |
1347 | else | |
1348 | cpu_mips_start_count(env); | |
1349 | } | |
5dc5d9f0 AJ |
1350 | |
1351 | /* Set/reset software interrupts */ | |
1352 | for (i = 0 ; i < 2 ; i++) { | |
1353 | if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { | |
1354 | cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); | |
1355 | } | |
1356 | } | |
f1aa6320 TS |
1357 | } |
1358 | ||
d9bea114 | 1359 | void helper_mtc0_ebase (target_ulong arg1) |
f1aa6320 TS |
1360 | { |
1361 | /* vectored interrupts not implemented */ | |
671b0f36 | 1362 | env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
f1aa6320 TS |
1363 | } |
1364 | ||
d9bea114 | 1365 | void helper_mtc0_config0 (target_ulong arg1) |
f1aa6320 | 1366 | { |
d9bea114 | 1367 | env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); |
f1aa6320 TS |
1368 | } |
1369 | ||
d9bea114 | 1370 | void helper_mtc0_config2 (target_ulong arg1) |
f1aa6320 TS |
1371 | { |
1372 | /* tertiary/secondary caches not implemented */ | |
1373 | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); | |
1374 | } | |
1375 | ||
2a6e32dd AJ |
1376 | void helper_mtc0_lladdr (target_ulong arg1) |
1377 | { | |
1378 | target_long mask = env->CP0_LLAddr_rw_bitmask; | |
1379 | arg1 = arg1 << env->CP0_LLAddr_shift; | |
1380 | env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); | |
1381 | } | |
1382 | ||
d9bea114 | 1383 | void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1384 | { |
1385 | /* Watch exceptions for instructions, data loads, data stores | |
1386 | not implemented. */ | |
d9bea114 | 1387 | env->CP0_WatchLo[sel] = (arg1 & ~0x7); |
f1aa6320 TS |
1388 | } |
1389 | ||
d9bea114 | 1390 | void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel) |
f1aa6320 | 1391 | { |
d9bea114 AJ |
1392 | env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); |
1393 | env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); | |
f1aa6320 TS |
1394 | } |
1395 | ||
d9bea114 | 1396 | void helper_mtc0_xcontext (target_ulong arg1) |
f1aa6320 TS |
1397 | { |
1398 | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; | |
d9bea114 | 1399 | env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); |
f1aa6320 TS |
1400 | } |
1401 | ||
d9bea114 | 1402 | void helper_mtc0_framemask (target_ulong arg1) |
f1aa6320 | 1403 | { |
d9bea114 | 1404 | env->CP0_Framemask = arg1; /* XXX */ |
f1aa6320 TS |
1405 | } |
1406 | ||
d9bea114 | 1407 | void helper_mtc0_debug (target_ulong arg1) |
f1aa6320 | 1408 | { |
d9bea114 AJ |
1409 | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); |
1410 | if (arg1 & (1 << CP0DB_DM)) | |
f1aa6320 TS |
1411 | env->hflags |= MIPS_HFLAG_DM; |
1412 | else | |
1413 | env->hflags &= ~MIPS_HFLAG_DM; | |
1414 | } | |
1415 | ||
d9bea114 | 1416 | void helper_mttc0_debug(target_ulong arg1) |
f1aa6320 TS |
1417 | { |
1418 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
d9bea114 | 1419 | uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
f1aa6320 TS |
1420 | |
1421 | /* XXX: Might be wrong, check with EJTAG spec. */ | |
b5dc7732 TS |
1422 | if (other_tc == env->current_tc) |
1423 | env->active_tc.CP0_Debug_tcstatus = val; | |
1424 | else | |
1425 | env->tcs[other_tc].CP0_Debug_tcstatus = val; | |
f1aa6320 | 1426 | env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
d9bea114 | 1427 | (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
f1aa6320 TS |
1428 | } |
1429 | ||
d9bea114 | 1430 | void helper_mtc0_performance0 (target_ulong arg1) |
f1aa6320 | 1431 | { |
d9bea114 | 1432 | env->CP0_Performance0 = arg1 & 0x000007ff; |
f1aa6320 TS |
1433 | } |
1434 | ||
d9bea114 | 1435 | void helper_mtc0_taglo (target_ulong arg1) |
f1aa6320 | 1436 | { |
d9bea114 | 1437 | env->CP0_TagLo = arg1 & 0xFFFFFCF6; |
f1aa6320 TS |
1438 | } |
1439 | ||
d9bea114 | 1440 | void helper_mtc0_datalo (target_ulong arg1) |
f1aa6320 | 1441 | { |
d9bea114 | 1442 | env->CP0_DataLo = arg1; /* XXX */ |
f1aa6320 TS |
1443 | } |
1444 | ||
d9bea114 | 1445 | void helper_mtc0_taghi (target_ulong arg1) |
f1aa6320 | 1446 | { |
d9bea114 | 1447 | env->CP0_TagHi = arg1; /* XXX */ |
f1aa6320 TS |
1448 | } |
1449 | ||
d9bea114 | 1450 | void helper_mtc0_datahi (target_ulong arg1) |
f1aa6320 | 1451 | { |
d9bea114 | 1452 | env->CP0_DataHi = arg1; /* XXX */ |
f1aa6320 TS |
1453 | } |
1454 | ||
f1aa6320 | 1455 | /* MIPS MT functions */ |
c01fccd2 | 1456 | target_ulong helper_mftgpr(uint32_t sel) |
f1aa6320 TS |
1457 | { |
1458 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1459 | ||
b5dc7732 TS |
1460 | if (other_tc == env->current_tc) |
1461 | return env->active_tc.gpr[sel]; | |
1462 | else | |
1463 | return env->tcs[other_tc].gpr[sel]; | |
f1aa6320 TS |
1464 | } |
1465 | ||
c01fccd2 | 1466 | target_ulong helper_mftlo(uint32_t sel) |
f1aa6320 TS |
1467 | { |
1468 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1469 | ||
b5dc7732 TS |
1470 | if (other_tc == env->current_tc) |
1471 | return env->active_tc.LO[sel]; | |
1472 | else | |
1473 | return env->tcs[other_tc].LO[sel]; | |
f1aa6320 TS |
1474 | } |
1475 | ||
c01fccd2 | 1476 | target_ulong helper_mfthi(uint32_t sel) |
f1aa6320 TS |
1477 | { |
1478 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1479 | ||
b5dc7732 TS |
1480 | if (other_tc == env->current_tc) |
1481 | return env->active_tc.HI[sel]; | |
1482 | else | |
1483 | return env->tcs[other_tc].HI[sel]; | |
f1aa6320 TS |
1484 | } |
1485 | ||
c01fccd2 | 1486 | target_ulong helper_mftacx(uint32_t sel) |
f1aa6320 TS |
1487 | { |
1488 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1489 | ||
b5dc7732 TS |
1490 | if (other_tc == env->current_tc) |
1491 | return env->active_tc.ACX[sel]; | |
1492 | else | |
1493 | return env->tcs[other_tc].ACX[sel]; | |
f1aa6320 TS |
1494 | } |
1495 | ||
c01fccd2 | 1496 | target_ulong helper_mftdsp(void) |
f1aa6320 TS |
1497 | { |
1498 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1499 | ||
b5dc7732 TS |
1500 | if (other_tc == env->current_tc) |
1501 | return env->active_tc.DSPControl; | |
1502 | else | |
1503 | return env->tcs[other_tc].DSPControl; | |
f1aa6320 | 1504 | } |
6af0bf9c | 1505 | |
d9bea114 | 1506 | void helper_mttgpr(target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1507 | { |
1508 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1509 | ||
b5dc7732 | 1510 | if (other_tc == env->current_tc) |
d9bea114 | 1511 | env->active_tc.gpr[sel] = arg1; |
b5dc7732 | 1512 | else |
d9bea114 | 1513 | env->tcs[other_tc].gpr[sel] = arg1; |
f1aa6320 TS |
1514 | } |
1515 | ||
d9bea114 | 1516 | void helper_mttlo(target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1517 | { |
1518 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1519 | ||
b5dc7732 | 1520 | if (other_tc == env->current_tc) |
d9bea114 | 1521 | env->active_tc.LO[sel] = arg1; |
b5dc7732 | 1522 | else |
d9bea114 | 1523 | env->tcs[other_tc].LO[sel] = arg1; |
f1aa6320 TS |
1524 | } |
1525 | ||
d9bea114 | 1526 | void helper_mtthi(target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1527 | { |
1528 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1529 | ||
b5dc7732 | 1530 | if (other_tc == env->current_tc) |
d9bea114 | 1531 | env->active_tc.HI[sel] = arg1; |
b5dc7732 | 1532 | else |
d9bea114 | 1533 | env->tcs[other_tc].HI[sel] = arg1; |
f1aa6320 TS |
1534 | } |
1535 | ||
d9bea114 | 1536 | void helper_mttacx(target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1537 | { |
1538 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1539 | ||
b5dc7732 | 1540 | if (other_tc == env->current_tc) |
d9bea114 | 1541 | env->active_tc.ACX[sel] = arg1; |
b5dc7732 | 1542 | else |
d9bea114 | 1543 | env->tcs[other_tc].ACX[sel] = arg1; |
f1aa6320 TS |
1544 | } |
1545 | ||
d9bea114 | 1546 | void helper_mttdsp(target_ulong arg1) |
f1aa6320 TS |
1547 | { |
1548 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1549 | ||
b5dc7732 | 1550 | if (other_tc == env->current_tc) |
d9bea114 | 1551 | env->active_tc.DSPControl = arg1; |
b5dc7732 | 1552 | else |
d9bea114 | 1553 | env->tcs[other_tc].DSPControl = arg1; |
f1aa6320 TS |
1554 | } |
1555 | ||
1556 | /* MIPS MT functions */ | |
9ed5726c | 1557 | target_ulong helper_dmt(void) |
f1aa6320 TS |
1558 | { |
1559 | // TODO | |
9ed5726c | 1560 | return 0; |
f1aa6320 TS |
1561 | } |
1562 | ||
9ed5726c | 1563 | target_ulong helper_emt(void) |
f1aa6320 TS |
1564 | { |
1565 | // TODO | |
9ed5726c | 1566 | return 0; |
f1aa6320 TS |
1567 | } |
1568 | ||
9ed5726c | 1569 | target_ulong helper_dvpe(void) |
f1aa6320 TS |
1570 | { |
1571 | // TODO | |
9ed5726c | 1572 | return 0; |
f1aa6320 TS |
1573 | } |
1574 | ||
9ed5726c | 1575 | target_ulong helper_evpe(void) |
f1aa6320 TS |
1576 | { |
1577 | // TODO | |
9ed5726c | 1578 | return 0; |
f1aa6320 | 1579 | } |
f9480ffc | 1580 | #endif /* !CONFIG_USER_ONLY */ |
f1aa6320 | 1581 | |
d9bea114 | 1582 | void helper_fork(target_ulong arg1, target_ulong arg2) |
f1aa6320 | 1583 | { |
d9bea114 AJ |
1584 | // arg1 = rt, arg2 = rs |
1585 | arg1 = 0; | |
f1aa6320 TS |
1586 | // TODO: store to TC register |
1587 | } | |
1588 | ||
1c7242da | 1589 | target_ulong helper_yield(target_ulong arg) |
f1aa6320 | 1590 | { |
1c7242da BS |
1591 | target_long arg1 = arg; |
1592 | ||
d9bea114 | 1593 | if (arg1 < 0) { |
f1aa6320 | 1594 | /* No scheduling policy implemented. */ |
d9bea114 | 1595 | if (arg1 != -2) { |
f1aa6320 | 1596 | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
b5dc7732 | 1597 | env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { |
f1aa6320 TS |
1598 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
1599 | env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; | |
c01fccd2 | 1600 | helper_raise_exception(EXCP_THREAD); |
f1aa6320 TS |
1601 | } |
1602 | } | |
d9bea114 | 1603 | } else if (arg1 == 0) { |
6958549d | 1604 | if (0 /* TODO: TC underflow */) { |
f1aa6320 | 1605 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
c01fccd2 | 1606 | helper_raise_exception(EXCP_THREAD); |
f1aa6320 TS |
1607 | } else { |
1608 | // TODO: Deallocate TC | |
1609 | } | |
d9bea114 | 1610 | } else if (arg1 > 0) { |
f1aa6320 TS |
1611 | /* Yield qualifier inputs not implemented. */ |
1612 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); | |
1613 | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; | |
c01fccd2 | 1614 | helper_raise_exception(EXCP_THREAD); |
f1aa6320 | 1615 | } |
be24bb4f | 1616 | return env->CP0_YQMask; |
f1aa6320 TS |
1617 | } |
1618 | ||
f1aa6320 | 1619 | #ifndef CONFIG_USER_ONLY |
6af0bf9c | 1620 | /* TLB management */ |
83dae095 | 1621 | static void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
814b9a47 TS |
1622 | { |
1623 | /* Flush qemu's TLB and discard all shadowed entries. */ | |
1624 | tlb_flush (env, flush_global); | |
ead9360e | 1625 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
814b9a47 TS |
1626 | } |
1627 | ||
29929e34 | 1628 | static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
814b9a47 TS |
1629 | { |
1630 | /* Discard entries from env->tlb[first] onwards. */ | |
ead9360e TS |
1631 | while (env->tlb->tlb_in_use > first) { |
1632 | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); | |
814b9a47 TS |
1633 | } |
1634 | } | |
1635 | ||
29929e34 | 1636 | static void r4k_fill_tlb (int idx) |
6af0bf9c | 1637 | { |
c227f099 | 1638 | r4k_tlb_t *tlb; |
6af0bf9c FB |
1639 | |
1640 | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ | |
ead9360e | 1641 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 1642 | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
d26bc211 | 1643 | #if defined(TARGET_MIPS64) |
e034e2c3 | 1644 | tlb->VPN &= env->SEGMask; |
100ce988 | 1645 | #endif |
98c1b82b | 1646 | tlb->ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 1647 | tlb->PageMask = env->CP0_PageMask; |
6af0bf9c | 1648 | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
98c1b82b PB |
1649 | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
1650 | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; | |
1651 | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; | |
6af0bf9c | 1652 | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
98c1b82b PB |
1653 | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
1654 | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; | |
1655 | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; | |
6af0bf9c FB |
1656 | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
1657 | } | |
1658 | ||
c01fccd2 | 1659 | void r4k_helper_tlbwi (void) |
6af0bf9c | 1660 | { |
bbc0d79c AJ |
1661 | int idx; |
1662 | ||
1663 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; | |
1664 | ||
814b9a47 TS |
1665 | /* Discard cached TLB entries. We could avoid doing this if the |
1666 | tlbwi is just upgrading access permissions on the current entry; | |
1667 | that might be a further win. */ | |
ead9360e | 1668 | r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
814b9a47 | 1669 | |
bbc0d79c AJ |
1670 | r4k_invalidate_tlb(env, idx, 0); |
1671 | r4k_fill_tlb(idx); | |
6af0bf9c FB |
1672 | } |
1673 | ||
c01fccd2 | 1674 | void r4k_helper_tlbwr (void) |
6af0bf9c FB |
1675 | { |
1676 | int r = cpu_mips_get_random(env); | |
1677 | ||
29929e34 TS |
1678 | r4k_invalidate_tlb(env, r, 1); |
1679 | r4k_fill_tlb(r); | |
6af0bf9c FB |
1680 | } |
1681 | ||
c01fccd2 | 1682 | void r4k_helper_tlbp (void) |
6af0bf9c | 1683 | { |
c227f099 | 1684 | r4k_tlb_t *tlb; |
f2e9ebef | 1685 | target_ulong mask; |
6af0bf9c | 1686 | target_ulong tag; |
f2e9ebef | 1687 | target_ulong VPN; |
6af0bf9c FB |
1688 | uint8_t ASID; |
1689 | int i; | |
1690 | ||
3d9fb9fe | 1691 | ASID = env->CP0_EntryHi & 0xFF; |
ead9360e TS |
1692 | for (i = 0; i < env->tlb->nb_tlb; i++) { |
1693 | tlb = &env->tlb->mmu.r4k.tlb[i]; | |
f2e9ebef TS |
1694 | /* 1k pages are not supported. */ |
1695 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
1696 | tag = env->CP0_EntryHi & ~mask; | |
1697 | VPN = tlb->VPN & ~mask; | |
6af0bf9c | 1698 | /* Check ASID, virtual page number & size */ |
f2e9ebef | 1699 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
6af0bf9c | 1700 | /* TLB match */ |
9c2149c8 | 1701 | env->CP0_Index = i; |
6af0bf9c FB |
1702 | break; |
1703 | } | |
1704 | } | |
ead9360e | 1705 | if (i == env->tlb->nb_tlb) { |
814b9a47 | 1706 | /* No match. Discard any shadow entries, if any of them match. */ |
ead9360e | 1707 | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { |
6958549d AJ |
1708 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
1709 | /* 1k pages are not supported. */ | |
1710 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
1711 | tag = env->CP0_EntryHi & ~mask; | |
1712 | VPN = tlb->VPN & ~mask; | |
1713 | /* Check ASID, virtual page number & size */ | |
1714 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { | |
29929e34 | 1715 | r4k_mips_tlb_flush_extra (env, i); |
6958549d AJ |
1716 | break; |
1717 | } | |
1718 | } | |
814b9a47 | 1719 | |
9c2149c8 | 1720 | env->CP0_Index |= 0x80000000; |
6af0bf9c FB |
1721 | } |
1722 | } | |
1723 | ||
c01fccd2 | 1724 | void r4k_helper_tlbr (void) |
6af0bf9c | 1725 | { |
c227f099 | 1726 | r4k_tlb_t *tlb; |
09c56b84 | 1727 | uint8_t ASID; |
bbc0d79c | 1728 | int idx; |
6af0bf9c | 1729 | |
09c56b84 | 1730 | ASID = env->CP0_EntryHi & 0xFF; |
bbc0d79c AJ |
1731 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
1732 | tlb = &env->tlb->mmu.r4k.tlb[idx]; | |
4ad40f36 FB |
1733 | |
1734 | /* If this will change the current ASID, flush qemu's TLB. */ | |
814b9a47 TS |
1735 | if (ASID != tlb->ASID) |
1736 | cpu_mips_tlb_flush (env, 1); | |
1737 | ||
ead9360e | 1738 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
4ad40f36 | 1739 | |
6af0bf9c | 1740 | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
3b1c8be4 | 1741 | env->CP0_PageMask = tlb->PageMask; |
7495fd0f TS |
1742 | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
1743 | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); | |
1744 | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | | |
1745 | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); | |
6af0bf9c | 1746 | } |
6af0bf9c | 1747 | |
c01fccd2 | 1748 | void helper_tlbwi(void) |
a7812ae4 | 1749 | { |
c01fccd2 | 1750 | env->tlb->helper_tlbwi(); |
a7812ae4 PB |
1751 | } |
1752 | ||
c01fccd2 | 1753 | void helper_tlbwr(void) |
a7812ae4 | 1754 | { |
c01fccd2 | 1755 | env->tlb->helper_tlbwr(); |
a7812ae4 PB |
1756 | } |
1757 | ||
c01fccd2 | 1758 | void helper_tlbp(void) |
a7812ae4 | 1759 | { |
c01fccd2 | 1760 | env->tlb->helper_tlbp(); |
a7812ae4 PB |
1761 | } |
1762 | ||
c01fccd2 | 1763 | void helper_tlbr(void) |
a7812ae4 | 1764 | { |
c01fccd2 | 1765 | env->tlb->helper_tlbr(); |
a7812ae4 PB |
1766 | } |
1767 | ||
2b0233ab | 1768 | /* Specials */ |
c01fccd2 | 1769 | target_ulong helper_di (void) |
2b0233ab | 1770 | { |
2796188e TS |
1771 | target_ulong t0 = env->CP0_Status; |
1772 | ||
be24bb4f | 1773 | env->CP0_Status = t0 & ~(1 << CP0St_IE); |
be24bb4f | 1774 | return t0; |
2b0233ab TS |
1775 | } |
1776 | ||
c01fccd2 | 1777 | target_ulong helper_ei (void) |
2b0233ab | 1778 | { |
2796188e TS |
1779 | target_ulong t0 = env->CP0_Status; |
1780 | ||
be24bb4f | 1781 | env->CP0_Status = t0 | (1 << CP0St_IE); |
be24bb4f | 1782 | return t0; |
2b0233ab TS |
1783 | } |
1784 | ||
cd5158ea | 1785 | static void debug_pre_eret (void) |
6af0bf9c | 1786 | { |
8fec2b8c | 1787 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
93fcfe39 AL |
1788 | qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1789 | env->active_tc.PC, env->CP0_EPC); | |
1790 | if (env->CP0_Status & (1 << CP0St_ERL)) | |
1791 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); | |
1792 | if (env->hflags & MIPS_HFLAG_DM) | |
1793 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); | |
1794 | qemu_log("\n"); | |
1795 | } | |
f41c52f1 TS |
1796 | } |
1797 | ||
cd5158ea | 1798 | static void debug_post_eret (void) |
f41c52f1 | 1799 | { |
8fec2b8c | 1800 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
93fcfe39 AL |
1801 | qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1802 | env->active_tc.PC, env->CP0_EPC); | |
1803 | if (env->CP0_Status & (1 << CP0St_ERL)) | |
1804 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); | |
1805 | if (env->hflags & MIPS_HFLAG_DM) | |
1806 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); | |
1807 | switch (env->hflags & MIPS_HFLAG_KSU) { | |
1808 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; | |
1809 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; | |
1810 | case MIPS_HFLAG_KM: qemu_log("\n"); break; | |
1811 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; | |
1812 | } | |
623a930e | 1813 | } |
6af0bf9c FB |
1814 | } |
1815 | ||
32188a03 NF |
1816 | static void set_pc (target_ulong error_pc) |
1817 | { | |
1818 | env->active_tc.PC = error_pc & ~(target_ulong)1; | |
1819 | if (error_pc & 1) { | |
1820 | env->hflags |= MIPS_HFLAG_M16; | |
1821 | } else { | |
1822 | env->hflags &= ~(MIPS_HFLAG_M16); | |
1823 | } | |
1824 | } | |
1825 | ||
c01fccd2 | 1826 | void helper_eret (void) |
2b0233ab | 1827 | { |
93fcfe39 | 1828 | debug_pre_eret(); |
2b0233ab | 1829 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
32188a03 | 1830 | set_pc(env->CP0_ErrorEPC); |
2b0233ab TS |
1831 | env->CP0_Status &= ~(1 << CP0St_ERL); |
1832 | } else { | |
32188a03 | 1833 | set_pc(env->CP0_EPC); |
2b0233ab TS |
1834 | env->CP0_Status &= ~(1 << CP0St_EXL); |
1835 | } | |
1836 | compute_hflags(env); | |
93fcfe39 | 1837 | debug_post_eret(); |
5499b6ff | 1838 | env->lladdr = 1; |
2b0233ab TS |
1839 | } |
1840 | ||
c01fccd2 | 1841 | void helper_deret (void) |
2b0233ab | 1842 | { |
93fcfe39 | 1843 | debug_pre_eret(); |
32188a03 NF |
1844 | set_pc(env->CP0_DEPC); |
1845 | ||
2b0233ab TS |
1846 | env->hflags &= MIPS_HFLAG_DM; |
1847 | compute_hflags(env); | |
93fcfe39 | 1848 | debug_post_eret(); |
5499b6ff | 1849 | env->lladdr = 1; |
2b0233ab | 1850 | } |
0eaef5aa | 1851 | #endif /* !CONFIG_USER_ONLY */ |
2b0233ab | 1852 | |
c01fccd2 | 1853 | target_ulong helper_rdhwr_cpunum(void) |
2b0233ab TS |
1854 | { |
1855 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
1856 | (env->CP0_HWREna & (1 << 0))) | |
2796188e | 1857 | return env->CP0_EBase & 0x3ff; |
2b0233ab | 1858 | else |
c01fccd2 | 1859 | helper_raise_exception(EXCP_RI); |
be24bb4f | 1860 | |
2796188e | 1861 | return 0; |
2b0233ab TS |
1862 | } |
1863 | ||
c01fccd2 | 1864 | target_ulong helper_rdhwr_synci_step(void) |
2b0233ab TS |
1865 | { |
1866 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
1867 | (env->CP0_HWREna & (1 << 1))) | |
2796188e | 1868 | return env->SYNCI_Step; |
2b0233ab | 1869 | else |
c01fccd2 | 1870 | helper_raise_exception(EXCP_RI); |
be24bb4f | 1871 | |
2796188e | 1872 | return 0; |
2b0233ab TS |
1873 | } |
1874 | ||
c01fccd2 | 1875 | target_ulong helper_rdhwr_cc(void) |
2b0233ab TS |
1876 | { |
1877 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
1878 | (env->CP0_HWREna & (1 << 2))) | |
2796188e | 1879 | return env->CP0_Count; |
2b0233ab | 1880 | else |
c01fccd2 | 1881 | helper_raise_exception(EXCP_RI); |
be24bb4f | 1882 | |
2796188e | 1883 | return 0; |
2b0233ab TS |
1884 | } |
1885 | ||
c01fccd2 | 1886 | target_ulong helper_rdhwr_ccres(void) |
2b0233ab TS |
1887 | { |
1888 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
1889 | (env->CP0_HWREna & (1 << 3))) | |
2796188e | 1890 | return env->CCRes; |
2b0233ab | 1891 | else |
c01fccd2 | 1892 | helper_raise_exception(EXCP_RI); |
be24bb4f | 1893 | |
2796188e | 1894 | return 0; |
2b0233ab TS |
1895 | } |
1896 | ||
c01fccd2 | 1897 | void helper_pmon (int function) |
6af0bf9c FB |
1898 | { |
1899 | function /= 2; | |
1900 | switch (function) { | |
1901 | case 2: /* TODO: char inbyte(int waitflag); */ | |
b5dc7732 TS |
1902 | if (env->active_tc.gpr[4] == 0) |
1903 | env->active_tc.gpr[2] = -1; | |
6af0bf9c FB |
1904 | /* Fall through */ |
1905 | case 11: /* TODO: char inbyte (void); */ | |
b5dc7732 | 1906 | env->active_tc.gpr[2] = -1; |
6af0bf9c FB |
1907 | break; |
1908 | case 3: | |
1909 | case 12: | |
b5dc7732 | 1910 | printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); |
6af0bf9c FB |
1911 | break; |
1912 | case 17: | |
1913 | break; | |
1914 | case 158: | |
1915 | { | |
b5dc7732 | 1916 | unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4]; |
6af0bf9c FB |
1917 | printf("%s", fmt); |
1918 | } | |
1919 | break; | |
1920 | } | |
1921 | } | |
e37e863f | 1922 | |
c01fccd2 | 1923 | void helper_wait (void) |
08ba7963 TS |
1924 | { |
1925 | env->halted = 1; | |
c01fccd2 | 1926 | helper_raise_exception(EXCP_HLT); |
08ba7963 TS |
1927 | } |
1928 | ||
5fafdf24 | 1929 | #if !defined(CONFIG_USER_ONLY) |
e37e863f | 1930 | |
4ad40f36 FB |
1931 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
1932 | ||
e37e863f | 1933 | #define MMUSUFFIX _mmu |
4ad40f36 | 1934 | #define ALIGNED_ONLY |
e37e863f FB |
1935 | |
1936 | #define SHIFT 0 | |
1937 | #include "softmmu_template.h" | |
1938 | ||
1939 | #define SHIFT 1 | |
1940 | #include "softmmu_template.h" | |
1941 | ||
1942 | #define SHIFT 2 | |
1943 | #include "softmmu_template.h" | |
1944 | ||
1945 | #define SHIFT 3 | |
1946 | #include "softmmu_template.h" | |
1947 | ||
4ad40f36 FB |
1948 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
1949 | { | |
1950 | env->CP0_BadVAddr = addr; | |
1951 | do_restore_state (retaddr); | |
c01fccd2 | 1952 | helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); |
4ad40f36 FB |
1953 | } |
1954 | ||
6ebbf390 | 1955 | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
e37e863f FB |
1956 | { |
1957 | TranslationBlock *tb; | |
1958 | CPUState *saved_env; | |
1959 | unsigned long pc; | |
1960 | int ret; | |
1961 | ||
1962 | /* XXX: hack to restore env in all cases, even if not called from | |
1963 | generated code */ | |
1964 | saved_env = env; | |
1965 | env = cpu_single_env; | |
6ebbf390 | 1966 | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); |
e37e863f FB |
1967 | if (ret) { |
1968 | if (retaddr) { | |
1969 | /* now we have a real cpu fault */ | |
1970 | pc = (unsigned long)retaddr; | |
1971 | tb = tb_find_pc(pc); | |
1972 | if (tb) { | |
1973 | /* the PC is inside the translated code. It means that we have | |
1974 | a virtual CPU fault */ | |
1975 | cpu_restore_state(tb, env, pc, NULL); | |
1976 | } | |
1977 | } | |
c01fccd2 | 1978 | helper_raise_exception_err(env->exception_index, env->error_code); |
e37e863f FB |
1979 | } |
1980 | env = saved_env; | |
1981 | } | |
1982 | ||
c227f099 | 1983 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
e18231a3 | 1984 | int unused, int size) |
647de6ca TS |
1985 | { |
1986 | if (is_exec) | |
c01fccd2 | 1987 | helper_raise_exception(EXCP_IBE); |
647de6ca | 1988 | else |
c01fccd2 | 1989 | helper_raise_exception(EXCP_DBE); |
647de6ca | 1990 | } |
f1aa6320 | 1991 | #endif /* !CONFIG_USER_ONLY */ |
fd4a04eb TS |
1992 | |
1993 | /* Complex FPU operations which may need stack space. */ | |
1994 | ||
f090c9d4 PB |
1995 | #define FLOAT_ONE32 make_float32(0x3f8 << 20) |
1996 | #define FLOAT_ONE64 make_float64(0x3ffULL << 52) | |
1997 | #define FLOAT_TWO32 make_float32(1 << 30) | |
1998 | #define FLOAT_TWO64 make_float64(1ULL << 62) | |
54454097 TS |
1999 | #define FLOAT_QNAN32 0x7fbfffff |
2000 | #define FLOAT_QNAN64 0x7ff7ffffffffffffULL | |
2001 | #define FLOAT_SNAN32 0x7fffffff | |
2002 | #define FLOAT_SNAN64 0x7fffffffffffffffULL | |
8dfdb87c | 2003 | |
fd4a04eb | 2004 | /* convert MIPS rounding mode in FCR31 to IEEE library */ |
6f4fc367 | 2005 | static unsigned int ieee_rm[] = { |
fd4a04eb TS |
2006 | float_round_nearest_even, |
2007 | float_round_to_zero, | |
2008 | float_round_up, | |
2009 | float_round_down | |
2010 | }; | |
2011 | ||
2012 | #define RESTORE_ROUNDING_MODE \ | |
f01be154 | 2013 | set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status) |
fd4a04eb | 2014 | |
41e0c701 AJ |
2015 | #define RESTORE_FLUSH_MODE \ |
2016 | set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); | |
2017 | ||
c01fccd2 | 2018 | target_ulong helper_cfc1 (uint32_t reg) |
fd4a04eb | 2019 | { |
d9bea114 | 2020 | target_ulong arg1; |
6c5c1e20 | 2021 | |
ead9360e TS |
2022 | switch (reg) { |
2023 | case 0: | |
d9bea114 | 2024 | arg1 = (int32_t)env->active_fpu.fcr0; |
ead9360e TS |
2025 | break; |
2026 | case 25: | |
d9bea114 | 2027 | arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); |
ead9360e TS |
2028 | break; |
2029 | case 26: | |
d9bea114 | 2030 | arg1 = env->active_fpu.fcr31 & 0x0003f07c; |
ead9360e TS |
2031 | break; |
2032 | case 28: | |
d9bea114 | 2033 | arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); |
ead9360e TS |
2034 | break; |
2035 | default: | |
d9bea114 | 2036 | arg1 = (int32_t)env->active_fpu.fcr31; |
ead9360e TS |
2037 | break; |
2038 | } | |
be24bb4f | 2039 | |
d9bea114 | 2040 | return arg1; |
ead9360e TS |
2041 | } |
2042 | ||
d9bea114 | 2043 | void helper_ctc1 (target_ulong arg1, uint32_t reg) |
ead9360e TS |
2044 | { |
2045 | switch(reg) { | |
fd4a04eb | 2046 | case 25: |
d9bea114 | 2047 | if (arg1 & 0xffffff00) |
fd4a04eb | 2048 | return; |
d9bea114 AJ |
2049 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | |
2050 | ((arg1 & 0x1) << 23); | |
fd4a04eb TS |
2051 | break; |
2052 | case 26: | |
d9bea114 | 2053 | if (arg1 & 0x007c0000) |
fd4a04eb | 2054 | return; |
d9bea114 | 2055 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); |
fd4a04eb TS |
2056 | break; |
2057 | case 28: | |
d9bea114 | 2058 | if (arg1 & 0x007c0000) |
fd4a04eb | 2059 | return; |
d9bea114 AJ |
2060 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | |
2061 | ((arg1 & 0x4) << 22); | |
fd4a04eb TS |
2062 | break; |
2063 | case 31: | |
d9bea114 | 2064 | if (arg1 & 0x007c0000) |
fd4a04eb | 2065 | return; |
d9bea114 | 2066 | env->active_fpu.fcr31 = arg1; |
fd4a04eb TS |
2067 | break; |
2068 | default: | |
2069 | return; | |
2070 | } | |
2071 | /* set rounding mode */ | |
2072 | RESTORE_ROUNDING_MODE; | |
41e0c701 AJ |
2073 | /* set flush-to-zero mode */ |
2074 | RESTORE_FLUSH_MODE; | |
f01be154 TS |
2075 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2076 | if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) | |
c01fccd2 | 2077 | helper_raise_exception(EXCP_FPE); |
fd4a04eb TS |
2078 | } |
2079 | ||
c904ef0e | 2080 | static inline char ieee_ex_to_mips(char xcpt) |
fd4a04eb TS |
2081 | { |
2082 | return (xcpt & float_flag_inexact) >> 5 | | |
2083 | (xcpt & float_flag_underflow) >> 3 | | |
2084 | (xcpt & float_flag_overflow) >> 1 | | |
2085 | (xcpt & float_flag_divbyzero) << 1 | | |
2086 | (xcpt & float_flag_invalid) << 4; | |
2087 | } | |
2088 | ||
c904ef0e | 2089 | static inline char mips_ex_to_ieee(char xcpt) |
fd4a04eb TS |
2090 | { |
2091 | return (xcpt & FP_INEXACT) << 5 | | |
2092 | (xcpt & FP_UNDERFLOW) << 3 | | |
2093 | (xcpt & FP_OVERFLOW) << 1 | | |
2094 | (xcpt & FP_DIV0) >> 1 | | |
2095 | (xcpt & FP_INVALID) >> 4; | |
2096 | } | |
2097 | ||
c904ef0e | 2098 | static inline void update_fcr31(void) |
fd4a04eb | 2099 | { |
f01be154 | 2100 | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); |
fd4a04eb | 2101 | |
f01be154 TS |
2102 | SET_FP_CAUSE(env->active_fpu.fcr31, tmp); |
2103 | if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) | |
c01fccd2 | 2104 | helper_raise_exception(EXCP_FPE); |
fd4a04eb | 2105 | else |
f01be154 | 2106 | UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); |
fd4a04eb TS |
2107 | } |
2108 | ||
a16336e4 TS |
2109 | /* Float support. |
2110 | Single precition routines have a "s" suffix, double precision a | |
2111 | "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", | |
2112 | paired single lower "pl", paired single upper "pu". */ | |
2113 | ||
a16336e4 | 2114 | /* unary operations, modifying fp status */ |
c01fccd2 | 2115 | uint64_t helper_float_sqrt_d(uint64_t fdt0) |
b6d96bed | 2116 | { |
f01be154 | 2117 | return float64_sqrt(fdt0, &env->active_fpu.fp_status); |
b6d96bed TS |
2118 | } |
2119 | ||
c01fccd2 | 2120 | uint32_t helper_float_sqrt_s(uint32_t fst0) |
b6d96bed | 2121 | { |
f01be154 | 2122 | return float32_sqrt(fst0, &env->active_fpu.fp_status); |
b6d96bed | 2123 | } |
a16336e4 | 2124 | |
c01fccd2 | 2125 | uint64_t helper_float_cvtd_s(uint32_t fst0) |
fd4a04eb | 2126 | { |
b6d96bed TS |
2127 | uint64_t fdt2; |
2128 | ||
f01be154 TS |
2129 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2130 | fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2131 | update_fcr31(); |
b6d96bed | 2132 | return fdt2; |
fd4a04eb | 2133 | } |
b6d96bed | 2134 | |
c01fccd2 | 2135 | uint64_t helper_float_cvtd_w(uint32_t wt0) |
fd4a04eb | 2136 | { |
b6d96bed TS |
2137 | uint64_t fdt2; |
2138 | ||
f01be154 TS |
2139 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2140 | fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2141 | update_fcr31(); |
b6d96bed | 2142 | return fdt2; |
fd4a04eb | 2143 | } |
b6d96bed | 2144 | |
c01fccd2 | 2145 | uint64_t helper_float_cvtd_l(uint64_t dt0) |
fd4a04eb | 2146 | { |
b6d96bed TS |
2147 | uint64_t fdt2; |
2148 | ||
f01be154 TS |
2149 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2150 | fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2151 | update_fcr31(); |
b6d96bed | 2152 | return fdt2; |
fd4a04eb | 2153 | } |
b6d96bed | 2154 | |
c01fccd2 | 2155 | uint64_t helper_float_cvtl_d(uint64_t fdt0) |
fd4a04eb | 2156 | { |
b6d96bed TS |
2157 | uint64_t dt2; |
2158 | ||
f01be154 TS |
2159 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2160 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2161 | update_fcr31(); |
f01be154 | 2162 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2163 | dt2 = FLOAT_SNAN64; |
2164 | return dt2; | |
fd4a04eb | 2165 | } |
b6d96bed | 2166 | |
c01fccd2 | 2167 | uint64_t helper_float_cvtl_s(uint32_t fst0) |
fd4a04eb | 2168 | { |
b6d96bed TS |
2169 | uint64_t dt2; |
2170 | ||
f01be154 TS |
2171 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2172 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2173 | update_fcr31(); |
f01be154 | 2174 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2175 | dt2 = FLOAT_SNAN64; |
2176 | return dt2; | |
fd4a04eb TS |
2177 | } |
2178 | ||
c01fccd2 | 2179 | uint64_t helper_float_cvtps_pw(uint64_t dt0) |
fd4a04eb | 2180 | { |
b6d96bed TS |
2181 | uint32_t fst2; |
2182 | uint32_t fsth2; | |
2183 | ||
f01be154 TS |
2184 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2185 | fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); | |
2186 | fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); | |
fd4a04eb | 2187 | update_fcr31(); |
b6d96bed | 2188 | return ((uint64_t)fsth2 << 32) | fst2; |
fd4a04eb | 2189 | } |
b6d96bed | 2190 | |
c01fccd2 | 2191 | uint64_t helper_float_cvtpw_ps(uint64_t fdt0) |
fd4a04eb | 2192 | { |
b6d96bed TS |
2193 | uint32_t wt2; |
2194 | uint32_t wth2; | |
2195 | ||
f01be154 TS |
2196 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2197 | wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); | |
2198 | wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); | |
fd4a04eb | 2199 | update_fcr31(); |
f01be154 | 2200 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { |
b6d96bed TS |
2201 | wt2 = FLOAT_SNAN32; |
2202 | wth2 = FLOAT_SNAN32; | |
2203 | } | |
2204 | return ((uint64_t)wth2 << 32) | wt2; | |
fd4a04eb | 2205 | } |
b6d96bed | 2206 | |
c01fccd2 | 2207 | uint32_t helper_float_cvts_d(uint64_t fdt0) |
fd4a04eb | 2208 | { |
b6d96bed TS |
2209 | uint32_t fst2; |
2210 | ||
f01be154 TS |
2211 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2212 | fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2213 | update_fcr31(); |
b6d96bed | 2214 | return fst2; |
fd4a04eb | 2215 | } |
b6d96bed | 2216 | |
c01fccd2 | 2217 | uint32_t helper_float_cvts_w(uint32_t wt0) |
fd4a04eb | 2218 | { |
b6d96bed TS |
2219 | uint32_t fst2; |
2220 | ||
f01be154 TS |
2221 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2222 | fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2223 | update_fcr31(); |
b6d96bed | 2224 | return fst2; |
fd4a04eb | 2225 | } |
b6d96bed | 2226 | |
c01fccd2 | 2227 | uint32_t helper_float_cvts_l(uint64_t dt0) |
fd4a04eb | 2228 | { |
b6d96bed TS |
2229 | uint32_t fst2; |
2230 | ||
f01be154 TS |
2231 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2232 | fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2233 | update_fcr31(); |
b6d96bed | 2234 | return fst2; |
fd4a04eb | 2235 | } |
b6d96bed | 2236 | |
c01fccd2 | 2237 | uint32_t helper_float_cvts_pl(uint32_t wt0) |
fd4a04eb | 2238 | { |
b6d96bed TS |
2239 | uint32_t wt2; |
2240 | ||
f01be154 | 2241 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
b6d96bed | 2242 | wt2 = wt0; |
fd4a04eb | 2243 | update_fcr31(); |
b6d96bed | 2244 | return wt2; |
fd4a04eb | 2245 | } |
b6d96bed | 2246 | |
c01fccd2 | 2247 | uint32_t helper_float_cvts_pu(uint32_t wth0) |
fd4a04eb | 2248 | { |
b6d96bed TS |
2249 | uint32_t wt2; |
2250 | ||
f01be154 | 2251 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
b6d96bed | 2252 | wt2 = wth0; |
fd4a04eb | 2253 | update_fcr31(); |
b6d96bed | 2254 | return wt2; |
fd4a04eb | 2255 | } |
b6d96bed | 2256 | |
c01fccd2 | 2257 | uint32_t helper_float_cvtw_s(uint32_t fst0) |
fd4a04eb | 2258 | { |
b6d96bed TS |
2259 | uint32_t wt2; |
2260 | ||
f01be154 TS |
2261 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2262 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2263 | update_fcr31(); |
f01be154 | 2264 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2265 | wt2 = FLOAT_SNAN32; |
2266 | return wt2; | |
fd4a04eb | 2267 | } |
b6d96bed | 2268 | |
c01fccd2 | 2269 | uint32_t helper_float_cvtw_d(uint64_t fdt0) |
fd4a04eb | 2270 | { |
b6d96bed TS |
2271 | uint32_t wt2; |
2272 | ||
f01be154 TS |
2273 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2274 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2275 | update_fcr31(); |
f01be154 | 2276 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2277 | wt2 = FLOAT_SNAN32; |
2278 | return wt2; | |
fd4a04eb TS |
2279 | } |
2280 | ||
c01fccd2 | 2281 | uint64_t helper_float_roundl_d(uint64_t fdt0) |
fd4a04eb | 2282 | { |
b6d96bed TS |
2283 | uint64_t dt2; |
2284 | ||
f01be154 TS |
2285 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2286 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2287 | RESTORE_ROUNDING_MODE; |
2288 | update_fcr31(); | |
f01be154 | 2289 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2290 | dt2 = FLOAT_SNAN64; |
2291 | return dt2; | |
fd4a04eb | 2292 | } |
b6d96bed | 2293 | |
c01fccd2 | 2294 | uint64_t helper_float_roundl_s(uint32_t fst0) |
fd4a04eb | 2295 | { |
b6d96bed TS |
2296 | uint64_t dt2; |
2297 | ||
f01be154 TS |
2298 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2299 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2300 | RESTORE_ROUNDING_MODE; |
2301 | update_fcr31(); | |
f01be154 | 2302 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2303 | dt2 = FLOAT_SNAN64; |
2304 | return dt2; | |
fd4a04eb | 2305 | } |
b6d96bed | 2306 | |
c01fccd2 | 2307 | uint32_t helper_float_roundw_d(uint64_t fdt0) |
fd4a04eb | 2308 | { |
b6d96bed TS |
2309 | uint32_t wt2; |
2310 | ||
f01be154 TS |
2311 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2312 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2313 | RESTORE_ROUNDING_MODE; |
2314 | update_fcr31(); | |
f01be154 | 2315 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2316 | wt2 = FLOAT_SNAN32; |
2317 | return wt2; | |
fd4a04eb | 2318 | } |
b6d96bed | 2319 | |
c01fccd2 | 2320 | uint32_t helper_float_roundw_s(uint32_t fst0) |
fd4a04eb | 2321 | { |
b6d96bed TS |
2322 | uint32_t wt2; |
2323 | ||
f01be154 TS |
2324 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2325 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2326 | RESTORE_ROUNDING_MODE; |
2327 | update_fcr31(); | |
f01be154 | 2328 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2329 | wt2 = FLOAT_SNAN32; |
2330 | return wt2; | |
fd4a04eb TS |
2331 | } |
2332 | ||
c01fccd2 | 2333 | uint64_t helper_float_truncl_d(uint64_t fdt0) |
fd4a04eb | 2334 | { |
b6d96bed TS |
2335 | uint64_t dt2; |
2336 | ||
f01be154 | 2337 | dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); |
fd4a04eb | 2338 | update_fcr31(); |
f01be154 | 2339 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2340 | dt2 = FLOAT_SNAN64; |
2341 | return dt2; | |
fd4a04eb | 2342 | } |
b6d96bed | 2343 | |
c01fccd2 | 2344 | uint64_t helper_float_truncl_s(uint32_t fst0) |
fd4a04eb | 2345 | { |
b6d96bed TS |
2346 | uint64_t dt2; |
2347 | ||
f01be154 | 2348 | dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); |
fd4a04eb | 2349 | update_fcr31(); |
f01be154 | 2350 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2351 | dt2 = FLOAT_SNAN64; |
2352 | return dt2; | |
fd4a04eb | 2353 | } |
b6d96bed | 2354 | |
c01fccd2 | 2355 | uint32_t helper_float_truncw_d(uint64_t fdt0) |
fd4a04eb | 2356 | { |
b6d96bed TS |
2357 | uint32_t wt2; |
2358 | ||
f01be154 | 2359 | wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); |
fd4a04eb | 2360 | update_fcr31(); |
f01be154 | 2361 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2362 | wt2 = FLOAT_SNAN32; |
2363 | return wt2; | |
fd4a04eb | 2364 | } |
b6d96bed | 2365 | |
c01fccd2 | 2366 | uint32_t helper_float_truncw_s(uint32_t fst0) |
fd4a04eb | 2367 | { |
b6d96bed TS |
2368 | uint32_t wt2; |
2369 | ||
f01be154 | 2370 | wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); |
fd4a04eb | 2371 | update_fcr31(); |
f01be154 | 2372 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2373 | wt2 = FLOAT_SNAN32; |
2374 | return wt2; | |
fd4a04eb TS |
2375 | } |
2376 | ||
c01fccd2 | 2377 | uint64_t helper_float_ceill_d(uint64_t fdt0) |
fd4a04eb | 2378 | { |
b6d96bed TS |
2379 | uint64_t dt2; |
2380 | ||
f01be154 TS |
2381 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2382 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2383 | RESTORE_ROUNDING_MODE; |
2384 | update_fcr31(); | |
f01be154 | 2385 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2386 | dt2 = FLOAT_SNAN64; |
2387 | return dt2; | |
fd4a04eb | 2388 | } |
b6d96bed | 2389 | |
c01fccd2 | 2390 | uint64_t helper_float_ceill_s(uint32_t fst0) |
fd4a04eb | 2391 | { |
b6d96bed TS |
2392 | uint64_t dt2; |
2393 | ||
f01be154 TS |
2394 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2395 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2396 | RESTORE_ROUNDING_MODE; |
2397 | update_fcr31(); | |
f01be154 | 2398 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2399 | dt2 = FLOAT_SNAN64; |
2400 | return dt2; | |
fd4a04eb | 2401 | } |
b6d96bed | 2402 | |
c01fccd2 | 2403 | uint32_t helper_float_ceilw_d(uint64_t fdt0) |
fd4a04eb | 2404 | { |
b6d96bed TS |
2405 | uint32_t wt2; |
2406 | ||
f01be154 TS |
2407 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2408 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2409 | RESTORE_ROUNDING_MODE; |
2410 | update_fcr31(); | |
f01be154 | 2411 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2412 | wt2 = FLOAT_SNAN32; |
2413 | return wt2; | |
fd4a04eb | 2414 | } |
b6d96bed | 2415 | |
c01fccd2 | 2416 | uint32_t helper_float_ceilw_s(uint32_t fst0) |
fd4a04eb | 2417 | { |
b6d96bed TS |
2418 | uint32_t wt2; |
2419 | ||
f01be154 TS |
2420 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2421 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2422 | RESTORE_ROUNDING_MODE; |
2423 | update_fcr31(); | |
f01be154 | 2424 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2425 | wt2 = FLOAT_SNAN32; |
2426 | return wt2; | |
fd4a04eb TS |
2427 | } |
2428 | ||
c01fccd2 | 2429 | uint64_t helper_float_floorl_d(uint64_t fdt0) |
fd4a04eb | 2430 | { |
b6d96bed TS |
2431 | uint64_t dt2; |
2432 | ||
f01be154 TS |
2433 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2434 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2435 | RESTORE_ROUNDING_MODE; |
2436 | update_fcr31(); | |
f01be154 | 2437 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2438 | dt2 = FLOAT_SNAN64; |
2439 | return dt2; | |
fd4a04eb | 2440 | } |
b6d96bed | 2441 | |
c01fccd2 | 2442 | uint64_t helper_float_floorl_s(uint32_t fst0) |
fd4a04eb | 2443 | { |
b6d96bed TS |
2444 | uint64_t dt2; |
2445 | ||
f01be154 TS |
2446 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2447 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2448 | RESTORE_ROUNDING_MODE; |
2449 | update_fcr31(); | |
f01be154 | 2450 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2451 | dt2 = FLOAT_SNAN64; |
2452 | return dt2; | |
fd4a04eb | 2453 | } |
b6d96bed | 2454 | |
c01fccd2 | 2455 | uint32_t helper_float_floorw_d(uint64_t fdt0) |
fd4a04eb | 2456 | { |
b6d96bed TS |
2457 | uint32_t wt2; |
2458 | ||
f01be154 TS |
2459 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2460 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2461 | RESTORE_ROUNDING_MODE; |
2462 | update_fcr31(); | |
f01be154 | 2463 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2464 | wt2 = FLOAT_SNAN32; |
2465 | return wt2; | |
fd4a04eb | 2466 | } |
b6d96bed | 2467 | |
c01fccd2 | 2468 | uint32_t helper_float_floorw_s(uint32_t fst0) |
fd4a04eb | 2469 | { |
b6d96bed TS |
2470 | uint32_t wt2; |
2471 | ||
f01be154 TS |
2472 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2473 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2474 | RESTORE_ROUNDING_MODE; |
2475 | update_fcr31(); | |
f01be154 | 2476 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2477 | wt2 = FLOAT_SNAN32; |
2478 | return wt2; | |
fd4a04eb TS |
2479 | } |
2480 | ||
a16336e4 | 2481 | /* unary operations, not modifying fp status */ |
b6d96bed | 2482 | #define FLOAT_UNOP(name) \ |
c01fccd2 | 2483 | uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ |
b6d96bed TS |
2484 | { \ |
2485 | return float64_ ## name(fdt0); \ | |
2486 | } \ | |
c01fccd2 | 2487 | uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ |
b6d96bed TS |
2488 | { \ |
2489 | return float32_ ## name(fst0); \ | |
2490 | } \ | |
c01fccd2 | 2491 | uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ |
b6d96bed TS |
2492 | { \ |
2493 | uint32_t wt0; \ | |
2494 | uint32_t wth0; \ | |
2495 | \ | |
2496 | wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ | |
2497 | wth0 = float32_ ## name(fdt0 >> 32); \ | |
2498 | return ((uint64_t)wth0 << 32) | wt0; \ | |
a16336e4 TS |
2499 | } |
2500 | FLOAT_UNOP(abs) | |
2501 | FLOAT_UNOP(chs) | |
2502 | #undef FLOAT_UNOP | |
2503 | ||
8dfdb87c | 2504 | /* MIPS specific unary operations */ |
c01fccd2 | 2505 | uint64_t helper_float_recip_d(uint64_t fdt0) |
8dfdb87c | 2506 | { |
b6d96bed TS |
2507 | uint64_t fdt2; |
2508 | ||
f01be154 TS |
2509 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2510 | fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); | |
8dfdb87c | 2511 | update_fcr31(); |
b6d96bed | 2512 | return fdt2; |
8dfdb87c | 2513 | } |
b6d96bed | 2514 | |
c01fccd2 | 2515 | uint32_t helper_float_recip_s(uint32_t fst0) |
8dfdb87c | 2516 | { |
b6d96bed TS |
2517 | uint32_t fst2; |
2518 | ||
f01be154 TS |
2519 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2520 | fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); | |
8dfdb87c | 2521 | update_fcr31(); |
b6d96bed | 2522 | return fst2; |
57fa1fb3 | 2523 | } |
57fa1fb3 | 2524 | |
c01fccd2 | 2525 | uint64_t helper_float_rsqrt_d(uint64_t fdt0) |
8dfdb87c | 2526 | { |
b6d96bed TS |
2527 | uint64_t fdt2; |
2528 | ||
f01be154 TS |
2529 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2530 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); | |
2531 | fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); | |
8dfdb87c | 2532 | update_fcr31(); |
b6d96bed | 2533 | return fdt2; |
8dfdb87c | 2534 | } |
b6d96bed | 2535 | |
c01fccd2 | 2536 | uint32_t helper_float_rsqrt_s(uint32_t fst0) |
8dfdb87c | 2537 | { |
b6d96bed TS |
2538 | uint32_t fst2; |
2539 | ||
f01be154 TS |
2540 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2541 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); | |
2542 | fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); | |
8dfdb87c | 2543 | update_fcr31(); |
b6d96bed | 2544 | return fst2; |
8dfdb87c TS |
2545 | } |
2546 | ||
c01fccd2 | 2547 | uint64_t helper_float_recip1_d(uint64_t fdt0) |
8dfdb87c | 2548 | { |
b6d96bed TS |
2549 | uint64_t fdt2; |
2550 | ||
f01be154 TS |
2551 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2552 | fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); | |
8dfdb87c | 2553 | update_fcr31(); |
b6d96bed | 2554 | return fdt2; |
8dfdb87c | 2555 | } |
b6d96bed | 2556 | |
c01fccd2 | 2557 | uint32_t helper_float_recip1_s(uint32_t fst0) |
8dfdb87c | 2558 | { |
b6d96bed TS |
2559 | uint32_t fst2; |
2560 | ||
f01be154 TS |
2561 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2562 | fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); | |
8dfdb87c | 2563 | update_fcr31(); |
b6d96bed | 2564 | return fst2; |
8dfdb87c | 2565 | } |
b6d96bed | 2566 | |
c01fccd2 | 2567 | uint64_t helper_float_recip1_ps(uint64_t fdt0) |
8dfdb87c | 2568 | { |
b6d96bed TS |
2569 | uint32_t fst2; |
2570 | uint32_t fsth2; | |
2571 | ||
f01be154 TS |
2572 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2573 | fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); | |
2574 | fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); | |
8dfdb87c | 2575 | update_fcr31(); |
b6d96bed | 2576 | return ((uint64_t)fsth2 << 32) | fst2; |
8dfdb87c TS |
2577 | } |
2578 | ||
c01fccd2 | 2579 | uint64_t helper_float_rsqrt1_d(uint64_t fdt0) |
8dfdb87c | 2580 | { |
b6d96bed TS |
2581 | uint64_t fdt2; |
2582 | ||
f01be154 TS |
2583 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2584 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); | |
2585 | fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); | |
8dfdb87c | 2586 | update_fcr31(); |
b6d96bed | 2587 | return fdt2; |
8dfdb87c | 2588 | } |
b6d96bed | 2589 | |
c01fccd2 | 2590 | uint32_t helper_float_rsqrt1_s(uint32_t fst0) |
8dfdb87c | 2591 | { |
b6d96bed TS |
2592 | uint32_t fst2; |
2593 | ||
f01be154 TS |
2594 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2595 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); | |
2596 | fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); | |
8dfdb87c | 2597 | update_fcr31(); |
b6d96bed | 2598 | return fst2; |
8dfdb87c | 2599 | } |
b6d96bed | 2600 | |
c01fccd2 | 2601 | uint64_t helper_float_rsqrt1_ps(uint64_t fdt0) |
8dfdb87c | 2602 | { |
b6d96bed TS |
2603 | uint32_t fst2; |
2604 | uint32_t fsth2; | |
2605 | ||
f01be154 TS |
2606 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2607 | fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); | |
2608 | fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); | |
2609 | fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); | |
2610 | fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); | |
8dfdb87c | 2611 | update_fcr31(); |
b6d96bed | 2612 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 | 2613 | } |
57fa1fb3 | 2614 | |
c01fccd2 | 2615 | #define FLOAT_OP(name, p) void helper_float_##name##_##p(void) |
b6d96bed | 2616 | |
fd4a04eb | 2617 | /* binary operations */ |
b6d96bed | 2618 | #define FLOAT_BINOP(name) \ |
c01fccd2 | 2619 | uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \ |
b6d96bed TS |
2620 | { \ |
2621 | uint64_t dt2; \ | |
2622 | \ | |
f01be154 TS |
2623 | set_float_exception_flags(0, &env->active_fpu.fp_status); \ |
2624 | dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ | |
ead9360e | 2625 | update_fcr31(); \ |
f01be154 | 2626 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ |
b6d96bed TS |
2627 | dt2 = FLOAT_QNAN64; \ |
2628 | return dt2; \ | |
2629 | } \ | |
2630 | \ | |
c01fccd2 | 2631 | uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \ |
b6d96bed TS |
2632 | { \ |
2633 | uint32_t wt2; \ | |
2634 | \ | |
f01be154 TS |
2635 | set_float_exception_flags(0, &env->active_fpu.fp_status); \ |
2636 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ | |
ead9360e | 2637 | update_fcr31(); \ |
f01be154 | 2638 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ |
b6d96bed TS |
2639 | wt2 = FLOAT_QNAN32; \ |
2640 | return wt2; \ | |
2641 | } \ | |
2642 | \ | |
c01fccd2 | 2643 | uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ |
b6d96bed TS |
2644 | { \ |
2645 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2646 | uint32_t fsth0 = fdt0 >> 32; \ | |
2647 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2648 | uint32_t fsth1 = fdt1 >> 32; \ | |
2649 | uint32_t wt2; \ | |
2650 | uint32_t wth2; \ | |
2651 | \ | |
f01be154 TS |
2652 | set_float_exception_flags(0, &env->active_fpu.fp_status); \ |
2653 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ | |
2654 | wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ | |
b6d96bed | 2655 | update_fcr31(); \ |
f01be154 | 2656 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \ |
b6d96bed TS |
2657 | wt2 = FLOAT_QNAN32; \ |
2658 | wth2 = FLOAT_QNAN32; \ | |
2659 | } \ | |
2660 | return ((uint64_t)wth2 << 32) | wt2; \ | |
fd4a04eb | 2661 | } |
b6d96bed | 2662 | |
fd4a04eb TS |
2663 | FLOAT_BINOP(add) |
2664 | FLOAT_BINOP(sub) | |
2665 | FLOAT_BINOP(mul) | |
2666 | FLOAT_BINOP(div) | |
2667 | #undef FLOAT_BINOP | |
2668 | ||
a16336e4 | 2669 | /* ternary operations */ |
b6d96bed | 2670 | #define FLOAT_TERNOP(name1, name2) \ |
c01fccd2 | 2671 | uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ |
b6d96bed TS |
2672 | uint64_t fdt2) \ |
2673 | { \ | |
f01be154 TS |
2674 | fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
2675 | return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2676 | } \ |
2677 | \ | |
c01fccd2 | 2678 | uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ |
b6d96bed TS |
2679 | uint32_t fst2) \ |
2680 | { \ | |
f01be154 TS |
2681 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2682 | return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2683 | } \ |
2684 | \ | |
c01fccd2 | 2685 | uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ |
b6d96bed TS |
2686 | uint64_t fdt2) \ |
2687 | { \ | |
2688 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2689 | uint32_t fsth0 = fdt0 >> 32; \ | |
2690 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2691 | uint32_t fsth1 = fdt1 >> 32; \ | |
2692 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ | |
2693 | uint32_t fsth2 = fdt2 >> 32; \ | |
2694 | \ | |
f01be154 TS |
2695 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2696 | fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ | |
2697 | fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ | |
2698 | fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ | |
b6d96bed | 2699 | return ((uint64_t)fsth2 << 32) | fst2; \ |
a16336e4 | 2700 | } |
b6d96bed | 2701 | |
a16336e4 TS |
2702 | FLOAT_TERNOP(mul, add) |
2703 | FLOAT_TERNOP(mul, sub) | |
2704 | #undef FLOAT_TERNOP | |
2705 | ||
2706 | /* negated ternary operations */ | |
b6d96bed | 2707 | #define FLOAT_NTERNOP(name1, name2) \ |
c01fccd2 | 2708 | uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ |
b6d96bed TS |
2709 | uint64_t fdt2) \ |
2710 | { \ | |
f01be154 TS |
2711 | fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
2712 | fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2713 | return float64_chs(fdt2); \ |
2714 | } \ | |
2715 | \ | |
c01fccd2 | 2716 | uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ |
b6d96bed TS |
2717 | uint32_t fst2) \ |
2718 | { \ | |
f01be154 TS |
2719 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2720 | fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2721 | return float32_chs(fst2); \ |
2722 | } \ | |
2723 | \ | |
c01fccd2 | 2724 | uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\ |
b6d96bed TS |
2725 | uint64_t fdt2) \ |
2726 | { \ | |
2727 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2728 | uint32_t fsth0 = fdt0 >> 32; \ | |
2729 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2730 | uint32_t fsth1 = fdt1 >> 32; \ | |
2731 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ | |
2732 | uint32_t fsth2 = fdt2 >> 32; \ | |
2733 | \ | |
f01be154 TS |
2734 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2735 | fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ | |
2736 | fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ | |
2737 | fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2738 | fst2 = float32_chs(fst2); \ |
2739 | fsth2 = float32_chs(fsth2); \ | |
2740 | return ((uint64_t)fsth2 << 32) | fst2; \ | |
a16336e4 | 2741 | } |
b6d96bed | 2742 | |
a16336e4 TS |
2743 | FLOAT_NTERNOP(mul, add) |
2744 | FLOAT_NTERNOP(mul, sub) | |
2745 | #undef FLOAT_NTERNOP | |
2746 | ||
8dfdb87c | 2747 | /* MIPS specific binary operations */ |
c01fccd2 | 2748 | uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2749 | { |
f01be154 TS |
2750 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2751 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); | |
2752 | fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); | |
8dfdb87c | 2753 | update_fcr31(); |
b6d96bed | 2754 | return fdt2; |
8dfdb87c | 2755 | } |
b6d96bed | 2756 | |
c01fccd2 | 2757 | uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2) |
8dfdb87c | 2758 | { |
f01be154 TS |
2759 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2760 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); | |
2761 | fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); | |
8dfdb87c | 2762 | update_fcr31(); |
b6d96bed | 2763 | return fst2; |
8dfdb87c | 2764 | } |
b6d96bed | 2765 | |
c01fccd2 | 2766 | uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2767 | { |
b6d96bed TS |
2768 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2769 | uint32_t fsth0 = fdt0 >> 32; | |
2770 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; | |
2771 | uint32_t fsth2 = fdt2 >> 32; | |
2772 | ||
f01be154 TS |
2773 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2774 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); | |
2775 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); | |
2776 | fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); | |
2777 | fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); | |
8dfdb87c | 2778 | update_fcr31(); |
b6d96bed | 2779 | return ((uint64_t)fsth2 << 32) | fst2; |
8dfdb87c TS |
2780 | } |
2781 | ||
c01fccd2 | 2782 | uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2783 | { |
f01be154 TS |
2784 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2785 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); | |
2786 | fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); | |
2787 | fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); | |
8dfdb87c | 2788 | update_fcr31(); |
b6d96bed | 2789 | return fdt2; |
8dfdb87c | 2790 | } |
b6d96bed | 2791 | |
c01fccd2 | 2792 | uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2) |
8dfdb87c | 2793 | { |
f01be154 TS |
2794 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2795 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); | |
2796 | fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); | |
2797 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); | |
8dfdb87c | 2798 | update_fcr31(); |
b6d96bed | 2799 | return fst2; |
8dfdb87c | 2800 | } |
b6d96bed | 2801 | |
c01fccd2 | 2802 | uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2803 | { |
b6d96bed TS |
2804 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2805 | uint32_t fsth0 = fdt0 >> 32; | |
2806 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; | |
2807 | uint32_t fsth2 = fdt2 >> 32; | |
2808 | ||
f01be154 TS |
2809 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2810 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); | |
2811 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); | |
2812 | fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); | |
2813 | fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); | |
2814 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); | |
2815 | fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); | |
8dfdb87c | 2816 | update_fcr31(); |
b6d96bed | 2817 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 | 2818 | } |
57fa1fb3 | 2819 | |
c01fccd2 | 2820 | uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1) |
fd4a04eb | 2821 | { |
b6d96bed TS |
2822 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2823 | uint32_t fsth0 = fdt0 >> 32; | |
2824 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; | |
2825 | uint32_t fsth1 = fdt1 >> 32; | |
2826 | uint32_t fst2; | |
2827 | uint32_t fsth2; | |
2828 | ||
f01be154 TS |
2829 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2830 | fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); | |
2831 | fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); | |
fd4a04eb | 2832 | update_fcr31(); |
b6d96bed | 2833 | return ((uint64_t)fsth2 << 32) | fst2; |
fd4a04eb TS |
2834 | } |
2835 | ||
c01fccd2 | 2836 | uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) |
57fa1fb3 | 2837 | { |
b6d96bed TS |
2838 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2839 | uint32_t fsth0 = fdt0 >> 32; | |
2840 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; | |
2841 | uint32_t fsth1 = fdt1 >> 32; | |
2842 | uint32_t fst2; | |
2843 | uint32_t fsth2; | |
2844 | ||
f01be154 TS |
2845 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2846 | fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); | |
2847 | fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); | |
57fa1fb3 | 2848 | update_fcr31(); |
b6d96bed | 2849 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 TS |
2850 | } |
2851 | ||
8dfdb87c | 2852 | /* compare operations */ |
b6d96bed | 2853 | #define FOP_COND_D(op, cond) \ |
c01fccd2 | 2854 | void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
b6d96bed TS |
2855 | { \ |
2856 | int c = cond; \ | |
2857 | update_fcr31(); \ | |
2858 | if (c) \ | |
f01be154 | 2859 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2860 | else \ |
f01be154 | 2861 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2862 | } \ |
c01fccd2 | 2863 | void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
b6d96bed TS |
2864 | { \ |
2865 | int c; \ | |
2866 | fdt0 = float64_abs(fdt0); \ | |
2867 | fdt1 = float64_abs(fdt1); \ | |
2868 | c = cond; \ | |
2869 | update_fcr31(); \ | |
2870 | if (c) \ | |
f01be154 | 2871 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2872 | else \ |
f01be154 | 2873 | CLEAR_FP_COND(cc, env->active_fpu); \ |
fd4a04eb TS |
2874 | } |
2875 | ||
cd5158ea | 2876 | static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
fd4a04eb TS |
2877 | { |
2878 | if (float64_is_signaling_nan(a) || | |
2879 | float64_is_signaling_nan(b) || | |
18569871 | 2880 | (sig && (float64_is_quiet_nan(a) || float64_is_quiet_nan(b)))) { |
fd4a04eb TS |
2881 | float_raise(float_flag_invalid, status); |
2882 | return 1; | |
18569871 | 2883 | } else if (float64_is_quiet_nan(a) || float64_is_quiet_nan(b)) { |
fd4a04eb TS |
2884 | return 1; |
2885 | } else { | |
2886 | return 0; | |
2887 | } | |
2888 | } | |
2889 | ||
2890 | /* NOTE: the comma operator will make "cond" to eval to false, | |
2891 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2892 | FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
2893 | FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)) | |
2894 | FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2895 | FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2896 | FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2897 | FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2898 | FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2899 | FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) | |
fd4a04eb TS |
2900 | /* NOTE: the comma operator will make "cond" to eval to false, |
2901 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2902 | FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
2903 | FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)) | |
2904 | FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2905 | FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2906 | FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2907 | FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2908 | FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2909 | FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) | |
b6d96bed TS |
2910 | |
2911 | #define FOP_COND_S(op, cond) \ | |
c01fccd2 | 2912 | void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ |
b6d96bed TS |
2913 | { \ |
2914 | int c = cond; \ | |
2915 | update_fcr31(); \ | |
2916 | if (c) \ | |
f01be154 | 2917 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2918 | else \ |
f01be154 | 2919 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2920 | } \ |
c01fccd2 | 2921 | void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ |
b6d96bed TS |
2922 | { \ |
2923 | int c; \ | |
2924 | fst0 = float32_abs(fst0); \ | |
2925 | fst1 = float32_abs(fst1); \ | |
2926 | c = cond; \ | |
2927 | update_fcr31(); \ | |
2928 | if (c) \ | |
f01be154 | 2929 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2930 | else \ |
f01be154 | 2931 | CLEAR_FP_COND(cc, env->active_fpu); \ |
fd4a04eb TS |
2932 | } |
2933 | ||
cd5158ea | 2934 | static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM) |
fd4a04eb | 2935 | { |
fd4a04eb TS |
2936 | if (float32_is_signaling_nan(a) || |
2937 | float32_is_signaling_nan(b) || | |
18569871 | 2938 | (sig && (float32_is_quiet_nan(a) || float32_is_quiet_nan(b)))) { |
fd4a04eb TS |
2939 | float_raise(float_flag_invalid, status); |
2940 | return 1; | |
18569871 | 2941 | } else if (float32_is_quiet_nan(a) || float32_is_quiet_nan(b)) { |
fd4a04eb TS |
2942 | return 1; |
2943 | } else { | |
2944 | return 0; | |
2945 | } | |
2946 | } | |
2947 | ||
2948 | /* NOTE: the comma operator will make "cond" to eval to false, | |
2949 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2950 | FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0)) |
2951 | FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)) | |
2952 | FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
2953 | FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
2954 | FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
2955 | FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
2956 | FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) | |
2957 | FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) | |
fd4a04eb TS |
2958 | /* NOTE: the comma operator will make "cond" to eval to false, |
2959 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2960 | FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0)) |
2961 | FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)) | |
2962 | FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
2963 | FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
2964 | FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
2965 | FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
2966 | FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) | |
2967 | FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) | |
b6d96bed TS |
2968 | |
2969 | #define FOP_COND_PS(op, condl, condh) \ | |
c01fccd2 | 2970 | void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
b6d96bed TS |
2971 | { \ |
2972 | uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ | |
2973 | uint32_t fsth0 = float32_abs(fdt0 >> 32); \ | |
2974 | uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ | |
2975 | uint32_t fsth1 = float32_abs(fdt1 >> 32); \ | |
2976 | int cl = condl; \ | |
2977 | int ch = condh; \ | |
2978 | \ | |
2979 | update_fcr31(); \ | |
2980 | if (cl) \ | |
f01be154 | 2981 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2982 | else \ |
f01be154 | 2983 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2984 | if (ch) \ |
f01be154 | 2985 | SET_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 2986 | else \ |
f01be154 | 2987 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 2988 | } \ |
c01fccd2 | 2989 | void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
b6d96bed TS |
2990 | { \ |
2991 | uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ | |
2992 | uint32_t fsth0 = float32_abs(fdt0 >> 32); \ | |
2993 | uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ | |
2994 | uint32_t fsth1 = float32_abs(fdt1 >> 32); \ | |
2995 | int cl = condl; \ | |
2996 | int ch = condh; \ | |
2997 | \ | |
2998 | update_fcr31(); \ | |
2999 | if (cl) \ | |
f01be154 | 3000 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3001 | else \ |
f01be154 | 3002 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3003 | if (ch) \ |
f01be154 | 3004 | SET_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 3005 | else \ |
f01be154 | 3006 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
fd4a04eb TS |
3007 | } |
3008 | ||
3009 | /* NOTE: the comma operator will make "cond" to eval to false, | |
3010 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
3011 | FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0), |
3012 | (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0)) | |
3013 | FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), | |
3014 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)) | |
3015 | FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
3016 | !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3017 | FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
3018 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3019 | FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
3020 | !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3021 | FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
3022 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3023 | FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), | |
3024 | !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3025 | FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), | |
3026 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) | |
fd4a04eb TS |
3027 | /* NOTE: the comma operator will make "cond" to eval to false, |
3028 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
3029 | FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0), |
3030 | (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0)) | |
3031 | FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), | |
3032 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)) | |
3033 | FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
3034 | !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3035 | FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
3036 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3037 | FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
3038 | !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3039 | FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
3040 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3041 | FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), | |
3042 | !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3043 | FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), | |
3044 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |