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PowerPC emulation optimization:
[qemu.git] / target-mips / op_helper.c
CommitLineData
6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
2d0e944d 20#include <stdlib.h>
6af0bf9c
FB		 21#include "exec.h"
22
4ad40f36
FB		 23#define GETPC() (__builtin_return_address(0))
24
6af0bf9c
FB		 25/*****************************************************************************/
26/* Exceptions processing helpers */
6af0bf9c 27
6af0bf9c
FB		 28void do_raise_exception_err (uint32_t exception, int error_code)
29{
30#if 1
31 if (logfile && exception < 0x100)
32 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
33#endif
34 env->exception_index = exception;
35 env->error_code = error_code;
36 T0 = 0;
37 cpu_loop_exit();
38}
39
6af0bf9c
FB		 40void do_raise_exception (uint32_t exception)
41{
42 do_raise_exception_err(exception, 0);
43}
44
4ad40f36
FB		 45void do_restore_state (void *pc_ptr)
46{
47 TranslationBlock *tb;
48 unsigned long pc = (unsigned long) pc_ptr;
49
50 tb = tb_find_pc (pc);
51 cpu_restore_state (tb, env, pc, NULL);
52}
53
e397ee33 54void do_raise_exception_direct_err (uint32_t exception, int error_code)
4ad40f36
FB		 55{
56 do_restore_state (GETPC ());
e397ee33
TS		 57 do_raise_exception_err (exception, error_code);
58}
59
60void do_raise_exception_direct (uint32_t exception)
61{
62 do_raise_exception_direct_err (exception, 0);
4ad40f36
FB		 63}
64
6af0bf9c
FB		 65#define MEMSUFFIX _raw
66#include "op_helper_mem.c"
67#undef MEMSUFFIX
68#if !defined(CONFIG_USER_ONLY)
69#define MEMSUFFIX _user
70#include "op_helper_mem.c"
71#undef MEMSUFFIX
72#define MEMSUFFIX _kernel
73#include "op_helper_mem.c"
74#undef MEMSUFFIX
75#endif
76
60aa19ab 77#ifdef TARGET_MIPS64
c570fd16
TS		 78#if TARGET_LONG_BITS > HOST_LONG_BITS
79/* Those might call libgcc functions. */
80void do_dsll (void)
81{
82 T0 = T0 << T1;
83}
84
85void do_dsll32 (void)
86{
87 T0 = T0 << (T1 + 32);
88}
89
90void do_dsra (void)
91{
92 T0 = (int64_t)T0 >> T1;
93}
94
95void do_dsra32 (void)
96{
97 T0 = (int64_t)T0 >> (T1 + 32);
98}
99
100void do_dsrl (void)
101{
102 T0 = T0 >> T1;
103}
104
105void do_dsrl32 (void)
106{
107 T0 = T0 >> (T1 + 32);
108}
109
110void do_drotr (void)
111{
112 target_ulong tmp;
113
114 if (T1) {
115 tmp = T0 << (0x40 - T1);
116 T0 = (T0 >> T1) | tmp;
5a63bcb2 117 }
c570fd16
TS		 118}
119
120void do_drotr32 (void)
121{
122 target_ulong tmp;
123
124 if (T1) {
125 tmp = T0 << (0x40 - (32 + T1));
126 T0 = (T0 >> (32 + T1)) | tmp;
5a63bcb2 127 }
c570fd16
TS		 128}
129
130void do_dsllv (void)
131{
132 T0 = T1 << (T0 & 0x3F);
133}
134
135void do_dsrav (void)
136{
137 T0 = (int64_t)T1 >> (T0 & 0x3F);
138}
139
140void do_dsrlv (void)
141{
142 T0 = T1 >> (T0 & 0x3F);
143}
144
145void do_drotrv (void)
146{
147 target_ulong tmp;
148
149 T0 &= 0x3F;
150 if (T0) {
151 tmp = T1 << (0x40 - T0);
152 T0 = (T1 >> T0) | tmp;
153 } else
154 T0 = T1;
155}
156#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
60aa19ab 157#endif /* TARGET_MIPS64 */
c570fd16 158
6af0bf9c 159/* 64 bits arithmetic for 32 bits hosts */
c570fd16 160#if TARGET_LONG_BITS > HOST_LONG_BITS
6af0bf9c
FB		 161static inline uint64_t get_HILO (void)
162{
ead9360e 163 return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
6af0bf9c
FB		 164}
165
166static inline void set_HILO (uint64_t HILO)
167{
ead9360e
TS		 168 env->LO[0][env->current_tc] = (int32_t)HILO;
169 env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 170}
171
172void do_mult (void)
173{
4ad40f36 174 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 175}
176
177void do_multu (void)
178{
c570fd16 179 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 180}
181
182void do_madd (void)
183{
184 int64_t tmp;
185
4ad40f36 186 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 187 set_HILO((int64_t)get_HILO() + tmp);
188}
189
190void do_maddu (void)
191{
192 uint64_t tmp;
193
c570fd16 194 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 195 set_HILO(get_HILO() + tmp);
196}
197
198void do_msub (void)
199{
200 int64_t tmp;
201
4ad40f36 202 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 203 set_HILO((int64_t)get_HILO() - tmp);
204}
205
206void do_msubu (void)
207{
208 uint64_t tmp;
209
c570fd16 210 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 211 set_HILO(get_HILO() - tmp);
212}
213#endif
214
80c27194
TS		 215#if HOST_LONG_BITS < 64
216void do_div (void)
217{
218 /* 64bit datatypes because we may see overflow/underflow. */
219 if (T1 != 0) {
ead9360e
TS		 220 env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
221 env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
80c27194
TS		 222 }
223}
224#endif
225
60aa19ab 226#ifdef TARGET_MIPS64
c570fd16
TS		 227void do_ddiv (void)
228{
229 if (T1 != 0) {
2d0e944d 230 lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
ead9360e
TS		 231 env->LO[0][env->current_tc] = res.quot;
232 env->HI[0][env->current_tc] = res.rem;
c570fd16
TS		 233 }
234}
235
12a4b2aa 236#if TARGET_LONG_BITS > HOST_LONG_BITS
c570fd16
TS		 237void do_ddivu (void)
238{
239 if (T1 != 0) {
ead9360e
TS		 240 env->LO[0][env->current_tc] = T0 / T1;
241 env->HI[0][env->current_tc] = T0 % T1;
c570fd16
TS		 242 }
243}
244#endif
12a4b2aa 245#endif /* TARGET_MIPS64 */
c570fd16 246
5fafdf24 247#if defined(CONFIG_USER_ONLY)
873eb012 248void do_mfc0_random (void)
048f6b4d 249{
873eb012 250 cpu_abort(env, "mfc0 random\n");
048f6b4d 251}
873eb012
TS		 252
253void do_mfc0_count (void)
254{
255 cpu_abort(env, "mfc0 count\n");
256}
257
8c0fdd85 258void cpu_mips_store_count(CPUState *env, uint32_t value)
048f6b4d 259{
8c0fdd85
TS		 260 cpu_abort(env, "mtc0 count\n");
261}
262
263void cpu_mips_store_compare(CPUState *env, uint32_t value)
264{
265 cpu_abort(env, "mtc0 compare\n");
266}
267
42532189
TS		 268void cpu_mips_start_count(CPUState *env)
269{
270 cpu_abort(env, "start count\n");
271}
272
273void cpu_mips_stop_count(CPUState *env)
274{
275 cpu_abort(env, "stop count\n");
276}
277
4de9b249
TS		 278void cpu_mips_update_irq(CPUState *env)
279{
280 cpu_abort(env, "mtc0 status / mtc0 cause\n");
281}
282
8c0fdd85
TS		 283void do_mtc0_status_debug(uint32_t old, uint32_t val)
284{
7a387fff 285 cpu_abort(env, "mtc0 status debug\n");
8c0fdd85
TS		 286}
287
7a387fff 288void do_mtc0_status_irqraise_debug (void)
8c0fdd85 289{
7a387fff 290 cpu_abort(env, "mtc0 status irqraise debug\n");
048f6b4d
FB		 291}
292
8c0fdd85
TS		 293void cpu_mips_tlb_flush (CPUState *env, int flush_global)
294{
295 cpu_abort(env, "mips_tlb_flush\n");
296}
297
048f6b4d
FB		 298#else
299
6af0bf9c 300/* CP0 helpers */
873eb012 301void do_mfc0_random (void)
6af0bf9c 302{
5dc4b744 303 T0 = (int32_t)cpu_mips_get_random(env);
873eb012 304}
6af0bf9c 305
873eb012
TS		 306void do_mfc0_count (void)
307{
5dc4b744 308 T0 = (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 309}
310
8c0fdd85 311void do_mtc0_status_debug(uint32_t old, uint32_t val)
6af0bf9c 312{
f41c52f1
TS		 313 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
314 old, old & env->CP0_Cause & CP0Ca_IP_mask,
315 val, val & env->CP0_Cause & CP0Ca_IP_mask,
316 env->CP0_Cause);
317 (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
318 : fputs("\n", logfile);
8c0fdd85
TS		 319}
320
321void do_mtc0_status_irqraise_debug(void)
322{
323 fprintf(logfile, "Raise pending IRQs\n");
6af0bf9c
FB		 324}
325
6ea83fed
FB		 326void fpu_handle_exception(void)
327{
328#ifdef CONFIG_SOFTFLOAT
ead9360e 329 int flags = get_float_exception_flags(&env->fpu->fp_status);
6ea83fed
FB		 330 unsigned int cpuflags = 0, enable, cause = 0;
331
ead9360e 332 enable = GET_FP_ENABLE(env->fpu->fcr31);
6ea83fed 333
3b46e624 334 /* determine current flags */
6ea83fed
FB		 335 if (flags & float_flag_invalid) {
336 cpuflags |= FP_INVALID;
337 cause |= FP_INVALID & enable;
338 }
339 if (flags & float_flag_divbyzero) {
3b46e624 340 cpuflags |= FP_DIV0;
6ea83fed
FB		 341 cause |= FP_DIV0 & enable;
342 }
343 if (flags & float_flag_overflow) {
3b46e624 344 cpuflags |= FP_OVERFLOW;
6ea83fed
FB		 345 cause |= FP_OVERFLOW & enable;
346 }
347 if (flags & float_flag_underflow) {
3b46e624 348 cpuflags |= FP_UNDERFLOW;
6ea83fed
FB		 349 cause |= FP_UNDERFLOW & enable;
350 }
351 if (flags & float_flag_inexact) {
5fafdf24 352 cpuflags |= FP_INEXACT;
6ea83fed
FB		 353 cause |= FP_INEXACT & enable;
354 }
ead9360e
TS		 355 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
356 SET_FP_CAUSE(env->fpu->fcr31, cause);
6ea83fed 357#else
ead9360e
TS		 358 SET_FP_FLAGS(env->fpu->fcr31, 0);
359 SET_FP_CAUSE(env->fpu->fcr31, 0);
6ea83fed
FB		 360#endif
361}
6ea83fed 362
6af0bf9c 363/* TLB management */
814b9a47
TS		 364void cpu_mips_tlb_flush (CPUState *env, int flush_global)
365{
366 /* Flush qemu's TLB and discard all shadowed entries. */
367 tlb_flush (env, flush_global);
ead9360e 368 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 369}
370
29929e34 371static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 372{
373 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 374 while (env->tlb->tlb_in_use > first) {
375 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 376 }
377}
378
29929e34 379static void r4k_fill_tlb (int idx)
6af0bf9c 380{
29929e34 381 r4k_tlb_t *tlb;
6af0bf9c
FB		 382
383 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 384 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 385 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
100ce988 386#ifdef TARGET_MIPS64
e034e2c3 387 tlb->VPN &= env->SEGMask;
100ce988 388#endif
98c1b82b 389 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 390 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 391 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 392 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
393 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
394 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 395 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 396 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
397 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
398 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 399 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
400}
401
29929e34 402void r4k_do_tlbwi (void)
6af0bf9c 403{
814b9a47
TS		 404 /* Discard cached TLB entries. We could avoid doing this if the
405 tlbwi is just upgrading access permissions on the current entry;
406 that might be a further win. */
ead9360e 407 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 408
ead9360e
TS		 409 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
410 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
6af0bf9c
FB		 411}
412
29929e34 413void r4k_do_tlbwr (void)
6af0bf9c
FB		 414{
415 int r = cpu_mips_get_random(env);
416
29929e34
TS		 417 r4k_invalidate_tlb(env, r, 1);
418 r4k_fill_tlb(r);
6af0bf9c
FB		 419}
420
29929e34 421void r4k_do_tlbp (void)
6af0bf9c 422{
29929e34 423 r4k_tlb_t *tlb;
f2e9ebef 424 target_ulong mask;
6af0bf9c 425 target_ulong tag;
f2e9ebef 426 target_ulong VPN;
6af0bf9c
FB		 427 uint8_t ASID;
428 int i;
429
3d9fb9fe 430 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 431 for (i = 0; i < env->tlb->nb_tlb; i++) {
432 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 433 /* 1k pages are not supported. */
434 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
435 tag = env->CP0_EntryHi & ~mask;
436 VPN = tlb->VPN & ~mask;
6af0bf9c 437 /* Check ASID, virtual page number & size */
f2e9ebef 438 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 439 /* TLB match */
9c2149c8 440 env->CP0_Index = i;
6af0bf9c
FB		 441 break;
442 }
443 }
ead9360e 444 if (i == env->tlb->nb_tlb) {
814b9a47 445 /* No match. Discard any shadow entries, if any of them match. */
ead9360e
TS		 446 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
447 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 448 /* 1k pages are not supported. */
449 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
450 tag = env->CP0_EntryHi & ~mask;
451 VPN = tlb->VPN & ~mask;
814b9a47 452 /* Check ASID, virtual page number & size */
f2e9ebef 453 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 454 r4k_mips_tlb_flush_extra (env, i);
814b9a47
TS		 455 break;
456 }
457 }
458
9c2149c8 459 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 460 }
461}
462
29929e34 463void r4k_do_tlbr (void)
6af0bf9c 464{
29929e34 465 r4k_tlb_t *tlb;
09c56b84 466 uint8_t ASID;
6af0bf9c 467
09c56b84 468 ASID = env->CP0_EntryHi & 0xFF;
ead9360e 469 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
4ad40f36
FB		 470
471 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 472 if (ASID != tlb->ASID)
473 cpu_mips_tlb_flush (env, 1);
474
ead9360e 475 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 476
6af0bf9c 477 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 478 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 479 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
480 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
481 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
482 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 483}
6af0bf9c 484
048f6b4d
FB		 485#endif /* !CONFIG_USER_ONLY */
486
c570fd16 487void dump_ldst (const unsigned char *func)
6af0bf9c
FB		 488{
489 if (loglevel)
3594c774 490 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
6af0bf9c
FB		 491}
492
493void dump_sc (void)
494{
495 if (loglevel) {
3594c774 496 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
6af0bf9c
FB		 497 T1, T0, env->CP0_LLAddr);
498 }
499}
500
f41c52f1 501void debug_pre_eret (void)
6af0bf9c 502{
f41c52f1 503 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 504 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 505 if (env->CP0_Status & (1 << CP0St_ERL))
506 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
507 if (env->hflags & MIPS_HFLAG_DM)
508 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
509 fputs("\n", logfile);
510}
511
512void debug_post_eret (void)
513{
744e0915 514 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 515 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 516 if (env->CP0_Status & (1 << CP0St_ERL))
517 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
518 if (env->hflags & MIPS_HFLAG_DM)
519 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
520 if (env->hflags & MIPS_HFLAG_UM)
521 fputs(", UM\n", logfile);
522 else
24c7b0e3 523 fputs("\n", logfile);
6af0bf9c
FB		 524}
525
6af0bf9c
FB		 526void do_pmon (int function)
527{
528 function /= 2;
529 switch (function) {
530 case 2: /* TODO: char inbyte(int waitflag); */
ead9360e
TS		 531 if (env->gpr[4][env->current_tc] == 0)
532 env->gpr[2][env->current_tc] = -1;
6af0bf9c
FB		 533 /* Fall through */
534 case 11: /* TODO: char inbyte (void); */
ead9360e 535 env->gpr[2][env->current_tc] = -1;
6af0bf9c
FB		 536 break;
537 case 3:
538 case 12:
ead9360e 539 printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF));
6af0bf9c
FB		 540 break;
541 case 17:
542 break;
543 case 158:
544 {
ead9360e 545 unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc];
6af0bf9c
FB		 546 printf("%s", fmt);
547 }
548 break;
549 }
550}
e37e863f 551
5fafdf24 552#if !defined(CONFIG_USER_ONLY)
e37e863f 553
4ad40f36
FB		 554static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
555
e37e863f 556#define MMUSUFFIX _mmu
4ad40f36 557#define ALIGNED_ONLY
e37e863f
FB		 558
559#define SHIFT 0
560#include "softmmu_template.h"
561
562#define SHIFT 1
563#include "softmmu_template.h"
564
565#define SHIFT 2
566#include "softmmu_template.h"
567
568#define SHIFT 3
569#include "softmmu_template.h"
570
4ad40f36
FB		 571static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
572{
573 env->CP0_BadVAddr = addr;
574 do_restore_state (retaddr);
575 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
576}
577
e37e863f
FB		 578void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
579{
580 TranslationBlock *tb;
581 CPUState *saved_env;
582 unsigned long pc;
583 int ret;
584
585 /* XXX: hack to restore env in all cases, even if not called from
586 generated code */
587 saved_env = env;
588 env = cpu_single_env;
589 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
590 if (ret) {
591 if (retaddr) {
592 /* now we have a real cpu fault */
593 pc = (unsigned long)retaddr;
594 tb = tb_find_pc(pc);
595 if (tb) {
596 /* the PC is inside the translated code. It means that we have
597 a virtual CPU fault */
598 cpu_restore_state(tb, env, pc, NULL);
599 }
600 }
601 do_raise_exception_err(env->exception_index, env->error_code);
602 }
603 env = saved_env;
604}
605
606#endif
fd4a04eb
TS		 607
608/* Complex FPU operations which may need stack space. */
609
8dfdb87c
TS		 610#define FLOAT_SIGN32 (1 << 31)
611#define FLOAT_SIGN64 (1ULL << 63)
612#define FLOAT_ONE32 (0x3f8 << 20)
613#define FLOAT_ONE64 (0x3ffULL << 52)
614#define FLOAT_TWO32 (1 << 30)
615#define FLOAT_TWO64 (1ULL << 62)
616
fd4a04eb
TS		 617/* convert MIPS rounding mode in FCR31 to IEEE library */
618unsigned int ieee_rm[] = {
619 float_round_nearest_even,
620 float_round_to_zero,
621 float_round_up,
622 float_round_down
623};
624
625#define RESTORE_ROUNDING_MODE \
ead9360e 626 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
fd4a04eb 627
ead9360e 628void do_cfc1 (int reg)
fd4a04eb 629{
ead9360e
TS		 630 switch (reg) {
631 case 0:
632 T0 = (int32_t)env->fpu->fcr0;
633 break;
634 case 25:
635 T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
636 break;
637 case 26:
638 T0 = env->fpu->fcr31 & 0x0003f07c;
639 break;
640 case 28:
641 T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
642 break;
643 default:
644 T0 = (int32_t)env->fpu->fcr31;
645 break;
646 }
647}
648
649void do_ctc1 (int reg)
650{
651 switch(reg) {
fd4a04eb
TS		 652 case 25:
653 if (T0 & 0xffffff00)
654 return;
ead9360e 655 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
fd4a04eb
TS		 656 ((T0 & 0x1) << 23);
657 break;
658 case 26:
659 if (T0 & 0x007c0000)
660 return;
ead9360e 661 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
fd4a04eb
TS		 662 break;
663 case 28:
664 if (T0 & 0x007c0000)
665 return;
ead9360e 666 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
fd4a04eb
TS		 667 ((T0 & 0x4) << 22);
668 break;
669 case 31:
670 if (T0 & 0x007c0000)
671 return;
ead9360e 672 env->fpu->fcr31 = T0;
fd4a04eb
TS		 673 break;
674 default:
675 return;
676 }
677 /* set rounding mode */
678 RESTORE_ROUNDING_MODE;
ead9360e
TS		 679 set_float_exception_flags(0, &env->fpu->fp_status);
680 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
fd4a04eb
TS		 681 do_raise_exception(EXCP_FPE);
682}
683
684inline char ieee_ex_to_mips(char xcpt)
685{
686 return (xcpt & float_flag_inexact) >> 5 |
687 (xcpt & float_flag_underflow) >> 3 |
688 (xcpt & float_flag_overflow) >> 1 |
689 (xcpt & float_flag_divbyzero) << 1 |
690 (xcpt & float_flag_invalid) << 4;
691}
692
693inline char mips_ex_to_ieee(char xcpt)
694{
695 return (xcpt & FP_INEXACT) << 5 |
696 (xcpt & FP_UNDERFLOW) << 3 |
697 (xcpt & FP_OVERFLOW) << 1 |
698 (xcpt & FP_DIV0) >> 1 |
699 (xcpt & FP_INVALID) >> 4;
700}
701
702inline void update_fcr31(void)
703{
ead9360e 704 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
fd4a04eb 705
ead9360e
TS		 706 SET_FP_CAUSE(env->fpu->fcr31, tmp);
707 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
fd4a04eb
TS		 708 do_raise_exception(EXCP_FPE);
709 else
ead9360e 710 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
fd4a04eb
TS		 711}
712
713#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
714
715FLOAT_OP(cvtd, s)
716{
ead9360e
TS		 717 set_float_exception_flags(0, &env->fpu->fp_status);
718 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 719 update_fcr31();
720}
721FLOAT_OP(cvtd, w)
722{
ead9360e
TS		 723 set_float_exception_flags(0, &env->fpu->fp_status);
724 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 725 update_fcr31();
726}
727FLOAT_OP(cvtd, l)
728{
ead9360e
TS		 729 set_float_exception_flags(0, &env->fpu->fp_status);
730 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 731 update_fcr31();
732}
733FLOAT_OP(cvtl, d)
734{
ead9360e
TS		 735 set_float_exception_flags(0, &env->fpu->fp_status);
736 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb 737 update_fcr31();
ead9360e 738 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 739 DT2 = 0x7fffffffffffffffULL;
740}
741FLOAT_OP(cvtl, s)
742{
ead9360e
TS		 743 set_float_exception_flags(0, &env->fpu->fp_status);
744 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb 745 update_fcr31();
ead9360e 746 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 747 DT2 = 0x7fffffffffffffffULL;
748}
749
750FLOAT_OP(cvtps, pw)
751{
ead9360e
TS		 752 set_float_exception_flags(0, &env->fpu->fp_status);
753 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
754 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
fd4a04eb
TS		 755 update_fcr31();
756}
757FLOAT_OP(cvtpw, ps)
758{
ead9360e
TS		 759 set_float_exception_flags(0, &env->fpu->fp_status);
760 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
761 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
fd4a04eb 762 update_fcr31();
ead9360e 763 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 764 WT2 = 0x7fffffff;
765}
766FLOAT_OP(cvts, d)
767{
ead9360e
TS		 768 set_float_exception_flags(0, &env->fpu->fp_status);
769 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 770 update_fcr31();
771}
772FLOAT_OP(cvts, w)
773{
ead9360e
TS		 774 set_float_exception_flags(0, &env->fpu->fp_status);
775 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 776 update_fcr31();
777}
778FLOAT_OP(cvts, l)
779{
ead9360e
TS		 780 set_float_exception_flags(0, &env->fpu->fp_status);
781 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 782 update_fcr31();
783}
784FLOAT_OP(cvts, pl)
785{
ead9360e 786 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 787 WT2 = WT0;
788 update_fcr31();
789}
790FLOAT_OP(cvts, pu)
791{
ead9360e 792 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 793 WT2 = WTH0;
794 update_fcr31();
795}
796FLOAT_OP(cvtw, s)
797{
ead9360e
TS		 798 set_float_exception_flags(0, &env->fpu->fp_status);
799 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb 800 update_fcr31();
ead9360e 801 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 802 WT2 = 0x7fffffff;
803}
804FLOAT_OP(cvtw, d)
805{
ead9360e
TS		 806 set_float_exception_flags(0, &env->fpu->fp_status);
807 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb 808 update_fcr31();
ead9360e 809 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 810 WT2 = 0x7fffffff;
811}
812
813FLOAT_OP(roundl, d)
814{
ead9360e
TS		 815 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
816 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 817 RESTORE_ROUNDING_MODE;
818 update_fcr31();
ead9360e 819 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 820 DT2 = 0x7fffffffffffffffULL;
821}
822FLOAT_OP(roundl, s)
823{
ead9360e
TS		 824 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
825 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 826 RESTORE_ROUNDING_MODE;
827 update_fcr31();
ead9360e 828 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 829 DT2 = 0x7fffffffffffffffULL;
830}
831FLOAT_OP(roundw, d)
832{
ead9360e
TS		 833 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
834 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 835 RESTORE_ROUNDING_MODE;
836 update_fcr31();
ead9360e 837 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 838 WT2 = 0x7fffffff;
839}
840FLOAT_OP(roundw, s)
841{
ead9360e
TS		 842 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
843 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 844 RESTORE_ROUNDING_MODE;
845 update_fcr31();
ead9360e 846 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 847 WT2 = 0x7fffffff;
848}
849
850FLOAT_OP(truncl, d)
851{
ead9360e 852 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 853 update_fcr31();
ead9360e 854 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 855 DT2 = 0x7fffffffffffffffULL;
856}
857FLOAT_OP(truncl, s)
858{
ead9360e 859 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 860 update_fcr31();
ead9360e 861 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 862 DT2 = 0x7fffffffffffffffULL;
863}
864FLOAT_OP(truncw, d)
865{
ead9360e 866 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 867 update_fcr31();
ead9360e 868 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 869 WT2 = 0x7fffffff;
870}
871FLOAT_OP(truncw, s)
872{
ead9360e 873 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 874 update_fcr31();
ead9360e 875 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 876 WT2 = 0x7fffffff;
877}
878
879FLOAT_OP(ceill, d)
880{
ead9360e
TS		 881 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
882 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 883 RESTORE_ROUNDING_MODE;
884 update_fcr31();
ead9360e 885 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 886 DT2 = 0x7fffffffffffffffULL;
887}
888FLOAT_OP(ceill, s)
889{
ead9360e
TS		 890 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
891 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 892 RESTORE_ROUNDING_MODE;
893 update_fcr31();
ead9360e 894 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 895 DT2 = 0x7fffffffffffffffULL;
896}
897FLOAT_OP(ceilw, d)
898{
ead9360e
TS		 899 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
900 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 901 RESTORE_ROUNDING_MODE;
902 update_fcr31();
ead9360e 903 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 904 WT2 = 0x7fffffff;
905}
906FLOAT_OP(ceilw, s)
907{
ead9360e
TS		 908 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
909 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 910 RESTORE_ROUNDING_MODE;
911 update_fcr31();
ead9360e 912 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 913 WT2 = 0x7fffffff;
914}
915
916FLOAT_OP(floorl, d)
917{
ead9360e
TS		 918 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
919 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 920 RESTORE_ROUNDING_MODE;
921 update_fcr31();
ead9360e 922 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 923 DT2 = 0x7fffffffffffffffULL;
924}
925FLOAT_OP(floorl, s)
926{
ead9360e
TS		 927 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
928 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 929 RESTORE_ROUNDING_MODE;
930 update_fcr31();
ead9360e 931 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 932 DT2 = 0x7fffffffffffffffULL;
933}
934FLOAT_OP(floorw, d)
935{
ead9360e
TS		 936 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
937 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 938 RESTORE_ROUNDING_MODE;
939 update_fcr31();
ead9360e 940 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 941 WT2 = 0x7fffffff;
942}
943FLOAT_OP(floorw, s)
944{
ead9360e
TS		 945 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
946 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 947 RESTORE_ROUNDING_MODE;
948 update_fcr31();
ead9360e 949 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
fd4a04eb
TS		 950 WT2 = 0x7fffffff;
951}
952
8dfdb87c
TS		 953/* MIPS specific unary operations */
954FLOAT_OP(recip, d)
955{
ead9360e
TS		 956 set_float_exception_flags(0, &env->fpu->fp_status);
957 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 958 update_fcr31();
959}
960FLOAT_OP(recip, s)
961{
ead9360e
TS		 962 set_float_exception_flags(0, &env->fpu->fp_status);
963 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c 964 update_fcr31();
57fa1fb3 965}
57fa1fb3 966
8dfdb87c
TS		 967FLOAT_OP(rsqrt, d)
968{
ead9360e
TS		 969 set_float_exception_flags(0, &env->fpu->fp_status);
970 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
971 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 972 update_fcr31();
973}
974FLOAT_OP(rsqrt, s)
975{
ead9360e
TS		 976 set_float_exception_flags(0, &env->fpu->fp_status);
977 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
978 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 979 update_fcr31();
980}
981
982FLOAT_OP(recip1, d)
983{
ead9360e
TS		 984 set_float_exception_flags(0, &env->fpu->fp_status);
985 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 986 update_fcr31();
987}
988FLOAT_OP(recip1, s)
989{
ead9360e
TS		 990 set_float_exception_flags(0, &env->fpu->fp_status);
991 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c
TS		 992 update_fcr31();
993}
994FLOAT_OP(recip1, ps)
995{
ead9360e
TS		 996 set_float_exception_flags(0, &env->fpu->fp_status);
997 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
998 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
8dfdb87c
TS		 999 update_fcr31();
1000}
1001
1002FLOAT_OP(rsqrt1, d)
1003{
ead9360e
TS		 1004 set_float_exception_flags(0, &env->fpu->fp_status);
1005 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1006 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 1007 update_fcr31();
1008}
1009FLOAT_OP(rsqrt1, s)
1010{
ead9360e
TS		 1011 set_float_exception_flags(0, &env->fpu->fp_status);
1012 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1013 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 1014 update_fcr31();
1015}
1016FLOAT_OP(rsqrt1, ps)
1017{
ead9360e
TS		 1018 set_float_exception_flags(0, &env->fpu->fp_status);
1019 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1020 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1021 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1022 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
8dfdb87c 1023 update_fcr31();
57fa1fb3 1024}
57fa1fb3 1025
fd4a04eb
TS		 1026/* binary operations */
1027#define FLOAT_BINOP(name) \
1028FLOAT_OP(name, d) \
1029{ \
ead9360e
TS		 1030 set_float_exception_flags(0, &env->fpu->fp_status); \
1031 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1032 update_fcr31(); \
1033 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1034 FDT2 = 0x7ff7ffffffffffffULL; \
fd4a04eb
TS		 1035} \
1036FLOAT_OP(name, s) \
1037{ \
ead9360e
TS		 1038 set_float_exception_flags(0, &env->fpu->fp_status); \
1039 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1040 update_fcr31(); \
1041 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1042 FST2 = 0x7fbfffff; \
fd4a04eb
TS		 1043} \
1044FLOAT_OP(name, ps) \
1045{ \
ead9360e
TS		 1046 set_float_exception_flags(0, &env->fpu->fp_status); \
1047 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1048 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
fd4a04eb 1049 update_fcr31(); \
ead9360e
TS		 1050 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
1051 FST2 = 0x7fbfffff; \
1052 FSTH2 = 0x7fbfffff; \
3a5b360d 1053 } \
fd4a04eb
TS		 1054}
1055FLOAT_BINOP(add)
1056FLOAT_BINOP(sub)
1057FLOAT_BINOP(mul)
1058FLOAT_BINOP(div)
1059#undef FLOAT_BINOP
1060
8dfdb87c
TS		 1061/* MIPS specific binary operations */
1062FLOAT_OP(recip2, d)
1063{
ead9360e
TS		 1064 set_float_exception_flags(0, &env->fpu->fp_status);
1065 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1066 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
8dfdb87c
TS		 1067 update_fcr31();
1068}
1069FLOAT_OP(recip2, s)
1070{
ead9360e
TS		 1071 set_float_exception_flags(0, &env->fpu->fp_status);
1072 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1073 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
8dfdb87c
TS		 1074 update_fcr31();
1075}
1076FLOAT_OP(recip2, ps)
1077{
ead9360e
TS		 1078 set_float_exception_flags(0, &env->fpu->fp_status);
1079 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1080 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1081 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1082 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
8dfdb87c
TS		 1083 update_fcr31();
1084}
1085
1086FLOAT_OP(rsqrt2, d)
1087{
ead9360e
TS		 1088 set_float_exception_flags(0, &env->fpu->fp_status);
1089 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1090 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
1091 FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
8dfdb87c
TS		 1092 update_fcr31();
1093}
1094FLOAT_OP(rsqrt2, s)
1095{
ead9360e
TS		 1096 set_float_exception_flags(0, &env->fpu->fp_status);
1097 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1098 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1099 FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
8dfdb87c
TS		 1100 update_fcr31();
1101}
1102FLOAT_OP(rsqrt2, ps)
1103{
ead9360e
TS		 1104 set_float_exception_flags(0, &env->fpu->fp_status);
1105 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1106 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1107 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1108 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
1109 FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1110 FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
8dfdb87c 1111 update_fcr31();
57fa1fb3 1112}
57fa1fb3 1113
fd4a04eb
TS		 1114FLOAT_OP(addr, ps)
1115{
ead9360e
TS		 1116 set_float_exception_flags(0, &env->fpu->fp_status);
1117 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1118 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
fd4a04eb
TS		 1119 update_fcr31();
1120}
1121
57fa1fb3
TS		 1122FLOAT_OP(mulr, ps)
1123{
ead9360e
TS		 1124 set_float_exception_flags(0, &env->fpu->fp_status);
1125 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1126 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
57fa1fb3
TS		 1127 update_fcr31();
1128}
1129
8dfdb87c 1130/* compare operations */
fd4a04eb
TS		 1131#define FOP_COND_D(op, cond) \
1132void do_cmp_d_ ## op (long cc) \
1133{ \
1134 int c = cond; \
1135 update_fcr31(); \
1136 if (c) \
ead9360e 1137 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1138 else \
ead9360e 1139 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1140} \
1141void do_cmpabs_d_ ## op (long cc) \
1142{ \
1143 int c; \
8dfdb87c
TS		 1144 FDT0 &= ~FLOAT_SIGN64; \
1145 FDT1 &= ~FLOAT_SIGN64; \
fd4a04eb
TS		 1146 c = cond; \
1147 update_fcr31(); \
1148 if (c) \
ead9360e 1149 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1150 else \
ead9360e 1151 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1152}
1153
1154int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1155{
1156 if (float64_is_signaling_nan(a) ||
1157 float64_is_signaling_nan(b) ||
1158 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1159 float_raise(float_flag_invalid, status);
1160 return 1;
1161 } else if (float64_is_nan(a) || float64_is_nan(b)) {
1162 return 1;
1163 } else {
1164 return 0;
1165 }
1166}
1167
1168/* NOTE: the comma operator will make "cond" to eval to false,
1169 * but float*_is_unordered() is still called. */
ead9360e
TS		 1170FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
1171FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
1172FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1173FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1174FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1175FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1176FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1177FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 1178/* NOTE: the comma operator will make "cond" to eval to false,
1179 * but float*_is_unordered() is still called. */
ead9360e
TS		 1180FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
1181FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
1182FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1183FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1184FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1185FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1186FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1187FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 1188
1189#define FOP_COND_S(op, cond) \
1190void do_cmp_s_ ## op (long cc) \
1191{ \
1192 int c = cond; \
1193 update_fcr31(); \
1194 if (c) \
ead9360e 1195 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1196 else \
ead9360e 1197 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1198} \
1199void do_cmpabs_s_ ## op (long cc) \
1200{ \
1201 int c; \
8dfdb87c
TS		 1202 FST0 &= ~FLOAT_SIGN32; \
1203 FST1 &= ~FLOAT_SIGN32; \
fd4a04eb
TS		 1204 c = cond; \
1205 update_fcr31(); \
1206 if (c) \
ead9360e 1207 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1208 else \
ead9360e 1209 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1210}
1211
1212flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1213{
fd4a04eb
TS		 1214 if (float32_is_signaling_nan(a) ||
1215 float32_is_signaling_nan(b) ||
1216 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1217 float_raise(float_flag_invalid, status);
1218 return 1;
1219 } else if (float32_is_nan(a) || float32_is_nan(b)) {
1220 return 1;
1221 } else {
1222 return 0;
1223 }
1224}
1225
1226/* NOTE: the comma operator will make "cond" to eval to false,
1227 * but float*_is_unordered() is still called. */
ead9360e
TS		 1228FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
1229FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
1230FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1231FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1232FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1233FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1234FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1235FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 1236/* NOTE: the comma operator will make "cond" to eval to false,
1237 * but float*_is_unordered() is still called. */
ead9360e
TS		 1238FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
1239FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
1240FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1241FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1242FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1243FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1244FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1245FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 1246
1247#define FOP_COND_PS(op, condl, condh) \
1248void do_cmp_ps_ ## op (long cc) \
1249{ \
1250 int cl = condl; \
1251 int ch = condh; \
1252 update_fcr31(); \
1253 if (cl) \
ead9360e 1254 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1255 else \
ead9360e 1256 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 1257 if (ch) \
ead9360e 1258 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 1259 else \
ead9360e 1260 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 1261} \
1262void do_cmpabs_ps_ ## op (long cc) \
1263{ \
1264 int cl, ch; \
8dfdb87c
TS		 1265 FST0 &= ~FLOAT_SIGN32; \
1266 FSTH0 &= ~FLOAT_SIGN32; \
1267 FST1 &= ~FLOAT_SIGN32; \
1268 FSTH1 &= ~FLOAT_SIGN32; \
fd4a04eb
TS		 1269 cl = condl; \
1270 ch = condh; \
1271 update_fcr31(); \
1272 if (cl) \
ead9360e 1273 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1274 else \
ead9360e 1275 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 1276 if (ch) \
ead9360e 1277 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 1278 else \
ead9360e 1279 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 1280}
1281
1282/* NOTE: the comma operator will make "cond" to eval to false,
1283 * but float*_is_unordered() is still called. */
ead9360e
TS		 1284FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
1285 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1286FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
1287 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
1288FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1289 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1290FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1291 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1292FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1293 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1294FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1295 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1296FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1297 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1298FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1299 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
fd4a04eb
TS		 1300/* NOTE: the comma operator will make "cond" to eval to false,
1301 * but float*_is_unordered() is still called. */
ead9360e
TS		 1302FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
1303 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1304FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
1305 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
1306FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1307 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1308FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1309 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1310FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1311 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1312FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1313 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1314FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1315 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1316FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1317 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
Qemu copy for testing