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525bd324 AG |
1 | /* |
2 | * Moxie helper routines. | |
3 | * | |
4 | * Copyright (c) 2008, 2009, 2010, 2013 Anthony Green | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <stdio.h> | |
21 | #include <string.h> | |
22 | #include <assert.h> | |
23 | ||
24 | #include "config.h" | |
25 | #include "cpu.h" | |
26 | #include "mmu.h" | |
27 | #include "exec/exec-all.h" | |
b1669e5e | 28 | #include "exec/softmmu_exec.h" |
525bd324 AG |
29 | #include "qemu/host-utils.h" |
30 | #include "helper.h" | |
31 | ||
32 | #define MMUSUFFIX _mmu | |
33 | ||
34 | #define SHIFT 0 | |
35 | #include "exec/softmmu_template.h" | |
36 | ||
37 | #define SHIFT 1 | |
38 | #include "exec/softmmu_template.h" | |
39 | ||
40 | #define SHIFT 2 | |
41 | #include "exec/softmmu_template.h" | |
42 | ||
43 | #define SHIFT 3 | |
44 | #include "exec/softmmu_template.h" | |
45 | ||
46 | /* Try to fill the TLB and return an exception if error. If retaddr is | |
47 | NULL, it means that the function was called in C code (i.e. not | |
48 | from generated code or from helper.c) */ | |
49 | void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx, | |
50 | uintptr_t retaddr) | |
51 | { | |
7510454e | 52 | MoxieCPU *cpu = moxie_env_get_cpu(env); |
525bd324 AG |
53 | int ret; |
54 | ||
7510454e | 55 | ret = moxie_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); |
525bd324 AG |
56 | if (unlikely(ret)) { |
57 | if (retaddr) { | |
58 | cpu_restore_state(env, retaddr); | |
59 | } | |
60 | } | |
61 | cpu_loop_exit(env); | |
62 | } | |
63 | ||
64 | void helper_raise_exception(CPUMoxieState *env, int ex) | |
65 | { | |
66 | env->exception_index = ex; | |
67 | /* Stash the exception type. */ | |
68 | env->sregs[2] = ex; | |
69 | /* Stash the address where the exception occurred. */ | |
70 | cpu_restore_state(env, GETPC()); | |
71 | env->sregs[5] = env->pc; | |
72 | /* Jump the the exception handline routine. */ | |
73 | env->pc = env->sregs[1]; | |
74 | cpu_loop_exit(env); | |
75 | } | |
76 | ||
77 | uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b) | |
78 | { | |
79 | if (unlikely(b == 0)) { | |
80 | helper_raise_exception(env, MOXIE_EX_DIV0); | |
81 | return 0; | |
82 | } | |
83 | if (unlikely(a == INT_MIN && b == -1)) { | |
84 | return INT_MIN; | |
85 | } | |
86 | ||
87 | return (int32_t)a / (int32_t)b; | |
88 | } | |
89 | ||
90 | uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b) | |
91 | { | |
92 | if (unlikely(b == 0)) { | |
93 | helper_raise_exception(env, MOXIE_EX_DIV0); | |
94 | return 0; | |
95 | } | |
96 | return a / b; | |
97 | } | |
98 | ||
99 | void helper_debug(CPUMoxieState *env) | |
100 | { | |
101 | env->exception_index = EXCP_DEBUG; | |
102 | cpu_loop_exit(env); | |
103 | } | |
104 | ||
105 | #if defined(CONFIG_USER_ONLY) | |
106 | ||
7510454e | 107 | void moxie_cpu_do_interrupt(CPUState *cs) |
525bd324 AG |
108 | { |
109 | env->exception_index = -1; | |
110 | } | |
111 | ||
7510454e | 112 | int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
525bd324 AG |
113 | int rw, int mmu_idx) |
114 | { | |
7510454e | 115 | MoxieCPU *cpu = MOXIE_CPU(cs); |
878096ee | 116 | |
7510454e AF |
117 | cpu->env.exception_index = 0xaa; |
118 | cpu->env.debug1 = address; | |
119 | cpu_dump_state(cs, stderr, fprintf, 0); | |
525bd324 AG |
120 | return 1; |
121 | } | |
122 | ||
525bd324 AG |
123 | #else /* !CONFIG_USER_ONLY */ |
124 | ||
7510454e | 125 | int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
525bd324 AG |
126 | int rw, int mmu_idx) |
127 | { | |
7510454e AF |
128 | MoxieCPU *cpu = MOXIE_CPU(cs); |
129 | CPUMoxieState *env = &cpu->env; | |
525bd324 AG |
130 | MoxieMMUResult res; |
131 | int prot, miss; | |
132 | target_ulong phy; | |
133 | int r = 1; | |
134 | ||
135 | address &= TARGET_PAGE_MASK; | |
136 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
137 | miss = moxie_mmu_translate(&res, env, address, rw, mmu_idx); | |
138 | if (miss) { | |
139 | /* handle the miss. */ | |
140 | phy = 0; | |
141 | env->exception_index = MOXIE_EX_MMU_MISS; | |
142 | } else { | |
143 | phy = res.phy; | |
144 | r = 0; | |
145 | } | |
146 | tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); | |
147 | return r; | |
148 | } | |
149 | ||
150 | ||
53574064 | 151 | void moxie_cpu_do_interrupt(CPUState *cs) |
525bd324 | 152 | { |
53574064 DH |
153 | MoxieCPU *cpu = MOXIE_CPU(cs); |
154 | CPUMoxieState *env = &cpu->env; | |
155 | ||
525bd324 AG |
156 | switch (env->exception_index) { |
157 | case MOXIE_EX_BREAK: | |
158 | break; | |
159 | default: | |
160 | break; | |
161 | } | |
162 | } | |
163 | ||
00b941e5 | 164 | hwaddr moxie_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
525bd324 | 165 | { |
00b941e5 | 166 | MoxieCPU *cpu = MOXIE_CPU(cs); |
525bd324 AG |
167 | uint32_t phy = addr; |
168 | MoxieMMUResult res; | |
169 | int miss; | |
00b941e5 AF |
170 | |
171 | miss = moxie_mmu_translate(&res, &cpu->env, addr, 0, 0); | |
525bd324 AG |
172 | if (!miss) { |
173 | phy = res.phy; | |
174 | } | |
175 | return phy; | |
176 | } | |
177 | #endif |