]>
Commit | Line | Data |
---|---|---|
e67db06e JL |
1 | /* |
2 | * QEMU OpenRISC CPU | |
3 | * | |
4 | * Copyright (c) 2012 Jia Liu <proljc@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
21 | #include "qemu-common.h" | |
22 | ||
f45748f1 AF |
23 | static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) |
24 | { | |
25 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); | |
26 | ||
27 | cpu->env.pc = value; | |
28 | } | |
29 | ||
e67db06e JL |
30 | /* CPUClass::reset() */ |
31 | static void openrisc_cpu_reset(CPUState *s) | |
32 | { | |
33 | OpenRISCCPU *cpu = OPENRISC_CPU(s); | |
34 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); | |
35 | ||
e67db06e JL |
36 | occ->parent_reset(s); |
37 | ||
38 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); | |
39 | ||
40 | tlb_flush(&cpu->env, 1); | |
41 | /*tb_flush(&cpu->env); FIXME: Do we need it? */ | |
42 | ||
43 | cpu->env.pc = 0x100; | |
44 | cpu->env.sr = SR_FO | SR_SM; | |
45 | cpu->env.exception_index = -1; | |
46 | ||
47 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; | |
48 | cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; | |
49 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); | |
50 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); | |
51 | ||
52 | #ifndef CONFIG_USER_ONLY | |
53 | cpu->env.picmr = 0x00000000; | |
54 | cpu->env.picsr = 0x00000000; | |
55 | ||
56 | cpu->env.ttmr = 0x00000000; | |
57 | cpu->env.ttcr = 0x00000000; | |
58 | #endif | |
59 | } | |
60 | ||
61 | static inline void set_feature(OpenRISCCPU *cpu, int feature) | |
62 | { | |
63 | cpu->feature |= feature; | |
64 | cpu->env.cpucfgr = cpu->feature; | |
65 | } | |
66 | ||
c296262b | 67 | static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) |
e67db06e | 68 | { |
14a10fc3 | 69 | CPUState *cs = CPU(dev); |
c296262b | 70 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); |
e67db06e | 71 | |
14a10fc3 AF |
72 | qemu_init_vcpu(cs); |
73 | cpu_reset(cs); | |
c296262b AF |
74 | |
75 | occ->parent_realize(dev, errp); | |
e67db06e JL |
76 | } |
77 | ||
78 | static void openrisc_cpu_initfn(Object *obj) | |
79 | { | |
c05efcb1 | 80 | CPUState *cs = CPU(obj); |
e67db06e JL |
81 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); |
82 | static int inited; | |
83 | ||
c05efcb1 | 84 | cs->env_ptr = &cpu->env; |
e67db06e JL |
85 | cpu_exec_init(&cpu->env); |
86 | ||
87 | #ifndef CONFIG_USER_ONLY | |
88 | cpu_openrisc_mmu_init(cpu); | |
89 | #endif | |
90 | ||
91 | if (tcg_enabled() && !inited) { | |
92 | inited = 1; | |
93 | openrisc_translate_init(); | |
94 | } | |
95 | } | |
96 | ||
97 | /* CPU models */ | |
bd039ce0 AF |
98 | |
99 | static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) | |
100 | { | |
101 | ObjectClass *oc; | |
071b3364 | 102 | char *typename; |
bd039ce0 AF |
103 | |
104 | if (cpu_model == NULL) { | |
105 | return NULL; | |
106 | } | |
107 | ||
071b3364 DZ |
108 | typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model); |
109 | oc = object_class_by_name(typename); | |
9b146e9a | 110 | g_free(typename); |
c432b784 AF |
111 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || |
112 | object_class_is_abstract(oc))) { | |
bd039ce0 AF |
113 | return NULL; |
114 | } | |
115 | return oc; | |
116 | } | |
117 | ||
e67db06e JL |
118 | static void or1200_initfn(Object *obj) |
119 | { | |
120 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
121 | ||
122 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
123 | set_feature(cpu, OPENRISC_FEATURE_OF32S); | |
124 | } | |
125 | ||
126 | static void openrisc_any_initfn(Object *obj) | |
127 | { | |
128 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
129 | ||
130 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
131 | } | |
132 | ||
133 | typedef struct OpenRISCCPUInfo { | |
134 | const char *name; | |
135 | void (*initfn)(Object *obj); | |
136 | } OpenRISCCPUInfo; | |
137 | ||
138 | static const OpenRISCCPUInfo openrisc_cpus[] = { | |
139 | { .name = "or1200", .initfn = or1200_initfn }, | |
140 | { .name = "any", .initfn = openrisc_any_initfn }, | |
141 | }; | |
142 | ||
143 | static void openrisc_cpu_class_init(ObjectClass *oc, void *data) | |
144 | { | |
145 | OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); | |
146 | CPUClass *cc = CPU_CLASS(occ); | |
c296262b AF |
147 | DeviceClass *dc = DEVICE_CLASS(oc); |
148 | ||
149 | occ->parent_realize = dc->realize; | |
150 | dc->realize = openrisc_cpu_realizefn; | |
e67db06e JL |
151 | |
152 | occ->parent_reset = cc->reset; | |
153 | cc->reset = openrisc_cpu_reset; | |
bd039ce0 AF |
154 | |
155 | cc->class_by_name = openrisc_cpu_class_by_name; | |
97a8ea5a | 156 | cc->do_interrupt = openrisc_cpu_do_interrupt; |
878096ee | 157 | cc->dump_state = openrisc_cpu_dump_state; |
f45748f1 | 158 | cc->set_pc = openrisc_cpu_set_pc; |
5b50e790 AF |
159 | cc->gdb_read_register = openrisc_cpu_gdb_read_register; |
160 | cc->gdb_write_register = openrisc_cpu_gdb_write_register; | |
00b941e5 AF |
161 | #ifndef CONFIG_USER_ONLY |
162 | cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; | |
163 | dc->vmsd = &vmstate_openrisc_cpu; | |
164 | #endif | |
a0e372f0 | 165 | cc->gdb_num_core_regs = 32 + 3; |
e67db06e JL |
166 | } |
167 | ||
168 | static void cpu_register(const OpenRISCCPUInfo *info) | |
169 | { | |
170 | TypeInfo type_info = { | |
e67db06e JL |
171 | .parent = TYPE_OPENRISC_CPU, |
172 | .instance_size = sizeof(OpenRISCCPU), | |
173 | .instance_init = info->initfn, | |
174 | .class_size = sizeof(OpenRISCCPUClass), | |
175 | }; | |
176 | ||
478032a9 | 177 | type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name); |
a1ebd6ce | 178 | type_register(&type_info); |
478032a9 | 179 | g_free((void *)type_info.name); |
e67db06e JL |
180 | } |
181 | ||
182 | static const TypeInfo openrisc_cpu_type_info = { | |
183 | .name = TYPE_OPENRISC_CPU, | |
184 | .parent = TYPE_CPU, | |
185 | .instance_size = sizeof(OpenRISCCPU), | |
186 | .instance_init = openrisc_cpu_initfn, | |
bc755a00 | 187 | .abstract = true, |
e67db06e JL |
188 | .class_size = sizeof(OpenRISCCPUClass), |
189 | .class_init = openrisc_cpu_class_init, | |
190 | }; | |
191 | ||
192 | static void openrisc_cpu_register_types(void) | |
193 | { | |
194 | int i; | |
195 | ||
196 | type_register_static(&openrisc_cpu_type_info); | |
197 | for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) { | |
198 | cpu_register(&openrisc_cpus[i]); | |
199 | } | |
200 | } | |
201 | ||
202 | OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) | |
203 | { | |
204 | OpenRISCCPU *cpu; | |
bd039ce0 | 205 | ObjectClass *oc; |
e67db06e | 206 | |
bd039ce0 AF |
207 | oc = openrisc_cpu_class_by_name(cpu_model); |
208 | if (oc == NULL) { | |
e67db06e JL |
209 | return NULL; |
210 | } | |
bd039ce0 | 211 | cpu = OPENRISC_CPU(object_new(object_class_get_name(oc))); |
e67db06e JL |
212 | cpu->env.cpu_model_str = cpu_model; |
213 | ||
c296262b | 214 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
e67db06e JL |
215 | |
216 | return cpu; | |
217 | } | |
218 | ||
e67db06e JL |
219 | /* Sort alphabetically by type name, except for "any". */ |
220 | static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) | |
221 | { | |
222 | ObjectClass *class_a = (ObjectClass *)a; | |
223 | ObjectClass *class_b = (ObjectClass *)b; | |
224 | const char *name_a, *name_b; | |
225 | ||
226 | name_a = object_class_get_name(class_a); | |
227 | name_b = object_class_get_name(class_b); | |
478032a9 | 228 | if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { |
e67db06e | 229 | return 1; |
478032a9 | 230 | } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { |
e67db06e JL |
231 | return -1; |
232 | } else { | |
233 | return strcmp(name_a, name_b); | |
234 | } | |
235 | } | |
236 | ||
237 | static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) | |
238 | { | |
239 | ObjectClass *oc = data; | |
8486af93 | 240 | CPUListState *s = user_data; |
478032a9 AF |
241 | const char *typename; |
242 | char *name; | |
e67db06e | 243 | |
478032a9 AF |
244 | typename = object_class_get_name(oc); |
245 | name = g_strndup(typename, | |
246 | strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); | |
e67db06e | 247 | (*s->cpu_fprintf)(s->file, " %s\n", |
478032a9 AF |
248 | name); |
249 | g_free(name); | |
e67db06e JL |
250 | } |
251 | ||
252 | void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) | |
253 | { | |
8486af93 | 254 | CPUListState s = { |
e67db06e JL |
255 | .file = f, |
256 | .cpu_fprintf = cpu_fprintf, | |
257 | }; | |
258 | GSList *list; | |
259 | ||
260 | list = object_class_get_list(TYPE_OPENRISC_CPU, false); | |
261 | list = g_slist_sort(list, openrisc_cpu_list_compare); | |
262 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
263 | g_slist_foreach(list, openrisc_cpu_list_entry, &s); | |
264 | g_slist_free(list); | |
265 | } | |
266 | ||
267 | type_init(openrisc_cpu_register_types) |