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e67db06e JL |
1 | /* |
2 | * QEMU OpenRISC CPU | |
3 | * | |
4 | * Copyright (c) 2012 Jia Liu <proljc@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
21 | #include "qemu-common.h" | |
22 | ||
f45748f1 AF |
23 | static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) |
24 | { | |
25 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); | |
26 | ||
27 | cpu->env.pc = value; | |
28 | } | |
29 | ||
8c2e1b00 AF |
30 | static bool openrisc_cpu_has_work(CPUState *cs) |
31 | { | |
32 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | | |
33 | CPU_INTERRUPT_TIMER); | |
34 | } | |
35 | ||
e67db06e JL |
36 | /* CPUClass::reset() */ |
37 | static void openrisc_cpu_reset(CPUState *s) | |
38 | { | |
39 | OpenRISCCPU *cpu = OPENRISC_CPU(s); | |
40 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); | |
41 | ||
e67db06e JL |
42 | occ->parent_reset(s); |
43 | ||
f0c3c505 AF |
44 | #ifndef CONFIG_USER_ONLY |
45 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb)); | |
46 | #else | |
47 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq)); | |
48 | #endif | |
e67db06e | 49 | |
00c8cb0a | 50 | tlb_flush(s, 1); |
e67db06e JL |
51 | /*tb_flush(&cpu->env); FIXME: Do we need it? */ |
52 | ||
53 | cpu->env.pc = 0x100; | |
54 | cpu->env.sr = SR_FO | SR_SM; | |
27103424 | 55 | s->exception_index = -1; |
e67db06e JL |
56 | |
57 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; | |
58 | cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; | |
59 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); | |
60 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); | |
61 | ||
62 | #ifndef CONFIG_USER_ONLY | |
63 | cpu->env.picmr = 0x00000000; | |
64 | cpu->env.picsr = 0x00000000; | |
65 | ||
66 | cpu->env.ttmr = 0x00000000; | |
67 | cpu->env.ttcr = 0x00000000; | |
68 | #endif | |
69 | } | |
70 | ||
71 | static inline void set_feature(OpenRISCCPU *cpu, int feature) | |
72 | { | |
73 | cpu->feature |= feature; | |
74 | cpu->env.cpucfgr = cpu->feature; | |
75 | } | |
76 | ||
c296262b | 77 | static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) |
e67db06e | 78 | { |
14a10fc3 | 79 | CPUState *cs = CPU(dev); |
c296262b | 80 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); |
e67db06e | 81 | |
14a10fc3 AF |
82 | qemu_init_vcpu(cs); |
83 | cpu_reset(cs); | |
c296262b AF |
84 | |
85 | occ->parent_realize(dev, errp); | |
e67db06e JL |
86 | } |
87 | ||
88 | static void openrisc_cpu_initfn(Object *obj) | |
89 | { | |
c05efcb1 | 90 | CPUState *cs = CPU(obj); |
e67db06e JL |
91 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); |
92 | static int inited; | |
93 | ||
c05efcb1 | 94 | cs->env_ptr = &cpu->env; |
e67db06e JL |
95 | cpu_exec_init(&cpu->env); |
96 | ||
97 | #ifndef CONFIG_USER_ONLY | |
98 | cpu_openrisc_mmu_init(cpu); | |
99 | #endif | |
100 | ||
101 | if (tcg_enabled() && !inited) { | |
102 | inited = 1; | |
103 | openrisc_translate_init(); | |
104 | } | |
105 | } | |
106 | ||
107 | /* CPU models */ | |
bd039ce0 AF |
108 | |
109 | static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) | |
110 | { | |
111 | ObjectClass *oc; | |
071b3364 | 112 | char *typename; |
bd039ce0 AF |
113 | |
114 | if (cpu_model == NULL) { | |
115 | return NULL; | |
116 | } | |
117 | ||
071b3364 DZ |
118 | typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model); |
119 | oc = object_class_by_name(typename); | |
9b146e9a | 120 | g_free(typename); |
c432b784 AF |
121 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || |
122 | object_class_is_abstract(oc))) { | |
bd039ce0 AF |
123 | return NULL; |
124 | } | |
125 | return oc; | |
126 | } | |
127 | ||
e67db06e JL |
128 | static void or1200_initfn(Object *obj) |
129 | { | |
130 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
131 | ||
132 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
133 | set_feature(cpu, OPENRISC_FEATURE_OF32S); | |
134 | } | |
135 | ||
136 | static void openrisc_any_initfn(Object *obj) | |
137 | { | |
138 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
139 | ||
140 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
141 | } | |
142 | ||
143 | typedef struct OpenRISCCPUInfo { | |
144 | const char *name; | |
145 | void (*initfn)(Object *obj); | |
146 | } OpenRISCCPUInfo; | |
147 | ||
148 | static const OpenRISCCPUInfo openrisc_cpus[] = { | |
149 | { .name = "or1200", .initfn = or1200_initfn }, | |
150 | { .name = "any", .initfn = openrisc_any_initfn }, | |
151 | }; | |
152 | ||
153 | static void openrisc_cpu_class_init(ObjectClass *oc, void *data) | |
154 | { | |
155 | OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); | |
156 | CPUClass *cc = CPU_CLASS(occ); | |
c296262b AF |
157 | DeviceClass *dc = DEVICE_CLASS(oc); |
158 | ||
159 | occ->parent_realize = dc->realize; | |
160 | dc->realize = openrisc_cpu_realizefn; | |
e67db06e JL |
161 | |
162 | occ->parent_reset = cc->reset; | |
163 | cc->reset = openrisc_cpu_reset; | |
bd039ce0 AF |
164 | |
165 | cc->class_by_name = openrisc_cpu_class_by_name; | |
8c2e1b00 | 166 | cc->has_work = openrisc_cpu_has_work; |
97a8ea5a | 167 | cc->do_interrupt = openrisc_cpu_do_interrupt; |
878096ee | 168 | cc->dump_state = openrisc_cpu_dump_state; |
f45748f1 | 169 | cc->set_pc = openrisc_cpu_set_pc; |
5b50e790 AF |
170 | cc->gdb_read_register = openrisc_cpu_gdb_read_register; |
171 | cc->gdb_write_register = openrisc_cpu_gdb_write_register; | |
7510454e AF |
172 | #ifdef CONFIG_USER_ONLY |
173 | cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault; | |
174 | #else | |
00b941e5 AF |
175 | cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; |
176 | dc->vmsd = &vmstate_openrisc_cpu; | |
177 | #endif | |
a0e372f0 | 178 | cc->gdb_num_core_regs = 32 + 3; |
e67db06e JL |
179 | } |
180 | ||
181 | static void cpu_register(const OpenRISCCPUInfo *info) | |
182 | { | |
183 | TypeInfo type_info = { | |
e67db06e JL |
184 | .parent = TYPE_OPENRISC_CPU, |
185 | .instance_size = sizeof(OpenRISCCPU), | |
186 | .instance_init = info->initfn, | |
187 | .class_size = sizeof(OpenRISCCPUClass), | |
188 | }; | |
189 | ||
478032a9 | 190 | type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name); |
a1ebd6ce | 191 | type_register(&type_info); |
478032a9 | 192 | g_free((void *)type_info.name); |
e67db06e JL |
193 | } |
194 | ||
195 | static const TypeInfo openrisc_cpu_type_info = { | |
196 | .name = TYPE_OPENRISC_CPU, | |
197 | .parent = TYPE_CPU, | |
198 | .instance_size = sizeof(OpenRISCCPU), | |
199 | .instance_init = openrisc_cpu_initfn, | |
bc755a00 | 200 | .abstract = true, |
e67db06e JL |
201 | .class_size = sizeof(OpenRISCCPUClass), |
202 | .class_init = openrisc_cpu_class_init, | |
203 | }; | |
204 | ||
205 | static void openrisc_cpu_register_types(void) | |
206 | { | |
207 | int i; | |
208 | ||
209 | type_register_static(&openrisc_cpu_type_info); | |
210 | for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) { | |
211 | cpu_register(&openrisc_cpus[i]); | |
212 | } | |
213 | } | |
214 | ||
215 | OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) | |
216 | { | |
9262685b | 217 | return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)); |
e67db06e JL |
218 | } |
219 | ||
e67db06e JL |
220 | /* Sort alphabetically by type name, except for "any". */ |
221 | static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) | |
222 | { | |
223 | ObjectClass *class_a = (ObjectClass *)a; | |
224 | ObjectClass *class_b = (ObjectClass *)b; | |
225 | const char *name_a, *name_b; | |
226 | ||
227 | name_a = object_class_get_name(class_a); | |
228 | name_b = object_class_get_name(class_b); | |
478032a9 | 229 | if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { |
e67db06e | 230 | return 1; |
478032a9 | 231 | } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { |
e67db06e JL |
232 | return -1; |
233 | } else { | |
234 | return strcmp(name_a, name_b); | |
235 | } | |
236 | } | |
237 | ||
238 | static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) | |
239 | { | |
240 | ObjectClass *oc = data; | |
8486af93 | 241 | CPUListState *s = user_data; |
478032a9 AF |
242 | const char *typename; |
243 | char *name; | |
e67db06e | 244 | |
478032a9 AF |
245 | typename = object_class_get_name(oc); |
246 | name = g_strndup(typename, | |
247 | strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); | |
e67db06e | 248 | (*s->cpu_fprintf)(s->file, " %s\n", |
478032a9 AF |
249 | name); |
250 | g_free(name); | |
e67db06e JL |
251 | } |
252 | ||
253 | void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) | |
254 | { | |
8486af93 | 255 | CPUListState s = { |
e67db06e JL |
256 | .file = f, |
257 | .cpu_fprintf = cpu_fprintf, | |
258 | }; | |
259 | GSList *list; | |
260 | ||
261 | list = object_class_get_list(TYPE_OPENRISC_CPU, false); | |
262 | list = g_slist_sort(list, openrisc_cpu_list_compare); | |
263 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
264 | g_slist_foreach(list, openrisc_cpu_list_entry, &s); | |
265 | g_slist_free(list); | |
266 | } | |
267 | ||
268 | type_init(openrisc_cpu_register_types) |