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e67db06e JL |
1 | /* |
2 | * QEMU OpenRISC CPU | |
3 | * | |
4 | * Copyright (c) 2012 Jia Liu <proljc@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
21 | #include "qemu-common.h" | |
22 | ||
23 | /* CPUClass::reset() */ | |
24 | static void openrisc_cpu_reset(CPUState *s) | |
25 | { | |
26 | OpenRISCCPU *cpu = OPENRISC_CPU(s); | |
27 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); | |
28 | ||
29 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
55e5c285 | 30 | qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); |
e67db06e JL |
31 | log_cpu_state(&cpu->env, 0); |
32 | } | |
33 | ||
34 | occ->parent_reset(s); | |
35 | ||
36 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); | |
37 | ||
38 | tlb_flush(&cpu->env, 1); | |
39 | /*tb_flush(&cpu->env); FIXME: Do we need it? */ | |
40 | ||
41 | cpu->env.pc = 0x100; | |
42 | cpu->env.sr = SR_FO | SR_SM; | |
43 | cpu->env.exception_index = -1; | |
44 | ||
45 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; | |
46 | cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; | |
47 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); | |
48 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); | |
49 | ||
50 | #ifndef CONFIG_USER_ONLY | |
51 | cpu->env.picmr = 0x00000000; | |
52 | cpu->env.picsr = 0x00000000; | |
53 | ||
54 | cpu->env.ttmr = 0x00000000; | |
55 | cpu->env.ttcr = 0x00000000; | |
56 | #endif | |
57 | } | |
58 | ||
59 | static inline void set_feature(OpenRISCCPU *cpu, int feature) | |
60 | { | |
61 | cpu->feature |= feature; | |
62 | cpu->env.cpucfgr = cpu->feature; | |
63 | } | |
64 | ||
c296262b | 65 | static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) |
e67db06e | 66 | { |
c296262b AF |
67 | OpenRISCCPU *cpu = OPENRISC_CPU(dev); |
68 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); | |
e67db06e JL |
69 | |
70 | qemu_init_vcpu(&cpu->env); | |
71 | cpu_reset(CPU(cpu)); | |
c296262b AF |
72 | |
73 | occ->parent_realize(dev, errp); | |
e67db06e JL |
74 | } |
75 | ||
76 | static void openrisc_cpu_initfn(Object *obj) | |
77 | { | |
c05efcb1 | 78 | CPUState *cs = CPU(obj); |
e67db06e JL |
79 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); |
80 | static int inited; | |
81 | ||
c05efcb1 | 82 | cs->env_ptr = &cpu->env; |
e67db06e JL |
83 | cpu_exec_init(&cpu->env); |
84 | ||
85 | #ifndef CONFIG_USER_ONLY | |
86 | cpu_openrisc_mmu_init(cpu); | |
87 | #endif | |
88 | ||
89 | if (tcg_enabled() && !inited) { | |
90 | inited = 1; | |
91 | openrisc_translate_init(); | |
92 | } | |
93 | } | |
94 | ||
95 | /* CPU models */ | |
bd039ce0 AF |
96 | |
97 | static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) | |
98 | { | |
99 | ObjectClass *oc; | |
100 | ||
101 | if (cpu_model == NULL) { | |
102 | return NULL; | |
103 | } | |
104 | ||
105 | oc = object_class_by_name(cpu_model); | |
c432b784 AF |
106 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || |
107 | object_class_is_abstract(oc))) { | |
bd039ce0 AF |
108 | return NULL; |
109 | } | |
110 | return oc; | |
111 | } | |
112 | ||
e67db06e JL |
113 | static void or1200_initfn(Object *obj) |
114 | { | |
115 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
116 | ||
117 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
118 | set_feature(cpu, OPENRISC_FEATURE_OF32S); | |
119 | } | |
120 | ||
121 | static void openrisc_any_initfn(Object *obj) | |
122 | { | |
123 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
124 | ||
125 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
126 | } | |
127 | ||
128 | typedef struct OpenRISCCPUInfo { | |
129 | const char *name; | |
130 | void (*initfn)(Object *obj); | |
131 | } OpenRISCCPUInfo; | |
132 | ||
133 | static const OpenRISCCPUInfo openrisc_cpus[] = { | |
134 | { .name = "or1200", .initfn = or1200_initfn }, | |
135 | { .name = "any", .initfn = openrisc_any_initfn }, | |
136 | }; | |
137 | ||
138 | static void openrisc_cpu_class_init(ObjectClass *oc, void *data) | |
139 | { | |
140 | OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); | |
141 | CPUClass *cc = CPU_CLASS(occ); | |
c296262b AF |
142 | DeviceClass *dc = DEVICE_CLASS(oc); |
143 | ||
144 | occ->parent_realize = dc->realize; | |
145 | dc->realize = openrisc_cpu_realizefn; | |
e67db06e JL |
146 | |
147 | occ->parent_reset = cc->reset; | |
148 | cc->reset = openrisc_cpu_reset; | |
bd039ce0 AF |
149 | |
150 | cc->class_by_name = openrisc_cpu_class_by_name; | |
97a8ea5a | 151 | cc->do_interrupt = openrisc_cpu_do_interrupt; |
e67db06e JL |
152 | } |
153 | ||
154 | static void cpu_register(const OpenRISCCPUInfo *info) | |
155 | { | |
156 | TypeInfo type_info = { | |
e67db06e JL |
157 | .parent = TYPE_OPENRISC_CPU, |
158 | .instance_size = sizeof(OpenRISCCPU), | |
159 | .instance_init = info->initfn, | |
160 | .class_size = sizeof(OpenRISCCPUClass), | |
161 | }; | |
162 | ||
478032a9 | 163 | type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name); |
a1ebd6ce | 164 | type_register(&type_info); |
478032a9 | 165 | g_free((void *)type_info.name); |
e67db06e JL |
166 | } |
167 | ||
168 | static const TypeInfo openrisc_cpu_type_info = { | |
169 | .name = TYPE_OPENRISC_CPU, | |
170 | .parent = TYPE_CPU, | |
171 | .instance_size = sizeof(OpenRISCCPU), | |
172 | .instance_init = openrisc_cpu_initfn, | |
bc755a00 | 173 | .abstract = true, |
e67db06e JL |
174 | .class_size = sizeof(OpenRISCCPUClass), |
175 | .class_init = openrisc_cpu_class_init, | |
176 | }; | |
177 | ||
178 | static void openrisc_cpu_register_types(void) | |
179 | { | |
180 | int i; | |
181 | ||
182 | type_register_static(&openrisc_cpu_type_info); | |
183 | for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) { | |
184 | cpu_register(&openrisc_cpus[i]); | |
185 | } | |
186 | } | |
187 | ||
188 | OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) | |
189 | { | |
190 | OpenRISCCPU *cpu; | |
bd039ce0 | 191 | ObjectClass *oc; |
e67db06e | 192 | |
bd039ce0 AF |
193 | oc = openrisc_cpu_class_by_name(cpu_model); |
194 | if (oc == NULL) { | |
e67db06e JL |
195 | return NULL; |
196 | } | |
bd039ce0 | 197 | cpu = OPENRISC_CPU(object_new(object_class_get_name(oc))); |
e67db06e JL |
198 | cpu->env.cpu_model_str = cpu_model; |
199 | ||
c296262b | 200 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
e67db06e JL |
201 | |
202 | return cpu; | |
203 | } | |
204 | ||
e67db06e JL |
205 | /* Sort alphabetically by type name, except for "any". */ |
206 | static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) | |
207 | { | |
208 | ObjectClass *class_a = (ObjectClass *)a; | |
209 | ObjectClass *class_b = (ObjectClass *)b; | |
210 | const char *name_a, *name_b; | |
211 | ||
212 | name_a = object_class_get_name(class_a); | |
213 | name_b = object_class_get_name(class_b); | |
478032a9 | 214 | if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { |
e67db06e | 215 | return 1; |
478032a9 | 216 | } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { |
e67db06e JL |
217 | return -1; |
218 | } else { | |
219 | return strcmp(name_a, name_b); | |
220 | } | |
221 | } | |
222 | ||
223 | static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) | |
224 | { | |
225 | ObjectClass *oc = data; | |
8486af93 | 226 | CPUListState *s = user_data; |
478032a9 AF |
227 | const char *typename; |
228 | char *name; | |
e67db06e | 229 | |
478032a9 AF |
230 | typename = object_class_get_name(oc); |
231 | name = g_strndup(typename, | |
232 | strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); | |
e67db06e | 233 | (*s->cpu_fprintf)(s->file, " %s\n", |
478032a9 AF |
234 | name); |
235 | g_free(name); | |
e67db06e JL |
236 | } |
237 | ||
238 | void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) | |
239 | { | |
8486af93 | 240 | CPUListState s = { |
e67db06e JL |
241 | .file = f, |
242 | .cpu_fprintf = cpu_fprintf, | |
243 | }; | |
244 | GSList *list; | |
245 | ||
246 | list = object_class_get_list(TYPE_OPENRISC_CPU, false); | |
247 | list = g_slist_sort(list, openrisc_cpu_list_compare); | |
248 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
249 | g_slist_foreach(list, openrisc_cpu_list_entry, &s); | |
250 | g_slist_free(list); | |
251 | } | |
252 | ||
253 | type_init(openrisc_cpu_register_types) |