[mirror_qemu.git] / target-ppc / cpu.h

/*
 *  PPC emulation cpu definitions for qemu.
 * 
 *  Copyright (c) 2003 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#if !defined (__CPU_PPC_H__)
#define __CPU_PPC_H__

#define TARGET_LONG_BITS 32

#include "cpu-defs.h"

#include "config.h"
#include <setjmp.h>

#include "softfloat.h"

#define TARGET_HAS_ICE 1

/* Instruction types */
enum {
    PPC_NONE     = 0x0000,
    PPC_INTEGER  = 0x0001, /* CPU has integer operations instructions        */
    PPC_FLOAT    = 0x0002, /* CPU has floating point operations instructions */
    PPC_FLOW     = 0x0004, /* CPU has flow control instructions              */
    PPC_MEM      = 0x0008, /* CPU has virtual memory instructions            */
    PPC_RES      = 0x0010, /* CPU has ld/st with reservation instructions    */
    PPC_CACHE    = 0x0020, /* CPU has cache control instructions             */
    PPC_MISC     = 0x0040, /* CPU has spr/msr access instructions            */
    PPC_EXTERN   = 0x0080, /* CPU has external control instructions          */
    PPC_SEGMENT  = 0x0100, /* CPU has memory segment instructions            */
    PPC_CACHE_OPT= 0x0200,
    PPC_FLOAT_OPT= 0x0400,
    PPC_MEM_OPT  = 0x0800,
};

#define PPC_COMMON  (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |           \
                     PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
/* PPC 604 */
#define PPC_604 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
                 PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT    \
                 PPC_MEM_OPT)
/* PPC 740/745/750/755 (aka G3) has external access instructions */
#define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
                 PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)

typedef struct ppc_tb_t ppc_tb_t;

/* Supervisor mode registers */
/* Machine state register */
#define MSR_POW 18
#define MSR_ILE 16
#define MSR_EE  15
#define MSR_PR  14
#define MSR_FP  13
#define MSR_ME  12
#define MSR_FE0 11
#define MSR_SE  10
#define MSR_BE  9
#define MSR_FE1 8
#define MSR_IP 6
#define MSR_IR 5
#define MSR_DR 4
#define MSR_RI 1
#define MSR_LE 0
#define msr_pow env->msr[MSR_POW]
#define msr_ile env->msr[MSR_ILE]
#define msr_ee  env->msr[MSR_EE]
#define msr_pr  env->msr[MSR_PR]
#define msr_fp  env->msr[MSR_FP]
#define msr_me  env->msr[MSR_ME]
#define msr_fe0 env->msr[MSR_FE0]
#define msr_se  env->msr[MSR_SE]
#define msr_be  env->msr[MSR_BE]
#define msr_fe1 env->msr[MSR_FE1]
#define msr_ip  env->msr[MSR_IP]
#define msr_ir  env->msr[MSR_IR]
#define msr_dr  env->msr[MSR_DR]
#define msr_ri  env->msr[MSR_RI]
#define msr_le  env->msr[MSR_LE]

/* Segment registers */
typedef struct CPUPPCState {
    /* general purpose registers */
    uint32_t gpr[32];
    /* floating point registers */
    float64 fpr[32];
    /* segment registers */
    uint32_t sdr1;
    uint32_t sr[16];
    /* XER */
    uint8_t xer[4];
    /* Reservation address */
    uint32_t reserve;
    /* machine state register */
    uint8_t msr[32];
    /* condition register */
    uint8_t crf[8];
    /* floating point status and control register */
    uint8_t fpscr[8];
    uint32_t nip;
    /* special purpose registers */
    uint32_t lr;
    uint32_t ctr;
    /* BATs */
    uint32_t DBAT[2][8];
    uint32_t IBAT[2][8];
    /* all others */
    uint32_t spr[1024];
    /* qemu dedicated */
     /* temporary float registers */
    float64 ft0;
    float64 ft1;
    float64 ft2;
    float_status fp_status;

    int interrupt_request;
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    int access_type; /* when a memory exception occurs, the access
                        type is stored here */
    int user_mode_only; /* user mode only simulation */
    struct TranslationBlock *current_tb; /* currently executing TB */
    /* soft mmu support */
    /* in order to avoid passing too many arguments to the memory
       write helpers, we store some rarely used information in the CPU
       context) */
    unsigned long mem_write_pc; /* host pc at which the memory was
                                   written */
    unsigned long mem_write_vaddr; /* target virtual addr at which the
                                      memory was written */
    /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];

    /* ice debug support */
    uint32_t breakpoints[MAX_BREAKPOINTS];
    int nb_breakpoints;
    int singlestep_enabled; /* XXX: should use CPU single step mode instead */

    /* Time base and decrementer */
    ppc_tb_t *tb_env;

    /* Power management */
    int power_mode;

    /* user data */
    void *opaque;
} CPUPPCState;

CPUPPCState *cpu_ppc_init(void);
int cpu_ppc_exec(CPUPPCState *s);
void cpu_ppc_close(CPUPPCState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
struct siginfo;
int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc);

void do_interrupt (CPUPPCState *env);
void cpu_loop_exit(void);

void dump_stack (CPUPPCState *env);

uint32_t _load_xer (CPUPPCState *env);
void _store_xer (CPUPPCState *env, uint32_t value);
uint32_t _load_msr (CPUPPCState *env);
void _store_msr (CPUPPCState *env, uint32_t value);

int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);

/* Time-base and decrementer management */
#ifndef NO_CPU_IO_DEFS
uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
#endif

#define TARGET_PAGE_BITS 12
#include "cpu-all.h"

#define ugpr(n) (env->gpr[n])
#define fprd(n) (env->fpr[n])
#define fprs(n) ((float)env->fpr[n])
#define fpru(n) ((uint32_t)env->fpr[n])
#define fpri(n) ((int32_t)env->fpr[n])

#define SPR_ENCODE(sprn)                               \
(((sprn) >> 5) | (((sprn) & 0x1F) << 5))

/* User mode SPR */
#define spr(n) env->spr[n]
#define XER_SO 31
#define XER_OV 30
#define XER_CA 29
#define XER_BC 0
#define xer_so env->xer[3]
#define xer_ov env->xer[2]
#define xer_ca env->xer[1]
#define xer_bc env->xer[0]

#define MQ     SPR_ENCODE(0)
#define XER    SPR_ENCODE(1)
#define RTCUR  SPR_ENCODE(4)
#define RTCLR  SPR_ENCODE(5)
#define LR     SPR_ENCODE(8)
#define CTR    SPR_ENCODE(9)
/* VEA mode SPR */
#define V_TBL  SPR_ENCODE(268)
#define V_TBU  SPR_ENCODE(269)
/* supervisor mode SPR */
#define DSISR  SPR_ENCODE(18)
#define DAR    SPR_ENCODE(19)
#define RTCUW  SPR_ENCODE(20)
#define RTCLW  SPR_ENCODE(21)
#define DECR   SPR_ENCODE(22)
#define SDR1   SPR_ENCODE(25)
#define SRR0   SPR_ENCODE(26)
#define SRR1   SPR_ENCODE(27)
#define SPRG0  SPR_ENCODE(272)
#define SPRG1  SPR_ENCODE(273)
#define SPRG2  SPR_ENCODE(274)
#define SPRG3  SPR_ENCODE(275)
#define SPRG4  SPR_ENCODE(276)
#define SPRG5  SPR_ENCODE(277)
#define SPRG6  SPR_ENCODE(278)
#define SPRG7  SPR_ENCODE(279)
#define ASR    SPR_ENCODE(280)
#define EAR    SPR_ENCODE(282)
#define O_TBL  SPR_ENCODE(284)
#define O_TBU  SPR_ENCODE(285)
#define PVR    SPR_ENCODE(287)
#define IBAT0U SPR_ENCODE(528)
#define IBAT0L SPR_ENCODE(529)
#define IBAT1U SPR_ENCODE(530)
#define IBAT1L SPR_ENCODE(531)
#define IBAT2U SPR_ENCODE(532)
#define IBAT2L SPR_ENCODE(533)
#define IBAT3U SPR_ENCODE(534)
#define IBAT3L SPR_ENCODE(535)
#define DBAT0U SPR_ENCODE(536)
#define DBAT0L SPR_ENCODE(537)
#define DBAT1U SPR_ENCODE(538)
#define DBAT1L SPR_ENCODE(539)
#define DBAT2U SPR_ENCODE(540)
#define DBAT2L SPR_ENCODE(541)
#define DBAT3U SPR_ENCODE(542)
#define DBAT3L SPR_ENCODE(543)
#define IBAT4U SPR_ENCODE(560)
#define IBAT4L SPR_ENCODE(561)
#define IBAT5U SPR_ENCODE(562)
#define IBAT5L SPR_ENCODE(563)
#define IBAT6U SPR_ENCODE(564)
#define IBAT6L SPR_ENCODE(565)
#define IBAT7U SPR_ENCODE(566)
#define IBAT7L SPR_ENCODE(567)
#define DBAT4U SPR_ENCODE(568)
#define DBAT4L SPR_ENCODE(569)
#define DBAT5U SPR_ENCODE(570)
#define DBAT5L SPR_ENCODE(571)
#define DBAT6U SPR_ENCODE(572)
#define DBAT6L SPR_ENCODE(573)
#define DBAT7U SPR_ENCODE(574)
#define DBAT7L SPR_ENCODE(575)
#define UMMCR0 SPR_ENCODE(936)
#define UPMC1  SPR_ENCODE(937)
#define UPMC2  SPR_ENCODE(938)
#define USIA   SPR_ENCODE(939)
#define UMMCR1 SPR_ENCODE(940)
#define UPMC3  SPR_ENCODE(941)
#define UPMC4  SPR_ENCODE(942)
#define MMCR0  SPR_ENCODE(952)
#define PMC1   SPR_ENCODE(953)
#define PMC2   SPR_ENCODE(954)
#define SIA    SPR_ENCODE(955)
#define MMCR1  SPR_ENCODE(956)
#define PMC3   SPR_ENCODE(957)
#define PMC4   SPR_ENCODE(958)
#define SDA    SPR_ENCODE(959)
#define DMISS  SPR_ENCODE(976)
#define DCMP   SPR_ENCODE(977)
#define DHASH1 SPR_ENCODE(978)
#define DHASH2 SPR_ENCODE(979)
#define IMISS  SPR_ENCODE(980)
#define ICMP   SPR_ENCODE(981)
#define RPA    SPR_ENCODE(982)
#define TCR    SPR_ENCODE(984)
#define IBR    SPR_ENCODE(986)
#define ESASRR SPR_ENCODE(987)
#define SEBR   SPR_ENCODE(990)
#define SER    SPR_ENCODE(991)
#define HID0   SPR_ENCODE(1008)
#define HID1   SPR_ENCODE(1009)
#define IABR   SPR_ENCODE(1010)
#define HID2   SPR_ENCODE(1011)
#define DABR   SPR_ENCODE(1013)
#define L2PM   SPR_ENCODE(1016)
#define L2CR   SPR_ENCODE(1017)
#define ICTC   SPR_ENCODE(1019)
#define THRM1  SPR_ENCODE(1020)
#define THRM2  SPR_ENCODE(1021)
#define THRM3  SPR_ENCODE(1022)
#define SP     SPR_ENCODE(1021)
#define SPR_LP SPR_ENCODE(1022)
#define DABR_MASK 0xFFFFFFF8
#define FPECR  SPR_ENCODE(1022)
#define PIR    SPR_ENCODE(1023)

/* Memory access type :
 * may be needed for precise access rights control and precise exceptions.
 */
enum {
    /* 1 bit to define user level / supervisor access */
    ACCESS_USER  = 0x00,
    ACCESS_SUPER = 0x01,
    /* Type of instruction that generated the access */
    ACCESS_CODE  = 0x10, /* Code fetch access                */
    ACCESS_INT   = 0x20, /* Integer load/store access        */
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
    ACCESS_RES   = 0x40, /* load/store with reservation      */
    ACCESS_EXT   = 0x50, /* external access                  */
    ACCESS_CACHE = 0x60, /* Cache manipulation               */
};

/*****************************************************************************/
/* Exceptions */
enum {
    EXCP_NONE          = -1,
    /* PPC hardware exceptions : exception vector / 0x100 */
    EXCP_RESET         = 0x01, /* System reset                     */
    EXCP_MACHINE_CHECK = 0x02, /* Machine check exception          */
    EXCP_DSI           = 0x03, /* Impossible memory access         */
    EXCP_ISI           = 0x04, /* Impossible instruction fetch     */
    EXCP_EXTERNAL      = 0x05, /* External interruption            */
    EXCP_ALIGN         = 0x06, /* Alignment exception              */
    EXCP_PROGRAM       = 0x07, /* Program exception                */
    EXCP_NO_FP         = 0x08, /* No floating point                */
    EXCP_DECR          = 0x09, /* Decrementer exception            */
    EXCP_RESA          = 0x0A, /* Implementation specific          */
    EXCP_RESB          = 0x0B, /* Implementation specific          */
    EXCP_SYSCALL       = 0x0C, /* System call                      */
    EXCP_TRACE         = 0x0D, /* Trace exception (optional)       */
    EXCP_FP_ASSIST     = 0x0E, /* Floating-point assist (optional) */
    /* MPC740/745/750 & IBM 750 */
    EXCP_PERF          = 0x0F,  /* Performance monitor              */
    EXCP_IABR          = 0x13,  /* Instruction address breakpoint   */
    EXCP_SMI           = 0x14,  /* System management interrupt      */
    EXCP_THRM          = 0x15,  /* Thermal management interrupt     */
    /* MPC755 */
    EXCP_TLBMISS       = 0x10,  /* Instruction TLB miss             */
    EXCP_TLBMISS_DL    = 0x11,  /* Data TLB miss for load           */
    EXCP_TLBMISS_DS    = 0x12,  /* Data TLB miss for store          */
    EXCP_PPC_MAX       = 0x16,
    /* Qemu exception */
    EXCP_OFCALL        = 0x20,  /* Call open-firmware emulator      */
    EXCP_RTASCALL      = 0x21,  /* Call RTAS emulator               */
    /* Special cases where we want to stop translation */
    EXCP_MTMSR         = 0x104, /* mtmsr instruction:               */
                                /* may change privilege level       */
    EXCP_BRANCH        = 0x108, /* branch instruction               */
    EXCP_RFI           = 0x10C, /* return from interrupt            */
    EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
};
/* Error codes */
enum {
    /* Exception subtypes for EXCP_DSI                              */
    EXCP_DSI_TRANSLATE = 0x01,  /* Data address can't be translated */
    EXCP_DSI_NOTSUP    = 0x02,  /* Access type not supported        */
    EXCP_DSI_PROT      = 0x03,  /* Memory protection violation      */
    EXCP_DSI_EXTERNAL  = 0x04,  /* External access disabled         */
    EXCP_DSI_DABR      = 0x05,  /* Data address breakpoint          */
    /* flags for EXCP_DSI */
    EXCP_DSI_DIRECT    = 0x10,
    EXCP_DSI_STORE     = 0x20,
    EXCP_DSI_ECXW      = 0x40,
    /* Exception subtypes for EXCP_ISI                              */
    EXCP_ISI_TRANSLATE = 0x01,  /* Code address can't be translated */
    EXCP_ISI_NOEXEC    = 0x02,  /* Try to fetch from a data segment */
    EXCP_ISI_GUARD     = 0x03,  /* Fetch from guarded memory        */
    EXCP_ISI_PROT      = 0x04,  /* Memory protection violation      */
    EXCP_ISI_DIRECT    = 0x05,  /* Trying to fetch from             *
				 * a direct store segment           */
    /* Exception subtypes for EXCP_ALIGN                            */
    EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception           */
    EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store */
    EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access    */
    EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary */
    EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary  */
    EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access           */
    /* Exception subtypes for EXCP_PROGRAM                          */
    /* FP exceptions */
    EXCP_FP            = 0x10,
    EXCP_FP_OX         = 0x01,  /* FP overflow                      */
    EXCP_FP_UX         = 0x02,  /* FP underflow                     */
    EXCP_FP_ZX         = 0x03,  /* FP divide by zero                */
    EXCP_FP_XX         = 0x04,  /* FP inexact                       */
    EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op               */
    EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite substraction */
    EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide       */
    EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide           */
    EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero       */
    EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare               */
    EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation             */
    EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root           */
    EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion    */
    /* Invalid instruction */
    EXCP_INVAL         = 0x20,
    EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction              */
    EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction         */
    EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access               */
    EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr */
    /* Privileged instruction */
    EXCP_PRIV          = 0x30,
    EXCP_PRIV_OPC      = 0x01,
    EXCP_PRIV_REG      = 0x02,
    /* Trap */
    EXCP_TRAP          = 0x40,
};

/*****************************************************************************/

#endif /* !defined (__CPU_PPC_H__) */
Commit	Line	Data
79aceca5 FB	1	/*
	2	* PPC emulation cpu definitions for qemu.
	3	*
	4	* Copyright (c) 2003 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#if !defined (__CPU_PPC_H__)
	21	#define __CPU_PPC_H__
	22
3cf1e035 FB	23	#define TARGET_LONG_BITS 32
3cf1e035 FB	24
79aceca5 FB	25	#include "cpu-defs.h"
79aceca5 FB	26
79aceca5 FB	27	#include "config.h"
	28	#include <setjmp.h>
	29
4ecc3190 FB	30	#include "softfloat.h"
4ecc3190 FB	31
1fddef4b FB	32	#define TARGET_HAS_ICE 1
1fddef4b FB	33
9a64fbe4 FB	34	/* Instruction types */
	35	enum {
	36	PPC_NONE = 0x0000,
	37	PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */
	38	PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */
	39	PPC_FLOW = 0x0004, /* CPU has flow control instructions */
	40	PPC_MEM = 0x0008, /* CPU has virtual memory instructions */
	41	PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */
	42	PPC_CACHE = 0x0020, /* CPU has cache control instructions */
	43	PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */
	44	PPC_EXTERN = 0x0080, /* CPU has external control instructions */
	45	PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */
	46	PPC_CACHE_OPT= 0x0200,
	47	PPC_FLOAT_OPT= 0x0400,
	48	PPC_MEM_OPT = 0x0800,
	49	};
79aceca5	50
9a64fbe4 FB	51	#define PPC_COMMON (PPC_INTEGER \| PPC_FLOAT \| PPC_FLOW \| PPC_MEM \| \
9a64fbe4 FB	52	PPC_RES \| PPC_CACHE \| PPC_MISC \| PPC_SEGMENT)
85c4adf6 FB	53	/* PPC 604 */
	54	#define PPC_604 (PPC_INTEGER \| PPC_FLOAT \| PPC_FLOW \| PPC_MEM \| \
	55	PPC_RES \| PPC_CACHE \| PPC_MISC \| PPC_EXTERN \| PPC_SEGMENT \
	56	PPC_MEM_OPT)
9a64fbe4 FB	57	/* PPC 740/745/750/755 (aka G3) has external access instructions */
	58	#define PPC_750 (PPC_INTEGER \| PPC_FLOAT \| PPC_FLOW \| PPC_MEM \| \
	59	PPC_RES \| PPC_CACHE \| PPC_MISC \| PPC_EXTERN \| PPC_SEGMENT)
79aceca5	60
9fddaa0c FB	61	typedef struct ppc_tb_t ppc_tb_t;
9fddaa0c FB	62
79aceca5 FB	63	/* Supervisor mode registers */
	64	/* Machine state register */
	65	#define MSR_POW 18
	66	#define MSR_ILE 16
	67	#define MSR_EE 15
	68	#define MSR_PR 14
	69	#define MSR_FP 13
	70	#define MSR_ME 12
	71	#define MSR_FE0 11
	72	#define MSR_SE 10
	73	#define MSR_BE 9
	74	#define MSR_FE1 8
	75	#define MSR_IP 6
	76	#define MSR_IR 5
	77	#define MSR_DR 4
	78	#define MSR_RI 1
	79	#define MSR_LE 0
	80	#define msr_pow env->msr[MSR_POW]
	81	#define msr_ile env->msr[MSR_ILE]
	82	#define msr_ee env->msr[MSR_EE]
	83	#define msr_pr env->msr[MSR_PR]
	84	#define msr_fp env->msr[MSR_FP]
	85	#define msr_me env->msr[MSR_ME]
	86	#define msr_fe0 env->msr[MSR_FE0]
	87	#define msr_se env->msr[MSR_SE]
	88	#define msr_be env->msr[MSR_BE]
	89	#define msr_fe1 env->msr[MSR_FE1]
	90	#define msr_ip env->msr[MSR_IP]
	91	#define msr_ir env->msr[MSR_IR]
	92	#define msr_dr env->msr[MSR_DR]
	93	#define msr_ri env->msr[MSR_RI]
	94	#define msr_le env->msr[MSR_LE]
	95
	96	/* Segment registers */
79aceca5 FB	97	typedef struct CPUPPCState {
	98	/* general purpose registers */
	99	uint32_t gpr[32];
	100	/* floating point registers */
4ecc3190	101	float64 fpr[32];
79aceca5	102	/* segment registers */
9a64fbe4 FB	103	uint32_t sdr1;
9a64fbe4 FB	104	uint32_t sr[16];
79aceca5	105	/* XER */
9a64fbe4	106	uint8_t xer[4];
79aceca5 FB	107	/* Reservation address */
	108	uint32_t reserve;
	109	/* machine state register */
	110	uint8_t msr[32];
	111	/* condition register */
	112	uint8_t crf[8];
	113	/* floating point status and control register */
9a64fbe4	114	uint8_t fpscr[8];
79aceca5	115	uint32_t nip;
9a64fbe4 FB	116	/* special purpose registers */
	117	uint32_t lr;
	118	uint32_t ctr;
9a64fbe4 FB	119	/* BATs */
	120	uint32_t DBAT[2][8];
	121	uint32_t IBAT[2][8];
	122	/* all others */
	123	uint32_t spr[1024];
79aceca5	124	/* qemu dedicated */
fb0eaffc	125	/* temporary float registers */
4ecc3190 FB	126	float64 ft0;
	127	float64 ft1;
	128	float64 ft2;
	129	float_status fp_status;
	130
79aceca5 FB	131	int interrupt_request;
	132	jmp_buf jmp_env;
	133	int exception_index;
	134	int error_code;
ac9eb073 FB	135	int access_type; /* when a memory exception occurs, the access
ac9eb073 FB	136	type is stored here */
79aceca5 FB	137	int user_mode_only; /* user mode only simulation */
79aceca5 FB	138	struct TranslationBlock current_tb; / currently executing TB */
9a64fbe4	139	/* soft mmu support */
d720b93d FB	140	/* in order to avoid passing too many arguments to the memory
	141	write helpers, we store some rarely used information in the CPU
	142	context) */
	143	unsigned long mem_write_pc; /* host pc at which the memory was
	144	written */
	145	unsigned long mem_write_vaddr; /* target virtual addr at which the
	146	memory was written */
a541f297	147	/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
9a64fbe4 FB	148	CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
9a64fbe4 FB	149	CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
a541f297 FB	150
	151	/* ice debug support */
	152	uint32_t breakpoints[MAX_BREAKPOINTS];
	153	int nb_breakpoints;
9fddaa0c FB	154	int singlestep_enabled; /* XXX: should use CPU single step mode instead */
	155
	156	/* Time base and decrementer */
	157	ppc_tb_t *tb_env;
	158
	159	/* Power management */
	160	int power_mode;
a541f297	161
79aceca5 FB	162	/* user data */
	163	void *opaque;
	164	} CPUPPCState;
	165
	166	CPUPPCState *cpu_ppc_init(void);
	167	int cpu_ppc_exec(CPUPPCState *s);
	168	void cpu_ppc_close(CPUPPCState *s);
	169	/* you can call this signal handler from your SIGBUS and SIGSEGV
	170	signal handlers to inform the virtual CPU of exceptions. non zero
	171	is returned if the signal was handled by the virtual CPU. */
	172	struct siginfo;
	173	int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
	174	void *puc);
	175
a541f297	176	void do_interrupt (CPUPPCState *env);
9a64fbe4	177	void cpu_loop_exit(void);
a541f297	178
9a64fbe4	179	void dump_stack (CPUPPCState *env);
a541f297 FB	180
	181	uint32_t _load_xer (CPUPPCState *env);
	182	void _store_xer (CPUPPCState *env, uint32_t value);
	183	uint32_t _load_msr (CPUPPCState *env);
	184	void _store_msr (CPUPPCState *env, uint32_t value);
	185
85c4adf6 FB	186	int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
85c4adf6 FB	187
9fddaa0c FB	188	/* Time-base and decrementer management */
	189	#ifndef NO_CPU_IO_DEFS
	190	uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
	191	uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
	192	void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
	193	void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
	194	uint32_t cpu_ppc_load_decr (CPUPPCState *env);
	195	void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
	196	#endif
79aceca5 FB	197
	198	#define TARGET_PAGE_BITS 12
	199	#include "cpu-all.h"
	200
	201	#define ugpr(n) (env->gpr[n])
9a64fbe4 FB	202	#define fprd(n) (env->fpr[n])
	203	#define fprs(n) ((float)env->fpr[n])
	204	#define fpru(n) ((uint32_t)env->fpr[n])
	205	#define fpri(n) ((int32_t)env->fpr[n])
79aceca5 FB	206
	207	#define SPR_ENCODE(sprn) \
	208	(((sprn) >> 5) \| (((sprn) & 0x1F) << 5))
	209
	210	/* User mode SPR */
	211	#define spr(n) env->spr[n]
79aceca5 FB	212	#define XER_SO 31
	213	#define XER_OV 30
	214	#define XER_CA 29
	215	#define XER_BC 0
9a64fbe4 FB	216	#define xer_so env->xer[3]
	217	#define xer_ov env->xer[2]
	218	#define xer_ca env->xer[1]
	219	#define xer_bc env->xer[0]
79aceca5	220
85c4adf6	221	#define MQ SPR_ENCODE(0)
9a64fbe4	222	#define XER SPR_ENCODE(1)
85c4adf6 FB	223	#define RTCUR SPR_ENCODE(4)
85c4adf6 FB	224	#define RTCLR SPR_ENCODE(5)
9a64fbe4 FB	225	#define LR SPR_ENCODE(8)
9a64fbe4 FB	226	#define CTR SPR_ENCODE(9)
79aceca5	227	/* VEA mode SPR */
9a64fbe4 FB	228	#define V_TBL SPR_ENCODE(268)
9a64fbe4 FB	229	#define V_TBU SPR_ENCODE(269)
79aceca5	230	/* supervisor mode SPR */
9a64fbe4 FB	231	#define DSISR SPR_ENCODE(18)
9a64fbe4 FB	232	#define DAR SPR_ENCODE(19)
85c4adf6 FB	233	#define RTCUW SPR_ENCODE(20)
85c4adf6 FB	234	#define RTCLW SPR_ENCODE(21)
9a64fbe4 FB	235	#define DECR SPR_ENCODE(22)
	236	#define SDR1 SPR_ENCODE(25)
	237	#define SRR0 SPR_ENCODE(26)
	238	#define SRR1 SPR_ENCODE(27)
	239	#define SPRG0 SPR_ENCODE(272)
	240	#define SPRG1 SPR_ENCODE(273)
	241	#define SPRG2 SPR_ENCODE(274)
	242	#define SPRG3 SPR_ENCODE(275)
	243	#define SPRG4 SPR_ENCODE(276)
	244	#define SPRG5 SPR_ENCODE(277)
	245	#define SPRG6 SPR_ENCODE(278)
	246	#define SPRG7 SPR_ENCODE(279)
	247	#define ASR SPR_ENCODE(280)
	248	#define EAR SPR_ENCODE(282)
	249	#define O_TBL SPR_ENCODE(284)
	250	#define O_TBU SPR_ENCODE(285)
	251	#define PVR SPR_ENCODE(287)
	252	#define IBAT0U SPR_ENCODE(528)
	253	#define IBAT0L SPR_ENCODE(529)
	254	#define IBAT1U SPR_ENCODE(530)
	255	#define IBAT1L SPR_ENCODE(531)
	256	#define IBAT2U SPR_ENCODE(532)
	257	#define IBAT2L SPR_ENCODE(533)
	258	#define IBAT3U SPR_ENCODE(534)
	259	#define IBAT3L SPR_ENCODE(535)
	260	#define DBAT0U SPR_ENCODE(536)
	261	#define DBAT0L SPR_ENCODE(537)
	262	#define DBAT1U SPR_ENCODE(538)
	263	#define DBAT1L SPR_ENCODE(539)
	264	#define DBAT2U SPR_ENCODE(540)
	265	#define DBAT2L SPR_ENCODE(541)
	266	#define DBAT3U SPR_ENCODE(542)
	267	#define DBAT3L SPR_ENCODE(543)
	268	#define IBAT4U SPR_ENCODE(560)
	269	#define IBAT4L SPR_ENCODE(561)
	270	#define IBAT5U SPR_ENCODE(562)
	271	#define IBAT5L SPR_ENCODE(563)
	272	#define IBAT6U SPR_ENCODE(564)
	273	#define IBAT6L SPR_ENCODE(565)
	274	#define IBAT7U SPR_ENCODE(566)
	275	#define IBAT7L SPR_ENCODE(567)
	276	#define DBAT4U SPR_ENCODE(568)
	277	#define DBAT4L SPR_ENCODE(569)
	278	#define DBAT5U SPR_ENCODE(570)
	279	#define DBAT5L SPR_ENCODE(571)
	280	#define DBAT6U SPR_ENCODE(572)
	281	#define DBAT6L SPR_ENCODE(573)
	282	#define DBAT7U SPR_ENCODE(574)
	283	#define DBAT7L SPR_ENCODE(575)
85c4adf6 FB	284	#define UMMCR0 SPR_ENCODE(936)
	285	#define UPMC1 SPR_ENCODE(937)
	286	#define UPMC2 SPR_ENCODE(938)
	287	#define USIA SPR_ENCODE(939)
	288	#define UMMCR1 SPR_ENCODE(940)
	289	#define UPMC3 SPR_ENCODE(941)
	290	#define UPMC4 SPR_ENCODE(942)
	291	#define MMCR0 SPR_ENCODE(952)
	292	#define PMC1 SPR_ENCODE(953)
	293	#define PMC2 SPR_ENCODE(954)
	294	#define SIA SPR_ENCODE(955)
	295	#define MMCR1 SPR_ENCODE(956)
	296	#define PMC3 SPR_ENCODE(957)
	297	#define PMC4 SPR_ENCODE(958)
	298	#define SDA SPR_ENCODE(959)
	299	#define DMISS SPR_ENCODE(976)
	300	#define DCMP SPR_ENCODE(977)
	301	#define DHASH1 SPR_ENCODE(978)
	302	#define DHASH2 SPR_ENCODE(979)
	303	#define IMISS SPR_ENCODE(980)
	304	#define ICMP SPR_ENCODE(981)
	305	#define RPA SPR_ENCODE(982)
	306	#define TCR SPR_ENCODE(984)
	307	#define IBR SPR_ENCODE(986)
	308	#define ESASRR SPR_ENCODE(987)
	309	#define SEBR SPR_ENCODE(990)
	310	#define SER SPR_ENCODE(991)
	311	#define HID0 SPR_ENCODE(1008)
	312	#define HID1 SPR_ENCODE(1009)
	313	#define IABR SPR_ENCODE(1010)
	314	#define HID2 SPR_ENCODE(1011)
9a64fbe4	315	#define DABR SPR_ENCODE(1013)
85c4adf6 FB	316	#define L2PM SPR_ENCODE(1016)
	317	#define L2CR SPR_ENCODE(1017)
	318	#define ICTC SPR_ENCODE(1019)
	319	#define THRM1 SPR_ENCODE(1020)
	320	#define THRM2 SPR_ENCODE(1021)
	321	#define THRM3 SPR_ENCODE(1022)
	322	#define SP SPR_ENCODE(1021)
ce93da6f	323	#define SPR_LP SPR_ENCODE(1022)
79aceca5	324	#define DABR_MASK 0xFFFFFFF8
9a64fbe4 FB	325	#define FPECR SPR_ENCODE(1022)
9a64fbe4 FB	326	#define PIR SPR_ENCODE(1023)
79aceca5	327
9a64fbe4 FB	328	/* Memory access type :
	329	* may be needed for precise access rights control and precise exceptions.
	330	*/
79aceca5	331	enum {
9a64fbe4 FB	332	/* 1 bit to define user level / supervisor access */
	333	ACCESS_USER = 0x00,
	334	ACCESS_SUPER = 0x01,
	335	/* Type of instruction that generated the access */
	336	ACCESS_CODE = 0x10, /* Code fetch access */
	337	ACCESS_INT = 0x20, /* Integer load/store access */
	338	ACCESS_FLOAT = 0x30, /* floating point load/store access */
	339	ACCESS_RES = 0x40, /* load/store with reservation */
	340	ACCESS_EXT = 0x50, /* external access */
	341	ACCESS_CACHE = 0x60, /* Cache manipulation */
	342	};
	343
	344	/*****************************************************************************/
	345	/* Exceptions */
	346	enum {
	347	EXCP_NONE = -1,
79aceca5 FB	348	/* PPC hardware exceptions : exception vector / 0x100 */
	349	EXCP_RESET = 0x01, /* System reset */
	350	EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */
	351	EXCP_DSI = 0x03, /* Impossible memory access */
	352	EXCP_ISI = 0x04, /* Impossible instruction fetch */
	353	EXCP_EXTERNAL = 0x05, /* External interruption */
	354	EXCP_ALIGN = 0x06, /* Alignment exception */
	355	EXCP_PROGRAM = 0x07, /* Program exception */
	356	EXCP_NO_FP = 0x08, /* No floating point */
	357	EXCP_DECR = 0x09, /* Decrementer exception */
	358	EXCP_RESA = 0x0A, /* Implementation specific */
	359	EXCP_RESB = 0x0B, /* Implementation specific */
	360	EXCP_SYSCALL = 0x0C, /* System call */
	361	EXCP_TRACE = 0x0D, /* Trace exception (optional) */
	362	EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */
9a64fbe4 FB	363	/* MPC740/745/750 & IBM 750 */
	364	EXCP_PERF = 0x0F, /* Performance monitor */
	365	EXCP_IABR = 0x13, /* Instruction address breakpoint */
	366	EXCP_SMI = 0x14, /* System management interrupt */
	367	EXCP_THRM = 0x15, /* Thermal management interrupt */
	368	/* MPC755 */
	369	EXCP_TLBMISS = 0x10, /* Instruction TLB miss */
	370	EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */
	371	EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */
	372	EXCP_PPC_MAX = 0x16,
	373	/* Qemu exception */
	374	EXCP_OFCALL = 0x20, /* Call open-firmware emulator */
	375	EXCP_RTASCALL = 0x21, /* Call RTAS emulator */
	376	/* Special cases where we want to stop translation */
	377	EXCP_MTMSR = 0x104, /* mtmsr instruction: */
	378	/* may change privilege level */
	379	EXCP_BRANCH = 0x108, /* branch instruction */
	380	EXCP_RFI = 0x10C, /* return from interrupt */
	381	EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
	382	};
	383	/* Error codes */
	384	enum {
	385	/* Exception subtypes for EXCP_DSI */
	386	EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */
	387	EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */
	388	EXCP_DSI_PROT = 0x03, /* Memory protection violation */
	389	EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */
	390	EXCP_DSI_DABR = 0x05, /* Data address breakpoint */
	391	/* flags for EXCP_DSI */
	392	EXCP_DSI_DIRECT = 0x10,
	393	EXCP_DSI_STORE = 0x20,
a541f297	394	EXCP_DSI_ECXW = 0x40,
9a64fbe4 FB	395	/* Exception subtypes for EXCP_ISI */
	396	EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */
	397	EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */
	398	EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */
	399	EXCP_ISI_PROT = 0x04, /* Memory protection violation */
a541f297 FB	400	EXCP_ISI_DIRECT = 0x05, /* Trying to fetch from *
a541f297 FB	401	* a direct store segment */
9a64fbe4 FB	402	/* Exception subtypes for EXCP_ALIGN */
	403	EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
	404	EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
	405	EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
	406	EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
	407	EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
	408	EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
	409	/* Exception subtypes for EXCP_PROGRAM */
79aceca5	410	/* FP exceptions */
9a64fbe4 FB	411	EXCP_FP = 0x10,
	412	EXCP_FP_OX = 0x01, /* FP overflow */
	413	EXCP_FP_UX = 0x02, /* FP underflow */
	414	EXCP_FP_ZX = 0x03, /* FP divide by zero */
	415	EXCP_FP_XX = 0x04, /* FP inexact */
	416	EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
	417	EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
	418	EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
	419	EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
	420	EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
	421	EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
	422	EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
	423	EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
	424	EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
79aceca5	425	/* Invalid instruction */
9a64fbe4 FB	426	EXCP_INVAL = 0x20,
	427	EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
	428	EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
	429	EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
	430	EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
79aceca5	431	/* Privileged instruction */
9a64fbe4 FB	432	EXCP_PRIV = 0x30,
	433	EXCP_PRIV_OPC = 0x01,
	434	EXCP_PRIV_REG = 0x02,
79aceca5	435	/* Trap */
9a64fbe4	436	EXCP_TRAP = 0x40,
79aceca5 FB	437	};
79aceca5 FB	438
9a64fbe4 FB	439	/*****************************************************************************/
9a64fbe4 FB	440
79aceca5	441	#endif /* !defined (__CPU_PPC_H__) */