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bd23cd45 BS |
1 | /* |
2 | * PowerPC floating point and SPE emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include "cpu.h" | |
2ef6175a | 20 | #include "exec/helper-proto.h" |
bd23cd45 | 21 | |
b748863a TM |
22 | #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL) |
23 | #define float32_snan_to_qnan(x) ((x) | 0x00400000) | |
24 | ||
bd23cd45 BS |
25 | /*****************************************************************************/ |
26 | /* Floating point operations helpers */ | |
8e703949 | 27 | uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg) |
bd23cd45 BS |
28 | { |
29 | CPU_FloatU f; | |
30 | CPU_DoubleU d; | |
31 | ||
32 | f.l = arg; | |
33 | d.d = float32_to_float64(f.f, &env->fp_status); | |
34 | return d.ll; | |
35 | } | |
36 | ||
8e703949 | 37 | uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg) |
bd23cd45 BS |
38 | { |
39 | CPU_FloatU f; | |
40 | CPU_DoubleU d; | |
41 | ||
42 | d.ll = arg; | |
43 | f.f = float64_to_float32(d.d, &env->fp_status); | |
44 | return f.l; | |
45 | } | |
46 | ||
47 | static inline int isden(float64 d) | |
48 | { | |
49 | CPU_DoubleU u; | |
50 | ||
51 | u.d = d; | |
52 | ||
53 | return ((u.ll >> 52) & 0x7FF) == 0; | |
54 | } | |
55 | ||
da29cb7b TM |
56 | static inline int ppc_float32_get_unbiased_exp(float32 f) |
57 | { | |
58 | return ((f >> 23) & 0xFF) - 127; | |
59 | } | |
60 | ||
61 | static inline int ppc_float64_get_unbiased_exp(float64 f) | |
62 | { | |
63 | return ((f >> 52) & 0x7FF) - 1023; | |
64 | } | |
65 | ||
58dd0a47 | 66 | void helper_compute_fprf(CPUPPCState *env, uint64_t arg) |
bd23cd45 BS |
67 | { |
68 | CPU_DoubleU farg; | |
69 | int isneg; | |
58dd0a47 | 70 | int fprf; |
bd23cd45 BS |
71 | |
72 | farg.ll = arg; | |
73 | isneg = float64_is_neg(farg.d); | |
74 | if (unlikely(float64_is_any_nan(farg.d))) { | |
75 | if (float64_is_signaling_nan(farg.d)) { | |
76 | /* Signaling NaN: flags are undefined */ | |
58dd0a47 | 77 | fprf = 0x00; |
bd23cd45 BS |
78 | } else { |
79 | /* Quiet NaN */ | |
58dd0a47 | 80 | fprf = 0x11; |
bd23cd45 BS |
81 | } |
82 | } else if (unlikely(float64_is_infinity(farg.d))) { | |
83 | /* +/- infinity */ | |
84 | if (isneg) { | |
58dd0a47 | 85 | fprf = 0x09; |
bd23cd45 | 86 | } else { |
58dd0a47 | 87 | fprf = 0x05; |
bd23cd45 BS |
88 | } |
89 | } else { | |
90 | if (float64_is_zero(farg.d)) { | |
91 | /* +/- zero */ | |
92 | if (isneg) { | |
58dd0a47 | 93 | fprf = 0x12; |
bd23cd45 | 94 | } else { |
58dd0a47 | 95 | fprf = 0x02; |
bd23cd45 BS |
96 | } |
97 | } else { | |
98 | if (isden(farg.d)) { | |
99 | /* Denormalized numbers */ | |
58dd0a47 | 100 | fprf = 0x10; |
bd23cd45 BS |
101 | } else { |
102 | /* Normalized numbers */ | |
58dd0a47 | 103 | fprf = 0x00; |
bd23cd45 BS |
104 | } |
105 | if (isneg) { | |
58dd0a47 | 106 | fprf |= 0x08; |
bd23cd45 | 107 | } else { |
58dd0a47 | 108 | fprf |= 0x04; |
bd23cd45 BS |
109 | } |
110 | } | |
111 | } | |
58dd0a47 TM |
112 | /* We update FPSCR_FPRF */ |
113 | env->fpscr &= ~(0x1F << FPSCR_FPRF); | |
114 | env->fpscr |= fprf << FPSCR_FPRF; | |
bd23cd45 BS |
115 | } |
116 | ||
117 | /* Floating-point invalid operations exception */ | |
59800ec8 TM |
118 | static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op, |
119 | int set_fpcc) | |
bd23cd45 | 120 | { |
27103424 | 121 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
bd23cd45 BS |
122 | uint64_t ret = 0; |
123 | int ve; | |
124 | ||
125 | ve = fpscr_ve; | |
126 | switch (op) { | |
127 | case POWERPC_EXCP_FP_VXSNAN: | |
128 | env->fpscr |= 1 << FPSCR_VXSNAN; | |
129 | break; | |
130 | case POWERPC_EXCP_FP_VXSOFT: | |
131 | env->fpscr |= 1 << FPSCR_VXSOFT; | |
132 | break; | |
133 | case POWERPC_EXCP_FP_VXISI: | |
134 | /* Magnitude subtraction of infinities */ | |
135 | env->fpscr |= 1 << FPSCR_VXISI; | |
136 | goto update_arith; | |
137 | case POWERPC_EXCP_FP_VXIDI: | |
138 | /* Division of infinity by infinity */ | |
139 | env->fpscr |= 1 << FPSCR_VXIDI; | |
140 | goto update_arith; | |
141 | case POWERPC_EXCP_FP_VXZDZ: | |
142 | /* Division of zero by zero */ | |
143 | env->fpscr |= 1 << FPSCR_VXZDZ; | |
144 | goto update_arith; | |
145 | case POWERPC_EXCP_FP_VXIMZ: | |
146 | /* Multiplication of zero by infinity */ | |
147 | env->fpscr |= 1 << FPSCR_VXIMZ; | |
148 | goto update_arith; | |
149 | case POWERPC_EXCP_FP_VXVC: | |
150 | /* Ordered comparison of NaN */ | |
151 | env->fpscr |= 1 << FPSCR_VXVC; | |
59800ec8 TM |
152 | if (set_fpcc) { |
153 | env->fpscr &= ~(0xF << FPSCR_FPCC); | |
154 | env->fpscr |= 0x11 << FPSCR_FPCC; | |
155 | } | |
bd23cd45 BS |
156 | /* We must update the target FPR before raising the exception */ |
157 | if (ve != 0) { | |
27103424 | 158 | cs->exception_index = POWERPC_EXCP_PROGRAM; |
bd23cd45 BS |
159 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; |
160 | /* Update the floating-point enabled exception summary */ | |
161 | env->fpscr |= 1 << FPSCR_FEX; | |
162 | /* Exception is differed */ | |
163 | ve = 0; | |
164 | } | |
165 | break; | |
166 | case POWERPC_EXCP_FP_VXSQRT: | |
167 | /* Square root of a negative number */ | |
168 | env->fpscr |= 1 << FPSCR_VXSQRT; | |
169 | update_arith: | |
170 | env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); | |
171 | if (ve == 0) { | |
172 | /* Set the result to quiet NaN */ | |
173 | ret = 0x7FF8000000000000ULL; | |
59800ec8 TM |
174 | if (set_fpcc) { |
175 | env->fpscr &= ~(0xF << FPSCR_FPCC); | |
176 | env->fpscr |= 0x11 << FPSCR_FPCC; | |
177 | } | |
bd23cd45 BS |
178 | } |
179 | break; | |
180 | case POWERPC_EXCP_FP_VXCVI: | |
181 | /* Invalid conversion */ | |
182 | env->fpscr |= 1 << FPSCR_VXCVI; | |
183 | env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); | |
184 | if (ve == 0) { | |
185 | /* Set the result to quiet NaN */ | |
186 | ret = 0x7FF8000000000000ULL; | |
59800ec8 TM |
187 | if (set_fpcc) { |
188 | env->fpscr &= ~(0xF << FPSCR_FPCC); | |
189 | env->fpscr |= 0x11 << FPSCR_FPCC; | |
190 | } | |
bd23cd45 BS |
191 | } |
192 | break; | |
193 | } | |
194 | /* Update the floating-point invalid operation summary */ | |
195 | env->fpscr |= 1 << FPSCR_VX; | |
196 | /* Update the floating-point exception summary */ | |
197 | env->fpscr |= 1 << FPSCR_FX; | |
198 | if (ve != 0) { | |
199 | /* Update the floating-point enabled exception summary */ | |
200 | env->fpscr |= 1 << FPSCR_FEX; | |
201 | if (msr_fe0 != 0 || msr_fe1 != 0) { | |
202 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, | |
203 | POWERPC_EXCP_FP | op); | |
204 | } | |
205 | } | |
206 | return ret; | |
207 | } | |
208 | ||
8e703949 | 209 | static inline void float_zero_divide_excp(CPUPPCState *env) |
bd23cd45 BS |
210 | { |
211 | env->fpscr |= 1 << FPSCR_ZX; | |
212 | env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); | |
213 | /* Update the floating-point exception summary */ | |
214 | env->fpscr |= 1 << FPSCR_FX; | |
215 | if (fpscr_ze != 0) { | |
216 | /* Update the floating-point enabled exception summary */ | |
217 | env->fpscr |= 1 << FPSCR_FEX; | |
218 | if (msr_fe0 != 0 || msr_fe1 != 0) { | |
219 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, | |
220 | POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX); | |
221 | } | |
222 | } | |
223 | } | |
224 | ||
8e703949 | 225 | static inline void float_overflow_excp(CPUPPCState *env) |
bd23cd45 | 226 | { |
27103424 AF |
227 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
228 | ||
bd23cd45 BS |
229 | env->fpscr |= 1 << FPSCR_OX; |
230 | /* Update the floating-point exception summary */ | |
231 | env->fpscr |= 1 << FPSCR_FX; | |
232 | if (fpscr_oe != 0) { | |
233 | /* XXX: should adjust the result */ | |
234 | /* Update the floating-point enabled exception summary */ | |
235 | env->fpscr |= 1 << FPSCR_FEX; | |
236 | /* We must update the target FPR before raising the exception */ | |
27103424 | 237 | cs->exception_index = POWERPC_EXCP_PROGRAM; |
bd23cd45 BS |
238 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; |
239 | } else { | |
240 | env->fpscr |= 1 << FPSCR_XX; | |
241 | env->fpscr |= 1 << FPSCR_FI; | |
242 | } | |
243 | } | |
244 | ||
8e703949 | 245 | static inline void float_underflow_excp(CPUPPCState *env) |
bd23cd45 | 246 | { |
27103424 AF |
247 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
248 | ||
bd23cd45 BS |
249 | env->fpscr |= 1 << FPSCR_UX; |
250 | /* Update the floating-point exception summary */ | |
251 | env->fpscr |= 1 << FPSCR_FX; | |
252 | if (fpscr_ue != 0) { | |
253 | /* XXX: should adjust the result */ | |
254 | /* Update the floating-point enabled exception summary */ | |
255 | env->fpscr |= 1 << FPSCR_FEX; | |
256 | /* We must update the target FPR before raising the exception */ | |
27103424 | 257 | cs->exception_index = POWERPC_EXCP_PROGRAM; |
bd23cd45 BS |
258 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX; |
259 | } | |
260 | } | |
261 | ||
8e703949 | 262 | static inline void float_inexact_excp(CPUPPCState *env) |
bd23cd45 | 263 | { |
27103424 AF |
264 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
265 | ||
bd23cd45 BS |
266 | env->fpscr |= 1 << FPSCR_XX; |
267 | /* Update the floating-point exception summary */ | |
268 | env->fpscr |= 1 << FPSCR_FX; | |
269 | if (fpscr_xe != 0) { | |
270 | /* Update the floating-point enabled exception summary */ | |
271 | env->fpscr |= 1 << FPSCR_FEX; | |
272 | /* We must update the target FPR before raising the exception */ | |
27103424 | 273 | cs->exception_index = POWERPC_EXCP_PROGRAM; |
bd23cd45 BS |
274 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; |
275 | } | |
276 | } | |
277 | ||
8e703949 | 278 | static inline void fpscr_set_rounding_mode(CPUPPCState *env) |
bd23cd45 BS |
279 | { |
280 | int rnd_type; | |
281 | ||
282 | /* Set rounding mode */ | |
283 | switch (fpscr_rn) { | |
284 | case 0: | |
285 | /* Best approximation (round to nearest) */ | |
286 | rnd_type = float_round_nearest_even; | |
287 | break; | |
288 | case 1: | |
289 | /* Smaller magnitude (round toward zero) */ | |
290 | rnd_type = float_round_to_zero; | |
291 | break; | |
292 | case 2: | |
293 | /* Round toward +infinite */ | |
294 | rnd_type = float_round_up; | |
295 | break; | |
296 | default: | |
297 | case 3: | |
298 | /* Round toward -infinite */ | |
299 | rnd_type = float_round_down; | |
300 | break; | |
301 | } | |
302 | set_float_rounding_mode(rnd_type, &env->fp_status); | |
303 | } | |
304 | ||
8e703949 | 305 | void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) |
bd23cd45 BS |
306 | { |
307 | int prev; | |
308 | ||
309 | prev = (env->fpscr >> bit) & 1; | |
310 | env->fpscr &= ~(1 << bit); | |
311 | if (prev == 1) { | |
312 | switch (bit) { | |
313 | case FPSCR_RN1: | |
314 | case FPSCR_RN: | |
8e703949 | 315 | fpscr_set_rounding_mode(env); |
bd23cd45 BS |
316 | break; |
317 | default: | |
318 | break; | |
319 | } | |
320 | } | |
321 | } | |
322 | ||
8e703949 | 323 | void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) |
bd23cd45 | 324 | { |
27103424 | 325 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
bd23cd45 BS |
326 | int prev; |
327 | ||
328 | prev = (env->fpscr >> bit) & 1; | |
329 | env->fpscr |= 1 << bit; | |
330 | if (prev == 0) { | |
331 | switch (bit) { | |
332 | case FPSCR_VX: | |
333 | env->fpscr |= 1 << FPSCR_FX; | |
334 | if (fpscr_ve) { | |
335 | goto raise_ve; | |
336 | } | |
90638255 | 337 | break; |
bd23cd45 BS |
338 | case FPSCR_OX: |
339 | env->fpscr |= 1 << FPSCR_FX; | |
340 | if (fpscr_oe) { | |
341 | goto raise_oe; | |
342 | } | |
343 | break; | |
344 | case FPSCR_UX: | |
345 | env->fpscr |= 1 << FPSCR_FX; | |
346 | if (fpscr_ue) { | |
347 | goto raise_ue; | |
348 | } | |
349 | break; | |
350 | case FPSCR_ZX: | |
351 | env->fpscr |= 1 << FPSCR_FX; | |
352 | if (fpscr_ze) { | |
353 | goto raise_ze; | |
354 | } | |
355 | break; | |
356 | case FPSCR_XX: | |
357 | env->fpscr |= 1 << FPSCR_FX; | |
358 | if (fpscr_xe) { | |
359 | goto raise_xe; | |
360 | } | |
361 | break; | |
362 | case FPSCR_VXSNAN: | |
363 | case FPSCR_VXISI: | |
364 | case FPSCR_VXIDI: | |
365 | case FPSCR_VXZDZ: | |
366 | case FPSCR_VXIMZ: | |
367 | case FPSCR_VXVC: | |
368 | case FPSCR_VXSOFT: | |
369 | case FPSCR_VXSQRT: | |
370 | case FPSCR_VXCVI: | |
371 | env->fpscr |= 1 << FPSCR_VX; | |
372 | env->fpscr |= 1 << FPSCR_FX; | |
373 | if (fpscr_ve != 0) { | |
374 | goto raise_ve; | |
375 | } | |
376 | break; | |
377 | case FPSCR_VE: | |
378 | if (fpscr_vx != 0) { | |
379 | raise_ve: | |
380 | env->error_code = POWERPC_EXCP_FP; | |
381 | if (fpscr_vxsnan) { | |
382 | env->error_code |= POWERPC_EXCP_FP_VXSNAN; | |
383 | } | |
384 | if (fpscr_vxisi) { | |
385 | env->error_code |= POWERPC_EXCP_FP_VXISI; | |
386 | } | |
387 | if (fpscr_vxidi) { | |
388 | env->error_code |= POWERPC_EXCP_FP_VXIDI; | |
389 | } | |
390 | if (fpscr_vxzdz) { | |
391 | env->error_code |= POWERPC_EXCP_FP_VXZDZ; | |
392 | } | |
393 | if (fpscr_vximz) { | |
394 | env->error_code |= POWERPC_EXCP_FP_VXIMZ; | |
395 | } | |
396 | if (fpscr_vxvc) { | |
397 | env->error_code |= POWERPC_EXCP_FP_VXVC; | |
398 | } | |
399 | if (fpscr_vxsoft) { | |
400 | env->error_code |= POWERPC_EXCP_FP_VXSOFT; | |
401 | } | |
402 | if (fpscr_vxsqrt) { | |
403 | env->error_code |= POWERPC_EXCP_FP_VXSQRT; | |
404 | } | |
405 | if (fpscr_vxcvi) { | |
406 | env->error_code |= POWERPC_EXCP_FP_VXCVI; | |
407 | } | |
408 | goto raise_excp; | |
409 | } | |
410 | break; | |
411 | case FPSCR_OE: | |
412 | if (fpscr_ox != 0) { | |
413 | raise_oe: | |
414 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; | |
415 | goto raise_excp; | |
416 | } | |
417 | break; | |
418 | case FPSCR_UE: | |
419 | if (fpscr_ux != 0) { | |
420 | raise_ue: | |
421 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX; | |
422 | goto raise_excp; | |
423 | } | |
424 | break; | |
425 | case FPSCR_ZE: | |
426 | if (fpscr_zx != 0) { | |
427 | raise_ze: | |
428 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX; | |
429 | goto raise_excp; | |
430 | } | |
431 | break; | |
432 | case FPSCR_XE: | |
433 | if (fpscr_xx != 0) { | |
434 | raise_xe: | |
435 | env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; | |
436 | goto raise_excp; | |
437 | } | |
438 | break; | |
439 | case FPSCR_RN1: | |
440 | case FPSCR_RN: | |
8e703949 | 441 | fpscr_set_rounding_mode(env); |
bd23cd45 BS |
442 | break; |
443 | default: | |
444 | break; | |
445 | raise_excp: | |
446 | /* Update the floating-point enabled exception summary */ | |
447 | env->fpscr |= 1 << FPSCR_FEX; | |
448 | /* We have to update Rc1 before raising the exception */ | |
27103424 | 449 | cs->exception_index = POWERPC_EXCP_PROGRAM; |
bd23cd45 BS |
450 | break; |
451 | } | |
452 | } | |
453 | } | |
454 | ||
8e703949 | 455 | void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) |
bd23cd45 | 456 | { |
27103424 | 457 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
7d08d856 | 458 | target_ulong prev, new; |
bd23cd45 BS |
459 | int i; |
460 | ||
461 | prev = env->fpscr; | |
7d08d856 AJ |
462 | new = (target_ulong)arg; |
463 | new &= ~0x60000000LL; | |
464 | new |= prev & 0x60000000LL; | |
465 | for (i = 0; i < sizeof(target_ulong) * 2; i++) { | |
bd23cd45 | 466 | if (mask & (1 << i)) { |
7d08d856 AJ |
467 | env->fpscr &= ~(0xFLL << (4 * i)); |
468 | env->fpscr |= new & (0xFLL << (4 * i)); | |
bd23cd45 BS |
469 | } |
470 | } | |
471 | /* Update VX and FEX */ | |
472 | if (fpscr_ix != 0) { | |
473 | env->fpscr |= 1 << FPSCR_VX; | |
474 | } else { | |
475 | env->fpscr &= ~(1 << FPSCR_VX); | |
476 | } | |
477 | if ((fpscr_ex & fpscr_eex) != 0) { | |
478 | env->fpscr |= 1 << FPSCR_FEX; | |
27103424 | 479 | cs->exception_index = POWERPC_EXCP_PROGRAM; |
bd23cd45 BS |
480 | /* XXX: we should compute it properly */ |
481 | env->error_code = POWERPC_EXCP_FP; | |
482 | } else { | |
483 | env->fpscr &= ~(1 << FPSCR_FEX); | |
484 | } | |
8e703949 | 485 | fpscr_set_rounding_mode(env); |
bd23cd45 BS |
486 | } |
487 | ||
d6478bc7 FC |
488 | void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) |
489 | { | |
490 | helper_store_fpscr(env, arg, mask); | |
491 | } | |
492 | ||
8e703949 | 493 | void helper_float_check_status(CPUPPCState *env) |
bd23cd45 | 494 | { |
27103424 | 495 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
db72c9f2 TG |
496 | int status = get_float_exception_flags(&env->fp_status); |
497 | ||
498 | if (status & float_flag_divbyzero) { | |
499 | float_zero_divide_excp(env); | |
500 | } else if (status & float_flag_overflow) { | |
501 | float_overflow_excp(env); | |
502 | } else if (status & float_flag_underflow) { | |
503 | float_underflow_excp(env); | |
504 | } else if (status & float_flag_inexact) { | |
505 | float_inexact_excp(env); | |
506 | } | |
507 | ||
27103424 | 508 | if (cs->exception_index == POWERPC_EXCP_PROGRAM && |
bd23cd45 BS |
509 | (env->error_code & POWERPC_EXCP_FP)) { |
510 | /* Differred floating-point exception after target FPR update */ | |
511 | if (msr_fe0 != 0 || msr_fe1 != 0) { | |
27103424 | 512 | helper_raise_exception_err(env, cs->exception_index, |
bd23cd45 BS |
513 | env->error_code); |
514 | } | |
bd23cd45 BS |
515 | } |
516 | } | |
517 | ||
8e703949 | 518 | void helper_reset_fpstatus(CPUPPCState *env) |
bd23cd45 BS |
519 | { |
520 | set_float_exception_flags(0, &env->fp_status); | |
521 | } | |
522 | ||
523 | /* fadd - fadd. */ | |
8e703949 | 524 | uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2) |
bd23cd45 BS |
525 | { |
526 | CPU_DoubleU farg1, farg2; | |
527 | ||
528 | farg1.ll = arg1; | |
529 | farg2.ll = arg2; | |
530 | ||
531 | if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) && | |
532 | float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) { | |
533 | /* Magnitude subtraction of infinities */ | |
59800ec8 | 534 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); |
bd23cd45 BS |
535 | } else { |
536 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
537 | float64_is_signaling_nan(farg2.d))) { | |
538 | /* sNaN addition */ | |
59800ec8 | 539 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
540 | } |
541 | farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status); | |
542 | } | |
543 | ||
544 | return farg1.ll; | |
545 | } | |
546 | ||
547 | /* fsub - fsub. */ | |
8e703949 | 548 | uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2) |
bd23cd45 BS |
549 | { |
550 | CPU_DoubleU farg1, farg2; | |
551 | ||
552 | farg1.ll = arg1; | |
553 | farg2.ll = arg2; | |
554 | ||
555 | if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) && | |
556 | float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) { | |
557 | /* Magnitude subtraction of infinities */ | |
59800ec8 | 558 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); |
bd23cd45 BS |
559 | } else { |
560 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
561 | float64_is_signaling_nan(farg2.d))) { | |
562 | /* sNaN subtraction */ | |
59800ec8 | 563 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
564 | } |
565 | farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status); | |
566 | } | |
567 | ||
568 | return farg1.ll; | |
569 | } | |
570 | ||
571 | /* fmul - fmul. */ | |
8e703949 | 572 | uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2) |
bd23cd45 BS |
573 | { |
574 | CPU_DoubleU farg1, farg2; | |
575 | ||
576 | farg1.ll = arg1; | |
577 | farg2.ll = arg2; | |
578 | ||
579 | if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || | |
580 | (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { | |
581 | /* Multiplication of zero by infinity */ | |
59800ec8 | 582 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); |
bd23cd45 BS |
583 | } else { |
584 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
585 | float64_is_signaling_nan(farg2.d))) { | |
586 | /* sNaN multiplication */ | |
59800ec8 | 587 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
588 | } |
589 | farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status); | |
590 | } | |
591 | ||
592 | return farg1.ll; | |
593 | } | |
594 | ||
595 | /* fdiv - fdiv. */ | |
8e703949 | 596 | uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2) |
bd23cd45 BS |
597 | { |
598 | CPU_DoubleU farg1, farg2; | |
599 | ||
600 | farg1.ll = arg1; | |
601 | farg2.ll = arg2; | |
602 | ||
603 | if (unlikely(float64_is_infinity(farg1.d) && | |
604 | float64_is_infinity(farg2.d))) { | |
605 | /* Division of infinity by infinity */ | |
59800ec8 | 606 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1); |
bd23cd45 BS |
607 | } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) { |
608 | /* Division of zero by zero */ | |
59800ec8 | 609 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); |
bd23cd45 BS |
610 | } else { |
611 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
612 | float64_is_signaling_nan(farg2.d))) { | |
613 | /* sNaN division */ | |
59800ec8 | 614 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
615 | } |
616 | farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status); | |
617 | } | |
618 | ||
619 | return farg1.ll; | |
620 | } | |
621 | ||
bd23cd45 | 622 | |
fab7fe42 TM |
623 | #define FPU_FCTI(op, cvt, nanval) \ |
624 | uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ | |
625 | { \ | |
626 | CPU_DoubleU farg; \ | |
627 | \ | |
628 | farg.ll = arg; \ | |
629 | farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \ | |
630 | \ | |
631 | if (unlikely(env->fp_status.float_exception_flags)) { \ | |
632 | if (float64_is_any_nan(arg)) { \ | |
633 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \ | |
634 | if (float64_is_signaling_nan(arg)) { \ | |
635 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \ | |
636 | } \ | |
637 | farg.ll = nanval; \ | |
638 | } else if (env->fp_status.float_exception_flags & \ | |
639 | float_flag_invalid) { \ | |
640 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \ | |
641 | } \ | |
642 | helper_float_check_status(env); \ | |
643 | } \ | |
644 | return farg.ll; \ | |
645 | } | |
646 | ||
7dff9abe TM |
647 | FPU_FCTI(fctiw, int32, 0x80000000U) |
648 | FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U) | |
649 | FPU_FCTI(fctiwu, uint32, 0x00000000U) | |
650 | FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U) | |
7dff9abe TM |
651 | FPU_FCTI(fctid, int64, 0x8000000000000000ULL) |
652 | FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL) | |
653 | FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL) | |
654 | FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL) | |
bd23cd45 | 655 | |
28288b48 TM |
656 | #define FPU_FCFI(op, cvtr, is_single) \ |
657 | uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ | |
658 | { \ | |
659 | CPU_DoubleU farg; \ | |
660 | \ | |
661 | if (is_single) { \ | |
662 | float32 tmp = cvtr(arg, &env->fp_status); \ | |
663 | farg.d = float32_to_float64(tmp, &env->fp_status); \ | |
664 | } else { \ | |
665 | farg.d = cvtr(arg, &env->fp_status); \ | |
666 | } \ | |
667 | helper_float_check_status(env); \ | |
668 | return farg.ll; \ | |
bd23cd45 BS |
669 | } |
670 | ||
28288b48 TM |
671 | FPU_FCFI(fcfid, int64_to_float64, 0) |
672 | FPU_FCFI(fcfids, int64_to_float32, 1) | |
673 | FPU_FCFI(fcfidu, uint64_to_float64, 0) | |
674 | FPU_FCFI(fcfidus, uint64_to_float32, 1) | |
bd23cd45 | 675 | |
8e703949 BS |
676 | static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg, |
677 | int rounding_mode) | |
bd23cd45 BS |
678 | { |
679 | CPU_DoubleU farg; | |
680 | ||
681 | farg.ll = arg; | |
682 | ||
683 | if (unlikely(float64_is_signaling_nan(farg.d))) { | |
684 | /* sNaN round */ | |
c7386080 | 685 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
7dff9abe | 686 | farg.ll = arg | 0x0008000000000000ULL; |
bd23cd45 | 687 | } else { |
c7386080 TM |
688 | int inexact = get_float_exception_flags(&env->fp_status) & |
689 | float_flag_inexact; | |
bd23cd45 BS |
690 | set_float_rounding_mode(rounding_mode, &env->fp_status); |
691 | farg.ll = float64_round_to_int(farg.d, &env->fp_status); | |
692 | /* Restore rounding mode from FPSCR */ | |
8e703949 | 693 | fpscr_set_rounding_mode(env); |
c7386080 TM |
694 | |
695 | /* fri* does not set FPSCR[XX] */ | |
696 | if (!inexact) { | |
697 | env->fp_status.float_exception_flags &= ~float_flag_inexact; | |
698 | } | |
bd23cd45 | 699 | } |
c7386080 | 700 | helper_float_check_status(env); |
bd23cd45 BS |
701 | return farg.ll; |
702 | } | |
703 | ||
8e703949 | 704 | uint64_t helper_frin(CPUPPCState *env, uint64_t arg) |
bd23cd45 | 705 | { |
c7386080 | 706 | return do_fri(env, arg, float_round_ties_away); |
bd23cd45 BS |
707 | } |
708 | ||
8e703949 | 709 | uint64_t helper_friz(CPUPPCState *env, uint64_t arg) |
bd23cd45 | 710 | { |
8e703949 | 711 | return do_fri(env, arg, float_round_to_zero); |
bd23cd45 BS |
712 | } |
713 | ||
8e703949 | 714 | uint64_t helper_frip(CPUPPCState *env, uint64_t arg) |
bd23cd45 | 715 | { |
8e703949 | 716 | return do_fri(env, arg, float_round_up); |
bd23cd45 BS |
717 | } |
718 | ||
8e703949 | 719 | uint64_t helper_frim(CPUPPCState *env, uint64_t arg) |
bd23cd45 | 720 | { |
8e703949 | 721 | return do_fri(env, arg, float_round_down); |
bd23cd45 BS |
722 | } |
723 | ||
724 | /* fmadd - fmadd. */ | |
8e703949 BS |
725 | uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2, |
726 | uint64_t arg3) | |
bd23cd45 BS |
727 | { |
728 | CPU_DoubleU farg1, farg2, farg3; | |
729 | ||
730 | farg1.ll = arg1; | |
731 | farg2.ll = arg2; | |
732 | farg3.ll = arg3; | |
733 | ||
734 | if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || | |
735 | (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { | |
736 | /* Multiplication of zero by infinity */ | |
59800ec8 | 737 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); |
bd23cd45 BS |
738 | } else { |
739 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
740 | float64_is_signaling_nan(farg2.d) || | |
741 | float64_is_signaling_nan(farg3.d))) { | |
742 | /* sNaN operation */ | |
59800ec8 | 743 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
744 | } |
745 | /* This is the way the PowerPC specification defines it */ | |
746 | float128 ft0_128, ft1_128; | |
747 | ||
748 | ft0_128 = float64_to_float128(farg1.d, &env->fp_status); | |
749 | ft1_128 = float64_to_float128(farg2.d, &env->fp_status); | |
750 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); | |
751 | if (unlikely(float128_is_infinity(ft0_128) && | |
752 | float64_is_infinity(farg3.d) && | |
753 | float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) { | |
754 | /* Magnitude subtraction of infinities */ | |
59800ec8 | 755 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); |
bd23cd45 BS |
756 | } else { |
757 | ft1_128 = float64_to_float128(farg3.d, &env->fp_status); | |
758 | ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status); | |
759 | farg1.d = float128_to_float64(ft0_128, &env->fp_status); | |
760 | } | |
761 | } | |
762 | ||
763 | return farg1.ll; | |
764 | } | |
765 | ||
766 | /* fmsub - fmsub. */ | |
8e703949 BS |
767 | uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2, |
768 | uint64_t arg3) | |
bd23cd45 BS |
769 | { |
770 | CPU_DoubleU farg1, farg2, farg3; | |
771 | ||
772 | farg1.ll = arg1; | |
773 | farg2.ll = arg2; | |
774 | farg3.ll = arg3; | |
775 | ||
776 | if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || | |
777 | (float64_is_zero(farg1.d) && | |
778 | float64_is_infinity(farg2.d)))) { | |
779 | /* Multiplication of zero by infinity */ | |
59800ec8 | 780 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); |
bd23cd45 BS |
781 | } else { |
782 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
783 | float64_is_signaling_nan(farg2.d) || | |
784 | float64_is_signaling_nan(farg3.d))) { | |
785 | /* sNaN operation */ | |
59800ec8 | 786 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
787 | } |
788 | /* This is the way the PowerPC specification defines it */ | |
789 | float128 ft0_128, ft1_128; | |
790 | ||
791 | ft0_128 = float64_to_float128(farg1.d, &env->fp_status); | |
792 | ft1_128 = float64_to_float128(farg2.d, &env->fp_status); | |
793 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); | |
794 | if (unlikely(float128_is_infinity(ft0_128) && | |
795 | float64_is_infinity(farg3.d) && | |
796 | float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) { | |
797 | /* Magnitude subtraction of infinities */ | |
59800ec8 | 798 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); |
bd23cd45 BS |
799 | } else { |
800 | ft1_128 = float64_to_float128(farg3.d, &env->fp_status); | |
801 | ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status); | |
802 | farg1.d = float128_to_float64(ft0_128, &env->fp_status); | |
803 | } | |
804 | } | |
805 | return farg1.ll; | |
806 | } | |
807 | ||
808 | /* fnmadd - fnmadd. */ | |
8e703949 BS |
809 | uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2, |
810 | uint64_t arg3) | |
bd23cd45 BS |
811 | { |
812 | CPU_DoubleU farg1, farg2, farg3; | |
813 | ||
814 | farg1.ll = arg1; | |
815 | farg2.ll = arg2; | |
816 | farg3.ll = arg3; | |
817 | ||
818 | if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || | |
819 | (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { | |
820 | /* Multiplication of zero by infinity */ | |
59800ec8 | 821 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); |
bd23cd45 BS |
822 | } else { |
823 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
824 | float64_is_signaling_nan(farg2.d) || | |
825 | float64_is_signaling_nan(farg3.d))) { | |
826 | /* sNaN operation */ | |
59800ec8 | 827 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
828 | } |
829 | /* This is the way the PowerPC specification defines it */ | |
830 | float128 ft0_128, ft1_128; | |
831 | ||
832 | ft0_128 = float64_to_float128(farg1.d, &env->fp_status); | |
833 | ft1_128 = float64_to_float128(farg2.d, &env->fp_status); | |
834 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); | |
835 | if (unlikely(float128_is_infinity(ft0_128) && | |
836 | float64_is_infinity(farg3.d) && | |
837 | float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) { | |
838 | /* Magnitude subtraction of infinities */ | |
59800ec8 | 839 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); |
bd23cd45 BS |
840 | } else { |
841 | ft1_128 = float64_to_float128(farg3.d, &env->fp_status); | |
842 | ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status); | |
843 | farg1.d = float128_to_float64(ft0_128, &env->fp_status); | |
844 | } | |
845 | if (likely(!float64_is_any_nan(farg1.d))) { | |
846 | farg1.d = float64_chs(farg1.d); | |
847 | } | |
848 | } | |
849 | return farg1.ll; | |
850 | } | |
851 | ||
852 | /* fnmsub - fnmsub. */ | |
8e703949 BS |
853 | uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2, |
854 | uint64_t arg3) | |
bd23cd45 BS |
855 | { |
856 | CPU_DoubleU farg1, farg2, farg3; | |
857 | ||
858 | farg1.ll = arg1; | |
859 | farg2.ll = arg2; | |
860 | farg3.ll = arg3; | |
861 | ||
862 | if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || | |
863 | (float64_is_zero(farg1.d) && | |
864 | float64_is_infinity(farg2.d)))) { | |
865 | /* Multiplication of zero by infinity */ | |
59800ec8 | 866 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); |
bd23cd45 BS |
867 | } else { |
868 | if (unlikely(float64_is_signaling_nan(farg1.d) || | |
869 | float64_is_signaling_nan(farg2.d) || | |
870 | float64_is_signaling_nan(farg3.d))) { | |
871 | /* sNaN operation */ | |
59800ec8 | 872 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
873 | } |
874 | /* This is the way the PowerPC specification defines it */ | |
875 | float128 ft0_128, ft1_128; | |
876 | ||
877 | ft0_128 = float64_to_float128(farg1.d, &env->fp_status); | |
878 | ft1_128 = float64_to_float128(farg2.d, &env->fp_status); | |
879 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); | |
880 | if (unlikely(float128_is_infinity(ft0_128) && | |
881 | float64_is_infinity(farg3.d) && | |
882 | float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) { | |
883 | /* Magnitude subtraction of infinities */ | |
59800ec8 | 884 | farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); |
bd23cd45 BS |
885 | } else { |
886 | ft1_128 = float64_to_float128(farg3.d, &env->fp_status); | |
887 | ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status); | |
888 | farg1.d = float128_to_float64(ft0_128, &env->fp_status); | |
889 | } | |
890 | if (likely(!float64_is_any_nan(farg1.d))) { | |
891 | farg1.d = float64_chs(farg1.d); | |
892 | } | |
893 | } | |
894 | return farg1.ll; | |
895 | } | |
896 | ||
897 | /* frsp - frsp. */ | |
8e703949 | 898 | uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) |
bd23cd45 BS |
899 | { |
900 | CPU_DoubleU farg; | |
901 | float32 f32; | |
902 | ||
903 | farg.ll = arg; | |
904 | ||
905 | if (unlikely(float64_is_signaling_nan(farg.d))) { | |
906 | /* sNaN square root */ | |
59800ec8 | 907 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
908 | } |
909 | f32 = float64_to_float32(farg.d, &env->fp_status); | |
910 | farg.d = float32_to_float64(f32, &env->fp_status); | |
911 | ||
912 | return farg.ll; | |
913 | } | |
914 | ||
915 | /* fsqrt - fsqrt. */ | |
8e703949 | 916 | uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg) |
bd23cd45 BS |
917 | { |
918 | CPU_DoubleU farg; | |
919 | ||
920 | farg.ll = arg; | |
921 | ||
b748863a | 922 | if (unlikely(float64_is_any_nan(farg.d))) { |
bd23cd45 | 923 | if (unlikely(float64_is_signaling_nan(farg.d))) { |
b748863a | 924 | /* sNaN reciprocal square root */ |
59800ec8 | 925 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
b748863a | 926 | farg.ll = float64_snan_to_qnan(farg.ll); |
bd23cd45 | 927 | } |
b748863a TM |
928 | } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { |
929 | /* Square root of a negative nonzero number */ | |
930 | farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); | |
931 | } else { | |
bd23cd45 BS |
932 | farg.d = float64_sqrt(farg.d, &env->fp_status); |
933 | } | |
934 | return farg.ll; | |
935 | } | |
936 | ||
937 | /* fre - fre. */ | |
8e703949 | 938 | uint64_t helper_fre(CPUPPCState *env, uint64_t arg) |
bd23cd45 BS |
939 | { |
940 | CPU_DoubleU farg; | |
941 | ||
942 | farg.ll = arg; | |
943 | ||
944 | if (unlikely(float64_is_signaling_nan(farg.d))) { | |
945 | /* sNaN reciprocal */ | |
59800ec8 | 946 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
947 | } |
948 | farg.d = float64_div(float64_one, farg.d, &env->fp_status); | |
949 | return farg.d; | |
950 | } | |
951 | ||
952 | /* fres - fres. */ | |
8e703949 | 953 | uint64_t helper_fres(CPUPPCState *env, uint64_t arg) |
bd23cd45 BS |
954 | { |
955 | CPU_DoubleU farg; | |
956 | float32 f32; | |
957 | ||
958 | farg.ll = arg; | |
959 | ||
960 | if (unlikely(float64_is_signaling_nan(farg.d))) { | |
961 | /* sNaN reciprocal */ | |
59800ec8 | 962 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
963 | } |
964 | farg.d = float64_div(float64_one, farg.d, &env->fp_status); | |
965 | f32 = float64_to_float32(farg.d, &env->fp_status); | |
966 | farg.d = float32_to_float64(f32, &env->fp_status); | |
967 | ||
968 | return farg.ll; | |
969 | } | |
970 | ||
971 | /* frsqrte - frsqrte. */ | |
8e703949 | 972 | uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg) |
bd23cd45 BS |
973 | { |
974 | CPU_DoubleU farg; | |
bd23cd45 BS |
975 | |
976 | farg.ll = arg; | |
977 | ||
b748863a | 978 | if (unlikely(float64_is_any_nan(farg.d))) { |
bd23cd45 BS |
979 | if (unlikely(float64_is_signaling_nan(farg.d))) { |
980 | /* sNaN reciprocal square root */ | |
59800ec8 | 981 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
b748863a | 982 | farg.ll = float64_snan_to_qnan(farg.ll); |
bd23cd45 | 983 | } |
b748863a TM |
984 | } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { |
985 | /* Reciprocal square root of a negative nonzero number */ | |
986 | farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); | |
987 | } else { | |
bd23cd45 BS |
988 | farg.d = float64_sqrt(farg.d, &env->fp_status); |
989 | farg.d = float64_div(float64_one, farg.d, &env->fp_status); | |
bd23cd45 | 990 | } |
b748863a | 991 | |
bd23cd45 BS |
992 | return farg.ll; |
993 | } | |
994 | ||
995 | /* fsel - fsel. */ | |
8e703949 BS |
996 | uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2, |
997 | uint64_t arg3) | |
bd23cd45 BS |
998 | { |
999 | CPU_DoubleU farg1; | |
1000 | ||
1001 | farg1.ll = arg1; | |
1002 | ||
1003 | if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) && | |
1004 | !float64_is_any_nan(farg1.d)) { | |
1005 | return arg2; | |
1006 | } else { | |
1007 | return arg3; | |
1008 | } | |
1009 | } | |
1010 | ||
da29cb7b TM |
1011 | uint32_t helper_ftdiv(uint64_t fra, uint64_t frb) |
1012 | { | |
1013 | int fe_flag = 0; | |
1014 | int fg_flag = 0; | |
1015 | ||
1016 | if (unlikely(float64_is_infinity(fra) || | |
1017 | float64_is_infinity(frb) || | |
1018 | float64_is_zero(frb))) { | |
1019 | fe_flag = 1; | |
1020 | fg_flag = 1; | |
1021 | } else { | |
1022 | int e_a = ppc_float64_get_unbiased_exp(fra); | |
1023 | int e_b = ppc_float64_get_unbiased_exp(frb); | |
1024 | ||
1025 | if (unlikely(float64_is_any_nan(fra) || | |
1026 | float64_is_any_nan(frb))) { | |
1027 | fe_flag = 1; | |
1028 | } else if ((e_b <= -1022) || (e_b >= 1021)) { | |
1029 | fe_flag = 1; | |
1030 | } else if (!float64_is_zero(fra) && | |
1031 | (((e_a - e_b) >= 1023) || | |
1032 | ((e_a - e_b) <= -1021) || | |
1033 | (e_a <= -970))) { | |
1034 | fe_flag = 1; | |
1035 | } | |
1036 | ||
1037 | if (unlikely(float64_is_zero_or_denormal(frb))) { | |
1038 | /* XB is not zero because of the above check and */ | |
1039 | /* so must be denormalized. */ | |
1040 | fg_flag = 1; | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); | |
1045 | } | |
6d41d146 TM |
1046 | |
1047 | uint32_t helper_ftsqrt(uint64_t frb) | |
1048 | { | |
1049 | int fe_flag = 0; | |
1050 | int fg_flag = 0; | |
1051 | ||
1052 | if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) { | |
1053 | fe_flag = 1; | |
1054 | fg_flag = 1; | |
1055 | } else { | |
1056 | int e_b = ppc_float64_get_unbiased_exp(frb); | |
1057 | ||
1058 | if (unlikely(float64_is_any_nan(frb))) { | |
1059 | fe_flag = 1; | |
1060 | } else if (unlikely(float64_is_zero(frb))) { | |
1061 | fe_flag = 1; | |
1062 | } else if (unlikely(float64_is_neg(frb))) { | |
1063 | fe_flag = 1; | |
1064 | } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) { | |
1065 | fe_flag = 1; | |
1066 | } | |
1067 | ||
1068 | if (unlikely(float64_is_zero_or_denormal(frb))) { | |
1069 | /* XB is not zero because of the above check and */ | |
1070 | /* therefore must be denormalized. */ | |
1071 | fg_flag = 1; | |
1072 | } | |
1073 | } | |
1074 | ||
1075 | return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); | |
1076 | } | |
da29cb7b | 1077 | |
8e703949 BS |
1078 | void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2, |
1079 | uint32_t crfD) | |
bd23cd45 BS |
1080 | { |
1081 | CPU_DoubleU farg1, farg2; | |
1082 | uint32_t ret = 0; | |
1083 | ||
1084 | farg1.ll = arg1; | |
1085 | farg2.ll = arg2; | |
1086 | ||
1087 | if (unlikely(float64_is_any_nan(farg1.d) || | |
1088 | float64_is_any_nan(farg2.d))) { | |
1089 | ret = 0x01UL; | |
1090 | } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) { | |
1091 | ret = 0x08UL; | |
1092 | } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) { | |
1093 | ret = 0x04UL; | |
1094 | } else { | |
1095 | ret = 0x02UL; | |
1096 | } | |
1097 | ||
1098 | env->fpscr &= ~(0x0F << FPSCR_FPRF); | |
1099 | env->fpscr |= ret << FPSCR_FPRF; | |
1100 | env->crf[crfD] = ret; | |
1101 | if (unlikely(ret == 0x01UL | |
1102 | && (float64_is_signaling_nan(farg1.d) || | |
1103 | float64_is_signaling_nan(farg2.d)))) { | |
1104 | /* sNaN comparison */ | |
59800ec8 | 1105 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); |
bd23cd45 BS |
1106 | } |
1107 | } | |
1108 | ||
8e703949 BS |
1109 | void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2, |
1110 | uint32_t crfD) | |
bd23cd45 BS |
1111 | { |
1112 | CPU_DoubleU farg1, farg2; | |
1113 | uint32_t ret = 0; | |
1114 | ||
1115 | farg1.ll = arg1; | |
1116 | farg2.ll = arg2; | |
1117 | ||
1118 | if (unlikely(float64_is_any_nan(farg1.d) || | |
1119 | float64_is_any_nan(farg2.d))) { | |
1120 | ret = 0x01UL; | |
1121 | } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) { | |
1122 | ret = 0x08UL; | |
1123 | } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) { | |
1124 | ret = 0x04UL; | |
1125 | } else { | |
1126 | ret = 0x02UL; | |
1127 | } | |
1128 | ||
1129 | env->fpscr &= ~(0x0F << FPSCR_FPRF); | |
1130 | env->fpscr |= ret << FPSCR_FPRF; | |
1131 | env->crf[crfD] = ret; | |
1132 | if (unlikely(ret == 0x01UL)) { | |
1133 | if (float64_is_signaling_nan(farg1.d) || | |
1134 | float64_is_signaling_nan(farg2.d)) { | |
1135 | /* sNaN comparison */ | |
8e703949 | 1136 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | |
59800ec8 | 1137 | POWERPC_EXCP_FP_VXVC, 1); |
bd23cd45 BS |
1138 | } else { |
1139 | /* qNaN comparison */ | |
59800ec8 | 1140 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 1); |
bd23cd45 BS |
1141 | } |
1142 | } | |
1143 | } | |
1144 | ||
1145 | /* Single-precision floating-point conversions */ | |
8e703949 | 1146 | static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1147 | { |
1148 | CPU_FloatU u; | |
1149 | ||
1150 | u.f = int32_to_float32(val, &env->vec_status); | |
1151 | ||
1152 | return u.l; | |
1153 | } | |
1154 | ||
8e703949 | 1155 | static inline uint32_t efscfui(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1156 | { |
1157 | CPU_FloatU u; | |
1158 | ||
1159 | u.f = uint32_to_float32(val, &env->vec_status); | |
1160 | ||
1161 | return u.l; | |
1162 | } | |
1163 | ||
8e703949 | 1164 | static inline int32_t efsctsi(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1165 | { |
1166 | CPU_FloatU u; | |
1167 | ||
1168 | u.l = val; | |
1169 | /* NaN are not treated the same way IEEE 754 does */ | |
1170 | if (unlikely(float32_is_quiet_nan(u.f))) { | |
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | return float32_to_int32(u.f, &env->vec_status); | |
1175 | } | |
1176 | ||
8e703949 | 1177 | static inline uint32_t efsctui(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1178 | { |
1179 | CPU_FloatU u; | |
1180 | ||
1181 | u.l = val; | |
1182 | /* NaN are not treated the same way IEEE 754 does */ | |
1183 | if (unlikely(float32_is_quiet_nan(u.f))) { | |
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | return float32_to_uint32(u.f, &env->vec_status); | |
1188 | } | |
1189 | ||
8e703949 | 1190 | static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1191 | { |
1192 | CPU_FloatU u; | |
1193 | ||
1194 | u.l = val; | |
1195 | /* NaN are not treated the same way IEEE 754 does */ | |
1196 | if (unlikely(float32_is_quiet_nan(u.f))) { | |
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | return float32_to_int32_round_to_zero(u.f, &env->vec_status); | |
1201 | } | |
1202 | ||
8e703949 | 1203 | static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1204 | { |
1205 | CPU_FloatU u; | |
1206 | ||
1207 | u.l = val; | |
1208 | /* NaN are not treated the same way IEEE 754 does */ | |
1209 | if (unlikely(float32_is_quiet_nan(u.f))) { | |
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | return float32_to_uint32_round_to_zero(u.f, &env->vec_status); | |
1214 | } | |
1215 | ||
8e703949 | 1216 | static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1217 | { |
1218 | CPU_FloatU u; | |
1219 | float32 tmp; | |
1220 | ||
1221 | u.f = int32_to_float32(val, &env->vec_status); | |
1222 | tmp = int64_to_float32(1ULL << 32, &env->vec_status); | |
1223 | u.f = float32_div(u.f, tmp, &env->vec_status); | |
1224 | ||
1225 | return u.l; | |
1226 | } | |
1227 | ||
8e703949 | 1228 | static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1229 | { |
1230 | CPU_FloatU u; | |
1231 | float32 tmp; | |
1232 | ||
1233 | u.f = uint32_to_float32(val, &env->vec_status); | |
1234 | tmp = uint64_to_float32(1ULL << 32, &env->vec_status); | |
1235 | u.f = float32_div(u.f, tmp, &env->vec_status); | |
1236 | ||
1237 | return u.l; | |
1238 | } | |
1239 | ||
8e703949 | 1240 | static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1241 | { |
1242 | CPU_FloatU u; | |
1243 | float32 tmp; | |
1244 | ||
1245 | u.l = val; | |
1246 | /* NaN are not treated the same way IEEE 754 does */ | |
1247 | if (unlikely(float32_is_quiet_nan(u.f))) { | |
1248 | return 0; | |
1249 | } | |
1250 | tmp = uint64_to_float32(1ULL << 32, &env->vec_status); | |
1251 | u.f = float32_mul(u.f, tmp, &env->vec_status); | |
1252 | ||
1253 | return float32_to_int32(u.f, &env->vec_status); | |
1254 | } | |
1255 | ||
8e703949 | 1256 | static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1257 | { |
1258 | CPU_FloatU u; | |
1259 | float32 tmp; | |
1260 | ||
1261 | u.l = val; | |
1262 | /* NaN are not treated the same way IEEE 754 does */ | |
1263 | if (unlikely(float32_is_quiet_nan(u.f))) { | |
1264 | return 0; | |
1265 | } | |
1266 | tmp = uint64_to_float32(1ULL << 32, &env->vec_status); | |
1267 | u.f = float32_mul(u.f, tmp, &env->vec_status); | |
1268 | ||
1269 | return float32_to_uint32(u.f, &env->vec_status); | |
1270 | } | |
1271 | ||
8e703949 BS |
1272 | #define HELPER_SPE_SINGLE_CONV(name) \ |
1273 | uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \ | |
1274 | { \ | |
1275 | return e##name(env, val); \ | |
bd23cd45 BS |
1276 | } |
1277 | /* efscfsi */ | |
1278 | HELPER_SPE_SINGLE_CONV(fscfsi); | |
1279 | /* efscfui */ | |
1280 | HELPER_SPE_SINGLE_CONV(fscfui); | |
1281 | /* efscfuf */ | |
1282 | HELPER_SPE_SINGLE_CONV(fscfuf); | |
1283 | /* efscfsf */ | |
1284 | HELPER_SPE_SINGLE_CONV(fscfsf); | |
1285 | /* efsctsi */ | |
1286 | HELPER_SPE_SINGLE_CONV(fsctsi); | |
1287 | /* efsctui */ | |
1288 | HELPER_SPE_SINGLE_CONV(fsctui); | |
1289 | /* efsctsiz */ | |
1290 | HELPER_SPE_SINGLE_CONV(fsctsiz); | |
1291 | /* efsctuiz */ | |
1292 | HELPER_SPE_SINGLE_CONV(fsctuiz); | |
1293 | /* efsctsf */ | |
1294 | HELPER_SPE_SINGLE_CONV(fsctsf); | |
1295 | /* efsctuf */ | |
1296 | HELPER_SPE_SINGLE_CONV(fsctuf); | |
1297 | ||
8e703949 BS |
1298 | #define HELPER_SPE_VECTOR_CONV(name) \ |
1299 | uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \ | |
1300 | { \ | |
1301 | return ((uint64_t)e##name(env, val >> 32) << 32) | \ | |
1302 | (uint64_t)e##name(env, val); \ | |
bd23cd45 BS |
1303 | } |
1304 | /* evfscfsi */ | |
1305 | HELPER_SPE_VECTOR_CONV(fscfsi); | |
1306 | /* evfscfui */ | |
1307 | HELPER_SPE_VECTOR_CONV(fscfui); | |
1308 | /* evfscfuf */ | |
1309 | HELPER_SPE_VECTOR_CONV(fscfuf); | |
1310 | /* evfscfsf */ | |
1311 | HELPER_SPE_VECTOR_CONV(fscfsf); | |
1312 | /* evfsctsi */ | |
1313 | HELPER_SPE_VECTOR_CONV(fsctsi); | |
1314 | /* evfsctui */ | |
1315 | HELPER_SPE_VECTOR_CONV(fsctui); | |
1316 | /* evfsctsiz */ | |
1317 | HELPER_SPE_VECTOR_CONV(fsctsiz); | |
1318 | /* evfsctuiz */ | |
1319 | HELPER_SPE_VECTOR_CONV(fsctuiz); | |
1320 | /* evfsctsf */ | |
1321 | HELPER_SPE_VECTOR_CONV(fsctsf); | |
1322 | /* evfsctuf */ | |
1323 | HELPER_SPE_VECTOR_CONV(fsctuf); | |
1324 | ||
1325 | /* Single-precision floating-point arithmetic */ | |
8e703949 | 1326 | static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1327 | { |
1328 | CPU_FloatU u1, u2; | |
1329 | ||
1330 | u1.l = op1; | |
1331 | u2.l = op2; | |
1332 | u1.f = float32_add(u1.f, u2.f, &env->vec_status); | |
1333 | return u1.l; | |
1334 | } | |
1335 | ||
8e703949 | 1336 | static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1337 | { |
1338 | CPU_FloatU u1, u2; | |
1339 | ||
1340 | u1.l = op1; | |
1341 | u2.l = op2; | |
1342 | u1.f = float32_sub(u1.f, u2.f, &env->vec_status); | |
1343 | return u1.l; | |
1344 | } | |
1345 | ||
8e703949 | 1346 | static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1347 | { |
1348 | CPU_FloatU u1, u2; | |
1349 | ||
1350 | u1.l = op1; | |
1351 | u2.l = op2; | |
1352 | u1.f = float32_mul(u1.f, u2.f, &env->vec_status); | |
1353 | return u1.l; | |
1354 | } | |
1355 | ||
8e703949 | 1356 | static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1357 | { |
1358 | CPU_FloatU u1, u2; | |
1359 | ||
1360 | u1.l = op1; | |
1361 | u2.l = op2; | |
1362 | u1.f = float32_div(u1.f, u2.f, &env->vec_status); | |
1363 | return u1.l; | |
1364 | } | |
1365 | ||
8e703949 BS |
1366 | #define HELPER_SPE_SINGLE_ARITH(name) \ |
1367 | uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \ | |
1368 | { \ | |
1369 | return e##name(env, op1, op2); \ | |
bd23cd45 BS |
1370 | } |
1371 | /* efsadd */ | |
1372 | HELPER_SPE_SINGLE_ARITH(fsadd); | |
1373 | /* efssub */ | |
1374 | HELPER_SPE_SINGLE_ARITH(fssub); | |
1375 | /* efsmul */ | |
1376 | HELPER_SPE_SINGLE_ARITH(fsmul); | |
1377 | /* efsdiv */ | |
1378 | HELPER_SPE_SINGLE_ARITH(fsdiv); | |
1379 | ||
1380 | #define HELPER_SPE_VECTOR_ARITH(name) \ | |
8e703949 | 1381 | uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \ |
bd23cd45 | 1382 | { \ |
8e703949 BS |
1383 | return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \ |
1384 | (uint64_t)e##name(env, op1, op2); \ | |
bd23cd45 BS |
1385 | } |
1386 | /* evfsadd */ | |
1387 | HELPER_SPE_VECTOR_ARITH(fsadd); | |
1388 | /* evfssub */ | |
1389 | HELPER_SPE_VECTOR_ARITH(fssub); | |
1390 | /* evfsmul */ | |
1391 | HELPER_SPE_VECTOR_ARITH(fsmul); | |
1392 | /* evfsdiv */ | |
1393 | HELPER_SPE_VECTOR_ARITH(fsdiv); | |
1394 | ||
1395 | /* Single-precision floating-point comparisons */ | |
8e703949 | 1396 | static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1397 | { |
1398 | CPU_FloatU u1, u2; | |
1399 | ||
1400 | u1.l = op1; | |
1401 | u2.l = op2; | |
1402 | return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0; | |
1403 | } | |
1404 | ||
8e703949 | 1405 | static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1406 | { |
1407 | CPU_FloatU u1, u2; | |
1408 | ||
1409 | u1.l = op1; | |
1410 | u2.l = op2; | |
1411 | return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4; | |
1412 | } | |
1413 | ||
8e703949 | 1414 | static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1415 | { |
1416 | CPU_FloatU u1, u2; | |
1417 | ||
1418 | u1.l = op1; | |
1419 | u2.l = op2; | |
1420 | return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0; | |
1421 | } | |
1422 | ||
8e703949 | 1423 | static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1424 | { |
1425 | /* XXX: TODO: ignore special values (NaN, infinites, ...) */ | |
8e703949 | 1426 | return efscmplt(env, op1, op2); |
bd23cd45 BS |
1427 | } |
1428 | ||
8e703949 | 1429 | static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1430 | { |
1431 | /* XXX: TODO: ignore special values (NaN, infinites, ...) */ | |
8e703949 | 1432 | return efscmpgt(env, op1, op2); |
bd23cd45 BS |
1433 | } |
1434 | ||
8e703949 | 1435 | static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2) |
bd23cd45 BS |
1436 | { |
1437 | /* XXX: TODO: ignore special values (NaN, infinites, ...) */ | |
8e703949 | 1438 | return efscmpeq(env, op1, op2); |
bd23cd45 BS |
1439 | } |
1440 | ||
8e703949 BS |
1441 | #define HELPER_SINGLE_SPE_CMP(name) \ |
1442 | uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \ | |
1443 | { \ | |
1444 | return e##name(env, op1, op2) << 2; \ | |
bd23cd45 BS |
1445 | } |
1446 | /* efststlt */ | |
1447 | HELPER_SINGLE_SPE_CMP(fststlt); | |
1448 | /* efststgt */ | |
1449 | HELPER_SINGLE_SPE_CMP(fststgt); | |
1450 | /* efststeq */ | |
1451 | HELPER_SINGLE_SPE_CMP(fststeq); | |
1452 | /* efscmplt */ | |
1453 | HELPER_SINGLE_SPE_CMP(fscmplt); | |
1454 | /* efscmpgt */ | |
1455 | HELPER_SINGLE_SPE_CMP(fscmpgt); | |
1456 | /* efscmpeq */ | |
1457 | HELPER_SINGLE_SPE_CMP(fscmpeq); | |
1458 | ||
1459 | static inline uint32_t evcmp_merge(int t0, int t1) | |
1460 | { | |
1461 | return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1); | |
1462 | } | |
1463 | ||
1464 | #define HELPER_VECTOR_SPE_CMP(name) \ | |
8e703949 | 1465 | uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \ |
bd23cd45 | 1466 | { \ |
8e703949 BS |
1467 | return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \ |
1468 | e##name(env, op1, op2)); \ | |
bd23cd45 BS |
1469 | } |
1470 | /* evfststlt */ | |
1471 | HELPER_VECTOR_SPE_CMP(fststlt); | |
1472 | /* evfststgt */ | |
1473 | HELPER_VECTOR_SPE_CMP(fststgt); | |
1474 | /* evfststeq */ | |
1475 | HELPER_VECTOR_SPE_CMP(fststeq); | |
1476 | /* evfscmplt */ | |
1477 | HELPER_VECTOR_SPE_CMP(fscmplt); | |
1478 | /* evfscmpgt */ | |
1479 | HELPER_VECTOR_SPE_CMP(fscmpgt); | |
1480 | /* evfscmpeq */ | |
1481 | HELPER_VECTOR_SPE_CMP(fscmpeq); | |
1482 | ||
1483 | /* Double-precision floating-point conversion */ | |
8e703949 | 1484 | uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1485 | { |
1486 | CPU_DoubleU u; | |
1487 | ||
1488 | u.d = int32_to_float64(val, &env->vec_status); | |
1489 | ||
1490 | return u.ll; | |
1491 | } | |
1492 | ||
8e703949 | 1493 | uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1494 | { |
1495 | CPU_DoubleU u; | |
1496 | ||
1497 | u.d = int64_to_float64(val, &env->vec_status); | |
1498 | ||
1499 | return u.ll; | |
1500 | } | |
1501 | ||
8e703949 | 1502 | uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1503 | { |
1504 | CPU_DoubleU u; | |
1505 | ||
1506 | u.d = uint32_to_float64(val, &env->vec_status); | |
1507 | ||
1508 | return u.ll; | |
1509 | } | |
1510 | ||
8e703949 | 1511 | uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1512 | { |
1513 | CPU_DoubleU u; | |
1514 | ||
1515 | u.d = uint64_to_float64(val, &env->vec_status); | |
1516 | ||
1517 | return u.ll; | |
1518 | } | |
1519 | ||
8e703949 | 1520 | uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1521 | { |
1522 | CPU_DoubleU u; | |
1523 | ||
1524 | u.ll = val; | |
1525 | /* NaN are not treated the same way IEEE 754 does */ | |
1526 | if (unlikely(float64_is_any_nan(u.d))) { | |
1527 | return 0; | |
1528 | } | |
1529 | ||
1530 | return float64_to_int32(u.d, &env->vec_status); | |
1531 | } | |
1532 | ||
8e703949 | 1533 | uint32_t helper_efdctui(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1534 | { |
1535 | CPU_DoubleU u; | |
1536 | ||
1537 | u.ll = val; | |
1538 | /* NaN are not treated the same way IEEE 754 does */ | |
1539 | if (unlikely(float64_is_any_nan(u.d))) { | |
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | return float64_to_uint32(u.d, &env->vec_status); | |
1544 | } | |
1545 | ||
8e703949 | 1546 | uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1547 | { |
1548 | CPU_DoubleU u; | |
1549 | ||
1550 | u.ll = val; | |
1551 | /* NaN are not treated the same way IEEE 754 does */ | |
1552 | if (unlikely(float64_is_any_nan(u.d))) { | |
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | return float64_to_int32_round_to_zero(u.d, &env->vec_status); | |
1557 | } | |
1558 | ||
8e703949 | 1559 | uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1560 | { |
1561 | CPU_DoubleU u; | |
1562 | ||
1563 | u.ll = val; | |
1564 | /* NaN are not treated the same way IEEE 754 does */ | |
1565 | if (unlikely(float64_is_any_nan(u.d))) { | |
1566 | return 0; | |
1567 | } | |
1568 | ||
1569 | return float64_to_int64_round_to_zero(u.d, &env->vec_status); | |
1570 | } | |
1571 | ||
8e703949 | 1572 | uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1573 | { |
1574 | CPU_DoubleU u; | |
1575 | ||
1576 | u.ll = val; | |
1577 | /* NaN are not treated the same way IEEE 754 does */ | |
1578 | if (unlikely(float64_is_any_nan(u.d))) { | |
1579 | return 0; | |
1580 | } | |
1581 | ||
1582 | return float64_to_uint32_round_to_zero(u.d, &env->vec_status); | |
1583 | } | |
1584 | ||
8e703949 | 1585 | uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1586 | { |
1587 | CPU_DoubleU u; | |
1588 | ||
1589 | u.ll = val; | |
1590 | /* NaN are not treated the same way IEEE 754 does */ | |
1591 | if (unlikely(float64_is_any_nan(u.d))) { | |
1592 | return 0; | |
1593 | } | |
1594 | ||
1595 | return float64_to_uint64_round_to_zero(u.d, &env->vec_status); | |
1596 | } | |
1597 | ||
8e703949 | 1598 | uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1599 | { |
1600 | CPU_DoubleU u; | |
1601 | float64 tmp; | |
1602 | ||
1603 | u.d = int32_to_float64(val, &env->vec_status); | |
1604 | tmp = int64_to_float64(1ULL << 32, &env->vec_status); | |
1605 | u.d = float64_div(u.d, tmp, &env->vec_status); | |
1606 | ||
1607 | return u.ll; | |
1608 | } | |
1609 | ||
8e703949 | 1610 | uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1611 | { |
1612 | CPU_DoubleU u; | |
1613 | float64 tmp; | |
1614 | ||
1615 | u.d = uint32_to_float64(val, &env->vec_status); | |
1616 | tmp = int64_to_float64(1ULL << 32, &env->vec_status); | |
1617 | u.d = float64_div(u.d, tmp, &env->vec_status); | |
1618 | ||
1619 | return u.ll; | |
1620 | } | |
1621 | ||
8e703949 | 1622 | uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1623 | { |
1624 | CPU_DoubleU u; | |
1625 | float64 tmp; | |
1626 | ||
1627 | u.ll = val; | |
1628 | /* NaN are not treated the same way IEEE 754 does */ | |
1629 | if (unlikely(float64_is_any_nan(u.d))) { | |
1630 | return 0; | |
1631 | } | |
1632 | tmp = uint64_to_float64(1ULL << 32, &env->vec_status); | |
1633 | u.d = float64_mul(u.d, tmp, &env->vec_status); | |
1634 | ||
1635 | return float64_to_int32(u.d, &env->vec_status); | |
1636 | } | |
1637 | ||
8e703949 | 1638 | uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1639 | { |
1640 | CPU_DoubleU u; | |
1641 | float64 tmp; | |
1642 | ||
1643 | u.ll = val; | |
1644 | /* NaN are not treated the same way IEEE 754 does */ | |
1645 | if (unlikely(float64_is_any_nan(u.d))) { | |
1646 | return 0; | |
1647 | } | |
1648 | tmp = uint64_to_float64(1ULL << 32, &env->vec_status); | |
1649 | u.d = float64_mul(u.d, tmp, &env->vec_status); | |
1650 | ||
1651 | return float64_to_uint32(u.d, &env->vec_status); | |
1652 | } | |
1653 | ||
8e703949 | 1654 | uint32_t helper_efscfd(CPUPPCState *env, uint64_t val) |
bd23cd45 BS |
1655 | { |
1656 | CPU_DoubleU u1; | |
1657 | CPU_FloatU u2; | |
1658 | ||
1659 | u1.ll = val; | |
1660 | u2.f = float64_to_float32(u1.d, &env->vec_status); | |
1661 | ||
1662 | return u2.l; | |
1663 | } | |
1664 | ||
8e703949 | 1665 | uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val) |
bd23cd45 BS |
1666 | { |
1667 | CPU_DoubleU u2; | |
1668 | CPU_FloatU u1; | |
1669 | ||
1670 | u1.l = val; | |
1671 | u2.d = float32_to_float64(u1.f, &env->vec_status); | |
1672 | ||
1673 | return u2.ll; | |
1674 | } | |
1675 | ||
1676 | /* Double precision fixed-point arithmetic */ | |
8e703949 | 1677 | uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1678 | { |
1679 | CPU_DoubleU u1, u2; | |
1680 | ||
1681 | u1.ll = op1; | |
1682 | u2.ll = op2; | |
1683 | u1.d = float64_add(u1.d, u2.d, &env->vec_status); | |
1684 | return u1.ll; | |
1685 | } | |
1686 | ||
8e703949 | 1687 | uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1688 | { |
1689 | CPU_DoubleU u1, u2; | |
1690 | ||
1691 | u1.ll = op1; | |
1692 | u2.ll = op2; | |
1693 | u1.d = float64_sub(u1.d, u2.d, &env->vec_status); | |
1694 | return u1.ll; | |
1695 | } | |
1696 | ||
8e703949 | 1697 | uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1698 | { |
1699 | CPU_DoubleU u1, u2; | |
1700 | ||
1701 | u1.ll = op1; | |
1702 | u2.ll = op2; | |
1703 | u1.d = float64_mul(u1.d, u2.d, &env->vec_status); | |
1704 | return u1.ll; | |
1705 | } | |
1706 | ||
8e703949 | 1707 | uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1708 | { |
1709 | CPU_DoubleU u1, u2; | |
1710 | ||
1711 | u1.ll = op1; | |
1712 | u2.ll = op2; | |
1713 | u1.d = float64_div(u1.d, u2.d, &env->vec_status); | |
1714 | return u1.ll; | |
1715 | } | |
1716 | ||
1717 | /* Double precision floating point helpers */ | |
8e703949 | 1718 | uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1719 | { |
1720 | CPU_DoubleU u1, u2; | |
1721 | ||
1722 | u1.ll = op1; | |
1723 | u2.ll = op2; | |
1724 | return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0; | |
1725 | } | |
1726 | ||
8e703949 | 1727 | uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1728 | { |
1729 | CPU_DoubleU u1, u2; | |
1730 | ||
1731 | u1.ll = op1; | |
1732 | u2.ll = op2; | |
1733 | return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4; | |
1734 | } | |
1735 | ||
8e703949 | 1736 | uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1737 | { |
1738 | CPU_DoubleU u1, u2; | |
1739 | ||
1740 | u1.ll = op1; | |
1741 | u2.ll = op2; | |
1742 | return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0; | |
1743 | } | |
1744 | ||
8e703949 | 1745 | uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1746 | { |
1747 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
8e703949 | 1748 | return helper_efdtstlt(env, op1, op2); |
bd23cd45 BS |
1749 | } |
1750 | ||
8e703949 | 1751 | uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1752 | { |
1753 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
8e703949 | 1754 | return helper_efdtstgt(env, op1, op2); |
bd23cd45 BS |
1755 | } |
1756 | ||
8e703949 | 1757 | uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2) |
bd23cd45 BS |
1758 | { |
1759 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
8e703949 | 1760 | return helper_efdtsteq(env, op1, op2); |
bd23cd45 | 1761 | } |
3c3cbbdc TM |
1762 | |
1763 | #define DECODE_SPLIT(opcode, shift1, nb1, shift2, nb2) \ | |
1764 | (((((opcode) >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \ | |
1765 | (((opcode) >> (shift2)) & ((1 << (nb2)) - 1))) | |
1766 | ||
1767 | #define xT(opcode) DECODE_SPLIT(opcode, 0, 1, 21, 5) | |
1768 | #define xA(opcode) DECODE_SPLIT(opcode, 2, 1, 16, 5) | |
1769 | #define xB(opcode) DECODE_SPLIT(opcode, 1, 1, 11, 5) | |
1770 | #define xC(opcode) DECODE_SPLIT(opcode, 3, 1, 6, 5) | |
1771 | #define BF(opcode) (((opcode) >> (31-8)) & 7) | |
1772 | ||
1773 | typedef union _ppc_vsr_t { | |
1774 | uint64_t u64[2]; | |
1775 | uint32_t u32[4]; | |
1776 | float32 f32[4]; | |
1777 | float64 f64[2]; | |
1778 | } ppc_vsr_t; | |
1779 | ||
80189035 TM |
1780 | #if defined(HOST_WORDS_BIGENDIAN) |
1781 | #define VsrW(i) u32[i] | |
1782 | #define VsrD(i) u64[i] | |
1783 | #else | |
1784 | #define VsrW(i) u32[3-(i)] | |
1785 | #define VsrD(i) u64[1-(i)] | |
1786 | #endif | |
1787 | ||
3c3cbbdc TM |
1788 | static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) |
1789 | { | |
1790 | if (n < 32) { | |
d359db00 TM |
1791 | vsr->VsrD(0) = env->fpr[n]; |
1792 | vsr->VsrD(1) = env->vsr[n]; | |
3c3cbbdc TM |
1793 | } else { |
1794 | vsr->u64[0] = env->avr[n-32].u64[0]; | |
1795 | vsr->u64[1] = env->avr[n-32].u64[1]; | |
1796 | } | |
1797 | } | |
1798 | ||
1799 | static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) | |
1800 | { | |
1801 | if (n < 32) { | |
d359db00 TM |
1802 | env->fpr[n] = vsr->VsrD(0); |
1803 | env->vsr[n] = vsr->VsrD(1); | |
3c3cbbdc TM |
1804 | } else { |
1805 | env->avr[n-32].u64[0] = vsr->u64[0]; | |
1806 | env->avr[n-32].u64[1] = vsr->u64[1]; | |
1807 | } | |
1808 | } | |
1809 | ||
1810 | #define float64_to_float64(x, env) x | |
ee6e02c0 TM |
1811 | |
1812 | ||
1813 | /* VSX_ADD_SUB - VSX floating point add/subract | |
1814 | * name - instruction mnemonic | |
1815 | * op - operation (add or sub) | |
1816 | * nels - number of elements (1, 2 or 4) | |
1817 | * tp - type (float32 or float64) | |
bcb7652e | 1818 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
ee6e02c0 TM |
1819 | * sfprf - set FPRF |
1820 | */ | |
3fd0aadf | 1821 | #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \ |
ee6e02c0 TM |
1822 | void helper_##name(CPUPPCState *env, uint32_t opcode) \ |
1823 | { \ | |
1824 | ppc_vsr_t xt, xa, xb; \ | |
1825 | int i; \ | |
1826 | \ | |
1827 | getVSR(xA(opcode), &xa, env); \ | |
1828 | getVSR(xB(opcode), &xb, env); \ | |
1829 | getVSR(xT(opcode), &xt, env); \ | |
1830 | helper_reset_fpstatus(env); \ | |
1831 | \ | |
1832 | for (i = 0; i < nels; i++) { \ | |
1833 | float_status tstat = env->fp_status; \ | |
1834 | set_float_exception_flags(0, &tstat); \ | |
bcb7652e | 1835 | xt.fld = tp##_##op(xa.fld, xb.fld, &tstat); \ |
ee6e02c0 TM |
1836 | env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ |
1837 | \ | |
1838 | if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ | |
bcb7652e | 1839 | if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \ |
ee6e02c0 | 1840 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \ |
bcb7652e TM |
1841 | } else if (tp##_is_signaling_nan(xa.fld) || \ |
1842 | tp##_is_signaling_nan(xb.fld)) { \ | |
ee6e02c0 TM |
1843 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ |
1844 | } \ | |
1845 | } \ | |
1846 | \ | |
3fd0aadf | 1847 | if (r2sp) { \ |
bcb7652e | 1848 | xt.fld = helper_frsp(env, xt.fld); \ |
3fd0aadf TM |
1849 | } \ |
1850 | \ | |
ee6e02c0 | 1851 | if (sfprf) { \ |
58dd0a47 | 1852 | helper_compute_fprf(env, xt.fld); \ |
ee6e02c0 TM |
1853 | } \ |
1854 | } \ | |
1855 | putVSR(xT(opcode), &xt, env); \ | |
1856 | helper_float_check_status(env); \ | |
1857 | } | |
1858 | ||
bcb7652e TM |
1859 | VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0) |
1860 | VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1) | |
1861 | VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0) | |
1862 | VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0) | |
1863 | VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0) | |
1864 | VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1) | |
1865 | VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0) | |
1866 | VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0) | |
5e591d88 TM |
1867 | |
1868 | /* VSX_MUL - VSX floating point multiply | |
1869 | * op - instruction mnemonic | |
1870 | * nels - number of elements (1, 2 or 4) | |
1871 | * tp - type (float32 or float64) | |
bcb7652e | 1872 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
5e591d88 TM |
1873 | * sfprf - set FPRF |
1874 | */ | |
ab9408a2 | 1875 | #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \ |
5e591d88 TM |
1876 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ |
1877 | { \ | |
1878 | ppc_vsr_t xt, xa, xb; \ | |
1879 | int i; \ | |
1880 | \ | |
1881 | getVSR(xA(opcode), &xa, env); \ | |
1882 | getVSR(xB(opcode), &xb, env); \ | |
1883 | getVSR(xT(opcode), &xt, env); \ | |
1884 | helper_reset_fpstatus(env); \ | |
1885 | \ | |
1886 | for (i = 0; i < nels; i++) { \ | |
1887 | float_status tstat = env->fp_status; \ | |
1888 | set_float_exception_flags(0, &tstat); \ | |
bcb7652e | 1889 | xt.fld = tp##_mul(xa.fld, xb.fld, &tstat); \ |
5e591d88 TM |
1890 | env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ |
1891 | \ | |
1892 | if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ | |
bcb7652e TM |
1893 | if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) || \ |
1894 | (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) { \ | |
5e591d88 | 1895 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf); \ |
bcb7652e TM |
1896 | } else if (tp##_is_signaling_nan(xa.fld) || \ |
1897 | tp##_is_signaling_nan(xb.fld)) { \ | |
5e591d88 TM |
1898 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ |
1899 | } \ | |
1900 | } \ | |
1901 | \ | |
ab9408a2 | 1902 | if (r2sp) { \ |
bcb7652e | 1903 | xt.fld = helper_frsp(env, xt.fld); \ |
ab9408a2 TM |
1904 | } \ |
1905 | \ | |
5e591d88 | 1906 | if (sfprf) { \ |
58dd0a47 | 1907 | helper_compute_fprf(env, xt.fld); \ |
5e591d88 TM |
1908 | } \ |
1909 | } \ | |
1910 | \ | |
1911 | putVSR(xT(opcode), &xt, env); \ | |
1912 | helper_float_check_status(env); \ | |
1913 | } | |
1914 | ||
bcb7652e TM |
1915 | VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0) |
1916 | VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1) | |
1917 | VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0) | |
1918 | VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0) | |
4b98eeef TM |
1919 | |
1920 | /* VSX_DIV - VSX floating point divide | |
1921 | * op - instruction mnemonic | |
1922 | * nels - number of elements (1, 2 or 4) | |
1923 | * tp - type (float32 or float64) | |
bcb7652e | 1924 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
4b98eeef TM |
1925 | * sfprf - set FPRF |
1926 | */ | |
b24d0b47 | 1927 | #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \ |
4b98eeef TM |
1928 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ |
1929 | { \ | |
1930 | ppc_vsr_t xt, xa, xb; \ | |
1931 | int i; \ | |
1932 | \ | |
1933 | getVSR(xA(opcode), &xa, env); \ | |
1934 | getVSR(xB(opcode), &xb, env); \ | |
1935 | getVSR(xT(opcode), &xt, env); \ | |
1936 | helper_reset_fpstatus(env); \ | |
1937 | \ | |
1938 | for (i = 0; i < nels; i++) { \ | |
1939 | float_status tstat = env->fp_status; \ | |
1940 | set_float_exception_flags(0, &tstat); \ | |
bcb7652e | 1941 | xt.fld = tp##_div(xa.fld, xb.fld, &tstat); \ |
4b98eeef TM |
1942 | env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ |
1943 | \ | |
1944 | if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ | |
bcb7652e | 1945 | if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \ |
4b98eeef | 1946 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf); \ |
bcb7652e TM |
1947 | } else if (tp##_is_zero(xa.fld) && \ |
1948 | tp##_is_zero(xb.fld)) { \ | |
4b98eeef | 1949 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \ |
bcb7652e TM |
1950 | } else if (tp##_is_signaling_nan(xa.fld) || \ |
1951 | tp##_is_signaling_nan(xb.fld)) { \ | |
4b98eeef TM |
1952 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ |
1953 | } \ | |
1954 | } \ | |
1955 | \ | |
b24d0b47 | 1956 | if (r2sp) { \ |
bcb7652e | 1957 | xt.fld = helper_frsp(env, xt.fld); \ |
b24d0b47 TM |
1958 | } \ |
1959 | \ | |
4b98eeef | 1960 | if (sfprf) { \ |
58dd0a47 | 1961 | helper_compute_fprf(env, xt.fld); \ |
4b98eeef TM |
1962 | } \ |
1963 | } \ | |
1964 | \ | |
1965 | putVSR(xT(opcode), &xt, env); \ | |
1966 | helper_float_check_status(env); \ | |
1967 | } | |
1968 | ||
bcb7652e TM |
1969 | VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0) |
1970 | VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1) | |
1971 | VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0) | |
1972 | VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0) | |
2009227f TM |
1973 | |
1974 | /* VSX_RE - VSX floating point reciprocal estimate | |
1975 | * op - instruction mnemonic | |
1976 | * nels - number of elements (1, 2 or 4) | |
1977 | * tp - type (float32 or float64) | |
bcb7652e | 1978 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
2009227f TM |
1979 | * sfprf - set FPRF |
1980 | */ | |
2c0c52ae | 1981 | #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \ |
2009227f TM |
1982 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ |
1983 | { \ | |
1984 | ppc_vsr_t xt, xb; \ | |
1985 | int i; \ | |
1986 | \ | |
1987 | getVSR(xB(opcode), &xb, env); \ | |
1988 | getVSR(xT(opcode), &xt, env); \ | |
1989 | helper_reset_fpstatus(env); \ | |
1990 | \ | |
1991 | for (i = 0; i < nels; i++) { \ | |
bcb7652e | 1992 | if (unlikely(tp##_is_signaling_nan(xb.fld))) { \ |
2009227f TM |
1993 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ |
1994 | } \ | |
bcb7652e | 1995 | xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status); \ |
2c0c52ae TM |
1996 | \ |
1997 | if (r2sp) { \ | |
bcb7652e | 1998 | xt.fld = helper_frsp(env, xt.fld); \ |
2c0c52ae TM |
1999 | } \ |
2000 | \ | |
2009227f | 2001 | if (sfprf) { \ |
58dd0a47 | 2002 | helper_compute_fprf(env, xt.fld); \ |
2009227f TM |
2003 | } \ |
2004 | } \ | |
2005 | \ | |
2006 | putVSR(xT(opcode), &xt, env); \ | |
2007 | helper_float_check_status(env); \ | |
2008 | } | |
2009 | ||
bcb7652e TM |
2010 | VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0) |
2011 | VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1) | |
2012 | VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0) | |
2013 | VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0) | |
d32404fe TM |
2014 | |
2015 | /* VSX_SQRT - VSX floating point square root | |
2016 | * op - instruction mnemonic | |
2017 | * nels - number of elements (1, 2 or 4) | |
2018 | * tp - type (float32 or float64) | |
bcb7652e | 2019 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
d32404fe TM |
2020 | * sfprf - set FPRF |
2021 | */ | |
cea4e574 | 2022 | #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \ |
d32404fe TM |
2023 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ |
2024 | { \ | |
2025 | ppc_vsr_t xt, xb; \ | |
2026 | int i; \ | |
2027 | \ | |
2028 | getVSR(xB(opcode), &xb, env); \ | |
2029 | getVSR(xT(opcode), &xt, env); \ | |
2030 | helper_reset_fpstatus(env); \ | |
2031 | \ | |
2032 | for (i = 0; i < nels; i++) { \ | |
2033 | float_status tstat = env->fp_status; \ | |
2034 | set_float_exception_flags(0, &tstat); \ | |
bcb7652e | 2035 | xt.fld = tp##_sqrt(xb.fld, &tstat); \ |
d32404fe TM |
2036 | env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ |
2037 | \ | |
2038 | if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ | |
bcb7652e | 2039 | if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \ |
d32404fe | 2040 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \ |
bcb7652e | 2041 | } else if (tp##_is_signaling_nan(xb.fld)) { \ |
d32404fe TM |
2042 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ |
2043 | } \ | |
2044 | } \ | |
2045 | \ | |
cea4e574 | 2046 | if (r2sp) { \ |
bcb7652e | 2047 | xt.fld = helper_frsp(env, xt.fld); \ |
cea4e574 TM |
2048 | } \ |
2049 | \ | |
d32404fe | 2050 | if (sfprf) { \ |
58dd0a47 | 2051 | helper_compute_fprf(env, xt.fld); \ |
d32404fe TM |
2052 | } \ |
2053 | } \ | |
2054 | \ | |
2055 | putVSR(xT(opcode), &xt, env); \ | |
2056 | helper_float_check_status(env); \ | |
2057 | } | |
2058 | ||
bcb7652e TM |
2059 | VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0) |
2060 | VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1) | |
2061 | VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0) | |
2062 | VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0) | |
d3f9df8f TM |
2063 | |
2064 | /* VSX_RSQRTE - VSX floating point reciprocal square root estimate | |
2065 | * op - instruction mnemonic | |
2066 | * nels - number of elements (1, 2 or 4) | |
2067 | * tp - type (float32 or float64) | |
bcb7652e | 2068 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
d3f9df8f TM |
2069 | * sfprf - set FPRF |
2070 | */ | |
968e76bc | 2071 | #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \ |
d3f9df8f TM |
2072 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ |
2073 | { \ | |
2074 | ppc_vsr_t xt, xb; \ | |
2075 | int i; \ | |
2076 | \ | |
2077 | getVSR(xB(opcode), &xb, env); \ | |
2078 | getVSR(xT(opcode), &xt, env); \ | |
2079 | helper_reset_fpstatus(env); \ | |
2080 | \ | |
2081 | for (i = 0; i < nels; i++) { \ | |
2082 | float_status tstat = env->fp_status; \ | |
2083 | set_float_exception_flags(0, &tstat); \ | |
bcb7652e TM |
2084 | xt.fld = tp##_sqrt(xb.fld, &tstat); \ |
2085 | xt.fld = tp##_div(tp##_one, xt.fld, &tstat); \ | |
d3f9df8f TM |
2086 | env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ |
2087 | \ | |
2088 | if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ | |
bcb7652e | 2089 | if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \ |
d3f9df8f | 2090 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \ |
bcb7652e | 2091 | } else if (tp##_is_signaling_nan(xb.fld)) { \ |
d3f9df8f TM |
2092 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ |
2093 | } \ | |
2094 | } \ | |
2095 | \ | |
968e76bc | 2096 | if (r2sp) { \ |
bcb7652e | 2097 | xt.fld = helper_frsp(env, xt.fld); \ |
968e76bc TM |
2098 | } \ |
2099 | \ | |
d3f9df8f | 2100 | if (sfprf) { \ |
58dd0a47 | 2101 | helper_compute_fprf(env, xt.fld); \ |
d3f9df8f TM |
2102 | } \ |
2103 | } \ | |
2104 | \ | |
2105 | putVSR(xT(opcode), &xt, env); \ | |
2106 | helper_float_check_status(env); \ | |
2107 | } | |
2108 | ||
bcb7652e TM |
2109 | VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0) |
2110 | VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1) | |
2111 | VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0) | |
2112 | VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0) | |
bc80838f | 2113 | |
bc80838f TM |
2114 | /* VSX_TDIV - VSX floating point test for divide |
2115 | * op - instruction mnemonic | |
2116 | * nels - number of elements (1, 2 or 4) | |
2117 | * tp - type (float32 or float64) | |
bcb7652e | 2118 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
bc80838f TM |
2119 | * emin - minimum unbiased exponent |
2120 | * emax - maximum unbiased exponent | |
2121 | * nbits - number of fraction bits | |
2122 | */ | |
2123 | #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \ | |
2124 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ | |
2125 | { \ | |
2126 | ppc_vsr_t xa, xb; \ | |
2127 | int i; \ | |
2128 | int fe_flag = 0; \ | |
2129 | int fg_flag = 0; \ | |
2130 | \ | |
2131 | getVSR(xA(opcode), &xa, env); \ | |
2132 | getVSR(xB(opcode), &xb, env); \ | |
2133 | \ | |
2134 | for (i = 0; i < nels; i++) { \ | |
bcb7652e TM |
2135 | if (unlikely(tp##_is_infinity(xa.fld) || \ |
2136 | tp##_is_infinity(xb.fld) || \ | |
2137 | tp##_is_zero(xb.fld))) { \ | |
bc80838f TM |
2138 | fe_flag = 1; \ |
2139 | fg_flag = 1; \ | |
2140 | } else { \ | |
bcb7652e TM |
2141 | int e_a = ppc_##tp##_get_unbiased_exp(xa.fld); \ |
2142 | int e_b = ppc_##tp##_get_unbiased_exp(xb.fld); \ | |
bc80838f | 2143 | \ |
bcb7652e TM |
2144 | if (unlikely(tp##_is_any_nan(xa.fld) || \ |
2145 | tp##_is_any_nan(xb.fld))) { \ | |
bc80838f TM |
2146 | fe_flag = 1; \ |
2147 | } else if ((e_b <= emin) || (e_b >= (emax-2))) { \ | |
2148 | fe_flag = 1; \ | |
bcb7652e | 2149 | } else if (!tp##_is_zero(xa.fld) && \ |
bc80838f TM |
2150 | (((e_a - e_b) >= emax) || \ |
2151 | ((e_a - e_b) <= (emin+1)) || \ | |
2152 | (e_a <= (emin+nbits)))) { \ | |
2153 | fe_flag = 1; \ | |
2154 | } \ | |
2155 | \ | |
bcb7652e | 2156 | if (unlikely(tp##_is_zero_or_denormal(xb.fld))) { \ |
bc80838f TM |
2157 | /* XB is not zero because of the above check and */ \ |
2158 | /* so must be denormalized. */ \ | |
2159 | fg_flag = 1; \ | |
2160 | } \ | |
2161 | } \ | |
2162 | } \ | |
2163 | \ | |
2164 | env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \ | |
2165 | } | |
2166 | ||
bcb7652e TM |
2167 | VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52) |
2168 | VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52) | |
2169 | VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23) | |
5cb151ac TM |
2170 | |
2171 | /* VSX_TSQRT - VSX floating point test for square root | |
2172 | * op - instruction mnemonic | |
2173 | * nels - number of elements (1, 2 or 4) | |
2174 | * tp - type (float32 or float64) | |
bcb7652e | 2175 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
5cb151ac TM |
2176 | * emin - minimum unbiased exponent |
2177 | * emax - maximum unbiased exponent | |
2178 | * nbits - number of fraction bits | |
2179 | */ | |
2180 | #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \ | |
2181 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ | |
2182 | { \ | |
2183 | ppc_vsr_t xa, xb; \ | |
2184 | int i; \ | |
2185 | int fe_flag = 0; \ | |
2186 | int fg_flag = 0; \ | |
2187 | \ | |
2188 | getVSR(xA(opcode), &xa, env); \ | |
2189 | getVSR(xB(opcode), &xb, env); \ | |
2190 | \ | |
2191 | for (i = 0; i < nels; i++) { \ | |
bcb7652e TM |
2192 | if (unlikely(tp##_is_infinity(xb.fld) || \ |
2193 | tp##_is_zero(xb.fld))) { \ | |
5cb151ac TM |
2194 | fe_flag = 1; \ |
2195 | fg_flag = 1; \ | |
2196 | } else { \ | |
bcb7652e | 2197 | int e_b = ppc_##tp##_get_unbiased_exp(xb.fld); \ |
5cb151ac | 2198 | \ |
bcb7652e | 2199 | if (unlikely(tp##_is_any_nan(xb.fld))) { \ |
5cb151ac | 2200 | fe_flag = 1; \ |
bcb7652e | 2201 | } else if (unlikely(tp##_is_zero(xb.fld))) { \ |
5cb151ac | 2202 | fe_flag = 1; \ |
bcb7652e | 2203 | } else if (unlikely(tp##_is_neg(xb.fld))) { \ |
5cb151ac | 2204 | fe_flag = 1; \ |
bcb7652e | 2205 | } else if (!tp##_is_zero(xb.fld) && \ |
5cb151ac TM |
2206 | (e_b <= (emin+nbits))) { \ |
2207 | fe_flag = 1; \ | |
2208 | } \ | |
2209 | \ | |
bcb7652e | 2210 | if (unlikely(tp##_is_zero_or_denormal(xb.fld))) { \ |
5cb151ac TM |
2211 | /* XB is not zero because of the above check and */ \ |
2212 | /* therefore must be denormalized. */ \ | |
2213 | fg_flag = 1; \ | |
2214 | } \ | |
2215 | } \ | |
2216 | } \ | |
2217 | \ | |
2218 | env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \ | |
2219 | } | |
2220 | ||
bcb7652e TM |
2221 | VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52) |
2222 | VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52) | |
2223 | VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23) | |
595c6eef TM |
2224 | |
2225 | /* VSX_MADD - VSX floating point muliply/add variations | |
2226 | * op - instruction mnemonic | |
2227 | * nels - number of elements (1, 2 or 4) | |
2228 | * tp - type (float32 or float64) | |
bcb7652e | 2229 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
595c6eef TM |
2230 | * maddflgs - flags for the float*muladd routine that control the |
2231 | * various forms (madd, msub, nmadd, nmsub) | |
2232 | * afrm - A form (1=A, 0=M) | |
2233 | * sfprf - set FPRF | |
2234 | */ | |
f53f81e0 | 2235 | #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp) \ |
595c6eef TM |
2236 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ |
2237 | { \ | |
2238 | ppc_vsr_t xt_in, xa, xb, xt_out; \ | |
2239 | ppc_vsr_t *b, *c; \ | |
2240 | int i; \ | |
2241 | \ | |
2242 | if (afrm) { /* AxB + T */ \ | |
2243 | b = &xb; \ | |
2244 | c = &xt_in; \ | |
2245 | } else { /* AxT + B */ \ | |
2246 | b = &xt_in; \ | |
2247 | c = &xb; \ | |
2248 | } \ | |
2249 | \ | |
2250 | getVSR(xA(opcode), &xa, env); \ | |
2251 | getVSR(xB(opcode), &xb, env); \ | |
2252 | getVSR(xT(opcode), &xt_in, env); \ | |
2253 | \ | |
2254 | xt_out = xt_in; \ | |
2255 | \ | |
2256 | helper_reset_fpstatus(env); \ | |
2257 | \ | |
2258 | for (i = 0; i < nels; i++) { \ | |
2259 | float_status tstat = env->fp_status; \ | |
2260 | set_float_exception_flags(0, &tstat); \ | |
f53f81e0 TM |
2261 | if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\ |
2262 | /* Avoid double rounding errors by rounding the intermediate */ \ | |
2263 | /* result to odd. */ \ | |
2264 | set_float_rounding_mode(float_round_to_zero, &tstat); \ | |
bcb7652e | 2265 | xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld, \ |
f53f81e0 | 2266 | maddflgs, &tstat); \ |
bcb7652e | 2267 | xt_out.fld |= (get_float_exception_flags(&tstat) & \ |
f53f81e0 TM |
2268 | float_flag_inexact) != 0; \ |
2269 | } else { \ | |
bcb7652e | 2270 | xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld, \ |
f53f81e0 TM |
2271 | maddflgs, &tstat); \ |
2272 | } \ | |
595c6eef TM |
2273 | env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ |
2274 | \ | |
2275 | if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ | |
bcb7652e TM |
2276 | if (tp##_is_signaling_nan(xa.fld) || \ |
2277 | tp##_is_signaling_nan(b->fld) || \ | |
2278 | tp##_is_signaling_nan(c->fld)) { \ | |
595c6eef TM |
2279 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ |
2280 | tstat.float_exception_flags &= ~float_flag_invalid; \ | |
2281 | } \ | |
bcb7652e TM |
2282 | if ((tp##_is_infinity(xa.fld) && tp##_is_zero(b->fld)) || \ |
2283 | (tp##_is_zero(xa.fld) && tp##_is_infinity(b->fld))) { \ | |
2284 | xt_out.fld = float64_to_##tp(fload_invalid_op_excp(env, \ | |
595c6eef TM |
2285 | POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status); \ |
2286 | tstat.float_exception_flags &= ~float_flag_invalid; \ | |
2287 | } \ | |
2288 | if ((tstat.float_exception_flags & float_flag_invalid) && \ | |
bcb7652e TM |
2289 | ((tp##_is_infinity(xa.fld) || \ |
2290 | tp##_is_infinity(b->fld)) && \ | |
2291 | tp##_is_infinity(c->fld))) { \ | |
595c6eef TM |
2292 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \ |
2293 | } \ | |
2294 | } \ | |
f53f81e0 TM |
2295 | \ |
2296 | if (r2sp) { \ | |
bcb7652e | 2297 | xt_out.fld = helper_frsp(env, xt_out.fld); \ |
f53f81e0 TM |
2298 | } \ |
2299 | \ | |
595c6eef | 2300 | if (sfprf) { \ |
58dd0a47 | 2301 | helper_compute_fprf(env, xt_out.fld); \ |
595c6eef TM |
2302 | } \ |
2303 | } \ | |
2304 | putVSR(xT(opcode), &xt_out, env); \ | |
2305 | helper_float_check_status(env); \ | |
2306 | } | |
2307 | ||
2308 | #define MADD_FLGS 0 | |
2309 | #define MSUB_FLGS float_muladd_negate_c | |
2310 | #define NMADD_FLGS float_muladd_negate_result | |
2311 | #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result) | |
2312 | ||
bcb7652e TM |
2313 | VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0) |
2314 | VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0) | |
2315 | VSX_MADD(xsmsubadp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 0) | |
2316 | VSX_MADD(xsmsubmdp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 0) | |
2317 | VSX_MADD(xsnmaddadp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 0) | |
2318 | VSX_MADD(xsnmaddmdp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 0) | |
2319 | VSX_MADD(xsnmsubadp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 0) | |
2320 | VSX_MADD(xsnmsubmdp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 0) | |
2321 | ||
2322 | VSX_MADD(xsmaddasp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 1) | |
2323 | VSX_MADD(xsmaddmsp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 1) | |
2324 | VSX_MADD(xsmsubasp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 1) | |
2325 | VSX_MADD(xsmsubmsp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 1) | |
2326 | VSX_MADD(xsnmaddasp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 1) | |
2327 | VSX_MADD(xsnmaddmsp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 1) | |
2328 | VSX_MADD(xsnmsubasp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 1) | |
2329 | VSX_MADD(xsnmsubmsp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 1) | |
2330 | ||
2331 | VSX_MADD(xvmaddadp, 2, float64, VsrD(i), MADD_FLGS, 1, 0, 0) | |
2332 | VSX_MADD(xvmaddmdp, 2, float64, VsrD(i), MADD_FLGS, 0, 0, 0) | |
2333 | VSX_MADD(xvmsubadp, 2, float64, VsrD(i), MSUB_FLGS, 1, 0, 0) | |
2334 | VSX_MADD(xvmsubmdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0, 0) | |
2335 | VSX_MADD(xvnmaddadp, 2, float64, VsrD(i), NMADD_FLGS, 1, 0, 0) | |
2336 | VSX_MADD(xvnmaddmdp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0, 0) | |
2337 | VSX_MADD(xvnmsubadp, 2, float64, VsrD(i), NMSUB_FLGS, 1, 0, 0) | |
2338 | VSX_MADD(xvnmsubmdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0, 0) | |
2339 | ||
2340 | VSX_MADD(xvmaddasp, 4, float32, VsrW(i), MADD_FLGS, 1, 0, 0) | |
2341 | VSX_MADD(xvmaddmsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0, 0) | |
2342 | VSX_MADD(xvmsubasp, 4, float32, VsrW(i), MSUB_FLGS, 1, 0, 0) | |
2343 | VSX_MADD(xvmsubmsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0, 0) | |
2344 | VSX_MADD(xvnmaddasp, 4, float32, VsrW(i), NMADD_FLGS, 1, 0, 0) | |
2345 | VSX_MADD(xvnmaddmsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0, 0) | |
2346 | VSX_MADD(xvnmsubasp, 4, float32, VsrW(i), NMSUB_FLGS, 1, 0, 0) | |
2347 | VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0, 0) | |
4f17e9c7 TM |
2348 | |
2349 | #define VSX_SCALAR_CMP(op, ordered) \ | |
2350 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ | |
2351 | { \ | |
2352 | ppc_vsr_t xa, xb; \ | |
2353 | uint32_t cc = 0; \ | |
2354 | \ | |
2355 | getVSR(xA(opcode), &xa, env); \ | |
2356 | getVSR(xB(opcode), &xb, env); \ | |
2357 | \ | |
50fc89e7 TM |
2358 | if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \ |
2359 | float64_is_any_nan(xb.VsrD(0)))) { \ | |
2360 | if (float64_is_signaling_nan(xa.VsrD(0)) || \ | |
2361 | float64_is_signaling_nan(xb.VsrD(0))) { \ | |
4f17e9c7 TM |
2362 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ |
2363 | } \ | |
2364 | if (ordered) { \ | |
2365 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ | |
2366 | } \ | |
2367 | cc = 1; \ | |
2368 | } else { \ | |
50fc89e7 | 2369 | if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \ |
4f17e9c7 | 2370 | cc = 8; \ |
50fc89e7 TM |
2371 | } else if (!float64_le(xa.VsrD(0), xb.VsrD(0), \ |
2372 | &env->fp_status)) { \ | |
4f17e9c7 TM |
2373 | cc = 4; \ |
2374 | } else { \ | |
2375 | cc = 2; \ | |
2376 | } \ | |
2377 | } \ | |
2378 | \ | |
2379 | env->fpscr &= ~(0x0F << FPSCR_FPRF); \ | |
2380 | env->fpscr |= cc << FPSCR_FPRF; \ | |
2381 | env->crf[BF(opcode)] = cc; \ | |
2382 | \ | |
2383 | helper_float_check_status(env); \ | |
2384 | } | |
2385 | ||
2386 | VSX_SCALAR_CMP(xscmpodp, 1) | |
2387 | VSX_SCALAR_CMP(xscmpudp, 0) | |
959e9c9d | 2388 | |
959e9c9d TM |
2389 | /* VSX_MAX_MIN - VSX floating point maximum/minimum |
2390 | * name - instruction mnemonic | |
2391 | * op - operation (max or min) | |
2392 | * nels - number of elements (1, 2 or 4) | |
2393 | * tp - type (float32 or float64) | |
bcb7652e | 2394 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
959e9c9d TM |
2395 | */ |
2396 | #define VSX_MAX_MIN(name, op, nels, tp, fld) \ | |
2397 | void helper_##name(CPUPPCState *env, uint32_t opcode) \ | |
2398 | { \ | |
2399 | ppc_vsr_t xt, xa, xb; \ | |
2400 | int i; \ | |
2401 | \ | |
2402 | getVSR(xA(opcode), &xa, env); \ | |
2403 | getVSR(xB(opcode), &xb, env); \ | |
2404 | getVSR(xT(opcode), &xt, env); \ | |
2405 | \ | |
2406 | for (i = 0; i < nels; i++) { \ | |
bcb7652e TM |
2407 | xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status); \ |
2408 | if (unlikely(tp##_is_signaling_nan(xa.fld) || \ | |
2409 | tp##_is_signaling_nan(xb.fld))) { \ | |
959e9c9d TM |
2410 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ |
2411 | } \ | |
2412 | } \ | |
2413 | \ | |
2414 | putVSR(xT(opcode), &xt, env); \ | |
2415 | helper_float_check_status(env); \ | |
2416 | } | |
2417 | ||
bcb7652e TM |
2418 | VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0)) |
2419 | VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i)) | |
2420 | VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i)) | |
2421 | VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0)) | |
2422 | VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i)) | |
2423 | VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i)) | |
354a6dec TM |
2424 | |
2425 | /* VSX_CMP - VSX floating point compare | |
2426 | * op - instruction mnemonic | |
2427 | * nels - number of elements (1, 2 or 4) | |
2428 | * tp - type (float32 or float64) | |
bcb7652e | 2429 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
354a6dec TM |
2430 | * cmp - comparison operation |
2431 | * svxvc - set VXVC bit | |
2432 | */ | |
2433 | #define VSX_CMP(op, nels, tp, fld, cmp, svxvc) \ | |
2434 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ | |
2435 | { \ | |
2436 | ppc_vsr_t xt, xa, xb; \ | |
2437 | int i; \ | |
2438 | int all_true = 1; \ | |
2439 | int all_false = 1; \ | |
2440 | \ | |
2441 | getVSR(xA(opcode), &xa, env); \ | |
2442 | getVSR(xB(opcode), &xb, env); \ | |
2443 | getVSR(xT(opcode), &xt, env); \ | |
2444 | \ | |
2445 | for (i = 0; i < nels; i++) { \ | |
bcb7652e TM |
2446 | if (unlikely(tp##_is_any_nan(xa.fld) || \ |
2447 | tp##_is_any_nan(xb.fld))) { \ | |
2448 | if (tp##_is_signaling_nan(xa.fld) || \ | |
2449 | tp##_is_signaling_nan(xb.fld)) { \ | |
354a6dec TM |
2450 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ |
2451 | } \ | |
2452 | if (svxvc) { \ | |
2453 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ | |
2454 | } \ | |
bcb7652e | 2455 | xt.fld = 0; \ |
354a6dec TM |
2456 | all_true = 0; \ |
2457 | } else { \ | |
bcb7652e TM |
2458 | if (tp##_##cmp(xb.fld, xa.fld, &env->fp_status) == 1) { \ |
2459 | xt.fld = -1; \ | |
354a6dec TM |
2460 | all_false = 0; \ |
2461 | } else { \ | |
bcb7652e | 2462 | xt.fld = 0; \ |
354a6dec TM |
2463 | all_true = 0; \ |
2464 | } \ | |
2465 | } \ | |
2466 | } \ | |
2467 | \ | |
2468 | putVSR(xT(opcode), &xt, env); \ | |
2469 | if ((opcode >> (31-21)) & 1) { \ | |
2470 | env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \ | |
2471 | } \ | |
2472 | helper_float_check_status(env); \ | |
2473 | } | |
2474 | ||
bcb7652e TM |
2475 | VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0) |
2476 | VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1) | |
2477 | VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1) | |
2478 | VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0) | |
2479 | VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1) | |
2480 | VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1) | |
ed8ac568 | 2481 | |
ed8ac568 TM |
2482 | /* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion |
2483 | * op - instruction mnemonic | |
2484 | * nels - number of elements (1, 2 or 4) | |
2485 | * stp - source type (float32 or float64) | |
2486 | * ttp - target type (float32 or float64) | |
2487 | * sfld - source vsr_t field | |
2488 | * tfld - target vsr_t field (f32 or f64) | |
2489 | * sfprf - set FPRF | |
2490 | */ | |
2491 | #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \ | |
2492 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ | |
2493 | { \ | |
2494 | ppc_vsr_t xt, xb; \ | |
2495 | int i; \ | |
2496 | \ | |
2497 | getVSR(xB(opcode), &xb, env); \ | |
2498 | getVSR(xT(opcode), &xt, env); \ | |
2499 | \ | |
2500 | for (i = 0; i < nels; i++) { \ | |
ed8ac568 TM |
2501 | xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \ |
2502 | if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \ | |
2503 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ | |
2504 | xt.tfld = ttp##_snan_to_qnan(xt.tfld); \ | |
2505 | } \ | |
2506 | if (sfprf) { \ | |
2507 | helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \ | |
58dd0a47 | 2508 | &env->fp_status)); \ |
ed8ac568 TM |
2509 | } \ |
2510 | } \ | |
2511 | \ | |
2512 | putVSR(xT(opcode), &xt, env); \ | |
2513 | helper_float_check_status(env); \ | |
2514 | } | |
2515 | ||
6bbad7a9 TM |
2516 | VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1) |
2517 | VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1) | |
2518 | VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0) | |
2519 | VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0) | |
5177d2ca | 2520 | |
7ee19fb9 TM |
2521 | uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb) |
2522 | { | |
2523 | float_status tstat = env->fp_status; | |
2524 | set_float_exception_flags(0, &tstat); | |
2525 | ||
2526 | return (uint64_t)float64_to_float32(xb, &tstat) << 32; | |
2527 | } | |
2528 | ||
2529 | uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb) | |
2530 | { | |
2531 | float_status tstat = env->fp_status; | |
2532 | set_float_exception_flags(0, &tstat); | |
2533 | ||
2534 | return float32_to_float64(xb >> 32, &tstat); | |
2535 | } | |
2536 | ||
5177d2ca TM |
2537 | /* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion |
2538 | * op - instruction mnemonic | |
2539 | * nels - number of elements (1, 2 or 4) | |
2540 | * stp - source type (float32 or float64) | |
2541 | * ttp - target type (int32, uint32, int64 or uint64) | |
2542 | * sfld - source vsr_t field | |
2543 | * tfld - target vsr_t field | |
5177d2ca TM |
2544 | * rnan - resulting NaN |
2545 | */ | |
d1dec5ef | 2546 | #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \ |
5177d2ca TM |
2547 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ |
2548 | { \ | |
2549 | ppc_vsr_t xt, xb; \ | |
2550 | int i; \ | |
2551 | \ | |
2552 | getVSR(xB(opcode), &xb, env); \ | |
2553 | getVSR(xT(opcode), &xt, env); \ | |
2554 | \ | |
2555 | for (i = 0; i < nels; i++) { \ | |
5177d2ca TM |
2556 | if (unlikely(stp##_is_any_nan(xb.sfld))) { \ |
2557 | if (stp##_is_signaling_nan(xb.sfld)) { \ | |
2558 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ | |
2559 | } \ | |
2560 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \ | |
2561 | xt.tfld = rnan; \ | |
2562 | } else { \ | |
0453099b TM |
2563 | xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \ |
2564 | &env->fp_status); \ | |
5177d2ca TM |
2565 | if (env->fp_status.float_exception_flags & float_flag_invalid) { \ |
2566 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \ | |
2567 | } \ | |
2568 | } \ | |
2569 | } \ | |
2570 | \ | |
2571 | putVSR(xT(opcode), &xt, env); \ | |
2572 | helper_float_check_status(env); \ | |
2573 | } | |
2574 | ||
d1dec5ef | 2575 | VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \ |
7dff9abe | 2576 | 0x8000000000000000ULL) |
d1dec5ef TM |
2577 | VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \ |
2578 | 0x80000000U) | |
2579 | VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL) | |
2580 | VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U) | |
2581 | VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \ | |
7dff9abe | 2582 | 0x8000000000000000ULL) |
d1dec5ef | 2583 | VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2*i), \ |
7dff9abe | 2584 | 0x80000000U) |
d1dec5ef TM |
2585 | VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL) |
2586 | VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2*i), 0U) | |
2587 | VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2*i), VsrD(i), \ | |
2588 | 0x8000000000000000ULL) | |
2589 | VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U) | |
2590 | VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2*i), VsrD(i), 0ULL) | |
2591 | VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U) | |
5177d2ca TM |
2592 | |
2593 | /* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion | |
2594 | * op - instruction mnemonic | |
2595 | * nels - number of elements (1, 2 or 4) | |
2596 | * stp - source type (int32, uint32, int64 or uint64) | |
2597 | * ttp - target type (float32 or float64) | |
2598 | * sfld - source vsr_t field | |
2599 | * tfld - target vsr_t field | |
2600 | * jdef - definition of the j index (i or 2*i) | |
2601 | * sfprf - set FPRF | |
2602 | */ | |
6cd7db3d | 2603 | #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \ |
5177d2ca TM |
2604 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ |
2605 | { \ | |
2606 | ppc_vsr_t xt, xb; \ | |
2607 | int i; \ | |
2608 | \ | |
2609 | getVSR(xB(opcode), &xb, env); \ | |
2610 | getVSR(xT(opcode), &xt, env); \ | |
2611 | \ | |
2612 | for (i = 0; i < nels; i++) { \ | |
5177d2ca | 2613 | xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \ |
74698350 TM |
2614 | if (r2sp) { \ |
2615 | xt.tfld = helper_frsp(env, xt.tfld); \ | |
2616 | } \ | |
5177d2ca | 2617 | if (sfprf) { \ |
58dd0a47 | 2618 | helper_compute_fprf(env, xt.tfld); \ |
5177d2ca TM |
2619 | } \ |
2620 | } \ | |
2621 | \ | |
2622 | putVSR(xT(opcode), &xt, env); \ | |
2623 | helper_float_check_status(env); \ | |
2624 | } | |
2625 | ||
6cd7db3d TM |
2626 | VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0) |
2627 | VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0) | |
2628 | VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1) | |
2629 | VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1) | |
2630 | VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0) | |
2631 | VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0) | |
2632 | VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2*i), VsrD(i), 0, 0) | |
2633 | VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2*i), VsrD(i), 0, 0) | |
2634 | VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2*i), 0, 0) | |
2635 | VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2*i), 0, 0) | |
2636 | VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0) | |
2637 | VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0) | |
88e33d08 TM |
2638 | |
2639 | /* For "use current rounding mode", define a value that will not be one of | |
2640 | * the existing rounding model enums. | |
2641 | */ | |
2642 | #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \ | |
2643 | float_round_up + float_round_to_zero) | |
2644 | ||
2645 | /* VSX_ROUND - VSX floating point round | |
2646 | * op - instruction mnemonic | |
2647 | * nels - number of elements (1, 2 or 4) | |
2648 | * tp - type (float32 or float64) | |
bcb7652e | 2649 | * fld - vsr_t field (VsrD(*) or VsrW(*)) |
88e33d08 TM |
2650 | * rmode - rounding mode |
2651 | * sfprf - set FPRF | |
2652 | */ | |
2653 | #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \ | |
2654 | void helper_##op(CPUPPCState *env, uint32_t opcode) \ | |
2655 | { \ | |
2656 | ppc_vsr_t xt, xb; \ | |
2657 | int i; \ | |
2658 | getVSR(xB(opcode), &xb, env); \ | |
2659 | getVSR(xT(opcode), &xt, env); \ | |
2660 | \ | |
2661 | if (rmode != FLOAT_ROUND_CURRENT) { \ | |
2662 | set_float_rounding_mode(rmode, &env->fp_status); \ | |
2663 | } \ | |
2664 | \ | |
2665 | for (i = 0; i < nels; i++) { \ | |
bcb7652e | 2666 | if (unlikely(tp##_is_signaling_nan(xb.fld))) { \ |
88e33d08 | 2667 | fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ |
bcb7652e | 2668 | xt.fld = tp##_snan_to_qnan(xb.fld); \ |
88e33d08 | 2669 | } else { \ |
bcb7652e | 2670 | xt.fld = tp##_round_to_int(xb.fld, &env->fp_status); \ |
88e33d08 TM |
2671 | } \ |
2672 | if (sfprf) { \ | |
58dd0a47 | 2673 | helper_compute_fprf(env, xt.fld); \ |
88e33d08 TM |
2674 | } \ |
2675 | } \ | |
2676 | \ | |
2677 | /* If this is not a "use current rounding mode" instruction, \ | |
2678 | * then inhibit setting of the XX bit and restore rounding \ | |
2679 | * mode from FPSCR */ \ | |
2680 | if (rmode != FLOAT_ROUND_CURRENT) { \ | |
2681 | fpscr_set_rounding_mode(env); \ | |
2682 | env->fp_status.float_exception_flags &= ~float_flag_inexact; \ | |
2683 | } \ | |
2684 | \ | |
2685 | putVSR(xT(opcode), &xt, env); \ | |
2686 | helper_float_check_status(env); \ | |
2687 | } | |
2688 | ||
bcb7652e TM |
2689 | VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_nearest_even, 1) |
2690 | VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1) | |
2691 | VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1) | |
2692 | VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1) | |
2693 | VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1) | |
88e33d08 | 2694 | |
bcb7652e TM |
2695 | VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_nearest_even, 0) |
2696 | VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0) | |
2697 | VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0) | |
2698 | VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0) | |
2699 | VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0) | |
88e33d08 | 2700 | |
bcb7652e TM |
2701 | VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_nearest_even, 0) |
2702 | VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0) | |
2703 | VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0) | |
2704 | VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0) | |
2705 | VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0) | |
3d1140bf TM |
2706 | |
2707 | uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) | |
2708 | { | |
2709 | helper_reset_fpstatus(env); | |
2710 | ||
2711 | uint64_t xt = helper_frsp(env, xb); | |
2712 | ||
58dd0a47 | 2713 | helper_compute_fprf(env, xt); |
3d1140bf TM |
2714 | helper_float_check_status(env); |
2715 | return xt; | |
2716 | } |