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[qemu.git] / target-ppc / helper.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
fdabc366
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
27
28#include "cpu.h"
29#include "exec-all.h"
9a64fbe4
FB		 30
31//#define DEBUG_MMU
32//#define DEBUG_BATS
76a66253 33//#define DEBUG_SOFTWARE_TLB
9a64fbe4 34//#define DEBUG_EXCEPTIONS
fdabc366 35//#define FLUSH_ALL_TLBS
9a64fbe4 36
9a64fbe4 37/*****************************************************************************/
3fc6c082 38/* PowerPC MMU emulation */
a541f297 39
d9bce9d9 40#if defined(CONFIG_USER_ONLY)
e96efcfc 41int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
24741ef3
FB		 42 int is_user, int is_softmmu)
43{
44 int exception, error_code;
d9bce9d9 45
24741ef3 46 if (rw == 2) {
e1833e1f 47 exception = POWERPC_EXCP_ISI;
8f793433 48 error_code = 0x40000000;
24741ef3 49 } else {
e1833e1f 50 exception = POWERPC_EXCP_DSI;
8f793433 51 error_code = 0x40000000;
24741ef3
FB		 52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
76a66253 59
24741ef3
FB		 60 return 1;
61}
76a66253 62
9b3c35e0 63target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
24741ef3
FB		 64{
65 return addr;
66}
36081602 67
24741ef3 68#else
76a66253
JM		 69/* Common routines used by software and hardware TLBs emulation */
70static inline int pte_is_valid (target_ulong pte0)
71{
72 return pte0 & 0x80000000 ? 1 : 0;
73}
74
75static inline void pte_invalidate (target_ulong *pte0)
76{
77 *pte0 &= ~0x80000000;
78}
79
caa4039c
JM		 80#if defined(TARGET_PPC64)
81static inline int pte64_is_valid (target_ulong pte0)
82{
83 return pte0 & 0x0000000000000001ULL ? 1 : 0;
84}
85
86static inline void pte64_invalidate (target_ulong *pte0)
87{
88 *pte0 &= ~0x0000000000000001ULL;
89}
90#endif
91
76a66253
JM		 92#define PTE_PTEM_MASK 0x7FFFFFBF
93#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
caa4039c
JM		 94#if defined(TARGET_PPC64)
95#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
96#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
97#endif
76a66253 98
caa4039c
JM		 99static inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
100 target_ulong pte0, target_ulong pte1,
101 int h, int rw)
76a66253 102{
caa4039c
JM		 103 target_ulong ptem, mmask;
104 int access, ret, pteh, ptev;
76a66253
JM		 105
106 access = 0;
107 ret = -1;
108 /* Check validity and table match */
caa4039c
JM		 109#if defined(TARGET_PPC64)
110 if (is_64b) {
111 ptev = pte64_is_valid(pte0);
112 pteh = (pte0 >> 1) & 1;
113 } else
114#endif
115 {
116 ptev = pte_is_valid(pte0);
117 pteh = (pte0 >> 6) & 1;
118 }
119 if (ptev && h == pteh) {
76a66253 120 /* Check vsid & api */
caa4039c
JM		 121#if defined(TARGET_PPC64)
122 if (is_64b) {
123 ptem = pte0 & PTE64_PTEM_MASK;
124 mmask = PTE64_CHECK_MASK;
125 } else
126#endif
127 {
128 ptem = pte0 & PTE_PTEM_MASK;
129 mmask = PTE_CHECK_MASK;
130 }
131 if (ptem == ctx->ptem) {
76a66253
JM		 132 if (ctx->raddr != (target_ulong)-1) {
133 /* all matches should have equal RPN, WIMG & PP */
caa4039c
JM		 134 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
135 if (loglevel != 0)
76a66253
JM		 136 fprintf(logfile, "Bad RPN/WIMG/PP\n");
137 return -3;
138 }
139 }
140 /* Compute access rights */
141 if (ctx->key == 0) {
142 access = PAGE_READ;
143 if ((pte1 & 0x00000003) != 0x3)
144 access |= PAGE_WRITE;
145 } else {
146 switch (pte1 & 0x00000003) {
147 case 0x0:
148 access = 0;
149 break;
150 case 0x1:
151 case 0x3:
152 access = PAGE_READ;
153 break;
154 case 0x2:
155 access = PAGE_READ | PAGE_WRITE;
156 break;
157 }
158 }
159 /* Keep the matching PTE informations */
160 ctx->raddr = pte1;
161 ctx->prot = access;
162 if ((rw == 0 && (access & PAGE_READ)) ||
163 (rw == 1 && (access & PAGE_WRITE))) {
164 /* Access granted */
165#if defined (DEBUG_MMU)
4a057712 166 if (loglevel != 0)
76a66253
JM		 167 fprintf(logfile, "PTE access granted !\n");
168#endif
169 ret = 0;
170 } else {
171 /* Access right violation */
172#if defined (DEBUG_MMU)
4a057712 173 if (loglevel != 0)
76a66253
JM		 174 fprintf(logfile, "PTE access rejected\n");
175#endif
176 ret = -2;
177 }
178 }
179 }
180
181 return ret;
182}
183
caa4039c
JM		 184static int pte32_check (mmu_ctx_t *ctx,
185 target_ulong pte0, target_ulong pte1, int h, int rw)
186{
187 return _pte_check(ctx, 0, pte0, pte1, h, rw);
188}
189
190#if defined(TARGET_PPC64)
191static int pte64_check (mmu_ctx_t *ctx,
192 target_ulong pte0, target_ulong pte1, int h, int rw)
193{
194 return _pte_check(ctx, 1, pte0, pte1, h, rw);
195}
196#endif
197
76a66253
JM		 198static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
199 int ret, int rw)
200{
201 int store = 0;
202
203 /* Update page flags */
204 if (!(*pte1p & 0x00000100)) {
205 /* Update accessed flag */
206 *pte1p |= 0x00000100;
207 store = 1;
208 }
209 if (!(*pte1p & 0x00000080)) {
210 if (rw == 1 && ret == 0) {
211 /* Update changed flag */
212 *pte1p |= 0x00000080;
213 store = 1;
214 } else {
215 /* Force page fault for first write access */
216 ctx->prot &= ~PAGE_WRITE;
217 }
218 }
219
220 return store;
221}
222
223/* Software driven TLB helpers */
224static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
225 int way, int is_code)
226{
227 int nr;
228
229 /* Select TLB num in a way from address */
230 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
231 /* Select TLB way */
232 nr += env->tlb_per_way * way;
233 /* 6xx have separate TLBs for instructions and data */
234 if (is_code && env->id_tlbs == 1)
235 nr += env->nb_tlb;
236
237 return nr;
238}
239
daf4f96e 240static void ppc6xx_tlb_invalidate_all (CPUState *env)
76a66253 241{
1d0a48fb 242 ppc6xx_tlb_t *tlb;
76a66253
JM		 243 int nr, max;
244
245#if defined (DEBUG_SOFTWARE_TLB) && 0
246 if (loglevel != 0) {
247 fprintf(logfile, "Invalidate all TLBs\n");
248 }
249#endif
250 /* Invalidate all defined software TLB */
251 max = env->nb_tlb;
252 if (env->id_tlbs == 1)
253 max *= 2;
254 for (nr = 0; nr < max; nr++) {
1d0a48fb 255 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 256 pte_invalidate(&tlb->pte0);
257 }
76a66253 258 tlb_flush(env, 1);
76a66253
JM		 259}
260
261static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
262 target_ulong eaddr,
263 int is_code, int match_epn)
264{
4a057712 265#if !defined(FLUSH_ALL_TLBS)
1d0a48fb 266 ppc6xx_tlb_t *tlb;
76a66253
JM		 267 int way, nr;
268
76a66253
JM		 269 /* Invalidate ITLB + DTLB, all ways */
270 for (way = 0; way < env->nb_ways; way++) {
271 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
1d0a48fb 272 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 273 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
274#if defined (DEBUG_SOFTWARE_TLB)
275 if (loglevel != 0) {
1b9eb036 276 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
76a66253
JM		 277 nr, env->nb_tlb, eaddr);
278 }
279#endif
280 pte_invalidate(&tlb->pte0);
281 tlb_flush_page(env, tlb->EPN);
282 }
283 }
284#else
285 /* XXX: PowerPC specification say this is valid as well */
286 ppc6xx_tlb_invalidate_all(env);
287#endif
288}
289
daf4f96e
JM		 290static void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
291 int is_code)
76a66253
JM		 292{
293 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
294}
295
296void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
297 target_ulong pte0, target_ulong pte1)
298{
1d0a48fb 299 ppc6xx_tlb_t *tlb;
76a66253
JM		 300 int nr;
301
302 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
1d0a48fb 303 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 304#if defined (DEBUG_SOFTWARE_TLB)
305 if (loglevel != 0) {
5fafdf24 306 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
1b9eb036 307 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
76a66253
JM		 308 }
309#endif
310 /* Invalidate any pending reference in Qemu for this virtual address */
311 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
312 tlb->pte0 = pte0;
313 tlb->pte1 = pte1;
314 tlb->EPN = EPN;
76a66253
JM		 315 /* Store last way for LRU mechanism */
316 env->last_way = way;
317}
318
319static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
320 target_ulong eaddr, int rw, int access_type)
321{
1d0a48fb 322 ppc6xx_tlb_t *tlb;
76a66253
JM		 323 int nr, best, way;
324 int ret;
d9bce9d9 325
76a66253
JM		 326 best = -1;
327 ret = -1; /* No TLB found */
328 for (way = 0; way < env->nb_ways; way++) {
329 nr = ppc6xx_tlb_getnum(env, eaddr, way,
330 access_type == ACCESS_CODE ? 1 : 0);
1d0a48fb 331 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 332 /* This test "emulates" the PTE index match for hardware TLBs */
333 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
334#if defined (DEBUG_SOFTWARE_TLB)
335 if (loglevel != 0) {
1b9eb036
JM		 336 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
337 "] <> " ADDRX "\n",
76a66253
JM		 338 nr, env->nb_tlb,
339 pte_is_valid(tlb->pte0) ? "valid" : "inval",
340 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
341 }
342#endif
343 continue;
344 }
345#if defined (DEBUG_SOFTWARE_TLB)
346 if (loglevel != 0) {
1b9eb036
JM		 347 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
348 " %c %c\n",
76a66253
JM		 349 nr, env->nb_tlb,
350 pte_is_valid(tlb->pte0) ? "valid" : "inval",
351 tlb->EPN, eaddr, tlb->pte1,
352 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
353 }
354#endif
caa4039c 355 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
76a66253
JM		 356 case -3:
357 /* TLB inconsistency */
358 return -1;
359 case -2:
360 /* Access violation */
361 ret = -2;
362 best = nr;
363 break;
364 case -1:
365 default:
366 /* No match */
367 break;
368 case 0:
369 /* access granted */
370 /* XXX: we should go on looping to check all TLBs consistency
371 * but we can speed-up the whole thing as the
372 * result would be undefined if TLBs are not consistent.
373 */
374 ret = 0;
375 best = nr;
376 goto done;
377 }
378 }
379 if (best != -1) {
380 done:
381#if defined (DEBUG_SOFTWARE_TLB)
4a057712 382 if (loglevel != 0) {
76a66253
JM		 383 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
384 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
385 }
386#endif
387 /* Update page flags */
1d0a48fb 388 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
76a66253
JM		 389 }
390
391 return ret;
392}
393
9a64fbe4 394/* Perform BAT hit & translation */
76a66253
JM		 395static int get_bat (CPUState *env, mmu_ctx_t *ctx,
396 target_ulong virtual, int rw, int type)
9a64fbe4 397{
76a66253
JM		 398 target_ulong *BATlt, *BATut, *BATu, *BATl;
399 target_ulong base, BEPIl, BEPIu, bl;
9a64fbe4
FB		 400 int i;
401 int ret = -1;
402
403#if defined (DEBUG_BATS)
4a057712 404 if (loglevel != 0) {
1b9eb036 405 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 406 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 407 }
9a64fbe4
FB		 408#endif
409 switch (type) {
410 case ACCESS_CODE:
411 BATlt = env->IBAT[1];
412 BATut = env->IBAT[0];
413 break;
414 default:
415 BATlt = env->DBAT[1];
416 BATut = env->DBAT[0];
417 break;
418 }
419#if defined (DEBUG_BATS)
4a057712 420 if (loglevel != 0) {
1b9eb036 421 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 422 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 423 }
9a64fbe4
FB		 424#endif
425 base = virtual & 0xFFFC0000;
426 for (i = 0; i < 4; i++) {
427 BATu = &BATut[i];
428 BATl = &BATlt[i];
429 BEPIu = *BATu & 0xF0000000;
430 BEPIl = *BATu & 0x0FFE0000;
431 bl = (*BATu & 0x00001FFC) << 15;
432#if defined (DEBUG_BATS)
4a057712 433 if (loglevel != 0) {
5fafdf24 434 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
1b9eb036 435 " BATl 0x" ADDRX "\n",
9a64fbe4
FB		 436 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
437 *BATu, *BATl);
9a64fbe4
FB		 438 }
439#endif
440 if ((virtual & 0xF0000000) == BEPIu &&
441 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
442 /* BAT matches */
443 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
444 (msr_pr == 1 && (*BATu & 0x00000001))) {
445 /* Get physical address */
76a66253 446 ctx->raddr = (*BATl & 0xF0000000) |
9a64fbe4 447 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
a541f297 448 (virtual & 0x0001F000);
9a64fbe4 449 if (*BATl & 0x00000001)
76a66253 450 ctx->prot = PAGE_READ;
9a64fbe4 451 if (*BATl & 0x00000002)
76a66253 452 ctx->prot = PAGE_WRITE | PAGE_READ;
9a64fbe4 453#if defined (DEBUG_BATS)
4a057712
JM		 454 if (loglevel != 0) {
455 fprintf(logfile, "BAT %d match: r 0x" PADDRX
1b9eb036 456 " prot=%c%c\n",
76a66253
JM		 457 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
458 ctx->prot & PAGE_WRITE ? 'W' : '-');
9a64fbe4
FB		 459 }
460#endif
461 ret = 0;
462 break;
463 }
464 }
465 }
466 if (ret < 0) {
467#if defined (DEBUG_BATS)
4a057712
JM		 468 if (loglevel != 0) {
469 fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
470 for (i = 0; i < 4; i++) {
471 BATu = &BATut[i];
472 BATl = &BATlt[i];
473 BEPIu = *BATu & 0xF0000000;
474 BEPIl = *BATu & 0x0FFE0000;
475 bl = (*BATu & 0x00001FFC) << 15;
476 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
477 " BATl 0x" ADDRX " \n\t"
478 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
479 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
480 *BATu, *BATl, BEPIu, BEPIl, bl);
481 }
9a64fbe4
FB		 482 }
483#endif
9a64fbe4
FB		 484 }
485 /* No hit */
486 return ret;
487}
488
489/* PTE table lookup */
caa4039c 490static inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
9a64fbe4 491{
76a66253
JM		 492 target_ulong base, pte0, pte1;
493 int i, good = -1;
caa4039c 494 int ret, r;
9a64fbe4 495
76a66253
JM		 496 ret = -1; /* No entry found */
497 base = ctx->pg_addr[h];
9a64fbe4 498 for (i = 0; i < 8; i++) {
caa4039c
JM		 499#if defined(TARGET_PPC64)
500 if (is_64b) {
501 pte0 = ldq_phys(base + (i * 16));
502 pte1 = ldq_phys(base + (i * 16) + 8);
503 r = pte64_check(ctx, pte0, pte1, h, rw);
504 } else
505#endif
506 {
507 pte0 = ldl_phys(base + (i * 8));
508 pte1 = ldl_phys(base + (i * 8) + 4);
509 r = pte32_check(ctx, pte0, pte1, h, rw);
510 }
9a64fbe4 511#if defined (DEBUG_MMU)
caa4039c 512 if (loglevel != 0) {
5fafdf24 513 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
1b9eb036
JM		 514 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
515 base + (i * 8), pte0, pte1,
caa4039c 516 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem);
76a66253 517 }
9a64fbe4 518#endif
caa4039c 519 switch (r) {
76a66253
JM		 520 case -3:
521 /* PTE inconsistency */
522 return -1;
523 case -2:
524 /* Access violation */
525 ret = -2;
526 good = i;
527 break;
528 case -1:
529 default:
530 /* No PTE match */
531 break;
532 case 0:
533 /* access granted */
534 /* XXX: we should go on looping to check all PTEs consistency
535 * but if we can speed-up the whole thing as the
536 * result would be undefined if PTEs are not consistent.
537 */
538 ret = 0;
539 good = i;
540 goto done;
9a64fbe4
FB		 541 }
542 }
543 if (good != -1) {
76a66253 544 done:
9a64fbe4 545#if defined (DEBUG_MMU)
4a057712
JM		 546 if (loglevel != 0) {
547 fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
1b9eb036 548 "ret=%d\n",
76a66253
JM		 549 ctx->raddr, ctx->prot, ret);
550 }
9a64fbe4
FB		 551#endif
552 /* Update page flags */
76a66253 553 pte1 = ctx->raddr;
caa4039c
JM		 554 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
555#if defined(TARGET_PPC64)
556 if (is_64b) {
557 stq_phys_notdirty(base + (good * 16) + 8, pte1);
558 } else
559#endif
560 {
561 stl_phys_notdirty(base + (good * 8) + 4, pte1);
562 }
563 }
9a64fbe4
FB		 564 }
565
566 return ret;
79aceca5
FB		 567}
568
caa4039c
JM		 569static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
570{
571 return _find_pte(ctx, 0, h, rw);
572}
573
574#if defined(TARGET_PPC64)
575static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
576{
577 return _find_pte(ctx, 1, h, rw);
578}
579#endif
580
581static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw)
582{
583#if defined(TARGET_PPC64)
a750fc0b
JM		 584 if (env->mmu_model == POWERPC_MMU_64B ||
585 env->mmu_model == POWERPC_MMU_64BRIDGE)
caa4039c
JM		 586 return find_pte64(ctx, h, rw);
587#endif
588
589 return find_pte32(ctx, h, rw);
590}
591
76a66253 592static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
caa4039c 593 int sdr_sh,
76a66253
JM		 594 target_phys_addr_t hash,
595 target_phys_addr_t mask)
79aceca5 596{
caa4039c
JM		 597 return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
598}
599
600#if defined(TARGET_PPC64)
601static int slb_lookup (CPUState *env, target_ulong eaddr,
602 target_ulong *vsid, target_ulong *page_mask, int *attr)
603{
604 target_phys_addr_t sr_base;
605 target_ulong mask;
606 uint64_t tmp64;
607 uint32_t tmp;
608 int n, ret;
609 int slb_nr;
610
611 ret = -5;
612 sr_base = env->spr[SPR_ASR];
613 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
614#if 0 /* XXX: Fix this */
615 slb_nr = env->slb_nr;
616#else
617 slb_nr = 32;
618#endif
619 for (n = 0; n < slb_nr; n++) {
620 tmp64 = ldq_phys(sr_base);
621 if (tmp64 & 0x0000000008000000ULL) {
622 /* SLB entry is valid */
623 switch (tmp64 & 0x0000000006000000ULL) {
624 case 0x0000000000000000ULL:
625 /* 256 MB segment */
626 mask = 0xFFFFFFFFF0000000ULL;
627 break;
628 case 0x0000000002000000ULL:
629 /* 1 TB segment */
630 mask = 0xFFFF000000000000ULL;
631 break;
632 case 0x0000000004000000ULL:
633 case 0x0000000006000000ULL:
634 /* Reserved => segment is invalid */
635 continue;
636 }
637 if ((eaddr & mask) == (tmp64 & mask)) {
638 /* SLB match */
639 tmp = ldl_phys(sr_base + 8);
640 *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
641 *page_mask = ~mask;
642 *attr = tmp & 0xFF;
643 ret = 0;
644 break;
645 }
646 }
647 sr_base += 12;
648 }
649
650 return ret;
79aceca5 651}
caa4039c 652#endif /* defined(TARGET_PPC64) */
79aceca5 653
9a64fbe4 654/* Perform segment based translation */
76a66253
JM		 655static int get_segment (CPUState *env, mmu_ctx_t *ctx,
656 target_ulong eaddr, int rw, int type)
79aceca5 657{
caa4039c
JM		 658 target_phys_addr_t sdr, hash, mask, sdr_mask;
659 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
660#if defined(TARGET_PPC64)
661 int attr;
9a64fbe4 662#endif
caa4039c
JM		 663 int ds, nx, vsid_sh, sdr_sh;
664 int ret, ret2;
665
666#if defined(TARGET_PPC64)
7dbe11ac
JM		 667 if (env->mmu_model == POWERPC_MMU_64B ||
668 env->mmu_model == POWERPC_MMU_64BRIDGE) {
caa4039c
JM		 669 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
670 if (ret < 0)
671 return ret;
672 ctx->key = ((attr & 0x40) && msr_pr == 1) ||
673 ((attr & 0x80) && msr_pr == 0) ? 1 : 0;
674 ds = 0;
675 nx = attr & 0x20 ? 1 : 0;
676 vsid_mask = 0x00003FFFFFFFFF80ULL;
677 vsid_sh = 7;
678 sdr_sh = 18;
679 sdr_mask = 0x3FF80;
680 } else
681#endif /* defined(TARGET_PPC64) */
682 {
683 sr = env->sr[eaddr >> 28];
684 page_mask = 0x0FFFFFFF;
685 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
686 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
687 ds = sr & 0x80000000 ? 1 : 0;
688 nx = sr & 0x10000000 ? 1 : 0;
689 vsid = sr & 0x00FFFFFF;
690 vsid_mask = 0x01FFFFC0;
691 vsid_sh = 6;
692 sdr_sh = 16;
693 sdr_mask = 0xFFC0;
9a64fbe4 694#if defined (DEBUG_MMU)
caa4039c
JM		 695 if (loglevel != 0) {
696 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
697 " nip=0x" ADDRX " lr=0x" ADDRX
698 " ir=%d dr=%d pr=%d %d t=%d\n",
699 eaddr, (int)(eaddr >> 28), sr, env->nip,
700 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
701 }
702 if (!ds && loglevel != 0) {
1b9eb036 703 fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
76a66253 704 ctx->key, sr & 0x10000000);
caa4039c 705 }
9a64fbe4 706#endif
caa4039c
JM		 707 }
708 ret = -1;
709 if (!ds) {
9a64fbe4 710 /* Check if instruction fetch is allowed, if needed */
caa4039c 711 if (type != ACCESS_CODE || nx == 0) {
9a64fbe4 712 /* Page address translation */
caa4039c
JM		 713 pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
714 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
76a66253
JM		 715 /* Primary table address */
716 sdr = env->sdr1;
caa4039c
JM		 717 mask = ((sdr & 0x000001FF) << sdr_sh) | sdr_mask;
718 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
76a66253 719 /* Secondary table address */
caa4039c
JM		 720 hash = (~hash) & vsid_mask;
721 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
722#if defined(TARGET_PPC64)
a750fc0b
JM		 723 if (env->mmu_model == POWERPC_MMU_64B ||
724 env->mmu_model == POWERPC_MMU_64BRIDGE) {
caa4039c
JM		 725 /* Only 5 bits of the page index are used in the AVPN */
726 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
727 } else
728#endif
729 {
730 ctx->ptem = (vsid << 7) | (pgidx >> 10);
731 }
76a66253
JM		 732 /* Initialize real address with an invalid value */
733 ctx->raddr = (target_ulong)-1;
7dbe11ac
JM		 734 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
735 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
76a66253
JM		 736 /* Software TLB search */
737 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
76a66253 738 } else {
9a64fbe4 739#if defined (DEBUG_MMU)
4a057712
JM		 740 if (loglevel != 0) {
741 fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
742 "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
743 sdr, (uint32_t)vsid, (uint32_t)pgidx,
744 (uint32_t)hash, ctx->pg_addr[0]);
76a66253 745 }
9a64fbe4 746#endif
76a66253 747 /* Primary table lookup */
caa4039c 748 ret = find_pte(env, ctx, 0, rw);
76a66253
JM		 749 if (ret < 0) {
750 /* Secondary table lookup */
9a64fbe4 751#if defined (DEBUG_MMU)
4a057712 752 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
76a66253 753 fprintf(logfile,
4a057712
JM		 754 "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
755 "hash=0x%05x pg_addr=0x" PADDRX "\n",
756 sdr, (uint32_t)vsid, (uint32_t)pgidx,
757 (uint32_t)hash, ctx->pg_addr[1]);
76a66253 758 }
9a64fbe4 759#endif
caa4039c 760 ret2 = find_pte(env, ctx, 1, rw);
76a66253
JM		 761 if (ret2 != -1)
762 ret = ret2;
763 }
9a64fbe4 764 }
9a64fbe4
FB		 765 } else {
766#if defined (DEBUG_MMU)
4a057712 767 if (loglevel != 0)
76a66253 768 fprintf(logfile, "No access allowed\n");
9a64fbe4 769#endif
76a66253 770 ret = -3;
9a64fbe4
FB		 771 }
772 } else {
773#if defined (DEBUG_MMU)
4a057712 774 if (loglevel != 0)
76a66253 775 fprintf(logfile, "direct store...\n");
9a64fbe4
FB		 776#endif
777 /* Direct-store segment : absolutely *BUGGY* for now */
778 switch (type) {
779 case ACCESS_INT:
780 /* Integer load/store : only access allowed */
781 break;
782 case ACCESS_CODE:
783 /* No code fetch is allowed in direct-store areas */
784 return -4;
785 case ACCESS_FLOAT:
786 /* Floating point load/store */
787 return -4;
788 case ACCESS_RES:
789 /* lwarx, ldarx or srwcx. */
790 return -4;
791 case ACCESS_CACHE:
792 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
793 /* Should make the instruction do no-op.
794 * As it already do no-op, it's quite easy :-)
795 */
76a66253 796 ctx->raddr = eaddr;
9a64fbe4
FB		 797 return 0;
798 case ACCESS_EXT:
799 /* eciwx or ecowx */
800 return -4;
801 default:
802 if (logfile) {
803 fprintf(logfile, "ERROR: instruction should not need "
804 "address translation\n");
805 }
9a64fbe4
FB		 806 return -4;
807 }
76a66253
JM		 808 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
809 ctx->raddr = eaddr;
9a64fbe4
FB		 810 ret = 2;
811 } else {
812 ret = -2;
813 }
79aceca5 814 }
9a64fbe4
FB		 815
816 return ret;
79aceca5
FB		 817}
818
c294fc58
JM		 819/* Generic TLB check function for embedded PowerPC implementations */
820static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
821 target_phys_addr_t *raddrp,
36081602
JM		 822 target_ulong address,
823 uint32_t pid, int ext, int i)
c294fc58
JM		 824{
825 target_ulong mask;
826
827 /* Check valid flag */
828 if (!(tlb->prot & PAGE_VALID)) {
829 if (loglevel != 0)
830 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
831 return -1;
832 }
833 mask = ~(tlb->size - 1);
daf4f96e 834#if defined (DEBUG_SOFTWARE_TLB)
c294fc58
JM		 835 if (loglevel != 0) {
836 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
837 ADDRX " " ADDRX " %d\n",
36081602 838 __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
c294fc58 839 }
daf4f96e 840#endif
c294fc58 841 /* Check PID */
36081602 842 if (tlb->PID != 0 && tlb->PID != pid)
c294fc58
JM		 843 return -1;
844 /* Check effective address */
845 if ((address & mask) != tlb->EPN)
846 return -1;
847 *raddrp = (tlb->RPN & mask) | (address & ~mask);
9706285b 848#if (TARGET_PHYS_ADDR_BITS >= 36)
36081602
JM		 849 if (ext) {
850 /* Extend the physical address to 36 bits */
851 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
852 }
9706285b 853#endif
c294fc58
JM		 854
855 return 0;
856}
857
858/* Generic TLB search function for PowerPC embedded implementations */
36081602 859int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
c294fc58
JM		 860{
861 ppcemb_tlb_t *tlb;
862 target_phys_addr_t raddr;
863 int i, ret;
864
865 /* Default return value is no match */
866 ret = -1;
a750fc0b 867 for (i = 0; i < env->nb_tlb; i++) {
c294fc58 868 tlb = &env->tlb[i].tlbe;
36081602 869 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
c294fc58
JM		 870 ret = i;
871 break;
872 }
873 }
874
875 return ret;
876}
877
daf4f96e
JM		 878/* Helpers specific to PowerPC 40x implementations */
879static void ppc4xx_tlb_invalidate_all (CPUState *env)
a750fc0b
JM		 880{
881 ppcemb_tlb_t *tlb;
a750fc0b
JM		 882 int i;
883
884 for (i = 0; i < env->nb_tlb; i++) {
885 tlb = &env->tlb[i].tlbe;
daf4f96e 886 tlb->prot &= ~PAGE_VALID;
a750fc0b 887 }
daf4f96e 888 tlb_flush(env, 1);
a750fc0b
JM		 889}
890
daf4f96e
JM		 891static void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
892 uint32_t pid)
0a032cbe 893{
daf4f96e 894#if !defined(FLUSH_ALL_TLBS)
0a032cbe 895 ppcemb_tlb_t *tlb;
daf4f96e
JM		 896 target_phys_addr_t raddr;
897 target_ulong page, end;
0a032cbe
JM		 898 int i;
899
900 for (i = 0; i < env->nb_tlb; i++) {
901 tlb = &env->tlb[i].tlbe;
daf4f96e 902 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
0a032cbe
JM		 903 end = tlb->EPN + tlb->size;
904 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
905 tlb_flush_page(env, page);
0a032cbe 906 tlb->prot &= ~PAGE_VALID;
daf4f96e 907 break;
0a032cbe
JM		 908 }
909 }
daf4f96e
JM		 910#else
911 ppc4xx_tlb_invalidate_all(env);
912#endif
0a032cbe
JM		 913}
914
36081602 915int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
e96efcfc 916 target_ulong address, int rw, int access_type)
a8dea12f
JM		 917{
918 ppcemb_tlb_t *tlb;
919 target_phys_addr_t raddr;
a8dea12f 920 int i, ret, zsel, zpr;
3b46e624 921
c55e9aef
JM		 922 ret = -1;
923 raddr = -1;
a8dea12f
JM		 924 for (i = 0; i < env->nb_tlb; i++) {
925 tlb = &env->tlb[i].tlbe;
36081602
JM		 926 if (ppcemb_tlb_check(env, tlb, &raddr, address,
927 env->spr[SPR_40x_PID], 0, i) < 0)
a8dea12f 928 continue;
a8dea12f
JM		 929 zsel = (tlb->attr >> 4) & 0xF;
930 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
daf4f96e 931#if defined (DEBUG_SOFTWARE_TLB)
4a057712 932 if (loglevel != 0) {
a8dea12f
JM		 933 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
934 __func__, i, zsel, zpr, rw, tlb->attr);
935 }
daf4f96e 936#endif
a8dea12f
JM		 937 if (access_type == ACCESS_CODE) {
938 /* Check execute enable bit */
939 switch (zpr) {
c294fc58
JM		 940 case 0x2:
941 if (msr_pr)
942 goto check_exec_perm;
943 goto exec_granted;
a8dea12f
JM		 944 case 0x0:
945 if (msr_pr) {
a8dea12f 946 ctx->prot = 0;
c55e9aef 947 ret = -3;
a8dea12f
JM		 948 break;
949 }
950 /* No break here */
951 case 0x1:
c294fc58 952 check_exec_perm:
a8dea12f
JM		 953 /* Check from TLB entry */
954 if (!(tlb->prot & PAGE_EXEC)) {
955 ret = -3;
956 } else {
c55e9aef 957 if (tlb->prot & PAGE_WRITE) {
a8dea12f 958 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 959 } else {
a8dea12f 960 ctx->prot = PAGE_READ;
c55e9aef 961 }
a8dea12f
JM		 962 ret = 0;
963 }
964 break;
965 case 0x3:
c294fc58 966 exec_granted:
a8dea12f 967 /* All accesses granted */
a8dea12f 968 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 969 ret = 0;
a8dea12f
JM		 970 break;
971 }
972 } else {
973 switch (zpr) {
c294fc58
JM		 974 case 0x2:
975 if (msr_pr)
976 goto check_rw_perm;
977 goto rw_granted;
a8dea12f
JM		 978 case 0x0:
979 if (msr_pr) {
a8dea12f 980 ctx->prot = 0;
c55e9aef 981 ret = -2;
a8dea12f
JM		 982 break;
983 }
984 /* No break here */
985 case 0x1:
c294fc58 986 check_rw_perm:
a8dea12f
JM		 987 /* Check from TLB entry */
988 /* Check write protection bit */
c55e9aef
JM		 989 if (tlb->prot & PAGE_WRITE) {
990 ctx->prot = PAGE_READ | PAGE_WRITE;
991 ret = 0;
a8dea12f 992 } else {
c55e9aef
JM		 993 ctx->prot = PAGE_READ;
994 if (rw)
995 ret = -2;
a8dea12f 996 else
c55e9aef 997 ret = 0;
a8dea12f
JM		 998 }
999 break;
1000 case 0x3:
c294fc58 1001 rw_granted:
a8dea12f 1002 /* All accesses granted */
a8dea12f 1003 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 1004 ret = 0;
a8dea12f
JM		 1005 break;
1006 }
1007 }
1008 if (ret >= 0) {
1009 ctx->raddr = raddr;
daf4f96e 1010#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1011 if (loglevel != 0) {
a8dea12f 1012 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
c55e9aef
JM		 1013 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1014 ret);
a8dea12f 1015 }
daf4f96e 1016#endif
c55e9aef 1017 return 0;
a8dea12f
JM		 1018 }
1019 }
daf4f96e 1020#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1021 if (loglevel != 0) {
c55e9aef
JM		 1022 fprintf(logfile, "%s: access refused " ADDRX " => " REGX
1023 " %d %d\n", __func__, address, raddr, ctx->prot,
1024 ret);
1025 }
daf4f96e 1026#endif
3b46e624 1027
a8dea12f
JM		 1028 return ret;
1029}
1030
c294fc58
JM		 1031void store_40x_sler (CPUPPCState *env, uint32_t val)
1032{
1033 /* XXX: TO BE FIXED */
1034 if (val != 0x00000000) {
1035 cpu_abort(env, "Little-endian regions are not supported by now\n");
1036 }
1037 env->spr[SPR_405_SLER] = val;
1038}
1039
5eb7995e
JM		 1040int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1041 target_ulong address, int rw,
1042 int access_type)
1043{
1044 ppcemb_tlb_t *tlb;
1045 target_phys_addr_t raddr;
1046 int i, prot, ret;
1047
1048 ret = -1;
1049 raddr = -1;
1050 for (i = 0; i < env->nb_tlb; i++) {
1051 tlb = &env->tlb[i].tlbe;
1052 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1053 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1054 continue;
1055 if (msr_pr)
1056 prot = tlb->prot & 0xF;
1057 else
1058 prot = (tlb->prot >> 4) & 0xF;
1059 /* Check the address space */
1060 if (access_type == ACCESS_CODE) {
1061 if (msr_is != (tlb->attr & 1))
1062 continue;
1063 ctx->prot = prot;
1064 if (prot & PAGE_EXEC) {
1065 ret = 0;
1066 break;
1067 }
1068 ret = -3;
1069 } else {
1070 if (msr_ds != (tlb->attr & 1))
1071 continue;
1072 ctx->prot = prot;
1073 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1074 ret = 0;
1075 break;
1076 }
1077 ret = -2;
1078 }
1079 }
1080 if (ret >= 0)
1081 ctx->raddr = raddr;
1082
1083 return ret;
1084}
1085
76a66253
JM		 1086static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1087 target_ulong eaddr, int rw)
1088{
1089 int in_plb, ret;
3b46e624 1090
76a66253
JM		 1091 ctx->raddr = eaddr;
1092 ctx->prot = PAGE_READ;
1093 ret = 0;
a750fc0b
JM		 1094 switch (env->mmu_model) {
1095 case POWERPC_MMU_32B:
1096 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1097 case POWERPC_MMU_SOFT_74xx:
a750fc0b
JM		 1098 case POWERPC_MMU_601:
1099 case POWERPC_MMU_SOFT_4xx:
1100 case POWERPC_MMU_REAL_4xx:
7dbe11ac 1101 case POWERPC_MMU_BOOKE:
caa4039c
JM		 1102 ctx->prot |= PAGE_WRITE;
1103 break;
1104#if defined(TARGET_PPC64)
a750fc0b
JM		 1105 case POWERPC_MMU_64B:
1106 case POWERPC_MMU_64BRIDGE:
caa4039c 1107 /* Real address are 60 bits long */
a750fc0b 1108 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
caa4039c
JM		 1109 ctx->prot |= PAGE_WRITE;
1110 break;
9706285b 1111#endif
a750fc0b 1112 case POWERPC_MMU_SOFT_4xx_Z:
caa4039c
JM		 1113 if (unlikely(msr_pe != 0)) {
1114 /* 403 family add some particular protections,
1115 * using PBL/PBU registers for accesses with no translation.
1116 */
1117 in_plb =
1118 /* Check PLB validity */
1119 (env->pb[0] < env->pb[1] &&
1120 /* and address in plb area */
1121 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1122 (env->pb[2] < env->pb[3] &&
1123 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1124 if (in_plb ^ msr_px) {
1125 /* Access in protected area */
1126 if (rw == 1) {
1127 /* Access is not allowed */
1128 ret = -2;
1129 }
1130 } else {
1131 /* Read-write access is allowed */
1132 ctx->prot |= PAGE_WRITE;
76a66253 1133 }
76a66253 1134 }
e1833e1f 1135 break;
a750fc0b 1136 case POWERPC_MMU_BOOKE_FSL:
caa4039c
JM		 1137 /* XXX: TODO */
1138 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1139 break;
1140 default:
1141 cpu_abort(env, "Unknown or invalid MMU model\n");
1142 return -1;
76a66253
JM		 1143 }
1144
1145 return ret;
1146}
1147
1148int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1149 int rw, int access_type, int check_BATs)
9a64fbe4
FB		 1150{
1151 int ret;
514fb8c1 1152#if 0
4a057712 1153 if (loglevel != 0) {
9a64fbe4
FB		 1154 fprintf(logfile, "%s\n", __func__);
1155 }
d9bce9d9 1156#endif
4b3686fa
FB		 1157 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1158 (access_type != ACCESS_CODE && msr_dr == 0)) {
9a64fbe4 1159 /* No address translation */
76a66253 1160 ret = check_physical(env, ctx, eaddr, rw);
9a64fbe4 1161 } else {
c55e9aef 1162 ret = -1;
a750fc0b
JM		 1163 switch (env->mmu_model) {
1164 case POWERPC_MMU_32B:
1165 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1166 case POWERPC_MMU_SOFT_74xx:
a8dea12f 1167 /* Try to find a BAT */
a8dea12f
JM		 1168 if (check_BATs)
1169 ret = get_bat(env, ctx, eaddr, rw, access_type);
c55e9aef
JM		 1170 /* No break here */
1171#if defined(TARGET_PPC64)
a750fc0b
JM		 1172 case POWERPC_MMU_64B:
1173 case POWERPC_MMU_64BRIDGE:
c55e9aef 1174#endif
a8dea12f 1175 if (ret < 0) {
c55e9aef 1176 /* We didn't match any BAT entry or don't have BATs */
a8dea12f
JM		 1177 ret = get_segment(env, ctx, eaddr, rw, access_type);
1178 }
1179 break;
a750fc0b
JM		 1180 case POWERPC_MMU_SOFT_4xx:
1181 case POWERPC_MMU_SOFT_4xx_Z:
36081602 1182 ret = mmu40x_get_physical_address(env, ctx, eaddr,
a8dea12f
JM		 1183 rw, access_type);
1184 break;
a750fc0b 1185 case POWERPC_MMU_601:
c55e9aef
JM		 1186 /* XXX: TODO */
1187 cpu_abort(env, "601 MMU model not implemented\n");
1188 return -1;
a750fc0b 1189 case POWERPC_MMU_BOOKE:
5eb7995e
JM		 1190 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1191 rw, access_type);
1192 break;
a750fc0b 1193 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1194 /* XXX: TODO */
1195 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1196 return -1;
a750fc0b 1197 case POWERPC_MMU_REAL_4xx:
2662a059
JM		 1198 cpu_abort(env, "PowerPC 401 does not do any translation\n");
1199 return -1;
c55e9aef
JM		 1200 default:
1201 cpu_abort(env, "Unknown or invalid MMU model\n");
a8dea12f 1202 return -1;
9a64fbe4
FB		 1203 }
1204 }
514fb8c1 1205#if 0
4a057712
JM		 1206 if (loglevel != 0) {
1207 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
c55e9aef 1208 __func__, eaddr, ret, ctx->raddr);
a541f297 1209 }
76a66253 1210#endif
d9bce9d9 1211
9a64fbe4
FB		 1212 return ret;
1213}
1214
9b3c35e0 1215target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
a6b025d3 1216{
76a66253 1217 mmu_ctx_t ctx;
a6b025d3 1218
76a66253 1219 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
a6b025d3 1220 return -1;
76a66253
JM		 1221
1222 return ctx.raddr & TARGET_PAGE_MASK;
a6b025d3 1223}
9a64fbe4 1224
9a64fbe4 1225/* Perform address translation */
e96efcfc 1226int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
a541f297 1227 int is_user, int is_softmmu)
9a64fbe4 1228{
76a66253 1229 mmu_ctx_t ctx;
a541f297 1230 int access_type;
9a64fbe4 1231 int ret = 0;
d9bce9d9 1232
b769d8fe
FB		 1233 if (rw == 2) {
1234 /* code access */
1235 rw = 0;
1236 access_type = ACCESS_CODE;
1237 } else {
1238 /* data access */
1239 /* XXX: put correct access by using cpu_restore_state()
1240 correctly */
1241 access_type = ACCESS_INT;
1242 // access_type = env->access_type;
1243 }
76a66253 1244 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
9a64fbe4 1245 if (ret == 0) {
76a66253
JM		 1246 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
1247 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1248 is_user, is_softmmu);
9a64fbe4 1249 } else if (ret < 0) {
9a64fbe4 1250#if defined (DEBUG_MMU)
4a057712 1251 if (loglevel != 0)
76a66253 1252 cpu_dump_state(env, logfile, fprintf, 0);
9a64fbe4
FB		 1253#endif
1254 if (access_type == ACCESS_CODE) {
9a64fbe4
FB		 1255 switch (ret) {
1256 case -1:
76a66253 1257 /* No matches in page tables or TLB */
a750fc0b
JM		 1258 switch (env->mmu_model) {
1259 case POWERPC_MMU_SOFT_6xx:
8f793433
JM		 1260 env->exception_index = POWERPC_EXCP_IFTLB;
1261 env->error_code = 1 << 18;
76a66253
JM		 1262 env->spr[SPR_IMISS] = address;
1263 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
76a66253 1264 goto tlb_miss;
7dbe11ac 1265 case POWERPC_MMU_SOFT_74xx:
8f793433 1266 env->exception_index = POWERPC_EXCP_IFTLB;
7dbe11ac 1267 goto tlb_miss_74xx;
a750fc0b
JM		 1268 case POWERPC_MMU_SOFT_4xx:
1269 case POWERPC_MMU_SOFT_4xx_Z:
8f793433
JM		 1270 env->exception_index = POWERPC_EXCP_ITLB;
1271 env->error_code = 0;
a8dea12f
JM		 1272 env->spr[SPR_40x_DEAR] = address;
1273 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef 1274 break;
a750fc0b 1275 case POWERPC_MMU_32B:
c55e9aef 1276#if defined(TARGET_PPC64)
a750fc0b 1277 case POWERPC_MMU_64B:
a750fc0b 1278 case POWERPC_MMU_64BRIDGE:
c55e9aef 1279#endif
8f793433
JM		 1280 env->exception_index = POWERPC_EXCP_ISI;
1281 env->error_code = 0x40000000;
1282 break;
a750fc0b 1283 case POWERPC_MMU_601:
c55e9aef
JM		 1284 /* XXX: TODO */
1285 cpu_abort(env, "MMU model not implemented\n");
1286 return -1;
a750fc0b 1287 case POWERPC_MMU_BOOKE:
c55e9aef
JM		 1288 /* XXX: TODO */
1289 cpu_abort(env, "MMU model not implemented\n");
1290 return -1;
a750fc0b 1291 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1292 /* XXX: TODO */
1293 cpu_abort(env, "MMU model not implemented\n");
1294 return -1;
a750fc0b 1295 case POWERPC_MMU_REAL_4xx:
2662a059
JM		 1296 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1297 "exceptions\n");
1298 return -1;
c55e9aef
JM		 1299 default:
1300 cpu_abort(env, "Unknown or invalid MMU model\n");
1301 return -1;
76a66253 1302 }
9a64fbe4
FB		 1303 break;
1304 case -2:
1305 /* Access rights violation */
8f793433
JM		 1306 env->exception_index = POWERPC_EXCP_ISI;
1307 env->error_code = 0x08000000;
9a64fbe4
FB		 1308 break;
1309 case -3:
76a66253 1310 /* No execute protection violation */
8f793433
JM		 1311 env->exception_index = POWERPC_EXCP_ISI;
1312 env->error_code = 0x10000000;
9a64fbe4
FB		 1313 break;
1314 case -4:
1315 /* Direct store exception */
1316 /* No code fetch is allowed in direct-store areas */
8f793433
JM		 1317 env->exception_index = POWERPC_EXCP_ISI;
1318 env->error_code = 0x10000000;
2be0071f 1319 break;
e1833e1f 1320#if defined(TARGET_PPC64)
2be0071f
FB		 1321 case -5:
1322 /* No match in segment table */
8f793433
JM		 1323 env->exception_index = POWERPC_EXCP_ISEG;
1324 env->error_code = 0;
9a64fbe4 1325 break;
e1833e1f 1326#endif
9a64fbe4
FB		 1327 }
1328 } else {
9a64fbe4
FB		 1329 switch (ret) {
1330 case -1:
76a66253 1331 /* No matches in page tables or TLB */
a750fc0b
JM		 1332 switch (env->mmu_model) {
1333 case POWERPC_MMU_SOFT_6xx:
76a66253 1334 if (rw == 1) {
8f793433
JM		 1335 env->exception_index = POWERPC_EXCP_DSTLB;
1336 env->error_code = 1 << 16;
76a66253 1337 } else {
8f793433
JM		 1338 env->exception_index = POWERPC_EXCP_DLTLB;
1339 env->error_code = 0;
76a66253
JM		 1340 }
1341 env->spr[SPR_DMISS] = address;
1342 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1343 tlb_miss:
8f793433 1344 env->error_code |= ctx.key << 19;
76a66253
JM		 1345 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1346 env->spr[SPR_HASH2] = ctx.pg_addr[1];
8f793433 1347 break;
7dbe11ac
JM		 1348 case POWERPC_MMU_SOFT_74xx:
1349 if (rw == 1) {
8f793433 1350 env->exception_index = POWERPC_EXCP_DSTLB;
7dbe11ac 1351 } else {
8f793433 1352 env->exception_index = POWERPC_EXCP_DLTLB;
7dbe11ac
JM		 1353 }
1354 tlb_miss_74xx:
1355 /* Implement LRU algorithm */
8f793433 1356 env->error_code = ctx.key << 19;
7dbe11ac
JM		 1357 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1358 ((env->last_way + 1) & (env->nb_ways - 1));
1359 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
7dbe11ac 1360 break;
a750fc0b
JM		 1361 case POWERPC_MMU_SOFT_4xx:
1362 case POWERPC_MMU_SOFT_4xx_Z:
8f793433
JM		 1363 env->exception_index = POWERPC_EXCP_DTLB;
1364 env->error_code = 0;
a8dea12f
JM		 1365 env->spr[SPR_40x_DEAR] = address;
1366 if (rw)
1367 env->spr[SPR_40x_ESR] = 0x00800000;
1368 else
1369 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef 1370 break;
a750fc0b 1371 case POWERPC_MMU_32B:
c55e9aef 1372#if defined(TARGET_PPC64)
a750fc0b 1373 case POWERPC_MMU_64B:
a750fc0b 1374 case POWERPC_MMU_64BRIDGE:
c55e9aef 1375#endif
8f793433
JM		 1376 env->exception_index = POWERPC_EXCP_DSI;
1377 env->error_code = 0;
1378 env->spr[SPR_DAR] = address;
1379 if (rw == 1)
1380 env->spr[SPR_DSISR] = 0x42000000;
1381 else
1382 env->spr[SPR_DSISR] = 0x40000000;
1383 break;
a750fc0b 1384 case POWERPC_MMU_601:
c55e9aef
JM		 1385 /* XXX: TODO */
1386 cpu_abort(env, "MMU model not implemented\n");
1387 return -1;
a750fc0b 1388 case POWERPC_MMU_BOOKE:
c55e9aef
JM		 1389 /* XXX: TODO */
1390 cpu_abort(env, "MMU model not implemented\n");
1391 return -1;
a750fc0b 1392 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1393 /* XXX: TODO */
1394 cpu_abort(env, "MMU model not implemented\n");
1395 return -1;
a750fc0b 1396 case POWERPC_MMU_REAL_4xx:
2662a059
JM		 1397 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1398 "exceptions\n");
1399 return -1;
c55e9aef
JM		 1400 default:
1401 cpu_abort(env, "Unknown or invalid MMU model\n");
1402 return -1;
76a66253 1403 }
9a64fbe4
FB		 1404 break;
1405 case -2:
1406 /* Access rights violation */
8f793433
JM		 1407 env->exception_index = POWERPC_EXCP_DSI;
1408 env->error_code = 0;
1409 env->spr[SPR_DAR] = address;
1410 if (rw == 1)
1411 env->spr[SPR_DSISR] = 0x0A000000;
1412 else
1413 env->spr[SPR_DSISR] = 0x08000000;
9a64fbe4
FB		 1414 break;
1415 case -4:
1416 /* Direct store exception */
1417 switch (access_type) {
1418 case ACCESS_FLOAT:
1419 /* Floating point load/store */
8f793433
JM		 1420 env->exception_index = POWERPC_EXCP_ALIGN;
1421 env->error_code = POWERPC_EXCP_ALIGN_FP;
1422 env->spr[SPR_DAR] = address;
9a64fbe4
FB		 1423 break;
1424 case ACCESS_RES:
8f793433
JM		 1425 /* lwarx, ldarx or stwcx. */
1426 env->exception_index = POWERPC_EXCP_DSI;
1427 env->error_code = 0;
1428 env->spr[SPR_DAR] = address;
1429 if (rw == 1)
1430 env->spr[SPR_DSISR] = 0x06000000;
1431 else
1432 env->spr[SPR_DSISR] = 0x04000000;
9a64fbe4
FB		 1433 break;
1434 case ACCESS_EXT:
1435 /* eciwx or ecowx */
8f793433
JM		 1436 env->exception_index = POWERPC_EXCP_DSI;
1437 env->error_code = 0;
1438 env->spr[SPR_DAR] = address;
1439 if (rw == 1)
1440 env->spr[SPR_DSISR] = 0x06100000;
1441 else
1442 env->spr[SPR_DSISR] = 0x04100000;
9a64fbe4
FB		 1443 break;
1444 default:
76a66253 1445 printf("DSI: invalid exception (%d)\n", ret);
8f793433
JM		 1446 env->exception_index = POWERPC_EXCP_PROGRAM;
1447 env->error_code =
1448 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1449 env->spr[SPR_DAR] = address;
9a64fbe4
FB		 1450 break;
1451 }
fdabc366 1452 break;
e1833e1f 1453#if defined(TARGET_PPC64)
2be0071f
FB		 1454 case -5:
1455 /* No match in segment table */
8f793433
JM		 1456 env->exception_index = POWERPC_EXCP_DSEG;
1457 env->error_code = 0;
1458 env->spr[SPR_DAR] = address;
2be0071f 1459 break;
e1833e1f 1460#endif
9a64fbe4 1461 }
9a64fbe4
FB		 1462 }
1463#if 0
8f793433
JM		 1464 printf("%s: set exception to %d %02x\n", __func__,
1465 env->exception, env->error_code);
9a64fbe4 1466#endif
9a64fbe4
FB		 1467 ret = 1;
1468 }
76a66253 1469
9a64fbe4
FB		 1470 return ret;
1471}
1472
3fc6c082
FB		 1473/*****************************************************************************/
1474/* BATs management */
1475#if !defined(FLUSH_ALL_TLBS)
1476static inline void do_invalidate_BAT (CPUPPCState *env,
1477 target_ulong BATu, target_ulong mask)
1478{
1479 target_ulong base, end, page;
76a66253 1480
3fc6c082
FB		 1481 base = BATu & ~0x0001FFFF;
1482 end = base + mask + 0x00020000;
1483#if defined (DEBUG_BATS)
76a66253 1484 if (loglevel != 0) {
1b9eb036 1485 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
76a66253
JM		 1486 base, end, mask);
1487 }
3fc6c082
FB		 1488#endif
1489 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1490 tlb_flush_page(env, page);
1491#if defined (DEBUG_BATS)
1492 if (loglevel != 0)
1493 fprintf(logfile, "Flush done\n");
1494#endif
1495}
1496#endif
1497
1498static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
1499 target_ulong value)
1500{
1501#if defined (DEBUG_BATS)
1502 if (loglevel != 0) {
1b9eb036
JM		 1503 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1504 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
3fc6c082
FB		 1505 }
1506#endif
1507}
1508
1509target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1510{
1511 return env->IBAT[0][nr];
1512}
1513
1514target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1515{
1516 return env->IBAT[1][nr];
1517}
1518
1519void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1520{
1521 target_ulong mask;
1522
1523 dump_store_bat(env, 'I', 0, nr, value);
1524 if (env->IBAT[0][nr] != value) {
1525 mask = (value << 15) & 0x0FFE0000UL;
1526#if !defined(FLUSH_ALL_TLBS)
1527 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1528#endif
1529 /* When storing valid upper BAT, mask BEPI and BRPN
1530 * and invalidate all TLBs covered by this BAT
1531 */
1532 mask = (value << 15) & 0x0FFE0000UL;
1533 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1534 (value & ~0x0001FFFFUL & ~mask);
1535 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1536 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1537#if !defined(FLUSH_ALL_TLBS)
1538 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
76a66253 1539#else
3fc6c082
FB		 1540 tlb_flush(env, 1);
1541#endif
1542 }
1543}
1544
1545void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1546{
1547 dump_store_bat(env, 'I', 1, nr, value);
1548 env->IBAT[1][nr] = value;
1549}
1550
1551target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1552{
1553 return env->DBAT[0][nr];
1554}
1555
1556target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1557{
1558 return env->DBAT[1][nr];
1559}
1560
1561void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1562{
1563 target_ulong mask;
1564
1565 dump_store_bat(env, 'D', 0, nr, value);
1566 if (env->DBAT[0][nr] != value) {
1567 /* When storing valid upper BAT, mask BEPI and BRPN
1568 * and invalidate all TLBs covered by this BAT
1569 */
1570 mask = (value << 15) & 0x0FFE0000UL;
1571#if !defined(FLUSH_ALL_TLBS)
1572 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1573#endif
1574 mask = (value << 15) & 0x0FFE0000UL;
1575 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1576 (value & ~0x0001FFFFUL & ~mask);
1577 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1578 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1579#if !defined(FLUSH_ALL_TLBS)
1580 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1581#else
1582 tlb_flush(env, 1);
1583#endif
1584 }
1585}
1586
1587void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1588{
1589 dump_store_bat(env, 'D', 1, nr, value);
1590 env->DBAT[1][nr] = value;
1591}
1592
0a032cbe
JM		 1593
1594/*****************************************************************************/
1595/* TLB management */
1596void ppc_tlb_invalidate_all (CPUPPCState *env)
1597{
daf4f96e
JM		 1598 switch (env->mmu_model) {
1599 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1600 case POWERPC_MMU_SOFT_74xx:
0a032cbe 1601 ppc6xx_tlb_invalidate_all(env);
daf4f96e
JM		 1602 break;
1603 case POWERPC_MMU_SOFT_4xx:
1604 case POWERPC_MMU_SOFT_4xx_Z:
0a032cbe 1605 ppc4xx_tlb_invalidate_all(env);
daf4f96e 1606 break;
7dbe11ac
JM		 1607 case POWERPC_MMU_REAL_4xx:
1608 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1609 break;
1610 case POWERPC_MMU_BOOKE:
1611 /* XXX: TODO */
1612 cpu_abort(env, "MMU model not implemented\n");
1613 break;
1614 case POWERPC_MMU_BOOKE_FSL:
1615 /* XXX: TODO */
1616 cpu_abort(env, "MMU model not implemented\n");
1617 break;
1618 case POWERPC_MMU_601:
1619 /* XXX: TODO */
1620 cpu_abort(env, "MMU model not implemented\n");
1621 break;
1622 case POWERPC_MMU_32B:
00af685f 1623#if defined(TARGET_PPC64)
7dbe11ac
JM		 1624 case POWERPC_MMU_64B:
1625 case POWERPC_MMU_64BRIDGE:
00af685f 1626#endif /* defined(TARGET_PPC64) */
0a032cbe 1627 tlb_flush(env, 1);
daf4f96e 1628 break;
00af685f
JM		 1629 default:
1630 /* XXX: TODO */
1631 cpu_abort(env, "Unknown MMU model %d\n", env->mmu_model);
1632 break;
0a032cbe
JM		 1633 }
1634}
1635
daf4f96e
JM		 1636void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1637{
1638#if !defined(FLUSH_ALL_TLBS)
1639 addr &= TARGET_PAGE_MASK;
1640 switch (env->mmu_model) {
1641 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1642 case POWERPC_MMU_SOFT_74xx:
daf4f96e
JM		 1643 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1644 if (env->id_tlbs == 1)
1645 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1646 break;
1647 case POWERPC_MMU_SOFT_4xx:
1648 case POWERPC_MMU_SOFT_4xx_Z:
1649 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1650 break;
7dbe11ac
JM		 1651 case POWERPC_MMU_REAL_4xx:
1652 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1653 break;
1654 case POWERPC_MMU_BOOKE:
1655 /* XXX: TODO */
1656 cpu_abort(env, "MMU model not implemented\n");
1657 break;
1658 case POWERPC_MMU_BOOKE_FSL:
1659 /* XXX: TODO */
1660 cpu_abort(env, "MMU model not implemented\n");
1661 break;
1662 case POWERPC_MMU_601:
1663 /* XXX: TODO */
1664 cpu_abort(env, "MMU model not implemented\n");
1665 break;
1666 case POWERPC_MMU_32B:
daf4f96e
JM		 1667 /* tlbie invalidate TLBs for all segments */
1668 addr &= ~((target_ulong)-1 << 28);
1669 /* XXX: this case should be optimized,
1670 * giving a mask to tlb_flush_page
1671 */
1672 tlb_flush_page(env, addr | (0x0 << 28));
1673 tlb_flush_page(env, addr | (0x1 << 28));
1674 tlb_flush_page(env, addr | (0x2 << 28));
1675 tlb_flush_page(env, addr | (0x3 << 28));
1676 tlb_flush_page(env, addr | (0x4 << 28));
1677 tlb_flush_page(env, addr | (0x5 << 28));
1678 tlb_flush_page(env, addr | (0x6 << 28));
1679 tlb_flush_page(env, addr | (0x7 << 28));
1680 tlb_flush_page(env, addr | (0x8 << 28));
1681 tlb_flush_page(env, addr | (0x9 << 28));
1682 tlb_flush_page(env, addr | (0xA << 28));
1683 tlb_flush_page(env, addr | (0xB << 28));
1684 tlb_flush_page(env, addr | (0xC << 28));
1685 tlb_flush_page(env, addr | (0xD << 28));
1686 tlb_flush_page(env, addr | (0xE << 28));
1687 tlb_flush_page(env, addr | (0xF << 28));
7dbe11ac 1688 break;
00af685f 1689#if defined(TARGET_PPC64)
7dbe11ac
JM		 1690 case POWERPC_MMU_64B:
1691 case POWERPC_MMU_64BRIDGE:
1692 /* tlbie invalidate TLBs for all segments */
1693 /* XXX: given the fact that there are too many segments to invalidate,
00af685f 1694 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
7dbe11ac
JM		 1695 * we just invalidate all TLBs
1696 */
1697 tlb_flush(env, 1);
1698 break;
00af685f
JM		 1699#endif /* defined(TARGET_PPC64) */
1700 default:
1701 /* XXX: TODO */
1702 cpu_abort(env, "Unknown MMU model 2\n");
1703 break;
daf4f96e
JM		 1704 }
1705#else
1706 ppc_tlb_invalidate_all(env);
1707#endif
1708}
1709
1710#if defined(TARGET_PPC64)
1711void ppc_slb_invalidate_all (CPUPPCState *env)
1712{
1713 /* XXX: TODO */
1714 tlb_flush(env, 1);
1715}
1716
1717void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
1718{
1719 /* XXX: TODO */
1720 tlb_flush(env, 1);
1721}
1722#endif
1723
1724
3fc6c082
FB		 1725/*****************************************************************************/
1726/* Special registers manipulation */
d9bce9d9
JM		 1727#if defined(TARGET_PPC64)
1728target_ulong ppc_load_asr (CPUPPCState *env)
1729{
1730 return env->asr;
1731}
1732
1733void ppc_store_asr (CPUPPCState *env, target_ulong value)
1734{
1735 if (env->asr != value) {
1736 env->asr = value;
1737 tlb_flush(env, 1);
1738 }
1739}
1740#endif
1741
3fc6c082
FB		 1742target_ulong do_load_sdr1 (CPUPPCState *env)
1743{
1744 return env->sdr1;
1745}
1746
1747void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1748{
1749#if defined (DEBUG_MMU)
1750 if (loglevel != 0) {
1b9eb036 1751 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
3fc6c082
FB		 1752 }
1753#endif
1754 if (env->sdr1 != value) {
1755 env->sdr1 = value;
76a66253 1756 tlb_flush(env, 1);
3fc6c082
FB		 1757 }
1758}
1759
1760target_ulong do_load_sr (CPUPPCState *env, int srnum)
1761{
1762 return env->sr[srnum];
1763}
1764
1765void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1766{
1767#if defined (DEBUG_MMU)
1768 if (loglevel != 0) {
1b9eb036
JM		 1769 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1770 __func__, srnum, value, env->sr[srnum]);
3fc6c082
FB		 1771 }
1772#endif
1773 if (env->sr[srnum] != value) {
1774 env->sr[srnum] = value;
1775#if !defined(FLUSH_ALL_TLBS) && 0
1776 {
1777 target_ulong page, end;
1778 /* Invalidate 256 MB of virtual memory */
1779 page = (16 << 20) * srnum;
1780 end = page + (16 << 20);
1781 for (; page != end; page += TARGET_PAGE_SIZE)
1782 tlb_flush_page(env, page);
1783 }
1784#else
76a66253 1785 tlb_flush(env, 1);
3fc6c082
FB		 1786#endif
1787 }
1788}
76a66253 1789#endif /* !defined (CONFIG_USER_ONLY) */
3fc6c082 1790
bfa1e5cf 1791target_ulong ppc_load_xer (CPUPPCState *env)
79aceca5
FB		 1792{
1793 return (xer_so << XER_SO) |
1794 (xer_ov << XER_OV) |
1795 (xer_ca << XER_CA) |
3fc6c082
FB		 1796 (xer_bc << XER_BC) |
1797 (xer_cmp << XER_CMP);
79aceca5
FB		 1798}
1799
bfa1e5cf 1800void ppc_store_xer (CPUPPCState *env, target_ulong value)
79aceca5
FB		 1801{
1802 xer_so = (value >> XER_SO) & 0x01;
1803 xer_ov = (value >> XER_OV) & 0x01;
1804 xer_ca = (value >> XER_CA) & 0x01;
3fc6c082 1805 xer_cmp = (value >> XER_CMP) & 0xFF;
d9bce9d9 1806 xer_bc = (value >> XER_BC) & 0x7F;
79aceca5
FB		 1807}
1808
76a66253
JM		 1809/* Swap temporary saved registers with GPRs */
1810static inline void swap_gpr_tgpr (CPUPPCState *env)
79aceca5 1811{
76a66253
JM		 1812 ppc_gpr_t tmp;
1813
1814 tmp = env->gpr[0];
1815 env->gpr[0] = env->tgpr[0];
1816 env->tgpr[0] = tmp;
1817 tmp = env->gpr[1];
1818 env->gpr[1] = env->tgpr[1];
1819 env->tgpr[1] = tmp;
1820 tmp = env->gpr[2];
1821 env->gpr[2] = env->tgpr[2];
1822 env->tgpr[2] = tmp;
1823 tmp = env->gpr[3];
1824 env->gpr[3] = env->tgpr[3];
1825 env->tgpr[3] = tmp;
79aceca5
FB		 1826}
1827
76a66253
JM		 1828/* GDBstub can read and write MSR... */
1829target_ulong do_load_msr (CPUPPCState *env)
79aceca5 1830{
76a66253
JM		 1831 return
1832#if defined (TARGET_PPC64)
d9bce9d9
JM		 1833 ((target_ulong)msr_sf << MSR_SF) |
1834 ((target_ulong)msr_isf << MSR_ISF) |
1835 ((target_ulong)msr_hv << MSR_HV) |
76a66253 1836#endif
d9bce9d9
JM		 1837 ((target_ulong)msr_ucle << MSR_UCLE) |
1838 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1839 ((target_ulong)msr_ap << MSR_AP) |
1840 ((target_ulong)msr_sa << MSR_SA) |
1841 ((target_ulong)msr_key << MSR_KEY) |
1842 ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
1843 ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
1844 ((target_ulong)msr_ile << MSR_ILE) |
1845 ((target_ulong)msr_ee << MSR_EE) |
1846 ((target_ulong)msr_pr << MSR_PR) |
1847 ((target_ulong)msr_fp << MSR_FP) |
1848 ((target_ulong)msr_me << MSR_ME) |
1849 ((target_ulong)msr_fe0 << MSR_FE0) |
1850 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1851 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1852 ((target_ulong)msr_fe1 << MSR_FE1) |
1853 ((target_ulong)msr_al << MSR_AL) |
1854 ((target_ulong)msr_ip << MSR_IP) |
1855 ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
1856 ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
1857 ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
1858 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1859 ((target_ulong)msr_ri << MSR_RI) |
1860 ((target_ulong)msr_le << MSR_LE);
3fc6c082
FB		 1861}
1862
a97fed52 1863int do_store_msr (CPUPPCState *env, target_ulong value)
313adae9 1864{
50443c98
FB		 1865 int enter_pm;
1866
3fc6c082
FB		 1867 value &= env->msr_mask;
1868 if (((value >> MSR_IR) & 1) != msr_ir ||
1869 ((value >> MSR_DR) & 1) != msr_dr) {
76a66253 1870 /* Flush all tlb when changing translation mode */
d094807b 1871 tlb_flush(env, 1);
3fc6c082 1872 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
a541f297 1873 }
3fc6c082
FB		 1874#if 0
1875 if (loglevel != 0) {
1876 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1877 }
1878#endif
a750fc0b
JM		 1879 switch (env->excp_model) {
1880 case POWERPC_EXCP_602:
1881 case POWERPC_EXCP_603:
1882 case POWERPC_EXCP_603E:
1883 case POWERPC_EXCP_G2:
76a66253
JM		 1884 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1885 /* Swap temporary saved registers with GPRs */
1886 swap_gpr_tgpr(env);
1887 }
1888 break;
1889 default:
1890 break;
1891 }
1892#if defined (TARGET_PPC64)
1893 msr_sf = (value >> MSR_SF) & 1;
1894 msr_isf = (value >> MSR_ISF) & 1;
1895 msr_hv = (value >> MSR_HV) & 1;
1896#endif
1897 msr_ucle = (value >> MSR_UCLE) & 1;
1898 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
1899 msr_ap = (value >> MSR_AP) & 1;
1900 msr_sa = (value >> MSR_SA) & 1;
1901 msr_key = (value >> MSR_KEY) & 1;
1902 msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
1903 msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
1904 msr_ile = (value >> MSR_ILE) & 1;
1905 msr_ee = (value >> MSR_EE) & 1;
1906 msr_pr = (value >> MSR_PR) & 1;
1907 msr_fp = (value >> MSR_FP) & 1;
1908 msr_me = (value >> MSR_ME) & 1;
1909 msr_fe0 = (value >> MSR_FE0) & 1;
1910 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
1911 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
1912 msr_fe1 = (value >> MSR_FE1) & 1;
1913 msr_al = (value >> MSR_AL) & 1;
1914 msr_ip = (value >> MSR_IP) & 1;
1915 msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
1916 msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
1917 msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
1918 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
1919 msr_ri = (value >> MSR_RI) & 1;
1920 msr_le = (value >> MSR_LE) & 1;
3fc6c082 1921 do_compute_hflags(env);
50443c98
FB		 1922
1923 enter_pm = 0;
a750fc0b
JM		 1924 switch (env->excp_model) {
1925 case POWERPC_EXCP_603:
1926 case POWERPC_EXCP_603E:
1927 case POWERPC_EXCP_G2:
d9bce9d9
JM		 1928 /* Don't handle SLEEP mode: we should disable all clocks...
1929 * No dynamic power-management.
1930 */
1931 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1932 enter_pm = 1;
1933 break;
a750fc0b 1934 case POWERPC_EXCP_604:
d9bce9d9
JM		 1935 if (msr_pow == 1)
1936 enter_pm = 1;
1937 break;
a750fc0b 1938 case POWERPC_EXCP_7x0:
76a66253 1939 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
50443c98
FB		 1940 enter_pm = 1;
1941 break;
1942 default:
1943 break;
1944 }
a97fed52
JM		 1945
1946 return enter_pm;
3fc6c082
FB		 1947}
1948
d9bce9d9 1949#if defined(TARGET_PPC64)
a97fed52 1950int ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
d9bce9d9 1951{
a97fed52
JM		 1952 return do_store_msr(env, (do_load_msr(env) & ~0xFFFFFFFFULL) |
1953 (value & 0xFFFFFFFF));
d9bce9d9
JM		 1954}
1955#endif
1956
76a66253 1957void do_compute_hflags (CPUPPCState *env)
3fc6c082 1958{
76a66253 1959 /* Compute current hflags */
4296f459 1960 env->hflags = (msr_vr << MSR_VR) |
c62db105
JM		 1961 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
1962 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
1963 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
76a66253 1964#if defined (TARGET_PPC64)
4296f459
JM		 1965 env->hflags |= msr_cm << MSR_CM;
1966 env->hflags |= (uint64_t)msr_sf << MSR_SF;
1967 env->hflags |= (uint64_t)msr_hv << MSR_HV;
4b3686fa 1968#endif
3fc6c082
FB		 1969}
1970
1971/*****************************************************************************/
1972/* Exception processing */
18fba28c 1973#if defined (CONFIG_USER_ONLY)
9a64fbe4 1974void do_interrupt (CPUState *env)
79aceca5 1975{
e1833e1f
JM		 1976 env->exception_index = POWERPC_EXCP_NONE;
1977 env->error_code = 0;
18fba28c 1978}
47103572 1979
e9df014c 1980void ppc_hw_interrupt (CPUState *env)
47103572 1981{
e1833e1f
JM		 1982 env->exception_index = POWERPC_EXCP_NONE;
1983 env->error_code = 0;
47103572 1984}
76a66253 1985#else /* defined (CONFIG_USER_ONLY) */
36081602 1986static void dump_syscall (CPUState *env)
d094807b 1987{
d9bce9d9 1988 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1b9eb036 1989 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
d094807b
FB		 1990 env->gpr[0], env->gpr[3], env->gpr[4],
1991 env->gpr[5], env->gpr[6], env->nip);
1992}
1993
e1833e1f
JM		 1994/* Note that this function should be greatly optimized
1995 * when called with a constant excp, from ppc_hw_interrupt
1996 */
1997static always_inline void powerpc_excp (CPUState *env,
1998 int excp_model, int excp)
18fba28c 1999{
e1833e1f
JM		 2000 target_ulong msr, vector;
2001 int srr0, srr1, asrr0, asrr1;
79aceca5 2002
b769d8fe 2003 if (loglevel & CPU_LOG_INT) {
1b9eb036
JM		 2004 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
2005 env->nip, excp, env->error_code);
b769d8fe 2006 }
e1833e1f
JM		 2007 msr = do_load_msr(env);
2008 srr0 = SPR_SRR0;
2009 srr1 = SPR_SRR1;
2010 asrr0 = -1;
2011 asrr1 = -1;
2012 msr &= ~((target_ulong)0x783F0000);
9a64fbe4 2013 switch (excp) {
e1833e1f
JM		 2014 case POWERPC_EXCP_NONE:
2015 /* Should never happen */
2016 return;
2017 case POWERPC_EXCP_CRITICAL: /* Critical input */
2018 msr_ri = 0; /* XXX: check this */
2019 switch (excp_model) {
a750fc0b 2020 case POWERPC_EXCP_40x:
e1833e1f
JM		 2021 srr0 = SPR_40x_SRR2;
2022 srr1 = SPR_40x_SRR3;
c62db105 2023 break;
a750fc0b 2024 case POWERPC_EXCP_BOOKE:
e1833e1f
JM		 2025 srr0 = SPR_BOOKE_CSRR0;
2026 srr1 = SPR_BOOKE_CSRR1;
c62db105 2027 break;
e1833e1f 2028 case POWERPC_EXCP_G2:
c62db105 2029 break;
e1833e1f
JM		 2030 default:
2031 goto excp_invalid;
2be0071f 2032 }
9a64fbe4 2033 goto store_next;
e1833e1f
JM		 2034 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2035 if (msr_me == 0) {
2036 /* Machine check exception is not enabled */
2037 /* XXX: we may just stop the processor here, to allow debugging */
2038 excp = POWERPC_EXCP_RESET;
2039 goto excp_reset;
2040 }
2041 msr_ri = 0;
2042 msr_me = 0;
2043#if defined(TARGET_PPC64H)
2044 msr_hv = 1;
2045#endif
2046 /* XXX: should also have something loaded in DAR / DSISR */
2047 switch (excp_model) {
a750fc0b 2048 case POWERPC_EXCP_40x:
e1833e1f
JM		 2049 srr0 = SPR_40x_SRR2;
2050 srr1 = SPR_40x_SRR3;
c62db105 2051 break;
a750fc0b 2052 case POWERPC_EXCP_BOOKE:
e1833e1f
JM		 2053 srr0 = SPR_BOOKE_MCSRR0;
2054 srr1 = SPR_BOOKE_MCSRR1;
2055 asrr0 = SPR_BOOKE_CSRR0;
2056 asrr1 = SPR_BOOKE_CSRR1;
c62db105
JM		 2057 break;
2058 default:
2059 break;
2be0071f 2060 }
e1833e1f
JM		 2061 goto store_next;
2062 case POWERPC_EXCP_DSI: /* Data storage exception */
a541f297 2063#if defined (DEBUG_EXCEPTIONS)
4a057712 2064 if (loglevel != 0) {
1b9eb036
JM		 2065 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
2066 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
76a66253 2067 }
e1833e1f
JM		 2068#endif
2069 msr_ri = 0;
2070#if defined(TARGET_PPC64H)
2071 if (lpes1 == 0)
2072 msr_hv = 1;
a541f297
FB		 2073#endif
2074 goto store_next;
e1833e1f 2075 case POWERPC_EXCP_ISI: /* Instruction storage exception */
a541f297 2076#if defined (DEBUG_EXCEPTIONS)
76a66253 2077 if (loglevel != 0) {
1b9eb036
JM		 2078 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
2079 "\n", msr, env->nip);
76a66253 2080 }
a541f297 2081#endif
e1833e1f
JM		 2082 msr_ri = 0;
2083#if defined(TARGET_PPC64H)
2084 if (lpes1 == 0)
2085 msr_hv = 1;
2086#endif
2087 msr |= env->error_code;
9a64fbe4 2088 goto store_next;
e1833e1f
JM		 2089 case POWERPC_EXCP_EXTERNAL: /* External input */
2090 msr_ri = 0;
2091#if defined(TARGET_PPC64H)
2092 if (lpes0 == 1)
2093 msr_hv = 1;
2094#endif
9a64fbe4 2095 goto store_next;
e1833e1f
JM		 2096 case POWERPC_EXCP_ALIGN: /* Alignment exception */
2097 msr_ri = 0;
2098#if defined(TARGET_PPC64H)
2099 if (lpes1 == 0)
2100 msr_hv = 1;
2101#endif
2102 /* XXX: this is false */
2103 /* Get rS/rD and rA from faulting opcode */
2104 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
9a64fbe4 2105 goto store_current;
e1833e1f 2106 case POWERPC_EXCP_PROGRAM: /* Program exception */
9a64fbe4 2107 switch (env->error_code & ~0xF) {
e1833e1f
JM		 2108 case POWERPC_EXCP_FP:
2109 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
9a64fbe4 2110#if defined (DEBUG_EXCEPTIONS)
4a057712 2111 if (loglevel != 0) {
a496775f
JM		 2112 fprintf(logfile, "Ignore floating point exception\n");
2113 }
9a64fbe4
FB		 2114#endif
2115 return;
76a66253 2116 }
e1833e1f
JM		 2117 msr_ri = 0;
2118#if defined(TARGET_PPC64H)
2119 if (lpes1 == 0)
2120 msr_hv = 1;
2121#endif
9a64fbe4
FB		 2122 msr |= 0x00100000;
2123 /* Set FX */
2124 env->fpscr[7] |= 0x8;
2125 /* Finally, update FEX */
2126 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
2127 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
2128 env->fpscr[7] |= 0x4;
e1833e1f
JM		 2129 if (msr_fe0 != msr_fe1) {
2130 msr |= 0x00010000;
2131 goto store_current;
2132 }
76a66253 2133 break;
e1833e1f 2134 case POWERPC_EXCP_INVAL:
a496775f 2135#if defined (DEBUG_EXCEPTIONS)
4a057712 2136 if (loglevel != 0) {
a496775f
JM		 2137 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
2138 env->nip);
2139 }
e1833e1f
JM		 2140#endif
2141 msr_ri = 0;
2142#if defined(TARGET_PPC64H)
2143 if (lpes1 == 0)
2144 msr_hv = 1;
a496775f 2145#endif
9a64fbe4 2146 msr |= 0x00080000;
76a66253 2147 break;
e1833e1f
JM		 2148 case POWERPC_EXCP_PRIV:
2149 msr_ri = 0;
2150#if defined(TARGET_PPC64H)
2151 if (lpes1 == 0)
2152 msr_hv = 1;
2153#endif
9a64fbe4 2154 msr |= 0x00040000;
76a66253 2155 break;
e1833e1f
JM		 2156 case POWERPC_EXCP_TRAP:
2157 msr_ri = 0;
2158#if defined(TARGET_PPC64H)
2159 if (lpes1 == 0)
2160 msr_hv = 1;
2161#endif
9a64fbe4
FB		 2162 msr |= 0x00020000;
2163 break;
2164 default:
2165 /* Should never occur */
e1833e1f
JM		 2166 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2167 env->error_code);
76a66253
JM		 2168 break;
2169 }
9a64fbe4 2170 goto store_next;
e1833e1f
JM		 2171 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2172 msr_ri = 0;
2173#if defined(TARGET_PPC64H)
2174 if (lpes1 == 0)
2175 msr_hv = 1;
2176#endif
2177 goto store_current;
2178 case POWERPC_EXCP_SYSCALL: /* System call exception */
d094807b
FB		 2179 /* NOTE: this is a temporary hack to support graphics OSI
2180 calls from the MOL driver */
e1833e1f 2181 /* XXX: To be removed */
d094807b
FB		 2182 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2183 env->osi_call) {
2184 if (env->osi_call(env) != 0)
2185 return;
2186 }
b769d8fe 2187 if (loglevel & CPU_LOG_INT) {
d094807b 2188 dump_syscall(env);
b769d8fe 2189 }
e1833e1f
JM		 2190 msr_ri = 0;
2191#if defined(TARGET_PPC64H)
2192 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2193 msr_hv = 1;
2194#endif
2195 goto store_next;
2196 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2197 msr_ri = 0;
2198 goto store_current;
2199 case POWERPC_EXCP_DECR: /* Decrementer exception */
2200 msr_ri = 0;
2201#if defined(TARGET_PPC64H)
2202 if (lpes1 == 0)
2203 msr_hv = 1;
2204#endif
2205 goto store_next;
2206 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2207 /* FIT on 4xx */
2208#if defined (DEBUG_EXCEPTIONS)
2209 if (loglevel != 0)
2210 fprintf(logfile, "FIT exception\n");
2211#endif
2212 msr_ri = 0; /* XXX: check this */
9a64fbe4 2213 goto store_next;
e1833e1f
JM		 2214 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2215#if defined (DEBUG_EXCEPTIONS)
2216 if (loglevel != 0)
2217 fprintf(logfile, "WDT exception\n");
2218#endif
2219 switch (excp_model) {
2220 case POWERPC_EXCP_BOOKE:
2221 srr0 = SPR_BOOKE_CSRR0;
2222 srr1 = SPR_BOOKE_CSRR1;
2223 break;
2224 default:
2225 break;
2226 }
2227 msr_ri = 0; /* XXX: check this */
2be0071f 2228 goto store_next;
e1833e1f
JM		 2229 case POWERPC_EXCP_DTLB: /* Data TLB error */
2230 msr_ri = 0; /* XXX: check this */
2231 goto store_next;
2232 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2233 msr_ri = 0; /* XXX: check this */
2234 goto store_next;
2235 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2236 switch (excp_model) {
2237 case POWERPC_EXCP_BOOKE:
2238 srr0 = SPR_BOOKE_DSRR0;
2239 srr1 = SPR_BOOKE_DSRR1;
2240 asrr0 = SPR_BOOKE_CSRR0;
2241 asrr1 = SPR_BOOKE_CSRR1;
2242 break;
2243 default:
2244 break;
2245 }
2be0071f 2246 /* XXX: TODO */
e1833e1f 2247 cpu_abort(env, "Debug exception is not implemented yet !\n");
2be0071f 2248 goto store_next;
e1833e1f
JM		 2249#if defined(TARGET_PPCEMB)
2250 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2251 msr_ri = 0; /* XXX: check this */
2252 goto store_current;
2253 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2be0071f 2254 /* XXX: TODO */
e1833e1f 2255 cpu_abort(env, "Embedded floating point data exception "
2be0071f
FB		 2256 "is not implemented yet !\n");
2257 goto store_next;
e1833e1f 2258 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2be0071f 2259 /* XXX: TODO */
e1833e1f
JM		 2260 cpu_abort(env, "Embedded floating point round exception "
2261 "is not implemented yet !\n");
9a64fbe4 2262 goto store_next;
e1833e1f
JM		 2263 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2264 msr_ri = 0;
2be0071f
FB		 2265 /* XXX: TODO */
2266 cpu_abort(env,
e1833e1f 2267 "Performance counter exception is not implemented yet !\n");
9a64fbe4 2268 goto store_next;
e1833e1f 2269 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
76a66253 2270 /* XXX: TODO */
e1833e1f
JM		 2271 cpu_abort(env,
2272 "Embedded doorbell interrupt is not implemented yet !\n");
2be0071f 2273 goto store_next;
e1833e1f
JM		 2274 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2275 switch (excp_model) {
2276 case POWERPC_EXCP_BOOKE:
2277 srr0 = SPR_BOOKE_CSRR0;
2278 srr1 = SPR_BOOKE_CSRR1;
a750fc0b 2279 break;
2be0071f 2280 default:
2be0071f
FB		 2281 break;
2282 }
e1833e1f
JM		 2283 /* XXX: TODO */
2284 cpu_abort(env, "Embedded doorbell critical interrupt "
2285 "is not implemented yet !\n");
2286 goto store_next;
2287#endif /* defined(TARGET_PPCEMB) */
2288 case POWERPC_EXCP_RESET: /* System reset exception */
2289 msr_ri = 0;
2290#if defined(TARGET_PPC64H)
2291 msr_hv = 1;
2292#endif
2293 excp_reset:
2294 goto store_next;
2295#if defined(TARGET_PPC64)
2296 case POWERPC_EXCP_DSEG: /* Data segment exception */
2297 msr_ri = 0;
2298#if defined(TARGET_PPC64H)
2299 if (lpes1 == 0)
2300 msr_hv = 1;
2301#endif
e1833e1f
JM		 2302 goto store_next;
2303 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2304 msr_ri = 0;
2305#if defined(TARGET_PPC64H)
2306 if (lpes1 == 0)
2307 msr_hv = 1;
2308#endif
e1833e1f
JM		 2309 goto store_next;
2310#endif /* defined(TARGET_PPC64) */
2311#if defined(TARGET_PPC64H)
2312 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2313 srr0 = SPR_HSRR0;
2314 srr1 = SPR_HSSR1;
2315 msr_hv = 1;
2316 goto store_next;
2317#endif
2318 case POWERPC_EXCP_TRACE: /* Trace exception */
2319 msr_ri = 0;
2320#if defined(TARGET_PPC64H)
2321 if (lpes1 == 0)
2322 msr_hv = 1;
2323#endif
2324 goto store_next;
2325#if defined(TARGET_PPC64H)
2326 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2327 srr0 = SPR_HSRR0;
2328 srr1 = SPR_HSSR1;
2329 msr_hv = 1;
2330 goto store_next;
2331 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2332 srr0 = SPR_HSRR0;
2333 srr1 = SPR_HSSR1;
2334 msr_hv = 1;
2335 /* XXX: TODO */
2336 cpu_abort(env, "Hypervisor instruction storage exception "
2337 "is not implemented yet !\n");
2338 goto store_next;
2339 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2340 srr0 = SPR_HSRR0;
2341 srr1 = SPR_HSSR1;
2342 msr_hv = 1;
2343 goto store_next;
2344 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2345 srr0 = SPR_HSRR0;
2346 srr1 = SPR_HSSR1;
2347 msr_hv = 1;
2348 goto store_next;
2349#endif /* defined(TARGET_PPC64H) */
2350 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2351 msr_ri = 0;
2352#if defined(TARGET_PPC64H)
2353 if (lpes1 == 0)
2354 msr_hv = 1;
2355#endif
2356 goto store_current;
2357 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
a496775f 2358#if defined (DEBUG_EXCEPTIONS)
e1833e1f
JM		 2359 if (loglevel != 0)
2360 fprintf(logfile, "PIT exception\n");
2361#endif
2362 msr_ri = 0; /* XXX: check this */
2363 goto store_next;
2364 case POWERPC_EXCP_IO: /* IO error exception */
2365 /* XXX: TODO */
2366 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2367 goto store_next;
2368 case POWERPC_EXCP_RUNM: /* Run mode exception */
2369 /* XXX: TODO */
2370 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2371 goto store_next;
2372 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2373 /* XXX: TODO */
2374 cpu_abort(env, "602 emulation trap exception "
2375 "is not implemented yet !\n");
2376 goto store_next;
2377 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2378 msr_ri = 0; /* XXX: check this */
2379#if defined(TARGET_PPC64H) /* XXX: check this */
2380 if (lpes1 == 0)
2381 msr_hv = 1;
a496775f 2382#endif
e1833e1f 2383 switch (excp_model) {
a750fc0b
JM		 2384 case POWERPC_EXCP_602:
2385 case POWERPC_EXCP_603:
2386 case POWERPC_EXCP_603E:
2387 case POWERPC_EXCP_G2:
e1833e1f 2388 goto tlb_miss_tgpr;
a750fc0b 2389 case POWERPC_EXCP_7x5:
76a66253 2390 goto tlb_miss;
7dbe11ac
JM		 2391 case POWERPC_EXCP_74xx:
2392 goto tlb_miss_74xx;
2be0071f 2393 default:
e1833e1f 2394 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2be0071f
FB		 2395 break;
2396 }
e1833e1f
JM		 2397 break;
2398 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2399 msr_ri = 0; /* XXX: check this */
2400#if defined(TARGET_PPC64H) /* XXX: check this */
2401 if (lpes1 == 0)
2402 msr_hv = 1;
a496775f 2403#endif
e1833e1f 2404 switch (excp_model) {
a750fc0b
JM		 2405 case POWERPC_EXCP_602:
2406 case POWERPC_EXCP_603:
2407 case POWERPC_EXCP_603E:
2408 case POWERPC_EXCP_G2:
e1833e1f 2409 goto tlb_miss_tgpr;
a750fc0b 2410 case POWERPC_EXCP_7x5:
76a66253 2411 goto tlb_miss;
7dbe11ac
JM		 2412 case POWERPC_EXCP_74xx:
2413 goto tlb_miss_74xx;
2be0071f 2414 default:
e1833e1f 2415 cpu_abort(env, "Invalid data load TLB miss exception\n");
2be0071f
FB		 2416 break;
2417 }
e1833e1f
JM		 2418 break;
2419 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2420 msr_ri = 0; /* XXX: check this */
2421#if defined(TARGET_PPC64H) /* XXX: check this */
2422 if (lpes1 == 0)
2423 msr_hv = 1;
2424#endif
2425 switch (excp_model) {
a750fc0b
JM		 2426 case POWERPC_EXCP_602:
2427 case POWERPC_EXCP_603:
2428 case POWERPC_EXCP_603E:
2429 case POWERPC_EXCP_G2:
e1833e1f 2430 tlb_miss_tgpr:
76a66253
JM		 2431 /* Swap temporary saved registers with GPRs */
2432 swap_gpr_tgpr(env);
2433 msr_tgpr = 1;
e1833e1f
JM		 2434 goto tlb_miss;
2435 case POWERPC_EXCP_7x5:
2436 tlb_miss:
2be0071f
FB		 2437#if defined (DEBUG_SOFTWARE_TLB)
2438 if (loglevel != 0) {
76a66253
JM		 2439 const unsigned char *es;
2440 target_ulong *miss, *cmp;
2441 int en;
1e6784f9 2442 if (excp == POWERPC_EXCP_IFTLB) {
76a66253
JM		 2443 es = "I";
2444 en = 'I';
2445 miss = &env->spr[SPR_IMISS];
2446 cmp = &env->spr[SPR_ICMP];
2447 } else {
1e6784f9 2448 if (excp == POWERPC_EXCP_DLTLB)
76a66253
JM		 2449 es = "DL";
2450 else
2451 es = "DS";
2452 en = 'D';
2453 miss = &env->spr[SPR_DMISS];
2454 cmp = &env->spr[SPR_DCMP];
2455 }
1b9eb036 2456 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
4a057712 2457 " H1 " ADDRX " H2 " ADDRX " %08x\n",
1b9eb036 2458 es, en, *miss, en, *cmp,
76a66253 2459 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2be0071f
FB		 2460 env->error_code);
2461 }
9a64fbe4 2462#endif
2be0071f
FB		 2463 msr |= env->crf[0] << 28;
2464 msr |= env->error_code; /* key, D/I, S/L bits */
2465 /* Set way using a LRU mechanism */
76a66253 2466 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
c62db105 2467 break;
7dbe11ac
JM		 2468 case POWERPC_EXCP_74xx:
2469 tlb_miss_74xx:
2470#if defined (DEBUG_SOFTWARE_TLB)
2471 if (loglevel != 0) {
2472 const unsigned char *es;
2473 target_ulong *miss, *cmp;
2474 int en;
2475 if (excp == POWERPC_EXCP_IFTLB) {
2476 es = "I";
2477 en = 'I';
2478 miss = &env->spr[SPR_IMISS];
2479 cmp = &env->spr[SPR_ICMP];
2480 } else {
2481 if (excp == POWERPC_EXCP_DLTLB)
2482 es = "DL";
2483 else
2484 es = "DS";
2485 en = 'D';
2486 miss = &env->spr[SPR_TLBMISS];
2487 cmp = &env->spr[SPR_PTEHI];
2488 }
2489 fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2490 " %08x\n",
2491 es, en, *miss, en, *cmp, env->error_code);
2492 }
2493#endif
2494 msr |= env->error_code; /* key bit */
2495 break;
2be0071f 2496 default:
e1833e1f 2497 cpu_abort(env, "Invalid data store TLB miss exception\n");
2be0071f
FB		 2498 break;
2499 }
e1833e1f
JM		 2500 goto store_next;
2501 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2502 /* XXX: TODO */
2503 cpu_abort(env, "Floating point assist exception "
2504 "is not implemented yet !\n");
2505 goto store_next;
2506 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2507 /* XXX: TODO */
2508 cpu_abort(env, "IABR exception is not implemented yet !\n");
2509 goto store_next;
2510 case POWERPC_EXCP_SMI: /* System management interrupt */
2511 /* XXX: TODO */
2512 cpu_abort(env, "SMI exception is not implemented yet !\n");
2513 goto store_next;
2514 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2515 /* XXX: TODO */
2516 cpu_abort(env, "Thermal management exception "
2517 "is not implemented yet !\n");
2518 goto store_next;
2519 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2520 msr_ri = 0;
2521#if defined(TARGET_PPC64H)
2522 if (lpes1 == 0)
2523 msr_hv = 1;
2524#endif
2525 /* XXX: TODO */
2526 cpu_abort(env,
2527 "Performance counter exception is not implemented yet !\n");
2528 goto store_next;
2529 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2530 /* XXX: TODO */
2531 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2532 goto store_next;
2533 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2534 /* XXX: TODO */
2535 cpu_abort(env,
2536 "970 soft-patch exception is not implemented yet !\n");
2537 goto store_next;
2538 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2539 /* XXX: TODO */
2540 cpu_abort(env,
2541 "970 maintenance exception is not implemented yet !\n");
2542 goto store_next;
2be0071f 2543 default:
e1833e1f
JM		 2544 excp_invalid:
2545 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2546 break;
9a64fbe4 2547 store_current:
2be0071f 2548 /* save current instruction location */
e1833e1f 2549 env->spr[srr0] = env->nip - 4;
9a64fbe4
FB		 2550 break;
2551 store_next:
2be0071f 2552 /* save next instruction location */
e1833e1f 2553 env->spr[srr0] = env->nip;
9a64fbe4
FB		 2554 break;
2555 }
e1833e1f
JM		 2556 /* Save MSR */
2557 env->spr[srr1] = msr;
2558 /* If any alternate SRR register are defined, duplicate saved values */
2559 if (asrr0 != -1)
2560 env->spr[asrr0] = env->spr[srr0];
2561 if (asrr1 != -1)
2562 env->spr[asrr1] = env->spr[srr1];
2be0071f 2563 /* If we disactivated any translation, flush TLBs */
e1833e1f 2564 if (msr_ir || msr_dr)
2be0071f 2565 tlb_flush(env, 1);
9a64fbe4 2566 /* reload MSR with correct bits */
9a64fbe4
FB		 2567 msr_ee = 0;
2568 msr_pr = 0;
2569 msr_fp = 0;
2570 msr_fe0 = 0;
2571 msr_se = 0;
2572 msr_be = 0;
2573 msr_fe1 = 0;
2574 msr_ir = 0;
2575 msr_dr = 0;
e1833e1f
JM		 2576#if 0 /* Fix this: not on all targets */
2577 msr_pmm = 0;
2578#endif
9a64fbe4 2579 msr_le = msr_ile;
e1833e1f
JM		 2580 do_compute_hflags(env);
2581 /* Jump to handler */
2582 vector = env->excp_vectors[excp];
2583 if (vector == (target_ulong)-1) {
2584 cpu_abort(env, "Raised an exception without defined vector %d\n",
2585 excp);
2586 }
2587 vector |= env->excp_prefix;
c62db105 2588#if defined(TARGET_PPC64)
e1833e1f
JM		 2589 if (excp_model == POWERPC_EXCP_BOOKE) {
2590 msr_cm = msr_icm;
2591 if (!msr_cm)
2592 vector = (uint32_t)vector;
c62db105
JM		 2593 } else {
2594 msr_sf = msr_isf;
e1833e1f
JM		 2595 if (!msr_sf)
2596 vector = (uint32_t)vector;
c62db105 2597 }
e1833e1f
JM		 2598#endif
2599 env->nip = vector;
2600 /* Reset exception state */
2601 env->exception_index = POWERPC_EXCP_NONE;
2602 env->error_code = 0;
fb0eaffc 2603}
47103572 2604
e1833e1f 2605void do_interrupt (CPUState *env)
47103572 2606{
e1833e1f
JM		 2607 powerpc_excp(env, env->excp_model, env->exception_index);
2608}
47103572 2609
e1833e1f
JM		 2610void ppc_hw_interrupt (CPUPPCState *env)
2611{
a496775f
JM		 2612#if 1
2613 if (loglevel & CPU_LOG_INT) {
2614 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2615 __func__, env, env->pending_interrupts,
2616 env->interrupt_request, msr_me, msr_ee);
2617 }
47103572 2618#endif
e1833e1f 2619 /* External reset */
47103572 2620 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
47103572 2621 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
e1833e1f
JM		 2622 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2623 return;
2624 }
2625 /* Machine check exception */
2626 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2627 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2628 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2629 return;
47103572 2630 }
e1833e1f
JM		 2631#if 0 /* TODO */
2632 /* External debug exception */
2633 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2634 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2635 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2636 return;
2637 }
2638#endif
2639#if defined(TARGET_PPC64H)
2640 if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) {
47103572
JM		 2641 /* Hypervisor decrementer exception */
2642 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
47103572 2643 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
e1833e1f
JM		 2644 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2645 return;
2646 }
2647 }
2648#endif
2649 if (msr_ce != 0) {
2650 /* External critical interrupt */
2651 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2652 /* Taking a critical external interrupt does not clear the external
2653 * critical interrupt status
2654 */
2655#if 0
2656 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
47103572 2657#endif
e1833e1f
JM		 2658 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2659 return;
2660 }
2661 }
2662 if (msr_ee != 0) {
2663 /* Watchdog timer on embedded PowerPC */
2664 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2665 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2666 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2667 return;
2668 }
2669#if defined(TARGET_PPCEMB)
2670 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2671 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2672 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2673 return;
2674 }
2675#endif
2676#if defined(TARGET_PPCEMB)
2677 /* External interrupt */
2678 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2679 /* Taking an external interrupt does not clear the external
2680 * interrupt status
2681 */
2682#if 0
2683 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2684#endif
2685 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2686 return;
2687 }
2688#endif
2689 /* Fixed interval timer on embedded PowerPC */
2690 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2691 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2692 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2693 return;
2694 }
2695 /* Programmable interval timer on embedded PowerPC */
2696 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2697 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2698 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2699 return;
2700 }
47103572
JM		 2701 /* Decrementer exception */
2702 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
47103572 2703 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
e1833e1f
JM		 2704 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2705 return;
2706 }
2707#if !defined(TARGET_PPCEMB)
47103572 2708 /* External interrupt */
e1833e1f 2709 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
e9df014c
JM		 2710 /* Taking an external interrupt does not clear the external
2711 * interrupt status
2712 */
2713#if 0
47103572 2714 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
e9df014c 2715#endif
e1833e1f
JM		 2716 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2717 return;
2718 }
d0dfae6e 2719#endif
e1833e1f
JM		 2720#if defined(TARGET_PPCEMB)
2721 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2722 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2723 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2724 return;
47103572 2725 }
47103572 2726#endif
e1833e1f
JM		 2727 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2728 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2729 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2730 return;
2731 }
2732 /* Thermal interrupt */
2733 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2734 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2735 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2736 return;
2737 }
47103572 2738 }
47103572 2739}
18fba28c 2740#endif /* !CONFIG_USER_ONLY */
a496775f
JM		 2741
2742void cpu_dump_EA (target_ulong EA)
2743{
2744 FILE *f;
2745
2746 if (logfile) {
2747 f = logfile;
2748 } else {
2749 f = stdout;
2750 return;
2751 }
4a057712
JM		 2752 fprintf(f, "Memory access at address " ADDRX "\n", EA);
2753}
2754
2755void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2756{
2757 FILE *f;
2758
2759 if (logfile) {
2760 f = logfile;
2761 } else {
2762 f = stdout;
2763 return;
2764 }
2765 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2766 RA, msr);
a496775f
JM		 2767}
2768
0a032cbe
JM		 2769void cpu_ppc_reset (void *opaque)
2770{
2771 CPUPPCState *env;
5eb7995e 2772 int i;
0a032cbe
JM		 2773
2774 env = opaque;
5eb7995e
JM		 2775 /* XXX: some of those flags initialisation values could depend
2776 * on the actual PowerPC implementation
2777 */
2778 for (i = 0; i < 63; i++)
2779 env->msr[i] = 0;
2780#if defined(TARGET_PPC64)
2781 msr_hv = 0; /* Should be 1... */
2782#endif
2783 msr_ap = 0; /* TO BE CHECKED */
2784 msr_sa = 0; /* TO BE CHECKED */
2785 msr_ip = 0; /* TO BE CHECKED */
0a032cbe
JM		 2786#if defined (DO_SINGLE_STEP) && 0
2787 /* Single step trace mode */
2788 msr_se = 1;
2789 msr_be = 1;
0a032cbe
JM		 2790#endif
2791#if defined(CONFIG_USER_ONLY)
5eb7995e 2792 msr_fp = 1; /* Allow floating point exceptions */
0a032cbe 2793 msr_pr = 1;
fe33cc71 2794#else
1c27f8fb 2795 env->nip = env->hreset_vector | env->excp_prefix;
0a032cbe
JM		 2796 ppc_tlb_invalidate_all(env);
2797#endif
2798 do_compute_hflags(env);
2799 env->reserve = -1;
5eb7995e
JM		 2800 /* Be sure no exception or interrupt is pending */
2801 env->pending_interrupts = 0;
e1833e1f
JM		 2802 env->exception_index = POWERPC_EXCP_NONE;
2803 env->error_code = 0;
5eb7995e
JM		 2804 /* Flush all TLBs */
2805 tlb_flush(env, 1);
0a032cbe
JM		 2806}
2807
2808CPUPPCState *cpu_ppc_init (void)
2809{
2810 CPUPPCState *env;
2811
2812 env = qemu_mallocz(sizeof(CPUPPCState));
2813 if (!env)
2814 return NULL;
2815 cpu_exec_init(env);
0a032cbe
JM		 2816
2817 return env;
2818}
2819
2820void cpu_ppc_close (CPUPPCState *env)
2821{
2822 /* Should also remove all opcode tables... */
2823 free(env);
2824}
Qemu copy for testing