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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation helpers for qemu. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
79aceca5 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
fdabc366 FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <signal.h> | |
26 | #include <assert.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
0411a972 | 30 | #include "helper_regs.h" |
9a64fbe4 FB |
31 | |
32 | //#define DEBUG_MMU | |
33 | //#define DEBUG_BATS | |
76a66253 | 34 | //#define DEBUG_SOFTWARE_TLB |
0411a972 | 35 | //#define DUMP_PAGE_TABLES |
9a64fbe4 | 36 | //#define DEBUG_EXCEPTIONS |
fdabc366 | 37 | //#define FLUSH_ALL_TLBS |
9a64fbe4 | 38 | |
9a64fbe4 | 39 | /*****************************************************************************/ |
3fc6c082 | 40 | /* PowerPC MMU emulation */ |
a541f297 | 41 | |
d9bce9d9 | 42 | #if defined(CONFIG_USER_ONLY) |
e96efcfc | 43 | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 44 | int mmu_idx, int is_softmmu) |
24741ef3 FB |
45 | { |
46 | int exception, error_code; | |
d9bce9d9 | 47 | |
24741ef3 | 48 | if (rw == 2) { |
e1833e1f | 49 | exception = POWERPC_EXCP_ISI; |
8f793433 | 50 | error_code = 0x40000000; |
24741ef3 | 51 | } else { |
e1833e1f | 52 | exception = POWERPC_EXCP_DSI; |
8f793433 | 53 | error_code = 0x40000000; |
24741ef3 FB |
54 | if (rw) |
55 | error_code |= 0x02000000; | |
56 | env->spr[SPR_DAR] = address; | |
57 | env->spr[SPR_DSISR] = error_code; | |
58 | } | |
59 | env->exception_index = exception; | |
60 | env->error_code = error_code; | |
76a66253 | 61 | |
24741ef3 FB |
62 | return 1; |
63 | } | |
76a66253 | 64 | |
9b3c35e0 | 65 | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
24741ef3 FB |
66 | { |
67 | return addr; | |
68 | } | |
36081602 | 69 | |
24741ef3 | 70 | #else |
76a66253 | 71 | /* Common routines used by software and hardware TLBs emulation */ |
b068d6a7 | 72 | static always_inline int pte_is_valid (target_ulong pte0) |
76a66253 JM |
73 | { |
74 | return pte0 & 0x80000000 ? 1 : 0; | |
75 | } | |
76 | ||
b068d6a7 | 77 | static always_inline void pte_invalidate (target_ulong *pte0) |
76a66253 JM |
78 | { |
79 | *pte0 &= ~0x80000000; | |
80 | } | |
81 | ||
caa4039c | 82 | #if defined(TARGET_PPC64) |
b068d6a7 | 83 | static always_inline int pte64_is_valid (target_ulong pte0) |
caa4039c JM |
84 | { |
85 | return pte0 & 0x0000000000000001ULL ? 1 : 0; | |
86 | } | |
87 | ||
b068d6a7 | 88 | static always_inline void pte64_invalidate (target_ulong *pte0) |
caa4039c JM |
89 | { |
90 | *pte0 &= ~0x0000000000000001ULL; | |
91 | } | |
92 | #endif | |
93 | ||
76a66253 JM |
94 | #define PTE_PTEM_MASK 0x7FFFFFBF |
95 | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) | |
caa4039c JM |
96 | #if defined(TARGET_PPC64) |
97 | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL | |
98 | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) | |
99 | #endif | |
76a66253 | 100 | |
b227a8e9 JM |
101 | static always_inline int pp_check (int key, int pp, int nx) |
102 | { | |
103 | int access; | |
104 | ||
105 | /* Compute access rights */ | |
106 | /* When pp is 3/7, the result is undefined. Set it to noaccess */ | |
107 | access = 0; | |
108 | if (key == 0) { | |
109 | switch (pp) { | |
110 | case 0x0: | |
111 | case 0x1: | |
112 | case 0x2: | |
113 | access |= PAGE_WRITE; | |
114 | /* No break here */ | |
115 | case 0x3: | |
116 | case 0x6: | |
117 | access |= PAGE_READ; | |
118 | break; | |
119 | } | |
120 | } else { | |
121 | switch (pp) { | |
122 | case 0x0: | |
123 | case 0x6: | |
124 | access = 0; | |
125 | break; | |
126 | case 0x1: | |
127 | case 0x3: | |
128 | access = PAGE_READ; | |
129 | break; | |
130 | case 0x2: | |
131 | access = PAGE_READ | PAGE_WRITE; | |
132 | break; | |
133 | } | |
134 | } | |
135 | if (nx == 0) | |
136 | access |= PAGE_EXEC; | |
137 | ||
138 | return access; | |
139 | } | |
140 | ||
141 | static always_inline int check_prot (int prot, int rw, int access_type) | |
142 | { | |
143 | int ret; | |
144 | ||
145 | if (access_type == ACCESS_CODE) { | |
146 | if (prot & PAGE_EXEC) | |
147 | ret = 0; | |
148 | else | |
149 | ret = -2; | |
150 | } else if (rw) { | |
151 | if (prot & PAGE_WRITE) | |
152 | ret = 0; | |
153 | else | |
154 | ret = -2; | |
155 | } else { | |
156 | if (prot & PAGE_READ) | |
157 | ret = 0; | |
158 | else | |
159 | ret = -2; | |
160 | } | |
161 | ||
162 | return ret; | |
163 | } | |
164 | ||
b068d6a7 JM |
165 | static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
166 | target_ulong pte0, target_ulong pte1, | |
b227a8e9 | 167 | int h, int rw, int type) |
76a66253 | 168 | { |
caa4039c | 169 | target_ulong ptem, mmask; |
b227a8e9 | 170 | int access, ret, pteh, ptev, pp; |
76a66253 JM |
171 | |
172 | access = 0; | |
173 | ret = -1; | |
174 | /* Check validity and table match */ | |
caa4039c JM |
175 | #if defined(TARGET_PPC64) |
176 | if (is_64b) { | |
177 | ptev = pte64_is_valid(pte0); | |
178 | pteh = (pte0 >> 1) & 1; | |
179 | } else | |
180 | #endif | |
181 | { | |
182 | ptev = pte_is_valid(pte0); | |
183 | pteh = (pte0 >> 6) & 1; | |
184 | } | |
185 | if (ptev && h == pteh) { | |
76a66253 | 186 | /* Check vsid & api */ |
caa4039c JM |
187 | #if defined(TARGET_PPC64) |
188 | if (is_64b) { | |
189 | ptem = pte0 & PTE64_PTEM_MASK; | |
190 | mmask = PTE64_CHECK_MASK; | |
b227a8e9 JM |
191 | pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
192 | ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */ | |
193 | ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ | |
caa4039c JM |
194 | } else |
195 | #endif | |
196 | { | |
197 | ptem = pte0 & PTE_PTEM_MASK; | |
198 | mmask = PTE_CHECK_MASK; | |
b227a8e9 | 199 | pp = pte1 & 0x00000003; |
caa4039c JM |
200 | } |
201 | if (ptem == ctx->ptem) { | |
76a66253 JM |
202 | if (ctx->raddr != (target_ulong)-1) { |
203 | /* all matches should have equal RPN, WIMG & PP */ | |
caa4039c JM |
204 | if ((ctx->raddr & mmask) != (pte1 & mmask)) { |
205 | if (loglevel != 0) | |
76a66253 JM |
206 | fprintf(logfile, "Bad RPN/WIMG/PP\n"); |
207 | return -3; | |
208 | } | |
209 | } | |
210 | /* Compute access rights */ | |
b227a8e9 | 211 | access = pp_check(ctx->key, pp, ctx->nx); |
76a66253 JM |
212 | /* Keep the matching PTE informations */ |
213 | ctx->raddr = pte1; | |
214 | ctx->prot = access; | |
b227a8e9 JM |
215 | ret = check_prot(ctx->prot, rw, type); |
216 | if (ret == 0) { | |
76a66253 JM |
217 | /* Access granted */ |
218 | #if defined (DEBUG_MMU) | |
4a057712 | 219 | if (loglevel != 0) |
76a66253 JM |
220 | fprintf(logfile, "PTE access granted !\n"); |
221 | #endif | |
76a66253 JM |
222 | } else { |
223 | /* Access right violation */ | |
224 | #if defined (DEBUG_MMU) | |
4a057712 | 225 | if (loglevel != 0) |
76a66253 JM |
226 | fprintf(logfile, "PTE access rejected\n"); |
227 | #endif | |
76a66253 JM |
228 | } |
229 | } | |
230 | } | |
231 | ||
232 | return ret; | |
233 | } | |
234 | ||
a11b8151 JM |
235 | static always_inline int pte32_check (mmu_ctx_t *ctx, |
236 | target_ulong pte0, target_ulong pte1, | |
237 | int h, int rw, int type) | |
caa4039c | 238 | { |
b227a8e9 | 239 | return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
caa4039c JM |
240 | } |
241 | ||
242 | #if defined(TARGET_PPC64) | |
a11b8151 JM |
243 | static always_inline int pte64_check (mmu_ctx_t *ctx, |
244 | target_ulong pte0, target_ulong pte1, | |
245 | int h, int rw, int type) | |
caa4039c | 246 | { |
b227a8e9 | 247 | return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
caa4039c JM |
248 | } |
249 | #endif | |
250 | ||
a11b8151 JM |
251 | static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
252 | int ret, int rw) | |
76a66253 JM |
253 | { |
254 | int store = 0; | |
255 | ||
256 | /* Update page flags */ | |
257 | if (!(*pte1p & 0x00000100)) { | |
258 | /* Update accessed flag */ | |
259 | *pte1p |= 0x00000100; | |
260 | store = 1; | |
261 | } | |
262 | if (!(*pte1p & 0x00000080)) { | |
263 | if (rw == 1 && ret == 0) { | |
264 | /* Update changed flag */ | |
265 | *pte1p |= 0x00000080; | |
266 | store = 1; | |
267 | } else { | |
268 | /* Force page fault for first write access */ | |
269 | ctx->prot &= ~PAGE_WRITE; | |
270 | } | |
271 | } | |
272 | ||
273 | return store; | |
274 | } | |
275 | ||
276 | /* Software driven TLB helpers */ | |
a11b8151 JM |
277 | static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
278 | int way, int is_code) | |
76a66253 JM |
279 | { |
280 | int nr; | |
281 | ||
282 | /* Select TLB num in a way from address */ | |
283 | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1); | |
284 | /* Select TLB way */ | |
285 | nr += env->tlb_per_way * way; | |
286 | /* 6xx have separate TLBs for instructions and data */ | |
287 | if (is_code && env->id_tlbs == 1) | |
288 | nr += env->nb_tlb; | |
289 | ||
290 | return nr; | |
291 | } | |
292 | ||
a11b8151 | 293 | static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env) |
76a66253 | 294 | { |
1d0a48fb | 295 | ppc6xx_tlb_t *tlb; |
76a66253 JM |
296 | int nr, max; |
297 | ||
298 | #if defined (DEBUG_SOFTWARE_TLB) && 0 | |
299 | if (loglevel != 0) { | |
300 | fprintf(logfile, "Invalidate all TLBs\n"); | |
301 | } | |
302 | #endif | |
303 | /* Invalidate all defined software TLB */ | |
304 | max = env->nb_tlb; | |
305 | if (env->id_tlbs == 1) | |
306 | max *= 2; | |
307 | for (nr = 0; nr < max; nr++) { | |
1d0a48fb | 308 | tlb = &env->tlb[nr].tlb6; |
76a66253 JM |
309 | pte_invalidate(&tlb->pte0); |
310 | } | |
76a66253 | 311 | tlb_flush(env, 1); |
76a66253 JM |
312 | } |
313 | ||
b068d6a7 JM |
314 | static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
315 | target_ulong eaddr, | |
316 | int is_code, | |
317 | int match_epn) | |
76a66253 | 318 | { |
4a057712 | 319 | #if !defined(FLUSH_ALL_TLBS) |
1d0a48fb | 320 | ppc6xx_tlb_t *tlb; |
76a66253 JM |
321 | int way, nr; |
322 | ||
76a66253 JM |
323 | /* Invalidate ITLB + DTLB, all ways */ |
324 | for (way = 0; way < env->nb_ways; way++) { | |
325 | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); | |
1d0a48fb | 326 | tlb = &env->tlb[nr].tlb6; |
76a66253 JM |
327 | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
328 | #if defined (DEBUG_SOFTWARE_TLB) | |
329 | if (loglevel != 0) { | |
1b9eb036 | 330 | fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n", |
76a66253 JM |
331 | nr, env->nb_tlb, eaddr); |
332 | } | |
333 | #endif | |
334 | pte_invalidate(&tlb->pte0); | |
335 | tlb_flush_page(env, tlb->EPN); | |
336 | } | |
337 | } | |
338 | #else | |
339 | /* XXX: PowerPC specification say this is valid as well */ | |
340 | ppc6xx_tlb_invalidate_all(env); | |
341 | #endif | |
342 | } | |
343 | ||
a11b8151 JM |
344 | static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env, |
345 | target_ulong eaddr, | |
346 | int is_code) | |
76a66253 JM |
347 | { |
348 | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0); | |
349 | } | |
350 | ||
351 | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, | |
352 | target_ulong pte0, target_ulong pte1) | |
353 | { | |
1d0a48fb | 354 | ppc6xx_tlb_t *tlb; |
76a66253 JM |
355 | int nr; |
356 | ||
357 | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); | |
1d0a48fb | 358 | tlb = &env->tlb[nr].tlb6; |
76a66253 JM |
359 | #if defined (DEBUG_SOFTWARE_TLB) |
360 | if (loglevel != 0) { | |
5fafdf24 | 361 | fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
1b9eb036 | 362 | " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
76a66253 JM |
363 | } |
364 | #endif | |
365 | /* Invalidate any pending reference in Qemu for this virtual address */ | |
366 | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1); | |
367 | tlb->pte0 = pte0; | |
368 | tlb->pte1 = pte1; | |
369 | tlb->EPN = EPN; | |
76a66253 JM |
370 | /* Store last way for LRU mechanism */ |
371 | env->last_way = way; | |
372 | } | |
373 | ||
a11b8151 JM |
374 | static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
375 | target_ulong eaddr, int rw, | |
376 | int access_type) | |
76a66253 | 377 | { |
1d0a48fb | 378 | ppc6xx_tlb_t *tlb; |
76a66253 JM |
379 | int nr, best, way; |
380 | int ret; | |
d9bce9d9 | 381 | |
76a66253 JM |
382 | best = -1; |
383 | ret = -1; /* No TLB found */ | |
384 | for (way = 0; way < env->nb_ways; way++) { | |
385 | nr = ppc6xx_tlb_getnum(env, eaddr, way, | |
386 | access_type == ACCESS_CODE ? 1 : 0); | |
1d0a48fb | 387 | tlb = &env->tlb[nr].tlb6; |
76a66253 JM |
388 | /* This test "emulates" the PTE index match for hardware TLBs */ |
389 | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { | |
390 | #if defined (DEBUG_SOFTWARE_TLB) | |
391 | if (loglevel != 0) { | |
1b9eb036 JM |
392 | fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX |
393 | "] <> " ADDRX "\n", | |
76a66253 JM |
394 | nr, env->nb_tlb, |
395 | pte_is_valid(tlb->pte0) ? "valid" : "inval", | |
396 | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); | |
397 | } | |
398 | #endif | |
399 | continue; | |
400 | } | |
401 | #if defined (DEBUG_SOFTWARE_TLB) | |
402 | if (loglevel != 0) { | |
1b9eb036 JM |
403 | fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
404 | " %c %c\n", | |
76a66253 JM |
405 | nr, env->nb_tlb, |
406 | pte_is_valid(tlb->pte0) ? "valid" : "inval", | |
407 | tlb->EPN, eaddr, tlb->pte1, | |
408 | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); | |
409 | } | |
410 | #endif | |
b227a8e9 | 411 | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
76a66253 JM |
412 | case -3: |
413 | /* TLB inconsistency */ | |
414 | return -1; | |
415 | case -2: | |
416 | /* Access violation */ | |
417 | ret = -2; | |
418 | best = nr; | |
419 | break; | |
420 | case -1: | |
421 | default: | |
422 | /* No match */ | |
423 | break; | |
424 | case 0: | |
425 | /* access granted */ | |
426 | /* XXX: we should go on looping to check all TLBs consistency | |
427 | * but we can speed-up the whole thing as the | |
428 | * result would be undefined if TLBs are not consistent. | |
429 | */ | |
430 | ret = 0; | |
431 | best = nr; | |
432 | goto done; | |
433 | } | |
434 | } | |
435 | if (best != -1) { | |
436 | done: | |
437 | #if defined (DEBUG_SOFTWARE_TLB) | |
4a057712 | 438 | if (loglevel != 0) { |
76a66253 JM |
439 | fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n", |
440 | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); | |
441 | } | |
442 | #endif | |
443 | /* Update page flags */ | |
1d0a48fb | 444 | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
76a66253 JM |
445 | } |
446 | ||
447 | return ret; | |
448 | } | |
449 | ||
9a64fbe4 | 450 | /* Perform BAT hit & translation */ |
faadf50e JM |
451 | static always_inline void bat_size_prot (CPUState *env, target_ulong *blp, |
452 | int *validp, int *protp, | |
453 | target_ulong *BATu, target_ulong *BATl) | |
454 | { | |
455 | target_ulong bl; | |
456 | int pp, valid, prot; | |
457 | ||
458 | bl = (*BATu & 0x00001FFC) << 15; | |
459 | valid = 0; | |
460 | prot = 0; | |
461 | if (((msr_pr == 0) && (*BATu & 0x00000002)) || | |
462 | ((msr_pr != 0) && (*BATu & 0x00000001))) { | |
463 | valid = 1; | |
464 | pp = *BATl & 0x00000003; | |
465 | if (pp != 0) { | |
466 | prot = PAGE_READ | PAGE_EXEC; | |
467 | if (pp == 0x2) | |
468 | prot |= PAGE_WRITE; | |
469 | } | |
470 | } | |
471 | *blp = bl; | |
472 | *validp = valid; | |
473 | *protp = prot; | |
474 | } | |
475 | ||
476 | static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp, | |
477 | int *validp, int *protp, | |
478 | target_ulong *BATu, | |
479 | target_ulong *BATl) | |
480 | { | |
481 | target_ulong bl; | |
482 | int key, pp, valid, prot; | |
483 | ||
484 | bl = (*BATl & 0x0000003F) << 17; | |
485 | if (loglevel != 0) { | |
486 | fprintf(logfile, "b %02x ==> bl %08x msk %08x\n", | |
487 | *BATl & 0x0000003F, bl, ~bl); | |
488 | } | |
489 | prot = 0; | |
490 | valid = (*BATl >> 6) & 1; | |
491 | if (valid) { | |
492 | pp = *BATu & 0x00000003; | |
493 | if (msr_pr == 0) | |
494 | key = (*BATu >> 3) & 1; | |
495 | else | |
496 | key = (*BATu >> 2) & 1; | |
497 | prot = pp_check(key, pp, 0); | |
498 | } | |
499 | *blp = bl; | |
500 | *validp = valid; | |
501 | *protp = prot; | |
502 | } | |
503 | ||
a11b8151 JM |
504 | static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, |
505 | target_ulong virtual, int rw, int type) | |
9a64fbe4 | 506 | { |
76a66253 JM |
507 | target_ulong *BATlt, *BATut, *BATu, *BATl; |
508 | target_ulong base, BEPIl, BEPIu, bl; | |
faadf50e | 509 | int i, valid, prot; |
9a64fbe4 FB |
510 | int ret = -1; |
511 | ||
512 | #if defined (DEBUG_BATS) | |
4a057712 | 513 | if (loglevel != 0) { |
1b9eb036 | 514 | fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__, |
76a66253 | 515 | type == ACCESS_CODE ? 'I' : 'D', virtual); |
9a64fbe4 | 516 | } |
9a64fbe4 FB |
517 | #endif |
518 | switch (type) { | |
519 | case ACCESS_CODE: | |
520 | BATlt = env->IBAT[1]; | |
521 | BATut = env->IBAT[0]; | |
522 | break; | |
523 | default: | |
524 | BATlt = env->DBAT[1]; | |
525 | BATut = env->DBAT[0]; | |
526 | break; | |
527 | } | |
528 | #if defined (DEBUG_BATS) | |
4a057712 | 529 | if (loglevel != 0) { |
1b9eb036 | 530 | fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__, |
76a66253 | 531 | type == ACCESS_CODE ? 'I' : 'D', virtual); |
9a64fbe4 | 532 | } |
9a64fbe4 FB |
533 | #endif |
534 | base = virtual & 0xFFFC0000; | |
faadf50e | 535 | for (i = 0; i < env->nb_BATs; i++) { |
9a64fbe4 FB |
536 | BATu = &BATut[i]; |
537 | BATl = &BATlt[i]; | |
538 | BEPIu = *BATu & 0xF0000000; | |
539 | BEPIl = *BATu & 0x0FFE0000; | |
faadf50e JM |
540 | if (unlikely(env->mmu_model == POWERPC_MMU_601)) { |
541 | bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl); | |
542 | } else { | |
543 | bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); | |
544 | } | |
9a64fbe4 | 545 | #if defined (DEBUG_BATS) |
4a057712 | 546 | if (loglevel != 0) { |
5fafdf24 | 547 | fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
1b9eb036 | 548 | " BATl 0x" ADDRX "\n", |
9a64fbe4 FB |
549 | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
550 | *BATu, *BATl); | |
9a64fbe4 FB |
551 | } |
552 | #endif | |
553 | if ((virtual & 0xF0000000) == BEPIu && | |
554 | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) { | |
555 | /* BAT matches */ | |
faadf50e | 556 | if (valid != 0) { |
9a64fbe4 | 557 | /* Get physical address */ |
76a66253 | 558 | ctx->raddr = (*BATl & 0xF0000000) | |
9a64fbe4 | 559 | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
a541f297 | 560 | (virtual & 0x0001F000); |
b227a8e9 | 561 | /* Compute access rights */ |
faadf50e | 562 | ctx->prot = prot; |
b227a8e9 | 563 | ret = check_prot(ctx->prot, rw, type); |
9a64fbe4 | 564 | #if defined (DEBUG_BATS) |
b227a8e9 | 565 | if (ret == 0 && loglevel != 0) { |
4a057712 | 566 | fprintf(logfile, "BAT %d match: r 0x" PADDRX |
1b9eb036 | 567 | " prot=%c%c\n", |
76a66253 JM |
568 | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
569 | ctx->prot & PAGE_WRITE ? 'W' : '-'); | |
9a64fbe4 FB |
570 | } |
571 | #endif | |
9a64fbe4 FB |
572 | break; |
573 | } | |
574 | } | |
575 | } | |
576 | if (ret < 0) { | |
577 | #if defined (DEBUG_BATS) | |
4a057712 JM |
578 | if (loglevel != 0) { |
579 | fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual); | |
580 | for (i = 0; i < 4; i++) { | |
581 | BATu = &BATut[i]; | |
582 | BATl = &BATlt[i]; | |
583 | BEPIu = *BATu & 0xF0000000; | |
584 | BEPIl = *BATu & 0x0FFE0000; | |
585 | bl = (*BATu & 0x00001FFC) << 15; | |
586 | fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX | |
587 | " BATl 0x" ADDRX " \n\t" | |
588 | "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n", | |
589 | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, | |
590 | *BATu, *BATl, BEPIu, BEPIl, bl); | |
591 | } | |
9a64fbe4 FB |
592 | } |
593 | #endif | |
9a64fbe4 | 594 | } |
b227a8e9 | 595 | |
9a64fbe4 FB |
596 | /* No hit */ |
597 | return ret; | |
598 | } | |
599 | ||
600 | /* PTE table lookup */ | |
b227a8e9 JM |
601 | static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, |
602 | int rw, int type) | |
9a64fbe4 | 603 | { |
76a66253 JM |
604 | target_ulong base, pte0, pte1; |
605 | int i, good = -1; | |
caa4039c | 606 | int ret, r; |
9a64fbe4 | 607 | |
76a66253 JM |
608 | ret = -1; /* No entry found */ |
609 | base = ctx->pg_addr[h]; | |
9a64fbe4 | 610 | for (i = 0; i < 8; i++) { |
caa4039c JM |
611 | #if defined(TARGET_PPC64) |
612 | if (is_64b) { | |
613 | pte0 = ldq_phys(base + (i * 16)); | |
614 | pte1 = ldq_phys(base + (i * 16) + 8); | |
b227a8e9 | 615 | r = pte64_check(ctx, pte0, pte1, h, rw, type); |
12de9a39 JM |
616 | #if defined (DEBUG_MMU) |
617 | if (loglevel != 0) { | |
618 | fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX | |
619 | " 0x" ADDRX " %d %d %d 0x" ADDRX "\n", | |
620 | base + (i * 16), pte0, pte1, | |
621 | (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), | |
622 | ctx->ptem); | |
623 | } | |
624 | #endif | |
caa4039c JM |
625 | } else |
626 | #endif | |
627 | { | |
628 | pte0 = ldl_phys(base + (i * 8)); | |
629 | pte1 = ldl_phys(base + (i * 8) + 4); | |
b227a8e9 | 630 | r = pte32_check(ctx, pte0, pte1, h, rw, type); |
9a64fbe4 | 631 | #if defined (DEBUG_MMU) |
12de9a39 JM |
632 | if (loglevel != 0) { |
633 | fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX | |
634 | " 0x" ADDRX " %d %d %d 0x" ADDRX "\n", | |
635 | base + (i * 8), pte0, pte1, | |
636 | (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), | |
637 | ctx->ptem); | |
638 | } | |
9a64fbe4 | 639 | #endif |
12de9a39 | 640 | } |
caa4039c | 641 | switch (r) { |
76a66253 JM |
642 | case -3: |
643 | /* PTE inconsistency */ | |
644 | return -1; | |
645 | case -2: | |
646 | /* Access violation */ | |
647 | ret = -2; | |
648 | good = i; | |
649 | break; | |
650 | case -1: | |
651 | default: | |
652 | /* No PTE match */ | |
653 | break; | |
654 | case 0: | |
655 | /* access granted */ | |
656 | /* XXX: we should go on looping to check all PTEs consistency | |
657 | * but if we can speed-up the whole thing as the | |
658 | * result would be undefined if PTEs are not consistent. | |
659 | */ | |
660 | ret = 0; | |
661 | good = i; | |
662 | goto done; | |
9a64fbe4 FB |
663 | } |
664 | } | |
665 | if (good != -1) { | |
76a66253 | 666 | done: |
9a64fbe4 | 667 | #if defined (DEBUG_MMU) |
4a057712 JM |
668 | if (loglevel != 0) { |
669 | fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x " | |
1b9eb036 | 670 | "ret=%d\n", |
76a66253 JM |
671 | ctx->raddr, ctx->prot, ret); |
672 | } | |
9a64fbe4 FB |
673 | #endif |
674 | /* Update page flags */ | |
76a66253 | 675 | pte1 = ctx->raddr; |
caa4039c JM |
676 | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
677 | #if defined(TARGET_PPC64) | |
678 | if (is_64b) { | |
679 | stq_phys_notdirty(base + (good * 16) + 8, pte1); | |
680 | } else | |
681 | #endif | |
682 | { | |
683 | stl_phys_notdirty(base + (good * 8) + 4, pte1); | |
684 | } | |
685 | } | |
9a64fbe4 FB |
686 | } |
687 | ||
688 | return ret; | |
79aceca5 FB |
689 | } |
690 | ||
a11b8151 | 691 | static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type) |
caa4039c | 692 | { |
b227a8e9 | 693 | return _find_pte(ctx, 0, h, rw, type); |
caa4039c JM |
694 | } |
695 | ||
696 | #if defined(TARGET_PPC64) | |
a11b8151 | 697 | static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type) |
caa4039c | 698 | { |
b227a8e9 | 699 | return _find_pte(ctx, 1, h, rw, type); |
caa4039c JM |
700 | } |
701 | #endif | |
702 | ||
b068d6a7 | 703 | static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, |
b227a8e9 | 704 | int h, int rw, int type) |
caa4039c JM |
705 | { |
706 | #if defined(TARGET_PPC64) | |
12de9a39 | 707 | if (env->mmu_model == POWERPC_MMU_64B) |
b227a8e9 | 708 | return find_pte64(ctx, h, rw, type); |
caa4039c JM |
709 | #endif |
710 | ||
b227a8e9 | 711 | return find_pte32(ctx, h, rw, type); |
caa4039c JM |
712 | } |
713 | ||
caa4039c | 714 | #if defined(TARGET_PPC64) |
a11b8151 | 715 | static always_inline int slb_is_valid (uint64_t slb64) |
eacc3249 JM |
716 | { |
717 | return slb64 & 0x0000000008000000ULL ? 1 : 0; | |
718 | } | |
719 | ||
a11b8151 | 720 | static always_inline void slb_invalidate (uint64_t *slb64) |
eacc3249 JM |
721 | { |
722 | *slb64 &= ~0x0000000008000000ULL; | |
723 | } | |
724 | ||
a11b8151 JM |
725 | static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr, |
726 | target_ulong *vsid, | |
727 | target_ulong *page_mask, int *attr) | |
caa4039c JM |
728 | { |
729 | target_phys_addr_t sr_base; | |
730 | target_ulong mask; | |
731 | uint64_t tmp64; | |
732 | uint32_t tmp; | |
733 | int n, ret; | |
caa4039c JM |
734 | |
735 | ret = -5; | |
736 | sr_base = env->spr[SPR_ASR]; | |
12de9a39 JM |
737 | #if defined(DEBUG_SLB) |
738 | if (loglevel != 0) { | |
739 | fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n", | |
740 | __func__, eaddr, sr_base); | |
741 | } | |
742 | #endif | |
caa4039c | 743 | mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
eacc3249 | 744 | for (n = 0; n < env->slb_nr; n++) { |
caa4039c | 745 | tmp64 = ldq_phys(sr_base); |
12de9a39 JM |
746 | tmp = ldl_phys(sr_base + 8); |
747 | #if defined(DEBUG_SLB) | |
748 | if (loglevel != 0) { | |
b33c17e1 JM |
749 | fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08" |
750 | PRIx32 "\n", __func__, n, sr_base, tmp64, tmp); | |
12de9a39 JM |
751 | } |
752 | #endif | |
eacc3249 | 753 | if (slb_is_valid(tmp64)) { |
caa4039c JM |
754 | /* SLB entry is valid */ |
755 | switch (tmp64 & 0x0000000006000000ULL) { | |
756 | case 0x0000000000000000ULL: | |
757 | /* 256 MB segment */ | |
758 | mask = 0xFFFFFFFFF0000000ULL; | |
759 | break; | |
760 | case 0x0000000002000000ULL: | |
761 | /* 1 TB segment */ | |
762 | mask = 0xFFFF000000000000ULL; | |
763 | break; | |
764 | case 0x0000000004000000ULL: | |
765 | case 0x0000000006000000ULL: | |
766 | /* Reserved => segment is invalid */ | |
767 | continue; | |
768 | } | |
769 | if ((eaddr & mask) == (tmp64 & mask)) { | |
770 | /* SLB match */ | |
caa4039c JM |
771 | *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
772 | *page_mask = ~mask; | |
773 | *attr = tmp & 0xFF; | |
eacc3249 | 774 | ret = n; |
caa4039c JM |
775 | break; |
776 | } | |
777 | } | |
778 | sr_base += 12; | |
779 | } | |
780 | ||
781 | return ret; | |
79aceca5 | 782 | } |
12de9a39 | 783 | |
eacc3249 JM |
784 | void ppc_slb_invalidate_all (CPUPPCState *env) |
785 | { | |
786 | target_phys_addr_t sr_base; | |
787 | uint64_t tmp64; | |
788 | int n, do_invalidate; | |
789 | ||
790 | do_invalidate = 0; | |
791 | sr_base = env->spr[SPR_ASR]; | |
2c1ee068 JM |
792 | /* XXX: Warning: slbia never invalidates the first segment */ |
793 | for (n = 1; n < env->slb_nr; n++) { | |
eacc3249 JM |
794 | tmp64 = ldq_phys(sr_base); |
795 | if (slb_is_valid(tmp64)) { | |
796 | slb_invalidate(&tmp64); | |
797 | stq_phys(sr_base, tmp64); | |
798 | /* XXX: given the fact that segment size is 256 MB or 1TB, | |
799 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
800 | * in Qemu, we just invalidate all TLBs | |
801 | */ | |
802 | do_invalidate = 1; | |
803 | } | |
804 | sr_base += 12; | |
805 | } | |
806 | if (do_invalidate) | |
807 | tlb_flush(env, 1); | |
808 | } | |
809 | ||
810 | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0) | |
811 | { | |
812 | target_phys_addr_t sr_base; | |
813 | target_ulong vsid, page_mask; | |
814 | uint64_t tmp64; | |
815 | int attr; | |
816 | int n; | |
817 | ||
818 | n = slb_lookup(env, T0, &vsid, &page_mask, &attr); | |
819 | if (n >= 0) { | |
820 | sr_base = env->spr[SPR_ASR]; | |
821 | sr_base += 12 * n; | |
822 | tmp64 = ldq_phys(sr_base); | |
823 | if (slb_is_valid(tmp64)) { | |
824 | slb_invalidate(&tmp64); | |
825 | stq_phys(sr_base, tmp64); | |
826 | /* XXX: given the fact that segment size is 256 MB or 1TB, | |
827 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
828 | * in Qemu, we just invalidate all TLBs | |
829 | */ | |
830 | tlb_flush(env, 1); | |
831 | } | |
832 | } | |
833 | } | |
834 | ||
12de9a39 JM |
835 | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr) |
836 | { | |
837 | target_phys_addr_t sr_base; | |
838 | target_ulong rt; | |
839 | uint64_t tmp64; | |
840 | uint32_t tmp; | |
841 | ||
842 | sr_base = env->spr[SPR_ASR]; | |
843 | sr_base += 12 * slb_nr; | |
844 | tmp64 = ldq_phys(sr_base); | |
845 | tmp = ldl_phys(sr_base + 8); | |
846 | if (tmp64 & 0x0000000008000000ULL) { | |
847 | /* SLB entry is valid */ | |
848 | /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */ | |
849 | rt = tmp >> 8; /* 65:88 => 40:63 */ | |
850 | rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */ | |
851 | /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */ | |
852 | rt |= ((tmp >> 4) & 0xF) << 27; | |
853 | } else { | |
854 | rt = 0; | |
855 | } | |
856 | #if defined(DEBUG_SLB) | |
857 | if (loglevel != 0) { | |
858 | fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d " | |
859 | ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt); | |
860 | } | |
861 | #endif | |
862 | ||
863 | return rt; | |
864 | } | |
865 | ||
866 | void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs) | |
867 | { | |
868 | target_phys_addr_t sr_base; | |
869 | uint64_t tmp64; | |
870 | uint32_t tmp; | |
871 | ||
872 | sr_base = env->spr[SPR_ASR]; | |
873 | sr_base += 12 * slb_nr; | |
874 | /* Copy Rs bits 37:63 to SLB 62:88 */ | |
875 | tmp = rs << 8; | |
876 | tmp64 = (rs >> 24) & 0x7; | |
877 | /* Copy Rs bits 33:36 to SLB 89:92 */ | |
878 | tmp |= ((rs >> 27) & 0xF) << 4; | |
879 | /* Set the valid bit */ | |
880 | tmp64 |= 1 << 27; | |
881 | /* Set ESID */ | |
882 | tmp64 |= (uint32_t)slb_nr << 28; | |
883 | #if defined(DEBUG_SLB) | |
884 | if (loglevel != 0) { | |
885 | fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 " %08" | |
886 | PRIx32 "\n", __func__, slb_nr, rs, sr_base, tmp64, tmp); | |
887 | } | |
888 | #endif | |
889 | /* Write SLB entry to memory */ | |
890 | stq_phys(sr_base, tmp64); | |
891 | stl_phys(sr_base + 8, tmp); | |
892 | } | |
caa4039c | 893 | #endif /* defined(TARGET_PPC64) */ |
79aceca5 | 894 | |
9a64fbe4 | 895 | /* Perform segment based translation */ |
b068d6a7 JM |
896 | static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1, |
897 | int sdr_sh, | |
898 | target_phys_addr_t hash, | |
899 | target_phys_addr_t mask) | |
12de9a39 JM |
900 | { |
901 | return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask); | |
902 | } | |
903 | ||
a11b8151 JM |
904 | static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, |
905 | target_ulong eaddr, int rw, int type) | |
79aceca5 | 906 | { |
12de9a39 | 907 | target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
caa4039c JM |
908 | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
909 | #if defined(TARGET_PPC64) | |
910 | int attr; | |
9a64fbe4 | 911 | #endif |
0411a972 | 912 | int ds, vsid_sh, sdr_sh, pr; |
caa4039c JM |
913 | int ret, ret2; |
914 | ||
0411a972 | 915 | pr = msr_pr; |
caa4039c | 916 | #if defined(TARGET_PPC64) |
12de9a39 JM |
917 | if (env->mmu_model == POWERPC_MMU_64B) { |
918 | #if defined (DEBUG_MMU) | |
919 | if (loglevel != 0) { | |
920 | fprintf(logfile, "Check SLBs\n"); | |
921 | } | |
922 | #endif | |
caa4039c JM |
923 | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr); |
924 | if (ret < 0) | |
925 | return ret; | |
0411a972 JM |
926 | ctx->key = ((attr & 0x40) && (pr != 0)) || |
927 | ((attr & 0x80) && (pr == 0)) ? 1 : 0; | |
caa4039c | 928 | ds = 0; |
b227a8e9 | 929 | ctx->nx = attr & 0x20 ? 1 : 0; |
caa4039c JM |
930 | vsid_mask = 0x00003FFFFFFFFF80ULL; |
931 | vsid_sh = 7; | |
932 | sdr_sh = 18; | |
933 | sdr_mask = 0x3FF80; | |
934 | } else | |
935 | #endif /* defined(TARGET_PPC64) */ | |
936 | { | |
937 | sr = env->sr[eaddr >> 28]; | |
938 | page_mask = 0x0FFFFFFF; | |
0411a972 JM |
939 | ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
940 | ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; | |
caa4039c | 941 | ds = sr & 0x80000000 ? 1 : 0; |
b227a8e9 | 942 | ctx->nx = sr & 0x10000000 ? 1 : 0; |
caa4039c JM |
943 | vsid = sr & 0x00FFFFFF; |
944 | vsid_mask = 0x01FFFFC0; | |
945 | vsid_sh = 6; | |
946 | sdr_sh = 16; | |
947 | sdr_mask = 0xFFC0; | |
9a64fbe4 | 948 | #if defined (DEBUG_MMU) |
caa4039c JM |
949 | if (loglevel != 0) { |
950 | fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX | |
951 | " nip=0x" ADDRX " lr=0x" ADDRX | |
952 | " ir=%d dr=%d pr=%d %d t=%d\n", | |
953 | eaddr, (int)(eaddr >> 28), sr, env->nip, | |
0411a972 JM |
954 | env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, |
955 | rw, type); | |
caa4039c | 956 | } |
9a64fbe4 | 957 | #endif |
caa4039c | 958 | } |
12de9a39 JM |
959 | #if defined (DEBUG_MMU) |
960 | if (loglevel != 0) { | |
961 | fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n", | |
b227a8e9 | 962 | ctx->key, ds, ctx->nx, vsid); |
12de9a39 JM |
963 | } |
964 | #endif | |
caa4039c JM |
965 | ret = -1; |
966 | if (!ds) { | |
9a64fbe4 | 967 | /* Check if instruction fetch is allowed, if needed */ |
b227a8e9 | 968 | if (type != ACCESS_CODE || ctx->nx == 0) { |
9a64fbe4 | 969 | /* Page address translation */ |
76a66253 JM |
970 | /* Primary table address */ |
971 | sdr = env->sdr1; | |
12de9a39 JM |
972 | pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS; |
973 | #if defined(TARGET_PPC64) | |
974 | if (env->mmu_model == POWERPC_MMU_64B) { | |
975 | htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); | |
976 | /* XXX: this is false for 1 TB segments */ | |
977 | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; | |
978 | } else | |
979 | #endif | |
980 | { | |
981 | htab_mask = sdr & 0x000001FF; | |
982 | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; | |
983 | } | |
984 | mask = (htab_mask << sdr_sh) | sdr_mask; | |
985 | #if defined (DEBUG_MMU) | |
986 | if (loglevel != 0) { | |
987 | fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask " | |
988 | PADDRX " " ADDRX "\n", sdr, sdr_sh, hash, mask, | |
989 | page_mask); | |
990 | } | |
991 | #endif | |
caa4039c | 992 | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask); |
76a66253 | 993 | /* Secondary table address */ |
caa4039c | 994 | hash = (~hash) & vsid_mask; |
12de9a39 JM |
995 | #if defined (DEBUG_MMU) |
996 | if (loglevel != 0) { | |
997 | fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask " | |
998 | PADDRX "\n", sdr, sdr_sh, hash, mask); | |
999 | } | |
1000 | #endif | |
caa4039c JM |
1001 | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask); |
1002 | #if defined(TARGET_PPC64) | |
12de9a39 | 1003 | if (env->mmu_model == POWERPC_MMU_64B) { |
caa4039c JM |
1004 | /* Only 5 bits of the page index are used in the AVPN */ |
1005 | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); | |
1006 | } else | |
1007 | #endif | |
1008 | { | |
1009 | ctx->ptem = (vsid << 7) | (pgidx >> 10); | |
1010 | } | |
76a66253 JM |
1011 | /* Initialize real address with an invalid value */ |
1012 | ctx->raddr = (target_ulong)-1; | |
7dbe11ac JM |
1013 | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx || |
1014 | env->mmu_model == POWERPC_MMU_SOFT_74xx)) { | |
76a66253 JM |
1015 | /* Software TLB search */ |
1016 | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); | |
76a66253 | 1017 | } else { |
9a64fbe4 | 1018 | #if defined (DEBUG_MMU) |
4a057712 JM |
1019 | if (loglevel != 0) { |
1020 | fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x " | |
1021 | "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n", | |
1022 | sdr, (uint32_t)vsid, (uint32_t)pgidx, | |
1023 | (uint32_t)hash, ctx->pg_addr[0]); | |
76a66253 | 1024 | } |
9a64fbe4 | 1025 | #endif |
76a66253 | 1026 | /* Primary table lookup */ |
b227a8e9 | 1027 | ret = find_pte(env, ctx, 0, rw, type); |
76a66253 JM |
1028 | if (ret < 0) { |
1029 | /* Secondary table lookup */ | |
9a64fbe4 | 1030 | #if defined (DEBUG_MMU) |
4a057712 | 1031 | if (eaddr != 0xEFFFFFFF && loglevel != 0) { |
76a66253 | 1032 | fprintf(logfile, |
4a057712 JM |
1033 | "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x " |
1034 | "hash=0x%05x pg_addr=0x" PADDRX "\n", | |
1035 | sdr, (uint32_t)vsid, (uint32_t)pgidx, | |
1036 | (uint32_t)hash, ctx->pg_addr[1]); | |
76a66253 | 1037 | } |
9a64fbe4 | 1038 | #endif |
b227a8e9 | 1039 | ret2 = find_pte(env, ctx, 1, rw, type); |
76a66253 JM |
1040 | if (ret2 != -1) |
1041 | ret = ret2; | |
1042 | } | |
9a64fbe4 | 1043 | } |
0411a972 | 1044 | #if defined (DUMP_PAGE_TABLES) |
b33c17e1 JM |
1045 | if (loglevel != 0) { |
1046 | target_phys_addr_t curaddr; | |
1047 | uint32_t a0, a1, a2, a3; | |
1048 | fprintf(logfile, | |
1049 | "Page table: " PADDRX " len " PADDRX "\n", | |
1050 | sdr, mask + 0x80); | |
1051 | for (curaddr = sdr; curaddr < (sdr + mask + 0x80); | |
1052 | curaddr += 16) { | |
1053 | a0 = ldl_phys(curaddr); | |
1054 | a1 = ldl_phys(curaddr + 4); | |
1055 | a2 = ldl_phys(curaddr + 8); | |
1056 | a3 = ldl_phys(curaddr + 12); | |
1057 | if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { | |
12de9a39 | 1058 | fprintf(logfile, |
b33c17e1 JM |
1059 | PADDRX ": %08x %08x %08x %08x\n", |
1060 | curaddr, a0, a1, a2, a3); | |
12de9a39 | 1061 | } |
b33c17e1 JM |
1062 | } |
1063 | } | |
12de9a39 | 1064 | #endif |
9a64fbe4 FB |
1065 | } else { |
1066 | #if defined (DEBUG_MMU) | |
4a057712 | 1067 | if (loglevel != 0) |
76a66253 | 1068 | fprintf(logfile, "No access allowed\n"); |
9a64fbe4 | 1069 | #endif |
76a66253 | 1070 | ret = -3; |
9a64fbe4 FB |
1071 | } |
1072 | } else { | |
1073 | #if defined (DEBUG_MMU) | |
4a057712 | 1074 | if (loglevel != 0) |
76a66253 | 1075 | fprintf(logfile, "direct store...\n"); |
9a64fbe4 FB |
1076 | #endif |
1077 | /* Direct-store segment : absolutely *BUGGY* for now */ | |
1078 | switch (type) { | |
1079 | case ACCESS_INT: | |
1080 | /* Integer load/store : only access allowed */ | |
1081 | break; | |
1082 | case ACCESS_CODE: | |
1083 | /* No code fetch is allowed in direct-store areas */ | |
1084 | return -4; | |
1085 | case ACCESS_FLOAT: | |
1086 | /* Floating point load/store */ | |
1087 | return -4; | |
1088 | case ACCESS_RES: | |
1089 | /* lwarx, ldarx or srwcx. */ | |
1090 | return -4; | |
1091 | case ACCESS_CACHE: | |
1092 | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */ | |
1093 | /* Should make the instruction do no-op. | |
1094 | * As it already do no-op, it's quite easy :-) | |
1095 | */ | |
76a66253 | 1096 | ctx->raddr = eaddr; |
9a64fbe4 FB |
1097 | return 0; |
1098 | case ACCESS_EXT: | |
1099 | /* eciwx or ecowx */ | |
1100 | return -4; | |
1101 | default: | |
1102 | if (logfile) { | |
1103 | fprintf(logfile, "ERROR: instruction should not need " | |
1104 | "address translation\n"); | |
1105 | } | |
9a64fbe4 FB |
1106 | return -4; |
1107 | } | |
76a66253 JM |
1108 | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
1109 | ctx->raddr = eaddr; | |
9a64fbe4 FB |
1110 | ret = 2; |
1111 | } else { | |
1112 | ret = -2; | |
1113 | } | |
79aceca5 | 1114 | } |
9a64fbe4 FB |
1115 | |
1116 | return ret; | |
79aceca5 FB |
1117 | } |
1118 | ||
c294fc58 | 1119 | /* Generic TLB check function for embedded PowerPC implementations */ |
a11b8151 JM |
1120 | static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, |
1121 | target_phys_addr_t *raddrp, | |
1122 | target_ulong address, | |
1123 | uint32_t pid, int ext, int i) | |
c294fc58 JM |
1124 | { |
1125 | target_ulong mask; | |
1126 | ||
1127 | /* Check valid flag */ | |
1128 | if (!(tlb->prot & PAGE_VALID)) { | |
1129 | if (loglevel != 0) | |
1130 | fprintf(logfile, "%s: TLB %d not valid\n", __func__, i); | |
1131 | return -1; | |
1132 | } | |
1133 | mask = ~(tlb->size - 1); | |
daf4f96e | 1134 | #if defined (DEBUG_SOFTWARE_TLB) |
c294fc58 JM |
1135 | if (loglevel != 0) { |
1136 | fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> " | |
1137 | ADDRX " " ADDRX " %d\n", | |
36081602 | 1138 | __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID); |
c294fc58 | 1139 | } |
daf4f96e | 1140 | #endif |
c294fc58 | 1141 | /* Check PID */ |
36081602 | 1142 | if (tlb->PID != 0 && tlb->PID != pid) |
c294fc58 JM |
1143 | return -1; |
1144 | /* Check effective address */ | |
1145 | if ((address & mask) != tlb->EPN) | |
1146 | return -1; | |
1147 | *raddrp = (tlb->RPN & mask) | (address & ~mask); | |
9706285b | 1148 | #if (TARGET_PHYS_ADDR_BITS >= 36) |
36081602 JM |
1149 | if (ext) { |
1150 | /* Extend the physical address to 36 bits */ | |
1151 | *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; | |
1152 | } | |
9706285b | 1153 | #endif |
c294fc58 JM |
1154 | |
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | /* Generic TLB search function for PowerPC embedded implementations */ | |
36081602 | 1159 | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid) |
c294fc58 JM |
1160 | { |
1161 | ppcemb_tlb_t *tlb; | |
1162 | target_phys_addr_t raddr; | |
1163 | int i, ret; | |
1164 | ||
1165 | /* Default return value is no match */ | |
1166 | ret = -1; | |
a750fc0b | 1167 | for (i = 0; i < env->nb_tlb; i++) { |
c294fc58 | 1168 | tlb = &env->tlb[i].tlbe; |
36081602 | 1169 | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
c294fc58 JM |
1170 | ret = i; |
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | return ret; | |
1176 | } | |
1177 | ||
daf4f96e | 1178 | /* Helpers specific to PowerPC 40x implementations */ |
a11b8151 | 1179 | static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env) |
a750fc0b JM |
1180 | { |
1181 | ppcemb_tlb_t *tlb; | |
a750fc0b JM |
1182 | int i; |
1183 | ||
1184 | for (i = 0; i < env->nb_tlb; i++) { | |
1185 | tlb = &env->tlb[i].tlbe; | |
daf4f96e | 1186 | tlb->prot &= ~PAGE_VALID; |
a750fc0b | 1187 | } |
daf4f96e | 1188 | tlb_flush(env, 1); |
a750fc0b JM |
1189 | } |
1190 | ||
a11b8151 JM |
1191 | static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env, |
1192 | target_ulong eaddr, | |
1193 | uint32_t pid) | |
0a032cbe | 1194 | { |
daf4f96e | 1195 | #if !defined(FLUSH_ALL_TLBS) |
0a032cbe | 1196 | ppcemb_tlb_t *tlb; |
daf4f96e JM |
1197 | target_phys_addr_t raddr; |
1198 | target_ulong page, end; | |
0a032cbe JM |
1199 | int i; |
1200 | ||
1201 | for (i = 0; i < env->nb_tlb; i++) { | |
1202 | tlb = &env->tlb[i].tlbe; | |
daf4f96e | 1203 | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
0a032cbe JM |
1204 | end = tlb->EPN + tlb->size; |
1205 | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) | |
1206 | tlb_flush_page(env, page); | |
0a032cbe | 1207 | tlb->prot &= ~PAGE_VALID; |
daf4f96e | 1208 | break; |
0a032cbe JM |
1209 | } |
1210 | } | |
daf4f96e JM |
1211 | #else |
1212 | ppc4xx_tlb_invalidate_all(env); | |
1213 | #endif | |
0a032cbe JM |
1214 | } |
1215 | ||
36081602 | 1216 | int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
e96efcfc | 1217 | target_ulong address, int rw, int access_type) |
a8dea12f JM |
1218 | { |
1219 | ppcemb_tlb_t *tlb; | |
1220 | target_phys_addr_t raddr; | |
0411a972 | 1221 | int i, ret, zsel, zpr, pr; |
3b46e624 | 1222 | |
c55e9aef JM |
1223 | ret = -1; |
1224 | raddr = -1; | |
0411a972 | 1225 | pr = msr_pr; |
a8dea12f JM |
1226 | for (i = 0; i < env->nb_tlb; i++) { |
1227 | tlb = &env->tlb[i].tlbe; | |
36081602 JM |
1228 | if (ppcemb_tlb_check(env, tlb, &raddr, address, |
1229 | env->spr[SPR_40x_PID], 0, i) < 0) | |
a8dea12f | 1230 | continue; |
a8dea12f JM |
1231 | zsel = (tlb->attr >> 4) & 0xF; |
1232 | zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; | |
daf4f96e | 1233 | #if defined (DEBUG_SOFTWARE_TLB) |
4a057712 | 1234 | if (loglevel != 0) { |
a8dea12f JM |
1235 | fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n", |
1236 | __func__, i, zsel, zpr, rw, tlb->attr); | |
1237 | } | |
daf4f96e | 1238 | #endif |
b227a8e9 JM |
1239 | /* Check execute enable bit */ |
1240 | switch (zpr) { | |
1241 | case 0x2: | |
0411a972 | 1242 | if (pr != 0) |
b227a8e9 JM |
1243 | goto check_perms; |
1244 | /* No break here */ | |
1245 | case 0x3: | |
1246 | /* All accesses granted */ | |
1247 | ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
1248 | ret = 0; | |
1249 | break; | |
1250 | case 0x0: | |
0411a972 | 1251 | if (pr != 0) { |
b227a8e9 JM |
1252 | ctx->prot = 0; |
1253 | ret = -2; | |
a8dea12f JM |
1254 | break; |
1255 | } | |
b227a8e9 JM |
1256 | /* No break here */ |
1257 | case 0x1: | |
1258 | check_perms: | |
1259 | /* Check from TLB entry */ | |
1260 | /* XXX: there is a problem here or in the TLB fill code... */ | |
1261 | ctx->prot = tlb->prot; | |
1262 | ctx->prot |= PAGE_EXEC; | |
1263 | ret = check_prot(ctx->prot, rw, access_type); | |
1264 | break; | |
a8dea12f JM |
1265 | } |
1266 | if (ret >= 0) { | |
1267 | ctx->raddr = raddr; | |
daf4f96e | 1268 | #if defined (DEBUG_SOFTWARE_TLB) |
4a057712 | 1269 | if (loglevel != 0) { |
a8dea12f | 1270 | fprintf(logfile, "%s: access granted " ADDRX " => " REGX |
c55e9aef JM |
1271 | " %d %d\n", __func__, address, ctx->raddr, ctx->prot, |
1272 | ret); | |
a8dea12f | 1273 | } |
daf4f96e | 1274 | #endif |
c55e9aef | 1275 | return 0; |
a8dea12f JM |
1276 | } |
1277 | } | |
daf4f96e | 1278 | #if defined (DEBUG_SOFTWARE_TLB) |
4a057712 | 1279 | if (loglevel != 0) { |
c55e9aef JM |
1280 | fprintf(logfile, "%s: access refused " ADDRX " => " REGX |
1281 | " %d %d\n", __func__, address, raddr, ctx->prot, | |
1282 | ret); | |
1283 | } | |
daf4f96e | 1284 | #endif |
3b46e624 | 1285 | |
a8dea12f JM |
1286 | return ret; |
1287 | } | |
1288 | ||
c294fc58 JM |
1289 | void store_40x_sler (CPUPPCState *env, uint32_t val) |
1290 | { | |
1291 | /* XXX: TO BE FIXED */ | |
1292 | if (val != 0x00000000) { | |
1293 | cpu_abort(env, "Little-endian regions are not supported by now\n"); | |
1294 | } | |
1295 | env->spr[SPR_405_SLER] = val; | |
1296 | } | |
1297 | ||
5eb7995e JM |
1298 | int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
1299 | target_ulong address, int rw, | |
1300 | int access_type) | |
1301 | { | |
1302 | ppcemb_tlb_t *tlb; | |
1303 | target_phys_addr_t raddr; | |
1304 | int i, prot, ret; | |
1305 | ||
1306 | ret = -1; | |
1307 | raddr = -1; | |
1308 | for (i = 0; i < env->nb_tlb; i++) { | |
1309 | tlb = &env->tlb[i].tlbe; | |
1310 | if (ppcemb_tlb_check(env, tlb, &raddr, address, | |
1311 | env->spr[SPR_BOOKE_PID], 1, i) < 0) | |
1312 | continue; | |
0411a972 | 1313 | if (msr_pr != 0) |
5eb7995e JM |
1314 | prot = tlb->prot & 0xF; |
1315 | else | |
1316 | prot = (tlb->prot >> 4) & 0xF; | |
1317 | /* Check the address space */ | |
1318 | if (access_type == ACCESS_CODE) { | |
d26bfc9a | 1319 | if (msr_ir != (tlb->attr & 1)) |
5eb7995e JM |
1320 | continue; |
1321 | ctx->prot = prot; | |
1322 | if (prot & PAGE_EXEC) { | |
1323 | ret = 0; | |
1324 | break; | |
1325 | } | |
1326 | ret = -3; | |
1327 | } else { | |
d26bfc9a | 1328 | if (msr_dr != (tlb->attr & 1)) |
5eb7995e JM |
1329 | continue; |
1330 | ctx->prot = prot; | |
1331 | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) { | |
1332 | ret = 0; | |
1333 | break; | |
1334 | } | |
1335 | ret = -2; | |
1336 | } | |
1337 | } | |
1338 | if (ret >= 0) | |
1339 | ctx->raddr = raddr; | |
1340 | ||
1341 | return ret; | |
1342 | } | |
1343 | ||
a11b8151 JM |
1344 | static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx, |
1345 | target_ulong eaddr, int rw) | |
76a66253 JM |
1346 | { |
1347 | int in_plb, ret; | |
3b46e624 | 1348 | |
76a66253 | 1349 | ctx->raddr = eaddr; |
b227a8e9 | 1350 | ctx->prot = PAGE_READ | PAGE_EXEC; |
76a66253 | 1351 | ret = 0; |
a750fc0b JM |
1352 | switch (env->mmu_model) { |
1353 | case POWERPC_MMU_32B: | |
faadf50e | 1354 | case POWERPC_MMU_601: |
a750fc0b | 1355 | case POWERPC_MMU_SOFT_6xx: |
7dbe11ac | 1356 | case POWERPC_MMU_SOFT_74xx: |
a750fc0b JM |
1357 | case POWERPC_MMU_SOFT_4xx: |
1358 | case POWERPC_MMU_REAL_4xx: | |
7dbe11ac | 1359 | case POWERPC_MMU_BOOKE: |
caa4039c JM |
1360 | ctx->prot |= PAGE_WRITE; |
1361 | break; | |
1362 | #if defined(TARGET_PPC64) | |
a750fc0b | 1363 | case POWERPC_MMU_64B: |
caa4039c | 1364 | /* Real address are 60 bits long */ |
a750fc0b | 1365 | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL; |
caa4039c JM |
1366 | ctx->prot |= PAGE_WRITE; |
1367 | break; | |
9706285b | 1368 | #endif |
a750fc0b | 1369 | case POWERPC_MMU_SOFT_4xx_Z: |
caa4039c JM |
1370 | if (unlikely(msr_pe != 0)) { |
1371 | /* 403 family add some particular protections, | |
1372 | * using PBL/PBU registers for accesses with no translation. | |
1373 | */ | |
1374 | in_plb = | |
1375 | /* Check PLB validity */ | |
1376 | (env->pb[0] < env->pb[1] && | |
1377 | /* and address in plb area */ | |
1378 | eaddr >= env->pb[0] && eaddr < env->pb[1]) || | |
1379 | (env->pb[2] < env->pb[3] && | |
1380 | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; | |
1381 | if (in_plb ^ msr_px) { | |
1382 | /* Access in protected area */ | |
1383 | if (rw == 1) { | |
1384 | /* Access is not allowed */ | |
1385 | ret = -2; | |
1386 | } | |
1387 | } else { | |
1388 | /* Read-write access is allowed */ | |
1389 | ctx->prot |= PAGE_WRITE; | |
76a66253 | 1390 | } |
76a66253 | 1391 | } |
e1833e1f | 1392 | break; |
a750fc0b | 1393 | case POWERPC_MMU_BOOKE_FSL: |
caa4039c JM |
1394 | /* XXX: TODO */ |
1395 | cpu_abort(env, "BookE FSL MMU model not implemented\n"); | |
1396 | break; | |
1397 | default: | |
1398 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
1399 | return -1; | |
76a66253 JM |
1400 | } |
1401 | ||
1402 | return ret; | |
1403 | } | |
1404 | ||
1405 | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr, | |
faadf50e | 1406 | int rw, int access_type) |
9a64fbe4 FB |
1407 | { |
1408 | int ret; | |
0411a972 | 1409 | |
514fb8c1 | 1410 | #if 0 |
4a057712 | 1411 | if (loglevel != 0) { |
9a64fbe4 FB |
1412 | fprintf(logfile, "%s\n", __func__); |
1413 | } | |
d9bce9d9 | 1414 | #endif |
4b3686fa FB |
1415 | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1416 | (access_type != ACCESS_CODE && msr_dr == 0)) { | |
9a64fbe4 | 1417 | /* No address translation */ |
76a66253 | 1418 | ret = check_physical(env, ctx, eaddr, rw); |
9a64fbe4 | 1419 | } else { |
c55e9aef | 1420 | ret = -1; |
a750fc0b JM |
1421 | switch (env->mmu_model) { |
1422 | case POWERPC_MMU_32B: | |
faadf50e | 1423 | case POWERPC_MMU_601: |
a750fc0b | 1424 | case POWERPC_MMU_SOFT_6xx: |
7dbe11ac | 1425 | case POWERPC_MMU_SOFT_74xx: |
c55e9aef | 1426 | #if defined(TARGET_PPC64) |
a750fc0b | 1427 | case POWERPC_MMU_64B: |
c55e9aef | 1428 | #endif |
faadf50e JM |
1429 | /* Try to find a BAT */ |
1430 | if (env->nb_BATs != 0) | |
1431 | ret = get_bat(env, ctx, eaddr, rw, access_type); | |
a8dea12f | 1432 | if (ret < 0) { |
c55e9aef | 1433 | /* We didn't match any BAT entry or don't have BATs */ |
a8dea12f JM |
1434 | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1435 | } | |
1436 | break; | |
a750fc0b JM |
1437 | case POWERPC_MMU_SOFT_4xx: |
1438 | case POWERPC_MMU_SOFT_4xx_Z: | |
36081602 | 1439 | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
a8dea12f JM |
1440 | rw, access_type); |
1441 | break; | |
a750fc0b | 1442 | case POWERPC_MMU_BOOKE: |
5eb7995e JM |
1443 | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1444 | rw, access_type); | |
1445 | break; | |
a750fc0b | 1446 | case POWERPC_MMU_BOOKE_FSL: |
c55e9aef JM |
1447 | /* XXX: TODO */ |
1448 | cpu_abort(env, "BookE FSL MMU model not implemented\n"); | |
1449 | return -1; | |
a750fc0b | 1450 | case POWERPC_MMU_REAL_4xx: |
2662a059 JM |
1451 | cpu_abort(env, "PowerPC 401 does not do any translation\n"); |
1452 | return -1; | |
c55e9aef JM |
1453 | default: |
1454 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
a8dea12f | 1455 | return -1; |
9a64fbe4 FB |
1456 | } |
1457 | } | |
514fb8c1 | 1458 | #if 0 |
4a057712 JM |
1459 | if (loglevel != 0) { |
1460 | fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n", | |
c55e9aef | 1461 | __func__, eaddr, ret, ctx->raddr); |
a541f297 | 1462 | } |
76a66253 | 1463 | #endif |
d9bce9d9 | 1464 | |
9a64fbe4 FB |
1465 | return ret; |
1466 | } | |
1467 | ||
9b3c35e0 | 1468 | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
a6b025d3 | 1469 | { |
76a66253 | 1470 | mmu_ctx_t ctx; |
a6b025d3 | 1471 | |
faadf50e | 1472 | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) |
a6b025d3 | 1473 | return -1; |
76a66253 JM |
1474 | |
1475 | return ctx.raddr & TARGET_PAGE_MASK; | |
a6b025d3 | 1476 | } |
9a64fbe4 | 1477 | |
9a64fbe4 | 1478 | /* Perform address translation */ |
e96efcfc | 1479 | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 1480 | int mmu_idx, int is_softmmu) |
9a64fbe4 | 1481 | { |
76a66253 | 1482 | mmu_ctx_t ctx; |
a541f297 | 1483 | int access_type; |
9a64fbe4 | 1484 | int ret = 0; |
d9bce9d9 | 1485 | |
b769d8fe FB |
1486 | if (rw == 2) { |
1487 | /* code access */ | |
1488 | rw = 0; | |
1489 | access_type = ACCESS_CODE; | |
1490 | } else { | |
1491 | /* data access */ | |
1492 | /* XXX: put correct access by using cpu_restore_state() | |
1493 | correctly */ | |
1494 | access_type = ACCESS_INT; | |
1495 | // access_type = env->access_type; | |
1496 | } | |
faadf50e | 1497 | ret = get_physical_address(env, &ctx, address, rw, access_type); |
9a64fbe4 | 1498 | if (ret == 0) { |
b227a8e9 JM |
1499 | ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK, |
1500 | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, | |
1501 | mmu_idx, is_softmmu); | |
9a64fbe4 | 1502 | } else if (ret < 0) { |
9a64fbe4 | 1503 | #if defined (DEBUG_MMU) |
4a057712 | 1504 | if (loglevel != 0) |
76a66253 | 1505 | cpu_dump_state(env, logfile, fprintf, 0); |
9a64fbe4 FB |
1506 | #endif |
1507 | if (access_type == ACCESS_CODE) { | |
9a64fbe4 FB |
1508 | switch (ret) { |
1509 | case -1: | |
76a66253 | 1510 | /* No matches in page tables or TLB */ |
a750fc0b JM |
1511 | switch (env->mmu_model) { |
1512 | case POWERPC_MMU_SOFT_6xx: | |
8f793433 JM |
1513 | env->exception_index = POWERPC_EXCP_IFTLB; |
1514 | env->error_code = 1 << 18; | |
76a66253 JM |
1515 | env->spr[SPR_IMISS] = address; |
1516 | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; | |
76a66253 | 1517 | goto tlb_miss; |
7dbe11ac | 1518 | case POWERPC_MMU_SOFT_74xx: |
8f793433 | 1519 | env->exception_index = POWERPC_EXCP_IFTLB; |
7dbe11ac | 1520 | goto tlb_miss_74xx; |
a750fc0b JM |
1521 | case POWERPC_MMU_SOFT_4xx: |
1522 | case POWERPC_MMU_SOFT_4xx_Z: | |
8f793433 JM |
1523 | env->exception_index = POWERPC_EXCP_ITLB; |
1524 | env->error_code = 0; | |
a8dea12f JM |
1525 | env->spr[SPR_40x_DEAR] = address; |
1526 | env->spr[SPR_40x_ESR] = 0x00000000; | |
c55e9aef | 1527 | break; |
a750fc0b | 1528 | case POWERPC_MMU_32B: |
faadf50e | 1529 | case POWERPC_MMU_601: |
c55e9aef | 1530 | #if defined(TARGET_PPC64) |
a750fc0b | 1531 | case POWERPC_MMU_64B: |
c55e9aef | 1532 | #endif |
8f793433 JM |
1533 | env->exception_index = POWERPC_EXCP_ISI; |
1534 | env->error_code = 0x40000000; | |
1535 | break; | |
a750fc0b | 1536 | case POWERPC_MMU_BOOKE: |
c55e9aef JM |
1537 | /* XXX: TODO */ |
1538 | cpu_abort(env, "MMU model not implemented\n"); | |
1539 | return -1; | |
a750fc0b | 1540 | case POWERPC_MMU_BOOKE_FSL: |
c55e9aef JM |
1541 | /* XXX: TODO */ |
1542 | cpu_abort(env, "MMU model not implemented\n"); | |
1543 | return -1; | |
a750fc0b | 1544 | case POWERPC_MMU_REAL_4xx: |
2662a059 JM |
1545 | cpu_abort(env, "PowerPC 401 should never raise any MMU " |
1546 | "exceptions\n"); | |
1547 | return -1; | |
c55e9aef JM |
1548 | default: |
1549 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
1550 | return -1; | |
76a66253 | 1551 | } |
9a64fbe4 FB |
1552 | break; |
1553 | case -2: | |
1554 | /* Access rights violation */ | |
8f793433 JM |
1555 | env->exception_index = POWERPC_EXCP_ISI; |
1556 | env->error_code = 0x08000000; | |
9a64fbe4 FB |
1557 | break; |
1558 | case -3: | |
76a66253 | 1559 | /* No execute protection violation */ |
8f793433 JM |
1560 | env->exception_index = POWERPC_EXCP_ISI; |
1561 | env->error_code = 0x10000000; | |
9a64fbe4 FB |
1562 | break; |
1563 | case -4: | |
1564 | /* Direct store exception */ | |
1565 | /* No code fetch is allowed in direct-store areas */ | |
8f793433 JM |
1566 | env->exception_index = POWERPC_EXCP_ISI; |
1567 | env->error_code = 0x10000000; | |
2be0071f | 1568 | break; |
e1833e1f | 1569 | #if defined(TARGET_PPC64) |
2be0071f FB |
1570 | case -5: |
1571 | /* No match in segment table */ | |
8f793433 JM |
1572 | env->exception_index = POWERPC_EXCP_ISEG; |
1573 | env->error_code = 0; | |
9a64fbe4 | 1574 | break; |
e1833e1f | 1575 | #endif |
9a64fbe4 FB |
1576 | } |
1577 | } else { | |
9a64fbe4 FB |
1578 | switch (ret) { |
1579 | case -1: | |
76a66253 | 1580 | /* No matches in page tables or TLB */ |
a750fc0b JM |
1581 | switch (env->mmu_model) { |
1582 | case POWERPC_MMU_SOFT_6xx: | |
76a66253 | 1583 | if (rw == 1) { |
8f793433 JM |
1584 | env->exception_index = POWERPC_EXCP_DSTLB; |
1585 | env->error_code = 1 << 16; | |
76a66253 | 1586 | } else { |
8f793433 JM |
1587 | env->exception_index = POWERPC_EXCP_DLTLB; |
1588 | env->error_code = 0; | |
76a66253 JM |
1589 | } |
1590 | env->spr[SPR_DMISS] = address; | |
1591 | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem; | |
1592 | tlb_miss: | |
8f793433 | 1593 | env->error_code |= ctx.key << 19; |
76a66253 JM |
1594 | env->spr[SPR_HASH1] = ctx.pg_addr[0]; |
1595 | env->spr[SPR_HASH2] = ctx.pg_addr[1]; | |
8f793433 | 1596 | break; |
7dbe11ac JM |
1597 | case POWERPC_MMU_SOFT_74xx: |
1598 | if (rw == 1) { | |
8f793433 | 1599 | env->exception_index = POWERPC_EXCP_DSTLB; |
7dbe11ac | 1600 | } else { |
8f793433 | 1601 | env->exception_index = POWERPC_EXCP_DLTLB; |
7dbe11ac JM |
1602 | } |
1603 | tlb_miss_74xx: | |
1604 | /* Implement LRU algorithm */ | |
8f793433 | 1605 | env->error_code = ctx.key << 19; |
7dbe11ac JM |
1606 | env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) | |
1607 | ((env->last_way + 1) & (env->nb_ways - 1)); | |
1608 | env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem; | |
7dbe11ac | 1609 | break; |
a750fc0b JM |
1610 | case POWERPC_MMU_SOFT_4xx: |
1611 | case POWERPC_MMU_SOFT_4xx_Z: | |
8f793433 JM |
1612 | env->exception_index = POWERPC_EXCP_DTLB; |
1613 | env->error_code = 0; | |
a8dea12f JM |
1614 | env->spr[SPR_40x_DEAR] = address; |
1615 | if (rw) | |
1616 | env->spr[SPR_40x_ESR] = 0x00800000; | |
1617 | else | |
1618 | env->spr[SPR_40x_ESR] = 0x00000000; | |
c55e9aef | 1619 | break; |
a750fc0b | 1620 | case POWERPC_MMU_32B: |
faadf50e | 1621 | case POWERPC_MMU_601: |
c55e9aef | 1622 | #if defined(TARGET_PPC64) |
a750fc0b | 1623 | case POWERPC_MMU_64B: |
c55e9aef | 1624 | #endif |
8f793433 JM |
1625 | env->exception_index = POWERPC_EXCP_DSI; |
1626 | env->error_code = 0; | |
1627 | env->spr[SPR_DAR] = address; | |
1628 | if (rw == 1) | |
1629 | env->spr[SPR_DSISR] = 0x42000000; | |
1630 | else | |
1631 | env->spr[SPR_DSISR] = 0x40000000; | |
1632 | break; | |
a750fc0b | 1633 | case POWERPC_MMU_BOOKE: |
c55e9aef JM |
1634 | /* XXX: TODO */ |
1635 | cpu_abort(env, "MMU model not implemented\n"); | |
1636 | return -1; | |
a750fc0b | 1637 | case POWERPC_MMU_BOOKE_FSL: |
c55e9aef JM |
1638 | /* XXX: TODO */ |
1639 | cpu_abort(env, "MMU model not implemented\n"); | |
1640 | return -1; | |
a750fc0b | 1641 | case POWERPC_MMU_REAL_4xx: |
2662a059 JM |
1642 | cpu_abort(env, "PowerPC 401 should never raise any MMU " |
1643 | "exceptions\n"); | |
1644 | return -1; | |
c55e9aef JM |
1645 | default: |
1646 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
1647 | return -1; | |
76a66253 | 1648 | } |
9a64fbe4 FB |
1649 | break; |
1650 | case -2: | |
1651 | /* Access rights violation */ | |
8f793433 JM |
1652 | env->exception_index = POWERPC_EXCP_DSI; |
1653 | env->error_code = 0; | |
1654 | env->spr[SPR_DAR] = address; | |
1655 | if (rw == 1) | |
1656 | env->spr[SPR_DSISR] = 0x0A000000; | |
1657 | else | |
1658 | env->spr[SPR_DSISR] = 0x08000000; | |
9a64fbe4 FB |
1659 | break; |
1660 | case -4: | |
1661 | /* Direct store exception */ | |
1662 | switch (access_type) { | |
1663 | case ACCESS_FLOAT: | |
1664 | /* Floating point load/store */ | |
8f793433 JM |
1665 | env->exception_index = POWERPC_EXCP_ALIGN; |
1666 | env->error_code = POWERPC_EXCP_ALIGN_FP; | |
1667 | env->spr[SPR_DAR] = address; | |
9a64fbe4 FB |
1668 | break; |
1669 | case ACCESS_RES: | |
8f793433 JM |
1670 | /* lwarx, ldarx or stwcx. */ |
1671 | env->exception_index = POWERPC_EXCP_DSI; | |
1672 | env->error_code = 0; | |
1673 | env->spr[SPR_DAR] = address; | |
1674 | if (rw == 1) | |
1675 | env->spr[SPR_DSISR] = 0x06000000; | |
1676 | else | |
1677 | env->spr[SPR_DSISR] = 0x04000000; | |
9a64fbe4 FB |
1678 | break; |
1679 | case ACCESS_EXT: | |
1680 | /* eciwx or ecowx */ | |
8f793433 JM |
1681 | env->exception_index = POWERPC_EXCP_DSI; |
1682 | env->error_code = 0; | |
1683 | env->spr[SPR_DAR] = address; | |
1684 | if (rw == 1) | |
1685 | env->spr[SPR_DSISR] = 0x06100000; | |
1686 | else | |
1687 | env->spr[SPR_DSISR] = 0x04100000; | |
9a64fbe4 FB |
1688 | break; |
1689 | default: | |
76a66253 | 1690 | printf("DSI: invalid exception (%d)\n", ret); |
8f793433 JM |
1691 | env->exception_index = POWERPC_EXCP_PROGRAM; |
1692 | env->error_code = | |
1693 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; | |
1694 | env->spr[SPR_DAR] = address; | |
9a64fbe4 FB |
1695 | break; |
1696 | } | |
fdabc366 | 1697 | break; |
e1833e1f | 1698 | #if defined(TARGET_PPC64) |
2be0071f FB |
1699 | case -5: |
1700 | /* No match in segment table */ | |
8f793433 JM |
1701 | env->exception_index = POWERPC_EXCP_DSEG; |
1702 | env->error_code = 0; | |
1703 | env->spr[SPR_DAR] = address; | |
2be0071f | 1704 | break; |
e1833e1f | 1705 | #endif |
9a64fbe4 | 1706 | } |
9a64fbe4 FB |
1707 | } |
1708 | #if 0 | |
8f793433 JM |
1709 | printf("%s: set exception to %d %02x\n", __func__, |
1710 | env->exception, env->error_code); | |
9a64fbe4 | 1711 | #endif |
9a64fbe4 FB |
1712 | ret = 1; |
1713 | } | |
76a66253 | 1714 | |
9a64fbe4 FB |
1715 | return ret; |
1716 | } | |
1717 | ||
3fc6c082 FB |
1718 | /*****************************************************************************/ |
1719 | /* BATs management */ | |
1720 | #if !defined(FLUSH_ALL_TLBS) | |
b068d6a7 JM |
1721 | static always_inline void do_invalidate_BAT (CPUPPCState *env, |
1722 | target_ulong BATu, | |
1723 | target_ulong mask) | |
3fc6c082 FB |
1724 | { |
1725 | target_ulong base, end, page; | |
76a66253 | 1726 | |
3fc6c082 FB |
1727 | base = BATu & ~0x0001FFFF; |
1728 | end = base + mask + 0x00020000; | |
1729 | #if defined (DEBUG_BATS) | |
76a66253 | 1730 | if (loglevel != 0) { |
1b9eb036 | 1731 | fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
76a66253 JM |
1732 | base, end, mask); |
1733 | } | |
3fc6c082 FB |
1734 | #endif |
1735 | for (page = base; page != end; page += TARGET_PAGE_SIZE) | |
1736 | tlb_flush_page(env, page); | |
1737 | #if defined (DEBUG_BATS) | |
1738 | if (loglevel != 0) | |
1739 | fprintf(logfile, "Flush done\n"); | |
1740 | #endif | |
1741 | } | |
1742 | #endif | |
1743 | ||
b068d6a7 JM |
1744 | static always_inline void dump_store_bat (CPUPPCState *env, char ID, |
1745 | int ul, int nr, target_ulong value) | |
3fc6c082 FB |
1746 | { |
1747 | #if defined (DEBUG_BATS) | |
1748 | if (loglevel != 0) { | |
1b9eb036 JM |
1749 | fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n", |
1750 | ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); | |
3fc6c082 FB |
1751 | } |
1752 | #endif | |
1753 | } | |
1754 | ||
1755 | target_ulong do_load_ibatu (CPUPPCState *env, int nr) | |
1756 | { | |
1757 | return env->IBAT[0][nr]; | |
1758 | } | |
1759 | ||
1760 | target_ulong do_load_ibatl (CPUPPCState *env, int nr) | |
1761 | { | |
1762 | return env->IBAT[1][nr]; | |
1763 | } | |
1764 | ||
1765 | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value) | |
1766 | { | |
1767 | target_ulong mask; | |
1768 | ||
1769 | dump_store_bat(env, 'I', 0, nr, value); | |
1770 | if (env->IBAT[0][nr] != value) { | |
1771 | mask = (value << 15) & 0x0FFE0000UL; | |
1772 | #if !defined(FLUSH_ALL_TLBS) | |
1773 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1774 | #endif | |
1775 | /* When storing valid upper BAT, mask BEPI and BRPN | |
1776 | * and invalidate all TLBs covered by this BAT | |
1777 | */ | |
1778 | mask = (value << 15) & 0x0FFE0000UL; | |
1779 | env->IBAT[0][nr] = (value & 0x00001FFFUL) | | |
1780 | (value & ~0x0001FFFFUL & ~mask); | |
1781 | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | | |
1782 | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); | |
1783 | #if !defined(FLUSH_ALL_TLBS) | |
1784 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
76a66253 | 1785 | #else |
3fc6c082 FB |
1786 | tlb_flush(env, 1); |
1787 | #endif | |
1788 | } | |
1789 | } | |
1790 | ||
1791 | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value) | |
1792 | { | |
1793 | dump_store_bat(env, 'I', 1, nr, value); | |
1794 | env->IBAT[1][nr] = value; | |
1795 | } | |
1796 | ||
1797 | target_ulong do_load_dbatu (CPUPPCState *env, int nr) | |
1798 | { | |
1799 | return env->DBAT[0][nr]; | |
1800 | } | |
1801 | ||
1802 | target_ulong do_load_dbatl (CPUPPCState *env, int nr) | |
1803 | { | |
1804 | return env->DBAT[1][nr]; | |
1805 | } | |
1806 | ||
1807 | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value) | |
1808 | { | |
1809 | target_ulong mask; | |
1810 | ||
1811 | dump_store_bat(env, 'D', 0, nr, value); | |
1812 | if (env->DBAT[0][nr] != value) { | |
1813 | /* When storing valid upper BAT, mask BEPI and BRPN | |
1814 | * and invalidate all TLBs covered by this BAT | |
1815 | */ | |
1816 | mask = (value << 15) & 0x0FFE0000UL; | |
1817 | #if !defined(FLUSH_ALL_TLBS) | |
1818 | do_invalidate_BAT(env, env->DBAT[0][nr], mask); | |
1819 | #endif | |
1820 | mask = (value << 15) & 0x0FFE0000UL; | |
1821 | env->DBAT[0][nr] = (value & 0x00001FFFUL) | | |
1822 | (value & ~0x0001FFFFUL & ~mask); | |
1823 | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | | |
1824 | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); | |
1825 | #if !defined(FLUSH_ALL_TLBS) | |
1826 | do_invalidate_BAT(env, env->DBAT[0][nr], mask); | |
1827 | #else | |
1828 | tlb_flush(env, 1); | |
1829 | #endif | |
1830 | } | |
1831 | } | |
1832 | ||
1833 | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value) | |
1834 | { | |
1835 | dump_store_bat(env, 'D', 1, nr, value); | |
1836 | env->DBAT[1][nr] = value; | |
1837 | } | |
1838 | ||
0a032cbe JM |
1839 | /*****************************************************************************/ |
1840 | /* TLB management */ | |
1841 | void ppc_tlb_invalidate_all (CPUPPCState *env) | |
1842 | { | |
daf4f96e JM |
1843 | switch (env->mmu_model) { |
1844 | case POWERPC_MMU_SOFT_6xx: | |
7dbe11ac | 1845 | case POWERPC_MMU_SOFT_74xx: |
0a032cbe | 1846 | ppc6xx_tlb_invalidate_all(env); |
daf4f96e JM |
1847 | break; |
1848 | case POWERPC_MMU_SOFT_4xx: | |
1849 | case POWERPC_MMU_SOFT_4xx_Z: | |
0a032cbe | 1850 | ppc4xx_tlb_invalidate_all(env); |
daf4f96e | 1851 | break; |
7dbe11ac JM |
1852 | case POWERPC_MMU_REAL_4xx: |
1853 | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); | |
1854 | break; | |
1855 | case POWERPC_MMU_BOOKE: | |
1856 | /* XXX: TODO */ | |
1857 | cpu_abort(env, "MMU model not implemented\n"); | |
1858 | break; | |
1859 | case POWERPC_MMU_BOOKE_FSL: | |
1860 | /* XXX: TODO */ | |
1861 | cpu_abort(env, "MMU model not implemented\n"); | |
1862 | break; | |
7dbe11ac | 1863 | case POWERPC_MMU_32B: |
faadf50e | 1864 | case POWERPC_MMU_601: |
00af685f | 1865 | #if defined(TARGET_PPC64) |
7dbe11ac | 1866 | case POWERPC_MMU_64B: |
00af685f | 1867 | #endif /* defined(TARGET_PPC64) */ |
0a032cbe | 1868 | tlb_flush(env, 1); |
daf4f96e | 1869 | break; |
00af685f JM |
1870 | default: |
1871 | /* XXX: TODO */ | |
12de9a39 | 1872 | cpu_abort(env, "Unknown MMU model\n"); |
00af685f | 1873 | break; |
0a032cbe JM |
1874 | } |
1875 | } | |
1876 | ||
daf4f96e JM |
1877 | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr) |
1878 | { | |
1879 | #if !defined(FLUSH_ALL_TLBS) | |
1880 | addr &= TARGET_PAGE_MASK; | |
1881 | switch (env->mmu_model) { | |
1882 | case POWERPC_MMU_SOFT_6xx: | |
7dbe11ac | 1883 | case POWERPC_MMU_SOFT_74xx: |
daf4f96e JM |
1884 | ppc6xx_tlb_invalidate_virt(env, addr, 0); |
1885 | if (env->id_tlbs == 1) | |
1886 | ppc6xx_tlb_invalidate_virt(env, addr, 1); | |
1887 | break; | |
1888 | case POWERPC_MMU_SOFT_4xx: | |
1889 | case POWERPC_MMU_SOFT_4xx_Z: | |
1890 | ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); | |
1891 | break; | |
7dbe11ac JM |
1892 | case POWERPC_MMU_REAL_4xx: |
1893 | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); | |
1894 | break; | |
1895 | case POWERPC_MMU_BOOKE: | |
1896 | /* XXX: TODO */ | |
1897 | cpu_abort(env, "MMU model not implemented\n"); | |
1898 | break; | |
1899 | case POWERPC_MMU_BOOKE_FSL: | |
1900 | /* XXX: TODO */ | |
7dbe11ac JM |
1901 | cpu_abort(env, "MMU model not implemented\n"); |
1902 | break; | |
1903 | case POWERPC_MMU_32B: | |
faadf50e | 1904 | case POWERPC_MMU_601: |
daf4f96e JM |
1905 | /* tlbie invalidate TLBs for all segments */ |
1906 | addr &= ~((target_ulong)-1 << 28); | |
1907 | /* XXX: this case should be optimized, | |
1908 | * giving a mask to tlb_flush_page | |
1909 | */ | |
1910 | tlb_flush_page(env, addr | (0x0 << 28)); | |
1911 | tlb_flush_page(env, addr | (0x1 << 28)); | |
1912 | tlb_flush_page(env, addr | (0x2 << 28)); | |
1913 | tlb_flush_page(env, addr | (0x3 << 28)); | |
1914 | tlb_flush_page(env, addr | (0x4 << 28)); | |
1915 | tlb_flush_page(env, addr | (0x5 << 28)); | |
1916 | tlb_flush_page(env, addr | (0x6 << 28)); | |
1917 | tlb_flush_page(env, addr | (0x7 << 28)); | |
1918 | tlb_flush_page(env, addr | (0x8 << 28)); | |
1919 | tlb_flush_page(env, addr | (0x9 << 28)); | |
1920 | tlb_flush_page(env, addr | (0xA << 28)); | |
1921 | tlb_flush_page(env, addr | (0xB << 28)); | |
1922 | tlb_flush_page(env, addr | (0xC << 28)); | |
1923 | tlb_flush_page(env, addr | (0xD << 28)); | |
1924 | tlb_flush_page(env, addr | (0xE << 28)); | |
1925 | tlb_flush_page(env, addr | (0xF << 28)); | |
7dbe11ac | 1926 | break; |
00af685f | 1927 | #if defined(TARGET_PPC64) |
7dbe11ac | 1928 | case POWERPC_MMU_64B: |
7dbe11ac JM |
1929 | /* tlbie invalidate TLBs for all segments */ |
1930 | /* XXX: given the fact that there are too many segments to invalidate, | |
00af685f | 1931 | * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu, |
7dbe11ac JM |
1932 | * we just invalidate all TLBs |
1933 | */ | |
1934 | tlb_flush(env, 1); | |
1935 | break; | |
00af685f JM |
1936 | #endif /* defined(TARGET_PPC64) */ |
1937 | default: | |
1938 | /* XXX: TODO */ | |
12de9a39 | 1939 | cpu_abort(env, "Unknown MMU model\n"); |
00af685f | 1940 | break; |
daf4f96e JM |
1941 | } |
1942 | #else | |
1943 | ppc_tlb_invalidate_all(env); | |
1944 | #endif | |
1945 | } | |
1946 | ||
3fc6c082 FB |
1947 | /*****************************************************************************/ |
1948 | /* Special registers manipulation */ | |
d9bce9d9 JM |
1949 | #if defined(TARGET_PPC64) |
1950 | target_ulong ppc_load_asr (CPUPPCState *env) | |
1951 | { | |
1952 | return env->asr; | |
1953 | } | |
1954 | ||
1955 | void ppc_store_asr (CPUPPCState *env, target_ulong value) | |
1956 | { | |
1957 | if (env->asr != value) { | |
1958 | env->asr = value; | |
1959 | tlb_flush(env, 1); | |
1960 | } | |
1961 | } | |
1962 | #endif | |
1963 | ||
3fc6c082 FB |
1964 | target_ulong do_load_sdr1 (CPUPPCState *env) |
1965 | { | |
1966 | return env->sdr1; | |
1967 | } | |
1968 | ||
1969 | void do_store_sdr1 (CPUPPCState *env, target_ulong value) | |
1970 | { | |
1971 | #if defined (DEBUG_MMU) | |
1972 | if (loglevel != 0) { | |
1b9eb036 | 1973 | fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value); |
3fc6c082 FB |
1974 | } |
1975 | #endif | |
1976 | if (env->sdr1 != value) { | |
12de9a39 JM |
1977 | /* XXX: for PowerPC 64, should check that the HTABSIZE value |
1978 | * is <= 28 | |
1979 | */ | |
3fc6c082 | 1980 | env->sdr1 = value; |
76a66253 | 1981 | tlb_flush(env, 1); |
3fc6c082 FB |
1982 | } |
1983 | } | |
1984 | ||
12de9a39 | 1985 | #if 0 // Unused |
3fc6c082 FB |
1986 | target_ulong do_load_sr (CPUPPCState *env, int srnum) |
1987 | { | |
1988 | return env->sr[srnum]; | |
1989 | } | |
12de9a39 | 1990 | #endif |
3fc6c082 FB |
1991 | |
1992 | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value) | |
1993 | { | |
1994 | #if defined (DEBUG_MMU) | |
1995 | if (loglevel != 0) { | |
1b9eb036 JM |
1996 | fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n", |
1997 | __func__, srnum, value, env->sr[srnum]); | |
3fc6c082 FB |
1998 | } |
1999 | #endif | |
2000 | if (env->sr[srnum] != value) { | |
2001 | env->sr[srnum] = value; | |
2002 | #if !defined(FLUSH_ALL_TLBS) && 0 | |
2003 | { | |
2004 | target_ulong page, end; | |
2005 | /* Invalidate 256 MB of virtual memory */ | |
2006 | page = (16 << 20) * srnum; | |
2007 | end = page + (16 << 20); | |
2008 | for (; page != end; page += TARGET_PAGE_SIZE) | |
2009 | tlb_flush_page(env, page); | |
2010 | } | |
2011 | #else | |
76a66253 | 2012 | tlb_flush(env, 1); |
3fc6c082 FB |
2013 | #endif |
2014 | } | |
2015 | } | |
76a66253 | 2016 | #endif /* !defined (CONFIG_USER_ONLY) */ |
3fc6c082 | 2017 | |
bfa1e5cf | 2018 | target_ulong ppc_load_xer (CPUPPCState *env) |
79aceca5 | 2019 | { |
0411a972 | 2020 | return hreg_load_xer(env); |
79aceca5 FB |
2021 | } |
2022 | ||
bfa1e5cf | 2023 | void ppc_store_xer (CPUPPCState *env, target_ulong value) |
79aceca5 | 2024 | { |
0411a972 | 2025 | hreg_store_xer(env, value); |
79aceca5 FB |
2026 | } |
2027 | ||
76a66253 | 2028 | /* GDBstub can read and write MSR... */ |
0411a972 | 2029 | void ppc_store_msr (CPUPPCState *env, target_ulong value) |
3fc6c082 | 2030 | { |
0411a972 | 2031 | hreg_store_msr(env, value); |
3fc6c082 FB |
2032 | } |
2033 | ||
2034 | /*****************************************************************************/ | |
2035 | /* Exception processing */ | |
18fba28c | 2036 | #if defined (CONFIG_USER_ONLY) |
9a64fbe4 | 2037 | void do_interrupt (CPUState *env) |
79aceca5 | 2038 | { |
e1833e1f JM |
2039 | env->exception_index = POWERPC_EXCP_NONE; |
2040 | env->error_code = 0; | |
18fba28c | 2041 | } |
47103572 | 2042 | |
e9df014c | 2043 | void ppc_hw_interrupt (CPUState *env) |
47103572 | 2044 | { |
e1833e1f JM |
2045 | env->exception_index = POWERPC_EXCP_NONE; |
2046 | env->error_code = 0; | |
47103572 | 2047 | } |
76a66253 | 2048 | #else /* defined (CONFIG_USER_ONLY) */ |
a11b8151 | 2049 | static always_inline void dump_syscall (CPUState *env) |
d094807b | 2050 | { |
d9bce9d9 | 2051 | fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX |
1b9eb036 | 2052 | " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n", |
d094807b FB |
2053 | env->gpr[0], env->gpr[3], env->gpr[4], |
2054 | env->gpr[5], env->gpr[6], env->nip); | |
2055 | } | |
2056 | ||
e1833e1f JM |
2057 | /* Note that this function should be greatly optimized |
2058 | * when called with a constant excp, from ppc_hw_interrupt | |
2059 | */ | |
2060 | static always_inline void powerpc_excp (CPUState *env, | |
2061 | int excp_model, int excp) | |
18fba28c | 2062 | { |
0411a972 | 2063 | target_ulong msr, new_msr, vector; |
e1833e1f | 2064 | int srr0, srr1, asrr0, asrr1; |
f9fdea6b JM |
2065 | #if defined(TARGET_PPC64H) |
2066 | int lpes0, lpes1, lev; | |
2067 | ||
2068 | lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; | |
2069 | lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; | |
2070 | #endif | |
79aceca5 | 2071 | |
b769d8fe | 2072 | if (loglevel & CPU_LOG_INT) { |
1b9eb036 JM |
2073 | fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
2074 | env->nip, excp, env->error_code); | |
b769d8fe | 2075 | } |
0411a972 JM |
2076 | msr = env->msr; |
2077 | new_msr = msr; | |
e1833e1f JM |
2078 | srr0 = SPR_SRR0; |
2079 | srr1 = SPR_SRR1; | |
2080 | asrr0 = -1; | |
2081 | asrr1 = -1; | |
2082 | msr &= ~((target_ulong)0x783F0000); | |
9a64fbe4 | 2083 | switch (excp) { |
e1833e1f JM |
2084 | case POWERPC_EXCP_NONE: |
2085 | /* Should never happen */ | |
2086 | return; | |
2087 | case POWERPC_EXCP_CRITICAL: /* Critical input */ | |
0411a972 | 2088 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f | 2089 | switch (excp_model) { |
a750fc0b | 2090 | case POWERPC_EXCP_40x: |
e1833e1f JM |
2091 | srr0 = SPR_40x_SRR2; |
2092 | srr1 = SPR_40x_SRR3; | |
c62db105 | 2093 | break; |
a750fc0b | 2094 | case POWERPC_EXCP_BOOKE: |
e1833e1f JM |
2095 | srr0 = SPR_BOOKE_CSRR0; |
2096 | srr1 = SPR_BOOKE_CSRR1; | |
c62db105 | 2097 | break; |
e1833e1f | 2098 | case POWERPC_EXCP_G2: |
c62db105 | 2099 | break; |
e1833e1f JM |
2100 | default: |
2101 | goto excp_invalid; | |
2be0071f | 2102 | } |
9a64fbe4 | 2103 | goto store_next; |
e1833e1f JM |
2104 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
2105 | if (msr_me == 0) { | |
e63ecc6f JM |
2106 | /* Machine check exception is not enabled. |
2107 | * Enter checkstop state. | |
2108 | */ | |
2109 | if (loglevel != 0) { | |
2110 | fprintf(logfile, "Machine check while not allowed. " | |
2111 | "Entering checkstop state\n"); | |
2112 | } else { | |
2113 | fprintf(stderr, "Machine check while not allowed. " | |
2114 | "Entering checkstop state\n"); | |
2115 | } | |
2116 | env->halted = 1; | |
2117 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
e1833e1f | 2118 | } |
0411a972 JM |
2119 | new_msr &= ~((target_ulong)1 << MSR_RI); |
2120 | new_msr &= ~((target_ulong)1 << MSR_ME); | |
e1833e1f | 2121 | #if defined(TARGET_PPC64H) |
0411a972 | 2122 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2123 | #endif |
2124 | /* XXX: should also have something loaded in DAR / DSISR */ | |
2125 | switch (excp_model) { | |
a750fc0b | 2126 | case POWERPC_EXCP_40x: |
e1833e1f JM |
2127 | srr0 = SPR_40x_SRR2; |
2128 | srr1 = SPR_40x_SRR3; | |
c62db105 | 2129 | break; |
a750fc0b | 2130 | case POWERPC_EXCP_BOOKE: |
e1833e1f JM |
2131 | srr0 = SPR_BOOKE_MCSRR0; |
2132 | srr1 = SPR_BOOKE_MCSRR1; | |
2133 | asrr0 = SPR_BOOKE_CSRR0; | |
2134 | asrr1 = SPR_BOOKE_CSRR1; | |
c62db105 JM |
2135 | break; |
2136 | default: | |
2137 | break; | |
2be0071f | 2138 | } |
e1833e1f JM |
2139 | goto store_next; |
2140 | case POWERPC_EXCP_DSI: /* Data storage exception */ | |
a541f297 | 2141 | #if defined (DEBUG_EXCEPTIONS) |
4a057712 | 2142 | if (loglevel != 0) { |
1b9eb036 JM |
2143 | fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX |
2144 | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]); | |
76a66253 | 2145 | } |
e1833e1f | 2146 | #endif |
0411a972 | 2147 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2148 | #if defined(TARGET_PPC64H) |
2149 | if (lpes1 == 0) | |
0411a972 | 2150 | new_msr |= (target_ulong)1 << MSR_HV; |
a541f297 FB |
2151 | #endif |
2152 | goto store_next; | |
e1833e1f | 2153 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
a541f297 | 2154 | #if defined (DEBUG_EXCEPTIONS) |
76a66253 | 2155 | if (loglevel != 0) { |
1b9eb036 JM |
2156 | fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX |
2157 | "\n", msr, env->nip); | |
76a66253 | 2158 | } |
a541f297 | 2159 | #endif |
0411a972 | 2160 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2161 | #if defined(TARGET_PPC64H) |
2162 | if (lpes1 == 0) | |
0411a972 | 2163 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2164 | #endif |
2165 | msr |= env->error_code; | |
9a64fbe4 | 2166 | goto store_next; |
e1833e1f | 2167 | case POWERPC_EXCP_EXTERNAL: /* External input */ |
0411a972 | 2168 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2169 | #if defined(TARGET_PPC64H) |
2170 | if (lpes0 == 1) | |
0411a972 | 2171 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f | 2172 | #endif |
9a64fbe4 | 2173 | goto store_next; |
e1833e1f | 2174 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
0411a972 | 2175 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2176 | #if defined(TARGET_PPC64H) |
2177 | if (lpes1 == 0) | |
0411a972 | 2178 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2179 | #endif |
2180 | /* XXX: this is false */ | |
2181 | /* Get rS/rD and rA from faulting opcode */ | |
2182 | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; | |
9a64fbe4 | 2183 | goto store_current; |
e1833e1f | 2184 | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
9a64fbe4 | 2185 | switch (env->error_code & ~0xF) { |
e1833e1f JM |
2186 | case POWERPC_EXCP_FP: |
2187 | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { | |
9a64fbe4 | 2188 | #if defined (DEBUG_EXCEPTIONS) |
4a057712 | 2189 | if (loglevel != 0) { |
a496775f JM |
2190 | fprintf(logfile, "Ignore floating point exception\n"); |
2191 | } | |
9a64fbe4 | 2192 | #endif |
7c58044c JM |
2193 | env->exception_index = POWERPC_EXCP_NONE; |
2194 | env->error_code = 0; | |
9a64fbe4 | 2195 | return; |
76a66253 | 2196 | } |
0411a972 | 2197 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2198 | #if defined(TARGET_PPC64H) |
2199 | if (lpes1 == 0) | |
0411a972 | 2200 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f | 2201 | #endif |
9a64fbe4 | 2202 | msr |= 0x00100000; |
5b52b991 JM |
2203 | if (msr_fe0 == msr_fe1) |
2204 | goto store_next; | |
2205 | msr |= 0x00010000; | |
76a66253 | 2206 | break; |
e1833e1f | 2207 | case POWERPC_EXCP_INVAL: |
a496775f | 2208 | #if defined (DEBUG_EXCEPTIONS) |
4a057712 | 2209 | if (loglevel != 0) { |
a496775f JM |
2210 | fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n", |
2211 | env->nip); | |
2212 | } | |
e1833e1f | 2213 | #endif |
0411a972 | 2214 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2215 | #if defined(TARGET_PPC64H) |
2216 | if (lpes1 == 0) | |
0411a972 | 2217 | new_msr |= (target_ulong)1 << MSR_HV; |
a496775f | 2218 | #endif |
9a64fbe4 | 2219 | msr |= 0x00080000; |
76a66253 | 2220 | break; |
e1833e1f | 2221 | case POWERPC_EXCP_PRIV: |
0411a972 | 2222 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2223 | #if defined(TARGET_PPC64H) |
2224 | if (lpes1 == 0) | |
0411a972 | 2225 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f | 2226 | #endif |
9a64fbe4 | 2227 | msr |= 0x00040000; |
76a66253 | 2228 | break; |
e1833e1f | 2229 | case POWERPC_EXCP_TRAP: |
0411a972 | 2230 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2231 | #if defined(TARGET_PPC64H) |
2232 | if (lpes1 == 0) | |
0411a972 | 2233 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f | 2234 | #endif |
9a64fbe4 FB |
2235 | msr |= 0x00020000; |
2236 | break; | |
2237 | default: | |
2238 | /* Should never occur */ | |
e1833e1f JM |
2239 | cpu_abort(env, "Invalid program exception %d. Aborting\n", |
2240 | env->error_code); | |
76a66253 JM |
2241 | break; |
2242 | } | |
5b52b991 | 2243 | goto store_current; |
e1833e1f | 2244 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
0411a972 | 2245 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2246 | #if defined(TARGET_PPC64H) |
2247 | if (lpes1 == 0) | |
0411a972 | 2248 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2249 | #endif |
2250 | goto store_current; | |
2251 | case POWERPC_EXCP_SYSCALL: /* System call exception */ | |
d094807b FB |
2252 | /* NOTE: this is a temporary hack to support graphics OSI |
2253 | calls from the MOL driver */ | |
e1833e1f | 2254 | /* XXX: To be removed */ |
d094807b FB |
2255 | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2256 | env->osi_call) { | |
7c58044c JM |
2257 | if (env->osi_call(env) != 0) { |
2258 | env->exception_index = POWERPC_EXCP_NONE; | |
2259 | env->error_code = 0; | |
d094807b | 2260 | return; |
7c58044c | 2261 | } |
d094807b | 2262 | } |
b769d8fe | 2263 | if (loglevel & CPU_LOG_INT) { |
d094807b | 2264 | dump_syscall(env); |
b769d8fe | 2265 | } |
0411a972 | 2266 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2267 | #if defined(TARGET_PPC64H) |
f9fdea6b | 2268 | lev = env->error_code; |
e1833e1f | 2269 | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
0411a972 | 2270 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2271 | #endif |
2272 | goto store_next; | |
2273 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ | |
0411a972 | 2274 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2275 | goto store_current; |
2276 | case POWERPC_EXCP_DECR: /* Decrementer exception */ | |
0411a972 | 2277 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2278 | #if defined(TARGET_PPC64H) |
2279 | if (lpes1 == 0) | |
0411a972 | 2280 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2281 | #endif |
2282 | goto store_next; | |
2283 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ | |
2284 | /* FIT on 4xx */ | |
2285 | #if defined (DEBUG_EXCEPTIONS) | |
2286 | if (loglevel != 0) | |
2287 | fprintf(logfile, "FIT exception\n"); | |
2288 | #endif | |
0411a972 | 2289 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
9a64fbe4 | 2290 | goto store_next; |
e1833e1f JM |
2291 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
2292 | #if defined (DEBUG_EXCEPTIONS) | |
2293 | if (loglevel != 0) | |
2294 | fprintf(logfile, "WDT exception\n"); | |
2295 | #endif | |
2296 | switch (excp_model) { | |
2297 | case POWERPC_EXCP_BOOKE: | |
2298 | srr0 = SPR_BOOKE_CSRR0; | |
2299 | srr1 = SPR_BOOKE_CSRR1; | |
2300 | break; | |
2301 | default: | |
2302 | break; | |
2303 | } | |
0411a972 | 2304 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2be0071f | 2305 | goto store_next; |
e1833e1f | 2306 | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
0411a972 | 2307 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2308 | goto store_next; |
2309 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ | |
0411a972 | 2310 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2311 | goto store_next; |
2312 | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ | |
2313 | switch (excp_model) { | |
2314 | case POWERPC_EXCP_BOOKE: | |
2315 | srr0 = SPR_BOOKE_DSRR0; | |
2316 | srr1 = SPR_BOOKE_DSRR1; | |
2317 | asrr0 = SPR_BOOKE_CSRR0; | |
2318 | asrr1 = SPR_BOOKE_CSRR1; | |
2319 | break; | |
2320 | default: | |
2321 | break; | |
2322 | } | |
2be0071f | 2323 | /* XXX: TODO */ |
e1833e1f | 2324 | cpu_abort(env, "Debug exception is not implemented yet !\n"); |
2be0071f | 2325 | goto store_next; |
e1833e1f JM |
2326 | #if defined(TARGET_PPCEMB) |
2327 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ | |
0411a972 | 2328 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2329 | goto store_current; |
2330 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ | |
2be0071f | 2331 | /* XXX: TODO */ |
e1833e1f | 2332 | cpu_abort(env, "Embedded floating point data exception " |
2be0071f FB |
2333 | "is not implemented yet !\n"); |
2334 | goto store_next; | |
e1833e1f | 2335 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2be0071f | 2336 | /* XXX: TODO */ |
e1833e1f JM |
2337 | cpu_abort(env, "Embedded floating point round exception " |
2338 | "is not implemented yet !\n"); | |
9a64fbe4 | 2339 | goto store_next; |
e1833e1f | 2340 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
0411a972 | 2341 | new_msr &= ~((target_ulong)1 << MSR_RI); |
2be0071f FB |
2342 | /* XXX: TODO */ |
2343 | cpu_abort(env, | |
e1833e1f | 2344 | "Performance counter exception is not implemented yet !\n"); |
9a64fbe4 | 2345 | goto store_next; |
e1833e1f | 2346 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
76a66253 | 2347 | /* XXX: TODO */ |
e1833e1f JM |
2348 | cpu_abort(env, |
2349 | "Embedded doorbell interrupt is not implemented yet !\n"); | |
2be0071f | 2350 | goto store_next; |
e1833e1f JM |
2351 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2352 | switch (excp_model) { | |
2353 | case POWERPC_EXCP_BOOKE: | |
2354 | srr0 = SPR_BOOKE_CSRR0; | |
2355 | srr1 = SPR_BOOKE_CSRR1; | |
a750fc0b | 2356 | break; |
2be0071f | 2357 | default: |
2be0071f FB |
2358 | break; |
2359 | } | |
e1833e1f JM |
2360 | /* XXX: TODO */ |
2361 | cpu_abort(env, "Embedded doorbell critical interrupt " | |
2362 | "is not implemented yet !\n"); | |
2363 | goto store_next; | |
2364 | #endif /* defined(TARGET_PPCEMB) */ | |
2365 | case POWERPC_EXCP_RESET: /* System reset exception */ | |
0411a972 | 2366 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2367 | #if defined(TARGET_PPC64H) |
0411a972 | 2368 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f | 2369 | #endif |
e1833e1f JM |
2370 | goto store_next; |
2371 | #if defined(TARGET_PPC64) | |
2372 | case POWERPC_EXCP_DSEG: /* Data segment exception */ | |
0411a972 | 2373 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2374 | #if defined(TARGET_PPC64H) |
2375 | if (lpes1 == 0) | |
0411a972 | 2376 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f | 2377 | #endif |
e1833e1f JM |
2378 | goto store_next; |
2379 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ | |
0411a972 | 2380 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2381 | #if defined(TARGET_PPC64H) |
2382 | if (lpes1 == 0) | |
0411a972 | 2383 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f | 2384 | #endif |
e1833e1f JM |
2385 | goto store_next; |
2386 | #endif /* defined(TARGET_PPC64) */ | |
2387 | #if defined(TARGET_PPC64H) | |
2388 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ | |
2389 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2390 | srr1 = SPR_HSRR1; |
0411a972 | 2391 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2392 | goto store_next; |
2393 | #endif | |
2394 | case POWERPC_EXCP_TRACE: /* Trace exception */ | |
0411a972 | 2395 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2396 | #if defined(TARGET_PPC64H) |
2397 | if (lpes1 == 0) | |
0411a972 | 2398 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2399 | #endif |
2400 | goto store_next; | |
2401 | #if defined(TARGET_PPC64H) | |
2402 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ | |
2403 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2404 | srr1 = SPR_HSRR1; |
0411a972 | 2405 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2406 | goto store_next; |
2407 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ | |
2408 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2409 | srr1 = SPR_HSRR1; |
0411a972 | 2410 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2411 | goto store_next; |
2412 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ | |
2413 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2414 | srr1 = SPR_HSRR1; |
0411a972 | 2415 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2416 | goto store_next; |
2417 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ | |
2418 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2419 | srr1 = SPR_HSRR1; |
0411a972 | 2420 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2421 | goto store_next; |
2422 | #endif /* defined(TARGET_PPC64H) */ | |
2423 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ | |
0411a972 | 2424 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2425 | #if defined(TARGET_PPC64H) |
2426 | if (lpes1 == 0) | |
0411a972 | 2427 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2428 | #endif |
2429 | goto store_current; | |
2430 | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ | |
a496775f | 2431 | #if defined (DEBUG_EXCEPTIONS) |
e1833e1f JM |
2432 | if (loglevel != 0) |
2433 | fprintf(logfile, "PIT exception\n"); | |
2434 | #endif | |
0411a972 | 2435 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2436 | goto store_next; |
2437 | case POWERPC_EXCP_IO: /* IO error exception */ | |
2438 | /* XXX: TODO */ | |
2439 | cpu_abort(env, "601 IO error exception is not implemented yet !\n"); | |
2440 | goto store_next; | |
2441 | case POWERPC_EXCP_RUNM: /* Run mode exception */ | |
2442 | /* XXX: TODO */ | |
2443 | cpu_abort(env, "601 run mode exception is not implemented yet !\n"); | |
2444 | goto store_next; | |
2445 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ | |
2446 | /* XXX: TODO */ | |
2447 | cpu_abort(env, "602 emulation trap exception " | |
2448 | "is not implemented yet !\n"); | |
2449 | goto store_next; | |
2450 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ | |
0411a972 | 2451 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2452 | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2453 | if (lpes1 == 0) | |
0411a972 | 2454 | new_msr |= (target_ulong)1 << MSR_HV; |
a496775f | 2455 | #endif |
e1833e1f | 2456 | switch (excp_model) { |
a750fc0b JM |
2457 | case POWERPC_EXCP_602: |
2458 | case POWERPC_EXCP_603: | |
2459 | case POWERPC_EXCP_603E: | |
2460 | case POWERPC_EXCP_G2: | |
e1833e1f | 2461 | goto tlb_miss_tgpr; |
a750fc0b | 2462 | case POWERPC_EXCP_7x5: |
76a66253 | 2463 | goto tlb_miss; |
7dbe11ac JM |
2464 | case POWERPC_EXCP_74xx: |
2465 | goto tlb_miss_74xx; | |
2be0071f | 2466 | default: |
e1833e1f | 2467 | cpu_abort(env, "Invalid instruction TLB miss exception\n"); |
2be0071f FB |
2468 | break; |
2469 | } | |
e1833e1f JM |
2470 | break; |
2471 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
0411a972 | 2472 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2473 | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2474 | if (lpes1 == 0) | |
0411a972 | 2475 | new_msr |= (target_ulong)1 << MSR_HV; |
a496775f | 2476 | #endif |
e1833e1f | 2477 | switch (excp_model) { |
a750fc0b JM |
2478 | case POWERPC_EXCP_602: |
2479 | case POWERPC_EXCP_603: | |
2480 | case POWERPC_EXCP_603E: | |
2481 | case POWERPC_EXCP_G2: | |
e1833e1f | 2482 | goto tlb_miss_tgpr; |
a750fc0b | 2483 | case POWERPC_EXCP_7x5: |
76a66253 | 2484 | goto tlb_miss; |
7dbe11ac JM |
2485 | case POWERPC_EXCP_74xx: |
2486 | goto tlb_miss_74xx; | |
2be0071f | 2487 | default: |
e1833e1f | 2488 | cpu_abort(env, "Invalid data load TLB miss exception\n"); |
2be0071f FB |
2489 | break; |
2490 | } | |
e1833e1f JM |
2491 | break; |
2492 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
0411a972 | 2493 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2494 | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2495 | if (lpes1 == 0) | |
0411a972 | 2496 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2497 | #endif |
2498 | switch (excp_model) { | |
a750fc0b JM |
2499 | case POWERPC_EXCP_602: |
2500 | case POWERPC_EXCP_603: | |
2501 | case POWERPC_EXCP_603E: | |
2502 | case POWERPC_EXCP_G2: | |
e1833e1f | 2503 | tlb_miss_tgpr: |
76a66253 | 2504 | /* Swap temporary saved registers with GPRs */ |
0411a972 JM |
2505 | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { |
2506 | new_msr |= (target_ulong)1 << MSR_TGPR; | |
2507 | hreg_swap_gpr_tgpr(env); | |
2508 | } | |
e1833e1f JM |
2509 | goto tlb_miss; |
2510 | case POWERPC_EXCP_7x5: | |
2511 | tlb_miss: | |
2be0071f FB |
2512 | #if defined (DEBUG_SOFTWARE_TLB) |
2513 | if (loglevel != 0) { | |
76a66253 JM |
2514 | const unsigned char *es; |
2515 | target_ulong *miss, *cmp; | |
2516 | int en; | |
1e6784f9 | 2517 | if (excp == POWERPC_EXCP_IFTLB) { |
76a66253 JM |
2518 | es = "I"; |
2519 | en = 'I'; | |
2520 | miss = &env->spr[SPR_IMISS]; | |
2521 | cmp = &env->spr[SPR_ICMP]; | |
2522 | } else { | |
1e6784f9 | 2523 | if (excp == POWERPC_EXCP_DLTLB) |
76a66253 JM |
2524 | es = "DL"; |
2525 | else | |
2526 | es = "DS"; | |
2527 | en = 'D'; | |
2528 | miss = &env->spr[SPR_DMISS]; | |
2529 | cmp = &env->spr[SPR_DCMP]; | |
2530 | } | |
1b9eb036 | 2531 | fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
4a057712 | 2532 | " H1 " ADDRX " H2 " ADDRX " %08x\n", |
1b9eb036 | 2533 | es, en, *miss, en, *cmp, |
76a66253 | 2534 | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2be0071f FB |
2535 | env->error_code); |
2536 | } | |
9a64fbe4 | 2537 | #endif |
2be0071f FB |
2538 | msr |= env->crf[0] << 28; |
2539 | msr |= env->error_code; /* key, D/I, S/L bits */ | |
2540 | /* Set way using a LRU mechanism */ | |
76a66253 | 2541 | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
c62db105 | 2542 | break; |
7dbe11ac JM |
2543 | case POWERPC_EXCP_74xx: |
2544 | tlb_miss_74xx: | |
2545 | #if defined (DEBUG_SOFTWARE_TLB) | |
2546 | if (loglevel != 0) { | |
2547 | const unsigned char *es; | |
2548 | target_ulong *miss, *cmp; | |
2549 | int en; | |
2550 | if (excp == POWERPC_EXCP_IFTLB) { | |
2551 | es = "I"; | |
2552 | en = 'I'; | |
0411a972 JM |
2553 | miss = &env->spr[SPR_TLBMISS]; |
2554 | cmp = &env->spr[SPR_PTEHI]; | |
7dbe11ac JM |
2555 | } else { |
2556 | if (excp == POWERPC_EXCP_DLTLB) | |
2557 | es = "DL"; | |
2558 | else | |
2559 | es = "DS"; | |
2560 | en = 'D'; | |
2561 | miss = &env->spr[SPR_TLBMISS]; | |
2562 | cmp = &env->spr[SPR_PTEHI]; | |
2563 | } | |
2564 | fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX | |
2565 | " %08x\n", | |
2566 | es, en, *miss, en, *cmp, env->error_code); | |
2567 | } | |
2568 | #endif | |
2569 | msr |= env->error_code; /* key bit */ | |
2570 | break; | |
2be0071f | 2571 | default: |
e1833e1f | 2572 | cpu_abort(env, "Invalid data store TLB miss exception\n"); |
2be0071f FB |
2573 | break; |
2574 | } | |
e1833e1f JM |
2575 | goto store_next; |
2576 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ | |
2577 | /* XXX: TODO */ | |
2578 | cpu_abort(env, "Floating point assist exception " | |
2579 | "is not implemented yet !\n"); | |
2580 | goto store_next; | |
2581 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ | |
2582 | /* XXX: TODO */ | |
2583 | cpu_abort(env, "IABR exception is not implemented yet !\n"); | |
2584 | goto store_next; | |
2585 | case POWERPC_EXCP_SMI: /* System management interrupt */ | |
2586 | /* XXX: TODO */ | |
2587 | cpu_abort(env, "SMI exception is not implemented yet !\n"); | |
2588 | goto store_next; | |
2589 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ | |
2590 | /* XXX: TODO */ | |
2591 | cpu_abort(env, "Thermal management exception " | |
2592 | "is not implemented yet !\n"); | |
2593 | goto store_next; | |
2594 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ | |
0411a972 | 2595 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2596 | #if defined(TARGET_PPC64H) |
2597 | if (lpes1 == 0) | |
0411a972 | 2598 | new_msr |= (target_ulong)1 << MSR_HV; |
e1833e1f JM |
2599 | #endif |
2600 | /* XXX: TODO */ | |
2601 | cpu_abort(env, | |
2602 | "Performance counter exception is not implemented yet !\n"); | |
2603 | goto store_next; | |
2604 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ | |
2605 | /* XXX: TODO */ | |
2606 | cpu_abort(env, "VPU assist exception is not implemented yet !\n"); | |
2607 | goto store_next; | |
2608 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ | |
2609 | /* XXX: TODO */ | |
2610 | cpu_abort(env, | |
2611 | "970 soft-patch exception is not implemented yet !\n"); | |
2612 | goto store_next; | |
2613 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ | |
2614 | /* XXX: TODO */ | |
2615 | cpu_abort(env, | |
2616 | "970 maintenance exception is not implemented yet !\n"); | |
2617 | goto store_next; | |
2be0071f | 2618 | default: |
e1833e1f JM |
2619 | excp_invalid: |
2620 | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp); | |
2621 | break; | |
9a64fbe4 | 2622 | store_current: |
2be0071f | 2623 | /* save current instruction location */ |
e1833e1f | 2624 | env->spr[srr0] = env->nip - 4; |
9a64fbe4 FB |
2625 | break; |
2626 | store_next: | |
2be0071f | 2627 | /* save next instruction location */ |
e1833e1f | 2628 | env->spr[srr0] = env->nip; |
9a64fbe4 FB |
2629 | break; |
2630 | } | |
e1833e1f JM |
2631 | /* Save MSR */ |
2632 | env->spr[srr1] = msr; | |
2633 | /* If any alternate SRR register are defined, duplicate saved values */ | |
2634 | if (asrr0 != -1) | |
2635 | env->spr[asrr0] = env->spr[srr0]; | |
2636 | if (asrr1 != -1) | |
2637 | env->spr[asrr1] = env->spr[srr1]; | |
2be0071f | 2638 | /* If we disactivated any translation, flush TLBs */ |
0411a972 | 2639 | if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) |
2be0071f | 2640 | tlb_flush(env, 1); |
9a64fbe4 | 2641 | /* reload MSR with correct bits */ |
0411a972 JM |
2642 | new_msr &= ~((target_ulong)1 << MSR_EE); |
2643 | new_msr &= ~((target_ulong)1 << MSR_PR); | |
2644 | new_msr &= ~((target_ulong)1 << MSR_FP); | |
2645 | new_msr &= ~((target_ulong)1 << MSR_FE0); | |
2646 | new_msr &= ~((target_ulong)1 << MSR_SE); | |
2647 | new_msr &= ~((target_ulong)1 << MSR_BE); | |
2648 | new_msr &= ~((target_ulong)1 << MSR_FE1); | |
2649 | new_msr &= ~((target_ulong)1 << MSR_IR); | |
2650 | new_msr &= ~((target_ulong)1 << MSR_DR); | |
e1833e1f | 2651 | #if 0 /* Fix this: not on all targets */ |
0411a972 | 2652 | new_msr &= ~((target_ulong)1 << MSR_PMM); |
e1833e1f | 2653 | #endif |
0411a972 JM |
2654 | new_msr &= ~((target_ulong)1 << MSR_LE); |
2655 | if (msr_ile) | |
2656 | new_msr |= (target_ulong)1 << MSR_LE; | |
2657 | else | |
2658 | new_msr &= ~((target_ulong)1 << MSR_LE); | |
e1833e1f JM |
2659 | /* Jump to handler */ |
2660 | vector = env->excp_vectors[excp]; | |
2661 | if (vector == (target_ulong)-1) { | |
2662 | cpu_abort(env, "Raised an exception without defined vector %d\n", | |
2663 | excp); | |
2664 | } | |
2665 | vector |= env->excp_prefix; | |
c62db105 | 2666 | #if defined(TARGET_PPC64) |
e1833e1f | 2667 | if (excp_model == POWERPC_EXCP_BOOKE) { |
0411a972 JM |
2668 | if (!msr_icm) { |
2669 | new_msr &= ~((target_ulong)1 << MSR_CM); | |
e1833e1f | 2670 | vector = (uint32_t)vector; |
0411a972 JM |
2671 | } else { |
2672 | new_msr |= (target_ulong)1 << MSR_CM; | |
2673 | } | |
c62db105 | 2674 | } else { |
0411a972 JM |
2675 | if (!msr_isf) { |
2676 | new_msr &= ~((target_ulong)1 << MSR_SF); | |
e1833e1f | 2677 | vector = (uint32_t)vector; |
0411a972 JM |
2678 | } else { |
2679 | new_msr |= (target_ulong)1 << MSR_SF; | |
2680 | } | |
c62db105 | 2681 | } |
e1833e1f | 2682 | #endif |
0411a972 JM |
2683 | /* XXX: we don't use hreg_store_msr here as already have treated |
2684 | * any special case that could occur. Just store MSR and update hflags | |
2685 | */ | |
2686 | env->msr = new_msr; | |
2687 | hreg_compute_hflags(env); | |
e1833e1f JM |
2688 | env->nip = vector; |
2689 | /* Reset exception state */ | |
2690 | env->exception_index = POWERPC_EXCP_NONE; | |
2691 | env->error_code = 0; | |
fb0eaffc | 2692 | } |
47103572 | 2693 | |
e1833e1f | 2694 | void do_interrupt (CPUState *env) |
47103572 | 2695 | { |
e1833e1f JM |
2696 | powerpc_excp(env, env->excp_model, env->exception_index); |
2697 | } | |
47103572 | 2698 | |
e1833e1f JM |
2699 | void ppc_hw_interrupt (CPUPPCState *env) |
2700 | { | |
f9fdea6b JM |
2701 | #if defined(TARGET_PPC64H) |
2702 | int hdice; | |
2703 | #endif | |
2704 | ||
0411a972 | 2705 | #if 0 |
a496775f JM |
2706 | if (loglevel & CPU_LOG_INT) { |
2707 | fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n", | |
2708 | __func__, env, env->pending_interrupts, | |
0411a972 | 2709 | env->interrupt_request, (int)msr_me, (int)msr_ee); |
a496775f | 2710 | } |
47103572 | 2711 | #endif |
e1833e1f | 2712 | /* External reset */ |
47103572 | 2713 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
47103572 | 2714 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); |
e1833e1f JM |
2715 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2716 | return; | |
2717 | } | |
2718 | /* Machine check exception */ | |
2719 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { | |
2720 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); | |
2721 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); | |
2722 | return; | |
47103572 | 2723 | } |
e1833e1f JM |
2724 | #if 0 /* TODO */ |
2725 | /* External debug exception */ | |
2726 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { | |
2727 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); | |
2728 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG); | |
2729 | return; | |
2730 | } | |
2731 | #endif | |
2732 | #if defined(TARGET_PPC64H) | |
f9fdea6b JM |
2733 | hdice = env->spr[SPR_LPCR] & 1; |
2734 | if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { | |
47103572 JM |
2735 | /* Hypervisor decrementer exception */ |
2736 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { | |
47103572 | 2737 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); |
e1833e1f JM |
2738 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2739 | return; | |
2740 | } | |
2741 | } | |
2742 | #endif | |
2743 | if (msr_ce != 0) { | |
2744 | /* External critical interrupt */ | |
2745 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { | |
2746 | /* Taking a critical external interrupt does not clear the external | |
2747 | * critical interrupt status | |
2748 | */ | |
2749 | #if 0 | |
2750 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT); | |
47103572 | 2751 | #endif |
e1833e1f JM |
2752 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2753 | return; | |
2754 | } | |
2755 | } | |
2756 | if (msr_ee != 0) { | |
2757 | /* Watchdog timer on embedded PowerPC */ | |
2758 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { | |
2759 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); | |
2760 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); | |
2761 | return; | |
2762 | } | |
2763 | #if defined(TARGET_PPCEMB) | |
2764 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { | |
2765 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL); | |
2766 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); | |
2767 | return; | |
2768 | } | |
2769 | #endif | |
2770 | #if defined(TARGET_PPCEMB) | |
2771 | /* External interrupt */ | |
2772 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { | |
2773 | /* Taking an external interrupt does not clear the external | |
2774 | * interrupt status | |
2775 | */ | |
2776 | #if 0 | |
2777 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT); | |
2778 | #endif | |
2779 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); | |
2780 | return; | |
2781 | } | |
2782 | #endif | |
2783 | /* Fixed interval timer on embedded PowerPC */ | |
2784 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { | |
2785 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); | |
2786 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); | |
2787 | return; | |
2788 | } | |
2789 | /* Programmable interval timer on embedded PowerPC */ | |
2790 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { | |
2791 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); | |
2792 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); | |
2793 | return; | |
2794 | } | |
47103572 JM |
2795 | /* Decrementer exception */ |
2796 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { | |
47103572 | 2797 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); |
e1833e1f JM |
2798 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2799 | return; | |
2800 | } | |
2801 | #if !defined(TARGET_PPCEMB) | |
47103572 | 2802 | /* External interrupt */ |
e1833e1f | 2803 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
e9df014c JM |
2804 | /* Taking an external interrupt does not clear the external |
2805 | * interrupt status | |
2806 | */ | |
2807 | #if 0 | |
47103572 | 2808 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT); |
e9df014c | 2809 | #endif |
e1833e1f JM |
2810 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2811 | return; | |
2812 | } | |
d0dfae6e | 2813 | #endif |
e1833e1f JM |
2814 | #if defined(TARGET_PPCEMB) |
2815 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { | |
2816 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); | |
2817 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); | |
2818 | return; | |
47103572 | 2819 | } |
47103572 | 2820 | #endif |
e1833e1f JM |
2821 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2822 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM); | |
2823 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); | |
2824 | return; | |
2825 | } | |
2826 | /* Thermal interrupt */ | |
2827 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { | |
2828 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM); | |
2829 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); | |
2830 | return; | |
2831 | } | |
47103572 | 2832 | } |
47103572 | 2833 | } |
18fba28c | 2834 | #endif /* !CONFIG_USER_ONLY */ |
a496775f JM |
2835 | |
2836 | void cpu_dump_EA (target_ulong EA) | |
2837 | { | |
2838 | FILE *f; | |
2839 | ||
2840 | if (logfile) { | |
2841 | f = logfile; | |
2842 | } else { | |
2843 | f = stdout; | |
2844 | return; | |
2845 | } | |
4a057712 JM |
2846 | fprintf(f, "Memory access at address " ADDRX "\n", EA); |
2847 | } | |
2848 | ||
2849 | void cpu_dump_rfi (target_ulong RA, target_ulong msr) | |
2850 | { | |
2851 | FILE *f; | |
2852 | ||
2853 | if (logfile) { | |
2854 | f = logfile; | |
2855 | } else { | |
2856 | f = stdout; | |
2857 | return; | |
2858 | } | |
2859 | fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n", | |
2860 | RA, msr); | |
a496775f JM |
2861 | } |
2862 | ||
0a032cbe JM |
2863 | void cpu_ppc_reset (void *opaque) |
2864 | { | |
2865 | CPUPPCState *env; | |
0411a972 | 2866 | target_ulong msr; |
0a032cbe JM |
2867 | |
2868 | env = opaque; | |
0411a972 | 2869 | msr = (target_ulong)0; |
5eb7995e | 2870 | #if defined(TARGET_PPC64) |
0411a972 | 2871 | msr |= (target_ulong)0 << MSR_HV; /* Should be 1... */ |
5eb7995e | 2872 | #endif |
0411a972 JM |
2873 | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
2874 | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ | |
2875 | msr |= (target_ulong)1 << MSR_EP; | |
0a032cbe JM |
2876 | #if defined (DO_SINGLE_STEP) && 0 |
2877 | /* Single step trace mode */ | |
0411a972 JM |
2878 | msr |= (target_ulong)1 << MSR_SE; |
2879 | msr |= (target_ulong)1 << MSR_BE; | |
0a032cbe JM |
2880 | #endif |
2881 | #if defined(CONFIG_USER_ONLY) | |
0411a972 JM |
2882 | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
2883 | msr |= (target_ulong)1 << MSR_PR; | |
fe33cc71 | 2884 | #else |
1c27f8fb | 2885 | env->nip = env->hreset_vector | env->excp_prefix; |
141c8ae2 JM |
2886 | if (env->mmu_model != POWERPC_MMU_REAL_4xx) |
2887 | ppc_tlb_invalidate_all(env); | |
0a032cbe | 2888 | #endif |
0411a972 JM |
2889 | env->msr = msr; |
2890 | hreg_compute_hflags(env); | |
0a032cbe | 2891 | env->reserve = -1; |
5eb7995e JM |
2892 | /* Be sure no exception or interrupt is pending */ |
2893 | env->pending_interrupts = 0; | |
e1833e1f JM |
2894 | env->exception_index = POWERPC_EXCP_NONE; |
2895 | env->error_code = 0; | |
5eb7995e JM |
2896 | /* Flush all TLBs */ |
2897 | tlb_flush(env, 1); | |
0a032cbe JM |
2898 | } |
2899 | ||
2900 | CPUPPCState *cpu_ppc_init (void) | |
2901 | { | |
2902 | CPUPPCState *env; | |
2903 | ||
2904 | env = qemu_mallocz(sizeof(CPUPPCState)); | |
2905 | if (!env) | |
2906 | return NULL; | |
2907 | cpu_exec_init(env); | |
0a032cbe JM |
2908 | |
2909 | return env; | |
2910 | } | |
2911 | ||
2912 | void cpu_ppc_close (CPUPPCState *env) | |
2913 | { | |
2914 | /* Should also remove all opcode tables... */ | |
2915 | free(env); | |
2916 | } |