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9a64fbe4 | 1 | /* |
2f5a189c | 2 | * PowerPC memory access emulation helpers for QEMU. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
9a64fbe4 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
9a64fbe4 | 18 | */ |
3e457172 | 19 | #include "cpu.h" |
603fccce | 20 | #include "host-utils.h" |
a7812ae4 | 21 | #include "helper.h" |
9a64fbe4 | 22 | |
0411a972 | 23 | #include "helper_regs.h" |
0487d6a8 | 24 | |
3e457172 BS |
25 | #if !defined(CONFIG_USER_ONLY) |
26 | #include "softmmu_exec.h" | |
27 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
28 | ||
fdabc366 | 29 | //#define DEBUG_OP |
d12d51d5 | 30 | |
ff4a62cd AJ |
31 | /*****************************************************************************/ |
32 | /* Memory load and stores */ | |
33 | ||
2f5a189c BS |
34 | static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr, |
35 | target_long arg) | |
ff4a62cd AJ |
36 | { |
37 | #if defined(TARGET_PPC64) | |
e42a61f1 | 38 | if (!msr_is_64bit(env, env->msr)) { |
b327c654 BS |
39 | return (uint32_t)(addr + arg); |
40 | } else | |
ff4a62cd | 41 | #endif |
b327c654 BS |
42 | { |
43 | return addr + arg; | |
44 | } | |
ff4a62cd AJ |
45 | } |
46 | ||
2f5a189c | 47 | void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) |
ff4a62cd | 48 | { |
76db3ba4 | 49 | for (; reg < 32; reg++) { |
b327c654 | 50 | if (msr_le) { |
2f5a189c | 51 | env->gpr[reg] = bswap32(cpu_ldl_data(env, addr)); |
b327c654 | 52 | } else { |
2f5a189c | 53 | env->gpr[reg] = cpu_ldl_data(env, addr); |
b327c654 | 54 | } |
2f5a189c | 55 | addr = addr_add(env, addr, 4); |
ff4a62cd AJ |
56 | } |
57 | } | |
58 | ||
2f5a189c | 59 | void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) |
ff4a62cd | 60 | { |
76db3ba4 | 61 | for (; reg < 32; reg++) { |
b327c654 | 62 | if (msr_le) { |
2f5a189c | 63 | cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg])); |
b327c654 | 64 | } else { |
2f5a189c | 65 | cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]); |
b327c654 | 66 | } |
2f5a189c | 67 | addr = addr_add(env, addr, 4); |
ff4a62cd AJ |
68 | } |
69 | } | |
70 | ||
2f5a189c | 71 | void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) |
dfbc799d AJ |
72 | { |
73 | int sh; | |
b327c654 | 74 | |
76db3ba4 | 75 | for (; nb > 3; nb -= 4) { |
2f5a189c | 76 | env->gpr[reg] = cpu_ldl_data(env, addr); |
dfbc799d | 77 | reg = (reg + 1) % 32; |
2f5a189c | 78 | addr = addr_add(env, addr, 4); |
dfbc799d AJ |
79 | } |
80 | if (unlikely(nb > 0)) { | |
81 | env->gpr[reg] = 0; | |
76db3ba4 | 82 | for (sh = 24; nb > 0; nb--, sh -= 8) { |
2f5a189c BS |
83 | env->gpr[reg] |= cpu_ldub_data(env, addr) << sh; |
84 | addr = addr_add(env, addr, 1); | |
dfbc799d AJ |
85 | } |
86 | } | |
87 | } | |
88 | /* PPC32 specification says we must generate an exception if | |
89 | * rA is in the range of registers to be loaded. | |
90 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
91 | * For now, I'll follow the spec... | |
92 | */ | |
2f5a189c BS |
93 | void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, |
94 | uint32_t ra, uint32_t rb) | |
dfbc799d AJ |
95 | { |
96 | if (likely(xer_bc != 0)) { | |
97 | if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) || | |
98 | (reg < rb && (reg + xer_bc) > rb))) { | |
e5f17ac6 | 99 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
e06fcd75 AJ |
100 | POWERPC_EXCP_INVAL | |
101 | POWERPC_EXCP_INVAL_LSWX); | |
dfbc799d | 102 | } else { |
2f5a189c | 103 | helper_lsw(env, addr, xer_bc, reg); |
dfbc799d AJ |
104 | } |
105 | } | |
106 | } | |
107 | ||
2f5a189c BS |
108 | void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, |
109 | uint32_t reg) | |
dfbc799d AJ |
110 | { |
111 | int sh; | |
b327c654 | 112 | |
76db3ba4 | 113 | for (; nb > 3; nb -= 4) { |
2f5a189c | 114 | cpu_stl_data(env, addr, env->gpr[reg]); |
dfbc799d | 115 | reg = (reg + 1) % 32; |
2f5a189c | 116 | addr = addr_add(env, addr, 4); |
dfbc799d AJ |
117 | } |
118 | if (unlikely(nb > 0)) { | |
a16b45e7 | 119 | for (sh = 24; nb > 0; nb--, sh -= 8) { |
2f5a189c BS |
120 | cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF); |
121 | addr = addr_add(env, addr, 1); | |
a16b45e7 | 122 | } |
dfbc799d AJ |
123 | } |
124 | } | |
125 | ||
2f5a189c | 126 | static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size) |
799a8c8d | 127 | { |
799a8c8d | 128 | int i; |
b327c654 BS |
129 | |
130 | addr &= ~(dcache_line_size - 1); | |
131 | for (i = 0; i < dcache_line_size; i += 4) { | |
2f5a189c | 132 | cpu_stl_data(env, addr + i, 0); |
799a8c8d | 133 | } |
b327c654 | 134 | if (env->reserve_addr == addr) { |
18b21a2f | 135 | env->reserve_addr = (target_ulong)-1ULL; |
b327c654 | 136 | } |
799a8c8d AJ |
137 | } |
138 | ||
2f5a189c | 139 | void helper_dcbz(CPUPPCState *env, target_ulong addr) |
799a8c8d | 140 | { |
2f5a189c | 141 | do_dcbz(env, addr, env->dcache_line_size); |
799a8c8d AJ |
142 | } |
143 | ||
2f5a189c | 144 | void helper_dcbz_970(CPUPPCState *env, target_ulong addr) |
799a8c8d | 145 | { |
b327c654 | 146 | if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { |
2f5a189c | 147 | do_dcbz(env, addr, 32); |
b327c654 | 148 | } else { |
2f5a189c | 149 | do_dcbz(env, addr, env->dcache_line_size); |
b327c654 | 150 | } |
799a8c8d AJ |
151 | } |
152 | ||
2f5a189c | 153 | void helper_icbi(CPUPPCState *env, target_ulong addr) |
37d269df | 154 | { |
76db3ba4 | 155 | addr &= ~(env->dcache_line_size - 1); |
37d269df AJ |
156 | /* Invalidate one cache line : |
157 | * PowerPC specification says this is to be treated like a load | |
158 | * (not a fetch) by the MMU. To be sure it will be so, | |
159 | * do the load "by hand". | |
160 | */ | |
2f5a189c | 161 | cpu_ldl_data(env, addr); |
37d269df AJ |
162 | } |
163 | ||
b327c654 | 164 | /* XXX: to be tested */ |
2f5a189c BS |
165 | target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, |
166 | uint32_t ra, uint32_t rb) | |
bdb4b689 AJ |
167 | { |
168 | int i, c, d; | |
b327c654 | 169 | |
bdb4b689 AJ |
170 | d = 24; |
171 | for (i = 0; i < xer_bc; i++) { | |
2f5a189c BS |
172 | c = cpu_ldub_data(env, addr); |
173 | addr = addr_add(env, addr, 1); | |
bdb4b689 AJ |
174 | /* ra (if not 0) and rb are never modified */ |
175 | if (likely(reg != rb && (ra == 0 || reg != ra))) { | |
176 | env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d); | |
177 | } | |
b327c654 | 178 | if (unlikely(c == xer_cmp)) { |
bdb4b689 | 179 | break; |
b327c654 | 180 | } |
bdb4b689 AJ |
181 | if (likely(d != 0)) { |
182 | d -= 8; | |
183 | } else { | |
184 | d = 24; | |
185 | reg++; | |
186 | reg = reg & 0x1F; | |
187 | } | |
188 | } | |
189 | return i; | |
190 | } | |
191 | ||
d6a46fe8 AJ |
192 | /*****************************************************************************/ |
193 | /* Altivec extension helpers */ | |
e2542fe2 | 194 | #if defined(HOST_WORDS_BIGENDIAN) |
d6a46fe8 AJ |
195 | #define HI_IDX 0 |
196 | #define LO_IDX 1 | |
197 | #else | |
198 | #define HI_IDX 1 | |
199 | #define LO_IDX 0 | |
200 | #endif | |
201 | ||
cbfb6ae9 | 202 | #define LVE(name, access, swap, element) \ |
2f5a189c BS |
203 | void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ |
204 | target_ulong addr) \ | |
cbfb6ae9 AJ |
205 | { \ |
206 | size_t n_elems = ARRAY_SIZE(r->element); \ | |
b327c654 | 207 | int adjust = HI_IDX*(n_elems - 1); \ |
cbfb6ae9 AJ |
208 | int sh = sizeof(r->element[0]) >> 1; \ |
209 | int index = (addr & 0xf) >> sh; \ | |
b327c654 BS |
210 | \ |
211 | if (msr_le) { \ | |
212 | r->element[LO_IDX ? index : (adjust - index)] = \ | |
2f5a189c | 213 | swap(access(env, addr)); \ |
b327c654 BS |
214 | } else { \ |
215 | r->element[LO_IDX ? index : (adjust - index)] = \ | |
2f5a189c | 216 | access(env, addr); \ |
b327c654 | 217 | } \ |
cbfb6ae9 AJ |
218 | } |
219 | #define I(x) (x) | |
2f5a189c BS |
220 | LVE(lvebx, cpu_ldub_data, I, u8) |
221 | LVE(lvehx, cpu_lduw_data, bswap16, u16) | |
222 | LVE(lvewx, cpu_ldl_data, bswap32, u32) | |
cbfb6ae9 AJ |
223 | #undef I |
224 | #undef LVE | |
225 | ||
b327c654 | 226 | #define STVE(name, access, swap, element) \ |
2f5a189c BS |
227 | void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ |
228 | target_ulong addr) \ | |
b327c654 BS |
229 | { \ |
230 | size_t n_elems = ARRAY_SIZE(r->element); \ | |
231 | int adjust = HI_IDX * (n_elems - 1); \ | |
232 | int sh = sizeof(r->element[0]) >> 1; \ | |
233 | int index = (addr & 0xf) >> sh; \ | |
234 | \ | |
235 | if (msr_le) { \ | |
2f5a189c BS |
236 | access(env, addr, swap(r->element[LO_IDX ? index : \ |
237 | (adjust - index)])); \ | |
cbfb6ae9 | 238 | } else { \ |
2f5a189c BS |
239 | access(env, addr, r->element[LO_IDX ? index : \ |
240 | (adjust - index)]); \ | |
cbfb6ae9 AJ |
241 | } \ |
242 | } | |
243 | #define I(x) (x) | |
2f5a189c BS |
244 | STVE(stvebx, cpu_stb_data, I, u8) |
245 | STVE(stvehx, cpu_stw_data, bswap16, u16) | |
246 | STVE(stvewx, cpu_stl_data, bswap32, u32) | |
cbfb6ae9 AJ |
247 | #undef I |
248 | #undef LVE | |
249 | ||
d6a46fe8 AJ |
250 | #undef HI_IDX |
251 | #undef LO_IDX | |
252 | ||
fdabc366 FB |
253 | /*****************************************************************************/ |
254 | /* Softmmu support */ | |
b327c654 | 255 | #if !defined(CONFIG_USER_ONLY) |
fdabc366 FB |
256 | |
257 | #define MMUSUFFIX _mmu | |
fdabc366 FB |
258 | |
259 | #define SHIFT 0 | |
260 | #include "softmmu_template.h" | |
261 | ||
262 | #define SHIFT 1 | |
263 | #include "softmmu_template.h" | |
264 | ||
265 | #define SHIFT 2 | |
266 | #include "softmmu_template.h" | |
267 | ||
268 | #define SHIFT 3 | |
269 | #include "softmmu_template.h" | |
270 | ||
271 | /* try to fill the TLB and return an exception if error. If retaddr is | |
272 | NULL, it means that the function was called in C code (i.e. not | |
273 | from generated code or from helper.c) */ | |
274 | /* XXX: fix it to restore all registers */ | |
2f5a189c | 275 | void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, |
20503968 | 276 | uintptr_t retaddr) |
fdabc366 FB |
277 | { |
278 | TranslationBlock *tb; | |
fdabc366 FB |
279 | int ret; |
280 | ||
97b348e7 | 281 | ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx); |
76a66253 | 282 | if (unlikely(ret != 0)) { |
fdabc366 FB |
283 | if (likely(retaddr)) { |
284 | /* now we have a real cpu fault */ | |
20503968 | 285 | tb = tb_find_pc(retaddr); |
fdabc366 FB |
286 | if (likely(tb)) { |
287 | /* the PC is inside the translated code. It means that we have | |
288 | a virtual CPU fault */ | |
20503968 | 289 | cpu_restore_state(tb, env, retaddr); |
76a66253 | 290 | } |
fdabc366 | 291 | } |
e5f17ac6 | 292 | helper_raise_exception_err(env, env->exception_index, env->error_code); |
fdabc366 | 293 | } |
9a64fbe4 | 294 | } |
76a66253 | 295 | #endif /* !CONFIG_USER_ONLY */ |