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10b46525 DG |
1 | /* |
2 | * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * Copyright (c) 2013 David Gibson, IBM Corporation | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | #include "cpu.h" | |
21 | #include "helper.h" | |
22 | #include "sysemu/kvm.h" | |
23 | #include "kvm_ppc.h" | |
24 | #include "mmu-hash64.h" | |
25 | ||
9d7c3f4a | 26 | //#define DEBUG_MMU |
10b46525 DG |
27 | //#define DEBUG_SLB |
28 | ||
9d7c3f4a DG |
29 | #ifdef DEBUG_MMU |
30 | # define LOG_MMU(...) qemu_log(__VA_ARGS__) | |
31 | # define LOG_MMU_STATE(env) log_cpu_state((env), 0) | |
32 | #else | |
33 | # define LOG_MMU(...) do { } while (0) | |
34 | # define LOG_MMU_STATE(...) do { } while (0) | |
35 | #endif | |
36 | ||
10b46525 DG |
37 | #ifdef DEBUG_SLB |
38 | # define LOG_SLB(...) qemu_log(__VA_ARGS__) | |
39 | #else | |
40 | # define LOG_SLB(...) do { } while (0) | |
41 | #endif | |
42 | ||
5dc68eb0 DG |
43 | struct mmu_ctx_hash64 { |
44 | hwaddr raddr; /* Real address */ | |
5dc68eb0 | 45 | int prot; /* Protection bits */ |
5dc68eb0 DG |
46 | }; |
47 | ||
10b46525 DG |
48 | /* |
49 | * SLB handling | |
50 | */ | |
51 | ||
0480884f | 52 | static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr) |
10b46525 DG |
53 | { |
54 | uint64_t esid_256M, esid_1T; | |
55 | int n; | |
56 | ||
57 | LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); | |
58 | ||
59 | esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; | |
60 | esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; | |
61 | ||
62 | for (n = 0; n < env->slb_nr; n++) { | |
63 | ppc_slb_t *slb = &env->slb[n]; | |
64 | ||
65 | LOG_SLB("%s: slot %d %016" PRIx64 " %016" | |
66 | PRIx64 "\n", __func__, n, slb->esid, slb->vsid); | |
67 | /* We check for 1T matches on all MMUs here - if the MMU | |
68 | * doesn't have 1T segment support, we will have prevented 1T | |
69 | * entries from being inserted in the slbmte code. */ | |
70 | if (((slb->esid == esid_256M) && | |
71 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M)) | |
72 | || ((slb->esid == esid_1T) && | |
73 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) { | |
74 | return slb; | |
75 | } | |
76 | } | |
77 | ||
78 | return NULL; | |
79 | } | |
80 | ||
81 | void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) | |
82 | { | |
83 | int i; | |
84 | uint64_t slbe, slbv; | |
85 | ||
86 | cpu_synchronize_state(env); | |
87 | ||
88 | cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n"); | |
89 | for (i = 0; i < env->slb_nr; i++) { | |
90 | slbe = env->slb[i].esid; | |
91 | slbv = env->slb[i].vsid; | |
92 | if (slbe == 0 && slbv == 0) { | |
93 | continue; | |
94 | } | |
95 | cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", | |
96 | i, slbe, slbv); | |
97 | } | |
98 | } | |
99 | ||
100 | void helper_slbia(CPUPPCState *env) | |
101 | { | |
102 | int n, do_invalidate; | |
103 | ||
104 | do_invalidate = 0; | |
105 | /* XXX: Warning: slbia never invalidates the first segment */ | |
106 | for (n = 1; n < env->slb_nr; n++) { | |
107 | ppc_slb_t *slb = &env->slb[n]; | |
108 | ||
109 | if (slb->esid & SLB_ESID_V) { | |
110 | slb->esid &= ~SLB_ESID_V; | |
111 | /* XXX: given the fact that segment size is 256 MB or 1TB, | |
112 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
113 | * in QEMU, we just invalidate all TLBs | |
114 | */ | |
115 | do_invalidate = 1; | |
116 | } | |
117 | } | |
118 | if (do_invalidate) { | |
119 | tlb_flush(env, 1); | |
120 | } | |
121 | } | |
122 | ||
123 | void helper_slbie(CPUPPCState *env, target_ulong addr) | |
124 | { | |
125 | ppc_slb_t *slb; | |
126 | ||
127 | slb = slb_lookup(env, addr); | |
128 | if (!slb) { | |
129 | return; | |
130 | } | |
131 | ||
132 | if (slb->esid & SLB_ESID_V) { | |
133 | slb->esid &= ~SLB_ESID_V; | |
134 | ||
135 | /* XXX: given the fact that segment size is 256 MB or 1TB, | |
136 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
137 | * in QEMU, we just invalidate all TLBs | |
138 | */ | |
139 | tlb_flush(env, 1); | |
140 | } | |
141 | } | |
142 | ||
143 | int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) | |
144 | { | |
145 | int slot = rb & 0xfff; | |
146 | ppc_slb_t *slb = &env->slb[slot]; | |
147 | ||
148 | if (rb & (0x1000 - env->slb_nr)) { | |
149 | return -1; /* Reserved bits set or slot too high */ | |
150 | } | |
151 | if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) { | |
152 | return -1; /* Bad segment size */ | |
153 | } | |
154 | if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) { | |
155 | return -1; /* 1T segment on MMU that doesn't support it */ | |
156 | } | |
157 | ||
158 | /* Mask out the slot number as we store the entry */ | |
159 | slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V); | |
160 | slb->vsid = rs; | |
161 | ||
162 | LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64 | |
163 | " %016" PRIx64 "\n", __func__, slot, rb, rs, | |
164 | slb->esid, slb->vsid); | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
169 | static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb, | |
170 | target_ulong *rt) | |
171 | { | |
172 | int slot = rb & 0xfff; | |
173 | ppc_slb_t *slb = &env->slb[slot]; | |
174 | ||
175 | if (slot >= env->slb_nr) { | |
176 | return -1; | |
177 | } | |
178 | ||
179 | *rt = slb->esid; | |
180 | return 0; | |
181 | } | |
182 | ||
183 | static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb, | |
184 | target_ulong *rt) | |
185 | { | |
186 | int slot = rb & 0xfff; | |
187 | ppc_slb_t *slb = &env->slb[slot]; | |
188 | ||
189 | if (slot >= env->slb_nr) { | |
190 | return -1; | |
191 | } | |
192 | ||
193 | *rt = slb->vsid; | |
194 | return 0; | |
195 | } | |
196 | ||
197 | void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) | |
198 | { | |
199 | if (ppc_store_slb(env, rb, rs) < 0) { | |
200 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, | |
201 | POWERPC_EXCP_INVAL); | |
202 | } | |
203 | } | |
204 | ||
205 | target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) | |
206 | { | |
207 | target_ulong rt = 0; | |
208 | ||
209 | if (ppc_load_slb_esid(env, rb, &rt) < 0) { | |
210 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, | |
211 | POWERPC_EXCP_INVAL); | |
212 | } | |
213 | return rt; | |
214 | } | |
215 | ||
216 | target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) | |
217 | { | |
218 | target_ulong rt = 0; | |
219 | ||
220 | if (ppc_load_slb_vsid(env, rb, &rt) < 0) { | |
221 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, | |
222 | POWERPC_EXCP_INVAL); | |
223 | } | |
224 | return rt; | |
225 | } | |
9d7c3f4a DG |
226 | |
227 | /* | |
228 | * 64-bit hash table MMU handling | |
229 | */ | |
230 | ||
e01b4445 DG |
231 | static int ppc_hash64_pte_prot(CPUPPCState *env, |
232 | ppc_slb_t *slb, ppc_hash_pte64_t pte) | |
496272a7 | 233 | { |
e01b4445 DG |
234 | unsigned pp, key; |
235 | /* Some pp bit combinations have undefined behaviour, so default | |
236 | * to no access in those cases */ | |
237 | int prot = 0; | |
238 | ||
239 | key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP) | |
240 | : (slb->vsid & SLB_VSID_KS)); | |
241 | pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61); | |
496272a7 | 242 | |
496272a7 DG |
243 | if (key == 0) { |
244 | switch (pp) { | |
245 | case 0x0: | |
246 | case 0x1: | |
247 | case 0x2: | |
e01b4445 DG |
248 | prot = PAGE_READ | PAGE_WRITE; |
249 | break; | |
250 | ||
496272a7 DG |
251 | case 0x3: |
252 | case 0x6: | |
e01b4445 | 253 | prot = PAGE_READ; |
496272a7 DG |
254 | break; |
255 | } | |
256 | } else { | |
257 | switch (pp) { | |
258 | case 0x0: | |
259 | case 0x6: | |
e01b4445 | 260 | prot = 0; |
496272a7 | 261 | break; |
e01b4445 | 262 | |
496272a7 DG |
263 | case 0x1: |
264 | case 0x3: | |
e01b4445 | 265 | prot = PAGE_READ; |
496272a7 | 266 | break; |
e01b4445 | 267 | |
496272a7 | 268 | case 0x2: |
e01b4445 | 269 | prot = PAGE_READ | PAGE_WRITE; |
496272a7 DG |
270 | break; |
271 | } | |
272 | } | |
496272a7 | 273 | |
e01b4445 | 274 | /* No execute if either noexec or guarded bits set */ |
57d0a39d DG |
275 | if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) |
276 | || (slb->vsid & SLB_VSID_N)) { | |
e01b4445 | 277 | prot |= PAGE_EXEC; |
496272a7 DG |
278 | } |
279 | ||
e01b4445 | 280 | return prot; |
496272a7 DG |
281 | } |
282 | ||
aea390e4 DG |
283 | static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr pteg_off, |
284 | bool secondary, target_ulong ptem, | |
285 | ppc_hash_pte64_t *pte) | |
286 | { | |
287 | hwaddr pte_offset = pteg_off; | |
288 | target_ulong pte0, pte1; | |
289 | int i; | |
290 | ||
291 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
292 | pte0 = ppc_hash64_load_hpte0(env, pte_offset); | |
293 | pte1 = ppc_hash64_load_hpte1(env, pte_offset); | |
294 | ||
295 | if ((pte0 & HPTE64_V_VALID) | |
296 | && (secondary == !!(pte0 & HPTE64_V_SECONDARY)) | |
297 | && HPTE64_V_COMPARE(pte0, ptem)) { | |
298 | pte->pte0 = pte0; | |
299 | pte->pte1 = pte1; | |
300 | return pte_offset; | |
301 | } | |
302 | ||
303 | pte_offset += HASH_PTE_SIZE_64; | |
304 | } | |
305 | ||
306 | return -1; | |
307 | } | |
308 | ||
7f3bdc2d DG |
309 | static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env, |
310 | ppc_slb_t *slb, target_ulong eaddr, | |
311 | ppc_hash_pte64_t *pte) | |
c69b6151 | 312 | { |
aea390e4 | 313 | hwaddr pteg_off, pte_offset; |
a1ff751a | 314 | hwaddr hash; |
18148898 | 315 | uint64_t vsid, epnshift, epnmask, epn, ptem; |
a1ff751a | 316 | |
18148898 DG |
317 | /* Page size according to the SLB, which we use to generate the |
318 | * EPN for hash table lookup.. When we implement more recent MMU | |
319 | * extensions this might be different from the actual page size | |
320 | * encoded in the PTE */ | |
321 | epnshift = (slb->vsid & SLB_VSID_L) | |
a1ff751a | 322 | ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS; |
18148898 | 323 | epnmask = ~((1ULL << epnshift) - 1); |
a1ff751a | 324 | |
a1ff751a | 325 | if (slb->vsid & SLB_VSID_B) { |
18148898 DG |
326 | /* 1TB segment */ |
327 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T; | |
328 | epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask; | |
329 | hash = vsid ^ (vsid << 25) ^ (epn >> epnshift); | |
a1ff751a | 330 | } else { |
18148898 DG |
331 | /* 256M segment */ |
332 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; | |
333 | epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask; | |
334 | hash = vsid ^ (epn >> epnshift); | |
a1ff751a | 335 | } |
18148898 | 336 | ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN); |
a1ff751a | 337 | |
a1ff751a DG |
338 | /* Page address translation */ |
339 | LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx | |
340 | " hash " TARGET_FMT_plx "\n", | |
341 | env->htab_base, env->htab_mask, hash); | |
342 | ||
a1ff751a DG |
343 | /* Primary PTEG lookup */ |
344 | LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
345 | " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx | |
346 | " hash=" TARGET_FMT_plx "\n", | |
347 | env->htab_base, env->htab_mask, vsid, ptem, hash); | |
348 | pteg_off = (hash * HASH_PTEG_SIZE_64) & env->htab_mask; | |
7f3bdc2d DG |
349 | pte_offset = ppc_hash64_pteg_search(env, pteg_off, 0, ptem, pte); |
350 | ||
a1ff751a DG |
351 | if (pte_offset == -1) { |
352 | /* Secondary PTEG lookup */ | |
353 | LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
354 | " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx | |
355 | " hash=" TARGET_FMT_plx "\n", env->htab_base, | |
356 | env->htab_mask, vsid, ptem, ~hash); | |
357 | ||
358 | pteg_off = (~hash * HASH_PTEG_SIZE_64) & env->htab_mask; | |
7f3bdc2d | 359 | pte_offset = ppc_hash64_pteg_search(env, pteg_off, 1, ptem, pte); |
a1ff751a DG |
360 | } |
361 | ||
7f3bdc2d | 362 | return pte_offset; |
c69b6151 | 363 | } |
0480884f | 364 | |
6d11d998 DG |
365 | static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte, |
366 | target_ulong eaddr) | |
367 | { | |
75d5ec89 | 368 | hwaddr rpn = pte.pte1 & HPTE64_R_RPN; |
6d11d998 DG |
369 | /* FIXME: Add support for SLLP extended page sizes */ |
370 | int target_page_bits = (slb->vsid & SLB_VSID_L) | |
371 | ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS; | |
372 | hwaddr mask = (1ULL << target_page_bits) - 1; | |
373 | ||
374 | return (rpn & ~mask) | (eaddr & mask); | |
375 | } | |
376 | ||
65d61643 DG |
377 | static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, |
378 | target_ulong eaddr, int rwx) | |
0480884f | 379 | { |
0480884f | 380 | ppc_slb_t *slb; |
7f3bdc2d DG |
381 | hwaddr pte_offset; |
382 | ppc_hash_pte64_t pte; | |
b3440746 | 383 | uint64_t new_pte1; |
e01b4445 | 384 | const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; |
0480884f | 385 | |
6a980110 DG |
386 | assert((rwx == 0) || (rwx == 1) || (rwx == 2)); |
387 | ||
65d61643 DG |
388 | /* 1. Handle real mode accesses */ |
389 | if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { | |
390 | /* Translation is off */ | |
391 | /* In real mode the top 4 effective address bits are ignored */ | |
392 | ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; | |
393 | ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE; | |
394 | return 0; | |
395 | } | |
396 | ||
bb218042 | 397 | /* 2. Translation is on, so look up the SLB */ |
0480884f | 398 | slb = slb_lookup(env, eaddr); |
bb218042 | 399 | |
0480884f DG |
400 | if (!slb) { |
401 | return -5; | |
402 | } | |
403 | ||
bb218042 DG |
404 | /* 3. Check for segment level no-execute violation */ |
405 | if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { | |
406 | return -3; | |
407 | } | |
408 | ||
7f3bdc2d DG |
409 | /* 4. Locate the PTE in the hash table */ |
410 | pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte); | |
411 | if (pte_offset == -1) { | |
412 | return -1; | |
413 | } | |
414 | LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); | |
415 | ||
416 | /* 5. Check access permissions */ | |
7f3bdc2d | 417 | |
e01b4445 | 418 | ctx->prot = ppc_hash64_pte_prot(env, slb, pte); |
6a980110 | 419 | |
e01b4445 | 420 | if ((need_prot[rwx] & ~ctx->prot) != 0) { |
6a980110 DG |
421 | /* Access right violation */ |
422 | LOG_MMU("PTE access rejected\n"); | |
e01b4445 | 423 | return -2; |
6a980110 DG |
424 | } |
425 | ||
87dc3fd1 DG |
426 | LOG_MMU("PTE access granted !\n"); |
427 | ||
428 | /* 6. Update PTE referenced and changed bits if necessary */ | |
429 | ||
b3440746 DG |
430 | new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */ |
431 | if (rwx == 1) { | |
432 | new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */ | |
433 | } else { | |
434 | /* Treat the page as read-only for now, so that a later write | |
435 | * will pass through this function again to set the C bit */ | |
436 | ctx->prot &= ~PAGE_WRITE; | |
437 | } | |
438 | ||
439 | if (new_pte1 != pte.pte1) { | |
440 | ppc_hash64_store_hpte1(env, pte_offset, new_pte1); | |
7f3bdc2d | 441 | } |
0480884f | 442 | |
6d11d998 DG |
443 | /* 7. Determine the real address from the PTE */ |
444 | ||
445 | ctx->raddr = ppc_hash64_pte_raddr(slb, pte, eaddr); | |
e01b4445 | 446 | |
e01b4445 | 447 | return 0; |
0480884f | 448 | } |
629bd516 | 449 | |
f2ad6be8 DG |
450 | hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr) |
451 | { | |
5883d8b2 DG |
452 | ppc_slb_t *slb; |
453 | hwaddr pte_offset; | |
454 | ppc_hash_pte64_t pte; | |
455 | ||
456 | if (msr_dr == 0) { | |
457 | /* In real mode the top 4 effective address bits are ignored */ | |
458 | return addr & 0x0FFFFFFFFFFFFFFFULL; | |
459 | } | |
f2ad6be8 | 460 | |
5883d8b2 DG |
461 | slb = slb_lookup(env, addr); |
462 | if (!slb) { | |
463 | return -1; | |
464 | } | |
465 | ||
466 | pte_offset = ppc_hash64_htab_lookup(env, slb, addr, &pte); | |
467 | if (pte_offset == -1) { | |
f2ad6be8 DG |
468 | return -1; |
469 | } | |
470 | ||
5883d8b2 | 471 | return ppc_hash64_pte_raddr(slb, pte, addr) & TARGET_PAGE_MASK; |
f2ad6be8 DG |
472 | } |
473 | ||
91cda45b | 474 | int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx, |
25de24ab DG |
475 | int mmu_idx) |
476 | { | |
5dc68eb0 | 477 | struct mmu_ctx_hash64 ctx; |
25de24ab DG |
478 | int ret = 0; |
479 | ||
65d61643 | 480 | ret = ppc_hash64_translate(env, &ctx, address, rwx); |
25de24ab DG |
481 | if (ret == 0) { |
482 | tlb_set_page(env, address & TARGET_PAGE_MASK, | |
483 | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, | |
484 | mmu_idx, TARGET_PAGE_SIZE); | |
485 | ret = 0; | |
486 | } else if (ret < 0) { | |
487 | LOG_MMU_STATE(env); | |
91cda45b | 488 | if (rwx == 2) { |
25de24ab DG |
489 | switch (ret) { |
490 | case -1: | |
491 | env->exception_index = POWERPC_EXCP_ISI; | |
492 | env->error_code = 0x40000000; | |
493 | break; | |
494 | case -2: | |
495 | /* Access rights violation */ | |
496 | env->exception_index = POWERPC_EXCP_ISI; | |
497 | env->error_code = 0x08000000; | |
498 | break; | |
499 | case -3: | |
500 | /* No execute protection violation */ | |
501 | env->exception_index = POWERPC_EXCP_ISI; | |
502 | env->error_code = 0x10000000; | |
503 | break; | |
504 | case -5: | |
505 | /* No match in segment table */ | |
506 | env->exception_index = POWERPC_EXCP_ISEG; | |
507 | env->error_code = 0; | |
508 | break; | |
509 | } | |
510 | } else { | |
511 | switch (ret) { | |
512 | case -1: | |
513 | /* No matches in page tables or TLB */ | |
514 | env->exception_index = POWERPC_EXCP_DSI; | |
515 | env->error_code = 0; | |
516 | env->spr[SPR_DAR] = address; | |
91cda45b | 517 | if (rwx == 1) { |
25de24ab DG |
518 | env->spr[SPR_DSISR] = 0x42000000; |
519 | } else { | |
520 | env->spr[SPR_DSISR] = 0x40000000; | |
521 | } | |
522 | break; | |
523 | case -2: | |
524 | /* Access rights violation */ | |
525 | env->exception_index = POWERPC_EXCP_DSI; | |
526 | env->error_code = 0; | |
527 | env->spr[SPR_DAR] = address; | |
91cda45b | 528 | if (rwx == 1) { |
25de24ab DG |
529 | env->spr[SPR_DSISR] = 0x0A000000; |
530 | } else { | |
531 | env->spr[SPR_DSISR] = 0x08000000; | |
532 | } | |
533 | break; | |
534 | case -5: | |
535 | /* No match in segment table */ | |
536 | env->exception_index = POWERPC_EXCP_DSEG; | |
537 | env->error_code = 0; | |
538 | env->spr[SPR_DAR] = address; | |
539 | break; | |
540 | } | |
541 | } | |
542 | #if 0 | |
543 | printf("%s: set exception to %d %02x\n", __func__, | |
544 | env->exception, env->error_code); | |
545 | #endif | |
546 | ret = 1; | |
547 | } | |
548 | ||
549 | return ret; | |
550 | } |