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9a64fbe4 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
9a64fbe4
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
9a64fbe4 19 */
9a64fbe4 20#include "exec.h"
603fccce 21#include "host-utils.h"
a7812ae4 22#include "helper.h"
9a64fbe4 23
0411a972 24#include "helper_regs.h"
0487d6a8 25
fdabc366
FB		 26//#define DEBUG_OP
27//#define DEBUG_EXCEPTIONS
76a66253 28//#define DEBUG_SOFTWARE_TLB
fdabc366 29
9a64fbe4
FB		 30/*****************************************************************************/
31/* Exceptions processing helpers */
9a64fbe4 32
64adab3f 33void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
9a64fbe4 34{
e06fcd75
AJ		 35#if 0
36 printf("Raise exception %3x code : %d\n", exception, error_code);
37#endif
38 env->exception_index = exception;
39 env->error_code = error_code;
40 cpu_loop_exit();
76a66253 41}
9fddaa0c 42
e06fcd75 43void helper_raise_exception (uint32_t exception)
9fddaa0c 44{
e06fcd75 45 helper_raise_exception_err(exception, 0);
9a64fbe4
FB		 46}
47
76a66253
JM		 48/*****************************************************************************/
49/* Registers load and stores */
a7812ae4 50target_ulong helper_load_cr (void)
76a66253 51{
e1571908
AJ		 52 return (env->crf[0] << 28) |
53 (env->crf[1] << 24) |
54 (env->crf[2] << 20) |
55 (env->crf[3] << 16) |
56 (env->crf[4] << 12) |
57 (env->crf[5] << 8) |
58 (env->crf[6] << 4) |
59 (env->crf[7] << 0);
76a66253
JM		 60}
61
e1571908 62void helper_store_cr (target_ulong val, uint32_t mask)
76a66253
JM		 63{
64 int i, sh;
65
36081602 66 for (i = 0, sh = 7; i < 8; i++, sh--) {
76a66253 67 if (mask & (1 << sh))
e1571908 68 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
76a66253
JM		 69 }
70}
71
45d827d2
AJ		 72/*****************************************************************************/
73/* SPR accesses */
74void helper_load_dump_spr (uint32_t sprn)
a496775f 75{
6b80055d 76 if (loglevel != 0) {
a496775f
JM		 77 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
79 }
a496775f
JM		 80}
81
45d827d2 82void helper_store_dump_spr (uint32_t sprn)
a496775f 83{
6b80055d 84 if (loglevel != 0) {
45d827d2
AJ		 85 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
87 }
88}
89
90target_ulong helper_load_tbl (void)
91{
92 return cpu_ppc_load_tbl(env);
93}
94
95target_ulong helper_load_tbu (void)
96{
97 return cpu_ppc_load_tbu(env);
98}
99
100target_ulong helper_load_atbl (void)
101{
102 return cpu_ppc_load_atbl(env);
103}
104
105target_ulong helper_load_atbu (void)
106{
107 return cpu_ppc_load_atbu(env);
108}
109
110target_ulong helper_load_601_rtcl (void)
111{
112 return cpu_ppc601_load_rtcl(env);
113}
114
115target_ulong helper_load_601_rtcu (void)
116{
117 return cpu_ppc601_load_rtcu(env);
118}
119
120#if !defined(CONFIG_USER_ONLY)
121#if defined (TARGET_PPC64)
122void helper_store_asr (target_ulong val)
123{
124 ppc_store_asr(env, val);
125}
126#endif
127
128void helper_store_sdr1 (target_ulong val)
129{
130 ppc_store_sdr1(env, val);
131}
132
133void helper_store_tbl (target_ulong val)
134{
135 cpu_ppc_store_tbl(env, val);
136}
137
138void helper_store_tbu (target_ulong val)
139{
140 cpu_ppc_store_tbu(env, val);
141}
142
143void helper_store_atbl (target_ulong val)
144{
145 cpu_ppc_store_atbl(env, val);
146}
147
148void helper_store_atbu (target_ulong val)
149{
150 cpu_ppc_store_atbu(env, val);
151}
152
153void helper_store_601_rtcl (target_ulong val)
154{
155 cpu_ppc601_store_rtcl(env, val);
156}
157
158void helper_store_601_rtcu (target_ulong val)
159{
160 cpu_ppc601_store_rtcu(env, val);
161}
162
163target_ulong helper_load_decr (void)
164{
165 return cpu_ppc_load_decr(env);
166}
167
168void helper_store_decr (target_ulong val)
169{
170 cpu_ppc_store_decr(env, val);
171}
172
173void helper_store_hid0_601 (target_ulong val)
174{
175 target_ulong hid0;
176
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
184 if (loglevel != 0) {
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
187 }
a496775f 188 }
45d827d2 189 env->spr[SPR_HID0] = (uint32_t)val;
a496775f
JM		 190}
191
45d827d2
AJ		 192void helper_store_403_pbr (uint32_t num, target_ulong value)
193{
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
197 tlb_flush(env, 1);
198 }
199}
200
201target_ulong helper_load_40x_pit (void)
202{
203 return load_40x_pit(env);
204}
205
206void helper_store_40x_pit (target_ulong val)
207{
208 store_40x_pit(env, val);
209}
210
211void helper_store_40x_dbcr0 (target_ulong val)
212{
213 store_40x_dbcr0(env, val);
214}
215
216void helper_store_40x_sler (target_ulong val)
217{
218 store_40x_sler(env, val);
219}
220
221void helper_store_booke_tcr (target_ulong val)
222{
223 store_booke_tcr(env, val);
224}
225
226void helper_store_booke_tsr (target_ulong val)
227{
228 store_booke_tsr(env, val);
229}
230
231void helper_store_ibatu (uint32_t nr, target_ulong val)
232{
233 ppc_store_ibatu(env, nr, val);
234}
235
236void helper_store_ibatl (uint32_t nr, target_ulong val)
237{
238 ppc_store_ibatl(env, nr, val);
239}
240
241void helper_store_dbatu (uint32_t nr, target_ulong val)
242{
243 ppc_store_dbatu(env, nr, val);
244}
245
246void helper_store_dbatl (uint32_t nr, target_ulong val)
247{
248 ppc_store_dbatl(env, nr, val);
249}
250
251void helper_store_601_batl (uint32_t nr, target_ulong val)
252{
253 ppc_store_ibatl_601(env, nr, val);
254}
255
256void helper_store_601_batu (uint32_t nr, target_ulong val)
257{
258 ppc_store_ibatu_601(env, nr, val);
259}
260#endif
261
ff4a62cd
AJ		 262/*****************************************************************************/
263/* Memory load and stores */
264
76db3ba4 265static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
ff4a62cd
AJ		 266{
267#if defined(TARGET_PPC64)
76db3ba4
AJ		 268 if (!msr_sf)
269 return (uint32_t)(addr + arg);
ff4a62cd
AJ		 270 else
271#endif
76db3ba4 272 return addr + arg;
ff4a62cd
AJ		 273}
274
275void helper_lmw (target_ulong addr, uint32_t reg)
276{
76db3ba4 277 for (; reg < 32; reg++) {
ff4a62cd 278 if (msr_le)
76db3ba4 279 env->gpr[reg] = bswap32(ldl(addr));
ff4a62cd 280 else
76db3ba4
AJ		 281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
ff4a62cd
AJ		 283 }
284}
285
286void helper_stmw (target_ulong addr, uint32_t reg)
287{
76db3ba4 288 for (; reg < 32; reg++) {
ff4a62cd 289 if (msr_le)
76db3ba4 290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
ff4a62cd 291 else
76db3ba4
AJ		 292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
ff4a62cd
AJ		 294 }
295}
296
dfbc799d
AJ		 297void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
298{
299 int sh;
76db3ba4
AJ		 300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
dfbc799d 302 reg = (reg + 1) % 32;
76db3ba4 303 addr = addr_add(addr, 4);
dfbc799d
AJ		 304 }
305 if (unlikely(nb > 0)) {
306 env->gpr[reg] = 0;
76db3ba4
AJ		 307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
dfbc799d
AJ		 310 }
311 }
312}
313/* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
317 */
318void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
319{
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
e06fcd75
AJ		 323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
324 POWERPC_EXCP_INVAL |
325 POWERPC_EXCP_INVAL_LSWX);
dfbc799d
AJ		 326 } else {
327 helper_lsw(addr, xer_bc, reg);
328 }
329 }
330}
331
332void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
333{
334 int sh;
76db3ba4
AJ		 335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
dfbc799d 337 reg = (reg + 1) % 32;
76db3ba4 338 addr = addr_add(addr, 4);
dfbc799d
AJ		 339 }
340 if (unlikely(nb > 0)) {
a16b45e7 341 for (sh = 24; nb > 0; nb--, sh -= 8) {
76db3ba4 342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
a16b45e7
AJ		 343 addr = addr_add(addr, 1);
344 }
dfbc799d
AJ		 345 }
346}
347
799a8c8d
AJ		 348static void do_dcbz(target_ulong addr, int dcache_line_size)
349{
76db3ba4 350 addr &= ~(dcache_line_size - 1);
799a8c8d 351 int i;
799a8c8d 352 for (i = 0 ; i < dcache_line_size ; i += 4) {
dcc532c8 353 stl(addr + i , 0);
799a8c8d 354 }
76db3ba4 355 if (env->reserve == addr)
799a8c8d
AJ		 356 env->reserve = (target_ulong)-1ULL;
357}
358
359void helper_dcbz(target_ulong addr)
360{
361 do_dcbz(addr, env->dcache_line_size);
362}
363
364void helper_dcbz_970(target_ulong addr)
365{
366 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
367 do_dcbz(addr, 32);
368 else
369 do_dcbz(addr, env->dcache_line_size);
370}
371
37d269df
AJ		 372void helper_icbi(target_ulong addr)
373{
374 uint32_t tmp;
375
76db3ba4 376 addr &= ~(env->dcache_line_size - 1);
37d269df
AJ		 377 /* Invalidate one cache line :
378 * PowerPC specification says this is to be treated like a load
379 * (not a fetch) by the MMU. To be sure it will be so,
380 * do the load "by hand".
381 */
dcc532c8 382 tmp = ldl(addr);
37d269df
AJ		 383 tb_invalidate_page_range(addr, addr + env->icache_line_size);
384}
385
bdb4b689
AJ		 386// XXX: to be tested
387target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
388{
389 int i, c, d;
bdb4b689
AJ		 390 d = 24;
391 for (i = 0; i < xer_bc; i++) {
76db3ba4
AJ		 392 c = ldub(addr);
393 addr = addr_add(addr, 1);
bdb4b689
AJ		 394 /* ra (if not 0) and rb are never modified */
395 if (likely(reg != rb && (ra == 0 || reg != ra))) {
396 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
397 }
398 if (unlikely(c == xer_cmp))
399 break;
400 if (likely(d != 0)) {
401 d -= 8;
402 } else {
403 d = 24;
404 reg++;
405 reg = reg & 0x1F;
406 }
407 }
408 return i;
409}
410
9a64fbe4 411/*****************************************************************************/
fdabc366 412/* Fixed point operations helpers */
d9bce9d9 413#if defined(TARGET_PPC64)
d9bce9d9 414
74637406
AJ		 415/* multiply high word */
416uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
fdabc366 417{
74637406 418 uint64_t tl, th;
fdabc366 419
74637406
AJ		 420 muls64(&tl, &th, arg1, arg2);
421 return th;
d9bce9d9 422}
d9bce9d9 423
74637406
AJ		 424/* multiply high word unsigned */
425uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
fdabc366 426{
74637406 427 uint64_t tl, th;
fdabc366 428
74637406
AJ		 429 mulu64(&tl, &th, arg1, arg2);
430 return th;
fdabc366
FB		 431}
432
74637406 433uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
fdabc366 434{
d9bce9d9
JM		 435 int64_t th;
436 uint64_t tl;
437
74637406 438 muls64(&tl, (uint64_t *)&th, arg1, arg2);
88ad920b 439 /* If th != 0 && th != -1, then we had an overflow */
6f2d8978 440 if (likely((uint64_t)(th + 1) <= 1)) {
3d7b417e 441 env->xer &= ~(1 << XER_OV);
fdabc366 442 } else {
3d7b417e 443 env->xer |= (1 << XER_OV) | (1 << XER_SO);
fdabc366 444 }
74637406 445 return (int64_t)tl;
d9bce9d9
JM		 446}
447#endif
448
26d67362 449target_ulong helper_cntlzw (target_ulong t)
603fccce 450{
26d67362 451 return clz32(t);
603fccce
JM		 452}
453
454#if defined(TARGET_PPC64)
26d67362 455target_ulong helper_cntlzd (target_ulong t)
603fccce 456{
26d67362 457 return clz64(t);
603fccce
JM		 458}
459#endif
460
9a64fbe4 461/* shift right arithmetic helper */
26d67362 462target_ulong helper_sraw (target_ulong value, target_ulong shift)
9a64fbe4
FB		 463{
464 int32_t ret;
465
26d67362
AJ		 466 if (likely(!(shift & 0x20))) {
467 if (likely((uint32_t)shift != 0)) {
468 shift &= 0x1f;
469 ret = (int32_t)value >> shift;
470 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
3d7b417e 471 env->xer &= ~(1 << XER_CA);
fdabc366 472 } else {
3d7b417e 473 env->xer |= (1 << XER_CA);
fdabc366
FB		 474 }
475 } else {
26d67362 476 ret = (int32_t)value;
3d7b417e 477 env->xer &= ~(1 << XER_CA);
fdabc366
FB		 478 }
479 } else {
26d67362
AJ		 480 ret = (int32_t)value >> 31;
481 if (ret) {
3d7b417e 482 env->xer |= (1 << XER_CA);
26d67362
AJ		 483 } else {
484 env->xer &= ~(1 << XER_CA);
76a66253 485 }
fdabc366 486 }
26d67362 487 return (target_long)ret;
9a64fbe4
FB		 488}
489
d9bce9d9 490#if defined(TARGET_PPC64)
26d67362 491target_ulong helper_srad (target_ulong value, target_ulong shift)
d9bce9d9
JM		 492{
493 int64_t ret;
494
26d67362
AJ		 495 if (likely(!(shift & 0x40))) {
496 if (likely((uint64_t)shift != 0)) {
497 shift &= 0x3f;
498 ret = (int64_t)value >> shift;
499 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
3d7b417e 500 env->xer &= ~(1 << XER_CA);
d9bce9d9 501 } else {
3d7b417e 502 env->xer |= (1 << XER_CA);
d9bce9d9
JM		 503 }
504 } else {
26d67362 505 ret = (int64_t)value;
3d7b417e 506 env->xer &= ~(1 << XER_CA);
d9bce9d9
JM		 507 }
508 } else {
26d67362
AJ		 509 ret = (int64_t)value >> 63;
510 if (ret) {
3d7b417e 511 env->xer |= (1 << XER_CA);
26d67362
AJ		 512 } else {
513 env->xer &= ~(1 << XER_CA);
d9bce9d9
JM		 514 }
515 }
26d67362 516 return ret;
d9bce9d9
JM		 517}
518#endif
519
26d67362 520target_ulong helper_popcntb (target_ulong val)
d9bce9d9 521{
6176a26d
AJ		 522 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
523 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
524 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
525 return val;
d9bce9d9
JM		 526}
527
528#if defined(TARGET_PPC64)
26d67362 529target_ulong helper_popcntb_64 (target_ulong val)
d9bce9d9 530{
6176a26d
AJ		 531 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
532 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
533 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
534 return val;
d9bce9d9
JM		 535}
536#endif
537
fdabc366 538/*****************************************************************************/
9a64fbe4 539/* Floating point operations helpers */
a0d7d5a7
AJ		 540uint64_t helper_float32_to_float64(uint32_t arg)
541{
542 CPU_FloatU f;
543 CPU_DoubleU d;
544 f.l = arg;
545 d.d = float32_to_float64(f.f, &env->fp_status);
546 return d.ll;
547}
548
549uint32_t helper_float64_to_float32(uint64_t arg)
550{
551 CPU_FloatU f;
552 CPU_DoubleU d;
553 d.ll = arg;
554 f.f = float64_to_float32(d.d, &env->fp_status);
555 return f.l;
556}
557
0ca9d380 558static always_inline int isden (float64 d)
7c58044c 559{
0ca9d380 560 CPU_DoubleU u;
7c58044c 561
0ca9d380 562 u.d = d;
7c58044c 563
0ca9d380 564 return ((u.ll >> 52) & 0x7FF) == 0;
7c58044c
JM		 565}
566
af12906f 567uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
7c58044c 568{
af12906f 569 CPU_DoubleU farg;
7c58044c 570 int isneg;
af12906f
AJ		 571 int ret;
572 farg.ll = arg;
f23c346e 573 isneg = float64_is_neg(farg.d);
af12906f
AJ		 574 if (unlikely(float64_is_nan(farg.d))) {
575 if (float64_is_signaling_nan(farg.d)) {
7c58044c 576 /* Signaling NaN: flags are undefined */
af12906f 577 ret = 0x00;
7c58044c
JM		 578 } else {
579 /* Quiet NaN */
af12906f 580 ret = 0x11;
7c58044c 581 }
f23c346e 582 } else if (unlikely(float64_is_infinity(farg.d))) {
7c58044c
JM		 583 /* +/- infinity */
584 if (isneg)
af12906f 585 ret = 0x09;
7c58044c 586 else
af12906f 587 ret = 0x05;
7c58044c 588 } else {
f23c346e 589 if (float64_is_zero(farg.d)) {
7c58044c
JM		 590 /* +/- zero */
591 if (isneg)
af12906f 592 ret = 0x12;
7c58044c 593 else
af12906f 594 ret = 0x02;
7c58044c 595 } else {
af12906f 596 if (isden(farg.d)) {
7c58044c 597 /* Denormalized numbers */
af12906f 598 ret = 0x10;
7c58044c
JM		 599 } else {
600 /* Normalized numbers */
af12906f 601 ret = 0x00;
7c58044c
JM		 602 }
603 if (isneg) {
af12906f 604 ret |= 0x08;
7c58044c 605 } else {
af12906f 606 ret |= 0x04;
7c58044c
JM		 607 }
608 }
609 }
610 if (set_fprf) {
611 /* We update FPSCR_FPRF */
612 env->fpscr &= ~(0x1F << FPSCR_FPRF);
af12906f 613 env->fpscr |= ret << FPSCR_FPRF;
7c58044c
JM		 614 }
615 /* We just need fpcc to update Rc1 */
af12906f 616 return ret & 0xF;
7c58044c
JM		 617}
618
619/* Floating-point invalid operations exception */
af12906f 620static always_inline uint64_t fload_invalid_op_excp (int op)
7c58044c 621{
af12906f 622 uint64_t ret = 0;
7c58044c
JM		 623 int ve;
624
625 ve = fpscr_ve;
e0147e41
AJ		 626 switch (op) {
627 case POWERPC_EXCP_FP_VXSNAN:
7c58044c 628 env->fpscr |= 1 << FPSCR_VXSNAN;
e0147e41
AJ		 629 break;
630 case POWERPC_EXCP_FP_VXSOFT:
7c58044c 631 env->fpscr |= 1 << FPSCR_VXSOFT;
e0147e41 632 break;
7c58044c
JM		 633 case POWERPC_EXCP_FP_VXISI:
634 /* Magnitude subtraction of infinities */
635 env->fpscr |= 1 << FPSCR_VXISI;
636 goto update_arith;
637 case POWERPC_EXCP_FP_VXIDI:
638 /* Division of infinity by infinity */
639 env->fpscr |= 1 << FPSCR_VXIDI;
640 goto update_arith;
641 case POWERPC_EXCP_FP_VXZDZ:
642 /* Division of zero by zero */
643 env->fpscr |= 1 << FPSCR_VXZDZ;
644 goto update_arith;
645 case POWERPC_EXCP_FP_VXIMZ:
646 /* Multiplication of zero by infinity */
647 env->fpscr |= 1 << FPSCR_VXIMZ;
648 goto update_arith;
649 case POWERPC_EXCP_FP_VXVC:
650 /* Ordered comparison of NaN */
651 env->fpscr |= 1 << FPSCR_VXVC;
652 env->fpscr &= ~(0xF << FPSCR_FPCC);
653 env->fpscr |= 0x11 << FPSCR_FPCC;
654 /* We must update the target FPR before raising the exception */
655 if (ve != 0) {
656 env->exception_index = POWERPC_EXCP_PROGRAM;
657 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
658 /* Update the floating-point enabled exception summary */
659 env->fpscr |= 1 << FPSCR_FEX;
660 /* Exception is differed */
661 ve = 0;
662 }
663 break;
664 case POWERPC_EXCP_FP_VXSQRT:
665 /* Square root of a negative number */
666 env->fpscr |= 1 << FPSCR_VXSQRT;
667 update_arith:
668 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
669 if (ve == 0) {
670 /* Set the result to quiet NaN */
e0147e41 671 ret = 0xFFF8000000000000ULL;
7c58044c
JM		 672 env->fpscr &= ~(0xF << FPSCR_FPCC);
673 env->fpscr |= 0x11 << FPSCR_FPCC;
674 }
675 break;
676 case POWERPC_EXCP_FP_VXCVI:
677 /* Invalid conversion */
678 env->fpscr |= 1 << FPSCR_VXCVI;
679 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
680 if (ve == 0) {
681 /* Set the result to quiet NaN */
e0147e41 682 ret = 0xFFF8000000000000ULL;
7c58044c
JM		 683 env->fpscr &= ~(0xF << FPSCR_FPCC);
684 env->fpscr |= 0x11 << FPSCR_FPCC;
685 }
686 break;
687 }
688 /* Update the floating-point invalid operation summary */
689 env->fpscr |= 1 << FPSCR_VX;
690 /* Update the floating-point exception summary */
691 env->fpscr |= 1 << FPSCR_FX;
692 if (ve != 0) {
693 /* Update the floating-point enabled exception summary */
694 env->fpscr |= 1 << FPSCR_FEX;
695 if (msr_fe0 != 0 || msr_fe1 != 0)
e06fcd75 696 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
7c58044c 697 }
af12906f 698 return ret;
7c58044c
JM		 699}
700
e33e94f9 701static always_inline void float_zero_divide_excp (void)
7c58044c 702{
7c58044c
JM		 703 env->fpscr |= 1 << FPSCR_ZX;
704 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
705 /* Update the floating-point exception summary */
706 env->fpscr |= 1 << FPSCR_FX;
707 if (fpscr_ze != 0) {
708 /* Update the floating-point enabled exception summary */
709 env->fpscr |= 1 << FPSCR_FEX;
710 if (msr_fe0 != 0 || msr_fe1 != 0) {
e06fcd75
AJ		 711 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
712 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
7c58044c 713 }
7c58044c
JM		 714 }
715}
716
717static always_inline void float_overflow_excp (void)
718{
719 env->fpscr |= 1 << FPSCR_OX;
720 /* Update the floating-point exception summary */
721 env->fpscr |= 1 << FPSCR_FX;
722 if (fpscr_oe != 0) {
723 /* XXX: should adjust the result */
724 /* Update the floating-point enabled exception summary */
725 env->fpscr |= 1 << FPSCR_FEX;
726 /* We must update the target FPR before raising the exception */
727 env->exception_index = POWERPC_EXCP_PROGRAM;
728 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
729 } else {
730 env->fpscr |= 1 << FPSCR_XX;
731 env->fpscr |= 1 << FPSCR_FI;
732 }
733}
734
735static always_inline void float_underflow_excp (void)
736{
737 env->fpscr |= 1 << FPSCR_UX;
738 /* Update the floating-point exception summary */
739 env->fpscr |= 1 << FPSCR_FX;
740 if (fpscr_ue != 0) {
741 /* XXX: should adjust the result */
742 /* Update the floating-point enabled exception summary */
743 env->fpscr |= 1 << FPSCR_FEX;
744 /* We must update the target FPR before raising the exception */
745 env->exception_index = POWERPC_EXCP_PROGRAM;
746 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
747 }
748}
749
750static always_inline void float_inexact_excp (void)
751{
752 env->fpscr |= 1 << FPSCR_XX;
753 /* Update the floating-point exception summary */
754 env->fpscr |= 1 << FPSCR_FX;
755 if (fpscr_xe != 0) {
756 /* Update the floating-point enabled exception summary */
757 env->fpscr |= 1 << FPSCR_FEX;
758 /* We must update the target FPR before raising the exception */
759 env->exception_index = POWERPC_EXCP_PROGRAM;
760 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
761 }
762}
763
764static always_inline void fpscr_set_rounding_mode (void)
765{
766 int rnd_type;
767
768 /* Set rounding mode */
769 switch (fpscr_rn) {
770 case 0:
771 /* Best approximation (round to nearest) */
772 rnd_type = float_round_nearest_even;
773 break;
774 case 1:
775 /* Smaller magnitude (round toward zero) */
776 rnd_type = float_round_to_zero;
777 break;
778 case 2:
779 /* Round toward +infinite */
780 rnd_type = float_round_up;
781 break;
782 default:
783 case 3:
784 /* Round toward -infinite */
785 rnd_type = float_round_down;
786 break;
787 }
788 set_float_rounding_mode(rnd_type, &env->fp_status);
789}
790
6e35d524
AJ		 791void helper_fpscr_clrbit (uint32_t bit)
792{
793 int prev;
794
795 prev = (env->fpscr >> bit) & 1;
796 env->fpscr &= ~(1 << bit);
797 if (prev == 1) {
798 switch (bit) {
799 case FPSCR_RN1:
800 case FPSCR_RN:
801 fpscr_set_rounding_mode();
802 break;
803 default:
804 break;
805 }
806 }
807}
808
af12906f 809void helper_fpscr_setbit (uint32_t bit)
7c58044c
JM		 810{
811 int prev;
812
813 prev = (env->fpscr >> bit) & 1;
814 env->fpscr |= 1 << bit;
815 if (prev == 0) {
816 switch (bit) {
817 case FPSCR_VX:
818 env->fpscr |= 1 << FPSCR_FX;
819 if (fpscr_ve)
820 goto raise_ve;
821 case FPSCR_OX:
822 env->fpscr |= 1 << FPSCR_FX;
823 if (fpscr_oe)
824 goto raise_oe;
825 break;
826 case FPSCR_UX:
827 env->fpscr |= 1 << FPSCR_FX;
828 if (fpscr_ue)
829 goto raise_ue;
830 break;
831 case FPSCR_ZX:
832 env->fpscr |= 1 << FPSCR_FX;
833 if (fpscr_ze)
834 goto raise_ze;
835 break;
836 case FPSCR_XX:
837 env->fpscr |= 1 << FPSCR_FX;
838 if (fpscr_xe)
839 goto raise_xe;
840 break;
841 case FPSCR_VXSNAN:
842 case FPSCR_VXISI:
843 case FPSCR_VXIDI:
844 case FPSCR_VXZDZ:
845 case FPSCR_VXIMZ:
846 case FPSCR_VXVC:
847 case FPSCR_VXSOFT:
848 case FPSCR_VXSQRT:
849 case FPSCR_VXCVI:
850 env->fpscr |= 1 << FPSCR_VX;
851 env->fpscr |= 1 << FPSCR_FX;
852 if (fpscr_ve != 0)
853 goto raise_ve;
854 break;
855 case FPSCR_VE:
856 if (fpscr_vx != 0) {
857 raise_ve:
858 env->error_code = POWERPC_EXCP_FP;
859 if (fpscr_vxsnan)
860 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
861 if (fpscr_vxisi)
862 env->error_code |= POWERPC_EXCP_FP_VXISI;
863 if (fpscr_vxidi)
864 env->error_code |= POWERPC_EXCP_FP_VXIDI;
865 if (fpscr_vxzdz)
866 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
867 if (fpscr_vximz)
868 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
869 if (fpscr_vxvc)
870 env->error_code |= POWERPC_EXCP_FP_VXVC;
871 if (fpscr_vxsoft)
872 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
873 if (fpscr_vxsqrt)
874 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
875 if (fpscr_vxcvi)
876 env->error_code |= POWERPC_EXCP_FP_VXCVI;
877 goto raise_excp;
878 }
879 break;
880 case FPSCR_OE:
881 if (fpscr_ox != 0) {
882 raise_oe:
883 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
884 goto raise_excp;
885 }
886 break;
887 case FPSCR_UE:
888 if (fpscr_ux != 0) {
889 raise_ue:
890 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
891 goto raise_excp;
892 }
893 break;
894 case FPSCR_ZE:
895 if (fpscr_zx != 0) {
896 raise_ze:
897 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
898 goto raise_excp;
899 }
900 break;
901 case FPSCR_XE:
902 if (fpscr_xx != 0) {
903 raise_xe:
904 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
905 goto raise_excp;
906 }
907 break;
908 case FPSCR_RN1:
909 case FPSCR_RN:
910 fpscr_set_rounding_mode();
911 break;
912 default:
913 break;
914 raise_excp:
915 /* Update the floating-point enabled exception summary */
916 env->fpscr |= 1 << FPSCR_FEX;
917 /* We have to update Rc1 before raising the exception */
918 env->exception_index = POWERPC_EXCP_PROGRAM;
919 break;
920 }
921 }
922}
923
af12906f 924void helper_store_fpscr (uint64_t arg, uint32_t mask)
7c58044c
JM		 925{
926 /*
927 * We use only the 32 LSB of the incoming fpr
928 */
7c58044c
JM		 929 uint32_t prev, new;
930 int i;
931
7c58044c 932 prev = env->fpscr;
af12906f 933 new = (uint32_t)arg;
27ee5df0
AJ		 934 new &= ~0x60000000;
935 new |= prev & 0x60000000;
936 for (i = 0; i < 8; i++) {
7c58044c
JM		 937 if (mask & (1 << i)) {
938 env->fpscr &= ~(0xF << (4 * i));
939 env->fpscr |= new & (0xF << (4 * i));
940 }
941 }
942 /* Update VX and FEX */
943 if (fpscr_ix != 0)
944 env->fpscr |= 1 << FPSCR_VX;
5567025f
AJ		 945 else
946 env->fpscr &= ~(1 << FPSCR_VX);
7c58044c
JM		 947 if ((fpscr_ex & fpscr_eex) != 0) {
948 env->fpscr |= 1 << FPSCR_FEX;
949 env->exception_index = POWERPC_EXCP_PROGRAM;
950 /* XXX: we should compute it properly */
951 env->error_code = POWERPC_EXCP_FP;
952 }
5567025f
AJ		 953 else
954 env->fpscr &= ~(1 << FPSCR_FEX);
7c58044c
JM		 955 fpscr_set_rounding_mode();
956}
7c58044c 957
af12906f 958void helper_float_check_status (void)
7c58044c 959{
af12906f 960#ifdef CONFIG_SOFTFLOAT
7c58044c
JM		 961 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
962 (env->error_code & POWERPC_EXCP_FP)) {
963 /* Differred floating-point exception after target FPR update */
964 if (msr_fe0 != 0 || msr_fe1 != 0)
e06fcd75 965 helper_raise_exception_err(env->exception_index, env->error_code);
be94c952
AJ		 966 } else {
967 int status = get_float_exception_flags(&env->fp_status);
e33e94f9
AJ		 968 if (status & float_flag_divbyzero) {
969 float_zero_divide_excp();
970 } else if (status & float_flag_overflow) {
be94c952
AJ		 971 float_overflow_excp();
972 } else if (status & float_flag_underflow) {
973 float_underflow_excp();
974 } else if (status & float_flag_inexact) {
975 float_inexact_excp();
976 }
7c58044c 977 }
af12906f
AJ		 978#else
979 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
980 (env->error_code & POWERPC_EXCP_FP)) {
981 /* Differred floating-point exception after target FPR update */
982 if (msr_fe0 != 0 || msr_fe1 != 0)
e06fcd75 983 helper_raise_exception_err(env->exception_index, env->error_code);
af12906f 984 }
af12906f
AJ		 985#endif
986}
987
988#ifdef CONFIG_SOFTFLOAT
989void helper_reset_fpstatus (void)
990{
be94c952 991 set_float_exception_flags(0, &env->fp_status);
7c58044c
JM		 992}
993#endif
994
af12906f
AJ		 995/* fadd - fadd. */
996uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
7c58044c 997{
af12906f
AJ		 998 CPU_DoubleU farg1, farg2;
999
1000 farg1.ll = arg1;
1001 farg2.ll = arg2;
1002#if USE_PRECISE_EMULATION
1003 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1004 float64_is_signaling_nan(farg2.d))) {
7c58044c 1005 /* sNaN addition */
af12906f 1006 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
17218d1f
AJ		 1007 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1008 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
7c58044c 1009 /* Magnitude subtraction of infinities */
cf1cf21e 1010 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
17218d1f
AJ		 1011 } else {
1012 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
7c58044c 1013 }
af12906f
AJ		 1014#else
1015 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1016#endif
1017 return farg1.ll;
7c58044c
JM		 1018}
1019
af12906f
AJ		 1020/* fsub - fsub. */
1021uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1022{
1023 CPU_DoubleU farg1, farg2;
1024
1025 farg1.ll = arg1;
1026 farg2.ll = arg2;
1027#if USE_PRECISE_EMULATION
7c58044c 1028{
af12906f
AJ		 1029 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1030 float64_is_signaling_nan(farg2.d))) {
7c58044c 1031 /* sNaN subtraction */
af12906f 1032 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
17218d1f
AJ		 1033 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1034 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
7c58044c 1035 /* Magnitude subtraction of infinities */
af12906f 1036 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
17218d1f
AJ		 1037 } else {
1038 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
7c58044c
JM		 1039 }
1040}
af12906f
AJ		 1041#else
1042 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1043#endif
1044 return farg1.ll;
1045}
7c58044c 1046
af12906f
AJ		 1047/* fmul - fmul. */
1048uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
7c58044c 1049{
af12906f
AJ		 1050 CPU_DoubleU farg1, farg2;
1051
1052 farg1.ll = arg1;
1053 farg2.ll = arg2;
1054#if USE_PRECISE_EMULATION
1055 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1056 float64_is_signaling_nan(farg2.d))) {
7c58044c 1057 /* sNaN multiplication */
af12906f 1058 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
f23c346e
AJ		 1059 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1060 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
7c58044c 1061 /* Multiplication of zero by infinity */
af12906f 1062 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
7c58044c 1063 } else {
af12906f 1064 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
7c58044c 1065 }
af12906f
AJ		 1066#else
1067 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1068#endif
1069 return farg1.ll;
1070}
7c58044c 1071
af12906f
AJ		 1072/* fdiv - fdiv. */
1073uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
7c58044c 1074{
af12906f
AJ		 1075 CPU_DoubleU farg1, farg2;
1076
1077 farg1.ll = arg1;
1078 farg2.ll = arg2;
1079#if USE_PRECISE_EMULATION
1080 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1081 float64_is_signaling_nan(farg2.d))) {
7c58044c 1082 /* sNaN division */
af12906f 1083 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
f23c346e 1084 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) {
7c58044c 1085 /* Division of infinity by infinity */
af12906f 1086 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
e33e94f9
AJ		 1087 } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
1088 /* Division of zero by zero */
1089 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
7c58044c 1090 } else {
af12906f 1091 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
7c58044c 1092 }
af12906f
AJ		 1093#else
1094 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1095#endif
1096 return farg1.ll;
7c58044c 1097}
7c58044c 1098
af12906f
AJ		 1099/* fabs */
1100uint64_t helper_fabs (uint64_t arg)
9a64fbe4 1101{
af12906f 1102 CPU_DoubleU farg;
9a64fbe4 1103
af12906f
AJ		 1104 farg.ll = arg;
1105 farg.d = float64_abs(farg.d);
1106 return farg.ll;
1107}
1108
1109/* fnabs */
1110uint64_t helper_fnabs (uint64_t arg)
1111{
1112 CPU_DoubleU farg;
1113
1114 farg.ll = arg;
1115 farg.d = float64_abs(farg.d);
1116 farg.d = float64_chs(farg.d);
1117 return farg.ll;
1118}
1119
1120/* fneg */
1121uint64_t helper_fneg (uint64_t arg)
1122{
1123 CPU_DoubleU farg;
1124
1125 farg.ll = arg;
1126 farg.d = float64_chs(farg.d);
1127 return farg.ll;
1128}
1129
1130/* fctiw - fctiw. */
1131uint64_t helper_fctiw (uint64_t arg)
1132{
1133 CPU_DoubleU farg;
1134 farg.ll = arg;
1135
1136 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1137 /* sNaN conversion */
af12906f 1138 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
f23c346e 1139 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
7c58044c 1140 /* qNan / infinity conversion */
af12906f 1141 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c 1142 } else {
af12906f 1143 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1cdb9c3d 1144#if USE_PRECISE_EMULATION
7c58044c
JM		 1145 /* XXX: higher bits are not supposed to be significant.
1146 * to make tests easier, return the same as a real PowerPC 750
1147 */
af12906f 1148 farg.ll |= 0xFFF80000ULL << 32;
e864cabd 1149#endif
7c58044c 1150 }
af12906f 1151 return farg.ll;
9a64fbe4
FB		 1152}
1153
af12906f
AJ		 1154/* fctiwz - fctiwz. */
1155uint64_t helper_fctiwz (uint64_t arg)
9a64fbe4 1156{
af12906f
AJ		 1157 CPU_DoubleU farg;
1158 farg.ll = arg;
4ecc3190 1159
af12906f 1160 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1161 /* sNaN conversion */
af12906f 1162 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
f23c346e 1163 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
7c58044c 1164 /* qNan / infinity conversion */
af12906f 1165 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c 1166 } else {
af12906f 1167 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1cdb9c3d 1168#if USE_PRECISE_EMULATION
7c58044c
JM		 1169 /* XXX: higher bits are not supposed to be significant.
1170 * to make tests easier, return the same as a real PowerPC 750
1171 */
af12906f 1172 farg.ll |= 0xFFF80000ULL << 32;
e864cabd 1173#endif
7c58044c 1174 }
af12906f 1175 return farg.ll;
9a64fbe4
FB		 1176}
1177
426613db 1178#if defined(TARGET_PPC64)
af12906f
AJ		 1179/* fcfid - fcfid. */
1180uint64_t helper_fcfid (uint64_t arg)
426613db 1181{
af12906f
AJ		 1182 CPU_DoubleU farg;
1183 farg.d = int64_to_float64(arg, &env->fp_status);
1184 return farg.ll;
426613db
JM		 1185}
1186
af12906f
AJ		 1187/* fctid - fctid. */
1188uint64_t helper_fctid (uint64_t arg)
426613db 1189{
af12906f
AJ		 1190 CPU_DoubleU farg;
1191 farg.ll = arg;
426613db 1192
af12906f 1193 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1194 /* sNaN conversion */
af12906f 1195 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
f23c346e 1196 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
7c58044c 1197 /* qNan / infinity conversion */
af12906f 1198 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c 1199 } else {
af12906f 1200 farg.ll = float64_to_int64(farg.d, &env->fp_status);
7c58044c 1201 }
af12906f 1202 return farg.ll;
426613db
JM		 1203}
1204
af12906f
AJ		 1205/* fctidz - fctidz. */
1206uint64_t helper_fctidz (uint64_t arg)
426613db 1207{
af12906f
AJ		 1208 CPU_DoubleU farg;
1209 farg.ll = arg;
426613db 1210
af12906f 1211 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1212 /* sNaN conversion */
af12906f 1213 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
f23c346e 1214 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
7c58044c 1215 /* qNan / infinity conversion */
af12906f 1216 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c 1217 } else {
af12906f 1218 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
7c58044c 1219 }
af12906f 1220 return farg.ll;
426613db
JM		 1221}
1222
1223#endif
1224
af12906f 1225static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
d7e4b87e 1226{
af12906f
AJ		 1227 CPU_DoubleU farg;
1228 farg.ll = arg;
1229
1230 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1231 /* sNaN round */
af12906f 1232 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
f23c346e 1233 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
7c58044c 1234 /* qNan / infinity round */
af12906f 1235 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
7c58044c
JM		 1236 } else {
1237 set_float_rounding_mode(rounding_mode, &env->fp_status);
af12906f 1238 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
7c58044c
JM		 1239 /* Restore rounding mode from FPSCR */
1240 fpscr_set_rounding_mode();
1241 }
af12906f 1242 return farg.ll;
d7e4b87e
JM		 1243}
1244
af12906f 1245uint64_t helper_frin (uint64_t arg)
d7e4b87e 1246{
af12906f 1247 return do_fri(arg, float_round_nearest_even);
d7e4b87e
JM		 1248}
1249
af12906f 1250uint64_t helper_friz (uint64_t arg)
d7e4b87e 1251{
af12906f 1252 return do_fri(arg, float_round_to_zero);
d7e4b87e
JM		 1253}
1254
af12906f 1255uint64_t helper_frip (uint64_t arg)
d7e4b87e 1256{
af12906f 1257 return do_fri(arg, float_round_up);
d7e4b87e
JM		 1258}
1259
af12906f 1260uint64_t helper_frim (uint64_t arg)
d7e4b87e 1261{
af12906f 1262 return do_fri(arg, float_round_down);
d7e4b87e
JM		 1263}
1264
af12906f
AJ		 1265/* fmadd - fmadd. */
1266uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
e864cabd 1267{
af12906f
AJ		 1268 CPU_DoubleU farg1, farg2, farg3;
1269
1270 farg1.ll = arg1;
1271 farg2.ll = arg2;
1272 farg3.ll = arg3;
1273#if USE_PRECISE_EMULATION
1274 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1275 float64_is_signaling_nan(farg2.d) ||
1276 float64_is_signaling_nan(farg3.d))) {
7c58044c 1277 /* sNaN operation */
af12906f 1278 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
da1e7ac9
AJ		 1279 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1280 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1281 /* Multiplication of zero by infinity */
1282 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
7c58044c 1283 } else {
e864cabd 1284#ifdef FLOAT128
7c58044c
JM		 1285 /* This is the way the PowerPC specification defines it */
1286 float128 ft0_128, ft1_128;
1287
af12906f
AJ		 1288 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1289 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
7c58044c 1290 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
da1e7ac9
AJ		 1291 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1292 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1293 /* Magnitude subtraction of infinities */
1294 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1295 } else {
1296 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1297 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1298 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1299 }
e864cabd 1300#else
7c58044c 1301 /* This is OK on x86 hosts */
af12906f 1302 farg1.d = (farg1.d * farg2.d) + farg3.d;
e864cabd 1303#endif
7c58044c 1304 }
af12906f
AJ		 1305#else
1306 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1307 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1308#endif
1309 return farg1.ll;
e864cabd
JM		 1310}
1311
af12906f
AJ		 1312/* fmsub - fmsub. */
1313uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
e864cabd 1314{
af12906f
AJ		 1315 CPU_DoubleU farg1, farg2, farg3;
1316
1317 farg1.ll = arg1;
1318 farg2.ll = arg2;
1319 farg3.ll = arg3;
1320#if USE_PRECISE_EMULATION
1321 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1322 float64_is_signaling_nan(farg2.d) ||
1323 float64_is_signaling_nan(farg3.d))) {
7c58044c 1324 /* sNaN operation */
af12906f 1325 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
da1e7ac9
AJ		 1326 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1327 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1328 /* Multiplication of zero by infinity */
1329 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
7c58044c 1330 } else {
e864cabd 1331#ifdef FLOAT128
7c58044c
JM		 1332 /* This is the way the PowerPC specification defines it */
1333 float128 ft0_128, ft1_128;
1334
af12906f
AJ		 1335 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1336 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
7c58044c 1337 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
da1e7ac9
AJ		 1338 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1339 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1340 /* Magnitude subtraction of infinities */
1341 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1342 } else {
1343 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1344 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1345 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1346 }
e864cabd 1347#else
7c58044c 1348 /* This is OK on x86 hosts */
af12906f 1349 farg1.d = (farg1.d * farg2.d) - farg3.d;
e864cabd 1350#endif
7c58044c 1351 }
af12906f
AJ		 1352#else
1353 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1354 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1355#endif
1356 return farg1.ll;
e864cabd 1357}
e864cabd 1358
af12906f
AJ		 1359/* fnmadd - fnmadd. */
1360uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
4b3686fa 1361{
af12906f
AJ		 1362 CPU_DoubleU farg1, farg2, farg3;
1363
1364 farg1.ll = arg1;
1365 farg2.ll = arg2;
1366 farg3.ll = arg3;
1367
1368 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1369 float64_is_signaling_nan(farg2.d) ||
1370 float64_is_signaling_nan(farg3.d))) {
7c58044c 1371 /* sNaN operation */
af12906f 1372 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
da1e7ac9
AJ		 1373 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1374 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1375 /* Multiplication of zero by infinity */
1376 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
7c58044c 1377 } else {
1cdb9c3d 1378#if USE_PRECISE_EMULATION
e864cabd 1379#ifdef FLOAT128
7c58044c
JM		 1380 /* This is the way the PowerPC specification defines it */
1381 float128 ft0_128, ft1_128;
1382
af12906f
AJ		 1383 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1384 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
7c58044c 1385 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
da1e7ac9
AJ		 1386 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1387 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1388 /* Magnitude subtraction of infinities */
1389 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1390 } else {
1391 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1392 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1393 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1394 }
e864cabd 1395#else
7c58044c 1396 /* This is OK on x86 hosts */
af12906f 1397 farg1.d = (farg1.d * farg2.d) + farg3.d;
e864cabd
JM		 1398#endif
1399#else
af12906f
AJ		 1400 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1401 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
e864cabd 1402#endif
a44d2ce1 1403 if (likely(!float64_is_nan(farg1.d)))
af12906f 1404 farg1.d = float64_chs(farg1.d);
7c58044c 1405 }
af12906f 1406 return farg1.ll;
4b3686fa
FB		 1407}
1408
af12906f
AJ		 1409/* fnmsub - fnmsub. */
1410uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
4b3686fa 1411{
af12906f
AJ		 1412 CPU_DoubleU farg1, farg2, farg3;
1413
1414 farg1.ll = arg1;
1415 farg2.ll = arg2;
1416 farg3.ll = arg3;
1417
1418 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1419 float64_is_signaling_nan(farg2.d) ||
1420 float64_is_signaling_nan(farg3.d))) {
7c58044c 1421 /* sNaN operation */
af12906f 1422 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
da1e7ac9
AJ		 1423 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1424 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1425 /* Multiplication of zero by infinity */
1426 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
7c58044c 1427 } else {
1cdb9c3d 1428#if USE_PRECISE_EMULATION
e864cabd 1429#ifdef FLOAT128
7c58044c
JM		 1430 /* This is the way the PowerPC specification defines it */
1431 float128 ft0_128, ft1_128;
1432
af12906f
AJ		 1433 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1434 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
7c58044c 1435 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
da1e7ac9
AJ		 1436 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1437 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1438 /* Magnitude subtraction of infinities */
1439 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1440 } else {
1441 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1442 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1443 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1444 }
e864cabd 1445#else
7c58044c 1446 /* This is OK on x86 hosts */
af12906f 1447 farg1.d = (farg1.d * farg2.d) - farg3.d;
e864cabd
JM		 1448#endif
1449#else
af12906f
AJ		 1450 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1451 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
e864cabd 1452#endif
a44d2ce1 1453 if (likely(!float64_is_nan(farg1.d)))
af12906f 1454 farg1.d = float64_chs(farg1.d);
7c58044c 1455 }
af12906f 1456 return farg1.ll;
1ef59d0a
FB		 1457}
1458
af12906f
AJ		 1459/* frsp - frsp. */
1460uint64_t helper_frsp (uint64_t arg)
7c58044c 1461{
af12906f 1462 CPU_DoubleU farg;
6ad193ed 1463 float32 f32;
af12906f
AJ		 1464 farg.ll = arg;
1465
1466#if USE_PRECISE_EMULATION
1467 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1468 /* sNaN square root */
af12906f 1469 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
7c58044c 1470 } else {
6ad193ed
AJ		 1471 f32 = float64_to_float32(farg.d, &env->fp_status);
1472 farg.d = float32_to_float64(f32, &env->fp_status);
7c58044c 1473 }
af12906f 1474#else
6ad193ed
AJ		 1475 f32 = float64_to_float32(farg.d, &env->fp_status);
1476 farg.d = float32_to_float64(f32, &env->fp_status);
af12906f
AJ		 1477#endif
1478 return farg.ll;
7c58044c 1479}
7c58044c 1480
af12906f
AJ		 1481/* fsqrt - fsqrt. */
1482uint64_t helper_fsqrt (uint64_t arg)
9a64fbe4 1483{
af12906f
AJ		 1484 CPU_DoubleU farg;
1485 farg.ll = arg;
1486
1487 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1488 /* sNaN square root */
af12906f 1489 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
f23c346e 1490 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
7c58044c 1491 /* Square root of a negative nonzero number */
af12906f 1492 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
7c58044c 1493 } else {
af12906f 1494 farg.d = float64_sqrt(farg.d, &env->fp_status);
7c58044c 1495 }
af12906f 1496 return farg.ll;
9a64fbe4
FB		 1497}
1498
af12906f
AJ		 1499/* fre - fre. */
1500uint64_t helper_fre (uint64_t arg)
d7e4b87e 1501{
05b93603 1502 CPU_DoubleU fone, farg;
01feec08 1503 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
af12906f 1504 farg.ll = arg;
d7e4b87e 1505
af12906f 1506 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1507 /* sNaN reciprocal */
af12906f 1508 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
d7e4b87e 1509 } else {
6c01bf6c 1510 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
d7e4b87e 1511 }
af12906f 1512 return farg.d;
d7e4b87e
JM		 1513}
1514
af12906f
AJ		 1515/* fres - fres. */
1516uint64_t helper_fres (uint64_t arg)
9a64fbe4 1517{
05b93603 1518 CPU_DoubleU fone, farg;
6c01bf6c 1519 float32 f32;
01feec08 1520 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
af12906f 1521 farg.ll = arg;
4ecc3190 1522
af12906f 1523 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1524 /* sNaN reciprocal */
af12906f 1525 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
4ecc3190 1526 } else {
6c01bf6c
AJ		 1527 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1528 f32 = float64_to_float32(farg.d, &env->fp_status);
1529 farg.d = float32_to_float64(f32, &env->fp_status);
4ecc3190 1530 }
af12906f 1531 return farg.ll;
9a64fbe4
FB		 1532}
1533
af12906f
AJ		 1534/* frsqrte - frsqrte. */
1535uint64_t helper_frsqrte (uint64_t arg)
9a64fbe4 1536{
05b93603 1537 CPU_DoubleU fone, farg;
6c01bf6c 1538 float32 f32;
01feec08 1539 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
af12906f 1540 farg.ll = arg;
4ecc3190 1541
af12906f 1542 if (unlikely(float64_is_signaling_nan(farg.d))) {
7c58044c 1543 /* sNaN reciprocal square root */
af12906f 1544 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
f23c346e 1545 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
7c58044c 1546 /* Reciprocal square root of a negative nonzero number */
af12906f 1547 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
4ecc3190 1548 } else {
6c01bf6c
AJ		 1549 farg.d = float64_sqrt(farg.d, &env->fp_status);
1550 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1551 f32 = float64_to_float32(farg.d, &env->fp_status);
1552 farg.d = float32_to_float64(f32, &env->fp_status);
4ecc3190 1553 }
af12906f 1554 return farg.ll;
9a64fbe4
FB		 1555}
1556
af12906f
AJ		 1557/* fsel - fsel. */
1558uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
9a64fbe4 1559{
6ad7365a 1560 CPU_DoubleU farg1;
af12906f
AJ		 1561
1562 farg1.ll = arg1;
af12906f 1563
572c8952 1564 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) && !float64_is_nan(farg1.d))
6ad7365a 1565 return arg2;
4ecc3190 1566 else
6ad7365a 1567 return arg3;
9a64fbe4
FB		 1568}
1569
9a819377 1570void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
9a64fbe4 1571{
af12906f 1572 CPU_DoubleU farg1, farg2;
e1571908 1573 uint32_t ret = 0;
af12906f
AJ		 1574 farg1.ll = arg1;
1575 farg2.ll = arg2;
e1571908 1576
9a819377
AJ		 1577 if (unlikely(float64_is_nan(farg1.d) ||
1578 float64_is_nan(farg2.d))) {
1579 ret = 0x01UL;
1580 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1581 ret = 0x08UL;
1582 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1583 ret = 0x04UL;
7c58044c 1584 } else {
9a819377 1585 ret = 0x02UL;
9a64fbe4 1586 }
9a819377 1587
7c58044c 1588 env->fpscr &= ~(0x0F << FPSCR_FPRF);
e1571908 1589 env->fpscr |= ret << FPSCR_FPRF;
9a819377
AJ		 1590 env->crf[crfD] = ret;
1591 if (unlikely(ret == 0x01UL
1592 && (float64_is_signaling_nan(farg1.d) ||
1593 float64_is_signaling_nan(farg2.d)))) {
1594 /* sNaN comparison */
1595 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1596 }
9a64fbe4
FB		 1597}
1598
9a819377 1599void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
9a64fbe4 1600{
af12906f 1601 CPU_DoubleU farg1, farg2;
e1571908 1602 uint32_t ret = 0;
af12906f
AJ		 1603 farg1.ll = arg1;
1604 farg2.ll = arg2;
e1571908 1605
af12906f
AJ		 1606 if (unlikely(float64_is_nan(farg1.d) ||
1607 float64_is_nan(farg2.d))) {
9a819377
AJ		 1608 ret = 0x01UL;
1609 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1610 ret = 0x08UL;
1611 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1612 ret = 0x04UL;
1613 } else {
1614 ret = 0x02UL;
1615 }
1616
1617 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1618 env->fpscr |= ret << FPSCR_FPRF;
1619 env->crf[crfD] = ret;
1620 if (unlikely (ret == 0x01UL)) {
af12906f
AJ		 1621 if (float64_is_signaling_nan(farg1.d) ||
1622 float64_is_signaling_nan(farg2.d)) {
7c58044c
JM		 1623 /* sNaN comparison */
1624 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1625 POWERPC_EXCP_FP_VXVC);
1626 } else {
1627 /* qNaN comparison */
1628 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1629 }
9a64fbe4 1630 }
9a64fbe4
FB		 1631}
1632
76a66253 1633#if !defined (CONFIG_USER_ONLY)
6527f6ea 1634void helper_store_msr (target_ulong val)
0411a972 1635{
6527f6ea
AJ		 1636 val = hreg_store_msr(env, val, 0);
1637 if (val != 0) {
0411a972 1638 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
e06fcd75 1639 helper_raise_exception(val);
0411a972
JM		 1640 }
1641}
1642
d72a19f7 1643static always_inline void do_rfi (target_ulong nip, target_ulong msr,
0411a972 1644 target_ulong msrm, int keep_msrh)
9a64fbe4 1645{
426613db 1646#if defined(TARGET_PPC64)
0411a972
JM		 1647 if (msr & (1ULL << MSR_SF)) {
1648 nip = (uint64_t)nip;
1649 msr &= (uint64_t)msrm;
a42bd6cc 1650 } else {
0411a972
JM		 1651 nip = (uint32_t)nip;
1652 msr = (uint32_t)(msr & msrm);
1653 if (keep_msrh)
1654 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
a42bd6cc 1655 }
426613db 1656#else
0411a972
JM		 1657 nip = (uint32_t)nip;
1658 msr &= (uint32_t)msrm;
426613db 1659#endif
0411a972
JM		 1660 /* XXX: beware: this is false if VLE is supported */
1661 env->nip = nip & ~((target_ulong)0x00000003);
a4f30719 1662 hreg_store_msr(env, msr, 1);
fdabc366 1663#if defined (DEBUG_OP)
0411a972 1664 cpu_dump_rfi(env->nip, env->msr);
fdabc366 1665#endif
0411a972
JM		 1666 /* No need to raise an exception here,
1667 * as rfi is always the last insn of a TB
1668 */
fdabc366 1669 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
9a64fbe4 1670}
d9bce9d9 1671
d72a19f7 1672void helper_rfi (void)
0411a972 1673{
d72a19f7
AJ		 1674 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1675 ~((target_ulong)0xFFFF0000), 1);
0411a972
JM		 1676}
1677
d9bce9d9 1678#if defined(TARGET_PPC64)
d72a19f7 1679void helper_rfid (void)
426613db 1680{
d72a19f7
AJ		 1681 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1682 ~((target_ulong)0xFFFF0000), 0);
d9bce9d9 1683}
7863667f 1684
d72a19f7 1685void helper_hrfid (void)
be147d08 1686{
d72a19f7
AJ		 1687 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1688 ~((target_ulong)0xFFFF0000), 0);
be147d08
JM		 1689}
1690#endif
76a66253 1691#endif
9a64fbe4 1692
cab3bee2 1693void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
9a64fbe4 1694{
cab3bee2
AJ		 1695 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1696 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1697 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1698 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1699 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
e06fcd75 1700 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
a42bd6cc 1701 }
9a64fbe4
FB		 1702}
1703
d9bce9d9 1704#if defined(TARGET_PPC64)
cab3bee2 1705void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
d9bce9d9 1706{
cab3bee2
AJ		 1707 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1708 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1709 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1710 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1711 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
e06fcd75 1712 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
d9bce9d9
JM		 1713}
1714#endif
1715
fdabc366 1716/*****************************************************************************/
76a66253 1717/* PowerPC 601 specific instructions (POWER bridge) */
9a64fbe4 1718
22e0e173 1719target_ulong helper_clcs (uint32_t arg)
9a64fbe4 1720{
22e0e173 1721 switch (arg) {
76a66253
JM		 1722 case 0x0CUL:
1723 /* Instruction cache line size */
22e0e173 1724 return env->icache_line_size;
76a66253
JM		 1725 break;
1726 case 0x0DUL:
1727 /* Data cache line size */
22e0e173 1728 return env->dcache_line_size;
76a66253
JM		 1729 break;
1730 case 0x0EUL:
1731 /* Minimum cache line size */
22e0e173
AJ		 1732 return (env->icache_line_size < env->dcache_line_size) ?
1733 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1734 break;
1735 case 0x0FUL:
1736 /* Maximum cache line size */
22e0e173
AJ		 1737 return (env->icache_line_size > env->dcache_line_size) ?
1738 env->icache_line_size : env->dcache_line_size;
76a66253
JM		 1739 break;
1740 default:
1741 /* Undefined */
22e0e173 1742 return 0;
76a66253
JM		 1743 break;
1744 }
1745}
1746
22e0e173 1747target_ulong helper_div (target_ulong arg1, target_ulong arg2)
76a66253 1748{
22e0e173 1749 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
76a66253 1750
22e0e173
AJ		 1751 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1752 (int32_t)arg2 == 0) {
76a66253 1753 env->spr[SPR_MQ] = 0;
22e0e173 1754 return INT32_MIN;
76a66253 1755 } else {
22e0e173
AJ		 1756 env->spr[SPR_MQ] = tmp % arg2;
1757 return tmp / (int32_t)arg2;
76a66253
JM		 1758 }
1759}
1760
22e0e173 1761target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
76a66253 1762{
22e0e173 1763 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
76a66253 1764
22e0e173
AJ		 1765 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1766 (int32_t)arg2 == 0) {
3d7b417e 1767 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1768 env->spr[SPR_MQ] = 0;
22e0e173 1769 return INT32_MIN;
76a66253 1770 } else {
22e0e173
AJ		 1771 env->spr[SPR_MQ] = tmp % arg2;
1772 tmp /= (int32_t)arg2;
1773 if ((int32_t)tmp != tmp) {
3d7b417e 1774 env->xer |= (1 << XER_OV) | (1 << XER_SO);
76a66253 1775 } else {
3d7b417e 1776 env->xer &= ~(1 << XER_OV);
76a66253 1777 }
22e0e173 1778 return tmp;
76a66253
JM		 1779 }
1780}
1781
22e0e173 1782target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
76a66253 1783{
22e0e173
AJ		 1784 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1785 (int32_t)arg2 == 0) {
1786 env->spr[SPR_MQ] = 0;
1787 return INT32_MIN;
76a66253 1788 } else {
22e0e173
AJ		 1789 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1790 return (int32_t)arg1 / (int32_t)arg2;
76a66253 1791 }
76a66253
JM		 1792}
1793
22e0e173 1794target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
76a66253 1795{
22e0e173
AJ		 1796 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1797 (int32_t)arg2 == 0) {
3d7b417e 1798 env->xer |= (1 << XER_OV) | (1 << XER_SO);
22e0e173
AJ		 1799 env->spr[SPR_MQ] = 0;
1800 return INT32_MIN;
76a66253 1801 } else {
3d7b417e 1802 env->xer &= ~(1 << XER_OV);
22e0e173
AJ		 1803 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1804 return (int32_t)arg1 / (int32_t)arg2;
76a66253
JM		 1805 }
1806}
1807
1808#if !defined (CONFIG_USER_ONLY)
22e0e173 1809target_ulong helper_rac (target_ulong addr)
76a66253 1810{
76a66253 1811 mmu_ctx_t ctx;
faadf50e 1812 int nb_BATs;
22e0e173 1813 target_ulong ret = 0;
76a66253
JM		 1814
1815 /* We don't have to generate many instances of this instruction,
1816 * as rac is supervisor only.
1817 */
faadf50e
JM		 1818 /* XXX: FIX THIS: Pretend we have no BAT */
1819 nb_BATs = env->nb_BATs;
1820 env->nb_BATs = 0;
22e0e173
AJ		 1821 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1822 ret = ctx.raddr;
faadf50e 1823 env->nb_BATs = nb_BATs;
22e0e173 1824 return ret;
76a66253
JM		 1825}
1826
d72a19f7 1827void helper_rfsvc (void)
76a66253 1828{
d72a19f7 1829 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
76a66253 1830}
76a66253
JM		 1831#endif
1832
1833/*****************************************************************************/
1834/* 602 specific instructions */
1835/* mfrom is the most crazy instruction ever seen, imho ! */
1836/* Real implementation uses a ROM table. Do the same */
5e9ae189
AJ		 1837/* Extremly decomposed:
1838 * -arg / 256
1839 * return 256 * log10(10 + 1.0) + 0.5
1840 */
db9a16a7 1841#if !defined (CONFIG_USER_ONLY)
cf02a65c 1842target_ulong helper_602_mfrom (target_ulong arg)
76a66253 1843{
cf02a65c 1844 if (likely(arg < 602)) {
76a66253 1845#include "mfrom_table.c"
45d827d2 1846 return mfrom_ROM_table[arg];
76a66253 1847 } else {
cf02a65c 1848 return 0;
76a66253
JM		 1849 }
1850}
db9a16a7 1851#endif
76a66253
JM		 1852
1853/*****************************************************************************/
1854/* Embedded PowerPC specific helpers */
76a66253 1855
a750fc0b 1856/* XXX: to be improved to check access rights when in user-mode */
06dca6a7 1857target_ulong helper_load_dcr (target_ulong dcrn)
a750fc0b 1858{
06dca6a7 1859 target_ulong val = 0;
a750fc0b
JM		 1860
1861 if (unlikely(env->dcr_env == NULL)) {
1862 if (loglevel != 0) {
1863 fprintf(logfile, "No DCR environment\n");
1864 }
e06fcd75
AJ		 1865 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1866 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
06dca6a7 1867 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
a750fc0b 1868 if (loglevel != 0) {
45d827d2 1869 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
a750fc0b 1870 }
e06fcd75
AJ		 1871 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1872 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b 1873 }
06dca6a7 1874 return val;
a750fc0b
JM		 1875}
1876
06dca6a7 1877void helper_store_dcr (target_ulong dcrn, target_ulong val)
a750fc0b
JM		 1878{
1879 if (unlikely(env->dcr_env == NULL)) {
1880 if (loglevel != 0) {
1881 fprintf(logfile, "No DCR environment\n");
1882 }
e06fcd75
AJ		 1883 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1884 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
06dca6a7 1885 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
a750fc0b 1886 if (loglevel != 0) {
45d827d2 1887 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
a750fc0b 1888 }
e06fcd75
AJ		 1889 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1890 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
a750fc0b
JM		 1891 }
1892}
1893
76a66253 1894#if !defined(CONFIG_USER_ONLY)
d72a19f7 1895void helper_40x_rfci (void)
76a66253 1896{
d72a19f7
AJ		 1897 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1898 ~((target_ulong)0xFFFF0000), 0);
a42bd6cc
JM		 1899}
1900
d72a19f7 1901void helper_rfci (void)
a42bd6cc 1902{
d72a19f7
AJ		 1903 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1904 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1905}
1906
d72a19f7 1907void helper_rfdi (void)
a42bd6cc 1908{
d72a19f7
AJ		 1909 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1910 ~((target_ulong)0x3FFF0000), 0);
a42bd6cc
JM		 1911}
1912
d72a19f7 1913void helper_rfmci (void)
a42bd6cc 1914{
d72a19f7
AJ		 1915 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1916 ~((target_ulong)0x3FFF0000), 0);
76a66253 1917}
76a66253
JM		 1918#endif
1919
1920/* 440 specific */
ef0d51af 1921target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
76a66253
JM		 1922{
1923 target_ulong mask;
1924 int i;
1925
1926 i = 1;
1927 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
ef0d51af
AJ		 1928 if ((high & mask) == 0) {
1929 if (update_Rc) {
1930 env->crf[0] = 0x4;
1931 }
76a66253 1932 goto done;
ef0d51af 1933 }
76a66253
JM		 1934 i++;
1935 }
1936 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
ef0d51af
AJ		 1937 if ((low & mask) == 0) {
1938 if (update_Rc) {
1939 env->crf[0] = 0x8;
1940 }
1941 goto done;
1942 }
76a66253
JM		 1943 i++;
1944 }
ef0d51af
AJ		 1945 if (update_Rc) {
1946 env->crf[0] = 0x2;
1947 }
76a66253 1948 done:
ef0d51af
AJ		 1949 env->xer = (env->xer & ~0x7F) | i;
1950 if (update_Rc) {
1951 env->crf[0] |= xer_so;
1952 }
1953 return i;
fdabc366
FB		 1954}
1955
d6a46fe8
AJ		 1956/*****************************************************************************/
1957/* Altivec extension helpers */
1958#if defined(WORDS_BIGENDIAN)
1959#define HI_IDX 0
1960#define LO_IDX 1
1961#else
1962#define HI_IDX 1
1963#define LO_IDX 0
1964#endif
1965
1966#if defined(WORDS_BIGENDIAN)
1967#define VECTOR_FOR_INORDER_I(index, element) \
1968 for (index = 0; index < ARRAY_SIZE(r->element); index++)
1969#else
1970#define VECTOR_FOR_INORDER_I(index, element) \
1971 for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
1972#endif
1973
7872c51c
AJ		 1974#define VARITH_DO(name, op, element) \
1975void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
1976{ \
1977 int i; \
1978 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
1979 r->element[i] = a->element[i] op b->element[i]; \
1980 } \
1981}
1982#define VARITH(suffix, element) \
1983 VARITH_DO(add##suffix, +, element) \
1984 VARITH_DO(sub##suffix, -, element)
1985VARITH(ubm, u8)
1986VARITH(uhm, u16)
1987VARITH(uwm, u32)
1988#undef VARITH_DO
1989#undef VARITH
1990
fab3cbe9
AJ		 1991#define VAVG_DO(name, element, etype) \
1992 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
1993 { \
1994 int i; \
1995 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
1996 etype x = (etype)a->element[i] + (etype)b->element[i] + 1; \
1997 r->element[i] = x >> 1; \
1998 } \
1999 }
2000
2001#define VAVG(type, signed_element, signed_type, unsigned_element, unsigned_type) \
2002 VAVG_DO(avgs##type, signed_element, signed_type) \
2003 VAVG_DO(avgu##type, unsigned_element, unsigned_type)
2004VAVG(b, s8, int16_t, u8, uint16_t)
2005VAVG(h, s16, int32_t, u16, uint32_t)
2006VAVG(w, s32, int64_t, u32, uint64_t)
2007#undef VAVG_DO
2008#undef VAVG
2009
e4039339
AJ		 2010#define VMINMAX_DO(name, compare, element) \
2011 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2012 { \
2013 int i; \
2014 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2015 if (a->element[i] compare b->element[i]) { \
2016 r->element[i] = b->element[i]; \
2017 } else { \
2018 r->element[i] = a->element[i]; \
2019 } \
2020 } \
2021 }
2022#define VMINMAX(suffix, element) \
2023 VMINMAX_DO(min##suffix, >, element) \
2024 VMINMAX_DO(max##suffix, <, element)
2025VMINMAX(sb, s8)
2026VMINMAX(sh, s16)
2027VMINMAX(sw, s32)
2028VMINMAX(ub, u8)
2029VMINMAX(uh, u16)
2030VMINMAX(uw, u32)
2031#undef VMINMAX_DO
2032#undef VMINMAX
2033
3b430048
AJ		 2034#define VMRG_DO(name, element, highp) \
2035 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2036 { \
2037 ppc_avr_t result; \
2038 int i; \
2039 size_t n_elems = ARRAY_SIZE(r->element); \
2040 for (i = 0; i < n_elems/2; i++) { \
2041 if (highp) { \
2042 result.element[i*2+HI_IDX] = a->element[i]; \
2043 result.element[i*2+LO_IDX] = b->element[i]; \
2044 } else { \
2045 result.element[n_elems - i*2 - (1+HI_IDX)] = b->element[n_elems - i - 1]; \
2046 result.element[n_elems - i*2 - (1+LO_IDX)] = a->element[n_elems - i - 1]; \
2047 } \
2048 } \
2049 *r = result; \
2050 }
2051#if defined(WORDS_BIGENDIAN)
2052#define MRGHI 0
2053#define MRGL0 1
2054#else
2055#define MRGHI 1
2056#define MRGLO 0
2057#endif
2058#define VMRG(suffix, element) \
2059 VMRG_DO(mrgl##suffix, element, MRGHI) \
2060 VMRG_DO(mrgh##suffix, element, MRGLO)
2061VMRG(b, u8)
2062VMRG(h, u16)
2063VMRG(w, u32)
2064#undef VMRG_DO
2065#undef VMRG
2066#undef MRGHI
2067#undef MRGLO
2068
2c277908
AJ		 2069#define VMUL_DO(name, mul_element, prod_element, evenp) \
2070 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2071 { \
2072 int i; \
2073 VECTOR_FOR_INORDER_I(i, prod_element) { \
2074 if (evenp) { \
2075 r->prod_element[i] = a->mul_element[i*2+HI_IDX] * b->mul_element[i*2+HI_IDX]; \
2076 } else { \
2077 r->prod_element[i] = a->mul_element[i*2+LO_IDX] * b->mul_element[i*2+LO_IDX]; \
2078 } \
2079 } \
2080 }
2081#define VMUL(suffix, mul_element, prod_element) \
2082 VMUL_DO(mule##suffix, mul_element, prod_element, 1) \
2083 VMUL_DO(mulo##suffix, mul_element, prod_element, 0)
2084VMUL(sb, s8, s16)
2085VMUL(sh, s16, s32)
2086VMUL(ub, u8, u16)
2087VMUL(uh, u16, u32)
2088#undef VMUL_DO
2089#undef VMUL
2090
07ef34c3
AJ		 2091#define VSR(suffix, element) \
2092 void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2093 { \
2094 int i; \
2095 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2096 unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
2097 unsigned int shift = b->element[i] & mask; \
2098 r->element[i] = a->element[i] >> shift; \
2099 } \
2100 }
2101VSR(ab, s8)
2102VSR(ah, s16)
2103VSR(aw, s32)
2104VSR(b, u8)
2105VSR(h, u16)
2106VSR(w, u32)
2107#undef VSR
2108
d6a46fe8
AJ		 2109#undef VECTOR_FOR_INORDER_I
2110#undef HI_IDX
2111#undef LO_IDX
2112
1c97856d 2113/*****************************************************************************/
0487d6a8
JM		 2114/* SPE extension helpers */
2115/* Use a table to make this quicker */
2116static uint8_t hbrev[16] = {
2117 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2118 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2119};
2120
b068d6a7 2121static always_inline uint8_t byte_reverse (uint8_t val)
0487d6a8
JM		 2122{
2123 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2124}
2125
b068d6a7 2126static always_inline uint32_t word_reverse (uint32_t val)
0487d6a8
JM		 2127{
2128 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2129 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2130}
2131
3cd7d1dd 2132#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
57951c27 2133target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
0487d6a8
JM		 2134{
2135 uint32_t a, b, d, mask;
2136
3cd7d1dd 2137 mask = UINT32_MAX >> (32 - MASKBITS);
57951c27
AJ		 2138 a = arg1 & mask;
2139 b = arg2 & mask;
3cd7d1dd 2140 d = word_reverse(1 + word_reverse(a | ~b));
57951c27 2141 return (arg1 & ~mask) | (d & b);
0487d6a8
JM		 2142}
2143
57951c27 2144uint32_t helper_cntlsw32 (uint32_t val)
0487d6a8
JM		 2145{
2146 if (val & 0x80000000)
603fccce 2147 return clz32(~val);
0487d6a8 2148 else
603fccce 2149 return clz32(val);
0487d6a8
JM		 2150}
2151
57951c27 2152uint32_t helper_cntlzw32 (uint32_t val)
0487d6a8 2153{
603fccce 2154 return clz32(val);
0487d6a8
JM		 2155}
2156
1c97856d
AJ		 2157/* Single-precision floating-point conversions */
2158static always_inline uint32_t efscfsi (uint32_t val)
0487d6a8 2159{
0ca9d380 2160 CPU_FloatU u;
0487d6a8
JM		 2161
2162 u.f = int32_to_float32(val, &env->spe_status);
2163
0ca9d380 2164 return u.l;
0487d6a8
JM		 2165}
2166
1c97856d 2167static always_inline uint32_t efscfui (uint32_t val)
0487d6a8 2168{
0ca9d380 2169 CPU_FloatU u;
0487d6a8
JM		 2170
2171 u.f = uint32_to_float32(val, &env->spe_status);
2172
0ca9d380 2173 return u.l;
0487d6a8
JM		 2174}
2175
1c97856d 2176static always_inline int32_t efsctsi (uint32_t val)
0487d6a8 2177{
0ca9d380 2178 CPU_FloatU u;
0487d6a8 2179
0ca9d380 2180 u.l = val;
0487d6a8 2181 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2182 if (unlikely(float32_is_nan(u.f)))
0487d6a8
JM		 2183 return 0;
2184
2185 return float32_to_int32(u.f, &env->spe_status);
2186}
2187
1c97856d 2188static always_inline uint32_t efsctui (uint32_t val)
0487d6a8 2189{
0ca9d380 2190 CPU_FloatU u;
0487d6a8 2191
0ca9d380 2192 u.l = val;
0487d6a8 2193 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2194 if (unlikely(float32_is_nan(u.f)))
0487d6a8
JM		 2195 return 0;
2196
2197 return float32_to_uint32(u.f, &env->spe_status);
2198}
2199
1c97856d 2200static always_inline uint32_t efsctsiz (uint32_t val)
0487d6a8 2201{
0ca9d380 2202 CPU_FloatU u;
0487d6a8 2203
0ca9d380 2204 u.l = val;
0487d6a8 2205 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2206 if (unlikely(float32_is_nan(u.f)))
0487d6a8
JM		 2207 return 0;
2208
2209 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2210}
2211
1c97856d 2212static always_inline uint32_t efsctuiz (uint32_t val)
0487d6a8 2213{
0ca9d380 2214 CPU_FloatU u;
0487d6a8 2215
0ca9d380 2216 u.l = val;
0487d6a8 2217 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2218 if (unlikely(float32_is_nan(u.f)))
0487d6a8
JM		 2219 return 0;
2220
2221 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2222}
2223
1c97856d 2224static always_inline uint32_t efscfsf (uint32_t val)
0487d6a8 2225{
0ca9d380 2226 CPU_FloatU u;
0487d6a8
JM		 2227 float32 tmp;
2228
2229 u.f = int32_to_float32(val, &env->spe_status);
2230 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2231 u.f = float32_div(u.f, tmp, &env->spe_status);
2232
0ca9d380 2233 return u.l;
0487d6a8
JM		 2234}
2235
1c97856d 2236static always_inline uint32_t efscfuf (uint32_t val)
0487d6a8 2237{
0ca9d380 2238 CPU_FloatU u;
0487d6a8
JM		 2239 float32 tmp;
2240
2241 u.f = uint32_to_float32(val, &env->spe_status);
2242 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2243 u.f = float32_div(u.f, tmp, &env->spe_status);
2244
0ca9d380 2245 return u.l;
0487d6a8
JM		 2246}
2247
1c97856d 2248static always_inline uint32_t efsctsf (uint32_t val)
0487d6a8 2249{
0ca9d380 2250 CPU_FloatU u;
0487d6a8
JM		 2251 float32 tmp;
2252
0ca9d380 2253 u.l = val;
0487d6a8 2254 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2255 if (unlikely(float32_is_nan(u.f)))
0487d6a8
JM		 2256 return 0;
2257 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2258 u.f = float32_mul(u.f, tmp, &env->spe_status);
2259
2260 return float32_to_int32(u.f, &env->spe_status);
2261}
2262
1c97856d 2263static always_inline uint32_t efsctuf (uint32_t val)
0487d6a8 2264{
0ca9d380 2265 CPU_FloatU u;
0487d6a8
JM		 2266 float32 tmp;
2267
0ca9d380 2268 u.l = val;
0487d6a8 2269 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2270 if (unlikely(float32_is_nan(u.f)))
0487d6a8
JM		 2271 return 0;
2272 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2273 u.f = float32_mul(u.f, tmp, &env->spe_status);
2274
2275 return float32_to_uint32(u.f, &env->spe_status);
2276}
2277
1c97856d
AJ		 2278#define HELPER_SPE_SINGLE_CONV(name) \
2279uint32_t helper_e##name (uint32_t val) \
2280{ \
2281 return e##name(val); \
2282}
2283/* efscfsi */
2284HELPER_SPE_SINGLE_CONV(fscfsi);
2285/* efscfui */
2286HELPER_SPE_SINGLE_CONV(fscfui);
2287/* efscfuf */
2288HELPER_SPE_SINGLE_CONV(fscfuf);
2289/* efscfsf */
2290HELPER_SPE_SINGLE_CONV(fscfsf);
2291/* efsctsi */
2292HELPER_SPE_SINGLE_CONV(fsctsi);
2293/* efsctui */
2294HELPER_SPE_SINGLE_CONV(fsctui);
2295/* efsctsiz */
2296HELPER_SPE_SINGLE_CONV(fsctsiz);
2297/* efsctuiz */
2298HELPER_SPE_SINGLE_CONV(fsctuiz);
2299/* efsctsf */
2300HELPER_SPE_SINGLE_CONV(fsctsf);
2301/* efsctuf */
2302HELPER_SPE_SINGLE_CONV(fsctuf);
2303
2304#define HELPER_SPE_VECTOR_CONV(name) \
2305uint64_t helper_ev##name (uint64_t val) \
2306{ \
2307 return ((uint64_t)e##name(val >> 32) << 32) | \
2308 (uint64_t)e##name(val); \
0487d6a8 2309}
1c97856d
AJ		 2310/* evfscfsi */
2311HELPER_SPE_VECTOR_CONV(fscfsi);
2312/* evfscfui */
2313HELPER_SPE_VECTOR_CONV(fscfui);
2314/* evfscfuf */
2315HELPER_SPE_VECTOR_CONV(fscfuf);
2316/* evfscfsf */
2317HELPER_SPE_VECTOR_CONV(fscfsf);
2318/* evfsctsi */
2319HELPER_SPE_VECTOR_CONV(fsctsi);
2320/* evfsctui */
2321HELPER_SPE_VECTOR_CONV(fsctui);
2322/* evfsctsiz */
2323HELPER_SPE_VECTOR_CONV(fsctsiz);
2324/* evfsctuiz */
2325HELPER_SPE_VECTOR_CONV(fsctuiz);
2326/* evfsctsf */
2327HELPER_SPE_VECTOR_CONV(fsctsf);
2328/* evfsctuf */
2329HELPER_SPE_VECTOR_CONV(fsctuf);
0487d6a8 2330
1c97856d
AJ		 2331/* Single-precision floating-point arithmetic */
2332static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
0487d6a8 2333{
1c97856d
AJ		 2334 CPU_FloatU u1, u2;
2335 u1.l = op1;
2336 u2.l = op2;
2337 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2338 return u1.l;
0487d6a8
JM		 2339}
2340
1c97856d 2341static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
0487d6a8 2342{
1c97856d
AJ		 2343 CPU_FloatU u1, u2;
2344 u1.l = op1;
2345 u2.l = op2;
2346 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2347 return u1.l;
0487d6a8
JM		 2348}
2349
1c97856d 2350static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
0487d6a8 2351{
1c97856d
AJ		 2352 CPU_FloatU u1, u2;
2353 u1.l = op1;
2354 u2.l = op2;
2355 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2356 return u1.l;
0487d6a8
JM		 2357}
2358
1c97856d 2359static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
0487d6a8 2360{
1c97856d
AJ		 2361 CPU_FloatU u1, u2;
2362 u1.l = op1;
2363 u2.l = op2;
2364 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2365 return u1.l;
0487d6a8
JM		 2366}
2367
1c97856d
AJ		 2368#define HELPER_SPE_SINGLE_ARITH(name) \
2369uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2370{ \
2371 return e##name(op1, op2); \
2372}
2373/* efsadd */
2374HELPER_SPE_SINGLE_ARITH(fsadd);
2375/* efssub */
2376HELPER_SPE_SINGLE_ARITH(fssub);
2377/* efsmul */
2378HELPER_SPE_SINGLE_ARITH(fsmul);
2379/* efsdiv */
2380HELPER_SPE_SINGLE_ARITH(fsdiv);
2381
2382#define HELPER_SPE_VECTOR_ARITH(name) \
2383uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2384{ \
2385 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2386 (uint64_t)e##name(op1, op2); \
2387}
2388/* evfsadd */
2389HELPER_SPE_VECTOR_ARITH(fsadd);
2390/* evfssub */
2391HELPER_SPE_VECTOR_ARITH(fssub);
2392/* evfsmul */
2393HELPER_SPE_VECTOR_ARITH(fsmul);
2394/* evfsdiv */
2395HELPER_SPE_VECTOR_ARITH(fsdiv);
2396
2397/* Single-precision floating-point comparisons */
2398static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
0487d6a8 2399{
1c97856d
AJ		 2400 CPU_FloatU u1, u2;
2401 u1.l = op1;
2402 u2.l = op2;
2403 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
0487d6a8
JM		 2404}
2405
1c97856d 2406static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
0487d6a8 2407{
1c97856d
AJ		 2408 CPU_FloatU u1, u2;
2409 u1.l = op1;
2410 u2.l = op2;
2411 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
0487d6a8
JM		 2412}
2413
1c97856d 2414static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
0487d6a8 2415{
1c97856d
AJ		 2416 CPU_FloatU u1, u2;
2417 u1.l = op1;
2418 u2.l = op2;
2419 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
0487d6a8
JM		 2420}
2421
1c97856d 2422static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2423{
2424 /* XXX: TODO: test special values (NaN, infinites, ...) */
1c97856d 2425 return efststlt(op1, op2);
0487d6a8
JM		 2426}
2427
1c97856d 2428static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2429{
2430 /* XXX: TODO: test special values (NaN, infinites, ...) */
1c97856d 2431 return efststgt(op1, op2);
0487d6a8
JM		 2432}
2433
1c97856d 2434static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
0487d6a8
JM		 2435{
2436 /* XXX: TODO: test special values (NaN, infinites, ...) */
1c97856d 2437 return efststeq(op1, op2);
0487d6a8
JM		 2438}
2439
1c97856d
AJ		 2440#define HELPER_SINGLE_SPE_CMP(name) \
2441uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2442{ \
2443 return e##name(op1, op2) << 2; \
2444}
2445/* efststlt */
2446HELPER_SINGLE_SPE_CMP(fststlt);
2447/* efststgt */
2448HELPER_SINGLE_SPE_CMP(fststgt);
2449/* efststeq */
2450HELPER_SINGLE_SPE_CMP(fststeq);
2451/* efscmplt */
2452HELPER_SINGLE_SPE_CMP(fscmplt);
2453/* efscmpgt */
2454HELPER_SINGLE_SPE_CMP(fscmpgt);
2455/* efscmpeq */
2456HELPER_SINGLE_SPE_CMP(fscmpeq);
2457
2458static always_inline uint32_t evcmp_merge (int t0, int t1)
0487d6a8 2459{
1c97856d 2460 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
0487d6a8
JM		 2461}
2462
1c97856d
AJ		 2463#define HELPER_VECTOR_SPE_CMP(name) \
2464uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2465{ \
2466 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
0487d6a8 2467}
1c97856d
AJ		 2468/* evfststlt */
2469HELPER_VECTOR_SPE_CMP(fststlt);
2470/* evfststgt */
2471HELPER_VECTOR_SPE_CMP(fststgt);
2472/* evfststeq */
2473HELPER_VECTOR_SPE_CMP(fststeq);
2474/* evfscmplt */
2475HELPER_VECTOR_SPE_CMP(fscmplt);
2476/* evfscmpgt */
2477HELPER_VECTOR_SPE_CMP(fscmpgt);
2478/* evfscmpeq */
2479HELPER_VECTOR_SPE_CMP(fscmpeq);
0487d6a8 2480
1c97856d
AJ		 2481/* Double-precision floating-point conversion */
2482uint64_t helper_efdcfsi (uint32_t val)
0487d6a8 2483{
1c97856d
AJ		 2484 CPU_DoubleU u;
2485
2486 u.d = int32_to_float64(val, &env->spe_status);
2487
2488 return u.ll;
0487d6a8
JM		 2489}
2490
1c97856d 2491uint64_t helper_efdcfsid (uint64_t val)
0487d6a8 2492{
0ca9d380 2493 CPU_DoubleU u;
0487d6a8 2494
0ca9d380 2495 u.d = int64_to_float64(val, &env->spe_status);
0487d6a8 2496
0ca9d380 2497 return u.ll;
0487d6a8
JM		 2498}
2499
1c97856d
AJ		 2500uint64_t helper_efdcfui (uint32_t val)
2501{
2502 CPU_DoubleU u;
2503
2504 u.d = uint32_to_float64(val, &env->spe_status);
2505
2506 return u.ll;
2507}
2508
2509uint64_t helper_efdcfuid (uint64_t val)
0487d6a8 2510{
0ca9d380 2511 CPU_DoubleU u;
0487d6a8 2512
0ca9d380 2513 u.d = uint64_to_float64(val, &env->spe_status);
0487d6a8 2514
0ca9d380 2515 return u.ll;
0487d6a8
JM		 2516}
2517
1c97856d 2518uint32_t helper_efdctsi (uint64_t val)
0487d6a8 2519{
0ca9d380 2520 CPU_DoubleU u;
0487d6a8 2521
0ca9d380 2522 u.ll = val;
0487d6a8 2523 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2524 if (unlikely(float64_is_nan(u.d)))
0487d6a8
JM		 2525 return 0;
2526
1c97856d 2527 return float64_to_int32(u.d, &env->spe_status);
0487d6a8
JM		 2528}
2529
1c97856d 2530uint32_t helper_efdctui (uint64_t val)
0487d6a8 2531{
0ca9d380 2532 CPU_DoubleU u;
0487d6a8 2533
0ca9d380 2534 u.ll = val;
0487d6a8 2535 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2536 if (unlikely(float64_is_nan(u.d)))
0487d6a8
JM		 2537 return 0;
2538
1c97856d 2539 return float64_to_uint32(u.d, &env->spe_status);
0487d6a8
JM		 2540}
2541
1c97856d 2542uint32_t helper_efdctsiz (uint64_t val)
0487d6a8 2543{
0ca9d380 2544 CPU_DoubleU u;
0487d6a8 2545
0ca9d380 2546 u.ll = val;
0487d6a8 2547 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2548 if (unlikely(float64_is_nan(u.d)))
0487d6a8
JM		 2549 return 0;
2550
1c97856d 2551 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2552}
2553
1c97856d 2554uint64_t helper_efdctsidz (uint64_t val)
0487d6a8 2555{
0ca9d380 2556 CPU_DoubleU u;
0487d6a8 2557
0ca9d380 2558 u.ll = val;
0487d6a8 2559 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2560 if (unlikely(float64_is_nan(u.d)))
0487d6a8
JM		 2561 return 0;
2562
1c97856d 2563 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2564}
2565
1c97856d 2566uint32_t helper_efdctuiz (uint64_t val)
0487d6a8 2567{
1c97856d 2568 CPU_DoubleU u;
0487d6a8 2569
1c97856d
AJ		 2570 u.ll = val;
2571 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2572 if (unlikely(float64_is_nan(u.d)))
1c97856d 2573 return 0;
0487d6a8 2574
1c97856d 2575 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2576}
2577
1c97856d 2578uint64_t helper_efdctuidz (uint64_t val)
0487d6a8 2579{
1c97856d 2580 CPU_DoubleU u;
0487d6a8 2581
1c97856d
AJ		 2582 u.ll = val;
2583 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2584 if (unlikely(float64_is_nan(u.d)))
1c97856d 2585 return 0;
0487d6a8 2586
1c97856d 2587 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
0487d6a8
JM		 2588}
2589
1c97856d 2590uint64_t helper_efdcfsf (uint32_t val)
0487d6a8 2591{
0ca9d380 2592 CPU_DoubleU u;
0487d6a8
JM		 2593 float64 tmp;
2594
0ca9d380 2595 u.d = int32_to_float64(val, &env->spe_status);
0487d6a8 2596 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2597 u.d = float64_div(u.d, tmp, &env->spe_status);
0487d6a8 2598
0ca9d380 2599 return u.ll;
0487d6a8
JM		 2600}
2601
1c97856d 2602uint64_t helper_efdcfuf (uint32_t val)
0487d6a8 2603{
0ca9d380 2604 CPU_DoubleU u;
0487d6a8
JM		 2605 float64 tmp;
2606
0ca9d380 2607 u.d = uint32_to_float64(val, &env->spe_status);
0487d6a8 2608 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2609 u.d = float64_div(u.d, tmp, &env->spe_status);
0487d6a8 2610
0ca9d380 2611 return u.ll;
0487d6a8
JM		 2612}
2613
1c97856d 2614uint32_t helper_efdctsf (uint64_t val)
0487d6a8 2615{
0ca9d380 2616 CPU_DoubleU u;
0487d6a8
JM		 2617 float64 tmp;
2618
0ca9d380 2619 u.ll = val;
0487d6a8 2620 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2621 if (unlikely(float64_is_nan(u.d)))
0487d6a8
JM		 2622 return 0;
2623 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2624 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2625
0ca9d380 2626 return float64_to_int32(u.d, &env->spe_status);
0487d6a8
JM		 2627}
2628
1c97856d 2629uint32_t helper_efdctuf (uint64_t val)
0487d6a8 2630{
0ca9d380 2631 CPU_DoubleU u;
0487d6a8
JM		 2632 float64 tmp;
2633
0ca9d380 2634 u.ll = val;
0487d6a8 2635 /* NaN are not treated the same way IEEE 754 does */
a44d2ce1 2636 if (unlikely(float64_is_nan(u.d)))
0487d6a8
JM		 2637 return 0;
2638 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
0ca9d380 2639 u.d = float64_mul(u.d, tmp, &env->spe_status);
0487d6a8 2640
0ca9d380 2641 return float64_to_uint32(u.d, &env->spe_status);
0487d6a8
JM		 2642}
2643
1c97856d 2644uint32_t helper_efscfd (uint64_t val)
0487d6a8 2645{
0ca9d380
AJ		 2646 CPU_DoubleU u1;
2647 CPU_FloatU u2;
0487d6a8 2648
0ca9d380
AJ		 2649 u1.ll = val;
2650 u2.f = float64_to_float32(u1.d, &env->spe_status);
0487d6a8 2651
0ca9d380 2652 return u2.l;
0487d6a8
JM		 2653}
2654
1c97856d 2655uint64_t helper_efdcfs (uint32_t val)
0487d6a8 2656{
0ca9d380
AJ		 2657 CPU_DoubleU u2;
2658 CPU_FloatU u1;
0487d6a8 2659
0ca9d380
AJ		 2660 u1.l = val;
2661 u2.d = float32_to_float64(u1.f, &env->spe_status);
0487d6a8 2662
0ca9d380 2663 return u2.ll;
0487d6a8
JM		 2664}
2665
1c97856d
AJ		 2666/* Double precision fixed-point arithmetic */
2667uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
0487d6a8 2668{
1c97856d
AJ		 2669 CPU_DoubleU u1, u2;
2670 u1.ll = op1;
2671 u2.ll = op2;
2672 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2673 return u1.ll;
0487d6a8
JM		 2674}
2675
1c97856d 2676uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
0487d6a8 2677{
1c97856d
AJ		 2678 CPU_DoubleU u1, u2;
2679 u1.ll = op1;
2680 u2.ll = op2;
2681 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2682 return u1.ll;
0487d6a8
JM		 2683}
2684
1c97856d 2685uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
0487d6a8 2686{
1c97856d
AJ		 2687 CPU_DoubleU u1, u2;
2688 u1.ll = op1;
2689 u2.ll = op2;
2690 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2691 return u1.ll;
0487d6a8
JM		 2692}
2693
1c97856d 2694uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
0487d6a8 2695{
1c97856d
AJ		 2696 CPU_DoubleU u1, u2;
2697 u1.ll = op1;
2698 u2.ll = op2;
2699 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2700 return u1.ll;
0487d6a8
JM		 2701}
2702
1c97856d
AJ		 2703/* Double precision floating point helpers */
2704uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
0487d6a8 2705{
1c97856d
AJ		 2706 CPU_DoubleU u1, u2;
2707 u1.ll = op1;
2708 u2.ll = op2;
2709 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
0487d6a8
JM		 2710}
2711
1c97856d 2712uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
0487d6a8 2713{
1c97856d
AJ		 2714 CPU_DoubleU u1, u2;
2715 u1.ll = op1;
2716 u2.ll = op2;
2717 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
0487d6a8
JM		 2718}
2719
1c97856d 2720uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
0487d6a8 2721{
1c97856d
AJ		 2722 CPU_DoubleU u1, u2;
2723 u1.ll = op1;
2724 u2.ll = op2;
2725 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
0487d6a8
JM		 2726}
2727
1c97856d 2728uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
0487d6a8 2729{
1c97856d
AJ		 2730 /* XXX: TODO: test special values (NaN, infinites, ...) */
2731 return helper_efdtstlt(op1, op2);
0487d6a8
JM		 2732}
2733
1c97856d
AJ		 2734uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2735{
2736 /* XXX: TODO: test special values (NaN, infinites, ...) */
2737 return helper_efdtstgt(op1, op2);
2738}
0487d6a8 2739
1c97856d
AJ		 2740uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2741{
2742 /* XXX: TODO: test special values (NaN, infinites, ...) */
2743 return helper_efdtsteq(op1, op2);
2744}
0487d6a8 2745
fdabc366
FB		 2746/*****************************************************************************/
2747/* Softmmu support */
2748#if !defined (CONFIG_USER_ONLY)
2749
2750#define MMUSUFFIX _mmu
fdabc366
FB		 2751
2752#define SHIFT 0
2753#include "softmmu_template.h"
2754
2755#define SHIFT 1
2756#include "softmmu_template.h"
2757
2758#define SHIFT 2
2759#include "softmmu_template.h"
2760
2761#define SHIFT 3
2762#include "softmmu_template.h"
2763
2764/* try to fill the TLB and return an exception if error. If retaddr is
2765 NULL, it means that the function was called in C code (i.e. not
2766 from generated code or from helper.c) */
2767/* XXX: fix it to restore all registers */
6ebbf390 2768void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
fdabc366
FB		 2769{
2770 TranslationBlock *tb;
2771 CPUState *saved_env;
44f8625d 2772 unsigned long pc;
fdabc366
FB		 2773 int ret;
2774
2775 /* XXX: hack to restore env in all cases, even if not called from
2776 generated code */
2777 saved_env = env;
2778 env = cpu_single_env;
6ebbf390 2779 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
76a66253 2780 if (unlikely(ret != 0)) {
fdabc366
FB		 2781 if (likely(retaddr)) {
2782 /* now we have a real cpu fault */
44f8625d 2783 pc = (unsigned long)retaddr;
fdabc366
FB		 2784 tb = tb_find_pc(pc);
2785 if (likely(tb)) {
2786 /* the PC is inside the translated code. It means that we have
2787 a virtual CPU fault */
2788 cpu_restore_state(tb, env, pc, NULL);
76a66253 2789 }
fdabc366 2790 }
e06fcd75 2791 helper_raise_exception_err(env->exception_index, env->error_code);
fdabc366
FB		 2792 }
2793 env = saved_env;
9a64fbe4
FB		 2794}
2795
74d37793
AJ		 2796/* Segment registers load and store */
2797target_ulong helper_load_sr (target_ulong sr_num)
2798{
2799 return env->sr[sr_num];
2800}
2801
2802void helper_store_sr (target_ulong sr_num, target_ulong val)
2803{
45d827d2 2804 ppc_store_sr(env, sr_num, val);
74d37793
AJ		 2805}
2806
2807/* SLB management */
2808#if defined(TARGET_PPC64)
2809target_ulong helper_load_slb (target_ulong slb_nr)
2810{
2811 return ppc_load_slb(env, slb_nr);
2812}
2813
2814void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2815{
2816 ppc_store_slb(env, slb_nr, rs);
2817}
2818
2819void helper_slbia (void)
2820{
2821 ppc_slb_invalidate_all(env);
2822}
2823
2824void helper_slbie (target_ulong addr)
2825{
2826 ppc_slb_invalidate_one(env, addr);
2827}
2828
2829#endif /* defined(TARGET_PPC64) */
2830
2831/* TLB management */
2832void helper_tlbia (void)
2833{
2834 ppc_tlb_invalidate_all(env);
2835}
2836
2837void helper_tlbie (target_ulong addr)
2838{
2839 ppc_tlb_invalidate_one(env, addr);
2840}
2841
76a66253
JM		 2842/* Software driven TLBs management */
2843/* PowerPC 602/603 software TLB load instructions helpers */
74d37793 2844static void do_6xx_tlb (target_ulong new_EPN, int is_code)
76a66253
JM		 2845{
2846 target_ulong RPN, CMP, EPN;
2847 int way;
d9bce9d9 2848
76a66253
JM		 2849 RPN = env->spr[SPR_RPA];
2850 if (is_code) {
2851 CMP = env->spr[SPR_ICMP];
2852 EPN = env->spr[SPR_IMISS];
2853 } else {
2854 CMP = env->spr[SPR_DCMP];
2855 EPN = env->spr[SPR_DMISS];
2856 }
2857 way = (env->spr[SPR_SRR1] >> 17) & 1;
2858#if defined (DEBUG_SOFTWARE_TLB)
2859 if (loglevel != 0) {
0e69805a 2860 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
6b542af7 2861 " PTE1 " ADDRX " way %d\n",
0e69805a 2862 __func__, new_EPN, EPN, CMP, RPN, way);
76a66253
JM		 2863 }
2864#endif
2865 /* Store this TLB */
0f3955e2 2866 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
d9bce9d9 2867 way, is_code, CMP, RPN);
76a66253
JM		 2868}
2869
74d37793 2870void helper_6xx_tlbd (target_ulong EPN)
0f3955e2 2871{
74d37793 2872 do_6xx_tlb(EPN, 0);
0f3955e2
AJ		 2873}
2874
74d37793 2875void helper_6xx_tlbi (target_ulong EPN)
0f3955e2 2876{
74d37793 2877 do_6xx_tlb(EPN, 1);
0f3955e2
AJ		 2878}
2879
2880/* PowerPC 74xx software TLB load instructions helpers */
74d37793 2881static void do_74xx_tlb (target_ulong new_EPN, int is_code)
7dbe11ac
JM		 2882{
2883 target_ulong RPN, CMP, EPN;
2884 int way;
2885
2886 RPN = env->spr[SPR_PTELO];
2887 CMP = env->spr[SPR_PTEHI];
2888 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2889 way = env->spr[SPR_TLBMISS] & 0x3;
2890#if defined (DEBUG_SOFTWARE_TLB)
2891 if (loglevel != 0) {
0e69805a 2892 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
6b542af7 2893 " PTE1 " ADDRX " way %d\n",
0e69805a 2894 __func__, new_EPN, EPN, CMP, RPN, way);
7dbe11ac
JM		 2895 }
2896#endif
2897 /* Store this TLB */
0f3955e2 2898 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
7dbe11ac
JM		 2899 way, is_code, CMP, RPN);
2900}
2901
74d37793 2902void helper_74xx_tlbd (target_ulong EPN)
0f3955e2 2903{
74d37793 2904 do_74xx_tlb(EPN, 0);
0f3955e2
AJ		 2905}
2906
74d37793 2907void helper_74xx_tlbi (target_ulong EPN)
0f3955e2 2908{
74d37793 2909 do_74xx_tlb(EPN, 1);
0f3955e2
AJ		 2910}
2911
a11b8151 2912static always_inline target_ulong booke_tlb_to_page_size (int size)
a8dea12f
JM		 2913{
2914 return 1024 << (2 * size);
2915}
2916
a11b8151 2917static always_inline int booke_page_size_to_tlb (target_ulong page_size)
a8dea12f
JM		 2918{
2919 int size;
2920
2921 switch (page_size) {
2922 case 0x00000400UL:
2923 size = 0x0;
2924 break;
2925 case 0x00001000UL:
2926 size = 0x1;
2927 break;
2928 case 0x00004000UL:
2929 size = 0x2;
2930 break;
2931 case 0x00010000UL:
2932 size = 0x3;
2933 break;
2934 case 0x00040000UL:
2935 size = 0x4;
2936 break;
2937 case 0x00100000UL:
2938 size = 0x5;
2939 break;
2940 case 0x00400000UL:
2941 size = 0x6;
2942 break;
2943 case 0x01000000UL:
2944 size = 0x7;
2945 break;
2946 case 0x04000000UL:
2947 size = 0x8;
2948 break;
2949 case 0x10000000UL:
2950 size = 0x9;
2951 break;
2952 case 0x40000000UL:
2953 size = 0xA;
2954 break;
2955#if defined (TARGET_PPC64)
2956 case 0x000100000000ULL:
2957 size = 0xB;
2958 break;
2959 case 0x000400000000ULL:
2960 size = 0xC;
2961 break;
2962 case 0x001000000000ULL:
2963 size = 0xD;
2964 break;
2965 case 0x004000000000ULL:
2966 size = 0xE;
2967 break;
2968 case 0x010000000000ULL:
2969 size = 0xF;
2970 break;
2971#endif
2972 default:
2973 size = -1;
2974 break;
2975 }
2976
2977 return size;
2978}
2979
76a66253 2980/* Helpers for 4xx TLB management */
74d37793 2981target_ulong helper_4xx_tlbre_lo (target_ulong entry)
76a66253 2982{
a8dea12f 2983 ppcemb_tlb_t *tlb;
74d37793 2984 target_ulong ret;
a8dea12f 2985 int size;
76a66253 2986
74d37793
AJ		 2987 entry &= 0x3F;
2988 tlb = &env->tlb[entry].tlbe;
2989 ret = tlb->EPN;
a8dea12f 2990 if (tlb->prot & PAGE_VALID)
74d37793 2991 ret |= 0x400;
a8dea12f
JM		 2992 size = booke_page_size_to_tlb(tlb->size);
2993 if (size < 0 || size > 0x7)
2994 size = 1;
74d37793 2995 ret |= size << 7;
a8dea12f 2996 env->spr[SPR_40x_PID] = tlb->PID;
74d37793 2997 return ret;
76a66253
JM		 2998}
2999
74d37793 3000target_ulong helper_4xx_tlbre_hi (target_ulong entry)
76a66253 3001{
a8dea12f 3002 ppcemb_tlb_t *tlb;
74d37793 3003 target_ulong ret;
76a66253 3004
74d37793
AJ		 3005 entry &= 0x3F;
3006 tlb = &env->tlb[entry].tlbe;
3007 ret = tlb->RPN;
a8dea12f 3008 if (tlb->prot & PAGE_EXEC)
74d37793 3009 ret |= 0x200;
a8dea12f 3010 if (tlb->prot & PAGE_WRITE)
74d37793
AJ		 3011 ret |= 0x100;
3012 return ret;
76a66253
JM		 3013}
3014
74d37793 3015void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
76a66253 3016{
a8dea12f 3017 ppcemb_tlb_t *tlb;
76a66253
JM		 3018 target_ulong page, end;
3019
c55e9aef 3020#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 3021 if (loglevel != 0) {
0e69805a 3022 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
c55e9aef
JM		 3023 }
3024#endif
74d37793
AJ		 3025 entry &= 0x3F;
3026 tlb = &env->tlb[entry].tlbe;
76a66253
JM		 3027 /* Invalidate previous TLB (if it's valid) */
3028 if (tlb->prot & PAGE_VALID) {
3029 end = tlb->EPN + tlb->size;
c55e9aef 3030#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 3031 if (loglevel != 0) {
c55e9aef 3032 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
74d37793 3033 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
c55e9aef
JM		 3034 }
3035#endif
76a66253
JM		 3036 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
3037 tlb_flush_page(env, page);
3038 }
74d37793 3039 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
c294fc58
JM		 3040 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
3041 * If this ever occurs, one should use the ppcemb target instead
3042 * of the ppc or ppc64 one
3043 */
74d37793 3044 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
71c8b8fd
JM		 3045 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
3046 "are not supported (%d)\n",
74d37793 3047 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
c294fc58 3048 }
74d37793
AJ		 3049 tlb->EPN = val & ~(tlb->size - 1);
3050 if (val & 0x40)
76a66253
JM		 3051 tlb->prot |= PAGE_VALID;
3052 else
3053 tlb->prot &= ~PAGE_VALID;
74d37793 3054 if (val & 0x20) {
c294fc58
JM		 3055 /* XXX: TO BE FIXED */
3056 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
3057 }
c55e9aef 3058 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
74d37793 3059 tlb->attr = val & 0xFF;
c55e9aef 3060#if defined (DEBUG_SOFTWARE_TLB)
c294fc58
JM		 3061 if (loglevel != 0) {
3062 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 3063 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
0e69805a 3064 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 3065 tlb->prot & PAGE_READ ? 'r' : '-',
3066 tlb->prot & PAGE_WRITE ? 'w' : '-',
3067 tlb->prot & PAGE_EXEC ? 'x' : '-',
3068 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3069 }
3070#endif
76a66253
JM		 3071 /* Invalidate new TLB (if valid) */
3072 if (tlb->prot & PAGE_VALID) {
3073 end = tlb->EPN + tlb->size;
c55e9aef 3074#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 3075 if (loglevel != 0) {
c55e9aef 3076 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
0e69805a 3077 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
c55e9aef
JM		 3078 }
3079#endif
76a66253
JM		 3080 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
3081 tlb_flush_page(env, page);
3082 }
76a66253
JM		 3083}
3084
74d37793 3085void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
76a66253 3086{
a8dea12f 3087 ppcemb_tlb_t *tlb;
76a66253 3088
c55e9aef 3089#if defined (DEBUG_SOFTWARE_TLB)
6b80055d 3090 if (loglevel != 0) {
0e69805a 3091 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
c55e9aef
JM		 3092 }
3093#endif
74d37793
AJ		 3094 entry &= 0x3F;
3095 tlb = &env->tlb[entry].tlbe;
3096 tlb->RPN = val & 0xFFFFFC00;
76a66253 3097 tlb->prot = PAGE_READ;
74d37793 3098 if (val & 0x200)
76a66253 3099 tlb->prot |= PAGE_EXEC;
74d37793 3100 if (val & 0x100)
76a66253 3101 tlb->prot |= PAGE_WRITE;
c55e9aef 3102#if defined (DEBUG_SOFTWARE_TLB)
6b80055d
JM		 3103 if (loglevel != 0) {
3104 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
c55e9aef 3105 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
74d37793 3106 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
c55e9aef
JM		 3107 tlb->prot & PAGE_READ ? 'r' : '-',
3108 tlb->prot & PAGE_WRITE ? 'w' : '-',
3109 tlb->prot & PAGE_EXEC ? 'x' : '-',
3110 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3111 }
3112#endif
76a66253 3113}
5eb7995e 3114
74d37793
AJ		 3115target_ulong helper_4xx_tlbsx (target_ulong address)
3116{
3117 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
3118}
3119
a4bb6c3e 3120/* PowerPC 440 TLB management */
74d37793 3121void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
5eb7995e
JM		 3122{
3123 ppcemb_tlb_t *tlb;
a4bb6c3e 3124 target_ulong EPN, RPN, size;
5eb7995e
JM		 3125 int do_flush_tlbs;
3126
3127#if defined (DEBUG_SOFTWARE_TLB)
3128 if (loglevel != 0) {
0e69805a
AJ		 3129 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3130 __func__, word, (int)entry, value);
5eb7995e
JM		 3131 }
3132#endif
3133 do_flush_tlbs = 0;
74d37793
AJ		 3134 entry &= 0x3F;
3135 tlb = &env->tlb[entry].tlbe;
a4bb6c3e
JM		 3136 switch (word) {
3137 default:
3138 /* Just here to please gcc */
3139 case 0:
74d37793 3140 EPN = value & 0xFFFFFC00;
a4bb6c3e 3141 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
5eb7995e 3142 do_flush_tlbs = 1;
a4bb6c3e 3143 tlb->EPN = EPN;
74d37793 3144 size = booke_tlb_to_page_size((value >> 4) & 0xF);
a4bb6c3e
JM		 3145 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3146 do_flush_tlbs = 1;
3147 tlb->size = size;
3148 tlb->attr &= ~0x1;
74d37793
AJ		 3149 tlb->attr |= (value >> 8) & 1;
3150 if (value & 0x200) {
a4bb6c3e
JM		 3151 tlb->prot |= PAGE_VALID;
3152 } else {
3153 if (tlb->prot & PAGE_VALID) {
3154 tlb->prot &= ~PAGE_VALID;
3155 do_flush_tlbs = 1;
3156 }
5eb7995e 3157 }
a4bb6c3e
JM		 3158 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3159 if (do_flush_tlbs)
3160 tlb_flush(env, 1);
3161 break;
3162 case 1:
74d37793 3163 RPN = value & 0xFFFFFC0F;
a4bb6c3e
JM		 3164 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3165 tlb_flush(env, 1);
3166 tlb->RPN = RPN;
3167 break;
3168 case 2:
74d37793 3169 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
a4bb6c3e 3170 tlb->prot = tlb->prot & PAGE_VALID;
74d37793 3171 if (value & 0x1)
a4bb6c3e 3172 tlb->prot |= PAGE_READ << 4;
74d37793 3173 if (value & 0x2)
a4bb6c3e 3174 tlb->prot |= PAGE_WRITE << 4;
74d37793 3175 if (value & 0x4)
a4bb6c3e 3176 tlb->prot |= PAGE_EXEC << 4;
74d37793 3177 if (value & 0x8)
a4bb6c3e 3178 tlb->prot |= PAGE_READ;
74d37793 3179 if (value & 0x10)
a4bb6c3e 3180 tlb->prot |= PAGE_WRITE;
74d37793 3181 if (value & 0x20)
a4bb6c3e
JM		 3182 tlb->prot |= PAGE_EXEC;
3183 break;
5eb7995e 3184 }
5eb7995e
JM		 3185}
3186
74d37793 3187target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
5eb7995e
JM		 3188{
3189 ppcemb_tlb_t *tlb;
74d37793 3190 target_ulong ret;
5eb7995e
JM		 3191 int size;
3192
74d37793
AJ		 3193 entry &= 0x3F;
3194 tlb = &env->tlb[entry].tlbe;
a4bb6c3e
JM		 3195 switch (word) {
3196 default:
3197 /* Just here to please gcc */
3198 case 0:
74d37793 3199 ret = tlb->EPN;
a4bb6c3e
JM		 3200 size = booke_page_size_to_tlb(tlb->size);
3201 if (size < 0 || size > 0xF)
3202 size = 1;
74d37793 3203 ret |= size << 4;
a4bb6c3e 3204 if (tlb->attr & 0x1)
74d37793 3205 ret |= 0x100;
a4bb6c3e 3206 if (tlb->prot & PAGE_VALID)
74d37793 3207 ret |= 0x200;
a4bb6c3e
JM		 3208 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3209 env->spr[SPR_440_MMUCR] |= tlb->PID;
3210 break;
3211 case 1:
74d37793 3212 ret = tlb->RPN;
a4bb6c3e
JM		 3213 break;
3214 case 2:
74d37793 3215 ret = tlb->attr & ~0x1;
a4bb6c3e 3216 if (tlb->prot & (PAGE_READ << 4))
74d37793 3217 ret |= 0x1;
a4bb6c3e 3218 if (tlb->prot & (PAGE_WRITE << 4))
74d37793 3219 ret |= 0x2;
a4bb6c3e 3220 if (tlb->prot & (PAGE_EXEC << 4))
74d37793 3221 ret |= 0x4;
a4bb6c3e 3222 if (tlb->prot & PAGE_READ)
74d37793 3223 ret |= 0x8;
a4bb6c3e 3224 if (tlb->prot & PAGE_WRITE)
74d37793 3225 ret |= 0x10;
a4bb6c3e 3226 if (tlb->prot & PAGE_EXEC)
74d37793 3227 ret |= 0x20;
a4bb6c3e
JM		 3228 break;
3229 }
74d37793 3230 return ret;
5eb7995e 3231}
74d37793
AJ		 3232
3233target_ulong helper_440_tlbsx (target_ulong address)
3234{
3235 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3236}
3237
76a66253 3238#endif /* !CONFIG_USER_ONLY */
Qemu copy for testing