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Fix fcntl64 logic bug, by Kirill A. Shutemov.
[qemu.git] / target-ppc / op_helper.c
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9a64fbe4 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
9a64fbe4 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
9a64fbe4
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
9a64fbe4
FB
20#include "exec.h"
21
0487d6a8
JM
22#include "op_helper.h"
23
9a64fbe4 24#define MEMSUFFIX _raw
0487d6a8 25#include "op_helper.h"
9a64fbe4 26#include "op_helper_mem.h"
a541f297 27#if !defined(CONFIG_USER_ONLY)
9a64fbe4 28#define MEMSUFFIX _user
0487d6a8 29#include "op_helper.h"
9a64fbe4
FB
30#include "op_helper_mem.h"
31#define MEMSUFFIX _kernel
0487d6a8 32#include "op_helper.h"
9a64fbe4
FB
33#include "op_helper_mem.h"
34#endif
35
fdabc366
FB
36//#define DEBUG_OP
37//#define DEBUG_EXCEPTIONS
76a66253 38//#define DEBUG_SOFTWARE_TLB
fdabc366
FB
39//#define FLUSH_ALL_TLBS
40
9a64fbe4
FB
41/*****************************************************************************/
42/* Exceptions processing helpers */
76a66253 43void cpu_loop_exit (void)
9a64fbe4 44{
9fddaa0c 45 longjmp(env->jmp_env, 1);
9a64fbe4
FB
46}
47
9fddaa0c 48void do_raise_exception_err (uint32_t exception, int error_code)
9a64fbe4 49{
9fddaa0c
FB
50#if 0
51 printf("Raise exception %3x code : %d\n", exception, error_code);
52#endif
53 switch (exception) {
9fddaa0c 54 case EXCP_PROGRAM:
76a66253
JM
55 if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
56 return;
57 break;
9fddaa0c 58 default:
76a66253
JM
59 break;
60 }
9fddaa0c
FB
61 env->exception_index = exception;
62 env->error_code = error_code;
76a66253
JM
63 cpu_loop_exit();
64}
9fddaa0c
FB
65
66void do_raise_exception (uint32_t exception)
67{
68 do_raise_exception_err(exception, 0);
9a64fbe4
FB
69}
70
76a66253
JM
71/*****************************************************************************/
72/* Registers load and stores */
73void do_load_cr (void)
74{
75 T0 = (env->crf[0] << 28) |
76 (env->crf[1] << 24) |
77 (env->crf[2] << 20) |
78 (env->crf[3] << 16) |
79 (env->crf[4] << 12) |
80 (env->crf[5] << 8) |
81 (env->crf[6] << 4) |
82 (env->crf[7] << 0);
83}
84
85void do_store_cr (uint32_t mask)
86{
87 int i, sh;
88
89 for (i = 0, sh = 7; i < 8; i++, sh --) {
90 if (mask & (1 << sh))
91 env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
92 }
93}
94
95void do_load_xer (void)
96{
97 T0 = (xer_so << XER_SO) |
98 (xer_ov << XER_OV) |
99 (xer_ca << XER_CA) |
100 (xer_bc << XER_BC) |
101 (xer_cmp << XER_CMP);
102}
103
104void do_store_xer (void)
105{
106 xer_so = (T0 >> XER_SO) & 0x01;
107 xer_ov = (T0 >> XER_OV) & 0x01;
108 xer_ca = (T0 >> XER_CA) & 0x01;
109 xer_cmp = (T0 >> XER_CMP) & 0xFF;
d9bce9d9 110 xer_bc = (T0 >> XER_BC) & 0x7F;
76a66253
JM
111}
112
113void do_load_fpscr (void)
114{
115 /* The 32 MSB of the target fpr are undefined.
116 * They'll be zero...
117 */
118 union {
119 float64 d;
120 struct {
121 uint32_t u[2];
122 } s;
123 } u;
124 int i;
125
d9bce9d9 126#if defined(WORDS_BIGENDIAN)
76a66253
JM
127#define WORD0 0
128#define WORD1 1
129#else
130#define WORD0 1
131#define WORD1 0
132#endif
133 u.s.u[WORD0] = 0;
134 u.s.u[WORD1] = 0;
135 for (i = 0; i < 8; i++)
136 u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
137 FT0 = u.d;
138}
139
140void do_store_fpscr (uint32_t mask)
141{
142 /*
143 * We use only the 32 LSB of the incoming fpr
144 */
145 union {
146 double d;
147 struct {
148 uint32_t u[2];
149 } s;
150 } u;
151 int i, rnd_type;
152
153 u.d = FT0;
154 if (mask & 0x80)
155 env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
156 for (i = 1; i < 7; i++) {
157 if (mask & (1 << (7 - i)))
158 env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
159 }
160 /* TODO: update FEX & VX */
161 /* Set rounding mode */
162 switch (env->fpscr[0] & 0x3) {
163 case 0:
164 /* Best approximation (round to nearest) */
165 rnd_type = float_round_nearest_even;
166 break;
167 case 1:
168 /* Smaller magnitude (round toward zero) */
169 rnd_type = float_round_to_zero;
170 break;
171 case 2:
172 /* Round toward +infinite */
173 rnd_type = float_round_up;
174 break;
175 default:
176 case 3:
177 /* Round toward -infinite */
178 rnd_type = float_round_down;
179 break;
180 }
181 set_float_rounding_mode(rnd_type, &env->fp_status);
182}
183
9a64fbe4 184/*****************************************************************************/
fdabc366 185/* Fixed point operations helpers */
d9bce9d9
JM
186#if defined(TARGET_PPC64)
187static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
fdabc366 188{
d9bce9d9
JM
189 *plow += a;
190 /* carry test */
191 if (*plow < a)
192 (*phigh)++;
193 *phigh += b;
fdabc366
FB
194}
195
d9bce9d9 196static void neg128 (uint64_t *plow, uint64_t *phigh)
fdabc366 197{
d9bce9d9
JM
198 *plow = ~ *plow;
199 *phigh = ~ *phigh;
200 add128(plow, phigh, 1, 0);
201}
202
203static void mul64 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
204{
205 uint32_t a0, a1, b0, b1;
206 uint64_t v;
207
208 a0 = a;
209 a1 = a >> 32;
210
211 b0 = b;
212 b1 = b >> 32;
213
214 v = (uint64_t)a0 * (uint64_t)b0;
215 *plow = v;
216 *phigh = 0;
217
218 v = (uint64_t)a0 * (uint64_t)b1;
219 add128(plow, phigh, v << 32, v >> 32);
220
221 v = (uint64_t)a1 * (uint64_t)b0;
222 add128(plow, phigh, v << 32, v >> 32);
223
224 v = (uint64_t)a1 * (uint64_t)b1;
225 *phigh += v;
226#if defined(DEBUG_MULDIV)
227 printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
228 a, b, *phigh, *plow);
229#endif
230}
231
232void do_mul64 (uint64_t *plow, uint64_t *phigh)
233{
234 mul64(plow, phigh, T0, T1);
235}
236
0487d6a8 237static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
d9bce9d9
JM
238{
239 int sa, sb;
240 sa = (a < 0);
241 if (sa)
242 a = -a;
243 sb = (b < 0);
244 if (sb)
245 b = -b;
246 mul64(plow, phigh, a, b);
247 if (sa ^ sb) {
248 neg128(plow, phigh);
fdabc366
FB
249 }
250}
251
d9bce9d9
JM
252void do_imul64 (uint64_t *plow, uint64_t *phigh)
253{
254 imul64(plow, phigh, T0, T1);
255}
256#endif
257
fdabc366
FB
258void do_adde (void)
259{
260 T2 = T0;
261 T0 += T1 + xer_ca;
d9bce9d9
JM
262 if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
263 (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
fdabc366
FB
264 xer_ca = 0;
265 } else {
266 xer_ca = 1;
267 }
268}
269
d9bce9d9
JM
270#if defined(TARGET_PPC64)
271void do_adde_64 (void)
fdabc366
FB
272{
273 T2 = T0;
274 T0 += T1 + xer_ca;
d9bce9d9
JM
275 if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
276 (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
fdabc366
FB
277 xer_ca = 0;
278 } else {
279 xer_ca = 1;
280 }
fdabc366 281}
d9bce9d9 282#endif
fdabc366
FB
283
284void do_addmeo (void)
285{
286 T1 = T0;
287 T0 += xer_ca + (-1);
d9bce9d9
JM
288 if (likely(!((uint32_t)T1 &
289 ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
fdabc366
FB
290 xer_ov = 0;
291 } else {
292 xer_so = 1;
293 xer_ov = 1;
294 }
295 if (likely(T1 != 0))
296 xer_ca = 1;
297}
298
d9bce9d9
JM
299#if defined(TARGET_PPC64)
300void do_addmeo_64 (void)
fdabc366
FB
301{
302 T1 = T0;
d9bce9d9
JM
303 T0 += xer_ca + (-1);
304 if (likely(!((uint64_t)T1 &
305 ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
fdabc366
FB
306 xer_ov = 0;
307 } else {
308 xer_so = 1;
309 xer_ov = 1;
310 }
d9bce9d9 311 if (likely(T1 != 0))
fdabc366 312 xer_ca = 1;
fdabc366 313}
d9bce9d9 314#endif
fdabc366
FB
315
316void do_divwo (void)
317{
d9bce9d9
JM
318 if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
319 (int32_t)T1 == 0))) {
fdabc366 320 xer_ov = 0;
d9bce9d9 321 T0 = (int32_t)T0 / (int32_t)T1;
fdabc366
FB
322 } else {
323 xer_so = 1;
324 xer_ov = 1;
325 T0 = (-1) * ((uint32_t)T0 >> 31);
326 }
327}
328
d9bce9d9
JM
329#if defined(TARGET_PPC64)
330void do_divdo (void)
331{
332 if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
333 (int64_t)T1 == 0))) {
334 xer_ov = 0;
335 T0 = (int64_t)T0 / (int64_t)T1;
336 } else {
337 xer_so = 1;
338 xer_ov = 1;
339 T0 = (-1ULL) * ((uint64_t)T0 >> 63);
340 }
341}
342#endif
343
fdabc366
FB
344void do_divwuo (void)
345{
346 if (likely((uint32_t)T1 != 0)) {
347 xer_ov = 0;
348 T0 = (uint32_t)T0 / (uint32_t)T1;
349 } else {
350 xer_so = 1;
351 xer_ov = 1;
352 T0 = 0;
353 }
354}
355
d9bce9d9
JM
356#if defined(TARGET_PPC64)
357void do_divduo (void)
358{
359 if (likely((uint64_t)T1 != 0)) {
360 xer_ov = 0;
361 T0 = (uint64_t)T0 / (uint64_t)T1;
362 } else {
363 xer_so = 1;
364 xer_ov = 1;
365 T0 = 0;
366 }
367}
368#endif
369
fdabc366
FB
370void do_mullwo (void)
371{
d9bce9d9 372 int64_t res = (int64_t)T0 * (int64_t)T1;
fdabc366
FB
373
374 if (likely((int32_t)res == res)) {
375 xer_ov = 0;
376 } else {
377 xer_ov = 1;
378 xer_so = 1;
379 }
380 T0 = (int32_t)res;
381}
382
d9bce9d9
JM
383#if defined(TARGET_PPC64)
384void do_mulldo (void)
fdabc366 385{
d9bce9d9
JM
386 int64_t th;
387 uint64_t tl;
388
389 do_imul64(&tl, &th);
390 if (likely(th == 0)) {
fdabc366 391 xer_ov = 0;
fdabc366
FB
392 } else {
393 xer_ov = 1;
394 xer_so = 1;
395 }
d9bce9d9 396 T0 = (int64_t)tl;
fdabc366 397}
d9bce9d9 398#endif
fdabc366 399
d9bce9d9 400void do_nego (void)
fdabc366 401{
d9bce9d9 402 if (likely((int32_t)T0 != INT32_MIN)) {
fdabc366 403 xer_ov = 0;
d9bce9d9 404 T0 = -(int32_t)T0;
fdabc366 405 } else {
fdabc366 406 xer_ov = 1;
d9bce9d9 407 xer_so = 1;
fdabc366 408 }
fdabc366
FB
409}
410
d9bce9d9
JM
411#if defined(TARGET_PPC64)
412void do_nego_64 (void)
fdabc366 413{
d9bce9d9 414 if (likely((int64_t)T0 != INT64_MIN)) {
fdabc366 415 xer_ov = 0;
d9bce9d9 416 T0 = -(int64_t)T0;
fdabc366 417 } else {
fdabc366 418 xer_ov = 1;
d9bce9d9 419 xer_so = 1;
fdabc366
FB
420 }
421}
d9bce9d9 422#endif
fdabc366
FB
423
424void do_subfe (void)
425{
426 T0 = T1 + ~T0 + xer_ca;
d9bce9d9
JM
427 if (likely((uint32_t)T0 >= (uint32_t)T1 &&
428 (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
fdabc366
FB
429 xer_ca = 0;
430 } else {
431 xer_ca = 1;
432 }
433}
434
d9bce9d9
JM
435#if defined(TARGET_PPC64)
436void do_subfe_64 (void)
fdabc366 437{
fdabc366 438 T0 = T1 + ~T0 + xer_ca;
d9bce9d9
JM
439 if (likely((uint64_t)T0 >= (uint64_t)T1 &&
440 (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
441 xer_ca = 0;
442 } else {
443 xer_ca = 1;
444 }
445}
446#endif
447
448void do_subfmeo (void)
449{
450 T1 = T0;
451 T0 = ~T0 + xer_ca - 1;
452 if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
453 (1UL << 31)))) {
fdabc366
FB
454 xer_ov = 0;
455 } else {
456 xer_so = 1;
457 xer_ov = 1;
458 }
d9bce9d9 459 if (likely((uint32_t)T1 != UINT32_MAX))
fdabc366 460 xer_ca = 1;
fdabc366
FB
461}
462
d9bce9d9
JM
463#if defined(TARGET_PPC64)
464void do_subfmeo_64 (void)
fdabc366
FB
465{
466 T1 = T0;
467 T0 = ~T0 + xer_ca - 1;
d9bce9d9
JM
468 if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
469 (1ULL << 63)))) {
fdabc366
FB
470 xer_ov = 0;
471 } else {
472 xer_so = 1;
473 xer_ov = 1;
474 }
d9bce9d9 475 if (likely((uint64_t)T1 != UINT64_MAX))
fdabc366
FB
476 xer_ca = 1;
477}
d9bce9d9 478#endif
fdabc366
FB
479
480void do_subfzeo (void)
481{
482 T1 = T0;
483 T0 = ~T0 + xer_ca;
d9bce9d9
JM
484 if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
485 ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
fdabc366
FB
486 xer_ov = 0;
487 } else {
488 xer_ov = 1;
489 xer_so = 1;
490 }
d9bce9d9 491 if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
fdabc366
FB
492 xer_ca = 0;
493 } else {
494 xer_ca = 1;
495 }
496}
497
d9bce9d9
JM
498#if defined(TARGET_PPC64)
499void do_subfzeo_64 (void)
500{
501 T1 = T0;
502 T0 = ~T0 + xer_ca;
503 if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
504 ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
505 xer_ov = 0;
506 } else {
507 xer_ov = 1;
508 xer_so = 1;
509 }
510 if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
511 xer_ca = 0;
512 } else {
513 xer_ca = 1;
514 }
515}
516#endif
517
9a64fbe4
FB
518/* shift right arithmetic helper */
519void do_sraw (void)
520{
521 int32_t ret;
522
fdabc366 523 if (likely(!(T1 & 0x20UL))) {
d9bce9d9 524 if (likely((uint32_t)T1 != 0)) {
fdabc366
FB
525 ret = (int32_t)T0 >> (T1 & 0x1fUL);
526 if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
76a66253 527 xer_ca = 0;
fdabc366 528 } else {
76a66253 529 xer_ca = 1;
fdabc366
FB
530 }
531 } else {
76a66253 532 ret = T0;
fdabc366
FB
533 xer_ca = 0;
534 }
535 } else {
536 ret = (-1) * ((uint32_t)T0 >> 31);
537 if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
538 xer_ca = 0;
76a66253 539 } else {
9a64fbe4 540 xer_ca = 1;
76a66253 541 }
fdabc366 542 }
4b3686fa 543 T0 = ret;
9a64fbe4
FB
544}
545
d9bce9d9
JM
546#if defined(TARGET_PPC64)
547void do_srad (void)
548{
549 int64_t ret;
550
551 if (likely(!(T1 & 0x40UL))) {
552 if (likely((uint64_t)T1 != 0)) {
553 ret = (int64_t)T0 >> (T1 & 0x3FUL);
554 if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
555 xer_ca = 0;
556 } else {
557 xer_ca = 1;
558 }
559 } else {
560 ret = T0;
561 xer_ca = 0;
562 }
563 } else {
564 ret = (-1) * ((uint64_t)T0 >> 63);
565 if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
566 xer_ca = 0;
567 } else {
568 xer_ca = 1;
569 }
570 }
571 T0 = ret;
572}
573#endif
574
575static inline int popcnt (uint32_t val)
576{
577 int i;
578
579 for (i = 0; val != 0;)
580 val = val ^ (val - 1);
581
582 return i;
583}
584
585void do_popcntb (void)
586{
587 uint32_t ret;
588 int i;
589
590 ret = 0;
591 for (i = 0; i < 32; i += 8)
592 ret |= popcnt((T0 >> i) & 0xFF) << i;
593 T0 = ret;
594}
595
596#if defined(TARGET_PPC64)
597void do_popcntb_64 (void)
598{
599 uint64_t ret;
600 int i;
601
602 ret = 0;
603 for (i = 0; i < 64; i += 8)
604 ret |= popcnt((T0 >> i) & 0xFF) << i;
605 T0 = ret;
606}
607#endif
608
fdabc366 609/*****************************************************************************/
9a64fbe4 610/* Floating point operations helpers */
9a64fbe4
FB
611void do_fctiw (void)
612{
613 union {
614 double d;
615 uint64_t i;
4ecc3190 616 } p;
9a64fbe4 617
4ecc3190 618 /* XXX: higher bits are not supposed to be significant.
76a66253 619 * to make tests easier, return the same as a real PowerPC 750 (aka G3)
4ecc3190
FB
620 */
621 p.i = float64_to_int32(FT0, &env->fp_status);
622 p.i |= 0xFFF80000ULL << 32;
623 FT0 = p.d;
9a64fbe4
FB
624}
625
626void do_fctiwz (void)
627{
628 union {
629 double d;
630 uint64_t i;
4ecc3190
FB
631 } p;
632
633 /* XXX: higher bits are not supposed to be significant.
d9bce9d9 634 * to make tests easier, return the same as a real PowerPC 750 (aka G3)
4ecc3190
FB
635 */
636 p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
637 p.i |= 0xFFF80000ULL << 32;
638 FT0 = p.d;
9a64fbe4
FB
639}
640
4b3686fa
FB
641void do_fnmadd (void)
642{
fdabc366
FB
643 FT0 = float64_mul(FT0, FT1, &env->fp_status);
644 FT0 = float64_add(FT0, FT2, &env->fp_status);
645 if (likely(!isnan(FT0)))
646 FT0 = float64_chs(FT0);
4b3686fa
FB
647}
648
649void do_fnmsub (void)
650{
fdabc366
FB
651 FT0 = float64_mul(FT0, FT1, &env->fp_status);
652 FT0 = float64_sub(FT0, FT2, &env->fp_status);
653 if (likely(!isnan(FT0)))
654 FT0 = float64_chs(FT0);
1ef59d0a
FB
655}
656
9a64fbe4
FB
657void do_fsqrt (void)
658{
fdabc366 659 FT0 = float64_sqrt(FT0, &env->fp_status);
9a64fbe4
FB
660}
661
9a64fbe4
FB
662void do_fres (void)
663{
4ecc3190
FB
664 union {
665 double d;
666 uint64_t i;
667 } p;
668
fdabc366 669 if (likely(isnormal(FT0))) {
76a66253 670 FT0 = float32_div(1.0, FT0, &env->fp_status);
4ecc3190
FB
671 } else {
672 p.d = FT0;
673 if (p.i == 0x8000000000000000ULL) {
674 p.i = 0xFFF0000000000000ULL;
675 } else if (p.i == 0x0000000000000000ULL) {
676 p.i = 0x7FF0000000000000ULL;
677 } else if (isnan(FT0)) {
678 p.i = 0x7FF8000000000000ULL;
679 } else if (FT0 < 0.0) {
680 p.i = 0x8000000000000000ULL;
681 } else {
682 p.i = 0x0000000000000000ULL;
683 }
684 FT0 = p.d;
685 }
9a64fbe4
FB
686}
687
4ecc3190 688void do_frsqrte (void)
9a64fbe4 689{
4ecc3190
FB
690 union {
691 double d;
692 uint64_t i;
693 } p;
694
fdabc366
FB
695 if (likely(isnormal(FT0) && FT0 > 0.0)) {
696 FT0 = float64_sqrt(FT0, &env->fp_status);
697 FT0 = float32_div(1.0, FT0, &env->fp_status);
4ecc3190
FB
698 } else {
699 p.d = FT0;
700 if (p.i == 0x8000000000000000ULL) {
701 p.i = 0xFFF0000000000000ULL;
702 } else if (p.i == 0x0000000000000000ULL) {
703 p.i = 0x7FF0000000000000ULL;
704 } else if (isnan(FT0)) {
705 if (!(p.i & 0x0008000000000000ULL))
706 p.i |= 0x000FFFFFFFFFFFFFULL;
707 } else if (FT0 < 0) {
708 p.i = 0x7FF8000000000000ULL;
709 } else {
710 p.i = 0x0000000000000000ULL;
711 }
712 FT0 = p.d;
713 }
9a64fbe4
FB
714}
715
716void do_fsel (void)
717{
718 if (FT0 >= 0)
9a64fbe4 719 FT0 = FT1;
4ecc3190
FB
720 else
721 FT0 = FT2;
9a64fbe4
FB
722}
723
724void do_fcmpu (void)
725{
fdabc366
FB
726 if (likely(!isnan(FT0) && !isnan(FT1))) {
727 if (float64_lt(FT0, FT1, &env->fp_status)) {
728 T0 = 0x08UL;
729 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
730 T0 = 0x04UL;
731 } else {
732 T0 = 0x02UL;
733 }
734 } else {
735 T0 = 0x01UL;
9a64fbe4
FB
736 env->fpscr[4] |= 0x1;
737 env->fpscr[6] |= 0x1;
9a64fbe4 738 }
4b3686fa 739 env->fpscr[3] = T0;
9a64fbe4
FB
740}
741
742void do_fcmpo (void)
743{
744 env->fpscr[4] &= ~0x1;
fdabc366
FB
745 if (likely(!isnan(FT0) && !isnan(FT1))) {
746 if (float64_lt(FT0, FT1, &env->fp_status)) {
747 T0 = 0x08UL;
748 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
749 T0 = 0x04UL;
750 } else {
751 T0 = 0x02UL;
752 }
753 } else {
754 T0 = 0x01UL;
9a64fbe4 755 env->fpscr[4] |= 0x1;
76a66253
JM
756 if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) {
757 /* Quiet NaN case */
9a64fbe4
FB
758 env->fpscr[6] |= 0x1;
759 if (!(env->fpscr[1] & 0x8))
760 env->fpscr[4] |= 0x8;
761 } else {
762 env->fpscr[4] |= 0x8;
763 }
9a64fbe4 764 }
4b3686fa 765 env->fpscr[3] = T0;
9a64fbe4
FB
766}
767
76a66253 768#if !defined (CONFIG_USER_ONLY)
fdabc366 769void do_rfi (void)
9a64fbe4 770{
d9bce9d9
JM
771 env->nip = (target_ulong)(env->spr[SPR_SRR0] & ~0x00000003);
772 T0 = (target_ulong)(env->spr[SPR_SRR1] & ~0xFFFF0000UL);
fdabc366
FB
773 do_store_msr(env, T0);
774#if defined (DEBUG_OP)
775 dump_rfi();
776#endif
777 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
9a64fbe4 778}
d9bce9d9
JM
779
780#if defined(TARGET_PPC64)
781void do_rfi_32 (void)
782{
783 env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
784 T0 = (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL);
785 do_store_msr(env, T0);
786#if defined (DEBUG_OP)
787 dump_rfi();
788#endif
789 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
790}
791#endif
76a66253 792#endif
9a64fbe4 793
76a66253 794void do_tw (int flags)
9a64fbe4 795{
d9bce9d9
JM
796 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
797 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
798 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
799 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
800 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01)))))
fdabc366 801 do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
9a64fbe4
FB
802}
803
d9bce9d9
JM
804#if defined(TARGET_PPC64)
805void do_td (int flags)
806{
807 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
808 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
809 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
810 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
811 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
812 do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
813}
814#endif
815
fdabc366 816/*****************************************************************************/
76a66253
JM
817/* PowerPC 601 specific instructions (POWER bridge) */
818void do_POWER_abso (void)
9a64fbe4 819{
d9bce9d9 820 if ((uint32_t)T0 == INT32_MIN) {
76a66253
JM
821 T0 = INT32_MAX;
822 xer_ov = 1;
823 xer_so = 1;
824 } else {
825 T0 = -T0;
826 xer_ov = 0;
827 }
9a64fbe4
FB
828}
829
76a66253 830void do_POWER_clcs (void)
9a64fbe4 831{
76a66253
JM
832 switch (T0) {
833 case 0x0CUL:
834 /* Instruction cache line size */
835 T0 = ICACHE_LINE_SIZE;
836 break;
837 case 0x0DUL:
838 /* Data cache line size */
839 T0 = DCACHE_LINE_SIZE;
840 break;
841 case 0x0EUL:
842 /* Minimum cache line size */
843 T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
844 ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
845 break;
846 case 0x0FUL:
847 /* Maximum cache line size */
848 T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
849 ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
850 break;
851 default:
852 /* Undefined */
853 break;
854 }
855}
856
857void do_POWER_div (void)
858{
859 uint64_t tmp;
860
d9bce9d9 861 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM
862 T0 = (long)((-1) * (T0 >> 31));
863 env->spr[SPR_MQ] = 0;
864 } else {
865 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
866 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 867 T0 = tmp / (int32_t)T1;
76a66253
JM
868 }
869}
870
871void do_POWER_divo (void)
872{
873 int64_t tmp;
874
d9bce9d9 875 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM
876 T0 = (long)((-1) * (T0 >> 31));
877 env->spr[SPR_MQ] = 0;
878 xer_ov = 1;
879 xer_so = 1;
880 } else {
881 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
882 env->spr[SPR_MQ] = tmp % T1;
d9bce9d9 883 tmp /= (int32_t)T1;
76a66253
JM
884 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
885 xer_ov = 1;
886 xer_so = 1;
887 } else {
888 xer_ov = 0;
889 }
890 T0 = tmp;
891 }
892}
893
894void do_POWER_divs (void)
895{
d9bce9d9 896 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM
897 T0 = (long)((-1) * (T0 >> 31));
898 env->spr[SPR_MQ] = 0;
899 } else {
900 env->spr[SPR_MQ] = T0 % T1;
d9bce9d9 901 T0 = (int32_t)T0 / (int32_t)T1;
76a66253
JM
902 }
903}
904
905void do_POWER_divso (void)
906{
d9bce9d9 907 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
76a66253
JM
908 T0 = (long)((-1) * (T0 >> 31));
909 env->spr[SPR_MQ] = 0;
910 xer_ov = 1;
911 xer_so = 1;
912 } else {
d9bce9d9
JM
913 T0 = (int32_t)T0 / (int32_t)T1;
914 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
76a66253
JM
915 xer_ov = 0;
916 }
917}
918
919void do_POWER_dozo (void)
920{
d9bce9d9 921 if ((int32_t)T1 > (int32_t)T0) {
76a66253
JM
922 T2 = T0;
923 T0 = T1 - T0;
d9bce9d9
JM
924 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
925 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
76a66253
JM
926 xer_so = 1;
927 xer_ov = 1;
928 } else {
929 xer_ov = 0;
930 }
931 } else {
932 T0 = 0;
933 xer_ov = 0;
934 }
935}
936
937void do_POWER_maskg (void)
938{
939 uint32_t ret;
940
d9bce9d9 941 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
76a66253
JM
942 ret = -1;
943 } else {
d9bce9d9
JM
944 ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
945 (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
946 if ((uint32_t)T0 > (uint32_t)T1)
76a66253
JM
947 ret = ~ret;
948 }
949 T0 = ret;
950}
951
952void do_POWER_mulo (void)
953{
954 uint64_t tmp;
955
956 tmp = (uint64_t)T0 * (uint64_t)T1;
957 env->spr[SPR_MQ] = tmp >> 32;
958 T0 = tmp;
959 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
960 xer_ov = 1;
961 xer_so = 1;
962 } else {
963 xer_ov = 0;
964 }
965}
966
967#if !defined (CONFIG_USER_ONLY)
968void do_POWER_rac (void)
969{
970#if 0
971 mmu_ctx_t ctx;
972
973 /* We don't have to generate many instances of this instruction,
974 * as rac is supervisor only.
975 */
976 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
977 T0 = ctx.raddr;
978#endif
979}
980
981void do_POWER_rfsvc (void)
982{
983 env->nip = env->lr & ~0x00000003UL;
984 T0 = env->ctr & 0x0000FFFFUL;
985 do_store_msr(env, T0);
986#if defined (DEBUG_OP)
987 dump_rfi();
988#endif
989 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
990}
991
992/* PowerPC 601 BAT management helper */
993void do_store_601_batu (int nr)
994{
d9bce9d9 995 do_store_ibatu(env, nr, (uint32_t)T0);
76a66253
JM
996 env->DBAT[0][nr] = env->IBAT[0][nr];
997 env->DBAT[1][nr] = env->IBAT[1][nr];
998}
999#endif
1000
1001/*****************************************************************************/
1002/* 602 specific instructions */
1003/* mfrom is the most crazy instruction ever seen, imho ! */
1004/* Real implementation uses a ROM table. Do the same */
1005#define USE_MFROM_ROM_TABLE
1006void do_op_602_mfrom (void)
1007{
1008 if (likely(T0 < 602)) {
d9bce9d9 1009#if defined(USE_MFROM_ROM_TABLE)
76a66253
JM
1010#include "mfrom_table.c"
1011 T0 = mfrom_ROM_table[T0];
fdabc366 1012#else
76a66253
JM
1013 double d;
1014 /* Extremly decomposed:
1015 * -T0 / 256
1016 * T0 = 256 * log10(10 + 1.0) + 0.5
1017 */
1018 d = T0;
1019 d = float64_div(d, 256, &env->fp_status);
1020 d = float64_chs(d);
1021 d = exp10(d); // XXX: use float emulation function
1022 d = float64_add(d, 1.0, &env->fp_status);
1023 d = log10(d); // XXX: use float emulation function
1024 d = float64_mul(d, 256, &env->fp_status);
1025 d = float64_add(d, 0.5, &env->fp_status);
1026 T0 = float64_round_to_int(d, &env->fp_status);
fdabc366 1027#endif
76a66253
JM
1028 } else {
1029 T0 = 0;
1030 }
1031}
1032
1033/*****************************************************************************/
1034/* Embedded PowerPC specific helpers */
1035void do_405_check_ov (void)
1036{
d9bce9d9
JM
1037 if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1038 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
76a66253
JM
1039 xer_ov = 0;
1040 } else {
1041 xer_ov = 1;
1042 xer_so = 1;
1043 }
1044}
1045
1046void do_405_check_sat (void)
1047{
d9bce9d9
JM
1048 if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1049 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
76a66253
JM
1050 /* Saturate result */
1051 if (T2 >> 31) {
1052 T0 = INT32_MIN;
1053 } else {
1054 T0 = INT32_MAX;
1055 }
1056 }
1057}
1058
1059#if !defined(CONFIG_USER_ONLY)
1060void do_4xx_rfci (void)
1061{
1062 env->nip = env->spr[SPR_40x_SRR2];
1063 T0 = env->spr[SPR_40x_SRR3] & ~0xFFFF0000;
1064 do_store_msr(env, T0);
1065#if defined (DEBUG_OP)
1066 dump_rfi();
1067#endif
1068 env->interrupt_request = CPU_INTERRUPT_EXITTB;
1069}
1070
1071void do_4xx_load_dcr (int dcrn)
1072{
1073 target_ulong val;
1074
1075 if (unlikely(env->dcr_read == NULL))
1076 do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1077 else if (unlikely((*env->dcr_read)(env->dcr_env, dcrn, &val) != 0))
1078 do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1079 else
1080 T0 = val;
1081}
1082
1083void do_4xx_store_dcr (int dcrn)
1084{
1085 if (unlikely(env->dcr_write == NULL))
1086 do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL);
1087 else if (unlikely((*env->dcr_write)(env->dcr_env, dcrn, T0) != 0))
1088 do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG);
1089}
1090
1091void do_load_403_pb (int num)
1092{
1093 T0 = env->pb[num];
1094}
1095
1096void do_store_403_pb (int num)
1097{
1098 if (likely(env->pb[num] != T0)) {
1099 env->pb[num] = T0;
1100 /* Should be optimized */
1101 tlb_flush(env, 1);
1102 }
1103}
1104#endif
1105
1106/* 440 specific */
1107void do_440_dlmzb (void)
1108{
1109 target_ulong mask;
1110 int i;
1111
1112 i = 1;
1113 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1114 if ((T0 & mask) == 0)
1115 goto done;
1116 i++;
1117 }
1118 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1119 if ((T1 & mask) == 0)
1120 break;
1121 i++;
1122 }
1123 done:
1124 T0 = i;
fdabc366
FB
1125}
1126
0487d6a8
JM
1127#if defined(TARGET_PPCSPE)
1128/* SPE extension helpers */
1129/* Use a table to make this quicker */
1130static uint8_t hbrev[16] = {
1131 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1132 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1133};
1134
1135static inline uint8_t byte_reverse (uint8_t val)
1136{
1137 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1138}
1139
1140static inline uint32_t word_reverse (uint32_t val)
1141{
1142 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1143 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1144}
1145
1146#define MASKBITS 16 // Random value - to be fixed
1147void do_brinc (void)
1148{
1149 uint32_t a, b, d, mask;
1150
1151 mask = (uint32_t)(-1UL) >> MASKBITS;
1152 b = T1_64 & mask;
1153 a = T0_64 & mask;
1154 d = word_reverse(1 + word_reverse(a | ~mask));
1155 T0_64 = (T0_64 & ~mask) | (d & mask);
1156}
1157
1158#define DO_SPE_OP2(name) \
1159void do_ev##name (void) \
1160{ \
1161 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1162 (uint64_t)_do_e##name(T0_64, T1_64); \
1163}
1164
1165#define DO_SPE_OP1(name) \
1166void do_ev##name (void) \
1167{ \
1168 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1169 (uint64_t)_do_e##name(T0_64); \
1170}
1171
1172/* Fixed-point vector arithmetic */
1173static inline uint32_t _do_eabs (uint32_t val)
1174{
1175 if (val != 0x80000000)
1176 val &= ~0x80000000;
1177
1178 return val;
1179}
1180
1181static inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1182{
1183 return op1 + op2;
1184}
1185
1186static inline int _do_ecntlsw (uint32_t val)
1187{
1188 if (val & 0x80000000)
1189 return _do_cntlzw(~val);
1190 else
1191 return _do_cntlzw(val);
1192}
1193
1194static inline int _do_ecntlzw (uint32_t val)
1195{
1196 return _do_cntlzw(val);
1197}
1198
1199static inline uint32_t _do_eneg (uint32_t val)
1200{
1201 if (val != 0x80000000)
1202 val ^= 0x80000000;
1203
1204 return val;
1205}
1206
1207static inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1208{
1209 return rotl32(op1, op2);
1210}
1211
1212static inline uint32_t _do_erndw (uint32_t val)
1213{
1214 return (val + 0x000080000000) & 0xFFFF0000;
1215}
1216
1217static inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1218{
1219 /* No error here: 6 bits are used */
1220 return op1 << (op2 & 0x3F);
1221}
1222
1223static inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1224{
1225 /* No error here: 6 bits are used */
1226 return op1 >> (op2 & 0x3F);
1227}
1228
1229static inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1230{
1231 /* No error here: 6 bits are used */
1232 return op1 >> (op2 & 0x3F);
1233}
1234
1235static inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1236{
1237 return op2 - op1;
1238}
1239
1240/* evabs */
1241DO_SPE_OP1(abs);
1242/* evaddw */
1243DO_SPE_OP2(addw);
1244/* evcntlsw */
1245DO_SPE_OP1(cntlsw);
1246/* evcntlzw */
1247DO_SPE_OP1(cntlzw);
1248/* evneg */
1249DO_SPE_OP1(neg);
1250/* evrlw */
1251DO_SPE_OP2(rlw);
1252/* evrnd */
1253DO_SPE_OP1(rndw);
1254/* evslw */
1255DO_SPE_OP2(slw);
1256/* evsrws */
1257DO_SPE_OP2(srws);
1258/* evsrwu */
1259DO_SPE_OP2(srwu);
1260/* evsubfw */
1261DO_SPE_OP2(subfw);
1262
1263/* evsel is a little bit more complicated... */
1264static inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
1265{
1266 if (n)
1267 return op1;
1268 else
1269 return op2;
1270}
1271
1272void do_evsel (void)
1273{
1274 T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1275 (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1276}
1277
1278/* Fixed-point vector comparisons */
1279#define DO_SPE_CMP(name) \
1280void do_ev##name (void) \
1281{ \
1282 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1283 T1_64 >> 32) << 32, \
1284 _do_e##name(T0_64, T1_64)); \
1285}
1286
1287static inline uint32_t _do_evcmp_merge (int t0, int t1)
1288{
1289 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1290}
1291static inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
1292{
1293 return op1 == op2 ? 1 : 0;
1294}
1295
1296static inline int _do_ecmpgts (int32_t op1, int32_t op2)
1297{
1298 return op1 > op2 ? 1 : 0;
1299}
1300
1301static inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
1302{
1303 return op1 > op2 ? 1 : 0;
1304}
1305
1306static inline int _do_ecmplts (int32_t op1, int32_t op2)
1307{
1308 return op1 < op2 ? 1 : 0;
1309}
1310
1311static inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
1312{
1313 return op1 < op2 ? 1 : 0;
1314}
1315
1316/* evcmpeq */
1317DO_SPE_CMP(cmpeq);
1318/* evcmpgts */
1319DO_SPE_CMP(cmpgts);
1320/* evcmpgtu */
1321DO_SPE_CMP(cmpgtu);
1322/* evcmplts */
1323DO_SPE_CMP(cmplts);
1324/* evcmpltu */
1325DO_SPE_CMP(cmpltu);
1326
1327/* Single precision floating-point conversions from/to integer */
1328static inline uint32_t _do_efscfsi (int32_t val)
1329{
1330 union {
1331 uint32_t u;
1332 float32 f;
1333 } u;
1334
1335 u.f = int32_to_float32(val, &env->spe_status);
1336
1337 return u.u;
1338}
1339
1340static inline uint32_t _do_efscfui (uint32_t val)
1341{
1342 union {
1343 uint32_t u;
1344 float32 f;
1345 } u;
1346
1347 u.f = uint32_to_float32(val, &env->spe_status);
1348
1349 return u.u;
1350}
1351
1352static inline int32_t _do_efsctsi (uint32_t val)
1353{
1354 union {
1355 int32_t u;
1356 float32 f;
1357 } u;
1358
1359 u.u = val;
1360 /* NaN are not treated the same way IEEE 754 does */
1361 if (unlikely(isnan(u.f)))
1362 return 0;
1363
1364 return float32_to_int32(u.f, &env->spe_status);
1365}
1366
1367static inline uint32_t _do_efsctui (uint32_t val)
1368{
1369 union {
1370 int32_t u;
1371 float32 f;
1372 } u;
1373
1374 u.u = val;
1375 /* NaN are not treated the same way IEEE 754 does */
1376 if (unlikely(isnan(u.f)))
1377 return 0;
1378
1379 return float32_to_uint32(u.f, &env->spe_status);
1380}
1381
1382static inline int32_t _do_efsctsiz (uint32_t val)
1383{
1384 union {
1385 int32_t u;
1386 float32 f;
1387 } u;
1388
1389 u.u = val;
1390 /* NaN are not treated the same way IEEE 754 does */
1391 if (unlikely(isnan(u.f)))
1392 return 0;
1393
1394 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1395}
1396
1397static inline uint32_t _do_efsctuiz (uint32_t val)
1398{
1399 union {
1400 int32_t u;
1401 float32 f;
1402 } u;
1403
1404 u.u = val;
1405 /* NaN are not treated the same way IEEE 754 does */
1406 if (unlikely(isnan(u.f)))
1407 return 0;
1408
1409 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1410}
1411
1412void do_efscfsi (void)
1413{
1414 T0_64 = _do_efscfsi(T0_64);
1415}
1416
1417void do_efscfui (void)
1418{
1419 T0_64 = _do_efscfui(T0_64);
1420}
1421
1422void do_efsctsi (void)
1423{
1424 T0_64 = _do_efsctsi(T0_64);
1425}
1426
1427void do_efsctui (void)
1428{
1429 T0_64 = _do_efsctui(T0_64);
1430}
1431
1432void do_efsctsiz (void)
1433{
1434 T0_64 = _do_efsctsiz(T0_64);
1435}
1436
1437void do_efsctuiz (void)
1438{
1439 T0_64 = _do_efsctuiz(T0_64);
1440}
1441
1442/* Single precision floating-point conversion to/from fractional */
1443static inline uint32_t _do_efscfsf (uint32_t val)
1444{
1445 union {
1446 uint32_t u;
1447 float32 f;
1448 } u;
1449 float32 tmp;
1450
1451 u.f = int32_to_float32(val, &env->spe_status);
1452 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1453 u.f = float32_div(u.f, tmp, &env->spe_status);
1454
1455 return u.u;
1456}
1457
1458static inline uint32_t _do_efscfuf (uint32_t val)
1459{
1460 union {
1461 uint32_t u;
1462 float32 f;
1463 } u;
1464 float32 tmp;
1465
1466 u.f = uint32_to_float32(val, &env->spe_status);
1467 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1468 u.f = float32_div(u.f, tmp, &env->spe_status);
1469
1470 return u.u;
1471}
1472
1473static inline int32_t _do_efsctsf (uint32_t val)
1474{
1475 union {
1476 int32_t u;
1477 float32 f;
1478 } u;
1479 float32 tmp;
1480
1481 u.u = val;
1482 /* NaN are not treated the same way IEEE 754 does */
1483 if (unlikely(isnan(u.f)))
1484 return 0;
1485 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1486 u.f = float32_mul(u.f, tmp, &env->spe_status);
1487
1488 return float32_to_int32(u.f, &env->spe_status);
1489}
1490
1491static inline uint32_t _do_efsctuf (uint32_t val)
1492{
1493 union {
1494 int32_t u;
1495 float32 f;
1496 } u;
1497 float32 tmp;
1498
1499 u.u = val;
1500 /* NaN are not treated the same way IEEE 754 does */
1501 if (unlikely(isnan(u.f)))
1502 return 0;
1503 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1504 u.f = float32_mul(u.f, tmp, &env->spe_status);
1505
1506 return float32_to_uint32(u.f, &env->spe_status);
1507}
1508
1509static inline int32_t _do_efsctsfz (uint32_t val)
1510{
1511 union {
1512 int32_t u;
1513 float32 f;
1514 } u;
1515 float32 tmp;
1516
1517 u.u = val;
1518 /* NaN are not treated the same way IEEE 754 does */
1519 if (unlikely(isnan(u.f)))
1520 return 0;
1521 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1522 u.f = float32_mul(u.f, tmp, &env->spe_status);
1523
1524 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1525}
1526
1527static inline uint32_t _do_efsctufz (uint32_t val)
1528{
1529 union {
1530 int32_t u;
1531 float32 f;
1532 } u;
1533 float32 tmp;
1534
1535 u.u = val;
1536 /* NaN are not treated the same way IEEE 754 does */
1537 if (unlikely(isnan(u.f)))
1538 return 0;
1539 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1540 u.f = float32_mul(u.f, tmp, &env->spe_status);
1541
1542 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1543}
1544
1545void do_efscfsf (void)
1546{
1547 T0_64 = _do_efscfsf(T0_64);
1548}
1549
1550void do_efscfuf (void)
1551{
1552 T0_64 = _do_efscfuf(T0_64);
1553}
1554
1555void do_efsctsf (void)
1556{
1557 T0_64 = _do_efsctsf(T0_64);
1558}
1559
1560void do_efsctuf (void)
1561{
1562 T0_64 = _do_efsctuf(T0_64);
1563}
1564
1565void do_efsctsfz (void)
1566{
1567 T0_64 = _do_efsctsfz(T0_64);
1568}
1569
1570void do_efsctufz (void)
1571{
1572 T0_64 = _do_efsctufz(T0_64);
1573}
1574
1575/* Double precision floating point helpers */
1576static inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
1577{
1578 /* XXX: TODO: test special values (NaN, infinites, ...) */
1579 return _do_efdtstlt(op1, op2);
1580}
1581
1582static inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
1583{
1584 /* XXX: TODO: test special values (NaN, infinites, ...) */
1585 return _do_efdtstgt(op1, op2);
1586}
1587
1588static inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
1589{
1590 /* XXX: TODO: test special values (NaN, infinites, ...) */
1591 return _do_efdtsteq(op1, op2);
1592}
1593
1594void do_efdcmplt (void)
1595{
1596 T0 = _do_efdcmplt(T0_64, T1_64);
1597}
1598
1599void do_efdcmpgt (void)
1600{
1601 T0 = _do_efdcmpgt(T0_64, T1_64);
1602}
1603
1604void do_efdcmpeq (void)
1605{
1606 T0 = _do_efdcmpeq(T0_64, T1_64);
1607}
1608
1609/* Double precision floating-point conversion to/from integer */
1610static inline uint64_t _do_efdcfsi (int64_t val)
1611{
1612 union {
1613 uint64_t u;
1614 float64 f;
1615 } u;
1616
1617 u.f = int64_to_float64(val, &env->spe_status);
1618
1619 return u.u;
1620}
1621
1622static inline uint64_t _do_efdcfui (uint64_t val)
1623{
1624 union {
1625 uint64_t u;
1626 float64 f;
1627 } u;
1628
1629 u.f = uint64_to_float64(val, &env->spe_status);
1630
1631 return u.u;
1632}
1633
1634static inline int64_t _do_efdctsi (uint64_t val)
1635{
1636 union {
1637 int64_t u;
1638 float64 f;
1639 } u;
1640
1641 u.u = val;
1642 /* NaN are not treated the same way IEEE 754 does */
1643 if (unlikely(isnan(u.f)))
1644 return 0;
1645
1646 return float64_to_int64(u.f, &env->spe_status);
1647}
1648
1649static inline uint64_t _do_efdctui (uint64_t val)
1650{
1651 union {
1652 int64_t u;
1653 float64 f;
1654 } u;
1655
1656 u.u = val;
1657 /* NaN are not treated the same way IEEE 754 does */
1658 if (unlikely(isnan(u.f)))
1659 return 0;
1660
1661 return float64_to_uint64(u.f, &env->spe_status);
1662}
1663
1664static inline int64_t _do_efdctsiz (uint64_t val)
1665{
1666 union {
1667 int64_t u;
1668 float64 f;
1669 } u;
1670
1671 u.u = val;
1672 /* NaN are not treated the same way IEEE 754 does */
1673 if (unlikely(isnan(u.f)))
1674 return 0;
1675
1676 return float64_to_int64_round_to_zero(u.f, &env->spe_status);
1677}
1678
1679static inline uint64_t _do_efdctuiz (uint64_t val)
1680{
1681 union {
1682 int64_t u;
1683 float64 f;
1684 } u;
1685
1686 u.u = val;
1687 /* NaN are not treated the same way IEEE 754 does */
1688 if (unlikely(isnan(u.f)))
1689 return 0;
1690
1691 return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
1692}
1693
1694void do_efdcfsi (void)
1695{
1696 T0_64 = _do_efdcfsi(T0_64);
1697}
1698
1699void do_efdcfui (void)
1700{
1701 T0_64 = _do_efdcfui(T0_64);
1702}
1703
1704void do_efdctsi (void)
1705{
1706 T0_64 = _do_efdctsi(T0_64);
1707}
1708
1709void do_efdctui (void)
1710{
1711 T0_64 = _do_efdctui(T0_64);
1712}
1713
1714void do_efdctsiz (void)
1715{
1716 T0_64 = _do_efdctsiz(T0_64);
1717}
1718
1719void do_efdctuiz (void)
1720{
1721 T0_64 = _do_efdctuiz(T0_64);
1722}
1723
1724/* Double precision floating-point conversion to/from fractional */
1725static inline uint64_t _do_efdcfsf (int64_t val)
1726{
1727 union {
1728 uint64_t u;
1729 float64 f;
1730 } u;
1731 float64 tmp;
1732
1733 u.f = int32_to_float64(val, &env->spe_status);
1734 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1735 u.f = float64_div(u.f, tmp, &env->spe_status);
1736
1737 return u.u;
1738}
1739
1740static inline uint64_t _do_efdcfuf (uint64_t val)
1741{
1742 union {
1743 uint64_t u;
1744 float64 f;
1745 } u;
1746 float64 tmp;
1747
1748 u.f = uint32_to_float64(val, &env->spe_status);
1749 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
1750 u.f = float64_div(u.f, tmp, &env->spe_status);
1751
1752 return u.u;
1753}
1754
1755static inline int64_t _do_efdctsf (uint64_t val)
1756{
1757 union {
1758 int64_t u;
1759 float64 f;
1760 } u;
1761 float64 tmp;
1762
1763 u.u = val;
1764 /* NaN are not treated the same way IEEE 754 does */
1765 if (unlikely(isnan(u.f)))
1766 return 0;
1767 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1768 u.f = float64_mul(u.f, tmp, &env->spe_status);
1769
1770 return float64_to_int32(u.f, &env->spe_status);
1771}
1772
1773static inline uint64_t _do_efdctuf (uint64_t val)
1774{
1775 union {
1776 int64_t u;
1777 float64 f;
1778 } u;
1779 float64 tmp;
1780
1781 u.u = val;
1782 /* NaN are not treated the same way IEEE 754 does */
1783 if (unlikely(isnan(u.f)))
1784 return 0;
1785 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1786 u.f = float64_mul(u.f, tmp, &env->spe_status);
1787
1788 return float64_to_uint32(u.f, &env->spe_status);
1789}
1790
1791static inline int64_t _do_efdctsfz (uint64_t val)
1792{
1793 union {
1794 int64_t u;
1795 float64 f;
1796 } u;
1797 float64 tmp;
1798
1799 u.u = val;
1800 /* NaN are not treated the same way IEEE 754 does */
1801 if (unlikely(isnan(u.f)))
1802 return 0;
1803 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1804 u.f = float64_mul(u.f, tmp, &env->spe_status);
1805
1806 return float64_to_int32_round_to_zero(u.f, &env->spe_status);
1807}
1808
1809static inline uint64_t _do_efdctufz (uint64_t val)
1810{
1811 union {
1812 int64_t u;
1813 float64 f;
1814 } u;
1815 float64 tmp;
1816
1817 u.u = val;
1818 /* NaN are not treated the same way IEEE 754 does */
1819 if (unlikely(isnan(u.f)))
1820 return 0;
1821 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
1822 u.f = float64_mul(u.f, tmp, &env->spe_status);
1823
1824 return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
1825}
1826
1827void do_efdcfsf (void)
1828{
1829 T0_64 = _do_efdcfsf(T0_64);
1830}
1831
1832void do_efdcfuf (void)
1833{
1834 T0_64 = _do_efdcfuf(T0_64);
1835}
1836
1837void do_efdctsf (void)
1838{
1839 T0_64 = _do_efdctsf(T0_64);
1840}
1841
1842void do_efdctuf (void)
1843{
1844 T0_64 = _do_efdctuf(T0_64);
1845}
1846
1847void do_efdctsfz (void)
1848{
1849 T0_64 = _do_efdctsfz(T0_64);
1850}
1851
1852void do_efdctufz (void)
1853{
1854 T0_64 = _do_efdctufz(T0_64);
1855}
1856
1857/* Floating point conversion between single and double precision */
1858static inline uint32_t _do_efscfd (uint64_t val)
1859{
1860 union {
1861 uint64_t u;
1862 float64 f;
1863 } u1;
1864 union {
1865 uint32_t u;
1866 float32 f;
1867 } u2;
1868
1869 u1.u = val;
1870 u2.f = float64_to_float32(u1.f, &env->spe_status);
1871
1872 return u2.u;
1873}
1874
1875static inline uint64_t _do_efdcfs (uint32_t val)
1876{
1877 union {
1878 uint64_t u;
1879 float64 f;
1880 } u2;
1881 union {
1882 uint32_t u;
1883 float32 f;
1884 } u1;
1885
1886 u1.u = val;
1887 u2.f = float32_to_float64(u1.f, &env->spe_status);
1888
1889 return u2.u;
1890}
1891
1892void do_efscfd (void)
1893{
1894 T0_64 = _do_efscfd(T0_64);
1895}
1896
1897void do_efdcfs (void)
1898{
1899 T0_64 = _do_efdcfs(T0_64);
1900}
1901
1902/* Single precision fixed-point vector arithmetic */
1903/* evfsabs */
1904DO_SPE_OP1(fsabs);
1905/* evfsnabs */
1906DO_SPE_OP1(fsnabs);
1907/* evfsneg */
1908DO_SPE_OP1(fsneg);
1909/* evfsadd */
1910DO_SPE_OP2(fsadd);
1911/* evfssub */
1912DO_SPE_OP2(fssub);
1913/* evfsmul */
1914DO_SPE_OP2(fsmul);
1915/* evfsdiv */
1916DO_SPE_OP2(fsdiv);
1917
1918/* Single-precision floating-point comparisons */
1919static inline int _do_efscmplt (uint32_t op1, uint32_t op2)
1920{
1921 /* XXX: TODO: test special values (NaN, infinites, ...) */
1922 return _do_efststlt(op1, op2);
1923}
1924
1925static inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
1926{
1927 /* XXX: TODO: test special values (NaN, infinites, ...) */
1928 return _do_efststgt(op1, op2);
1929}
1930
1931static inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
1932{
1933 /* XXX: TODO: test special values (NaN, infinites, ...) */
1934 return _do_efststeq(op1, op2);
1935}
1936
1937void do_efscmplt (void)
1938{
1939 T0 = _do_efscmplt(T0_64, T1_64);
1940}
1941
1942void do_efscmpgt (void)
1943{
1944 T0 = _do_efscmpgt(T0_64, T1_64);
1945}
1946
1947void do_efscmpeq (void)
1948{
1949 T0 = _do_efscmpeq(T0_64, T1_64);
1950}
1951
1952/* Single-precision floating-point vector comparisons */
1953/* evfscmplt */
1954DO_SPE_CMP(fscmplt);
1955/* evfscmpgt */
1956DO_SPE_CMP(fscmpgt);
1957/* evfscmpeq */
1958DO_SPE_CMP(fscmpeq);
1959/* evfststlt */
1960DO_SPE_CMP(fststlt);
1961/* evfststgt */
1962DO_SPE_CMP(fststgt);
1963/* evfststeq */
1964DO_SPE_CMP(fststeq);
1965
1966/* Single-precision floating-point vector conversions */
1967/* evfscfsi */
1968DO_SPE_OP1(fscfsi);
1969/* evfscfui */
1970DO_SPE_OP1(fscfui);
1971/* evfscfuf */
1972DO_SPE_OP1(fscfuf);
1973/* evfscfsf */
1974DO_SPE_OP1(fscfsf);
1975/* evfsctsi */
1976DO_SPE_OP1(fsctsi);
1977/* evfsctui */
1978DO_SPE_OP1(fsctui);
1979/* evfsctsiz */
1980DO_SPE_OP1(fsctsiz);
1981/* evfsctuiz */
1982DO_SPE_OP1(fsctuiz);
1983/* evfsctsf */
1984DO_SPE_OP1(fsctsf);
1985/* evfsctuf */
1986DO_SPE_OP1(fsctuf);
1987#endif /* defined(TARGET_PPCSPE) */
1988
fdabc366
FB
1989/*****************************************************************************/
1990/* Softmmu support */
1991#if !defined (CONFIG_USER_ONLY)
1992
1993#define MMUSUFFIX _mmu
1994#define GETPC() (__builtin_return_address(0))
1995
1996#define SHIFT 0
1997#include "softmmu_template.h"
1998
1999#define SHIFT 1
2000#include "softmmu_template.h"
2001
2002#define SHIFT 2
2003#include "softmmu_template.h"
2004
2005#define SHIFT 3
2006#include "softmmu_template.h"
2007
2008/* try to fill the TLB and return an exception if error. If retaddr is
2009 NULL, it means that the function was called in C code (i.e. not
2010 from generated code or from helper.c) */
2011/* XXX: fix it to restore all registers */
2012void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
2013{
2014 TranslationBlock *tb;
2015 CPUState *saved_env;
2016 target_phys_addr_t pc;
2017 int ret;
2018
2019 /* XXX: hack to restore env in all cases, even if not called from
2020 generated code */
2021 saved_env = env;
2022 env = cpu_single_env;
2023 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
76a66253 2024 if (unlikely(ret != 0)) {
fdabc366
FB
2025 if (likely(retaddr)) {
2026 /* now we have a real cpu fault */
2027 pc = (target_phys_addr_t)retaddr;
2028 tb = tb_find_pc(pc);
2029 if (likely(tb)) {
2030 /* the PC is inside the translated code. It means that we have
2031 a virtual CPU fault */
2032 cpu_restore_state(tb, env, pc, NULL);
76a66253 2033 }
fdabc366
FB
2034 }
2035 do_raise_exception_err(env->exception_index, env->error_code);
2036 }
2037 env = saved_env;
9a64fbe4
FB
2038}
2039
76a66253
JM
2040/* TLB invalidation helpers */
2041void do_tlbia (void)
2042{
2043 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2044 ppc6xx_tlb_invalidate_all(env);
2045 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2046 /* XXX: TODO */
2047#if 0
2048 ppcbooke_tlb_invalidate_all(env);
2049#endif
2050 } else {
2051 tlb_flush(env, 1);
2052 }
2053}
2054
2055void do_tlbie (void)
2056{
d9bce9d9 2057 T0 = (uint32_t)T0;
76a66253
JM
2058#if !defined(FLUSH_ALL_TLBS)
2059 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2060 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2061 if (env->id_tlbs == 1)
2062 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2063 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2064 /* XXX: TODO */
2065#if 0
2066 ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2067 env->spr[SPR_BOOKE_PID]);
2068#endif
2069 } else {
2070 /* tlbie invalidate TLBs for all segments */
2071 T0 &= TARGET_PAGE_MASK;
2072 T0 &= ~((target_ulong)-1 << 28);
2073 /* XXX: this case should be optimized,
2074 * giving a mask to tlb_flush_page
2075 */
2076 tlb_flush_page(env, T0 | (0x0 << 28));
2077 tlb_flush_page(env, T0 | (0x1 << 28));
2078 tlb_flush_page(env, T0 | (0x2 << 28));
2079 tlb_flush_page(env, T0 | (0x3 << 28));
2080 tlb_flush_page(env, T0 | (0x4 << 28));
2081 tlb_flush_page(env, T0 | (0x5 << 28));
2082 tlb_flush_page(env, T0 | (0x6 << 28));
2083 tlb_flush_page(env, T0 | (0x7 << 28));
2084 tlb_flush_page(env, T0 | (0x8 << 28));
2085 tlb_flush_page(env, T0 | (0x9 << 28));
2086 tlb_flush_page(env, T0 | (0xA << 28));
2087 tlb_flush_page(env, T0 | (0xB << 28));
2088 tlb_flush_page(env, T0 | (0xC << 28));
2089 tlb_flush_page(env, T0 | (0xD << 28));
2090 tlb_flush_page(env, T0 | (0xE << 28));
2091 tlb_flush_page(env, T0 | (0xF << 28));
2092 }
2093#else
2094 do_tlbia();
2095#endif
2096}
2097
d9bce9d9
JM
2098#if defined(TARGET_PPC64)
2099void do_tlbie_64 (void)
2100{
2101 T0 = (uint64_t)T0;
2102#if !defined(FLUSH_ALL_TLBS)
2103 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
2104 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0);
2105 if (env->id_tlbs == 1)
2106 ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1);
2107 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
2108 /* XXX: TODO */
2109#if 0
2110 ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK,
2111 env->spr[SPR_BOOKE_PID]);
2112#endif
2113 } else {
2114 /* tlbie invalidate TLBs for all segments
2115 * As we have 2^36 segments, invalidate all qemu TLBs
2116 */
2117#if 0
2118 T0 &= TARGET_PAGE_MASK;
2119 T0 &= ~((target_ulong)-1 << 28);
2120 /* XXX: this case should be optimized,
2121 * giving a mask to tlb_flush_page
2122 */
2123 tlb_flush_page(env, T0 | (0x0 << 28));
2124 tlb_flush_page(env, T0 | (0x1 << 28));
2125 tlb_flush_page(env, T0 | (0x2 << 28));
2126 tlb_flush_page(env, T0 | (0x3 << 28));
2127 tlb_flush_page(env, T0 | (0x4 << 28));
2128 tlb_flush_page(env, T0 | (0x5 << 28));
2129 tlb_flush_page(env, T0 | (0x6 << 28));
2130 tlb_flush_page(env, T0 | (0x7 << 28));
2131 tlb_flush_page(env, T0 | (0x8 << 28));
2132 tlb_flush_page(env, T0 | (0x9 << 28));
2133 tlb_flush_page(env, T0 | (0xA << 28));
2134 tlb_flush_page(env, T0 | (0xB << 28));
2135 tlb_flush_page(env, T0 | (0xC << 28));
2136 tlb_flush_page(env, T0 | (0xD << 28));
2137 tlb_flush_page(env, T0 | (0xE << 28));
2138 tlb_flush_page(env, T0 | (0xF << 28));
2139#else
2140 tlb_flush(env, 1);
2141#endif
2142 }
2143#else
2144 do_tlbia();
2145#endif
2146}
2147#endif
2148
2149#if defined(TARGET_PPC64)
2150void do_slbia (void)
2151{
2152 /* XXX: TODO */
2153 tlb_flush(env, 1);
2154}
2155
2156void do_slbie (void)
2157{
2158 /* XXX: TODO */
2159 tlb_flush(env, 1);
2160}
2161#endif
2162
76a66253
JM
2163/* Software driven TLBs management */
2164/* PowerPC 602/603 software TLB load instructions helpers */
2165void do_load_6xx_tlb (int is_code)
2166{
2167 target_ulong RPN, CMP, EPN;
2168 int way;
d9bce9d9 2169
76a66253
JM
2170 RPN = env->spr[SPR_RPA];
2171 if (is_code) {
2172 CMP = env->spr[SPR_ICMP];
2173 EPN = env->spr[SPR_IMISS];
2174 } else {
2175 CMP = env->spr[SPR_DCMP];
2176 EPN = env->spr[SPR_DMISS];
2177 }
2178 way = (env->spr[SPR_SRR1] >> 17) & 1;
2179#if defined (DEBUG_SOFTWARE_TLB)
2180 if (loglevel != 0) {
2181 fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2182 __func__, (unsigned long)T0, (unsigned long)EPN,
2183 (unsigned long)CMP, (unsigned long)RPN, way);
2184 }
2185#endif
2186 /* Store this TLB */
d9bce9d9
JM
2187 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2188 way, is_code, CMP, RPN);
76a66253
JM
2189}
2190
2191/* Helpers for 4xx TLB management */
2192void do_4xx_tlbia (void)
2193{
2194#if 0
2195 ppc_tlb_t *tlb;
2196 target_ulong page, end;
2197 int i;
2198
2199 for (i = 0; i < 64; i++) {
2200 tlb = &env->tlb[i];
2201 if (tlb->prot & PAGE_VALID) {
2202 end = tlb->EPN + tlb->size;
2203 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2204 tlb_flush_page(env, page);
2205 tlb->prot &= ~PAGE_VALID;
2206 }
2207 }
2208#endif
2209}
2210
2211void do_4xx_tlbre_lo (void)
2212{
2213#if 0
2214 ppc_tlb_t *tlb;
2215
2216 T0 &= 0x3F;
2217 tlb = &env->tlb[T0];
2218 T0 = tlb->stor[0];
2219 env->spr[SPR_40x_PID] = tlb->pid;
2220#endif
2221}
2222
2223void do_4xx_tlbre_hi (void)
2224{
2225#if 0
2226 ppc_tlb_t *tlb;
2227
2228 T0 &= 0x3F;
2229 tlb = &env->tlb[T0];
2230 T0 = tlb->stor[1];
2231#endif
2232}
2233
2234static int tlb_4xx_search (target_ulong virtual)
2235{
2236#if 0
2237 ppc_tlb_t *tlb;
2238 target_ulong base, mask;
2239 int i, ret;
2240
2241 /* Default return value is no match */
2242 ret = -1;
2243 for (i = 0; i < 64; i++) {
2244 tlb = &env->tlb[i];
2245 /* Check TLB validity */
2246 if (!(tlb->prot & PAGE_VALID))
2247 continue;
2248 /* Check TLB PID vs current PID */
2249 if (tlb->pid != 0 && tlb->pid != env->spr[SPR_40x_PID])
2250 continue;
2251 /* Check TLB address vs virtual address */
2252 base = tlb->EPN;
2253 mask = ~(tlb->size - 1);
2254 if ((base & mask) != (virtual & mask))
2255 continue;
2256 ret = i;
2257 break;
2258 }
2259
2260 return ret;
2261#else
2262 return -1;
2263#endif
2264}
2265
2266void do_4xx_tlbsx (void)
2267{
2268 T0 = tlb_4xx_search(T0);
2269}
2270
2271void do_4xx_tlbsx_ (void)
2272{
2273 int tmp = xer_ov;
2274
2275 T0 = tlb_4xx_search(T0);
2276 if (T0 != -1)
2277 tmp |= 0x02;
2278 env->crf[0] = tmp;
2279}
2280
2281void do_4xx_tlbwe_lo (void)
2282{
2283#if 0
2284 ppc_tlb_t *tlb;
2285 target_ulong page, end;
2286
2287 T0 &= 0x3F;
2288 tlb = &env->tlb[T0];
2289 /* Invalidate previous TLB (if it's valid) */
2290 if (tlb->prot & PAGE_VALID) {
2291 end = tlb->EPN + tlb->size;
2292 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2293 tlb_flush_page(env, page);
2294 }
2295 tlb->size = 1024 << (2 * ((T1 >> 7) & 0x7));
2296 tlb->EPN = (T1 & 0xFFFFFC00) & ~(tlb->size - 1);
2297 if (T1 & 0x400)
2298 tlb->prot |= PAGE_VALID;
2299 else
2300 tlb->prot &= ~PAGE_VALID;
2301 tlb->pid = env->spr[SPR_BOOKE_PID]; /* PID */
2302 /* Invalidate new TLB (if valid) */
2303 if (tlb->prot & PAGE_VALID) {
2304 end = tlb->EPN + tlb->size;
2305 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2306 tlb_flush_page(env, page);
2307 }
2308#endif
2309}
2310
2311void do_4xx_tlbwe_hi (void)
2312{
2313#if 0
2314 ppc_tlb_t *tlb;
2315
2316 T0 &= 0x3F;
2317 tlb = &env->tlb[T0];
2318 tlb->RPN = T1 & 0xFFFFFC00;
2319 tlb->prot = PAGE_READ;
2320 if (T1 & 0x200)
2321 tlb->prot |= PAGE_EXEC;
2322 if (T1 & 0x100)
2323 tlb->prot |= PAGE_WRITE;
2324#endif
2325}
2326#endif /* !CONFIG_USER_ONLY */