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Commit | Line | Data |
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9a64fbe4 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation helpers for qemu. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
9a64fbe4 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
9a64fbe4 FB |
20 | #include "exec.h" |
21 | ||
0487d6a8 JM |
22 | #include "op_helper.h" |
23 | ||
9a64fbe4 | 24 | #define MEMSUFFIX _raw |
0487d6a8 | 25 | #include "op_helper.h" |
9a64fbe4 | 26 | #include "op_helper_mem.h" |
a541f297 | 27 | #if !defined(CONFIG_USER_ONLY) |
9a64fbe4 | 28 | #define MEMSUFFIX _user |
0487d6a8 | 29 | #include "op_helper.h" |
9a64fbe4 FB |
30 | #include "op_helper_mem.h" |
31 | #define MEMSUFFIX _kernel | |
0487d6a8 | 32 | #include "op_helper.h" |
9a64fbe4 FB |
33 | #include "op_helper_mem.h" |
34 | #endif | |
35 | ||
fdabc366 FB |
36 | //#define DEBUG_OP |
37 | //#define DEBUG_EXCEPTIONS | |
76a66253 | 38 | //#define DEBUG_SOFTWARE_TLB |
fdabc366 FB |
39 | //#define FLUSH_ALL_TLBS |
40 | ||
9a64fbe4 FB |
41 | /*****************************************************************************/ |
42 | /* Exceptions processing helpers */ | |
9a64fbe4 | 43 | |
9fddaa0c | 44 | void do_raise_exception_err (uint32_t exception, int error_code) |
9a64fbe4 | 45 | { |
9fddaa0c FB |
46 | #if 0 |
47 | printf("Raise exception %3x code : %d\n", exception, error_code); | |
48 | #endif | |
49 | switch (exception) { | |
e1833e1f JM |
50 | case POWERPC_EXCP_PROGRAM: |
51 | if (error_code == POWERPC_EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0) | |
76a66253 JM |
52 | return; |
53 | break; | |
9fddaa0c | 54 | default: |
76a66253 JM |
55 | break; |
56 | } | |
9fddaa0c FB |
57 | env->exception_index = exception; |
58 | env->error_code = error_code; | |
76a66253 JM |
59 | cpu_loop_exit(); |
60 | } | |
9fddaa0c FB |
61 | |
62 | void do_raise_exception (uint32_t exception) | |
63 | { | |
64 | do_raise_exception_err(exception, 0); | |
9a64fbe4 FB |
65 | } |
66 | ||
a496775f JM |
67 | void cpu_dump_EA (target_ulong EA); |
68 | void do_print_mem_EA (target_ulong EA) | |
69 | { | |
70 | cpu_dump_EA(EA); | |
71 | } | |
72 | ||
76a66253 JM |
73 | /*****************************************************************************/ |
74 | /* Registers load and stores */ | |
75 | void do_load_cr (void) | |
76 | { | |
77 | T0 = (env->crf[0] << 28) | | |
78 | (env->crf[1] << 24) | | |
79 | (env->crf[2] << 20) | | |
80 | (env->crf[3] << 16) | | |
81 | (env->crf[4] << 12) | | |
82 | (env->crf[5] << 8) | | |
83 | (env->crf[6] << 4) | | |
84 | (env->crf[7] << 0); | |
85 | } | |
86 | ||
87 | void do_store_cr (uint32_t mask) | |
88 | { | |
89 | int i, sh; | |
90 | ||
36081602 | 91 | for (i = 0, sh = 7; i < 8; i++, sh--) { |
76a66253 JM |
92 | if (mask & (1 << sh)) |
93 | env->crf[i] = (T0 >> (sh * 4)) & 0xFUL; | |
94 | } | |
95 | } | |
96 | ||
97 | void do_load_xer (void) | |
98 | { | |
99 | T0 = (xer_so << XER_SO) | | |
100 | (xer_ov << XER_OV) | | |
101 | (xer_ca << XER_CA) | | |
102 | (xer_bc << XER_BC) | | |
103 | (xer_cmp << XER_CMP); | |
104 | } | |
105 | ||
106 | void do_store_xer (void) | |
107 | { | |
108 | xer_so = (T0 >> XER_SO) & 0x01; | |
109 | xer_ov = (T0 >> XER_OV) & 0x01; | |
110 | xer_ca = (T0 >> XER_CA) & 0x01; | |
111 | xer_cmp = (T0 >> XER_CMP) & 0xFF; | |
d9bce9d9 | 112 | xer_bc = (T0 >> XER_BC) & 0x7F; |
76a66253 JM |
113 | } |
114 | ||
c80f84e3 JM |
115 | #if defined(TARGET_PPC64) |
116 | void do_store_pri (int prio) | |
117 | { | |
118 | env->spr[SPR_PPR] &= ~0x001C000000000000ULL; | |
119 | env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50; | |
120 | } | |
121 | #endif | |
122 | ||
76a66253 JM |
123 | void do_load_fpscr (void) |
124 | { | |
125 | /* The 32 MSB of the target fpr are undefined. | |
126 | * They'll be zero... | |
127 | */ | |
128 | union { | |
129 | float64 d; | |
130 | struct { | |
131 | uint32_t u[2]; | |
132 | } s; | |
133 | } u; | |
134 | int i; | |
135 | ||
d9bce9d9 | 136 | #if defined(WORDS_BIGENDIAN) |
76a66253 JM |
137 | #define WORD0 0 |
138 | #define WORD1 1 | |
139 | #else | |
140 | #define WORD0 1 | |
141 | #define WORD1 0 | |
142 | #endif | |
143 | u.s.u[WORD0] = 0; | |
144 | u.s.u[WORD1] = 0; | |
145 | for (i = 0; i < 8; i++) | |
146 | u.s.u[WORD1] |= env->fpscr[i] << (4 * i); | |
147 | FT0 = u.d; | |
148 | } | |
149 | ||
150 | void do_store_fpscr (uint32_t mask) | |
151 | { | |
152 | /* | |
153 | * We use only the 32 LSB of the incoming fpr | |
154 | */ | |
155 | union { | |
156 | double d; | |
157 | struct { | |
158 | uint32_t u[2]; | |
159 | } s; | |
160 | } u; | |
161 | int i, rnd_type; | |
162 | ||
163 | u.d = FT0; | |
164 | if (mask & 0x80) | |
165 | env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9); | |
166 | for (i = 1; i < 7; i++) { | |
167 | if (mask & (1 << (7 - i))) | |
168 | env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF; | |
169 | } | |
170 | /* TODO: update FEX & VX */ | |
171 | /* Set rounding mode */ | |
172 | switch (env->fpscr[0] & 0x3) { | |
173 | case 0: | |
174 | /* Best approximation (round to nearest) */ | |
175 | rnd_type = float_round_nearest_even; | |
176 | break; | |
177 | case 1: | |
178 | /* Smaller magnitude (round toward zero) */ | |
179 | rnd_type = float_round_to_zero; | |
180 | break; | |
181 | case 2: | |
182 | /* Round toward +infinite */ | |
183 | rnd_type = float_round_up; | |
184 | break; | |
185 | default: | |
186 | case 3: | |
187 | /* Round toward -infinite */ | |
188 | rnd_type = float_round_down; | |
189 | break; | |
190 | } | |
191 | set_float_rounding_mode(rnd_type, &env->fp_status); | |
192 | } | |
193 | ||
a496775f JM |
194 | target_ulong ppc_load_dump_spr (int sprn) |
195 | { | |
6b80055d | 196 | if (loglevel != 0) { |
a496775f JM |
197 | fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n", |
198 | sprn, sprn, env->spr[sprn]); | |
199 | } | |
200 | ||
201 | return env->spr[sprn]; | |
202 | } | |
203 | ||
204 | void ppc_store_dump_spr (int sprn, target_ulong val) | |
205 | { | |
6b80055d | 206 | if (loglevel != 0) { |
a496775f JM |
207 | fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n", |
208 | sprn, sprn, env->spr[sprn], val); | |
209 | } | |
210 | env->spr[sprn] = val; | |
211 | } | |
212 | ||
9a64fbe4 | 213 | /*****************************************************************************/ |
fdabc366 | 214 | /* Fixed point operations helpers */ |
d9bce9d9 JM |
215 | #if defined(TARGET_PPC64) |
216 | static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b) | |
fdabc366 | 217 | { |
d9bce9d9 JM |
218 | *plow += a; |
219 | /* carry test */ | |
220 | if (*plow < a) | |
221 | (*phigh)++; | |
222 | *phigh += b; | |
fdabc366 FB |
223 | } |
224 | ||
d9bce9d9 | 225 | static void neg128 (uint64_t *plow, uint64_t *phigh) |
fdabc366 | 226 | { |
36081602 JM |
227 | *plow = ~*plow; |
228 | *phigh = ~*phigh; | |
d9bce9d9 JM |
229 | add128(plow, phigh, 1, 0); |
230 | } | |
231 | ||
232 | static void mul64 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b) | |
233 | { | |
234 | uint32_t a0, a1, b0, b1; | |
235 | uint64_t v; | |
236 | ||
237 | a0 = a; | |
238 | a1 = a >> 32; | |
239 | ||
240 | b0 = b; | |
241 | b1 = b >> 32; | |
3b46e624 | 242 | |
d9bce9d9 JM |
243 | v = (uint64_t)a0 * (uint64_t)b0; |
244 | *plow = v; | |
245 | *phigh = 0; | |
246 | ||
247 | v = (uint64_t)a0 * (uint64_t)b1; | |
248 | add128(plow, phigh, v << 32, v >> 32); | |
249 | ||
250 | v = (uint64_t)a1 * (uint64_t)b0; | |
251 | add128(plow, phigh, v << 32, v >> 32); | |
252 | ||
253 | v = (uint64_t)a1 * (uint64_t)b1; | |
254 | *phigh += v; | |
255 | #if defined(DEBUG_MULDIV) | |
256 | printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n", | |
257 | a, b, *phigh, *plow); | |
258 | #endif | |
259 | } | |
260 | ||
261 | void do_mul64 (uint64_t *plow, uint64_t *phigh) | |
262 | { | |
263 | mul64(plow, phigh, T0, T1); | |
264 | } | |
265 | ||
0487d6a8 | 266 | static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b) |
d9bce9d9 JM |
267 | { |
268 | int sa, sb; | |
36081602 | 269 | |
d9bce9d9 JM |
270 | sa = (a < 0); |
271 | if (sa) | |
272 | a = -a; | |
273 | sb = (b < 0); | |
274 | if (sb) | |
275 | b = -b; | |
276 | mul64(plow, phigh, a, b); | |
277 | if (sa ^ sb) { | |
278 | neg128(plow, phigh); | |
fdabc366 FB |
279 | } |
280 | } | |
281 | ||
d9bce9d9 JM |
282 | void do_imul64 (uint64_t *plow, uint64_t *phigh) |
283 | { | |
284 | imul64(plow, phigh, T0, T1); | |
285 | } | |
286 | #endif | |
287 | ||
fdabc366 FB |
288 | void do_adde (void) |
289 | { | |
290 | T2 = T0; | |
291 | T0 += T1 + xer_ca; | |
d9bce9d9 JM |
292 | if (likely(!((uint32_t)T0 < (uint32_t)T2 || |
293 | (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) { | |
fdabc366 FB |
294 | xer_ca = 0; |
295 | } else { | |
296 | xer_ca = 1; | |
297 | } | |
298 | } | |
299 | ||
d9bce9d9 JM |
300 | #if defined(TARGET_PPC64) |
301 | void do_adde_64 (void) | |
fdabc366 FB |
302 | { |
303 | T2 = T0; | |
304 | T0 += T1 + xer_ca; | |
d9bce9d9 JM |
305 | if (likely(!((uint64_t)T0 < (uint64_t)T2 || |
306 | (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) { | |
fdabc366 FB |
307 | xer_ca = 0; |
308 | } else { | |
309 | xer_ca = 1; | |
310 | } | |
fdabc366 | 311 | } |
d9bce9d9 | 312 | #endif |
fdabc366 FB |
313 | |
314 | void do_addmeo (void) | |
315 | { | |
316 | T1 = T0; | |
317 | T0 += xer_ca + (-1); | |
d9bce9d9 JM |
318 | if (likely(!((uint32_t)T1 & |
319 | ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) { | |
fdabc366 FB |
320 | xer_ov = 0; |
321 | } else { | |
fdabc366 | 322 | xer_ov = 1; |
966439a6 | 323 | xer_so = 1; |
fdabc366 FB |
324 | } |
325 | if (likely(T1 != 0)) | |
326 | xer_ca = 1; | |
327 | } | |
328 | ||
d9bce9d9 JM |
329 | #if defined(TARGET_PPC64) |
330 | void do_addmeo_64 (void) | |
fdabc366 FB |
331 | { |
332 | T1 = T0; | |
d9bce9d9 JM |
333 | T0 += xer_ca + (-1); |
334 | if (likely(!((uint64_t)T1 & | |
335 | ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) { | |
fdabc366 FB |
336 | xer_ov = 0; |
337 | } else { | |
fdabc366 | 338 | xer_ov = 1; |
966439a6 | 339 | xer_so = 1; |
fdabc366 | 340 | } |
d9bce9d9 | 341 | if (likely(T1 != 0)) |
fdabc366 | 342 | xer_ca = 1; |
fdabc366 | 343 | } |
d9bce9d9 | 344 | #endif |
fdabc366 FB |
345 | |
346 | void do_divwo (void) | |
347 | { | |
d9bce9d9 JM |
348 | if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || |
349 | (int32_t)T1 == 0))) { | |
fdabc366 | 350 | xer_ov = 0; |
d9bce9d9 | 351 | T0 = (int32_t)T0 / (int32_t)T1; |
fdabc366 | 352 | } else { |
fdabc366 | 353 | xer_ov = 1; |
966439a6 | 354 | xer_so = 1; |
fdabc366 FB |
355 | T0 = (-1) * ((uint32_t)T0 >> 31); |
356 | } | |
357 | } | |
358 | ||
d9bce9d9 JM |
359 | #if defined(TARGET_PPC64) |
360 | void do_divdo (void) | |
361 | { | |
362 | if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) || | |
363 | (int64_t)T1 == 0))) { | |
364 | xer_ov = 0; | |
365 | T0 = (int64_t)T0 / (int64_t)T1; | |
366 | } else { | |
d9bce9d9 | 367 | xer_ov = 1; |
966439a6 | 368 | xer_so = 1; |
d9bce9d9 JM |
369 | T0 = (-1ULL) * ((uint64_t)T0 >> 63); |
370 | } | |
371 | } | |
372 | #endif | |
373 | ||
fdabc366 FB |
374 | void do_divwuo (void) |
375 | { | |
376 | if (likely((uint32_t)T1 != 0)) { | |
377 | xer_ov = 0; | |
378 | T0 = (uint32_t)T0 / (uint32_t)T1; | |
379 | } else { | |
fdabc366 | 380 | xer_ov = 1; |
966439a6 | 381 | xer_so = 1; |
fdabc366 FB |
382 | T0 = 0; |
383 | } | |
384 | } | |
385 | ||
d9bce9d9 JM |
386 | #if defined(TARGET_PPC64) |
387 | void do_divduo (void) | |
388 | { | |
389 | if (likely((uint64_t)T1 != 0)) { | |
390 | xer_ov = 0; | |
391 | T0 = (uint64_t)T0 / (uint64_t)T1; | |
392 | } else { | |
d9bce9d9 | 393 | xer_ov = 1; |
966439a6 | 394 | xer_so = 1; |
d9bce9d9 JM |
395 | T0 = 0; |
396 | } | |
397 | } | |
398 | #endif | |
399 | ||
fdabc366 FB |
400 | void do_mullwo (void) |
401 | { | |
d9bce9d9 | 402 | int64_t res = (int64_t)T0 * (int64_t)T1; |
fdabc366 FB |
403 | |
404 | if (likely((int32_t)res == res)) { | |
405 | xer_ov = 0; | |
406 | } else { | |
407 | xer_ov = 1; | |
408 | xer_so = 1; | |
409 | } | |
410 | T0 = (int32_t)res; | |
411 | } | |
412 | ||
d9bce9d9 JM |
413 | #if defined(TARGET_PPC64) |
414 | void do_mulldo (void) | |
fdabc366 | 415 | { |
d9bce9d9 JM |
416 | int64_t th; |
417 | uint64_t tl; | |
418 | ||
419 | do_imul64(&tl, &th); | |
420 | if (likely(th == 0)) { | |
fdabc366 | 421 | xer_ov = 0; |
fdabc366 FB |
422 | } else { |
423 | xer_ov = 1; | |
424 | xer_so = 1; | |
425 | } | |
d9bce9d9 | 426 | T0 = (int64_t)tl; |
fdabc366 | 427 | } |
d9bce9d9 | 428 | #endif |
fdabc366 | 429 | |
d9bce9d9 | 430 | void do_nego (void) |
fdabc366 | 431 | { |
d9bce9d9 | 432 | if (likely((int32_t)T0 != INT32_MIN)) { |
fdabc366 | 433 | xer_ov = 0; |
d9bce9d9 | 434 | T0 = -(int32_t)T0; |
fdabc366 | 435 | } else { |
fdabc366 | 436 | xer_ov = 1; |
d9bce9d9 | 437 | xer_so = 1; |
fdabc366 | 438 | } |
fdabc366 FB |
439 | } |
440 | ||
d9bce9d9 JM |
441 | #if defined(TARGET_PPC64) |
442 | void do_nego_64 (void) | |
fdabc366 | 443 | { |
d9bce9d9 | 444 | if (likely((int64_t)T0 != INT64_MIN)) { |
fdabc366 | 445 | xer_ov = 0; |
d9bce9d9 | 446 | T0 = -(int64_t)T0; |
fdabc366 | 447 | } else { |
fdabc366 | 448 | xer_ov = 1; |
d9bce9d9 | 449 | xer_so = 1; |
fdabc366 FB |
450 | } |
451 | } | |
d9bce9d9 | 452 | #endif |
fdabc366 FB |
453 | |
454 | void do_subfe (void) | |
455 | { | |
456 | T0 = T1 + ~T0 + xer_ca; | |
d9bce9d9 JM |
457 | if (likely((uint32_t)T0 >= (uint32_t)T1 && |
458 | (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) { | |
fdabc366 FB |
459 | xer_ca = 0; |
460 | } else { | |
461 | xer_ca = 1; | |
462 | } | |
463 | } | |
464 | ||
d9bce9d9 JM |
465 | #if defined(TARGET_PPC64) |
466 | void do_subfe_64 (void) | |
fdabc366 | 467 | { |
fdabc366 | 468 | T0 = T1 + ~T0 + xer_ca; |
d9bce9d9 JM |
469 | if (likely((uint64_t)T0 >= (uint64_t)T1 && |
470 | (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) { | |
471 | xer_ca = 0; | |
472 | } else { | |
473 | xer_ca = 1; | |
474 | } | |
475 | } | |
476 | #endif | |
477 | ||
478 | void do_subfmeo (void) | |
479 | { | |
480 | T1 = T0; | |
481 | T0 = ~T0 + xer_ca - 1; | |
482 | if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) & | |
483 | (1UL << 31)))) { | |
fdabc366 FB |
484 | xer_ov = 0; |
485 | } else { | |
fdabc366 | 486 | xer_ov = 1; |
966439a6 | 487 | xer_so = 1; |
fdabc366 | 488 | } |
d9bce9d9 | 489 | if (likely((uint32_t)T1 != UINT32_MAX)) |
fdabc366 | 490 | xer_ca = 1; |
fdabc366 FB |
491 | } |
492 | ||
d9bce9d9 JM |
493 | #if defined(TARGET_PPC64) |
494 | void do_subfmeo_64 (void) | |
fdabc366 FB |
495 | { |
496 | T1 = T0; | |
497 | T0 = ~T0 + xer_ca - 1; | |
d9bce9d9 JM |
498 | if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) & |
499 | (1ULL << 63)))) { | |
fdabc366 FB |
500 | xer_ov = 0; |
501 | } else { | |
fdabc366 | 502 | xer_ov = 1; |
966439a6 | 503 | xer_so = 1; |
fdabc366 | 504 | } |
d9bce9d9 | 505 | if (likely((uint64_t)T1 != UINT64_MAX)) |
fdabc366 FB |
506 | xer_ca = 1; |
507 | } | |
d9bce9d9 | 508 | #endif |
fdabc366 FB |
509 | |
510 | void do_subfzeo (void) | |
511 | { | |
512 | T1 = T0; | |
513 | T0 = ~T0 + xer_ca; | |
d9bce9d9 JM |
514 | if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) & |
515 | ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) { | |
fdabc366 FB |
516 | xer_ov = 0; |
517 | } else { | |
518 | xer_ov = 1; | |
519 | xer_so = 1; | |
520 | } | |
d9bce9d9 | 521 | if (likely((uint32_t)T0 >= (uint32_t)~T1)) { |
fdabc366 FB |
522 | xer_ca = 0; |
523 | } else { | |
524 | xer_ca = 1; | |
525 | } | |
526 | } | |
527 | ||
d9bce9d9 JM |
528 | #if defined(TARGET_PPC64) |
529 | void do_subfzeo_64 (void) | |
530 | { | |
531 | T1 = T0; | |
532 | T0 = ~T0 + xer_ca; | |
533 | if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) & | |
534 | ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) { | |
535 | xer_ov = 0; | |
536 | } else { | |
537 | xer_ov = 1; | |
538 | xer_so = 1; | |
539 | } | |
540 | if (likely((uint64_t)T0 >= (uint64_t)~T1)) { | |
541 | xer_ca = 0; | |
542 | } else { | |
543 | xer_ca = 1; | |
544 | } | |
545 | } | |
546 | #endif | |
547 | ||
9a64fbe4 FB |
548 | /* shift right arithmetic helper */ |
549 | void do_sraw (void) | |
550 | { | |
551 | int32_t ret; | |
552 | ||
fdabc366 | 553 | if (likely(!(T1 & 0x20UL))) { |
d9bce9d9 | 554 | if (likely((uint32_t)T1 != 0)) { |
fdabc366 FB |
555 | ret = (int32_t)T0 >> (T1 & 0x1fUL); |
556 | if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) { | |
76a66253 | 557 | xer_ca = 0; |
fdabc366 | 558 | } else { |
76a66253 | 559 | xer_ca = 1; |
fdabc366 FB |
560 | } |
561 | } else { | |
76a66253 | 562 | ret = T0; |
fdabc366 FB |
563 | xer_ca = 0; |
564 | } | |
565 | } else { | |
566 | ret = (-1) * ((uint32_t)T0 >> 31); | |
567 | if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) { | |
568 | xer_ca = 0; | |
76a66253 | 569 | } else { |
9a64fbe4 | 570 | xer_ca = 1; |
76a66253 | 571 | } |
fdabc366 | 572 | } |
4b3686fa | 573 | T0 = ret; |
9a64fbe4 FB |
574 | } |
575 | ||
d9bce9d9 JM |
576 | #if defined(TARGET_PPC64) |
577 | void do_srad (void) | |
578 | { | |
579 | int64_t ret; | |
580 | ||
581 | if (likely(!(T1 & 0x40UL))) { | |
582 | if (likely((uint64_t)T1 != 0)) { | |
583 | ret = (int64_t)T0 >> (T1 & 0x3FUL); | |
584 | if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) { | |
585 | xer_ca = 0; | |
586 | } else { | |
587 | xer_ca = 1; | |
588 | } | |
589 | } else { | |
590 | ret = T0; | |
591 | xer_ca = 0; | |
592 | } | |
593 | } else { | |
594 | ret = (-1) * ((uint64_t)T0 >> 63); | |
595 | if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) { | |
596 | xer_ca = 0; | |
597 | } else { | |
598 | xer_ca = 1; | |
599 | } | |
600 | } | |
601 | T0 = ret; | |
602 | } | |
603 | #endif | |
604 | ||
605 | static inline int popcnt (uint32_t val) | |
606 | { | |
607 | int i; | |
608 | ||
609 | for (i = 0; val != 0;) | |
610 | val = val ^ (val - 1); | |
611 | ||
612 | return i; | |
613 | } | |
614 | ||
615 | void do_popcntb (void) | |
616 | { | |
617 | uint32_t ret; | |
618 | int i; | |
619 | ||
620 | ret = 0; | |
621 | for (i = 0; i < 32; i += 8) | |
622 | ret |= popcnt((T0 >> i) & 0xFF) << i; | |
623 | T0 = ret; | |
624 | } | |
625 | ||
626 | #if defined(TARGET_PPC64) | |
627 | void do_popcntb_64 (void) | |
628 | { | |
629 | uint64_t ret; | |
630 | int i; | |
631 | ||
632 | ret = 0; | |
633 | for (i = 0; i < 64; i += 8) | |
634 | ret |= popcnt((T0 >> i) & 0xFF) << i; | |
635 | T0 = ret; | |
636 | } | |
637 | #endif | |
638 | ||
fdabc366 | 639 | /*****************************************************************************/ |
9a64fbe4 | 640 | /* Floating point operations helpers */ |
9a64fbe4 FB |
641 | void do_fctiw (void) |
642 | { | |
643 | union { | |
644 | double d; | |
645 | uint64_t i; | |
4ecc3190 | 646 | } p; |
9a64fbe4 | 647 | |
e864cabd JM |
648 | p.i = float64_to_int32(FT0, &env->fp_status); |
649 | #if USE_PRECISE_EMULATION | |
4ecc3190 | 650 | /* XXX: higher bits are not supposed to be significant. |
76a66253 | 651 | * to make tests easier, return the same as a real PowerPC 750 (aka G3) |
4ecc3190 | 652 | */ |
4ecc3190 | 653 | p.i |= 0xFFF80000ULL << 32; |
e864cabd | 654 | #endif |
4ecc3190 | 655 | FT0 = p.d; |
9a64fbe4 FB |
656 | } |
657 | ||
658 | void do_fctiwz (void) | |
659 | { | |
660 | union { | |
661 | double d; | |
662 | uint64_t i; | |
4ecc3190 FB |
663 | } p; |
664 | ||
e864cabd JM |
665 | p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status); |
666 | #if USE_PRECISE_EMULATION | |
4ecc3190 | 667 | /* XXX: higher bits are not supposed to be significant. |
d9bce9d9 | 668 | * to make tests easier, return the same as a real PowerPC 750 (aka G3) |
4ecc3190 | 669 | */ |
4ecc3190 | 670 | p.i |= 0xFFF80000ULL << 32; |
e864cabd | 671 | #endif |
4ecc3190 | 672 | FT0 = p.d; |
9a64fbe4 FB |
673 | } |
674 | ||
426613db JM |
675 | #if defined(TARGET_PPC64) |
676 | void do_fcfid (void) | |
677 | { | |
678 | union { | |
679 | double d; | |
680 | uint64_t i; | |
681 | } p; | |
682 | ||
683 | p.d = FT0; | |
684 | FT0 = int64_to_float64(p.i, &env->fp_status); | |
685 | } | |
686 | ||
687 | void do_fctid (void) | |
688 | { | |
689 | union { | |
690 | double d; | |
691 | uint64_t i; | |
692 | } p; | |
693 | ||
694 | p.i = float64_to_int64(FT0, &env->fp_status); | |
695 | FT0 = p.d; | |
696 | } | |
697 | ||
698 | void do_fctidz (void) | |
699 | { | |
700 | union { | |
701 | double d; | |
702 | uint64_t i; | |
703 | } p; | |
704 | ||
705 | p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status); | |
706 | FT0 = p.d; | |
707 | } | |
708 | ||
709 | #endif | |
710 | ||
d7e4b87e JM |
711 | static inline void do_fri (int rounding_mode) |
712 | { | |
713 | int curmode; | |
714 | ||
715 | curmode = env->fp_status.float_rounding_mode; | |
716 | set_float_rounding_mode(rounding_mode, &env->fp_status); | |
717 | FT0 = float64_round_to_int(FT0, &env->fp_status); | |
718 | set_float_rounding_mode(curmode, &env->fp_status); | |
719 | } | |
720 | ||
721 | void do_frin (void) | |
722 | { | |
723 | do_fri(float_round_nearest_even); | |
724 | } | |
725 | ||
726 | void do_friz (void) | |
727 | { | |
728 | do_fri(float_round_to_zero); | |
729 | } | |
730 | ||
731 | void do_frip (void) | |
732 | { | |
733 | do_fri(float_round_up); | |
734 | } | |
735 | ||
736 | void do_frim (void) | |
737 | { | |
738 | do_fri(float_round_down); | |
739 | } | |
740 | ||
e864cabd JM |
741 | #if USE_PRECISE_EMULATION |
742 | void do_fmadd (void) | |
743 | { | |
744 | #ifdef FLOAT128 | |
745 | float128 ft0_128, ft1_128; | |
746 | ||
747 | ft0_128 = float64_to_float128(FT0, &env->fp_status); | |
748 | ft1_128 = float64_to_float128(FT1, &env->fp_status); | |
749 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); | |
750 | ft1_128 = float64_to_float128(FT2, &env->fp_status); | |
751 | ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status); | |
752 | FT0 = float128_to_float64(ft0_128, &env->fp_status); | |
753 | #else | |
754 | /* This is OK on x86 hosts */ | |
755 | FT0 = (FT0 * FT1) + FT2; | |
756 | #endif | |
757 | } | |
758 | ||
759 | void do_fmsub (void) | |
760 | { | |
761 | #ifdef FLOAT128 | |
762 | float128 ft0_128, ft1_128; | |
763 | ||
764 | ft0_128 = float64_to_float128(FT0, &env->fp_status); | |
765 | ft1_128 = float64_to_float128(FT1, &env->fp_status); | |
766 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); | |
767 | ft1_128 = float64_to_float128(FT2, &env->fp_status); | |
768 | ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status); | |
769 | FT0 = float128_to_float64(ft0_128, &env->fp_status); | |
770 | #else | |
771 | /* This is OK on x86 hosts */ | |
772 | FT0 = (FT0 * FT1) - FT2; | |
773 | #endif | |
774 | } | |
775 | #endif /* USE_PRECISE_EMULATION */ | |
776 | ||
4b3686fa FB |
777 | void do_fnmadd (void) |
778 | { | |
e864cabd JM |
779 | #if USE_PRECISE_EMULATION |
780 | #ifdef FLOAT128 | |
781 | float128 ft0_128, ft1_128; | |
782 | ||
783 | ft0_128 = float64_to_float128(FT0, &env->fp_status); | |
784 | ft1_128 = float64_to_float128(FT1, &env->fp_status); | |
785 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); | |
786 | ft1_128 = float64_to_float128(FT2, &env->fp_status); | |
787 | ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status); | |
788 | FT0 = float128_to_float64(ft0_128, &env->fp_status); | |
789 | #else | |
790 | /* This is OK on x86 hosts */ | |
791 | FT0 = (FT0 * FT1) + FT2; | |
792 | #endif | |
793 | #else | |
fdabc366 FB |
794 | FT0 = float64_mul(FT0, FT1, &env->fp_status); |
795 | FT0 = float64_add(FT0, FT2, &env->fp_status); | |
e864cabd | 796 | #endif |
fdabc366 FB |
797 | if (likely(!isnan(FT0))) |
798 | FT0 = float64_chs(FT0); | |
4b3686fa FB |
799 | } |
800 | ||
801 | void do_fnmsub (void) | |
802 | { | |
e864cabd JM |
803 | #if USE_PRECISE_EMULATION |
804 | #ifdef FLOAT128 | |
805 | float128 ft0_128, ft1_128; | |
806 | ||
807 | ft0_128 = float64_to_float128(FT0, &env->fp_status); | |
808 | ft1_128 = float64_to_float128(FT1, &env->fp_status); | |
809 | ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); | |
810 | ft1_128 = float64_to_float128(FT2, &env->fp_status); | |
811 | ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status); | |
812 | FT0 = float128_to_float64(ft0_128, &env->fp_status); | |
813 | #else | |
814 | /* This is OK on x86 hosts */ | |
815 | FT0 = (FT0 * FT1) - FT2; | |
816 | #endif | |
817 | #else | |
fdabc366 FB |
818 | FT0 = float64_mul(FT0, FT1, &env->fp_status); |
819 | FT0 = float64_sub(FT0, FT2, &env->fp_status); | |
e864cabd | 820 | #endif |
fdabc366 FB |
821 | if (likely(!isnan(FT0))) |
822 | FT0 = float64_chs(FT0); | |
1ef59d0a FB |
823 | } |
824 | ||
9a64fbe4 FB |
825 | void do_fsqrt (void) |
826 | { | |
fdabc366 | 827 | FT0 = float64_sqrt(FT0, &env->fp_status); |
9a64fbe4 FB |
828 | } |
829 | ||
d7e4b87e JM |
830 | void do_fre (void) |
831 | { | |
832 | union { | |
833 | double d; | |
834 | uint64_t i; | |
835 | } p; | |
836 | ||
837 | if (likely(isnormal(FT0))) { | |
838 | FT0 = float64_div(1.0, FT0, &env->fp_status); | |
839 | } else { | |
840 | p.d = FT0; | |
841 | if (p.i == 0x8000000000000000ULL) { | |
842 | p.i = 0xFFF0000000000000ULL; | |
843 | } else if (p.i == 0x0000000000000000ULL) { | |
844 | p.i = 0x7FF0000000000000ULL; | |
845 | } else if (isnan(FT0)) { | |
846 | p.i = 0x7FF8000000000000ULL; | |
847 | } else if (FT0 < 0.0) { | |
848 | p.i = 0x8000000000000000ULL; | |
849 | } else { | |
850 | p.i = 0x0000000000000000ULL; | |
851 | } | |
852 | FT0 = p.d; | |
853 | } | |
854 | } | |
855 | ||
9a64fbe4 FB |
856 | void do_fres (void) |
857 | { | |
4ecc3190 FB |
858 | union { |
859 | double d; | |
860 | uint64_t i; | |
861 | } p; | |
862 | ||
fdabc366 | 863 | if (likely(isnormal(FT0))) { |
e864cabd JM |
864 | #if USE_PRECISE_EMULATION |
865 | FT0 = float64_div(1.0, FT0, &env->fp_status); | |
866 | FT0 = float64_to_float32(FT0, &env->fp_status); | |
867 | #else | |
76a66253 | 868 | FT0 = float32_div(1.0, FT0, &env->fp_status); |
e864cabd | 869 | #endif |
4ecc3190 FB |
870 | } else { |
871 | p.d = FT0; | |
872 | if (p.i == 0x8000000000000000ULL) { | |
873 | p.i = 0xFFF0000000000000ULL; | |
874 | } else if (p.i == 0x0000000000000000ULL) { | |
875 | p.i = 0x7FF0000000000000ULL; | |
876 | } else if (isnan(FT0)) { | |
877 | p.i = 0x7FF8000000000000ULL; | |
878 | } else if (FT0 < 0.0) { | |
879 | p.i = 0x8000000000000000ULL; | |
880 | } else { | |
881 | p.i = 0x0000000000000000ULL; | |
882 | } | |
883 | FT0 = p.d; | |
884 | } | |
9a64fbe4 FB |
885 | } |
886 | ||
4ecc3190 | 887 | void do_frsqrte (void) |
9a64fbe4 | 888 | { |
4ecc3190 FB |
889 | union { |
890 | double d; | |
891 | uint64_t i; | |
892 | } p; | |
893 | ||
fdabc366 FB |
894 | if (likely(isnormal(FT0) && FT0 > 0.0)) { |
895 | FT0 = float64_sqrt(FT0, &env->fp_status); | |
896 | FT0 = float32_div(1.0, FT0, &env->fp_status); | |
4ecc3190 FB |
897 | } else { |
898 | p.d = FT0; | |
899 | if (p.i == 0x8000000000000000ULL) { | |
900 | p.i = 0xFFF0000000000000ULL; | |
901 | } else if (p.i == 0x0000000000000000ULL) { | |
902 | p.i = 0x7FF0000000000000ULL; | |
903 | } else if (isnan(FT0)) { | |
904 | if (!(p.i & 0x0008000000000000ULL)) | |
905 | p.i |= 0x000FFFFFFFFFFFFFULL; | |
906 | } else if (FT0 < 0) { | |
907 | p.i = 0x7FF8000000000000ULL; | |
908 | } else { | |
909 | p.i = 0x0000000000000000ULL; | |
910 | } | |
911 | FT0 = p.d; | |
912 | } | |
9a64fbe4 FB |
913 | } |
914 | ||
915 | void do_fsel (void) | |
916 | { | |
917 | if (FT0 >= 0) | |
9a64fbe4 | 918 | FT0 = FT1; |
4ecc3190 FB |
919 | else |
920 | FT0 = FT2; | |
9a64fbe4 FB |
921 | } |
922 | ||
923 | void do_fcmpu (void) | |
924 | { | |
fdabc366 FB |
925 | if (likely(!isnan(FT0) && !isnan(FT1))) { |
926 | if (float64_lt(FT0, FT1, &env->fp_status)) { | |
927 | T0 = 0x08UL; | |
928 | } else if (!float64_le(FT0, FT1, &env->fp_status)) { | |
929 | T0 = 0x04UL; | |
930 | } else { | |
931 | T0 = 0x02UL; | |
932 | } | |
933 | } else { | |
934 | T0 = 0x01UL; | |
9a64fbe4 FB |
935 | env->fpscr[4] |= 0x1; |
936 | env->fpscr[6] |= 0x1; | |
9a64fbe4 | 937 | } |
4b3686fa | 938 | env->fpscr[3] = T0; |
9a64fbe4 FB |
939 | } |
940 | ||
941 | void do_fcmpo (void) | |
942 | { | |
943 | env->fpscr[4] &= ~0x1; | |
fdabc366 FB |
944 | if (likely(!isnan(FT0) && !isnan(FT1))) { |
945 | if (float64_lt(FT0, FT1, &env->fp_status)) { | |
946 | T0 = 0x08UL; | |
947 | } else if (!float64_le(FT0, FT1, &env->fp_status)) { | |
948 | T0 = 0x04UL; | |
949 | } else { | |
950 | T0 = 0x02UL; | |
951 | } | |
952 | } else { | |
953 | T0 = 0x01UL; | |
9a64fbe4 | 954 | env->fpscr[4] |= 0x1; |
76a66253 JM |
955 | if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) { |
956 | /* Quiet NaN case */ | |
9a64fbe4 FB |
957 | env->fpscr[6] |= 0x1; |
958 | if (!(env->fpscr[1] & 0x8)) | |
959 | env->fpscr[4] |= 0x8; | |
960 | } else { | |
961 | env->fpscr[4] |= 0x8; | |
962 | } | |
9a64fbe4 | 963 | } |
4b3686fa | 964 | env->fpscr[3] = T0; |
9a64fbe4 FB |
965 | } |
966 | ||
76a66253 | 967 | #if !defined (CONFIG_USER_ONLY) |
6b80055d | 968 | void cpu_dump_rfi (target_ulong RA, target_ulong msr); |
fdabc366 | 969 | void do_rfi (void) |
9a64fbe4 | 970 | { |
426613db | 971 | #if defined(TARGET_PPC64) |
a42bd6cc JM |
972 | if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) { |
973 | env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003); | |
974 | do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); | |
975 | } else { | |
976 | env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); | |
977 | ppc_store_msr_32(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); | |
978 | } | |
426613db | 979 | #else |
a42bd6cc JM |
980 | env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); |
981 | do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); | |
426613db | 982 | #endif |
fdabc366 | 983 | #if defined (DEBUG_OP) |
6b80055d | 984 | cpu_dump_rfi(env->nip, do_load_msr(env)); |
fdabc366 FB |
985 | #endif |
986 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
9a64fbe4 | 987 | } |
d9bce9d9 JM |
988 | |
989 | #if defined(TARGET_PPC64) | |
426613db JM |
990 | void do_rfid (void) |
991 | { | |
a42bd6cc JM |
992 | if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) { |
993 | env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003); | |
994 | do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); | |
995 | } else { | |
996 | env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); | |
997 | do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); | |
998 | } | |
d9bce9d9 | 999 | #if defined (DEBUG_OP) |
6b80055d | 1000 | cpu_dump_rfi(env->nip, do_load_msr(env)); |
d9bce9d9 JM |
1001 | #endif |
1002 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
1003 | } | |
1004 | #endif | |
76a66253 | 1005 | #endif |
9a64fbe4 | 1006 | |
76a66253 | 1007 | void do_tw (int flags) |
9a64fbe4 | 1008 | { |
d9bce9d9 JM |
1009 | if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) || |
1010 | ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) || | |
1011 | ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) || | |
1012 | ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) || | |
a42bd6cc | 1013 | ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) { |
e1833e1f | 1014 | do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); |
a42bd6cc | 1015 | } |
9a64fbe4 FB |
1016 | } |
1017 | ||
d9bce9d9 JM |
1018 | #if defined(TARGET_PPC64) |
1019 | void do_td (int flags) | |
1020 | { | |
1021 | if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) || | |
1022 | ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) || | |
1023 | ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) || | |
1024 | ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) || | |
1025 | ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01))))) | |
e1833e1f | 1026 | do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); |
d9bce9d9 JM |
1027 | } |
1028 | #endif | |
1029 | ||
fdabc366 | 1030 | /*****************************************************************************/ |
76a66253 JM |
1031 | /* PowerPC 601 specific instructions (POWER bridge) */ |
1032 | void do_POWER_abso (void) | |
9a64fbe4 | 1033 | { |
d9bce9d9 | 1034 | if ((uint32_t)T0 == INT32_MIN) { |
76a66253 JM |
1035 | T0 = INT32_MAX; |
1036 | xer_ov = 1; | |
1037 | xer_so = 1; | |
1038 | } else { | |
1039 | T0 = -T0; | |
1040 | xer_ov = 0; | |
1041 | } | |
9a64fbe4 FB |
1042 | } |
1043 | ||
76a66253 | 1044 | void do_POWER_clcs (void) |
9a64fbe4 | 1045 | { |
76a66253 JM |
1046 | switch (T0) { |
1047 | case 0x0CUL: | |
1048 | /* Instruction cache line size */ | |
1049 | T0 = ICACHE_LINE_SIZE; | |
1050 | break; | |
1051 | case 0x0DUL: | |
1052 | /* Data cache line size */ | |
1053 | T0 = DCACHE_LINE_SIZE; | |
1054 | break; | |
1055 | case 0x0EUL: | |
1056 | /* Minimum cache line size */ | |
1057 | T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ? | |
1058 | ICACHE_LINE_SIZE : DCACHE_LINE_SIZE; | |
1059 | break; | |
1060 | case 0x0FUL: | |
1061 | /* Maximum cache line size */ | |
1062 | T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ? | |
1063 | ICACHE_LINE_SIZE : DCACHE_LINE_SIZE; | |
1064 | break; | |
1065 | default: | |
1066 | /* Undefined */ | |
1067 | break; | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | void do_POWER_div (void) | |
1072 | { | |
1073 | uint64_t tmp; | |
1074 | ||
d9bce9d9 | 1075 | if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) { |
76a66253 JM |
1076 | T0 = (long)((-1) * (T0 >> 31)); |
1077 | env->spr[SPR_MQ] = 0; | |
1078 | } else { | |
1079 | tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ]; | |
1080 | env->spr[SPR_MQ] = tmp % T1; | |
d9bce9d9 | 1081 | T0 = tmp / (int32_t)T1; |
76a66253 JM |
1082 | } |
1083 | } | |
1084 | ||
1085 | void do_POWER_divo (void) | |
1086 | { | |
1087 | int64_t tmp; | |
1088 | ||
d9bce9d9 | 1089 | if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) { |
76a66253 JM |
1090 | T0 = (long)((-1) * (T0 >> 31)); |
1091 | env->spr[SPR_MQ] = 0; | |
1092 | xer_ov = 1; | |
1093 | xer_so = 1; | |
1094 | } else { | |
1095 | tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ]; | |
1096 | env->spr[SPR_MQ] = tmp % T1; | |
d9bce9d9 | 1097 | tmp /= (int32_t)T1; |
76a66253 JM |
1098 | if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) { |
1099 | xer_ov = 1; | |
1100 | xer_so = 1; | |
1101 | } else { | |
1102 | xer_ov = 0; | |
1103 | } | |
1104 | T0 = tmp; | |
1105 | } | |
1106 | } | |
1107 | ||
1108 | void do_POWER_divs (void) | |
1109 | { | |
d9bce9d9 | 1110 | if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) { |
76a66253 JM |
1111 | T0 = (long)((-1) * (T0 >> 31)); |
1112 | env->spr[SPR_MQ] = 0; | |
1113 | } else { | |
1114 | env->spr[SPR_MQ] = T0 % T1; | |
d9bce9d9 | 1115 | T0 = (int32_t)T0 / (int32_t)T1; |
76a66253 JM |
1116 | } |
1117 | } | |
1118 | ||
1119 | void do_POWER_divso (void) | |
1120 | { | |
d9bce9d9 | 1121 | if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) { |
76a66253 JM |
1122 | T0 = (long)((-1) * (T0 >> 31)); |
1123 | env->spr[SPR_MQ] = 0; | |
1124 | xer_ov = 1; | |
1125 | xer_so = 1; | |
1126 | } else { | |
d9bce9d9 JM |
1127 | T0 = (int32_t)T0 / (int32_t)T1; |
1128 | env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1; | |
76a66253 JM |
1129 | xer_ov = 0; |
1130 | } | |
1131 | } | |
1132 | ||
1133 | void do_POWER_dozo (void) | |
1134 | { | |
d9bce9d9 | 1135 | if ((int32_t)T1 > (int32_t)T0) { |
76a66253 JM |
1136 | T2 = T0; |
1137 | T0 = T1 - T0; | |
d9bce9d9 JM |
1138 | if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) & |
1139 | ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) { | |
76a66253 | 1140 | xer_ov = 1; |
966439a6 | 1141 | xer_so = 1; |
76a66253 JM |
1142 | } else { |
1143 | xer_ov = 0; | |
1144 | } | |
1145 | } else { | |
1146 | T0 = 0; | |
1147 | xer_ov = 0; | |
1148 | } | |
1149 | } | |
1150 | ||
1151 | void do_POWER_maskg (void) | |
1152 | { | |
1153 | uint32_t ret; | |
1154 | ||
d9bce9d9 | 1155 | if ((uint32_t)T0 == (uint32_t)(T1 + 1)) { |
76a66253 JM |
1156 | ret = -1; |
1157 | } else { | |
d9bce9d9 JM |
1158 | ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^ |
1159 | (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1); | |
1160 | if ((uint32_t)T0 > (uint32_t)T1) | |
76a66253 JM |
1161 | ret = ~ret; |
1162 | } | |
1163 | T0 = ret; | |
1164 | } | |
1165 | ||
1166 | void do_POWER_mulo (void) | |
1167 | { | |
1168 | uint64_t tmp; | |
1169 | ||
1170 | tmp = (uint64_t)T0 * (uint64_t)T1; | |
1171 | env->spr[SPR_MQ] = tmp >> 32; | |
1172 | T0 = tmp; | |
1173 | if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) { | |
1174 | xer_ov = 1; | |
1175 | xer_so = 1; | |
1176 | } else { | |
1177 | xer_ov = 0; | |
1178 | } | |
1179 | } | |
1180 | ||
1181 | #if !defined (CONFIG_USER_ONLY) | |
1182 | void do_POWER_rac (void) | |
1183 | { | |
1184 | #if 0 | |
1185 | mmu_ctx_t ctx; | |
1186 | ||
1187 | /* We don't have to generate many instances of this instruction, | |
1188 | * as rac is supervisor only. | |
1189 | */ | |
1190 | if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0) | |
1191 | T0 = ctx.raddr; | |
1192 | #endif | |
1193 | } | |
1194 | ||
1195 | void do_POWER_rfsvc (void) | |
1196 | { | |
1197 | env->nip = env->lr & ~0x00000003UL; | |
1198 | T0 = env->ctr & 0x0000FFFFUL; | |
1199 | do_store_msr(env, T0); | |
1200 | #if defined (DEBUG_OP) | |
6b80055d | 1201 | cpu_dump_rfi(env->nip, do_load_msr(env)); |
76a66253 JM |
1202 | #endif |
1203 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
1204 | } | |
1205 | ||
1206 | /* PowerPC 601 BAT management helper */ | |
1207 | void do_store_601_batu (int nr) | |
1208 | { | |
d9bce9d9 | 1209 | do_store_ibatu(env, nr, (uint32_t)T0); |
76a66253 JM |
1210 | env->DBAT[0][nr] = env->IBAT[0][nr]; |
1211 | env->DBAT[1][nr] = env->IBAT[1][nr]; | |
1212 | } | |
1213 | #endif | |
1214 | ||
1215 | /*****************************************************************************/ | |
1216 | /* 602 specific instructions */ | |
1217 | /* mfrom is the most crazy instruction ever seen, imho ! */ | |
1218 | /* Real implementation uses a ROM table. Do the same */ | |
1219 | #define USE_MFROM_ROM_TABLE | |
1220 | void do_op_602_mfrom (void) | |
1221 | { | |
1222 | if (likely(T0 < 602)) { | |
d9bce9d9 | 1223 | #if defined(USE_MFROM_ROM_TABLE) |
76a66253 JM |
1224 | #include "mfrom_table.c" |
1225 | T0 = mfrom_ROM_table[T0]; | |
fdabc366 | 1226 | #else |
76a66253 JM |
1227 | double d; |
1228 | /* Extremly decomposed: | |
1229 | * -T0 / 256 | |
1230 | * T0 = 256 * log10(10 + 1.0) + 0.5 | |
1231 | */ | |
1232 | d = T0; | |
1233 | d = float64_div(d, 256, &env->fp_status); | |
1234 | d = float64_chs(d); | |
1235 | d = exp10(d); // XXX: use float emulation function | |
1236 | d = float64_add(d, 1.0, &env->fp_status); | |
1237 | d = log10(d); // XXX: use float emulation function | |
1238 | d = float64_mul(d, 256, &env->fp_status); | |
1239 | d = float64_add(d, 0.5, &env->fp_status); | |
1240 | T0 = float64_round_to_int(d, &env->fp_status); | |
fdabc366 | 1241 | #endif |
76a66253 JM |
1242 | } else { |
1243 | T0 = 0; | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | /*****************************************************************************/ | |
1248 | /* Embedded PowerPC specific helpers */ | |
1249 | void do_405_check_ov (void) | |
1250 | { | |
d9bce9d9 JM |
1251 | if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) || |
1252 | !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) { | |
76a66253 JM |
1253 | xer_ov = 0; |
1254 | } else { | |
1255 | xer_ov = 1; | |
1256 | xer_so = 1; | |
1257 | } | |
1258 | } | |
1259 | ||
1260 | void do_405_check_sat (void) | |
1261 | { | |
d9bce9d9 JM |
1262 | if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) || |
1263 | !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) { | |
76a66253 JM |
1264 | /* Saturate result */ |
1265 | if (T2 >> 31) { | |
1266 | T0 = INT32_MIN; | |
1267 | } else { | |
1268 | T0 = INT32_MAX; | |
1269 | } | |
1270 | } | |
1271 | } | |
1272 | ||
a750fc0b JM |
1273 | /* XXX: to be improved to check access rights when in user-mode */ |
1274 | void do_load_dcr (void) | |
1275 | { | |
1276 | target_ulong val; | |
1277 | ||
1278 | if (unlikely(env->dcr_env == NULL)) { | |
1279 | if (loglevel != 0) { | |
1280 | fprintf(logfile, "No DCR environment\n"); | |
1281 | } | |
e1833e1f JM |
1282 | do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1283 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); | |
a750fc0b JM |
1284 | } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) { |
1285 | if (loglevel != 0) { | |
1286 | fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0); | |
1287 | } | |
e1833e1f JM |
1288 | do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1289 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); | |
a750fc0b JM |
1290 | } else { |
1291 | T0 = val; | |
1292 | } | |
1293 | } | |
1294 | ||
1295 | void do_store_dcr (void) | |
1296 | { | |
1297 | if (unlikely(env->dcr_env == NULL)) { | |
1298 | if (loglevel != 0) { | |
1299 | fprintf(logfile, "No DCR environment\n"); | |
1300 | } | |
e1833e1f JM |
1301 | do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1302 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); | |
a750fc0b JM |
1303 | } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) { |
1304 | if (loglevel != 0) { | |
1305 | fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0); | |
1306 | } | |
e1833e1f JM |
1307 | do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1308 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); | |
a750fc0b JM |
1309 | } |
1310 | } | |
1311 | ||
76a66253 | 1312 | #if !defined(CONFIG_USER_ONLY) |
a42bd6cc | 1313 | void do_40x_rfci (void) |
76a66253 JM |
1314 | { |
1315 | env->nip = env->spr[SPR_40x_SRR2]; | |
a42bd6cc JM |
1316 | do_store_msr(env, env->spr[SPR_40x_SRR3] & ~0xFFFF0000); |
1317 | #if defined (DEBUG_OP) | |
6b80055d | 1318 | cpu_dump_rfi(env->nip, do_load_msr(env)); |
a42bd6cc JM |
1319 | #endif |
1320 | env->interrupt_request = CPU_INTERRUPT_EXITTB; | |
1321 | } | |
1322 | ||
1323 | void do_rfci (void) | |
1324 | { | |
1325 | #if defined(TARGET_PPC64) | |
1326 | if (env->spr[SPR_BOOKE_CSRR1] & (1 << MSR_CM)) { | |
1327 | env->nip = (uint64_t)env->spr[SPR_BOOKE_CSRR0]; | |
1328 | } else | |
1329 | #endif | |
1330 | { | |
1331 | env->nip = (uint32_t)env->spr[SPR_BOOKE_CSRR0]; | |
1332 | } | |
1333 | do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_CSRR1] & ~0x3FFF0000); | |
1334 | #if defined (DEBUG_OP) | |
6b80055d | 1335 | cpu_dump_rfi(env->nip, do_load_msr(env)); |
a42bd6cc JM |
1336 | #endif |
1337 | env->interrupt_request = CPU_INTERRUPT_EXITTB; | |
1338 | } | |
1339 | ||
1340 | void do_rfdi (void) | |
1341 | { | |
1342 | #if defined(TARGET_PPC64) | |
1343 | if (env->spr[SPR_BOOKE_DSRR1] & (1 << MSR_CM)) { | |
1344 | env->nip = (uint64_t)env->spr[SPR_BOOKE_DSRR0]; | |
1345 | } else | |
1346 | #endif | |
1347 | { | |
1348 | env->nip = (uint32_t)env->spr[SPR_BOOKE_DSRR0]; | |
1349 | } | |
1350 | do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_DSRR1] & ~0x3FFF0000); | |
1351 | #if defined (DEBUG_OP) | |
6b80055d | 1352 | cpu_dump_rfi(env->nip, do_load_msr(env)); |
a42bd6cc JM |
1353 | #endif |
1354 | env->interrupt_request = CPU_INTERRUPT_EXITTB; | |
1355 | } | |
1356 | ||
1357 | void do_rfmci (void) | |
1358 | { | |
1359 | #if defined(TARGET_PPC64) | |
1360 | if (env->spr[SPR_BOOKE_MCSRR1] & (1 << MSR_CM)) { | |
1361 | env->nip = (uint64_t)env->spr[SPR_BOOKE_MCSRR0]; | |
1362 | } else | |
1363 | #endif | |
1364 | { | |
1365 | env->nip = (uint32_t)env->spr[SPR_BOOKE_MCSRR0]; | |
1366 | } | |
1367 | do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_MCSRR1] & ~0x3FFF0000); | |
76a66253 | 1368 | #if defined (DEBUG_OP) |
6b80055d | 1369 | cpu_dump_rfi(env->nip, do_load_msr(env)); |
76a66253 JM |
1370 | #endif |
1371 | env->interrupt_request = CPU_INTERRUPT_EXITTB; | |
1372 | } | |
1373 | ||
76a66253 JM |
1374 | void do_load_403_pb (int num) |
1375 | { | |
1376 | T0 = env->pb[num]; | |
1377 | } | |
1378 | ||
1379 | void do_store_403_pb (int num) | |
1380 | { | |
1381 | if (likely(env->pb[num] != T0)) { | |
1382 | env->pb[num] = T0; | |
1383 | /* Should be optimized */ | |
1384 | tlb_flush(env, 1); | |
1385 | } | |
1386 | } | |
1387 | #endif | |
1388 | ||
1389 | /* 440 specific */ | |
1390 | void do_440_dlmzb (void) | |
1391 | { | |
1392 | target_ulong mask; | |
1393 | int i; | |
1394 | ||
1395 | i = 1; | |
1396 | for (mask = 0xFF000000; mask != 0; mask = mask >> 8) { | |
1397 | if ((T0 & mask) == 0) | |
1398 | goto done; | |
1399 | i++; | |
1400 | } | |
1401 | for (mask = 0xFF000000; mask != 0; mask = mask >> 8) { | |
1402 | if ((T1 & mask) == 0) | |
1403 | break; | |
1404 | i++; | |
1405 | } | |
1406 | done: | |
1407 | T0 = i; | |
fdabc366 FB |
1408 | } |
1409 | ||
35cdaad6 | 1410 | #if defined(TARGET_PPCEMB) |
0487d6a8 JM |
1411 | /* SPE extension helpers */ |
1412 | /* Use a table to make this quicker */ | |
1413 | static uint8_t hbrev[16] = { | |
1414 | 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, | |
1415 | 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF, | |
1416 | }; | |
1417 | ||
1418 | static inline uint8_t byte_reverse (uint8_t val) | |
1419 | { | |
1420 | return hbrev[val >> 4] | (hbrev[val & 0xF] << 4); | |
1421 | } | |
1422 | ||
1423 | static inline uint32_t word_reverse (uint32_t val) | |
1424 | { | |
1425 | return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) | | |
1426 | (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24); | |
1427 | } | |
1428 | ||
1429 | #define MASKBITS 16 // Random value - to be fixed | |
1430 | void do_brinc (void) | |
1431 | { | |
1432 | uint32_t a, b, d, mask; | |
1433 | ||
1434 | mask = (uint32_t)(-1UL) >> MASKBITS; | |
1435 | b = T1_64 & mask; | |
1436 | a = T0_64 & mask; | |
1437 | d = word_reverse(1 + word_reverse(a | ~mask)); | |
1438 | T0_64 = (T0_64 & ~mask) | (d & mask); | |
1439 | } | |
1440 | ||
1441 | #define DO_SPE_OP2(name) \ | |
1442 | void do_ev##name (void) \ | |
1443 | { \ | |
1444 | T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \ | |
1445 | (uint64_t)_do_e##name(T0_64, T1_64); \ | |
1446 | } | |
1447 | ||
1448 | #define DO_SPE_OP1(name) \ | |
1449 | void do_ev##name (void) \ | |
1450 | { \ | |
1451 | T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \ | |
1452 | (uint64_t)_do_e##name(T0_64); \ | |
1453 | } | |
1454 | ||
1455 | /* Fixed-point vector arithmetic */ | |
1456 | static inline uint32_t _do_eabs (uint32_t val) | |
1457 | { | |
1458 | if (val != 0x80000000) | |
1459 | val &= ~0x80000000; | |
1460 | ||
1461 | return val; | |
1462 | } | |
1463 | ||
1464 | static inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2) | |
1465 | { | |
1466 | return op1 + op2; | |
1467 | } | |
1468 | ||
1469 | static inline int _do_ecntlsw (uint32_t val) | |
1470 | { | |
1471 | if (val & 0x80000000) | |
1472 | return _do_cntlzw(~val); | |
1473 | else | |
1474 | return _do_cntlzw(val); | |
1475 | } | |
1476 | ||
1477 | static inline int _do_ecntlzw (uint32_t val) | |
1478 | { | |
1479 | return _do_cntlzw(val); | |
1480 | } | |
1481 | ||
1482 | static inline uint32_t _do_eneg (uint32_t val) | |
1483 | { | |
1484 | if (val != 0x80000000) | |
1485 | val ^= 0x80000000; | |
1486 | ||
1487 | return val; | |
1488 | } | |
1489 | ||
1490 | static inline uint32_t _do_erlw (uint32_t op1, uint32_t op2) | |
1491 | { | |
1492 | return rotl32(op1, op2); | |
1493 | } | |
1494 | ||
1495 | static inline uint32_t _do_erndw (uint32_t val) | |
1496 | { | |
1497 | return (val + 0x000080000000) & 0xFFFF0000; | |
1498 | } | |
1499 | ||
1500 | static inline uint32_t _do_eslw (uint32_t op1, uint32_t op2) | |
1501 | { | |
1502 | /* No error here: 6 bits are used */ | |
1503 | return op1 << (op2 & 0x3F); | |
1504 | } | |
1505 | ||
1506 | static inline int32_t _do_esrws (int32_t op1, uint32_t op2) | |
1507 | { | |
1508 | /* No error here: 6 bits are used */ | |
1509 | return op1 >> (op2 & 0x3F); | |
1510 | } | |
1511 | ||
1512 | static inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2) | |
1513 | { | |
1514 | /* No error here: 6 bits are used */ | |
1515 | return op1 >> (op2 & 0x3F); | |
1516 | } | |
1517 | ||
1518 | static inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2) | |
1519 | { | |
1520 | return op2 - op1; | |
1521 | } | |
1522 | ||
1523 | /* evabs */ | |
1524 | DO_SPE_OP1(abs); | |
1525 | /* evaddw */ | |
1526 | DO_SPE_OP2(addw); | |
1527 | /* evcntlsw */ | |
1528 | DO_SPE_OP1(cntlsw); | |
1529 | /* evcntlzw */ | |
1530 | DO_SPE_OP1(cntlzw); | |
1531 | /* evneg */ | |
1532 | DO_SPE_OP1(neg); | |
1533 | /* evrlw */ | |
1534 | DO_SPE_OP2(rlw); | |
1535 | /* evrnd */ | |
1536 | DO_SPE_OP1(rndw); | |
1537 | /* evslw */ | |
1538 | DO_SPE_OP2(slw); | |
1539 | /* evsrws */ | |
1540 | DO_SPE_OP2(srws); | |
1541 | /* evsrwu */ | |
1542 | DO_SPE_OP2(srwu); | |
1543 | /* evsubfw */ | |
1544 | DO_SPE_OP2(subfw); | |
1545 | ||
1546 | /* evsel is a little bit more complicated... */ | |
1547 | static inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n) | |
1548 | { | |
1549 | if (n) | |
1550 | return op1; | |
1551 | else | |
1552 | return op2; | |
1553 | } | |
1554 | ||
1555 | void do_evsel (void) | |
1556 | { | |
1557 | T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) | | |
1558 | (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1); | |
1559 | } | |
1560 | ||
1561 | /* Fixed-point vector comparisons */ | |
1562 | #define DO_SPE_CMP(name) \ | |
1563 | void do_ev##name (void) \ | |
1564 | { \ | |
1565 | T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \ | |
1566 | T1_64 >> 32) << 32, \ | |
1567 | _do_e##name(T0_64, T1_64)); \ | |
1568 | } | |
1569 | ||
1570 | static inline uint32_t _do_evcmp_merge (int t0, int t1) | |
1571 | { | |
1572 | return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1); | |
1573 | } | |
1574 | static inline int _do_ecmpeq (uint32_t op1, uint32_t op2) | |
1575 | { | |
1576 | return op1 == op2 ? 1 : 0; | |
1577 | } | |
1578 | ||
1579 | static inline int _do_ecmpgts (int32_t op1, int32_t op2) | |
1580 | { | |
1581 | return op1 > op2 ? 1 : 0; | |
1582 | } | |
1583 | ||
1584 | static inline int _do_ecmpgtu (uint32_t op1, uint32_t op2) | |
1585 | { | |
1586 | return op1 > op2 ? 1 : 0; | |
1587 | } | |
1588 | ||
1589 | static inline int _do_ecmplts (int32_t op1, int32_t op2) | |
1590 | { | |
1591 | return op1 < op2 ? 1 : 0; | |
1592 | } | |
1593 | ||
1594 | static inline int _do_ecmpltu (uint32_t op1, uint32_t op2) | |
1595 | { | |
1596 | return op1 < op2 ? 1 : 0; | |
1597 | } | |
1598 | ||
1599 | /* evcmpeq */ | |
1600 | DO_SPE_CMP(cmpeq); | |
1601 | /* evcmpgts */ | |
1602 | DO_SPE_CMP(cmpgts); | |
1603 | /* evcmpgtu */ | |
1604 | DO_SPE_CMP(cmpgtu); | |
1605 | /* evcmplts */ | |
1606 | DO_SPE_CMP(cmplts); | |
1607 | /* evcmpltu */ | |
1608 | DO_SPE_CMP(cmpltu); | |
1609 | ||
1610 | /* Single precision floating-point conversions from/to integer */ | |
1611 | static inline uint32_t _do_efscfsi (int32_t val) | |
1612 | { | |
1613 | union { | |
1614 | uint32_t u; | |
1615 | float32 f; | |
1616 | } u; | |
1617 | ||
1618 | u.f = int32_to_float32(val, &env->spe_status); | |
1619 | ||
1620 | return u.u; | |
1621 | } | |
1622 | ||
1623 | static inline uint32_t _do_efscfui (uint32_t val) | |
1624 | { | |
1625 | union { | |
1626 | uint32_t u; | |
1627 | float32 f; | |
1628 | } u; | |
1629 | ||
1630 | u.f = uint32_to_float32(val, &env->spe_status); | |
1631 | ||
1632 | return u.u; | |
1633 | } | |
1634 | ||
1635 | static inline int32_t _do_efsctsi (uint32_t val) | |
1636 | { | |
1637 | union { | |
1638 | int32_t u; | |
1639 | float32 f; | |
1640 | } u; | |
1641 | ||
1642 | u.u = val; | |
1643 | /* NaN are not treated the same way IEEE 754 does */ | |
1644 | if (unlikely(isnan(u.f))) | |
1645 | return 0; | |
1646 | ||
1647 | return float32_to_int32(u.f, &env->spe_status); | |
1648 | } | |
1649 | ||
1650 | static inline uint32_t _do_efsctui (uint32_t val) | |
1651 | { | |
1652 | union { | |
1653 | int32_t u; | |
1654 | float32 f; | |
1655 | } u; | |
1656 | ||
1657 | u.u = val; | |
1658 | /* NaN are not treated the same way IEEE 754 does */ | |
1659 | if (unlikely(isnan(u.f))) | |
1660 | return 0; | |
1661 | ||
1662 | return float32_to_uint32(u.f, &env->spe_status); | |
1663 | } | |
1664 | ||
1665 | static inline int32_t _do_efsctsiz (uint32_t val) | |
1666 | { | |
1667 | union { | |
1668 | int32_t u; | |
1669 | float32 f; | |
1670 | } u; | |
1671 | ||
1672 | u.u = val; | |
1673 | /* NaN are not treated the same way IEEE 754 does */ | |
1674 | if (unlikely(isnan(u.f))) | |
1675 | return 0; | |
1676 | ||
1677 | return float32_to_int32_round_to_zero(u.f, &env->spe_status); | |
1678 | } | |
1679 | ||
1680 | static inline uint32_t _do_efsctuiz (uint32_t val) | |
1681 | { | |
1682 | union { | |
1683 | int32_t u; | |
1684 | float32 f; | |
1685 | } u; | |
1686 | ||
1687 | u.u = val; | |
1688 | /* NaN are not treated the same way IEEE 754 does */ | |
1689 | if (unlikely(isnan(u.f))) | |
1690 | return 0; | |
1691 | ||
1692 | return float32_to_uint32_round_to_zero(u.f, &env->spe_status); | |
1693 | } | |
1694 | ||
1695 | void do_efscfsi (void) | |
1696 | { | |
1697 | T0_64 = _do_efscfsi(T0_64); | |
1698 | } | |
1699 | ||
1700 | void do_efscfui (void) | |
1701 | { | |
1702 | T0_64 = _do_efscfui(T0_64); | |
1703 | } | |
1704 | ||
1705 | void do_efsctsi (void) | |
1706 | { | |
1707 | T0_64 = _do_efsctsi(T0_64); | |
1708 | } | |
1709 | ||
1710 | void do_efsctui (void) | |
1711 | { | |
1712 | T0_64 = _do_efsctui(T0_64); | |
1713 | } | |
1714 | ||
1715 | void do_efsctsiz (void) | |
1716 | { | |
1717 | T0_64 = _do_efsctsiz(T0_64); | |
1718 | } | |
1719 | ||
1720 | void do_efsctuiz (void) | |
1721 | { | |
1722 | T0_64 = _do_efsctuiz(T0_64); | |
1723 | } | |
1724 | ||
1725 | /* Single precision floating-point conversion to/from fractional */ | |
1726 | static inline uint32_t _do_efscfsf (uint32_t val) | |
1727 | { | |
1728 | union { | |
1729 | uint32_t u; | |
1730 | float32 f; | |
1731 | } u; | |
1732 | float32 tmp; | |
1733 | ||
1734 | u.f = int32_to_float32(val, &env->spe_status); | |
1735 | tmp = int64_to_float32(1ULL << 32, &env->spe_status); | |
1736 | u.f = float32_div(u.f, tmp, &env->spe_status); | |
1737 | ||
1738 | return u.u; | |
1739 | } | |
1740 | ||
1741 | static inline uint32_t _do_efscfuf (uint32_t val) | |
1742 | { | |
1743 | union { | |
1744 | uint32_t u; | |
1745 | float32 f; | |
1746 | } u; | |
1747 | float32 tmp; | |
1748 | ||
1749 | u.f = uint32_to_float32(val, &env->spe_status); | |
1750 | tmp = uint64_to_float32(1ULL << 32, &env->spe_status); | |
1751 | u.f = float32_div(u.f, tmp, &env->spe_status); | |
1752 | ||
1753 | return u.u; | |
1754 | } | |
1755 | ||
1756 | static inline int32_t _do_efsctsf (uint32_t val) | |
1757 | { | |
1758 | union { | |
1759 | int32_t u; | |
1760 | float32 f; | |
1761 | } u; | |
1762 | float32 tmp; | |
1763 | ||
1764 | u.u = val; | |
1765 | /* NaN are not treated the same way IEEE 754 does */ | |
1766 | if (unlikely(isnan(u.f))) | |
1767 | return 0; | |
1768 | tmp = uint64_to_float32(1ULL << 32, &env->spe_status); | |
1769 | u.f = float32_mul(u.f, tmp, &env->spe_status); | |
1770 | ||
1771 | return float32_to_int32(u.f, &env->spe_status); | |
1772 | } | |
1773 | ||
1774 | static inline uint32_t _do_efsctuf (uint32_t val) | |
1775 | { | |
1776 | union { | |
1777 | int32_t u; | |
1778 | float32 f; | |
1779 | } u; | |
1780 | float32 tmp; | |
1781 | ||
1782 | u.u = val; | |
1783 | /* NaN are not treated the same way IEEE 754 does */ | |
1784 | if (unlikely(isnan(u.f))) | |
1785 | return 0; | |
1786 | tmp = uint64_to_float32(1ULL << 32, &env->spe_status); | |
1787 | u.f = float32_mul(u.f, tmp, &env->spe_status); | |
1788 | ||
1789 | return float32_to_uint32(u.f, &env->spe_status); | |
1790 | } | |
1791 | ||
1792 | static inline int32_t _do_efsctsfz (uint32_t val) | |
1793 | { | |
1794 | union { | |
1795 | int32_t u; | |
1796 | float32 f; | |
1797 | } u; | |
1798 | float32 tmp; | |
1799 | ||
1800 | u.u = val; | |
1801 | /* NaN are not treated the same way IEEE 754 does */ | |
1802 | if (unlikely(isnan(u.f))) | |
1803 | return 0; | |
1804 | tmp = uint64_to_float32(1ULL << 32, &env->spe_status); | |
1805 | u.f = float32_mul(u.f, tmp, &env->spe_status); | |
1806 | ||
1807 | return float32_to_int32_round_to_zero(u.f, &env->spe_status); | |
1808 | } | |
1809 | ||
1810 | static inline uint32_t _do_efsctufz (uint32_t val) | |
1811 | { | |
1812 | union { | |
1813 | int32_t u; | |
1814 | float32 f; | |
1815 | } u; | |
1816 | float32 tmp; | |
1817 | ||
1818 | u.u = val; | |
1819 | /* NaN are not treated the same way IEEE 754 does */ | |
1820 | if (unlikely(isnan(u.f))) | |
1821 | return 0; | |
1822 | tmp = uint64_to_float32(1ULL << 32, &env->spe_status); | |
1823 | u.f = float32_mul(u.f, tmp, &env->spe_status); | |
1824 | ||
1825 | return float32_to_uint32_round_to_zero(u.f, &env->spe_status); | |
1826 | } | |
1827 | ||
1828 | void do_efscfsf (void) | |
1829 | { | |
1830 | T0_64 = _do_efscfsf(T0_64); | |
1831 | } | |
1832 | ||
1833 | void do_efscfuf (void) | |
1834 | { | |
1835 | T0_64 = _do_efscfuf(T0_64); | |
1836 | } | |
1837 | ||
1838 | void do_efsctsf (void) | |
1839 | { | |
1840 | T0_64 = _do_efsctsf(T0_64); | |
1841 | } | |
1842 | ||
1843 | void do_efsctuf (void) | |
1844 | { | |
1845 | T0_64 = _do_efsctuf(T0_64); | |
1846 | } | |
1847 | ||
1848 | void do_efsctsfz (void) | |
1849 | { | |
1850 | T0_64 = _do_efsctsfz(T0_64); | |
1851 | } | |
1852 | ||
1853 | void do_efsctufz (void) | |
1854 | { | |
1855 | T0_64 = _do_efsctufz(T0_64); | |
1856 | } | |
1857 | ||
1858 | /* Double precision floating point helpers */ | |
1859 | static inline int _do_efdcmplt (uint64_t op1, uint64_t op2) | |
1860 | { | |
1861 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
1862 | return _do_efdtstlt(op1, op2); | |
1863 | } | |
1864 | ||
1865 | static inline int _do_efdcmpgt (uint64_t op1, uint64_t op2) | |
1866 | { | |
1867 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
1868 | return _do_efdtstgt(op1, op2); | |
1869 | } | |
1870 | ||
1871 | static inline int _do_efdcmpeq (uint64_t op1, uint64_t op2) | |
1872 | { | |
1873 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
1874 | return _do_efdtsteq(op1, op2); | |
1875 | } | |
1876 | ||
1877 | void do_efdcmplt (void) | |
1878 | { | |
1879 | T0 = _do_efdcmplt(T0_64, T1_64); | |
1880 | } | |
1881 | ||
1882 | void do_efdcmpgt (void) | |
1883 | { | |
1884 | T0 = _do_efdcmpgt(T0_64, T1_64); | |
1885 | } | |
1886 | ||
1887 | void do_efdcmpeq (void) | |
1888 | { | |
1889 | T0 = _do_efdcmpeq(T0_64, T1_64); | |
1890 | } | |
1891 | ||
1892 | /* Double precision floating-point conversion to/from integer */ | |
1893 | static inline uint64_t _do_efdcfsi (int64_t val) | |
1894 | { | |
1895 | union { | |
1896 | uint64_t u; | |
1897 | float64 f; | |
1898 | } u; | |
1899 | ||
1900 | u.f = int64_to_float64(val, &env->spe_status); | |
1901 | ||
1902 | return u.u; | |
1903 | } | |
1904 | ||
1905 | static inline uint64_t _do_efdcfui (uint64_t val) | |
1906 | { | |
1907 | union { | |
1908 | uint64_t u; | |
1909 | float64 f; | |
1910 | } u; | |
1911 | ||
1912 | u.f = uint64_to_float64(val, &env->spe_status); | |
1913 | ||
1914 | return u.u; | |
1915 | } | |
1916 | ||
1917 | static inline int64_t _do_efdctsi (uint64_t val) | |
1918 | { | |
1919 | union { | |
1920 | int64_t u; | |
1921 | float64 f; | |
1922 | } u; | |
1923 | ||
1924 | u.u = val; | |
1925 | /* NaN are not treated the same way IEEE 754 does */ | |
1926 | if (unlikely(isnan(u.f))) | |
1927 | return 0; | |
1928 | ||
1929 | return float64_to_int64(u.f, &env->spe_status); | |
1930 | } | |
1931 | ||
1932 | static inline uint64_t _do_efdctui (uint64_t val) | |
1933 | { | |
1934 | union { | |
1935 | int64_t u; | |
1936 | float64 f; | |
1937 | } u; | |
1938 | ||
1939 | u.u = val; | |
1940 | /* NaN are not treated the same way IEEE 754 does */ | |
1941 | if (unlikely(isnan(u.f))) | |
1942 | return 0; | |
1943 | ||
1944 | return float64_to_uint64(u.f, &env->spe_status); | |
1945 | } | |
1946 | ||
1947 | static inline int64_t _do_efdctsiz (uint64_t val) | |
1948 | { | |
1949 | union { | |
1950 | int64_t u; | |
1951 | float64 f; | |
1952 | } u; | |
1953 | ||
1954 | u.u = val; | |
1955 | /* NaN are not treated the same way IEEE 754 does */ | |
1956 | if (unlikely(isnan(u.f))) | |
1957 | return 0; | |
1958 | ||
1959 | return float64_to_int64_round_to_zero(u.f, &env->spe_status); | |
1960 | } | |
1961 | ||
1962 | static inline uint64_t _do_efdctuiz (uint64_t val) | |
1963 | { | |
1964 | union { | |
1965 | int64_t u; | |
1966 | float64 f; | |
1967 | } u; | |
1968 | ||
1969 | u.u = val; | |
1970 | /* NaN are not treated the same way IEEE 754 does */ | |
1971 | if (unlikely(isnan(u.f))) | |
1972 | return 0; | |
1973 | ||
1974 | return float64_to_uint64_round_to_zero(u.f, &env->spe_status); | |
1975 | } | |
1976 | ||
1977 | void do_efdcfsi (void) | |
1978 | { | |
1979 | T0_64 = _do_efdcfsi(T0_64); | |
1980 | } | |
1981 | ||
1982 | void do_efdcfui (void) | |
1983 | { | |
1984 | T0_64 = _do_efdcfui(T0_64); | |
1985 | } | |
1986 | ||
1987 | void do_efdctsi (void) | |
1988 | { | |
1989 | T0_64 = _do_efdctsi(T0_64); | |
1990 | } | |
1991 | ||
1992 | void do_efdctui (void) | |
1993 | { | |
1994 | T0_64 = _do_efdctui(T0_64); | |
1995 | } | |
1996 | ||
1997 | void do_efdctsiz (void) | |
1998 | { | |
1999 | T0_64 = _do_efdctsiz(T0_64); | |
2000 | } | |
2001 | ||
2002 | void do_efdctuiz (void) | |
2003 | { | |
2004 | T0_64 = _do_efdctuiz(T0_64); | |
2005 | } | |
2006 | ||
2007 | /* Double precision floating-point conversion to/from fractional */ | |
2008 | static inline uint64_t _do_efdcfsf (int64_t val) | |
2009 | { | |
2010 | union { | |
2011 | uint64_t u; | |
2012 | float64 f; | |
2013 | } u; | |
2014 | float64 tmp; | |
2015 | ||
2016 | u.f = int32_to_float64(val, &env->spe_status); | |
2017 | tmp = int64_to_float64(1ULL << 32, &env->spe_status); | |
2018 | u.f = float64_div(u.f, tmp, &env->spe_status); | |
2019 | ||
2020 | return u.u; | |
2021 | } | |
2022 | ||
2023 | static inline uint64_t _do_efdcfuf (uint64_t val) | |
2024 | { | |
2025 | union { | |
2026 | uint64_t u; | |
2027 | float64 f; | |
2028 | } u; | |
2029 | float64 tmp; | |
2030 | ||
2031 | u.f = uint32_to_float64(val, &env->spe_status); | |
2032 | tmp = int64_to_float64(1ULL << 32, &env->spe_status); | |
2033 | u.f = float64_div(u.f, tmp, &env->spe_status); | |
2034 | ||
2035 | return u.u; | |
2036 | } | |
2037 | ||
2038 | static inline int64_t _do_efdctsf (uint64_t val) | |
2039 | { | |
2040 | union { | |
2041 | int64_t u; | |
2042 | float64 f; | |
2043 | } u; | |
2044 | float64 tmp; | |
2045 | ||
2046 | u.u = val; | |
2047 | /* NaN are not treated the same way IEEE 754 does */ | |
2048 | if (unlikely(isnan(u.f))) | |
2049 | return 0; | |
2050 | tmp = uint64_to_float64(1ULL << 32, &env->spe_status); | |
2051 | u.f = float64_mul(u.f, tmp, &env->spe_status); | |
2052 | ||
2053 | return float64_to_int32(u.f, &env->spe_status); | |
2054 | } | |
2055 | ||
2056 | static inline uint64_t _do_efdctuf (uint64_t val) | |
2057 | { | |
2058 | union { | |
2059 | int64_t u; | |
2060 | float64 f; | |
2061 | } u; | |
2062 | float64 tmp; | |
2063 | ||
2064 | u.u = val; | |
2065 | /* NaN are not treated the same way IEEE 754 does */ | |
2066 | if (unlikely(isnan(u.f))) | |
2067 | return 0; | |
2068 | tmp = uint64_to_float64(1ULL << 32, &env->spe_status); | |
2069 | u.f = float64_mul(u.f, tmp, &env->spe_status); | |
2070 | ||
2071 | return float64_to_uint32(u.f, &env->spe_status); | |
2072 | } | |
2073 | ||
2074 | static inline int64_t _do_efdctsfz (uint64_t val) | |
2075 | { | |
2076 | union { | |
2077 | int64_t u; | |
2078 | float64 f; | |
2079 | } u; | |
2080 | float64 tmp; | |
2081 | ||
2082 | u.u = val; | |
2083 | /* NaN are not treated the same way IEEE 754 does */ | |
2084 | if (unlikely(isnan(u.f))) | |
2085 | return 0; | |
2086 | tmp = uint64_to_float64(1ULL << 32, &env->spe_status); | |
2087 | u.f = float64_mul(u.f, tmp, &env->spe_status); | |
2088 | ||
2089 | return float64_to_int32_round_to_zero(u.f, &env->spe_status); | |
2090 | } | |
2091 | ||
2092 | static inline uint64_t _do_efdctufz (uint64_t val) | |
2093 | { | |
2094 | union { | |
2095 | int64_t u; | |
2096 | float64 f; | |
2097 | } u; | |
2098 | float64 tmp; | |
2099 | ||
2100 | u.u = val; | |
2101 | /* NaN are not treated the same way IEEE 754 does */ | |
2102 | if (unlikely(isnan(u.f))) | |
2103 | return 0; | |
2104 | tmp = uint64_to_float64(1ULL << 32, &env->spe_status); | |
2105 | u.f = float64_mul(u.f, tmp, &env->spe_status); | |
2106 | ||
2107 | return float64_to_uint32_round_to_zero(u.f, &env->spe_status); | |
2108 | } | |
2109 | ||
2110 | void do_efdcfsf (void) | |
2111 | { | |
2112 | T0_64 = _do_efdcfsf(T0_64); | |
2113 | } | |
2114 | ||
2115 | void do_efdcfuf (void) | |
2116 | { | |
2117 | T0_64 = _do_efdcfuf(T0_64); | |
2118 | } | |
2119 | ||
2120 | void do_efdctsf (void) | |
2121 | { | |
2122 | T0_64 = _do_efdctsf(T0_64); | |
2123 | } | |
2124 | ||
2125 | void do_efdctuf (void) | |
2126 | { | |
2127 | T0_64 = _do_efdctuf(T0_64); | |
2128 | } | |
2129 | ||
2130 | void do_efdctsfz (void) | |
2131 | { | |
2132 | T0_64 = _do_efdctsfz(T0_64); | |
2133 | } | |
2134 | ||
2135 | void do_efdctufz (void) | |
2136 | { | |
2137 | T0_64 = _do_efdctufz(T0_64); | |
2138 | } | |
2139 | ||
2140 | /* Floating point conversion between single and double precision */ | |
2141 | static inline uint32_t _do_efscfd (uint64_t val) | |
2142 | { | |
2143 | union { | |
2144 | uint64_t u; | |
2145 | float64 f; | |
2146 | } u1; | |
2147 | union { | |
2148 | uint32_t u; | |
2149 | float32 f; | |
2150 | } u2; | |
2151 | ||
2152 | u1.u = val; | |
2153 | u2.f = float64_to_float32(u1.f, &env->spe_status); | |
2154 | ||
2155 | return u2.u; | |
2156 | } | |
2157 | ||
2158 | static inline uint64_t _do_efdcfs (uint32_t val) | |
2159 | { | |
2160 | union { | |
2161 | uint64_t u; | |
2162 | float64 f; | |
2163 | } u2; | |
2164 | union { | |
2165 | uint32_t u; | |
2166 | float32 f; | |
2167 | } u1; | |
2168 | ||
2169 | u1.u = val; | |
2170 | u2.f = float32_to_float64(u1.f, &env->spe_status); | |
2171 | ||
2172 | return u2.u; | |
2173 | } | |
2174 | ||
2175 | void do_efscfd (void) | |
2176 | { | |
2177 | T0_64 = _do_efscfd(T0_64); | |
2178 | } | |
2179 | ||
2180 | void do_efdcfs (void) | |
2181 | { | |
2182 | T0_64 = _do_efdcfs(T0_64); | |
2183 | } | |
2184 | ||
2185 | /* Single precision fixed-point vector arithmetic */ | |
2186 | /* evfsabs */ | |
2187 | DO_SPE_OP1(fsabs); | |
2188 | /* evfsnabs */ | |
2189 | DO_SPE_OP1(fsnabs); | |
2190 | /* evfsneg */ | |
2191 | DO_SPE_OP1(fsneg); | |
2192 | /* evfsadd */ | |
2193 | DO_SPE_OP2(fsadd); | |
2194 | /* evfssub */ | |
2195 | DO_SPE_OP2(fssub); | |
2196 | /* evfsmul */ | |
2197 | DO_SPE_OP2(fsmul); | |
2198 | /* evfsdiv */ | |
2199 | DO_SPE_OP2(fsdiv); | |
2200 | ||
2201 | /* Single-precision floating-point comparisons */ | |
2202 | static inline int _do_efscmplt (uint32_t op1, uint32_t op2) | |
2203 | { | |
2204 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
2205 | return _do_efststlt(op1, op2); | |
2206 | } | |
2207 | ||
2208 | static inline int _do_efscmpgt (uint32_t op1, uint32_t op2) | |
2209 | { | |
2210 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
2211 | return _do_efststgt(op1, op2); | |
2212 | } | |
2213 | ||
2214 | static inline int _do_efscmpeq (uint32_t op1, uint32_t op2) | |
2215 | { | |
2216 | /* XXX: TODO: test special values (NaN, infinites, ...) */ | |
2217 | return _do_efststeq(op1, op2); | |
2218 | } | |
2219 | ||
2220 | void do_efscmplt (void) | |
2221 | { | |
2222 | T0 = _do_efscmplt(T0_64, T1_64); | |
2223 | } | |
2224 | ||
2225 | void do_efscmpgt (void) | |
2226 | { | |
2227 | T0 = _do_efscmpgt(T0_64, T1_64); | |
2228 | } | |
2229 | ||
2230 | void do_efscmpeq (void) | |
2231 | { | |
2232 | T0 = _do_efscmpeq(T0_64, T1_64); | |
2233 | } | |
2234 | ||
2235 | /* Single-precision floating-point vector comparisons */ | |
2236 | /* evfscmplt */ | |
2237 | DO_SPE_CMP(fscmplt); | |
2238 | /* evfscmpgt */ | |
2239 | DO_SPE_CMP(fscmpgt); | |
2240 | /* evfscmpeq */ | |
2241 | DO_SPE_CMP(fscmpeq); | |
2242 | /* evfststlt */ | |
2243 | DO_SPE_CMP(fststlt); | |
2244 | /* evfststgt */ | |
2245 | DO_SPE_CMP(fststgt); | |
2246 | /* evfststeq */ | |
2247 | DO_SPE_CMP(fststeq); | |
2248 | ||
2249 | /* Single-precision floating-point vector conversions */ | |
2250 | /* evfscfsi */ | |
2251 | DO_SPE_OP1(fscfsi); | |
2252 | /* evfscfui */ | |
2253 | DO_SPE_OP1(fscfui); | |
2254 | /* evfscfuf */ | |
2255 | DO_SPE_OP1(fscfuf); | |
2256 | /* evfscfsf */ | |
2257 | DO_SPE_OP1(fscfsf); | |
2258 | /* evfsctsi */ | |
2259 | DO_SPE_OP1(fsctsi); | |
2260 | /* evfsctui */ | |
2261 | DO_SPE_OP1(fsctui); | |
2262 | /* evfsctsiz */ | |
2263 | DO_SPE_OP1(fsctsiz); | |
2264 | /* evfsctuiz */ | |
2265 | DO_SPE_OP1(fsctuiz); | |
2266 | /* evfsctsf */ | |
2267 | DO_SPE_OP1(fsctsf); | |
2268 | /* evfsctuf */ | |
2269 | DO_SPE_OP1(fsctuf); | |
35cdaad6 | 2270 | #endif /* defined(TARGET_PPCEMB) */ |
0487d6a8 | 2271 | |
fdabc366 FB |
2272 | /*****************************************************************************/ |
2273 | /* Softmmu support */ | |
2274 | #if !defined (CONFIG_USER_ONLY) | |
2275 | ||
2276 | #define MMUSUFFIX _mmu | |
2277 | #define GETPC() (__builtin_return_address(0)) | |
2278 | ||
2279 | #define SHIFT 0 | |
2280 | #include "softmmu_template.h" | |
2281 | ||
2282 | #define SHIFT 1 | |
2283 | #include "softmmu_template.h" | |
2284 | ||
2285 | #define SHIFT 2 | |
2286 | #include "softmmu_template.h" | |
2287 | ||
2288 | #define SHIFT 3 | |
2289 | #include "softmmu_template.h" | |
2290 | ||
2291 | /* try to fill the TLB and return an exception if error. If retaddr is | |
2292 | NULL, it means that the function was called in C code (i.e. not | |
2293 | from generated code or from helper.c) */ | |
2294 | /* XXX: fix it to restore all registers */ | |
2295 | void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) | |
2296 | { | |
2297 | TranslationBlock *tb; | |
2298 | CPUState *saved_env; | |
2299 | target_phys_addr_t pc; | |
2300 | int ret; | |
2301 | ||
2302 | /* XXX: hack to restore env in all cases, even if not called from | |
2303 | generated code */ | |
2304 | saved_env = env; | |
2305 | env = cpu_single_env; | |
2306 | ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1); | |
76a66253 | 2307 | if (unlikely(ret != 0)) { |
fdabc366 FB |
2308 | if (likely(retaddr)) { |
2309 | /* now we have a real cpu fault */ | |
a750fc0b | 2310 | pc = (target_phys_addr_t)(unsigned long)retaddr; |
fdabc366 FB |
2311 | tb = tb_find_pc(pc); |
2312 | if (likely(tb)) { | |
2313 | /* the PC is inside the translated code. It means that we have | |
2314 | a virtual CPU fault */ | |
2315 | cpu_restore_state(tb, env, pc, NULL); | |
76a66253 | 2316 | } |
fdabc366 FB |
2317 | } |
2318 | do_raise_exception_err(env->exception_index, env->error_code); | |
2319 | } | |
2320 | env = saved_env; | |
9a64fbe4 FB |
2321 | } |
2322 | ||
76a66253 JM |
2323 | /* TLB invalidation helpers */ |
2324 | void do_tlbia (void) | |
2325 | { | |
0a032cbe | 2326 | ppc_tlb_invalidate_all(env); |
76a66253 JM |
2327 | } |
2328 | ||
2329 | void do_tlbie (void) | |
2330 | { | |
d9bce9d9 | 2331 | T0 = (uint32_t)T0; |
76a66253 | 2332 | #if !defined(FLUSH_ALL_TLBS) |
a750fc0b JM |
2333 | /* XXX: Remove thoses tests */ |
2334 | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) { | |
76a66253 JM |
2335 | ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0); |
2336 | if (env->id_tlbs == 1) | |
2337 | ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1); | |
a750fc0b JM |
2338 | } else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) { |
2339 | ppc4xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, | |
2340 | env->spr[SPR_40x_PID]); | |
76a66253 JM |
2341 | } else { |
2342 | /* tlbie invalidate TLBs for all segments */ | |
2343 | T0 &= TARGET_PAGE_MASK; | |
2344 | T0 &= ~((target_ulong)-1 << 28); | |
2345 | /* XXX: this case should be optimized, | |
2346 | * giving a mask to tlb_flush_page | |
2347 | */ | |
2348 | tlb_flush_page(env, T0 | (0x0 << 28)); | |
2349 | tlb_flush_page(env, T0 | (0x1 << 28)); | |
2350 | tlb_flush_page(env, T0 | (0x2 << 28)); | |
2351 | tlb_flush_page(env, T0 | (0x3 << 28)); | |
2352 | tlb_flush_page(env, T0 | (0x4 << 28)); | |
2353 | tlb_flush_page(env, T0 | (0x5 << 28)); | |
2354 | tlb_flush_page(env, T0 | (0x6 << 28)); | |
2355 | tlb_flush_page(env, T0 | (0x7 << 28)); | |
2356 | tlb_flush_page(env, T0 | (0x8 << 28)); | |
2357 | tlb_flush_page(env, T0 | (0x9 << 28)); | |
2358 | tlb_flush_page(env, T0 | (0xA << 28)); | |
2359 | tlb_flush_page(env, T0 | (0xB << 28)); | |
2360 | tlb_flush_page(env, T0 | (0xC << 28)); | |
2361 | tlb_flush_page(env, T0 | (0xD << 28)); | |
2362 | tlb_flush_page(env, T0 | (0xE << 28)); | |
2363 | tlb_flush_page(env, T0 | (0xF << 28)); | |
2364 | } | |
2365 | #else | |
2366 | do_tlbia(); | |
2367 | #endif | |
2368 | } | |
2369 | ||
d9bce9d9 JM |
2370 | #if defined(TARGET_PPC64) |
2371 | void do_tlbie_64 (void) | |
2372 | { | |
2373 | T0 = (uint64_t)T0; | |
2374 | #if !defined(FLUSH_ALL_TLBS) | |
a750fc0b | 2375 | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) { |
d9bce9d9 JM |
2376 | ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 0); |
2377 | if (env->id_tlbs == 1) | |
2378 | ppc6xx_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, 1); | |
a750fc0b | 2379 | } else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) { |
d9bce9d9 JM |
2380 | /* XXX: TODO */ |
2381 | #if 0 | |
2382 | ppcbooke_tlb_invalidate_virt(env, T0 & TARGET_PAGE_MASK, | |
2383 | env->spr[SPR_BOOKE_PID]); | |
2384 | #endif | |
2385 | } else { | |
2386 | /* tlbie invalidate TLBs for all segments | |
2387 | * As we have 2^36 segments, invalidate all qemu TLBs | |
2388 | */ | |
2389 | #if 0 | |
2390 | T0 &= TARGET_PAGE_MASK; | |
2391 | T0 &= ~((target_ulong)-1 << 28); | |
2392 | /* XXX: this case should be optimized, | |
2393 | * giving a mask to tlb_flush_page | |
2394 | */ | |
2395 | tlb_flush_page(env, T0 | (0x0 << 28)); | |
2396 | tlb_flush_page(env, T0 | (0x1 << 28)); | |
2397 | tlb_flush_page(env, T0 | (0x2 << 28)); | |
2398 | tlb_flush_page(env, T0 | (0x3 << 28)); | |
2399 | tlb_flush_page(env, T0 | (0x4 << 28)); | |
2400 | tlb_flush_page(env, T0 | (0x5 << 28)); | |
2401 | tlb_flush_page(env, T0 | (0x6 << 28)); | |
2402 | tlb_flush_page(env, T0 | (0x7 << 28)); | |
2403 | tlb_flush_page(env, T0 | (0x8 << 28)); | |
2404 | tlb_flush_page(env, T0 | (0x9 << 28)); | |
2405 | tlb_flush_page(env, T0 | (0xA << 28)); | |
2406 | tlb_flush_page(env, T0 | (0xB << 28)); | |
2407 | tlb_flush_page(env, T0 | (0xC << 28)); | |
2408 | tlb_flush_page(env, T0 | (0xD << 28)); | |
2409 | tlb_flush_page(env, T0 | (0xE << 28)); | |
2410 | tlb_flush_page(env, T0 | (0xF << 28)); | |
2411 | #else | |
2412 | tlb_flush(env, 1); | |
2413 | #endif | |
2414 | } | |
2415 | #else | |
2416 | do_tlbia(); | |
2417 | #endif | |
2418 | } | |
2419 | #endif | |
2420 | ||
2421 | #if defined(TARGET_PPC64) | |
2422 | void do_slbia (void) | |
2423 | { | |
2424 | /* XXX: TODO */ | |
2425 | tlb_flush(env, 1); | |
2426 | } | |
2427 | ||
2428 | void do_slbie (void) | |
2429 | { | |
2430 | /* XXX: TODO */ | |
2431 | tlb_flush(env, 1); | |
2432 | } | |
2433 | #endif | |
2434 | ||
76a66253 JM |
2435 | /* Software driven TLBs management */ |
2436 | /* PowerPC 602/603 software TLB load instructions helpers */ | |
2437 | void do_load_6xx_tlb (int is_code) | |
2438 | { | |
2439 | target_ulong RPN, CMP, EPN; | |
2440 | int way; | |
d9bce9d9 | 2441 | |
76a66253 JM |
2442 | RPN = env->spr[SPR_RPA]; |
2443 | if (is_code) { | |
2444 | CMP = env->spr[SPR_ICMP]; | |
2445 | EPN = env->spr[SPR_IMISS]; | |
2446 | } else { | |
2447 | CMP = env->spr[SPR_DCMP]; | |
2448 | EPN = env->spr[SPR_DMISS]; | |
2449 | } | |
2450 | way = (env->spr[SPR_SRR1] >> 17) & 1; | |
2451 | #if defined (DEBUG_SOFTWARE_TLB) | |
2452 | if (loglevel != 0) { | |
2453 | fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n", | |
2454 | __func__, (unsigned long)T0, (unsigned long)EPN, | |
2455 | (unsigned long)CMP, (unsigned long)RPN, way); | |
2456 | } | |
2457 | #endif | |
2458 | /* Store this TLB */ | |
d9bce9d9 JM |
2459 | ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK), |
2460 | way, is_code, CMP, RPN); | |
76a66253 JM |
2461 | } |
2462 | ||
a8dea12f JM |
2463 | static target_ulong booke_tlb_to_page_size (int size) |
2464 | { | |
2465 | return 1024 << (2 * size); | |
2466 | } | |
2467 | ||
2468 | static int booke_page_size_to_tlb (target_ulong page_size) | |
2469 | { | |
2470 | int size; | |
2471 | ||
2472 | switch (page_size) { | |
2473 | case 0x00000400UL: | |
2474 | size = 0x0; | |
2475 | break; | |
2476 | case 0x00001000UL: | |
2477 | size = 0x1; | |
2478 | break; | |
2479 | case 0x00004000UL: | |
2480 | size = 0x2; | |
2481 | break; | |
2482 | case 0x00010000UL: | |
2483 | size = 0x3; | |
2484 | break; | |
2485 | case 0x00040000UL: | |
2486 | size = 0x4; | |
2487 | break; | |
2488 | case 0x00100000UL: | |
2489 | size = 0x5; | |
2490 | break; | |
2491 | case 0x00400000UL: | |
2492 | size = 0x6; | |
2493 | break; | |
2494 | case 0x01000000UL: | |
2495 | size = 0x7; | |
2496 | break; | |
2497 | case 0x04000000UL: | |
2498 | size = 0x8; | |
2499 | break; | |
2500 | case 0x10000000UL: | |
2501 | size = 0x9; | |
2502 | break; | |
2503 | case 0x40000000UL: | |
2504 | size = 0xA; | |
2505 | break; | |
2506 | #if defined (TARGET_PPC64) | |
2507 | case 0x000100000000ULL: | |
2508 | size = 0xB; | |
2509 | break; | |
2510 | case 0x000400000000ULL: | |
2511 | size = 0xC; | |
2512 | break; | |
2513 | case 0x001000000000ULL: | |
2514 | size = 0xD; | |
2515 | break; | |
2516 | case 0x004000000000ULL: | |
2517 | size = 0xE; | |
2518 | break; | |
2519 | case 0x010000000000ULL: | |
2520 | size = 0xF; | |
2521 | break; | |
2522 | #endif | |
2523 | default: | |
2524 | size = -1; | |
2525 | break; | |
2526 | } | |
2527 | ||
2528 | return size; | |
2529 | } | |
2530 | ||
76a66253 | 2531 | /* Helpers for 4xx TLB management */ |
76a66253 JM |
2532 | void do_4xx_tlbre_lo (void) |
2533 | { | |
a8dea12f JM |
2534 | ppcemb_tlb_t *tlb; |
2535 | int size; | |
76a66253 JM |
2536 | |
2537 | T0 &= 0x3F; | |
a8dea12f JM |
2538 | tlb = &env->tlb[T0].tlbe; |
2539 | T0 = tlb->EPN; | |
2540 | if (tlb->prot & PAGE_VALID) | |
2541 | T0 |= 0x400; | |
2542 | size = booke_page_size_to_tlb(tlb->size); | |
2543 | if (size < 0 || size > 0x7) | |
2544 | size = 1; | |
2545 | T0 |= size << 7; | |
2546 | env->spr[SPR_40x_PID] = tlb->PID; | |
76a66253 JM |
2547 | } |
2548 | ||
2549 | void do_4xx_tlbre_hi (void) | |
2550 | { | |
a8dea12f | 2551 | ppcemb_tlb_t *tlb; |
76a66253 JM |
2552 | |
2553 | T0 &= 0x3F; | |
a8dea12f JM |
2554 | tlb = &env->tlb[T0].tlbe; |
2555 | T0 = tlb->RPN; | |
2556 | if (tlb->prot & PAGE_EXEC) | |
2557 | T0 |= 0x200; | |
2558 | if (tlb->prot & PAGE_WRITE) | |
2559 | T0 |= 0x100; | |
76a66253 JM |
2560 | } |
2561 | ||
76a66253 JM |
2562 | void do_4xx_tlbsx (void) |
2563 | { | |
36081602 | 2564 | T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]); |
76a66253 JM |
2565 | } |
2566 | ||
2567 | void do_4xx_tlbsx_ (void) | |
2568 | { | |
966439a6 | 2569 | int tmp = xer_so; |
76a66253 | 2570 | |
36081602 | 2571 | T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]); |
76a66253 JM |
2572 | if (T0 != -1) |
2573 | tmp |= 0x02; | |
2574 | env->crf[0] = tmp; | |
2575 | } | |
2576 | ||
c55e9aef | 2577 | void do_4xx_tlbwe_hi (void) |
76a66253 | 2578 | { |
a8dea12f | 2579 | ppcemb_tlb_t *tlb; |
76a66253 JM |
2580 | target_ulong page, end; |
2581 | ||
c55e9aef | 2582 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d | 2583 | if (loglevel != 0) { |
c55e9aef JM |
2584 | fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1); |
2585 | } | |
2586 | #endif | |
76a66253 | 2587 | T0 &= 0x3F; |
a8dea12f | 2588 | tlb = &env->tlb[T0].tlbe; |
76a66253 JM |
2589 | /* Invalidate previous TLB (if it's valid) */ |
2590 | if (tlb->prot & PAGE_VALID) { | |
2591 | end = tlb->EPN + tlb->size; | |
c55e9aef | 2592 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d | 2593 | if (loglevel != 0) { |
c55e9aef JM |
2594 | fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX |
2595 | " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end); | |
2596 | } | |
2597 | #endif | |
76a66253 JM |
2598 | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) |
2599 | tlb_flush_page(env, page); | |
2600 | } | |
a8dea12f | 2601 | tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7); |
c294fc58 JM |
2602 | /* We cannot handle TLB size < TARGET_PAGE_SIZE. |
2603 | * If this ever occurs, one should use the ppcemb target instead | |
2604 | * of the ppc or ppc64 one | |
2605 | */ | |
2606 | if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) { | |
71c8b8fd JM |
2607 | cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u " |
2608 | "are not supported (%d)\n", | |
c294fc58 JM |
2609 | tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7)); |
2610 | } | |
a750fc0b | 2611 | tlb->EPN = T1 & ~(tlb->size - 1); |
c55e9aef | 2612 | if (T1 & 0x40) |
76a66253 JM |
2613 | tlb->prot |= PAGE_VALID; |
2614 | else | |
2615 | tlb->prot &= ~PAGE_VALID; | |
c294fc58 JM |
2616 | if (T1 & 0x20) { |
2617 | /* XXX: TO BE FIXED */ | |
2618 | cpu_abort(env, "Little-endian TLB entries are not supported by now\n"); | |
2619 | } | |
c55e9aef | 2620 | tlb->PID = env->spr[SPR_40x_PID]; /* PID */ |
a8dea12f | 2621 | tlb->attr = T1 & 0xFF; |
c55e9aef | 2622 | #if defined (DEBUG_SOFTWARE_TLB) |
c294fc58 JM |
2623 | if (loglevel != 0) { |
2624 | fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX | |
c55e9aef | 2625 | " size " ADDRX " prot %c%c%c%c PID %d\n", __func__, |
5fafdf24 | 2626 | (int)T0, tlb->RPN, tlb->EPN, tlb->size, |
c55e9aef JM |
2627 | tlb->prot & PAGE_READ ? 'r' : '-', |
2628 | tlb->prot & PAGE_WRITE ? 'w' : '-', | |
2629 | tlb->prot & PAGE_EXEC ? 'x' : '-', | |
2630 | tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); | |
2631 | } | |
2632 | #endif | |
76a66253 JM |
2633 | /* Invalidate new TLB (if valid) */ |
2634 | if (tlb->prot & PAGE_VALID) { | |
2635 | end = tlb->EPN + tlb->size; | |
c55e9aef | 2636 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d | 2637 | if (loglevel != 0) { |
c55e9aef JM |
2638 | fprintf(logfile, "%s: invalidate TLB %d start " ADDRX |
2639 | " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end); | |
2640 | } | |
2641 | #endif | |
76a66253 JM |
2642 | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) |
2643 | tlb_flush_page(env, page); | |
2644 | } | |
76a66253 JM |
2645 | } |
2646 | ||
c55e9aef | 2647 | void do_4xx_tlbwe_lo (void) |
76a66253 | 2648 | { |
a8dea12f | 2649 | ppcemb_tlb_t *tlb; |
76a66253 | 2650 | |
c55e9aef | 2651 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d | 2652 | if (loglevel != 0) { |
c55e9aef JM |
2653 | fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1); |
2654 | } | |
2655 | #endif | |
76a66253 | 2656 | T0 &= 0x3F; |
a8dea12f | 2657 | tlb = &env->tlb[T0].tlbe; |
76a66253 JM |
2658 | tlb->RPN = T1 & 0xFFFFFC00; |
2659 | tlb->prot = PAGE_READ; | |
2660 | if (T1 & 0x200) | |
2661 | tlb->prot |= PAGE_EXEC; | |
2662 | if (T1 & 0x100) | |
2663 | tlb->prot |= PAGE_WRITE; | |
c55e9aef | 2664 | #if defined (DEBUG_SOFTWARE_TLB) |
6b80055d JM |
2665 | if (loglevel != 0) { |
2666 | fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX | |
c55e9aef | 2667 | " size " ADDRX " prot %c%c%c%c PID %d\n", __func__, |
5fafdf24 | 2668 | (int)T0, tlb->RPN, tlb->EPN, tlb->size, |
c55e9aef JM |
2669 | tlb->prot & PAGE_READ ? 'r' : '-', |
2670 | tlb->prot & PAGE_WRITE ? 'w' : '-', | |
2671 | tlb->prot & PAGE_EXEC ? 'x' : '-', | |
2672 | tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); | |
2673 | } | |
2674 | #endif | |
76a66253 | 2675 | } |
5eb7995e | 2676 | |
a4bb6c3e JM |
2677 | /* PowerPC 440 TLB management */ |
2678 | void do_440_tlbwe (int word) | |
5eb7995e JM |
2679 | { |
2680 | ppcemb_tlb_t *tlb; | |
a4bb6c3e | 2681 | target_ulong EPN, RPN, size; |
5eb7995e JM |
2682 | int do_flush_tlbs; |
2683 | ||
2684 | #if defined (DEBUG_SOFTWARE_TLB) | |
2685 | if (loglevel != 0) { | |
a4bb6c3e JM |
2686 | fprintf(logfile, "%s word %d T0 " REGX " T1 " REGX "\n", |
2687 | __func__, word, T0, T1); | |
5eb7995e JM |
2688 | } |
2689 | #endif | |
2690 | do_flush_tlbs = 0; | |
2691 | T0 &= 0x3F; | |
2692 | tlb = &env->tlb[T0].tlbe; | |
a4bb6c3e JM |
2693 | switch (word) { |
2694 | default: | |
2695 | /* Just here to please gcc */ | |
2696 | case 0: | |
2697 | EPN = T1 & 0xFFFFFC00; | |
2698 | if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN) | |
5eb7995e | 2699 | do_flush_tlbs = 1; |
a4bb6c3e JM |
2700 | tlb->EPN = EPN; |
2701 | size = booke_tlb_to_page_size((T1 >> 4) & 0xF); | |
2702 | if ((tlb->prot & PAGE_VALID) && tlb->size < size) | |
2703 | do_flush_tlbs = 1; | |
2704 | tlb->size = size; | |
2705 | tlb->attr &= ~0x1; | |
2706 | tlb->attr |= (T1 >> 8) & 1; | |
2707 | if (T1 & 0x200) { | |
2708 | tlb->prot |= PAGE_VALID; | |
2709 | } else { | |
2710 | if (tlb->prot & PAGE_VALID) { | |
2711 | tlb->prot &= ~PAGE_VALID; | |
2712 | do_flush_tlbs = 1; | |
2713 | } | |
5eb7995e | 2714 | } |
a4bb6c3e JM |
2715 | tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF; |
2716 | if (do_flush_tlbs) | |
2717 | tlb_flush(env, 1); | |
2718 | break; | |
2719 | case 1: | |
2720 | RPN = T1 & 0xFFFFFC0F; | |
2721 | if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) | |
2722 | tlb_flush(env, 1); | |
2723 | tlb->RPN = RPN; | |
2724 | break; | |
2725 | case 2: | |
2726 | tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00); | |
2727 | tlb->prot = tlb->prot & PAGE_VALID; | |
2728 | if (T1 & 0x1) | |
2729 | tlb->prot |= PAGE_READ << 4; | |
2730 | if (T1 & 0x2) | |
2731 | tlb->prot |= PAGE_WRITE << 4; | |
2732 | if (T1 & 0x4) | |
2733 | tlb->prot |= PAGE_EXEC << 4; | |
2734 | if (T1 & 0x8) | |
2735 | tlb->prot |= PAGE_READ; | |
2736 | if (T1 & 0x10) | |
2737 | tlb->prot |= PAGE_WRITE; | |
2738 | if (T1 & 0x20) | |
2739 | tlb->prot |= PAGE_EXEC; | |
2740 | break; | |
5eb7995e | 2741 | } |
5eb7995e JM |
2742 | } |
2743 | ||
a4bb6c3e | 2744 | void do_440_tlbsx (void) |
5eb7995e | 2745 | { |
a750fc0b | 2746 | T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR] & 0xFF); |
5eb7995e JM |
2747 | } |
2748 | ||
a4bb6c3e | 2749 | void do_440_tlbsx_ (void) |
5eb7995e JM |
2750 | { |
2751 | int tmp = xer_so; | |
2752 | ||
a750fc0b | 2753 | T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR] & 0xFF); |
5eb7995e JM |
2754 | if (T0 != -1) |
2755 | tmp |= 0x02; | |
2756 | env->crf[0] = tmp; | |
2757 | } | |
2758 | ||
a4bb6c3e | 2759 | void do_440_tlbre (int word) |
5eb7995e JM |
2760 | { |
2761 | ppcemb_tlb_t *tlb; | |
2762 | int size; | |
2763 | ||
2764 | T0 &= 0x3F; | |
2765 | tlb = &env->tlb[T0].tlbe; | |
a4bb6c3e JM |
2766 | switch (word) { |
2767 | default: | |
2768 | /* Just here to please gcc */ | |
2769 | case 0: | |
2770 | T0 = tlb->EPN; | |
2771 | size = booke_page_size_to_tlb(tlb->size); | |
2772 | if (size < 0 || size > 0xF) | |
2773 | size = 1; | |
2774 | T0 |= size << 4; | |
2775 | if (tlb->attr & 0x1) | |
2776 | T0 |= 0x100; | |
2777 | if (tlb->prot & PAGE_VALID) | |
2778 | T0 |= 0x200; | |
2779 | env->spr[SPR_440_MMUCR] &= ~0x000000FF; | |
2780 | env->spr[SPR_440_MMUCR] |= tlb->PID; | |
2781 | break; | |
2782 | case 1: | |
2783 | T0 = tlb->RPN; | |
2784 | break; | |
2785 | case 2: | |
2786 | T0 = tlb->attr & ~0x1; | |
2787 | if (tlb->prot & (PAGE_READ << 4)) | |
2788 | T0 |= 0x1; | |
2789 | if (tlb->prot & (PAGE_WRITE << 4)) | |
2790 | T0 |= 0x2; | |
2791 | if (tlb->prot & (PAGE_EXEC << 4)) | |
2792 | T0 |= 0x4; | |
2793 | if (tlb->prot & PAGE_READ) | |
2794 | T0 |= 0x8; | |
2795 | if (tlb->prot & PAGE_WRITE) | |
2796 | T0 |= 0x10; | |
2797 | if (tlb->prot & PAGE_EXEC) | |
2798 | T0 |= 0x20; | |
2799 | break; | |
2800 | } | |
5eb7995e | 2801 | } |
76a66253 | 2802 | #endif /* !CONFIG_USER_ONLY */ |