]>
Commit | Line | Data |
---|---|---|
79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
79aceca5 | 21 | #include "cpu.h" |
76cad711 | 22 | #include "disas/disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
1de7afc9 | 24 | #include "qemu/host-utils.h" |
f08b6170 | 25 | #include "exec/cpu_ldst.h" |
79aceca5 | 26 | |
2ef6175a RH |
27 | #include "exec/helper-proto.h" |
28 | #include "exec/helper-gen.h" | |
a7812ae4 | 29 | |
a7e30d84 LV |
30 | #include "trace-tcg.h" |
31 | ||
32 | ||
8cbcb4fa AJ |
33 | #define CPU_SINGLE_STEP 0x1 |
34 | #define CPU_BRANCH_STEP 0x2 | |
35 | #define GDBSTUB_SINGLE_STEP 0x4 | |
36 | ||
a750fc0b | 37 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 38 | //#define PPC_DEBUG_DISAS |
76a66253 | 39 | //#define DO_PPC_STATISTICS |
79aceca5 | 40 | |
d12d51d5 | 41 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 42 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
43 | #else |
44 | # define LOG_DISAS(...) do { } while (0) | |
45 | #endif | |
a750fc0b JM |
46 | /*****************************************************************************/ |
47 | /* Code translation helpers */ | |
c53be334 | 48 | |
f78fb44e | 49 | /* global register indexes */ |
a7812ae4 | 50 | static TCGv_ptr cpu_env; |
1d542695 | 51 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
1d542695 | 52 | + 10*4 + 22*5 /* SPE GPRh */ |
a5e26afa | 53 | + 10*4 + 22*5 /* FPR */ |
47e4661c | 54 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
472b24ce | 55 | + 10*5 + 22*6 /* VSR */ |
47e4661c | 56 | + 8*5 /* CRF */]; |
f78fb44e | 57 | static TCGv cpu_gpr[32]; |
f78fb44e | 58 | static TCGv cpu_gprh[32]; |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fpr[32]; |
60 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
472b24ce | 61 | static TCGv_i64 cpu_vsr[32]; |
a7812ae4 | 62 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 63 | static TCGv cpu_nip; |
6527f6ea | 64 | static TCGv cpu_msr; |
cfdcd37a AJ |
65 | static TCGv cpu_ctr; |
66 | static TCGv cpu_lr; | |
697ab892 DG |
67 | #if defined(TARGET_PPC64) |
68 | static TCGv cpu_cfar; | |
69 | #endif | |
da91a00f | 70 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 71 | static TCGv cpu_reserve; |
30304420 | 72 | static TCGv cpu_fpscr; |
a7859e89 | 73 | static TCGv_i32 cpu_access_type; |
f78fb44e | 74 | |
022c62cb | 75 | #include "exec/gen-icount.h" |
2e70f6ef PB |
76 | |
77 | void ppc_translate_init(void) | |
78 | { | |
f78fb44e AJ |
79 | int i; |
80 | char* p; | |
2dc766da | 81 | size_t cpu_reg_names_size; |
b2437bf2 | 82 | static int done_init = 0; |
f78fb44e | 83 | |
2e70f6ef PB |
84 | if (done_init) |
85 | return; | |
f78fb44e | 86 | |
a7812ae4 | 87 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 88 | |
f78fb44e | 89 | p = cpu_reg_names; |
2dc766da | 90 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
91 | |
92 | for (i = 0; i < 8; i++) { | |
2dc766da | 93 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 | 94 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 95 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 96 | p += 5; |
2dc766da | 97 | cpu_reg_names_size -= 5; |
47e4661c AJ |
98 | } |
99 | ||
f78fb44e | 100 | for (i = 0; i < 32; i++) { |
2dc766da | 101 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 102 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 103 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 104 | p += (i < 10) ? 3 : 4; |
2dc766da | 105 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 106 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
13b6a455 AG |
107 | cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0, |
108 | offsetof(CPUPPCState, gprh[i]), p); | |
f78fb44e | 109 | p += (i < 10) ? 4 : 5; |
2dc766da | 110 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
1d542695 | 111 | |
2dc766da | 112 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 | 113 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 114 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 115 | p += (i < 10) ? 4 : 5; |
2dc766da | 116 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 117 | |
2dc766da | 118 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 119 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 120 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 121 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 122 | #else |
a7812ae4 | 123 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 124 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 125 | #endif |
1d542695 | 126 | p += (i < 10) ? 6 : 7; |
2dc766da | 127 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 128 | |
2dc766da | 129 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 130 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 131 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 132 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 133 | #else |
a7812ae4 | 134 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 135 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 136 | #endif |
1d542695 | 137 | p += (i < 10) ? 6 : 7; |
2dc766da | 138 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
472b24ce TM |
139 | snprintf(p, cpu_reg_names_size, "vsr%d", i); |
140 | cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
141 | offsetof(CPUPPCState, vsr[i]), p); | |
142 | p += (i < 10) ? 5 : 6; | |
143 | cpu_reg_names_size -= (i < 10) ? 5 : 6; | |
f78fb44e | 144 | } |
f10dc08e | 145 | |
a7812ae4 | 146 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 147 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 148 | |
6527f6ea | 149 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 150 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 151 | |
a7812ae4 | 152 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 153 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 154 | |
a7812ae4 | 155 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 156 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 157 | |
697ab892 DG |
158 | #if defined(TARGET_PPC64) |
159 | cpu_cfar = tcg_global_mem_new(TCG_AREG0, | |
1328c2bf | 160 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
161 | #endif |
162 | ||
a7812ae4 | 163 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 164 | offsetof(CPUPPCState, xer), "xer"); |
da91a00f RH |
165 | cpu_so = tcg_global_mem_new(TCG_AREG0, |
166 | offsetof(CPUPPCState, so), "SO"); | |
167 | cpu_ov = tcg_global_mem_new(TCG_AREG0, | |
168 | offsetof(CPUPPCState, ov), "OV"); | |
169 | cpu_ca = tcg_global_mem_new(TCG_AREG0, | |
170 | offsetof(CPUPPCState, ca), "CA"); | |
3d7b417e | 171 | |
cf360a32 | 172 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 173 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 174 | "reserve_addr"); |
cf360a32 | 175 | |
30304420 DG |
176 | cpu_fpscr = tcg_global_mem_new(TCG_AREG0, |
177 | offsetof(CPUPPCState, fpscr), "fpscr"); | |
e1571908 | 178 | |
a7859e89 | 179 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 180 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 181 | |
2e70f6ef PB |
182 | done_init = 1; |
183 | } | |
184 | ||
79aceca5 FB |
185 | /* internal defines */ |
186 | typedef struct DisasContext { | |
187 | struct TranslationBlock *tb; | |
0fa85d43 | 188 | target_ulong nip; |
79aceca5 | 189 | uint32_t opcode; |
9a64fbe4 | 190 | uint32_t exception; |
3cc62370 FB |
191 | /* Routine used to access memory */ |
192 | int mem_idx; | |
76db3ba4 | 193 | int access_type; |
3cc62370 | 194 | /* Translation flags */ |
76db3ba4 | 195 | int le_mode; |
e22c357b | 196 | TCGMemOp default_tcg_memop_mask; |
d9bce9d9 JM |
197 | #if defined(TARGET_PPC64) |
198 | int sf_mode; | |
697ab892 | 199 | int has_cfar; |
9a64fbe4 | 200 | #endif |
3cc62370 | 201 | int fpu_enabled; |
a9d9eb8f | 202 | int altivec_enabled; |
1f29871c | 203 | int vsx_enabled; |
0487d6a8 | 204 | int spe_enabled; |
c227f099 | 205 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 206 | int singlestep_enabled; |
7d08d856 AJ |
207 | uint64_t insns_flags; |
208 | uint64_t insns_flags2; | |
79aceca5 FB |
209 | } DisasContext; |
210 | ||
e22c357b DK |
211 | /* Return true iff byteswap is needed in a scalar memop */ |
212 | static inline bool need_byteswap(const DisasContext *ctx) | |
213 | { | |
214 | #if defined(TARGET_WORDS_BIGENDIAN) | |
215 | return ctx->le_mode; | |
216 | #else | |
217 | return !ctx->le_mode; | |
218 | #endif | |
219 | } | |
220 | ||
79482e5a RH |
221 | /* True when active word size < size of target_long. */ |
222 | #ifdef TARGET_PPC64 | |
223 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
224 | #else | |
225 | # define NARROW_MODE(C) 0 | |
226 | #endif | |
227 | ||
c227f099 | 228 | struct opc_handler_t { |
70560da7 FC |
229 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
230 | uint32_t inval1; | |
231 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
232 | uint32_t inval2; | |
9a64fbe4 | 233 | /* instruction type */ |
0487d6a8 | 234 | uint64_t type; |
a5858d7a AG |
235 | /* extended instruction type */ |
236 | uint64_t type2; | |
79aceca5 FB |
237 | /* handler */ |
238 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 239 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 240 | const char *oname; |
a750fc0b JM |
241 | #endif |
242 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
243 | uint64_t count; |
244 | #endif | |
3fc6c082 | 245 | }; |
79aceca5 | 246 | |
636aa200 | 247 | static inline void gen_reset_fpstatus(void) |
7c58044c | 248 | { |
8e703949 | 249 | gen_helper_reset_fpstatus(cpu_env); |
7c58044c JM |
250 | } |
251 | ||
636aa200 | 252 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 253 | { |
0f2f39c2 | 254 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 255 | |
7c58044c JM |
256 | if (set_fprf != 0) { |
257 | /* This case might be optimized later */ | |
0f2f39c2 | 258 | tcg_gen_movi_i32(t0, 1); |
8e703949 | 259 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
a7812ae4 | 260 | if (unlikely(set_rc)) { |
0f2f39c2 | 261 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 262 | } |
8e703949 | 263 | gen_helper_float_check_status(cpu_env); |
7c58044c JM |
264 | } else if (unlikely(set_rc)) { |
265 | /* We always need to compute fpcc */ | |
0f2f39c2 | 266 | tcg_gen_movi_i32(t0, 0); |
8e703949 | 267 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
0f2f39c2 | 268 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 269 | } |
af12906f | 270 | |
0f2f39c2 | 271 | tcg_temp_free_i32(t0); |
7c58044c JM |
272 | } |
273 | ||
636aa200 | 274 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 275 | { |
76db3ba4 AJ |
276 | if (ctx->access_type != access_type) { |
277 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
278 | ctx->access_type = access_type; | |
279 | } | |
a7859e89 AJ |
280 | } |
281 | ||
636aa200 | 282 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 283 | { |
e0c8f9ce RH |
284 | if (NARROW_MODE(ctx)) { |
285 | nip = (uint32_t)nip; | |
286 | } | |
287 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
288 | } |
289 | ||
7019cb3d AK |
290 | void gen_update_current_nip(void *opaque) |
291 | { | |
292 | DisasContext *ctx = opaque; | |
293 | ||
294 | tcg_gen_movi_tl(cpu_nip, ctx->nip); | |
295 | } | |
296 | ||
636aa200 | 297 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
298 | { |
299 | TCGv_i32 t0, t1; | |
300 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
301 | gen_update_nip(ctx, ctx->nip); | |
302 | } | |
303 | t0 = tcg_const_i32(excp); | |
304 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 305 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
306 | tcg_temp_free_i32(t0); |
307 | tcg_temp_free_i32(t1); | |
308 | ctx->exception = (excp); | |
309 | } | |
e1833e1f | 310 | |
636aa200 | 311 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
312 | { |
313 | TCGv_i32 t0; | |
314 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
315 | gen_update_nip(ctx, ctx->nip); | |
316 | } | |
317 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 318 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
319 | tcg_temp_free_i32(t0); |
320 | ctx->exception = (excp); | |
321 | } | |
e1833e1f | 322 | |
636aa200 | 323 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
324 | { |
325 | TCGv_i32 t0; | |
5518f3a6 | 326 | |
ee2b3994 SB |
327 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
328 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
5518f3a6 | 329 | gen_update_nip(ctx, ctx->nip); |
ee2b3994 | 330 | } |
e06fcd75 | 331 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 332 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
333 | tcg_temp_free_i32(t0); |
334 | } | |
9a64fbe4 | 335 | |
636aa200 | 336 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
337 | { |
338 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
339 | } | |
a9d9eb8f | 340 | |
f24e5695 | 341 | /* Stop translation */ |
636aa200 | 342 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 343 | { |
d9bce9d9 | 344 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 345 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
346 | } |
347 | ||
f24e5695 | 348 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 349 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 350 | { |
e1833e1f | 351 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
352 | } |
353 | ||
79aceca5 | 354 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
355 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
356 | ||
357 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
358 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 359 | |
c7697e1f | 360 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
361 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
362 | ||
363 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
364 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 365 | |
c227f099 | 366 | typedef struct opcode_t { |
79aceca5 | 367 | unsigned char opc1, opc2, opc3; |
1235fc06 | 368 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
369 | unsigned char pad[5]; |
370 | #else | |
371 | unsigned char pad[1]; | |
372 | #endif | |
c227f099 | 373 | opc_handler_t handler; |
b55266b5 | 374 | const char *oname; |
c227f099 | 375 | } opcode_t; |
79aceca5 | 376 | |
a750fc0b | 377 | /*****************************************************************************/ |
79aceca5 FB |
378 | /*** Instruction decoding ***/ |
379 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 380 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
381 | { \ |
382 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
383 | } | |
384 | ||
385 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 386 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 387 | { \ |
18fba28c | 388 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
389 | } |
390 | ||
f9fc6d81 TM |
391 | #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \ |
392 | static inline uint32_t name(uint32_t opcode) \ | |
393 | { \ | |
394 | return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \ | |
395 | ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \ | |
396 | } | |
79aceca5 FB |
397 | /* Opcode part 1 */ |
398 | EXTRACT_HELPER(opc1, 26, 6); | |
399 | /* Opcode part 2 */ | |
400 | EXTRACT_HELPER(opc2, 1, 5); | |
401 | /* Opcode part 3 */ | |
402 | EXTRACT_HELPER(opc3, 6, 5); | |
403 | /* Update Cr0 flags */ | |
404 | EXTRACT_HELPER(Rc, 0, 1); | |
a737d3eb TM |
405 | /* Update Cr6 flags (Altivec) */ |
406 | EXTRACT_HELPER(Rc21, 10, 1); | |
79aceca5 FB |
407 | /* Destination */ |
408 | EXTRACT_HELPER(rD, 21, 5); | |
409 | /* Source */ | |
410 | EXTRACT_HELPER(rS, 21, 5); | |
411 | /* First operand */ | |
412 | EXTRACT_HELPER(rA, 16, 5); | |
413 | /* Second operand */ | |
414 | EXTRACT_HELPER(rB, 11, 5); | |
415 | /* Third operand */ | |
416 | EXTRACT_HELPER(rC, 6, 5); | |
417 | /*** Get CRn ***/ | |
418 | EXTRACT_HELPER(crfD, 23, 3); | |
419 | EXTRACT_HELPER(crfS, 18, 3); | |
420 | EXTRACT_HELPER(crbD, 21, 5); | |
421 | EXTRACT_HELPER(crbA, 16, 5); | |
422 | EXTRACT_HELPER(crbB, 11, 5); | |
423 | /* SPR / TBL */ | |
3fc6c082 | 424 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 425 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
426 | { |
427 | uint32_t sprn = _SPR(opcode); | |
428 | ||
429 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
430 | } | |
79aceca5 | 431 | /*** Get constants ***/ |
79aceca5 FB |
432 | /* 16 bits signed immediate value */ |
433 | EXTRACT_SHELPER(SIMM, 0, 16); | |
434 | /* 16 bits unsigned immediate value */ | |
435 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
436 | /* 5 bits signed immediate value */ |
437 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
438 | /* 5 bits signed immediate value */ |
439 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
440 | /* Bit count */ |
441 | EXTRACT_HELPER(NB, 11, 5); | |
442 | /* Shift count */ | |
443 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
444 | /* Vector shift count */ |
445 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
446 | /* Mask start */ |
447 | EXTRACT_HELPER(MB, 6, 5); | |
448 | /* Mask end */ | |
449 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
450 | /* Trap operand */ |
451 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
452 | |
453 | EXTRACT_HELPER(CRM, 12, 8); | |
79aceca5 | 454 | EXTRACT_HELPER(SR, 16, 4); |
7d08d856 AJ |
455 | |
456 | /* mtfsf/mtfsfi */ | |
779f6590 | 457 | EXTRACT_HELPER(FPBF, 23, 3); |
e4bb997e | 458 | EXTRACT_HELPER(FPIMM, 12, 4); |
779f6590 | 459 | EXTRACT_HELPER(FPL, 25, 1); |
7d08d856 AJ |
460 | EXTRACT_HELPER(FPFLM, 17, 8); |
461 | EXTRACT_HELPER(FPW, 16, 1); | |
fb0eaffc | 462 | |
79aceca5 | 463 | /*** Jump target decoding ***/ |
79aceca5 | 464 | /* Immediate address */ |
636aa200 | 465 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
466 | { |
467 | return (opcode >> 0) & 0x03FFFFFC; | |
468 | } | |
469 | ||
636aa200 | 470 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
471 | { |
472 | return (opcode >> 0) & 0xFFFC; | |
473 | } | |
474 | ||
475 | EXTRACT_HELPER(BO, 21, 5); | |
476 | EXTRACT_HELPER(BI, 16, 5); | |
477 | /* Absolute/relative address */ | |
478 | EXTRACT_HELPER(AA, 1, 1); | |
479 | /* Link */ | |
480 | EXTRACT_HELPER(LK, 0, 1); | |
481 | ||
f0b01f02 TM |
482 | /* DFP Z22-form */ |
483 | EXTRACT_HELPER(DCM, 10, 6) | |
484 | ||
485 | /* DFP Z23-form */ | |
486 | EXTRACT_HELPER(RMC, 9, 2) | |
487 | ||
79aceca5 | 488 | /* Create a mask between <start> and <end> bits */ |
636aa200 | 489 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 490 | { |
76a66253 | 491 | target_ulong ret; |
79aceca5 | 492 | |
76a66253 JM |
493 | #if defined(TARGET_PPC64) |
494 | if (likely(start == 0)) { | |
6f2d8978 | 495 | ret = UINT64_MAX << (63 - end); |
76a66253 | 496 | } else if (likely(end == 63)) { |
6f2d8978 | 497 | ret = UINT64_MAX >> start; |
76a66253 JM |
498 | } |
499 | #else | |
500 | if (likely(start == 0)) { | |
6f2d8978 | 501 | ret = UINT32_MAX << (31 - end); |
76a66253 | 502 | } else if (likely(end == 31)) { |
6f2d8978 | 503 | ret = UINT32_MAX >> start; |
76a66253 JM |
504 | } |
505 | #endif | |
506 | else { | |
507 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
508 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
509 | if (unlikely(start > end)) | |
510 | return ~ret; | |
511 | } | |
79aceca5 FB |
512 | |
513 | return ret; | |
514 | } | |
515 | ||
f9fc6d81 TM |
516 | EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5); |
517 | EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5); | |
518 | EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5); | |
519 | EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5); | |
551e3ef7 | 520 | EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5); |
f9fc6d81 | 521 | EXTRACT_HELPER(DM, 8, 2); |
76c15fe0 | 522 | EXTRACT_HELPER(UIM, 16, 2); |
acc42968 | 523 | EXTRACT_HELPER(SHW, 8, 2); |
f0b01f02 | 524 | EXTRACT_HELPER(SP, 19, 2); |
a750fc0b | 525 | /*****************************************************************************/ |
a750fc0b | 526 | /* PowerPC instructions table */ |
933dc6eb | 527 | |
76a66253 | 528 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 529 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 530 | { \ |
79aceca5 FB |
531 | .opc1 = op1, \ |
532 | .opc2 = op2, \ | |
533 | .opc3 = op3, \ | |
18fba28c | 534 | .pad = { 0, }, \ |
79aceca5 | 535 | .handler = { \ |
70560da7 FC |
536 | .inval1 = invl, \ |
537 | .type = _typ, \ | |
538 | .type2 = _typ2, \ | |
539 | .handler = &gen_##name, \ | |
540 | .oname = stringify(name), \ | |
541 | }, \ | |
542 | .oname = stringify(name), \ | |
543 | } | |
544 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
545 | { \ | |
546 | .opc1 = op1, \ | |
547 | .opc2 = op2, \ | |
548 | .opc3 = op3, \ | |
549 | .pad = { 0, }, \ | |
550 | .handler = { \ | |
551 | .inval1 = invl1, \ | |
552 | .inval2 = invl2, \ | |
9a64fbe4 | 553 | .type = _typ, \ |
a5858d7a | 554 | .type2 = _typ2, \ |
79aceca5 | 555 | .handler = &gen_##name, \ |
76a66253 | 556 | .oname = stringify(name), \ |
79aceca5 | 557 | }, \ |
3fc6c082 | 558 | .oname = stringify(name), \ |
79aceca5 | 559 | } |
a5858d7a | 560 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 561 | { \ |
c7697e1f JM |
562 | .opc1 = op1, \ |
563 | .opc2 = op2, \ | |
564 | .opc3 = op3, \ | |
565 | .pad = { 0, }, \ | |
566 | .handler = { \ | |
70560da7 | 567 | .inval1 = invl, \ |
c7697e1f | 568 | .type = _typ, \ |
a5858d7a | 569 | .type2 = _typ2, \ |
c7697e1f JM |
570 | .handler = &gen_##name, \ |
571 | .oname = onam, \ | |
572 | }, \ | |
573 | .oname = onam, \ | |
574 | } | |
76a66253 | 575 | #else |
a5858d7a | 576 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 577 | { \ |
c7697e1f JM |
578 | .opc1 = op1, \ |
579 | .opc2 = op2, \ | |
580 | .opc3 = op3, \ | |
581 | .pad = { 0, }, \ | |
582 | .handler = { \ | |
70560da7 FC |
583 | .inval1 = invl, \ |
584 | .type = _typ, \ | |
585 | .type2 = _typ2, \ | |
586 | .handler = &gen_##name, \ | |
587 | }, \ | |
588 | .oname = stringify(name), \ | |
589 | } | |
590 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
591 | { \ | |
592 | .opc1 = op1, \ | |
593 | .opc2 = op2, \ | |
594 | .opc3 = op3, \ | |
595 | .pad = { 0, }, \ | |
596 | .handler = { \ | |
597 | .inval1 = invl1, \ | |
598 | .inval2 = invl2, \ | |
c7697e1f | 599 | .type = _typ, \ |
a5858d7a | 600 | .type2 = _typ2, \ |
c7697e1f | 601 | .handler = &gen_##name, \ |
5c55ff99 BS |
602 | }, \ |
603 | .oname = stringify(name), \ | |
604 | } | |
a5858d7a | 605 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
606 | { \ |
607 | .opc1 = op1, \ | |
608 | .opc2 = op2, \ | |
609 | .opc3 = op3, \ | |
610 | .pad = { 0, }, \ | |
611 | .handler = { \ | |
70560da7 | 612 | .inval1 = invl, \ |
5c55ff99 | 613 | .type = _typ, \ |
a5858d7a | 614 | .type2 = _typ2, \ |
5c55ff99 BS |
615 | .handler = &gen_##name, \ |
616 | }, \ | |
617 | .oname = onam, \ | |
618 | } | |
619 | #endif | |
2e610050 | 620 | |
5c55ff99 | 621 | /* SPR load/store helpers */ |
636aa200 | 622 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 623 | { |
1328c2bf | 624 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 625 | } |
2e610050 | 626 | |
636aa200 | 627 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 628 | { |
1328c2bf | 629 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 630 | } |
2e610050 | 631 | |
54623277 | 632 | /* Invalid instruction */ |
99e300ef | 633 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 634 | { |
e06fcd75 | 635 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
636 | } |
637 | ||
c227f099 | 638 | static opc_handler_t invalid_handler = { |
70560da7 FC |
639 | .inval1 = 0xFFFFFFFF, |
640 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 641 | .type = PPC_NONE, |
a5858d7a | 642 | .type2 = PPC_NONE, |
79aceca5 FB |
643 | .handler = gen_invalid, |
644 | }; | |
645 | ||
71a8c019 TM |
646 | #if defined(TARGET_PPC64) |
647 | /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */ | |
648 | /* so the function is wrapped in the standard 64-bit ifdef in order to */ | |
649 | /* avoid compiler warnings in 32-bit implementations. */ | |
650 | static bool is_user_mode(DisasContext *ctx) | |
651 | { | |
652 | #if defined(CONFIG_USER_ONLY) | |
653 | return true; | |
654 | #else | |
655 | return ctx->mem_idx == 0; | |
656 | #endif | |
657 | } | |
658 | #endif | |
659 | ||
e1571908 AJ |
660 | /*** Integer comparison ***/ |
661 | ||
636aa200 | 662 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 663 | { |
2fdcb629 RH |
664 | TCGv t0 = tcg_temp_new(); |
665 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 666 | |
da91a00f | 667 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 668 | |
2fdcb629 RH |
669 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
670 | tcg_gen_trunc_tl_i32(t1, t0); | |
671 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
672 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
673 | ||
674 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
675 | tcg_gen_trunc_tl_i32(t1, t0); | |
676 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
677 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
678 | ||
679 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
680 | tcg_gen_trunc_tl_i32(t1, t0); | |
681 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
682 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
683 | ||
684 | tcg_temp_free(t0); | |
685 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
686 | } |
687 | ||
636aa200 | 688 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 689 | { |
2fdcb629 | 690 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
691 | gen_op_cmp(arg0, t0, s, crf); |
692 | tcg_temp_free(t0); | |
e1571908 AJ |
693 | } |
694 | ||
636aa200 | 695 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 696 | { |
ea363694 | 697 | TCGv t0, t1; |
2fdcb629 RH |
698 | t0 = tcg_temp_new(); |
699 | t1 = tcg_temp_new(); | |
e1571908 | 700 | if (s) { |
ea363694 AJ |
701 | tcg_gen_ext32s_tl(t0, arg0); |
702 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 703 | } else { |
ea363694 AJ |
704 | tcg_gen_ext32u_tl(t0, arg0); |
705 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 706 | } |
ea363694 AJ |
707 | gen_op_cmp(t0, t1, s, crf); |
708 | tcg_temp_free(t1); | |
709 | tcg_temp_free(t0); | |
e1571908 AJ |
710 | } |
711 | ||
636aa200 | 712 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 713 | { |
2fdcb629 | 714 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
715 | gen_op_cmp32(arg0, t0, s, crf); |
716 | tcg_temp_free(t0); | |
e1571908 | 717 | } |
e1571908 | 718 | |
636aa200 | 719 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 720 | { |
02765534 | 721 | if (NARROW_MODE(ctx)) { |
e1571908 | 722 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 723 | } else { |
e1571908 | 724 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 725 | } |
e1571908 AJ |
726 | } |
727 | ||
728 | /* cmp */ | |
99e300ef | 729 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 730 | { |
36f48d9c | 731 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
732 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
733 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
734 | } else { |
735 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
736 | 1, crfD(ctx->opcode)); | |
02765534 | 737 | } |
e1571908 AJ |
738 | } |
739 | ||
740 | /* cmpi */ | |
99e300ef | 741 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 742 | { |
36f48d9c | 743 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
744 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
745 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
746 | } else { |
747 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
748 | 1, crfD(ctx->opcode)); | |
02765534 | 749 | } |
e1571908 AJ |
750 | } |
751 | ||
752 | /* cmpl */ | |
99e300ef | 753 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 754 | { |
36f48d9c | 755 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
756 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
757 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
758 | } else { |
759 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
760 | 0, crfD(ctx->opcode)); | |
02765534 | 761 | } |
e1571908 AJ |
762 | } |
763 | ||
764 | /* cmpli */ | |
99e300ef | 765 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 766 | { |
36f48d9c | 767 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
768 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
769 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
770 | } else { |
771 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
772 | 0, crfD(ctx->opcode)); | |
02765534 | 773 | } |
e1571908 AJ |
774 | } |
775 | ||
776 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 777 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
778 | { |
779 | int l1, l2; | |
780 | uint32_t bi = rC(ctx->opcode); | |
781 | uint32_t mask; | |
a7812ae4 | 782 | TCGv_i32 t0; |
e1571908 AJ |
783 | |
784 | l1 = gen_new_label(); | |
785 | l2 = gen_new_label(); | |
786 | ||
787 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 788 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
789 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
790 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
791 | if (rA(ctx->opcode) == 0) |
792 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
793 | else | |
794 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
795 | tcg_gen_br(l2); | |
796 | gen_set_label(l1); | |
797 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
798 | gen_set_label(l2); | |
a7812ae4 | 799 | tcg_temp_free_i32(t0); |
e1571908 AJ |
800 | } |
801 | ||
fcfda20f AJ |
802 | /* cmpb: PowerPC 2.05 specification */ |
803 | static void gen_cmpb(DisasContext *ctx) | |
804 | { | |
805 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
806 | cpu_gpr[rB(ctx->opcode)]); | |
807 | } | |
808 | ||
79aceca5 | 809 | /*** Integer arithmetic ***/ |
79aceca5 | 810 | |
636aa200 BS |
811 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
812 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 813 | { |
ffe30937 | 814 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 815 | |
8e7a6db9 | 816 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 817 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
818 | if (sub) { |
819 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
820 | } else { | |
821 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
822 | } | |
823 | tcg_temp_free(t0); | |
02765534 | 824 | if (NARROW_MODE(ctx)) { |
ffe30937 RH |
825 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
826 | } | |
ffe30937 RH |
827 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
828 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
829 | } |
830 | ||
74637406 | 831 | /* Common add function */ |
636aa200 | 832 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
833 | TCGv arg2, bool add_ca, bool compute_ca, |
834 | bool compute_ov, bool compute_rc0) | |
74637406 | 835 | { |
b5a73f8d | 836 | TCGv t0 = ret; |
d9bce9d9 | 837 | |
752d634e | 838 | if (compute_ca || compute_ov) { |
146de60d | 839 | t0 = tcg_temp_new(); |
74637406 | 840 | } |
79aceca5 | 841 | |
da91a00f | 842 | if (compute_ca) { |
79482e5a | 843 | if (NARROW_MODE(ctx)) { |
752d634e RH |
844 | /* Caution: a non-obvious corner case of the spec is that we |
845 | must produce the *entire* 64-bit addition, but produce the | |
846 | carry into bit 32. */ | |
79482e5a | 847 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
848 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
849 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
850 | if (add_ca) { |
851 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
852 | } | |
752d634e RH |
853 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
854 | tcg_temp_free(t1); | |
855 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
856 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
b5a73f8d | 857 | } else { |
79482e5a RH |
858 | TCGv zero = tcg_const_tl(0); |
859 | if (add_ca) { | |
860 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
861 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
862 | } else { | |
863 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
864 | } | |
865 | tcg_temp_free(zero); | |
b5a73f8d | 866 | } |
b5a73f8d RH |
867 | } else { |
868 | tcg_gen_add_tl(t0, arg1, arg2); | |
869 | if (add_ca) { | |
870 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
871 | } | |
da91a00f | 872 | } |
79aceca5 | 873 | |
74637406 AJ |
874 | if (compute_ov) { |
875 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
876 | } | |
b5a73f8d | 877 | if (unlikely(compute_rc0)) { |
74637406 | 878 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 879 | } |
74637406 | 880 | |
a7812ae4 | 881 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
882 | tcg_gen_mov_tl(ret, t0); |
883 | tcg_temp_free(t0); | |
884 | } | |
39dd32ee | 885 | } |
74637406 AJ |
886 | /* Add functions with two operands */ |
887 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 888 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
889 | { \ |
890 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
891 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 892 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
893 | } |
894 | /* Add functions with one operand and one immediate */ | |
895 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
896 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 897 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 898 | { \ |
b5a73f8d | 899 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
900 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
901 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 902 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
903 | tcg_temp_free(t0); \ |
904 | } | |
905 | ||
906 | /* add add. addo addo. */ | |
907 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
908 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
909 | /* addc addc. addco addco. */ | |
910 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
911 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
912 | /* adde adde. addeo addeo. */ | |
913 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
914 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
915 | /* addme addme. addmeo addmeo. */ | |
916 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
917 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
918 | /* addze addze. addzeo addzeo.*/ | |
919 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
920 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
921 | /* addi */ | |
99e300ef | 922 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 923 | { |
74637406 AJ |
924 | target_long simm = SIMM(ctx->opcode); |
925 | ||
926 | if (rA(ctx->opcode) == 0) { | |
927 | /* li case */ | |
928 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
929 | } else { | |
b5a73f8d RH |
930 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
931 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 932 | } |
d9bce9d9 | 933 | } |
74637406 | 934 | /* addic addic.*/ |
b5a73f8d | 935 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 936 | { |
b5a73f8d RH |
937 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
938 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
939 | c, 0, 1, 0, compute_rc0); | |
940 | tcg_temp_free(c); | |
d9bce9d9 | 941 | } |
99e300ef BS |
942 | |
943 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 944 | { |
b5a73f8d | 945 | gen_op_addic(ctx, 0); |
d9bce9d9 | 946 | } |
e8eaa2c0 BS |
947 | |
948 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 949 | { |
b5a73f8d | 950 | gen_op_addic(ctx, 1); |
d9bce9d9 | 951 | } |
99e300ef | 952 | |
54623277 | 953 | /* addis */ |
99e300ef | 954 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 955 | { |
74637406 AJ |
956 | target_long simm = SIMM(ctx->opcode); |
957 | ||
958 | if (rA(ctx->opcode) == 0) { | |
959 | /* lis case */ | |
960 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
961 | } else { | |
b5a73f8d RH |
962 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
963 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 964 | } |
d9bce9d9 | 965 | } |
74637406 | 966 | |
636aa200 BS |
967 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
968 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 969 | { |
2ef1b120 AJ |
970 | int l1 = gen_new_label(); |
971 | int l2 = gen_new_label(); | |
a7812ae4 PB |
972 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
973 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 974 | |
2ef1b120 AJ |
975 | tcg_gen_trunc_tl_i32(t0, arg1); |
976 | tcg_gen_trunc_tl_i32(t1, arg2); | |
977 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 978 | if (sign) { |
2ef1b120 AJ |
979 | int l3 = gen_new_label(); |
980 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
981 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 982 | gen_set_label(l3); |
2ef1b120 | 983 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 984 | } else { |
2ef1b120 | 985 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
986 | } |
987 | if (compute_ov) { | |
da91a00f | 988 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
989 | } |
990 | tcg_gen_br(l2); | |
991 | gen_set_label(l1); | |
992 | if (sign) { | |
2ef1b120 | 993 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
994 | } else { |
995 | tcg_gen_movi_i32(t0, 0); | |
996 | } | |
997 | if (compute_ov) { | |
da91a00f RH |
998 | tcg_gen_movi_tl(cpu_ov, 1); |
999 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
1000 | } |
1001 | gen_set_label(l2); | |
2ef1b120 | 1002 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
1003 | tcg_temp_free_i32(t0); |
1004 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1005 | if (unlikely(Rc(ctx->opcode) != 0)) |
1006 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1007 | } |
74637406 AJ |
1008 | /* Div functions */ |
1009 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 1010 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1011 | { \ |
1012 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1013 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1014 | sign, compute_ov); \ | |
1015 | } | |
1016 | /* divwu divwu. divwuo divwuo. */ | |
1017 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1018 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1019 | /* divw divw. divwo divwo. */ | |
1020 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1021 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
1022 | |
1023 | /* div[wd]eu[o][.] */ | |
1024 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1025 | static void gen_##name(DisasContext *ctx) \ | |
1026 | { \ | |
1027 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ | |
1028 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ | |
1029 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1030 | tcg_temp_free_i32(t0); \ | |
1031 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1032 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1033 | } \ | |
1034 | } | |
1035 | ||
6a4fda33 TM |
1036 | GEN_DIVE(divweu, divweu, 0); |
1037 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1038 | GEN_DIVE(divwe, divwe, 0); |
1039 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1040 | |
d9bce9d9 | 1041 | #if defined(TARGET_PPC64) |
636aa200 BS |
1042 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1043 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1044 | { |
2ef1b120 AJ |
1045 | int l1 = gen_new_label(); |
1046 | int l2 = gen_new_label(); | |
74637406 AJ |
1047 | |
1048 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
1049 | if (sign) { | |
2ef1b120 | 1050 | int l3 = gen_new_label(); |
74637406 AJ |
1051 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
1052 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
1053 | gen_set_label(l3); | |
74637406 AJ |
1054 | tcg_gen_div_i64(ret, arg1, arg2); |
1055 | } else { | |
1056 | tcg_gen_divu_i64(ret, arg1, arg2); | |
1057 | } | |
1058 | if (compute_ov) { | |
da91a00f | 1059 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
1060 | } |
1061 | tcg_gen_br(l2); | |
1062 | gen_set_label(l1); | |
1063 | if (sign) { | |
1064 | tcg_gen_sari_i64(ret, arg1, 63); | |
1065 | } else { | |
1066 | tcg_gen_movi_i64(ret, 0); | |
1067 | } | |
1068 | if (compute_ov) { | |
da91a00f RH |
1069 | tcg_gen_movi_tl(cpu_ov, 1); |
1070 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
1071 | } |
1072 | gen_set_label(l2); | |
1073 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1074 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1075 | } |
74637406 | 1076 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1077 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1078 | { \ |
2ef1b120 AJ |
1079 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1080 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1081 | sign, compute_ov); \ | |
74637406 AJ |
1082 | } |
1083 | /* divwu divwu. divwuo divwuo. */ | |
1084 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1085 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1086 | /* divw divw. divwo divwo. */ | |
1087 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1088 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1089 | |
1090 | GEN_DIVE(divdeu, divdeu, 0); | |
1091 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1092 | GEN_DIVE(divde, divde, 0); |
1093 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1094 | #endif |
74637406 AJ |
1095 | |
1096 | /* mulhw mulhw. */ | |
99e300ef | 1097 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1098 | { |
23ad1d5d RH |
1099 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1100 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1101 | |
23ad1d5d RH |
1102 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1103 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1104 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1105 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1106 | tcg_temp_free_i32(t0); | |
1107 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1108 | if (unlikely(Rc(ctx->opcode) != 0)) |
1109 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1110 | } |
99e300ef | 1111 | |
54623277 | 1112 | /* mulhwu mulhwu. */ |
99e300ef | 1113 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1114 | { |
23ad1d5d RH |
1115 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1116 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1117 | |
23ad1d5d RH |
1118 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1119 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1120 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1121 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1122 | tcg_temp_free_i32(t0); | |
1123 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1124 | if (unlikely(Rc(ctx->opcode) != 0)) |
1125 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1126 | } |
99e300ef | 1127 | |
54623277 | 1128 | /* mullw mullw. */ |
99e300ef | 1129 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1130 | { |
1fa74845 TM |
1131 | #if defined(TARGET_PPC64) |
1132 | TCGv_i64 t0, t1; | |
1133 | t0 = tcg_temp_new_i64(); | |
1134 | t1 = tcg_temp_new_i64(); | |
1135 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1136 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1137 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
1138 | tcg_temp_free(t0); | |
1139 | tcg_temp_free(t1); | |
1140 | #else | |
74637406 AJ |
1141 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1142 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1143 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
1fa74845 | 1144 | #endif |
74637406 AJ |
1145 | if (unlikely(Rc(ctx->opcode) != 0)) |
1146 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1147 | } |
99e300ef | 1148 | |
54623277 | 1149 | /* mullwo mullwo. */ |
99e300ef | 1150 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1151 | { |
e4a2c846 RH |
1152 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1153 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
f11ebbf8 TM |
1154 | #if defined(TARGET_PPC64) |
1155 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1156 | #endif | |
74637406 | 1157 | |
e4a2c846 RH |
1158 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1159 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1160 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1161 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
f11ebbf8 TM |
1162 | #if defined(TARGET_PPC64) |
1163 | tcg_gen_ext_i32_tl(t2, t1); | |
1164 | tcg_gen_deposit_i64(cpu_gpr[rD(ctx->opcode)], | |
1165 | cpu_gpr[rD(ctx->opcode)], t2, 32, 32); | |
1166 | tcg_temp_free(t2); | |
1167 | #endif | |
e4a2c846 RH |
1168 | |
1169 | tcg_gen_sari_i32(t0, t0, 31); | |
1170 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1171 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
1172 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1173 | ||
1174 | tcg_temp_free_i32(t0); | |
1175 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1176 | if (unlikely(Rc(ctx->opcode) != 0)) |
1177 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1178 | } |
99e300ef | 1179 | |
54623277 | 1180 | /* mulli */ |
99e300ef | 1181 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1182 | { |
74637406 AJ |
1183 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1184 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1185 | } |
23ad1d5d | 1186 | |
d9bce9d9 | 1187 | #if defined(TARGET_PPC64) |
74637406 | 1188 | /* mulhd mulhd. */ |
23ad1d5d RH |
1189 | static void gen_mulhd(DisasContext *ctx) |
1190 | { | |
1191 | TCGv lo = tcg_temp_new(); | |
1192 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1193 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1194 | tcg_temp_free(lo); | |
1195 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1196 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1197 | } | |
1198 | } | |
1199 | ||
74637406 | 1200 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1201 | static void gen_mulhdu(DisasContext *ctx) |
1202 | { | |
1203 | TCGv lo = tcg_temp_new(); | |
1204 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1205 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1206 | tcg_temp_free(lo); | |
1207 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1208 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1209 | } | |
1210 | } | |
99e300ef | 1211 | |
54623277 | 1212 | /* mulld mulld. */ |
99e300ef | 1213 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1214 | { |
74637406 AJ |
1215 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1216 | cpu_gpr[rB(ctx->opcode)]); | |
1217 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1218 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1219 | } |
d15f74fb | 1220 | |
74637406 | 1221 | /* mulldo mulldo. */ |
d15f74fb BS |
1222 | static void gen_mulldo(DisasContext *ctx) |
1223 | { | |
1224 | gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env, | |
1225 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1226 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1227 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1228 | } | |
1229 | } | |
d9bce9d9 | 1230 | #endif |
74637406 | 1231 | |
74637406 | 1232 | /* Common subf function */ |
636aa200 | 1233 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1234 | TCGv arg2, bool add_ca, bool compute_ca, |
1235 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1236 | { |
b5a73f8d | 1237 | TCGv t0 = ret; |
79aceca5 | 1238 | |
752d634e | 1239 | if (compute_ca || compute_ov) { |
b5a73f8d | 1240 | t0 = tcg_temp_new(); |
da91a00f | 1241 | } |
74637406 | 1242 | |
79482e5a RH |
1243 | if (compute_ca) { |
1244 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1245 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1246 | /* Caution: a non-obvious corner case of the spec is that we |
1247 | must produce the *entire* 64-bit addition, but produce the | |
1248 | carry into bit 32. */ | |
79482e5a | 1249 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1250 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1251 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1252 | if (add_ca) { |
752d634e | 1253 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1254 | } else { |
752d634e | 1255 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1256 | } |
752d634e | 1257 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1258 | tcg_gen_add_tl(t0, t0, inv1); |
c80d1df5 | 1259 | tcg_temp_free(inv1); |
752d634e RH |
1260 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1261 | tcg_temp_free(t1); | |
1262 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
1263 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
79482e5a | 1264 | } else if (add_ca) { |
08f4a0f7 RH |
1265 | TCGv zero, inv1 = tcg_temp_new(); |
1266 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1267 | zero = tcg_const_tl(0); |
1268 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1269 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
b5a73f8d | 1270 | tcg_temp_free(zero); |
08f4a0f7 | 1271 | tcg_temp_free(inv1); |
b5a73f8d | 1272 | } else { |
79482e5a | 1273 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1274 | tcg_gen_sub_tl(t0, arg2, arg1); |
b5a73f8d | 1275 | } |
79482e5a RH |
1276 | } else if (add_ca) { |
1277 | /* Since we're ignoring carry-out, we can simplify the | |
1278 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1279 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1280 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1281 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1282 | } else { |
b5a73f8d | 1283 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1284 | } |
b5a73f8d | 1285 | |
74637406 AJ |
1286 | if (compute_ov) { |
1287 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1288 | } | |
b5a73f8d | 1289 | if (unlikely(compute_rc0)) { |
74637406 | 1290 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1291 | } |
74637406 | 1292 | |
a7812ae4 | 1293 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1294 | tcg_gen_mov_tl(ret, t0); |
1295 | tcg_temp_free(t0); | |
79aceca5 | 1296 | } |
79aceca5 | 1297 | } |
74637406 AJ |
1298 | /* Sub functions with Two operands functions */ |
1299 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1300 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1301 | { \ |
1302 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1303 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1304 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1305 | } |
1306 | /* Sub functions with one operand and one immediate */ | |
1307 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1308 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1309 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1310 | { \ |
b5a73f8d | 1311 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1312 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1313 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1314 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1315 | tcg_temp_free(t0); \ |
1316 | } | |
1317 | /* subf subf. subfo subfo. */ | |
1318 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1319 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1320 | /* subfc subfc. subfco subfco. */ | |
1321 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1322 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1323 | /* subfe subfe. subfeo subfo. */ | |
1324 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1325 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1326 | /* subfme subfme. subfmeo subfmeo. */ | |
1327 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1328 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1329 | /* subfze subfze. subfzeo subfzeo.*/ | |
1330 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1331 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1332 | |
54623277 | 1333 | /* subfic */ |
99e300ef | 1334 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1335 | { |
b5a73f8d RH |
1336 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1337 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1338 | c, 0, 1, 0, 0); | |
1339 | tcg_temp_free(c); | |
79aceca5 FB |
1340 | } |
1341 | ||
fd3f0081 RH |
1342 | /* neg neg. nego nego. */ |
1343 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1344 | { | |
1345 | TCGv zero = tcg_const_tl(0); | |
1346 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1347 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1348 | tcg_temp_free(zero); | |
1349 | } | |
1350 | ||
1351 | static void gen_neg(DisasContext *ctx) | |
1352 | { | |
1353 | gen_op_arith_neg(ctx, 0); | |
1354 | } | |
1355 | ||
1356 | static void gen_nego(DisasContext *ctx) | |
1357 | { | |
1358 | gen_op_arith_neg(ctx, 1); | |
1359 | } | |
1360 | ||
79aceca5 | 1361 | /*** Integer logical ***/ |
26d67362 | 1362 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1363 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1364 | { \ |
26d67362 AJ |
1365 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1366 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1367 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1368 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1369 | } |
79aceca5 | 1370 | |
26d67362 | 1371 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1372 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1373 | { \ |
26d67362 | 1374 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1375 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1376 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1377 | } |
1378 | ||
1379 | /* and & and. */ | |
26d67362 | 1380 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1381 | /* andc & andc. */ |
26d67362 | 1382 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1383 | |
54623277 | 1384 | /* andi. */ |
e8eaa2c0 | 1385 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1386 | { |
26d67362 AJ |
1387 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1388 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1389 | } |
e8eaa2c0 | 1390 | |
54623277 | 1391 | /* andis. */ |
e8eaa2c0 | 1392 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1393 | { |
26d67362 AJ |
1394 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1395 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1396 | } |
99e300ef | 1397 | |
54623277 | 1398 | /* cntlzw */ |
99e300ef | 1399 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1400 | { |
a7812ae4 | 1401 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1402 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1403 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1404 | } |
79aceca5 | 1405 | /* eqv & eqv. */ |
26d67362 | 1406 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1407 | /* extsb & extsb. */ |
26d67362 | 1408 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1409 | /* extsh & extsh. */ |
26d67362 | 1410 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1411 | /* nand & nand. */ |
26d67362 | 1412 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1413 | /* nor & nor. */ |
26d67362 | 1414 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1415 | |
54623277 | 1416 | /* or & or. */ |
99e300ef | 1417 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1418 | { |
76a66253 JM |
1419 | int rs, ra, rb; |
1420 | ||
1421 | rs = rS(ctx->opcode); | |
1422 | ra = rA(ctx->opcode); | |
1423 | rb = rB(ctx->opcode); | |
1424 | /* Optimisation for mr. ri case */ | |
1425 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1426 | if (rs != rb) |
1427 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1428 | else | |
1429 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1430 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1431 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1432 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1433 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1434 | #if defined(TARGET_PPC64) |
1435 | } else { | |
26d67362 AJ |
1436 | int prio = 0; |
1437 | ||
c80f84e3 JM |
1438 | switch (rs) { |
1439 | case 1: | |
1440 | /* Set process priority to low */ | |
26d67362 | 1441 | prio = 2; |
c80f84e3 JM |
1442 | break; |
1443 | case 6: | |
1444 | /* Set process priority to medium-low */ | |
26d67362 | 1445 | prio = 3; |
c80f84e3 JM |
1446 | break; |
1447 | case 2: | |
1448 | /* Set process priority to normal */ | |
26d67362 | 1449 | prio = 4; |
c80f84e3 | 1450 | break; |
be147d08 JM |
1451 | #if !defined(CONFIG_USER_ONLY) |
1452 | case 31: | |
76db3ba4 | 1453 | if (ctx->mem_idx > 0) { |
be147d08 | 1454 | /* Set process priority to very low */ |
26d67362 | 1455 | prio = 1; |
be147d08 JM |
1456 | } |
1457 | break; | |
1458 | case 5: | |
76db3ba4 | 1459 | if (ctx->mem_idx > 0) { |
be147d08 | 1460 | /* Set process priority to medium-hight */ |
26d67362 | 1461 | prio = 5; |
be147d08 JM |
1462 | } |
1463 | break; | |
1464 | case 3: | |
76db3ba4 | 1465 | if (ctx->mem_idx > 0) { |
be147d08 | 1466 | /* Set process priority to high */ |
26d67362 | 1467 | prio = 6; |
be147d08 JM |
1468 | } |
1469 | break; | |
be147d08 | 1470 | case 7: |
76db3ba4 | 1471 | if (ctx->mem_idx > 1) { |
be147d08 | 1472 | /* Set process priority to very high */ |
26d67362 | 1473 | prio = 7; |
be147d08 JM |
1474 | } |
1475 | break; | |
be147d08 | 1476 | #endif |
c80f84e3 JM |
1477 | default: |
1478 | /* nop */ | |
1479 | break; | |
1480 | } | |
26d67362 | 1481 | if (prio) { |
a7812ae4 | 1482 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1483 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1484 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1485 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1486 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1487 | tcg_temp_free(t0); |
26d67362 | 1488 | } |
c80f84e3 | 1489 | #endif |
9a64fbe4 | 1490 | } |
9a64fbe4 | 1491 | } |
79aceca5 | 1492 | /* orc & orc. */ |
26d67362 | 1493 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1494 | |
54623277 | 1495 | /* xor & xor. */ |
99e300ef | 1496 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1497 | { |
9a64fbe4 | 1498 | /* Optimisation for "set to zero" case */ |
26d67362 | 1499 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1500 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1501 | else |
1502 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1503 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1504 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1505 | } |
99e300ef | 1506 | |
54623277 | 1507 | /* ori */ |
99e300ef | 1508 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1509 | { |
76a66253 | 1510 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1511 | |
9a64fbe4 FB |
1512 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1513 | /* NOP */ | |
76a66253 | 1514 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1515 | return; |
76a66253 | 1516 | } |
26d67362 | 1517 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1518 | } |
99e300ef | 1519 | |
54623277 | 1520 | /* oris */ |
99e300ef | 1521 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1522 | { |
76a66253 | 1523 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1524 | |
9a64fbe4 FB |
1525 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1526 | /* NOP */ | |
1527 | return; | |
76a66253 | 1528 | } |
26d67362 | 1529 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1530 | } |
99e300ef | 1531 | |
54623277 | 1532 | /* xori */ |
99e300ef | 1533 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1534 | { |
76a66253 | 1535 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1536 | |
1537 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1538 | /* NOP */ | |
1539 | return; | |
1540 | } | |
26d67362 | 1541 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1542 | } |
99e300ef | 1543 | |
54623277 | 1544 | /* xoris */ |
99e300ef | 1545 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1546 | { |
76a66253 | 1547 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1548 | |
1549 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1550 | /* NOP */ | |
1551 | return; | |
1552 | } | |
26d67362 | 1553 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1554 | } |
99e300ef | 1555 | |
54623277 | 1556 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1557 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1558 | { |
eaabeef2 DG |
1559 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1560 | } | |
1561 | ||
1562 | static void gen_popcntw(DisasContext *ctx) | |
1563 | { | |
1564 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1565 | } | |
1566 | ||
d9bce9d9 | 1567 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1568 | /* popcntd: PowerPC 2.06 specification */ |
1569 | static void gen_popcntd(DisasContext *ctx) | |
1570 | { | |
1571 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1572 | } |
eaabeef2 | 1573 | #endif |
d9bce9d9 | 1574 | |
725bcec2 AJ |
1575 | /* prtyw: PowerPC 2.05 specification */ |
1576 | static void gen_prtyw(DisasContext *ctx) | |
1577 | { | |
1578 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1579 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1580 | TCGv t0 = tcg_temp_new(); | |
1581 | tcg_gen_shri_tl(t0, rs, 16); | |
1582 | tcg_gen_xor_tl(ra, rs, t0); | |
1583 | tcg_gen_shri_tl(t0, ra, 8); | |
1584 | tcg_gen_xor_tl(ra, ra, t0); | |
1585 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1586 | tcg_temp_free(t0); | |
1587 | } | |
1588 | ||
1589 | #if defined(TARGET_PPC64) | |
1590 | /* prtyd: PowerPC 2.05 specification */ | |
1591 | static void gen_prtyd(DisasContext *ctx) | |
1592 | { | |
1593 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1594 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1595 | TCGv t0 = tcg_temp_new(); | |
1596 | tcg_gen_shri_tl(t0, rs, 32); | |
1597 | tcg_gen_xor_tl(ra, rs, t0); | |
1598 | tcg_gen_shri_tl(t0, ra, 16); | |
1599 | tcg_gen_xor_tl(ra, ra, t0); | |
1600 | tcg_gen_shri_tl(t0, ra, 8); | |
1601 | tcg_gen_xor_tl(ra, ra, t0); | |
1602 | tcg_gen_andi_tl(ra, ra, 1); | |
1603 | tcg_temp_free(t0); | |
1604 | } | |
1605 | #endif | |
1606 | ||
86ba37ed TM |
1607 | #if defined(TARGET_PPC64) |
1608 | /* bpermd */ | |
1609 | static void gen_bpermd(DisasContext *ctx) | |
1610 | { | |
1611 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
1612 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1613 | } | |
1614 | #endif | |
1615 | ||
d9bce9d9 JM |
1616 | #if defined(TARGET_PPC64) |
1617 | /* extsw & extsw. */ | |
26d67362 | 1618 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1619 | |
54623277 | 1620 | /* cntlzd */ |
99e300ef | 1621 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1622 | { |
a7812ae4 | 1623 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1624 | if (unlikely(Rc(ctx->opcode) != 0)) |
1625 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1626 | } | |
d9bce9d9 JM |
1627 | #endif |
1628 | ||
79aceca5 | 1629 | /*** Integer rotate ***/ |
99e300ef | 1630 | |
54623277 | 1631 | /* rlwimi & rlwimi. */ |
99e300ef | 1632 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1633 | { |
76a66253 | 1634 | uint32_t mb, me, sh; |
79aceca5 FB |
1635 | |
1636 | mb = MB(ctx->opcode); | |
1637 | me = ME(ctx->opcode); | |
76a66253 | 1638 | sh = SH(ctx->opcode); |
d03ef511 | 1639 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
6ea7b35c TM |
1640 | #if defined(TARGET_PPC64) |
1641 | tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1642 | #else | |
d03ef511 | 1643 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
6ea7b35c | 1644 | #endif |
d03ef511 | 1645 | } else { |
d03ef511 | 1646 | target_ulong mask; |
a7812ae4 PB |
1647 | TCGv t1; |
1648 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1649 | #if defined(TARGET_PPC64) |
6ea7b35c TM |
1650 | tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)], |
1651 | cpu_gpr[rS(ctx->opcode)], 32, 32); | |
1652 | tcg_gen_rotli_i64(t0, t0, sh); | |
54843a58 AJ |
1653 | #else |
1654 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1655 | #endif | |
76a66253 | 1656 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1657 | mb += 32; |
1658 | me += 32; | |
76a66253 | 1659 | #endif |
d03ef511 | 1660 | mask = MASK(mb, me); |
a7812ae4 | 1661 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1662 | tcg_gen_andi_tl(t0, t0, mask); |
1663 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1664 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1665 | tcg_temp_free(t0); | |
1666 | tcg_temp_free(t1); | |
1667 | } | |
76a66253 | 1668 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1669 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1670 | } |
99e300ef | 1671 | |
54623277 | 1672 | /* rlwinm & rlwinm. */ |
99e300ef | 1673 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1674 | { |
1675 | uint32_t mb, me, sh; | |
3b46e624 | 1676 | |
79aceca5 FB |
1677 | sh = SH(ctx->opcode); |
1678 | mb = MB(ctx->opcode); | |
1679 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1680 | |
1681 | if (likely(mb == 0 && me == (31 - sh))) { | |
1682 | if (likely(sh == 0)) { | |
1683 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1684 | } else { | |
a7812ae4 | 1685 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1686 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1687 | tcg_gen_shli_tl(t0, t0, sh); | |
1688 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1689 | tcg_temp_free(t0); | |
79aceca5 | 1690 | } |
d03ef511 | 1691 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1692 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1693 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1694 | tcg_gen_shri_tl(t0, t0, mb); | |
1695 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1696 | tcg_temp_free(t0); | |
1697 | } else { | |
a7812ae4 | 1698 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1699 | #if defined(TARGET_PPC64) |
a7f23d0f TM |
1700 | tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)], |
1701 | cpu_gpr[rS(ctx->opcode)], 32, 32); | |
1702 | tcg_gen_rotli_i64(t0, t0, sh); | |
54843a58 AJ |
1703 | #else |
1704 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1705 | #endif | |
76a66253 | 1706 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1707 | mb += 32; |
1708 | me += 32; | |
76a66253 | 1709 | #endif |
d03ef511 AJ |
1710 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1711 | tcg_temp_free(t0); | |
1712 | } | |
76a66253 | 1713 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1714 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1715 | } |
99e300ef | 1716 | |
54623277 | 1717 | /* rlwnm & rlwnm. */ |
99e300ef | 1718 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1719 | { |
1720 | uint32_t mb, me; | |
54843a58 AJ |
1721 | TCGv t0; |
1722 | #if defined(TARGET_PPC64) | |
1c0a150f | 1723 | TCGv t1; |
54843a58 | 1724 | #endif |
79aceca5 FB |
1725 | |
1726 | mb = MB(ctx->opcode); | |
1727 | me = ME(ctx->opcode); | |
a7812ae4 | 1728 | t0 = tcg_temp_new(); |
d03ef511 | 1729 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1730 | #if defined(TARGET_PPC64) |
1c0a150f TM |
1731 | t1 = tcg_temp_new_i64(); |
1732 | tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)], | |
1733 | cpu_gpr[rS(ctx->opcode)], 32, 32); | |
1734 | tcg_gen_rotl_i64(t0, t1, t0); | |
1735 | tcg_temp_free_i64(t1); | |
54843a58 AJ |
1736 | #else |
1737 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1738 | #endif | |
76a66253 JM |
1739 | if (unlikely(mb != 0 || me != 31)) { |
1740 | #if defined(TARGET_PPC64) | |
1741 | mb += 32; | |
1742 | me += 32; | |
1743 | #endif | |
54843a58 | 1744 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1745 | } else { |
1c0a150f TM |
1746 | #if defined(TARGET_PPC64) |
1747 | tcg_gen_andi_tl(t0, t0, MASK(32, 63)); | |
1748 | #endif | |
54843a58 | 1749 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1750 | } |
54843a58 | 1751 | tcg_temp_free(t0); |
76a66253 | 1752 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1753 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1754 | } |
1755 | ||
d9bce9d9 JM |
1756 | #if defined(TARGET_PPC64) |
1757 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1758 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1759 | { \ |
1760 | gen_##name(ctx, 0); \ | |
1761 | } \ | |
e8eaa2c0 BS |
1762 | \ |
1763 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1764 | { \ |
1765 | gen_##name(ctx, 1); \ | |
1766 | } | |
1767 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1768 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1769 | { \ |
1770 | gen_##name(ctx, 0, 0); \ | |
1771 | } \ | |
e8eaa2c0 BS |
1772 | \ |
1773 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1774 | { \ |
1775 | gen_##name(ctx, 0, 1); \ | |
1776 | } \ | |
e8eaa2c0 BS |
1777 | \ |
1778 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1779 | { \ |
1780 | gen_##name(ctx, 1, 0); \ | |
1781 | } \ | |
e8eaa2c0 BS |
1782 | \ |
1783 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1784 | { \ |
1785 | gen_##name(ctx, 1, 1); \ | |
1786 | } | |
51789c41 | 1787 | |
636aa200 BS |
1788 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1789 | uint32_t sh) | |
51789c41 | 1790 | { |
d03ef511 AJ |
1791 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1792 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1793 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1794 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1795 | } else { | |
a7812ae4 | 1796 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1797 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1798 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1799 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1800 | } else { |
1801 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1802 | } |
d03ef511 | 1803 | tcg_temp_free(t0); |
51789c41 | 1804 | } |
51789c41 | 1805 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1806 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1807 | } |
d9bce9d9 | 1808 | /* rldicl - rldicl. */ |
636aa200 | 1809 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1810 | { |
51789c41 | 1811 | uint32_t sh, mb; |
d9bce9d9 | 1812 | |
9d53c753 JM |
1813 | sh = SH(ctx->opcode) | (shn << 5); |
1814 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1815 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1816 | } |
51789c41 | 1817 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1818 | /* rldicr - rldicr. */ |
636aa200 | 1819 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1820 | { |
51789c41 | 1821 | uint32_t sh, me; |
d9bce9d9 | 1822 | |
9d53c753 JM |
1823 | sh = SH(ctx->opcode) | (shn << 5); |
1824 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1825 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1826 | } |
51789c41 | 1827 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1828 | /* rldic - rldic. */ |
636aa200 | 1829 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1830 | { |
51789c41 | 1831 | uint32_t sh, mb; |
d9bce9d9 | 1832 | |
9d53c753 JM |
1833 | sh = SH(ctx->opcode) | (shn << 5); |
1834 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1835 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1836 | } | |
1837 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1838 | ||
636aa200 | 1839 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1840 | { |
54843a58 | 1841 | TCGv t0; |
d03ef511 | 1842 | |
a7812ae4 | 1843 | t0 = tcg_temp_new(); |
d03ef511 | 1844 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1845 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1846 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1847 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1848 | } else { | |
1849 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1850 | } | |
1851 | tcg_temp_free(t0); | |
51789c41 | 1852 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1853 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1854 | } |
51789c41 | 1855 | |
d9bce9d9 | 1856 | /* rldcl - rldcl. */ |
636aa200 | 1857 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1858 | { |
51789c41 | 1859 | uint32_t mb; |
d9bce9d9 | 1860 | |
9d53c753 | 1861 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1862 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1863 | } |
36081602 | 1864 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1865 | /* rldcr - rldcr. */ |
636aa200 | 1866 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1867 | { |
51789c41 | 1868 | uint32_t me; |
d9bce9d9 | 1869 | |
9d53c753 | 1870 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1871 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1872 | } |
36081602 | 1873 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1874 | /* rldimi - rldimi. */ |
636aa200 | 1875 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1876 | { |
271a916e | 1877 | uint32_t sh, mb, me; |
d9bce9d9 | 1878 | |
9d53c753 JM |
1879 | sh = SH(ctx->opcode) | (shn << 5); |
1880 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1881 | me = 63 - sh; |
d03ef511 AJ |
1882 | if (unlikely(sh == 0 && mb == 0)) { |
1883 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1884 | } else { | |
1885 | TCGv t0, t1; | |
1886 | target_ulong mask; | |
1887 | ||
a7812ae4 | 1888 | t0 = tcg_temp_new(); |
54843a58 | 1889 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1890 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1891 | mask = MASK(mb, me); |
1892 | tcg_gen_andi_tl(t0, t0, mask); | |
1893 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1894 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1895 | tcg_temp_free(t0); | |
1896 | tcg_temp_free(t1); | |
51789c41 | 1897 | } |
51789c41 | 1898 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1899 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1900 | } |
36081602 | 1901 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1902 | #endif |
1903 | ||
79aceca5 | 1904 | /*** Integer shift ***/ |
99e300ef | 1905 | |
54623277 | 1906 | /* slw & slw. */ |
99e300ef | 1907 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1908 | { |
7fd6bf7d | 1909 | TCGv t0, t1; |
26d67362 | 1910 | |
7fd6bf7d AJ |
1911 | t0 = tcg_temp_new(); |
1912 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1913 | #if defined(TARGET_PPC64) | |
1914 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1915 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1916 | #else | |
1917 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1918 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1919 | #endif | |
1920 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1921 | t1 = tcg_temp_new(); | |
1922 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1923 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1924 | tcg_temp_free(t1); | |
fea0c503 | 1925 | tcg_temp_free(t0); |
7fd6bf7d | 1926 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1927 | if (unlikely(Rc(ctx->opcode) != 0)) |
1928 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1929 | } | |
99e300ef | 1930 | |
54623277 | 1931 | /* sraw & sraw. */ |
99e300ef | 1932 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1933 | { |
d15f74fb | 1934 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1935 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1936 | if (unlikely(Rc(ctx->opcode) != 0)) |
1937 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1938 | } | |
99e300ef | 1939 | |
54623277 | 1940 | /* srawi & srawi. */ |
99e300ef | 1941 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1942 | { |
26d67362 | 1943 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
1944 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1945 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
1946 | if (sh == 0) { | |
1947 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 1948 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1949 | } else { |
ba4af3e4 RH |
1950 | TCGv t0; |
1951 | tcg_gen_ext32s_tl(dst, src); | |
1952 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
1953 | t0 = tcg_temp_new(); | |
1954 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
1955 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
1956 | tcg_temp_free(t0); | |
1957 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
1958 | tcg_gen_sari_tl(dst, dst, sh); | |
1959 | } | |
1960 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1961 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 1962 | } |
79aceca5 | 1963 | } |
99e300ef | 1964 | |
54623277 | 1965 | /* srw & srw. */ |
99e300ef | 1966 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1967 | { |
fea0c503 | 1968 | TCGv t0, t1; |
d9bce9d9 | 1969 | |
7fd6bf7d AJ |
1970 | t0 = tcg_temp_new(); |
1971 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1972 | #if defined(TARGET_PPC64) | |
1973 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1974 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1975 | #else | |
1976 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1977 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1978 | #endif | |
1979 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1980 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1981 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1982 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1983 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1984 | tcg_temp_free(t1); |
fea0c503 | 1985 | tcg_temp_free(t0); |
26d67362 AJ |
1986 | if (unlikely(Rc(ctx->opcode) != 0)) |
1987 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1988 | } | |
54623277 | 1989 | |
d9bce9d9 JM |
1990 | #if defined(TARGET_PPC64) |
1991 | /* sld & sld. */ | |
99e300ef | 1992 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1993 | { |
7fd6bf7d | 1994 | TCGv t0, t1; |
26d67362 | 1995 | |
7fd6bf7d AJ |
1996 | t0 = tcg_temp_new(); |
1997 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1998 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1999 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2000 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2001 | t1 = tcg_temp_new(); | |
2002 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2003 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2004 | tcg_temp_free(t1); | |
fea0c503 | 2005 | tcg_temp_free(t0); |
26d67362 AJ |
2006 | if (unlikely(Rc(ctx->opcode) != 0)) |
2007 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2008 | } | |
99e300ef | 2009 | |
54623277 | 2010 | /* srad & srad. */ |
99e300ef | 2011 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2012 | { |
d15f74fb | 2013 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2014 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2015 | if (unlikely(Rc(ctx->opcode) != 0)) |
2016 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2017 | } | |
d9bce9d9 | 2018 | /* sradi & sradi. */ |
636aa200 | 2019 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2020 | { |
26d67362 | 2021 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2022 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2023 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2024 | if (sh == 0) { | |
2025 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2026 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 2027 | } else { |
ba4af3e4 RH |
2028 | TCGv t0; |
2029 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2030 | t0 = tcg_temp_new(); | |
2031 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2032 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2033 | tcg_temp_free(t0); | |
2034 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
2035 | tcg_gen_sari_tl(dst, src, sh); | |
2036 | } | |
2037 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2038 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2039 | } |
d9bce9d9 | 2040 | } |
e8eaa2c0 BS |
2041 | |
2042 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2043 | { |
2044 | gen_sradi(ctx, 0); | |
2045 | } | |
e8eaa2c0 BS |
2046 | |
2047 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2048 | { |
2049 | gen_sradi(ctx, 1); | |
2050 | } | |
99e300ef | 2051 | |
54623277 | 2052 | /* srd & srd. */ |
99e300ef | 2053 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2054 | { |
7fd6bf7d | 2055 | TCGv t0, t1; |
26d67362 | 2056 | |
7fd6bf7d AJ |
2057 | t0 = tcg_temp_new(); |
2058 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2059 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2060 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2061 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2062 | t1 = tcg_temp_new(); | |
2063 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2064 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2065 | tcg_temp_free(t1); | |
fea0c503 | 2066 | tcg_temp_free(t0); |
26d67362 AJ |
2067 | if (unlikely(Rc(ctx->opcode) != 0)) |
2068 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2069 | } | |
d9bce9d9 | 2070 | #endif |
79aceca5 FB |
2071 | |
2072 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 2073 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 2074 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2075 | { \ |
76a66253 | 2076 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2077 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2078 | return; \ |
2079 | } \ | |
eb44b959 AJ |
2080 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2081 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2082 | gen_reset_fpstatus(); \ |
8e703949 BS |
2083 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2084 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2085 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2086 | if (isfloat) { \ |
8e703949 BS |
2087 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2088 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2089 | } \ |
af12906f AJ |
2090 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
2091 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
2092 | } |
2093 | ||
7c58044c JM |
2094 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
2095 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
2096 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 2097 | |
7c58044c | 2098 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2099 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2100 | { \ |
76a66253 | 2101 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2102 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2103 | return; \ |
2104 | } \ | |
eb44b959 AJ |
2105 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2106 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2107 | gen_reset_fpstatus(); \ |
8e703949 BS |
2108 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2109 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2110 | cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2111 | if (isfloat) { \ |
8e703949 BS |
2112 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2113 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2114 | } \ |
af12906f AJ |
2115 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2116 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2117 | } |
7c58044c JM |
2118 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2119 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2120 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2121 | |
7c58044c | 2122 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2123 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2124 | { \ |
76a66253 | 2125 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2126 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2127 | return; \ |
2128 | } \ | |
eb44b959 AJ |
2129 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2130 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2131 | gen_reset_fpstatus(); \ |
8e703949 BS |
2132 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2133 | cpu_fpr[rA(ctx->opcode)], \ | |
2134 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2135 | if (isfloat) { \ |
8e703949 BS |
2136 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2137 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2138 | } \ |
af12906f AJ |
2139 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2140 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2141 | } |
7c58044c JM |
2142 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2143 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2144 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2145 | |
7c58044c | 2146 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 2147 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2148 | { \ |
76a66253 | 2149 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2150 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2151 | return; \ |
2152 | } \ | |
eb44b959 AJ |
2153 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2154 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2155 | gen_reset_fpstatus(); \ |
8e703949 BS |
2156 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2157 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2158 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2159 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2160 | } |
2161 | ||
7c58044c | 2162 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2163 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2164 | { \ |
76a66253 | 2165 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2166 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2167 | return; \ |
2168 | } \ | |
eb44b959 AJ |
2169 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2170 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2171 | gen_reset_fpstatus(); \ |
8e703949 BS |
2172 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2173 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2174 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2175 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2176 | } |
2177 | ||
9a64fbe4 | 2178 | /* fadd - fadds */ |
7c58044c | 2179 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2180 | /* fdiv - fdivs */ |
7c58044c | 2181 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2182 | /* fmul - fmuls */ |
7c58044c | 2183 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2184 | |
d7e4b87e | 2185 | /* fre */ |
7c58044c | 2186 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2187 | |
a750fc0b | 2188 | /* fres */ |
7c58044c | 2189 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2190 | |
a750fc0b | 2191 | /* frsqrte */ |
7c58044c JM |
2192 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2193 | ||
2194 | /* frsqrtes */ | |
99e300ef | 2195 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2196 | { |
af12906f | 2197 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2198 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2199 | return; |
2200 | } | |
eb44b959 AJ |
2201 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2202 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f | 2203 | gen_reset_fpstatus(); |
8e703949 BS |
2204 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2205 | cpu_fpr[rB(ctx->opcode)]); | |
2206 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2207 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2208 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
7c58044c | 2209 | } |
79aceca5 | 2210 | |
a750fc0b | 2211 | /* fsel */ |
7c58044c | 2212 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2213 | /* fsub - fsubs */ |
7c58044c | 2214 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2215 | /* Optional: */ |
99e300ef | 2216 | |
54623277 | 2217 | /* fsqrt */ |
99e300ef | 2218 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2219 | { |
76a66253 | 2220 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2221 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2222 | return; |
2223 | } | |
eb44b959 AJ |
2224 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2225 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2226 | gen_reset_fpstatus(); |
8e703949 BS |
2227 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2228 | cpu_fpr[rB(ctx->opcode)]); | |
af12906f | 2229 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
c7d344af | 2230 | } |
79aceca5 | 2231 | |
99e300ef | 2232 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2233 | { |
76a66253 | 2234 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2235 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2236 | return; |
2237 | } | |
eb44b959 AJ |
2238 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2239 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2240 | gen_reset_fpstatus(); |
8e703949 BS |
2241 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2242 | cpu_fpr[rB(ctx->opcode)]); | |
2243 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2244 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2245 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2246 | } |
2247 | ||
2248 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2249 | /* fmadd - fmadds */ |
7c58044c | 2250 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2251 | /* fmsub - fmsubs */ |
7c58044c | 2252 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2253 | /* fnmadd - fnmadds */ |
7c58044c | 2254 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2255 | /* fnmsub - fnmsubs */ |
7c58044c | 2256 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2257 | |
2258 | /*** Floating-Point round & convert ***/ | |
2259 | /* fctiw */ | |
7c58044c | 2260 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
fab7fe42 TM |
2261 | /* fctiwu */ |
2262 | GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206); | |
79aceca5 | 2263 | /* fctiwz */ |
7c58044c | 2264 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
fab7fe42 TM |
2265 | /* fctiwuz */ |
2266 | GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206); | |
79aceca5 | 2267 | /* frsp */ |
7c58044c | 2268 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2269 | #if defined(TARGET_PPC64) |
2270 | /* fcfid */ | |
7c58044c | 2271 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
28288b48 TM |
2272 | /* fcfids */ |
2273 | GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206); | |
2274 | /* fcfidu */ | |
2275 | GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); | |
2276 | /* fcfidus */ | |
2277 | GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); | |
426613db | 2278 | /* fctid */ |
7c58044c | 2279 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
fab7fe42 TM |
2280 | /* fctidu */ |
2281 | GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206); | |
426613db | 2282 | /* fctidz */ |
7c58044c | 2283 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
fab7fe42 TM |
2284 | /* fctidu */ |
2285 | GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206); | |
426613db | 2286 | #endif |
79aceca5 | 2287 | |
d7e4b87e | 2288 | /* frin */ |
7c58044c | 2289 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2290 | /* friz */ |
7c58044c | 2291 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2292 | /* frip */ |
7c58044c | 2293 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2294 | /* frim */ |
7c58044c | 2295 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2296 | |
da29cb7b TM |
2297 | static void gen_ftdiv(DisasContext *ctx) |
2298 | { | |
2299 | if (unlikely(!ctx->fpu_enabled)) { | |
2300 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2301 | return; | |
2302 | } | |
2303 | gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2304 | cpu_fpr[rB(ctx->opcode)]); | |
2305 | } | |
2306 | ||
6d41d146 TM |
2307 | static void gen_ftsqrt(DisasContext *ctx) |
2308 | { | |
2309 | if (unlikely(!ctx->fpu_enabled)) { | |
2310 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2311 | return; | |
2312 | } | |
2313 | gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2314 | } | |
2315 | ||
da29cb7b TM |
2316 | |
2317 | ||
79aceca5 | 2318 | /*** Floating-Point compare ***/ |
99e300ef | 2319 | |
54623277 | 2320 | /* fcmpo */ |
99e300ef | 2321 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2322 | { |
330c483b | 2323 | TCGv_i32 crf; |
76a66253 | 2324 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2325 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2326 | return; |
2327 | } | |
eb44b959 AJ |
2328 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2329 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2330 | gen_reset_fpstatus(); |
9a819377 | 2331 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2332 | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2333 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2334 | tcg_temp_free_i32(crf); |
8e703949 | 2335 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2336 | } |
2337 | ||
2338 | /* fcmpu */ | |
99e300ef | 2339 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2340 | { |
330c483b | 2341 | TCGv_i32 crf; |
76a66253 | 2342 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2343 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2344 | return; |
2345 | } | |
eb44b959 AJ |
2346 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2347 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2348 | gen_reset_fpstatus(); |
9a819377 | 2349 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2350 | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2351 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2352 | tcg_temp_free_i32(crf); |
8e703949 | 2353 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2354 | } |
2355 | ||
9a64fbe4 FB |
2356 | /*** Floating-point move ***/ |
2357 | /* fabs */ | |
7c58044c | 2358 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2359 | static void gen_fabs(DisasContext *ctx) |
2360 | { | |
2361 | if (unlikely(!ctx->fpu_enabled)) { | |
2362 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2363 | return; | |
2364 | } | |
2365 | tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2366 | ~(1ULL << 63)); | |
2367 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2368 | } | |
9a64fbe4 FB |
2369 | |
2370 | /* fmr - fmr. */ | |
7c58044c | 2371 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2372 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2373 | { |
76a66253 | 2374 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2375 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2376 | return; |
2377 | } | |
af12906f AJ |
2378 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2379 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2380 | } |
2381 | ||
2382 | /* fnabs */ | |
7c58044c | 2383 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2384 | static void gen_fnabs(DisasContext *ctx) |
2385 | { | |
2386 | if (unlikely(!ctx->fpu_enabled)) { | |
2387 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2388 | return; | |
2389 | } | |
2390 | tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2391 | 1ULL << 63); | |
2392 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2393 | } | |
2394 | ||
9a64fbe4 | 2395 | /* fneg */ |
7c58044c | 2396 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2397 | static void gen_fneg(DisasContext *ctx) |
2398 | { | |
2399 | if (unlikely(!ctx->fpu_enabled)) { | |
2400 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2401 | return; | |
2402 | } | |
2403 | tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2404 | 1ULL << 63); | |
2405 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2406 | } | |
9a64fbe4 | 2407 | |
f0332888 AJ |
2408 | /* fcpsgn: PowerPC 2.05 specification */ |
2409 | /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ | |
2410 | static void gen_fcpsgn(DisasContext *ctx) | |
2411 | { | |
2412 | if (unlikely(!ctx->fpu_enabled)) { | |
2413 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2414 | return; | |
2415 | } | |
2416 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2417 | cpu_fpr[rB(ctx->opcode)], 0, 63); | |
2418 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2419 | } | |
2420 | ||
097ec5d8 TM |
2421 | static void gen_fmrgew(DisasContext *ctx) |
2422 | { | |
2423 | TCGv_i64 b0; | |
2424 | if (unlikely(!ctx->fpu_enabled)) { | |
2425 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2426 | return; | |
2427 | } | |
2428 | b0 = tcg_temp_new_i64(); | |
2429 | tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32); | |
2430 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2431 | b0, 0, 32); | |
2432 | tcg_temp_free_i64(b0); | |
2433 | } | |
2434 | ||
2435 | static void gen_fmrgow(DisasContext *ctx) | |
2436 | { | |
2437 | if (unlikely(!ctx->fpu_enabled)) { | |
2438 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2439 | return; | |
2440 | } | |
2441 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], | |
2442 | cpu_fpr[rB(ctx->opcode)], | |
2443 | cpu_fpr[rA(ctx->opcode)], | |
2444 | 32, 32); | |
2445 | } | |
2446 | ||
79aceca5 | 2447 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2448 | |
54623277 | 2449 | /* mcrfs */ |
99e300ef | 2450 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2451 | { |
30304420 | 2452 | TCGv tmp = tcg_temp_new(); |
7c58044c JM |
2453 | int bfa; |
2454 | ||
76a66253 | 2455 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2456 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2457 | return; |
2458 | } | |
7c58044c | 2459 | bfa = 4 * (7 - crfS(ctx->opcode)); |
30304420 DG |
2460 | tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); |
2461 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); | |
2462 | tcg_temp_free(tmp); | |
e1571908 | 2463 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
30304420 | 2464 | tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2465 | } |
2466 | ||
2467 | /* mffs */ | |
99e300ef | 2468 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2469 | { |
76a66253 | 2470 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2471 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2472 | return; |
2473 | } | |
7c58044c | 2474 | gen_reset_fpstatus(); |
30304420 | 2475 | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
af12906f | 2476 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2477 | } |
2478 | ||
2479 | /* mtfsb0 */ | |
99e300ef | 2480 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2481 | { |
fb0eaffc | 2482 | uint8_t crb; |
3b46e624 | 2483 | |
76a66253 | 2484 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2485 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2486 | return; |
2487 | } | |
6e35d524 | 2488 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2489 | gen_reset_fpstatus(); |
6e35d524 | 2490 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2491 | TCGv_i32 t0; |
2492 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2493 | gen_update_nip(ctx, ctx->nip - 4); | |
2494 | t0 = tcg_const_i32(crb); | |
8e703949 | 2495 | gen_helper_fpscr_clrbit(cpu_env, t0); |
6e35d524 AJ |
2496 | tcg_temp_free_i32(t0); |
2497 | } | |
7c58044c | 2498 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2499 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2500 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c | 2501 | } |
79aceca5 FB |
2502 | } |
2503 | ||
2504 | /* mtfsb1 */ | |
99e300ef | 2505 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2506 | { |
fb0eaffc | 2507 | uint8_t crb; |
3b46e624 | 2508 | |
76a66253 | 2509 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2510 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2511 | return; |
2512 | } | |
6e35d524 | 2513 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2514 | gen_reset_fpstatus(); |
2515 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2516 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2517 | TCGv_i32 t0; |
2518 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2519 | gen_update_nip(ctx, ctx->nip - 4); | |
2520 | t0 = tcg_const_i32(crb); | |
8e703949 | 2521 | gen_helper_fpscr_setbit(cpu_env, t0); |
0f2f39c2 | 2522 | tcg_temp_free_i32(t0); |
af12906f | 2523 | } |
7c58044c | 2524 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2525 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2526 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2527 | } |
2528 | /* We can raise a differed exception */ | |
8e703949 | 2529 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2530 | } |
2531 | ||
2532 | /* mtfsf */ | |
99e300ef | 2533 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2534 | { |
0f2f39c2 | 2535 | TCGv_i32 t0; |
7d08d856 | 2536 | int flm, l, w; |
af12906f | 2537 | |
76a66253 | 2538 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2539 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2540 | return; |
2541 | } | |
7d08d856 AJ |
2542 | flm = FPFLM(ctx->opcode); |
2543 | l = FPL(ctx->opcode); | |
2544 | w = FPW(ctx->opcode); | |
2545 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2546 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2547 | return; | |
2548 | } | |
eb44b959 AJ |
2549 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2550 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2551 | gen_reset_fpstatus(); |
7d08d856 AJ |
2552 | if (l) { |
2553 | t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); | |
2554 | } else { | |
2555 | t0 = tcg_const_i32(flm << (w * 8)); | |
2556 | } | |
8e703949 | 2557 | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2558 | tcg_temp_free_i32(t0); |
7c58044c | 2559 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2560 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2561 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2562 | } |
2563 | /* We can raise a differed exception */ | |
8e703949 | 2564 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2565 | } |
2566 | ||
2567 | /* mtfsfi */ | |
99e300ef | 2568 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2569 | { |
7d08d856 | 2570 | int bf, sh, w; |
0f2f39c2 AJ |
2571 | TCGv_i64 t0; |
2572 | TCGv_i32 t1; | |
7c58044c | 2573 | |
76a66253 | 2574 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2575 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2576 | return; |
2577 | } | |
7d08d856 AJ |
2578 | w = FPW(ctx->opcode); |
2579 | bf = FPBF(ctx->opcode); | |
2580 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2581 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2582 | return; | |
2583 | } | |
2584 | sh = (8 * w) + 7 - bf; | |
eb44b959 AJ |
2585 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2586 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2587 | gen_reset_fpstatus(); |
7d08d856 | 2588 | t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); |
af12906f | 2589 | t1 = tcg_const_i32(1 << sh); |
8e703949 | 2590 | gen_helper_store_fpscr(cpu_env, t0, t1); |
0f2f39c2 AJ |
2591 | tcg_temp_free_i64(t0); |
2592 | tcg_temp_free_i32(t1); | |
7c58044c | 2593 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2594 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2595 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2596 | } |
2597 | /* We can raise a differed exception */ | |
8e703949 | 2598 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2599 | } |
2600 | ||
76a66253 JM |
2601 | /*** Addressing modes ***/ |
2602 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2603 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2604 | target_long maskl) | |
76a66253 JM |
2605 | { |
2606 | target_long simm = SIMM(ctx->opcode); | |
2607 | ||
be147d08 | 2608 | simm &= ~maskl; |
76db3ba4 | 2609 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2610 | if (NARROW_MODE(ctx)) { |
2611 | simm = (uint32_t)simm; | |
2612 | } | |
e2be8d8d | 2613 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2614 | } else if (likely(simm != 0)) { |
e2be8d8d | 2615 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2616 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2617 | tcg_gen_ext32u_tl(EA, EA); |
2618 | } | |
76db3ba4 | 2619 | } else { |
c791fe84 | 2620 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2621 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2622 | } else { |
2623 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2624 | } | |
76db3ba4 | 2625 | } |
76a66253 JM |
2626 | } |
2627 | ||
636aa200 | 2628 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2629 | { |
76db3ba4 | 2630 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2631 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2632 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2633 | } else { |
2634 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2635 | } | |
76db3ba4 | 2636 | } else { |
e2be8d8d | 2637 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2638 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2639 | tcg_gen_ext32u_tl(EA, EA); |
2640 | } | |
76db3ba4 | 2641 | } |
76a66253 JM |
2642 | } |
2643 | ||
636aa200 | 2644 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2645 | { |
76db3ba4 | 2646 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2647 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2648 | } else if (NARROW_MODE(ctx)) { |
2649 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2650 | } else { |
c791fe84 | 2651 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2652 | } |
2653 | } | |
2654 | ||
636aa200 BS |
2655 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2656 | target_long val) | |
76db3ba4 AJ |
2657 | { |
2658 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2659 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2660 | tcg_gen_ext32u_tl(ret, ret); |
2661 | } | |
76a66253 JM |
2662 | } |
2663 | ||
636aa200 | 2664 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 AJ |
2665 | { |
2666 | int l1 = gen_new_label(); | |
2667 | TCGv t0 = tcg_temp_new(); | |
2668 | TCGv_i32 t1, t2; | |
2669 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2670 | gen_update_nip(ctx, ctx->nip - 4); | |
2671 | tcg_gen_andi_tl(t0, EA, mask); | |
2672 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2673 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2674 | t2 = tcg_const_i32(0); | |
e5f17ac6 | 2675 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2676 | tcg_temp_free_i32(t1); |
2677 | tcg_temp_free_i32(t2); | |
2678 | gen_set_label(l1); | |
2679 | tcg_temp_free(t0); | |
2680 | } | |
2681 | ||
7863667f | 2682 | /*** Integer load ***/ |
636aa200 | 2683 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2684 | { |
2685 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2686 | } | |
2687 | ||
636aa200 | 2688 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 | 2689 | { |
e22c357b DK |
2690 | TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask; |
2691 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2692 | } |
2693 | ||
636aa200 | 2694 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2695 | { |
e22c357b DK |
2696 | TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask; |
2697 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2698 | } |
2699 | ||
636aa200 | 2700 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2701 | { |
e22c357b DK |
2702 | TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask; |
2703 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2704 | } |
2705 | ||
f976b09e AG |
2706 | static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2707 | { | |
2708 | TCGv tmp = tcg_temp_new(); | |
2709 | gen_qemu_ld32u(ctx, tmp, addr); | |
2710 | tcg_gen_extu_tl_i64(val, tmp); | |
2711 | tcg_temp_free(tmp); | |
2712 | } | |
2713 | ||
636aa200 | 2714 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2715 | { |
e22c357b DK |
2716 | TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask; |
2717 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2718 | } |
2719 | ||
cac7f0ba TM |
2720 | static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2721 | { | |
2722 | TCGv tmp = tcg_temp_new(); | |
2723 | gen_qemu_ld32s(ctx, tmp, addr); | |
2724 | tcg_gen_ext_tl_i64(val, tmp); | |
2725 | tcg_temp_free(tmp); | |
2726 | } | |
2727 | ||
636aa200 | 2728 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2729 | { |
e22c357b DK |
2730 | TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask; |
2731 | tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2732 | } |
2733 | ||
636aa200 | 2734 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2735 | { |
76db3ba4 | 2736 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2737 | } |
2738 | ||
636aa200 | 2739 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2740 | { |
e22c357b DK |
2741 | TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask; |
2742 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2743 | } |
2744 | ||
636aa200 | 2745 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2746 | { |
e22c357b DK |
2747 | TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask; |
2748 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2749 | } |
2750 | ||
f976b09e AG |
2751 | static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2752 | { | |
2753 | TCGv tmp = tcg_temp_new(); | |
2754 | tcg_gen_trunc_i64_tl(tmp, val); | |
2755 | gen_qemu_st32(ctx, tmp, addr); | |
2756 | tcg_temp_free(tmp); | |
2757 | } | |
2758 | ||
636aa200 | 2759 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2760 | { |
e22c357b DK |
2761 | TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask; |
2762 | tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2763 | } |
2764 | ||
0c8aacd4 | 2765 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2766 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2767 | { \ |
76db3ba4 AJ |
2768 | TCGv EA; \ |
2769 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2770 | EA = tcg_temp_new(); \ | |
2771 | gen_addr_imm_index(ctx, EA, 0); \ | |
2772 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2773 | tcg_temp_free(EA); \ |
79aceca5 FB |
2774 | } |
2775 | ||
0c8aacd4 | 2776 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2777 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2778 | { \ |
b61f2753 | 2779 | TCGv EA; \ |
76a66253 JM |
2780 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2781 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2782 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2783 | return; \ |
9a64fbe4 | 2784 | } \ |
76db3ba4 | 2785 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2786 | EA = tcg_temp_new(); \ |
9d53c753 | 2787 | if (type == PPC_64B) \ |
76db3ba4 | 2788 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2789 | else \ |
76db3ba4 AJ |
2790 | gen_addr_imm_index(ctx, EA, 0); \ |
2791 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2792 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2793 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2794 | } |
2795 | ||
0c8aacd4 | 2796 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2797 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2798 | { \ |
b61f2753 | 2799 | TCGv EA; \ |
76a66253 JM |
2800 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2801 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2802 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2803 | return; \ |
9a64fbe4 | 2804 | } \ |
76db3ba4 | 2805 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2806 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2807 | gen_addr_reg_index(ctx, EA); \ |
2808 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2809 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2810 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2811 | } |
2812 | ||
cd6e9320 | 2813 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
99e300ef | 2814 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2815 | { \ |
76db3ba4 AJ |
2816 | TCGv EA; \ |
2817 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2818 | EA = tcg_temp_new(); \ | |
2819 | gen_addr_reg_index(ctx, EA); \ | |
2820 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2821 | tcg_temp_free(EA); \ |
79aceca5 | 2822 | } |
cd6e9320 TH |
2823 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2824 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2825 | |
0c8aacd4 AJ |
2826 | #define GEN_LDS(name, ldop, op, type) \ |
2827 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2828 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2829 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2830 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2831 | |
2832 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2833 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2834 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2835 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2836 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2837 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2838 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2839 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2840 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2841 | /* lwaux */ |
0c8aacd4 | 2842 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2843 | /* lwax */ |
0c8aacd4 | 2844 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2845 | /* ldux */ |
0c8aacd4 | 2846 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2847 | /* ldx */ |
0c8aacd4 | 2848 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2849 | |
2850 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2851 | { |
b61f2753 | 2852 | TCGv EA; |
d9bce9d9 JM |
2853 | if (Rc(ctx->opcode)) { |
2854 | if (unlikely(rA(ctx->opcode) == 0 || | |
2855 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2856 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2857 | return; |
2858 | } | |
2859 | } | |
76db3ba4 | 2860 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2861 | EA = tcg_temp_new(); |
76db3ba4 | 2862 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2863 | if (ctx->opcode & 0x02) { |
2864 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2865 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2866 | } else { |
2867 | /* ld - ldu */ | |
76db3ba4 | 2868 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2869 | } |
d9bce9d9 | 2870 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2871 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2872 | tcg_temp_free(EA); | |
d9bce9d9 | 2873 | } |
99e300ef | 2874 | |
54623277 | 2875 | /* lq */ |
99e300ef | 2876 | static void gen_lq(DisasContext *ctx) |
be147d08 | 2877 | { |
be147d08 | 2878 | int ra, rd; |
b61f2753 | 2879 | TCGv EA; |
be147d08 | 2880 | |
e0498daa TM |
2881 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2882 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2883 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2884 | ||
2885 | if (!legal_in_user_mode && is_user_mode(ctx)) { | |
e06fcd75 | 2886 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2887 | return; |
2888 | } | |
e0498daa TM |
2889 | |
2890 | if (!le_is_supported && ctx->le_mode) { | |
2891 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); | |
2892 | return; | |
2893 | } | |
2894 | ||
be147d08 JM |
2895 | ra = rA(ctx->opcode); |
2896 | rd = rD(ctx->opcode); | |
2897 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2898 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2899 | return; |
2900 | } | |
e0498daa | 2901 | |
76db3ba4 | 2902 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2903 | EA = tcg_temp_new(); |
76db3ba4 | 2904 | gen_addr_imm_index(ctx, EA, 0x0F); |
e0498daa | 2905 | |
e22c357b DK |
2906 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary |
2907 | 64-bit byteswap already. */ | |
e0498daa TM |
2908 | if (unlikely(ctx->le_mode)) { |
2909 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
2910 | gen_addr_add(ctx, EA, EA, 8); | |
2911 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2912 | } else { | |
2913 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2914 | gen_addr_add(ctx, EA, EA, 8); | |
2915 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
2916 | } | |
b61f2753 | 2917 | tcg_temp_free(EA); |
be147d08 | 2918 | } |
d9bce9d9 | 2919 | #endif |
79aceca5 FB |
2920 | |
2921 | /*** Integer store ***/ | |
0c8aacd4 | 2922 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2923 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2924 | { \ |
76db3ba4 AJ |
2925 | TCGv EA; \ |
2926 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2927 | EA = tcg_temp_new(); \ | |
2928 | gen_addr_imm_index(ctx, EA, 0); \ | |
2929 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2930 | tcg_temp_free(EA); \ |
79aceca5 FB |
2931 | } |
2932 | ||
0c8aacd4 | 2933 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2934 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2935 | { \ |
b61f2753 | 2936 | TCGv EA; \ |
76a66253 | 2937 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2938 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2939 | return; \ |
9a64fbe4 | 2940 | } \ |
76db3ba4 | 2941 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2942 | EA = tcg_temp_new(); \ |
9d53c753 | 2943 | if (type == PPC_64B) \ |
76db3ba4 | 2944 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2945 | else \ |
76db3ba4 AJ |
2946 | gen_addr_imm_index(ctx, EA, 0); \ |
2947 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2948 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2949 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2950 | } |
2951 | ||
0c8aacd4 | 2952 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2953 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2954 | { \ |
b61f2753 | 2955 | TCGv EA; \ |
76a66253 | 2956 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2957 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2958 | return; \ |
9a64fbe4 | 2959 | } \ |
76db3ba4 | 2960 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2961 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2962 | gen_addr_reg_index(ctx, EA); \ |
2963 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2964 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2965 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2966 | } |
2967 | ||
cd6e9320 TH |
2968 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
2969 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 2970 | { \ |
76db3ba4 AJ |
2971 | TCGv EA; \ |
2972 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2973 | EA = tcg_temp_new(); \ | |
2974 | gen_addr_reg_index(ctx, EA); \ | |
2975 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2976 | tcg_temp_free(EA); \ |
79aceca5 | 2977 | } |
cd6e9320 TH |
2978 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
2979 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2980 | |
0c8aacd4 AJ |
2981 | #define GEN_STS(name, stop, op, type) \ |
2982 | GEN_ST(name, stop, op | 0x20, type); \ | |
2983 | GEN_STU(name, stop, op | 0x21, type); \ | |
2984 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2985 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2986 | |
2987 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2988 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2989 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2990 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2991 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2992 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2993 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
2994 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2995 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
2996 | |
2997 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2998 | { |
be147d08 | 2999 | int rs; |
b61f2753 | 3000 | TCGv EA; |
be147d08 JM |
3001 | |
3002 | rs = rS(ctx->opcode); | |
84cab1e2 TM |
3003 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
3004 | ||
3005 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
3006 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
3007 | ||
3008 | if (!legal_in_user_mode && is_user_mode(ctx)) { | |
e06fcd75 | 3009 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3010 | return; |
3011 | } | |
84cab1e2 TM |
3012 | |
3013 | if (!le_is_supported && ctx->le_mode) { | |
3014 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); | |
d9bce9d9 JM |
3015 | return; |
3016 | } | |
84cab1e2 TM |
3017 | |
3018 | if (unlikely(rs & 1)) { | |
3019 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
be147d08 JM |
3020 | return; |
3021 | } | |
76db3ba4 | 3022 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 3023 | EA = tcg_temp_new(); |
76db3ba4 | 3024 | gen_addr_imm_index(ctx, EA, 0x03); |
84cab1e2 | 3025 | |
e22c357b DK |
3026 | /* We only need to swap high and low halves. gen_qemu_st64 does |
3027 | necessary 64-bit byteswap already. */ | |
84cab1e2 TM |
3028 | if (unlikely(ctx->le_mode)) { |
3029 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
3030 | gen_addr_add(ctx, EA, EA, 8); | |
3031 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
3032 | } else { | |
3033 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
3034 | gen_addr_add(ctx, EA, EA, 8); | |
3035 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
3036 | } | |
b61f2753 | 3037 | tcg_temp_free(EA); |
be147d08 | 3038 | } else { |
84cab1e2 | 3039 | /* std / stdu*/ |
be147d08 JM |
3040 | if (Rc(ctx->opcode)) { |
3041 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 3042 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
3043 | return; |
3044 | } | |
3045 | } | |
76db3ba4 | 3046 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 3047 | EA = tcg_temp_new(); |
76db3ba4 AJ |
3048 | gen_addr_imm_index(ctx, EA, 0x03); |
3049 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 3050 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
3051 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
3052 | tcg_temp_free(EA); | |
d9bce9d9 | 3053 | } |
d9bce9d9 JM |
3054 | } |
3055 | #endif | |
79aceca5 | 3056 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 3057 | |
79aceca5 | 3058 | /* lhbrx */ |
86178a57 | 3059 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3060 | { |
e22c357b DK |
3061 | TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3062 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3063 | } |
0c8aacd4 | 3064 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 3065 | |
79aceca5 | 3066 | /* lwbrx */ |
86178a57 | 3067 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3068 | { |
e22c357b DK |
3069 | TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3070 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3071 | } |
0c8aacd4 | 3072 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 3073 | |
cd6e9320 TH |
3074 | #if defined(TARGET_PPC64) |
3075 | /* ldbrx */ | |
3076 | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
3077 | { | |
e22c357b DK |
3078 | TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3079 | tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op); | |
cd6e9320 TH |
3080 | } |
3081 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); | |
3082 | #endif /* TARGET_PPC64 */ | |
3083 | ||
79aceca5 | 3084 | /* sthbrx */ |
86178a57 | 3085 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3086 | { |
e22c357b DK |
3087 | TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3088 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3089 | } |
0c8aacd4 | 3090 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 3091 | |
79aceca5 | 3092 | /* stwbrx */ |
86178a57 | 3093 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3094 | { |
e22c357b DK |
3095 | TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3096 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3097 | } |
0c8aacd4 | 3098 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 | 3099 | |
cd6e9320 TH |
3100 | #if defined(TARGET_PPC64) |
3101 | /* stdbrx */ | |
3102 | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
3103 | { | |
e22c357b DK |
3104 | TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3105 | tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op); | |
cd6e9320 TH |
3106 | } |
3107 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); | |
3108 | #endif /* TARGET_PPC64 */ | |
3109 | ||
79aceca5 | 3110 | /*** Integer load and store multiple ***/ |
99e300ef | 3111 | |
54623277 | 3112 | /* lmw */ |
99e300ef | 3113 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 3114 | { |
76db3ba4 AJ |
3115 | TCGv t0; |
3116 | TCGv_i32 t1; | |
3117 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3118 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3119 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3120 | t0 = tcg_temp_new(); |
3121 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3122 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 3123 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
3124 | tcg_temp_free(t0); |
3125 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3126 | } |
3127 | ||
3128 | /* stmw */ | |
99e300ef | 3129 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 3130 | { |
76db3ba4 AJ |
3131 | TCGv t0; |
3132 | TCGv_i32 t1; | |
3133 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3134 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3135 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3136 | t0 = tcg_temp_new(); |
3137 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
3138 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 3139 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
3140 | tcg_temp_free(t0); |
3141 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3142 | } |
3143 | ||
3144 | /*** Integer load and store strings ***/ | |
54623277 | 3145 | |
79aceca5 | 3146 | /* lswi */ |
3fc6c082 | 3147 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
3148 | * rA is in the range of registers to be loaded. |
3149 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
3150 | * For now, I'll follow the spec... | |
3151 | */ | |
99e300ef | 3152 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 3153 | { |
dfbc799d AJ |
3154 | TCGv t0; |
3155 | TCGv_i32 t1, t2; | |
79aceca5 FB |
3156 | int nb = NB(ctx->opcode); |
3157 | int start = rD(ctx->opcode); | |
9a64fbe4 | 3158 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3159 | int nr; |
3160 | ||
3161 | if (nb == 0) | |
3162 | nb = 32; | |
3163 | nr = nb / 4; | |
76a66253 JM |
3164 | if (unlikely(((start + nr) > 32 && |
3165 | start <= ra && (start + nr - 32) > ra) || | |
3166 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 3167 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3168 | return; |
297d8e62 | 3169 | } |
76db3ba4 | 3170 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 3171 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3172 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 3173 | t0 = tcg_temp_new(); |
76db3ba4 | 3174 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
3175 | t1 = tcg_const_i32(nb); |
3176 | t2 = tcg_const_i32(start); | |
2f5a189c | 3177 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3178 | tcg_temp_free(t0); |
3179 | tcg_temp_free_i32(t1); | |
3180 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3181 | } |
3182 | ||
3183 | /* lswx */ | |
99e300ef | 3184 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3185 | { |
76db3ba4 AJ |
3186 | TCGv t0; |
3187 | TCGv_i32 t1, t2, t3; | |
3188 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3189 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3190 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3191 | t0 = tcg_temp_new(); |
3192 | gen_addr_reg_index(ctx, t0); | |
3193 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3194 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3195 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 3196 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
3197 | tcg_temp_free(t0); |
3198 | tcg_temp_free_i32(t1); | |
3199 | tcg_temp_free_i32(t2); | |
3200 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3201 | } |
3202 | ||
3203 | /* stswi */ | |
99e300ef | 3204 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3205 | { |
76db3ba4 AJ |
3206 | TCGv t0; |
3207 | TCGv_i32 t1, t2; | |
4b3686fa | 3208 | int nb = NB(ctx->opcode); |
76db3ba4 | 3209 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 3210 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3211 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3212 | t0 = tcg_temp_new(); |
3213 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3214 | if (nb == 0) |
3215 | nb = 32; | |
dfbc799d | 3216 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3217 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3218 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3219 | tcg_temp_free(t0); |
3220 | tcg_temp_free_i32(t1); | |
3221 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3222 | } |
3223 | ||
3224 | /* stswx */ | |
99e300ef | 3225 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3226 | { |
76db3ba4 AJ |
3227 | TCGv t0; |
3228 | TCGv_i32 t1, t2; | |
3229 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3230 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3231 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3232 | t0 = tcg_temp_new(); |
3233 | gen_addr_reg_index(ctx, t0); | |
3234 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3235 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3236 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3237 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3238 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3239 | tcg_temp_free(t0); |
3240 | tcg_temp_free_i32(t1); | |
3241 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3242 | } |
3243 | ||
3244 | /*** Memory synchronisation ***/ | |
3245 | /* eieio */ | |
99e300ef | 3246 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3247 | { |
79aceca5 FB |
3248 | } |
3249 | ||
3250 | /* isync */ | |
99e300ef | 3251 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3252 | { |
e06fcd75 | 3253 | gen_stop_exception(ctx); |
79aceca5 FB |
3254 | } |
3255 | ||
5c77a786 TM |
3256 | #define LARX(name, len, loadop) \ |
3257 | static void gen_##name(DisasContext *ctx) \ | |
3258 | { \ | |
3259 | TCGv t0; \ | |
3260 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ | |
3261 | gen_set_access_type(ctx, ACCESS_RES); \ | |
3262 | t0 = tcg_temp_local_new(); \ | |
3263 | gen_addr_reg_index(ctx, t0); \ | |
3264 | if ((len) > 1) { \ | |
3265 | gen_check_align(ctx, t0, (len)-1); \ | |
3266 | } \ | |
3267 | gen_qemu_##loadop(ctx, gpr, t0); \ | |
3268 | tcg_gen_mov_tl(cpu_reserve, t0); \ | |
3269 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ | |
3270 | tcg_temp_free(t0); \ | |
79aceca5 FB |
3271 | } |
3272 | ||
5c77a786 TM |
3273 | /* lwarx */ |
3274 | LARX(lbarx, 1, ld8u); | |
3275 | LARX(lharx, 2, ld16u); | |
3276 | LARX(lwarx, 4, ld32u); | |
3277 | ||
3278 | ||
4425265b | 3279 | #if defined(CONFIG_USER_ONLY) |
587c51f7 TM |
3280 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
3281 | int reg, int size) | |
4425265b NF |
3282 | { |
3283 | TCGv t0 = tcg_temp_new(); | |
3284 | uint32_t save_exception = ctx->exception; | |
3285 | ||
1328c2bf | 3286 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
4425265b | 3287 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
1328c2bf | 3288 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b NF |
3289 | tcg_temp_free(t0); |
3290 | gen_update_nip(ctx, ctx->nip-4); | |
3291 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3292 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3293 | ctx->exception = save_exception; | |
3294 | } | |
4425265b | 3295 | #else |
587c51f7 TM |
3296 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
3297 | int reg, int size) | |
3298 | { | |
3299 | int l1; | |
4425265b | 3300 | |
587c51f7 TM |
3301 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3302 | l1 = gen_new_label(); | |
3303 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); | |
3304 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3305 | #if defined(TARGET_PPC64) | |
3306 | if (size == 8) { | |
3307 | gen_qemu_st64(ctx, cpu_gpr[reg], EA); | |
3308 | } else | |
3309 | #endif | |
3310 | if (size == 4) { | |
3311 | gen_qemu_st32(ctx, cpu_gpr[reg], EA); | |
3312 | } else if (size == 2) { | |
3313 | gen_qemu_st16(ctx, cpu_gpr[reg], EA); | |
27b95bfe TM |
3314 | #if defined(TARGET_PPC64) |
3315 | } else if (size == 16) { | |
3707cd62 | 3316 | TCGv gpr1, gpr2 , EA8; |
27b95bfe TM |
3317 | if (unlikely(ctx->le_mode)) { |
3318 | gpr1 = cpu_gpr[reg+1]; | |
3319 | gpr2 = cpu_gpr[reg]; | |
3320 | } else { | |
3321 | gpr1 = cpu_gpr[reg]; | |
3322 | gpr2 = cpu_gpr[reg+1]; | |
3323 | } | |
3324 | gen_qemu_st64(ctx, gpr1, EA); | |
3707cd62 TM |
3325 | EA8 = tcg_temp_local_new(); |
3326 | gen_addr_add(ctx, EA8, EA, 8); | |
3327 | gen_qemu_st64(ctx, gpr2, EA8); | |
3328 | tcg_temp_free(EA8); | |
27b95bfe | 3329 | #endif |
587c51f7 TM |
3330 | } else { |
3331 | gen_qemu_st8(ctx, cpu_gpr[reg], EA); | |
4425265b | 3332 | } |
587c51f7 TM |
3333 | gen_set_label(l1); |
3334 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3335 | } | |
4425265b | 3336 | #endif |
587c51f7 TM |
3337 | |
3338 | #define STCX(name, len) \ | |
3339 | static void gen_##name(DisasContext *ctx) \ | |
3340 | { \ | |
3341 | TCGv t0; \ | |
27b95bfe TM |
3342 | if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \ |
3343 | gen_inval_exception(ctx, \ | |
3344 | POWERPC_EXCP_INVAL_INVAL); \ | |
3345 | return; \ | |
3346 | } \ | |
587c51f7 TM |
3347 | gen_set_access_type(ctx, ACCESS_RES); \ |
3348 | t0 = tcg_temp_local_new(); \ | |
3349 | gen_addr_reg_index(ctx, t0); \ | |
3350 | if (len > 1) { \ | |
3351 | gen_check_align(ctx, t0, (len)-1); \ | |
3352 | } \ | |
3353 | gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \ | |
3354 | tcg_temp_free(t0); \ | |
79aceca5 FB |
3355 | } |
3356 | ||
587c51f7 TM |
3357 | STCX(stbcx_, 1); |
3358 | STCX(sthcx_, 2); | |
3359 | STCX(stwcx_, 4); | |
3360 | ||
426613db | 3361 | #if defined(TARGET_PPC64) |
426613db | 3362 | /* ldarx */ |
5c77a786 | 3363 | LARX(ldarx, 8, ld64); |
426613db | 3364 | |
9c294d5a TM |
3365 | /* lqarx */ |
3366 | static void gen_lqarx(DisasContext *ctx) | |
3367 | { | |
3368 | TCGv EA; | |
3369 | int rd = rD(ctx->opcode); | |
3370 | TCGv gpr1, gpr2; | |
3371 | ||
3372 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3373 | (rd == rB(ctx->opcode)))) { | |
3374 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3375 | return; | |
3376 | } | |
3377 | ||
3378 | gen_set_access_type(ctx, ACCESS_RES); | |
3379 | EA = tcg_temp_local_new(); | |
3380 | gen_addr_reg_index(ctx, EA); | |
3381 | gen_check_align(ctx, EA, 15); | |
3382 | if (unlikely(ctx->le_mode)) { | |
3383 | gpr1 = cpu_gpr[rd+1]; | |
3384 | gpr2 = cpu_gpr[rd]; | |
3385 | } else { | |
3386 | gpr1 = cpu_gpr[rd]; | |
3387 | gpr2 = cpu_gpr[rd+1]; | |
3388 | } | |
3389 | gen_qemu_ld64(ctx, gpr1, EA); | |
3390 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3391 | ||
3392 | gen_addr_add(ctx, EA, EA, 8); | |
3393 | gen_qemu_ld64(ctx, gpr2, EA); | |
3394 | ||
3395 | tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); | |
3396 | tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
3397 | ||
3398 | tcg_temp_free(EA); | |
3399 | } | |
3400 | ||
426613db | 3401 | /* stdcx. */ |
587c51f7 | 3402 | STCX(stdcx_, 8); |
27b95bfe | 3403 | STCX(stqcx_, 16); |
426613db JM |
3404 | #endif /* defined(TARGET_PPC64) */ |
3405 | ||
79aceca5 | 3406 | /* sync */ |
99e300ef | 3407 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3408 | { |
79aceca5 FB |
3409 | } |
3410 | ||
0db1b20e | 3411 | /* wait */ |
99e300ef | 3412 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3413 | { |
931ff272 | 3414 | TCGv_i32 t0 = tcg_temp_new_i32(); |
259186a7 AF |
3415 | tcg_gen_st_i32(t0, cpu_env, |
3416 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3417 | tcg_temp_free_i32(t0); |
0db1b20e | 3418 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3419 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3420 | } |
3421 | ||
79aceca5 | 3422 | /*** Floating-point load ***/ |
a0d7d5a7 | 3423 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3424 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3425 | { \ |
a0d7d5a7 | 3426 | TCGv EA; \ |
76a66253 | 3427 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3428 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3429 | return; \ |
3430 | } \ | |
76db3ba4 | 3431 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3432 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3433 | gen_addr_imm_index(ctx, EA, 0); \ |
3434 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3435 | tcg_temp_free(EA); \ |
79aceca5 FB |
3436 | } |
3437 | ||
a0d7d5a7 | 3438 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3439 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3440 | { \ |
a0d7d5a7 | 3441 | TCGv EA; \ |
76a66253 | 3442 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3443 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3444 | return; \ |
3445 | } \ | |
76a66253 | 3446 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3447 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3448 | return; \ |
9a64fbe4 | 3449 | } \ |
76db3ba4 | 3450 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3451 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3452 | gen_addr_imm_index(ctx, EA, 0); \ |
3453 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3454 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3455 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3456 | } |
3457 | ||
a0d7d5a7 | 3458 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3459 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3460 | { \ |
a0d7d5a7 | 3461 | TCGv EA; \ |
76a66253 | 3462 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3463 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3464 | return; \ |
3465 | } \ | |
76a66253 | 3466 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3467 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3468 | return; \ |
9a64fbe4 | 3469 | } \ |
76db3ba4 | 3470 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3471 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3472 | gen_addr_reg_index(ctx, EA); \ |
3473 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3474 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3475 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3476 | } |
3477 | ||
a0d7d5a7 | 3478 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3479 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3480 | { \ |
a0d7d5a7 | 3481 | TCGv EA; \ |
76a66253 | 3482 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3483 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3484 | return; \ |
3485 | } \ | |
76db3ba4 | 3486 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3487 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3488 | gen_addr_reg_index(ctx, EA); \ |
3489 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3490 | tcg_temp_free(EA); \ |
79aceca5 FB |
3491 | } |
3492 | ||
a0d7d5a7 AJ |
3493 | #define GEN_LDFS(name, ldop, op, type) \ |
3494 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3495 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3496 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3497 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3498 | ||
636aa200 | 3499 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3500 | { |
3501 | TCGv t0 = tcg_temp_new(); | |
3502 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3503 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3504 | tcg_gen_trunc_tl_i32(t1, t0); |
3505 | tcg_temp_free(t0); | |
8e703949 | 3506 | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
a0d7d5a7 AJ |
3507 | tcg_temp_free_i32(t1); |
3508 | } | |
79aceca5 | 3509 | |
a0d7d5a7 AJ |
3510 | /* lfd lfdu lfdux lfdx */ |
3511 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3512 | /* lfs lfsu lfsux lfsx */ | |
3513 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 | 3514 | |
05050ee8 AJ |
3515 | /* lfdp */ |
3516 | static void gen_lfdp(DisasContext *ctx) | |
3517 | { | |
3518 | TCGv EA; | |
3519 | if (unlikely(!ctx->fpu_enabled)) { | |
3520 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3521 | return; | |
3522 | } | |
3523 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3524 | EA = tcg_temp_new(); | |
e22c357b DK |
3525 | gen_addr_imm_index(ctx, EA, 0); |
3526 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary | |
3527 | 64-bit byteswap already. */ | |
05050ee8 AJ |
3528 | if (unlikely(ctx->le_mode)) { |
3529 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3530 | tcg_gen_addi_tl(EA, EA, 8); | |
3531 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3532 | } else { | |
3533 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3534 | tcg_gen_addi_tl(EA, EA, 8); | |
3535 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3536 | } | |
3537 | tcg_temp_free(EA); | |
3538 | } | |
3539 | ||
3540 | /* lfdpx */ | |
3541 | static void gen_lfdpx(DisasContext *ctx) | |
3542 | { | |
3543 | TCGv EA; | |
3544 | if (unlikely(!ctx->fpu_enabled)) { | |
3545 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3546 | return; | |
3547 | } | |
3548 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3549 | EA = tcg_temp_new(); | |
3550 | gen_addr_reg_index(ctx, EA); | |
e22c357b DK |
3551 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary |
3552 | 64-bit byteswap already. */ | |
05050ee8 AJ |
3553 | if (unlikely(ctx->le_mode)) { |
3554 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3555 | tcg_gen_addi_tl(EA, EA, 8); | |
3556 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3557 | } else { | |
3558 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3559 | tcg_gen_addi_tl(EA, EA, 8); | |
3560 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3561 | } | |
3562 | tcg_temp_free(EA); | |
3563 | } | |
3564 | ||
199f830d AJ |
3565 | /* lfiwax */ |
3566 | static void gen_lfiwax(DisasContext *ctx) | |
3567 | { | |
3568 | TCGv EA; | |
3569 | TCGv t0; | |
3570 | if (unlikely(!ctx->fpu_enabled)) { | |
3571 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3572 | return; | |
3573 | } | |
3574 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3575 | EA = tcg_temp_new(); | |
3576 | t0 = tcg_temp_new(); | |
3577 | gen_addr_reg_index(ctx, EA); | |
909eedb7 | 3578 | gen_qemu_ld32s(ctx, t0, EA); |
199f830d | 3579 | tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); |
199f830d AJ |
3580 | tcg_temp_free(EA); |
3581 | tcg_temp_free(t0); | |
3582 | } | |
3583 | ||
66c3e328 TM |
3584 | /* lfiwzx */ |
3585 | static void gen_lfiwzx(DisasContext *ctx) | |
3586 | { | |
3587 | TCGv EA; | |
3588 | if (unlikely(!ctx->fpu_enabled)) { | |
3589 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3590 | return; | |
3591 | } | |
3592 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3593 | EA = tcg_temp_new(); | |
3594 | gen_addr_reg_index(ctx, EA); | |
3595 | gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3596 | tcg_temp_free(EA); | |
3597 | } | |
79aceca5 | 3598 | /*** Floating-point store ***/ |
a0d7d5a7 | 3599 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3600 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3601 | { \ |
a0d7d5a7 | 3602 | TCGv EA; \ |
76a66253 | 3603 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3604 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3605 | return; \ |
3606 | } \ | |
76db3ba4 | 3607 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3608 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3609 | gen_addr_imm_index(ctx, EA, 0); \ |
3610 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3611 | tcg_temp_free(EA); \ |
79aceca5 FB |
3612 | } |
3613 | ||
a0d7d5a7 | 3614 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3615 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3616 | { \ |
a0d7d5a7 | 3617 | TCGv EA; \ |
76a66253 | 3618 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3619 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3620 | return; \ |
3621 | } \ | |
76a66253 | 3622 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3623 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3624 | return; \ |
9a64fbe4 | 3625 | } \ |
76db3ba4 | 3626 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3627 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3628 | gen_addr_imm_index(ctx, EA, 0); \ |
3629 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3630 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3631 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3632 | } |
3633 | ||
a0d7d5a7 | 3634 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3635 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3636 | { \ |
a0d7d5a7 | 3637 | TCGv EA; \ |
76a66253 | 3638 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3639 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3640 | return; \ |
3641 | } \ | |
76a66253 | 3642 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3643 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3644 | return; \ |
9a64fbe4 | 3645 | } \ |
76db3ba4 | 3646 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3647 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3648 | gen_addr_reg_index(ctx, EA); \ |
3649 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3650 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3651 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3652 | } |
3653 | ||
a0d7d5a7 | 3654 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3655 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3656 | { \ |
a0d7d5a7 | 3657 | TCGv EA; \ |
76a66253 | 3658 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3659 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3660 | return; \ |
3661 | } \ | |
76db3ba4 | 3662 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3663 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3664 | gen_addr_reg_index(ctx, EA); \ |
3665 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3666 | tcg_temp_free(EA); \ |
79aceca5 FB |
3667 | } |
3668 | ||
a0d7d5a7 AJ |
3669 | #define GEN_STFS(name, stop, op, type) \ |
3670 | GEN_STF(name, stop, op | 0x20, type); \ | |
3671 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3672 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3673 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3674 | ||
636aa200 | 3675 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3676 | { |
3677 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3678 | TCGv t1 = tcg_temp_new(); | |
8e703949 | 3679 | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
a0d7d5a7 AJ |
3680 | tcg_gen_extu_i32_tl(t1, t0); |
3681 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3682 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3683 | tcg_temp_free(t1); |
3684 | } | |
79aceca5 FB |
3685 | |
3686 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3687 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3688 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3689 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 | 3690 | |
44bc0c4d AJ |
3691 | /* stfdp */ |
3692 | static void gen_stfdp(DisasContext *ctx) | |
3693 | { | |
3694 | TCGv EA; | |
3695 | if (unlikely(!ctx->fpu_enabled)) { | |
3696 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3697 | return; | |
3698 | } | |
3699 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3700 | EA = tcg_temp_new(); | |
e22c357b DK |
3701 | gen_addr_imm_index(ctx, EA, 0); |
3702 | /* We only need to swap high and low halves. gen_qemu_st64 does necessary | |
3703 | 64-bit byteswap already. */ | |
44bc0c4d AJ |
3704 | if (unlikely(ctx->le_mode)) { |
3705 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3706 | tcg_gen_addi_tl(EA, EA, 8); | |
3707 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3708 | } else { | |
3709 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3710 | tcg_gen_addi_tl(EA, EA, 8); | |
3711 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3712 | } | |
3713 | tcg_temp_free(EA); | |
3714 | } | |
3715 | ||
3716 | /* stfdpx */ | |
3717 | static void gen_stfdpx(DisasContext *ctx) | |
3718 | { | |
3719 | TCGv EA; | |
3720 | if (unlikely(!ctx->fpu_enabled)) { | |
3721 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3722 | return; | |
3723 | } | |
3724 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3725 | EA = tcg_temp_new(); | |
3726 | gen_addr_reg_index(ctx, EA); | |
e22c357b DK |
3727 | /* We only need to swap high and low halves. gen_qemu_st64 does necessary |
3728 | 64-bit byteswap already. */ | |
44bc0c4d AJ |
3729 | if (unlikely(ctx->le_mode)) { |
3730 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3731 | tcg_gen_addi_tl(EA, EA, 8); | |
3732 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3733 | } else { | |
3734 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3735 | tcg_gen_addi_tl(EA, EA, 8); | |
3736 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3737 | } | |
3738 | tcg_temp_free(EA); | |
3739 | } | |
3740 | ||
79aceca5 | 3741 | /* Optional: */ |
636aa200 | 3742 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3743 | { |
3744 | TCGv t0 = tcg_temp_new(); | |
3745 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3746 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3747 | tcg_temp_free(t0); |
3748 | } | |
79aceca5 | 3749 | /* stfiwx */ |
a0d7d5a7 | 3750 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 | 3751 | |
697ab892 DG |
3752 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3753 | { | |
3754 | #if defined(TARGET_PPC64) | |
3755 | if (ctx->has_cfar) | |
3756 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3757 | #endif | |
3758 | } | |
3759 | ||
79aceca5 | 3760 | /*** Branch ***/ |
636aa200 | 3761 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 FB |
3762 | { |
3763 | TranslationBlock *tb; | |
3764 | tb = ctx->tb; | |
e0c8f9ce | 3765 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3766 | dest = (uint32_t) dest; |
e0c8f9ce | 3767 | } |
57fec1fe | 3768 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3769 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3770 | tcg_gen_goto_tb(n); |
a2ffb812 | 3771 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cfd0495 | 3772 | tcg_gen_exit_tb((uintptr_t)tb + n); |
c1942362 | 3773 | } else { |
a2ffb812 | 3774 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3775 | if (unlikely(ctx->singlestep_enabled)) { |
3776 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3777 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3778 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3779 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
8cbcb4fa AJ |
3780 | target_ulong tmp = ctx->nip; |
3781 | ctx->nip = dest; | |
e06fcd75 | 3782 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3783 | ctx->nip = tmp; |
3784 | } | |
3785 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3786 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3787 | } |
3788 | } | |
57fec1fe | 3789 | tcg_gen_exit_tb(0); |
c1942362 | 3790 | } |
c53be334 FB |
3791 | } |
3792 | ||
636aa200 | 3793 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3794 | { |
e0c8f9ce RH |
3795 | if (NARROW_MODE(ctx)) { |
3796 | nip = (uint32_t)nip; | |
3797 | } | |
3798 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3799 | } |
3800 | ||
79aceca5 | 3801 | /* b ba bl bla */ |
99e300ef | 3802 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3803 | { |
76a66253 | 3804 | target_ulong li, target; |
38a64f9d | 3805 | |
8cbcb4fa | 3806 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3807 | /* sign extend LI */ |
e0c8f9ce RH |
3808 | li = LI(ctx->opcode); |
3809 | li = (li ^ 0x02000000) - 0x02000000; | |
3810 | if (likely(AA(ctx->opcode) == 0)) { | |
046d6672 | 3811 | target = ctx->nip + li - 4; |
e0c8f9ce | 3812 | } else { |
9a64fbe4 | 3813 | target = li; |
e0c8f9ce RH |
3814 | } |
3815 | if (LK(ctx->opcode)) { | |
e1833e1f | 3816 | gen_setlr(ctx, ctx->nip); |
e0c8f9ce | 3817 | } |
697ab892 | 3818 | gen_update_cfar(ctx, ctx->nip); |
c1942362 | 3819 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3820 | } |
3821 | ||
e98a6e40 FB |
3822 | #define BCOND_IM 0 |
3823 | #define BCOND_LR 1 | |
3824 | #define BCOND_CTR 2 | |
52a4984d | 3825 | #define BCOND_TAR 3 |
e98a6e40 | 3826 | |
636aa200 | 3827 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3828 | { |
d9bce9d9 | 3829 | uint32_t bo = BO(ctx->opcode); |
05f92404 | 3830 | int l1; |
a2ffb812 | 3831 | TCGv target; |
e98a6e40 | 3832 | |
8cbcb4fa | 3833 | ctx->exception = POWERPC_EXCP_BRANCH; |
52a4984d | 3834 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
a7812ae4 | 3835 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3836 | if (type == BCOND_CTR) |
3837 | tcg_gen_mov_tl(target, cpu_ctr); | |
52a4984d TM |
3838 | else if (type == BCOND_TAR) |
3839 | gen_load_spr(target, SPR_TAR); | |
a2ffb812 AJ |
3840 | else |
3841 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3842 | } else { |
3843 | TCGV_UNUSED(target); | |
e98a6e40 | 3844 | } |
e1833e1f JM |
3845 | if (LK(ctx->opcode)) |
3846 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3847 | l1 = gen_new_label(); |
3848 | if ((bo & 0x4) == 0) { | |
3849 | /* Decrement and test CTR */ | |
a7812ae4 | 3850 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3851 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3852 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3853 | return; |
3854 | } | |
3855 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3856 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3857 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3858 | } else { |
a2ffb812 | 3859 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3860 | } |
a2ffb812 AJ |
3861 | if (bo & 0x2) { |
3862 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3863 | } else { | |
3864 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3865 | } |
a7812ae4 | 3866 | tcg_temp_free(temp); |
a2ffb812 AJ |
3867 | } |
3868 | if ((bo & 0x10) == 0) { | |
3869 | /* Test CR */ | |
3870 | uint32_t bi = BI(ctx->opcode); | |
3871 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3872 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3873 | |
d9bce9d9 | 3874 | if (bo & 0x8) { |
a2ffb812 AJ |
3875 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3876 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3877 | } else { |
a2ffb812 AJ |
3878 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3879 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3880 | } |
a7812ae4 | 3881 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3882 | } |
697ab892 | 3883 | gen_update_cfar(ctx, ctx->nip); |
e98a6e40 | 3884 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3885 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3886 | if (likely(AA(ctx->opcode) == 0)) { | |
3887 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3888 | } else { | |
3889 | gen_goto_tb(ctx, 0, li); | |
3890 | } | |
c53be334 | 3891 | gen_set_label(l1); |
c1942362 | 3892 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3893 | } else { |
e0c8f9ce | 3894 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3895 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3896 | } else { |
a2ffb812 | 3897 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3898 | } |
a2ffb812 AJ |
3899 | tcg_gen_exit_tb(0); |
3900 | gen_set_label(l1); | |
e0c8f9ce | 3901 | gen_update_nip(ctx, ctx->nip); |
57fec1fe | 3902 | tcg_gen_exit_tb(0); |
08e46e54 | 3903 | } |
a9e8f4e7 | 3904 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
c80d1df5 AG |
3905 | tcg_temp_free(target); |
3906 | } | |
e98a6e40 FB |
3907 | } |
3908 | ||
99e300ef | 3909 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3910 | { |
e98a6e40 FB |
3911 | gen_bcond(ctx, BCOND_IM); |
3912 | } | |
3913 | ||
99e300ef | 3914 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3915 | { |
e98a6e40 FB |
3916 | gen_bcond(ctx, BCOND_CTR); |
3917 | } | |
3918 | ||
99e300ef | 3919 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3920 | { |
e98a6e40 FB |
3921 | gen_bcond(ctx, BCOND_LR); |
3922 | } | |
79aceca5 | 3923 | |
52a4984d TM |
3924 | static void gen_bctar(DisasContext *ctx) |
3925 | { | |
3926 | gen_bcond(ctx, BCOND_TAR); | |
3927 | } | |
3928 | ||
79aceca5 | 3929 | /*** Condition register logical ***/ |
e1571908 | 3930 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3931 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3932 | { \ |
fc0d441e JM |
3933 | uint8_t bitmask; \ |
3934 | int sh; \ | |
a7812ae4 | 3935 | TCGv_i32 t0, t1; \ |
fc0d441e | 3936 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3937 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3938 | if (sh > 0) \ |
fea0c503 | 3939 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3940 | else if (sh < 0) \ |
fea0c503 | 3941 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3942 | else \ |
fea0c503 | 3943 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3944 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3945 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3946 | if (sh > 0) \ | |
fea0c503 | 3947 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3948 | else if (sh < 0) \ |
fea0c503 | 3949 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3950 | else \ |
fea0c503 AJ |
3951 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3952 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3953 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3954 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3955 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3956 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3957 | tcg_temp_free_i32(t0); \ |
3958 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3959 | } |
3960 | ||
3961 | /* crand */ | |
e1571908 | 3962 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3963 | /* crandc */ |
e1571908 | 3964 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3965 | /* creqv */ |
e1571908 | 3966 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3967 | /* crnand */ |
e1571908 | 3968 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3969 | /* crnor */ |
e1571908 | 3970 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3971 | /* cror */ |
e1571908 | 3972 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3973 | /* crorc */ |
e1571908 | 3974 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3975 | /* crxor */ |
e1571908 | 3976 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3977 | |
54623277 | 3978 | /* mcrf */ |
99e300ef | 3979 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3980 | { |
47e4661c | 3981 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3982 | } |
3983 | ||
3984 | /*** System linkage ***/ | |
99e300ef | 3985 | |
54623277 | 3986 | /* rfi (mem_idx only) */ |
99e300ef | 3987 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3988 | { |
9a64fbe4 | 3989 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3990 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3991 | #else |
3992 | /* Restore CPU state */ | |
76db3ba4 | 3993 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3994 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3995 | return; |
9a64fbe4 | 3996 | } |
697ab892 | 3997 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3998 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3999 | gen_sync_exception(ctx); |
9a64fbe4 | 4000 | #endif |
79aceca5 FB |
4001 | } |
4002 | ||
426613db | 4003 | #if defined(TARGET_PPC64) |
99e300ef | 4004 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
4005 | { |
4006 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4007 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4008 | #else |
4009 | /* Restore CPU state */ | |
76db3ba4 | 4010 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4011 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4012 | return; |
4013 | } | |
697ab892 | 4014 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 4015 | gen_helper_rfid(cpu_env); |
e06fcd75 | 4016 | gen_sync_exception(ctx); |
426613db JM |
4017 | #endif |
4018 | } | |
426613db | 4019 | |
99e300ef | 4020 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
4021 | { |
4022 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4023 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
4024 | #else |
4025 | /* Restore CPU state */ | |
76db3ba4 | 4026 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 4027 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
4028 | return; |
4029 | } | |
e5f17ac6 | 4030 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 4031 | gen_sync_exception(ctx); |
be147d08 JM |
4032 | #endif |
4033 | } | |
4034 | #endif | |
4035 | ||
79aceca5 | 4036 | /* sc */ |
417bf010 JM |
4037 | #if defined(CONFIG_USER_ONLY) |
4038 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
4039 | #else | |
4040 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
4041 | #endif | |
99e300ef | 4042 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 4043 | { |
e1833e1f JM |
4044 | uint32_t lev; |
4045 | ||
4046 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 4047 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
4048 | } |
4049 | ||
4050 | /*** Trap ***/ | |
99e300ef | 4051 | |
54623277 | 4052 | /* tw */ |
99e300ef | 4053 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 4054 | { |
cab3bee2 | 4055 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
4056 | /* Update the nip since this might generate a trap exception */ |
4057 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
4058 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4059 | t0); | |
cab3bee2 | 4060 | tcg_temp_free_i32(t0); |
79aceca5 FB |
4061 | } |
4062 | ||
4063 | /* twi */ | |
99e300ef | 4064 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 4065 | { |
cab3bee2 AJ |
4066 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
4067 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
4068 | /* Update the nip since this might generate a trap exception */ |
4069 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 4070 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4071 | tcg_temp_free(t0); |
4072 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
4073 | } |
4074 | ||
d9bce9d9 JM |
4075 | #if defined(TARGET_PPC64) |
4076 | /* td */ | |
99e300ef | 4077 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 4078 | { |
cab3bee2 | 4079 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
4080 | /* Update the nip since this might generate a trap exception */ |
4081 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
4082 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4083 | t0); | |
cab3bee2 | 4084 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
4085 | } |
4086 | ||
4087 | /* tdi */ | |
99e300ef | 4088 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 4089 | { |
cab3bee2 AJ |
4090 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
4091 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
4092 | /* Update the nip since this might generate a trap exception */ |
4093 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 4094 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4095 | tcg_temp_free(t0); |
4096 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
4097 | } |
4098 | #endif | |
4099 | ||
79aceca5 | 4100 | /*** Processor control ***/ |
99e300ef | 4101 | |
da91a00f RH |
4102 | static void gen_read_xer(TCGv dst) |
4103 | { | |
4104 | TCGv t0 = tcg_temp_new(); | |
4105 | TCGv t1 = tcg_temp_new(); | |
4106 | TCGv t2 = tcg_temp_new(); | |
4107 | tcg_gen_mov_tl(dst, cpu_xer); | |
4108 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
4109 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
4110 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
4111 | tcg_gen_or_tl(t0, t0, t1); | |
4112 | tcg_gen_or_tl(dst, dst, t2); | |
4113 | tcg_gen_or_tl(dst, dst, t0); | |
4114 | tcg_temp_free(t0); | |
4115 | tcg_temp_free(t1); | |
4116 | tcg_temp_free(t2); | |
4117 | } | |
4118 | ||
4119 | static void gen_write_xer(TCGv src) | |
4120 | { | |
4121 | tcg_gen_andi_tl(cpu_xer, src, | |
4122 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
4123 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
4124 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
4125 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
4126 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
4127 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
4128 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
4129 | } | |
4130 | ||
54623277 | 4131 | /* mcrxr */ |
99e300ef | 4132 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 4133 | { |
da91a00f RH |
4134 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4135 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4136 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4137 | ||
4138 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
4139 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
4140 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
294d1292 SB |
4141 | tcg_gen_shli_i32(t0, t0, 3); |
4142 | tcg_gen_shli_i32(t1, t1, 2); | |
4143 | tcg_gen_shli_i32(dst, dst, 1); | |
da91a00f RH |
4144 | tcg_gen_or_i32(dst, dst, t0); |
4145 | tcg_gen_or_i32(dst, dst, t1); | |
4146 | tcg_temp_free_i32(t0); | |
4147 | tcg_temp_free_i32(t1); | |
4148 | ||
4149 | tcg_gen_movi_tl(cpu_so, 0); | |
4150 | tcg_gen_movi_tl(cpu_ov, 0); | |
4151 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
4152 | } |
4153 | ||
0cfe11ea | 4154 | /* mfcr mfocrf */ |
99e300ef | 4155 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 4156 | { |
76a66253 | 4157 | uint32_t crm, crn; |
3b46e624 | 4158 | |
76a66253 JM |
4159 | if (likely(ctx->opcode & 0x00100000)) { |
4160 | crm = CRM(ctx->opcode); | |
8dd640e4 | 4161 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 4162 | crn = ctz32 (crm); |
e1571908 | 4163 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
4164 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
4165 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 4166 | } |
d9bce9d9 | 4167 | } else { |
651721b2 AJ |
4168 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4169 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
4170 | tcg_gen_shli_i32(t0, t0, 4); | |
4171 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
4172 | tcg_gen_shli_i32(t0, t0, 4); | |
4173 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
4174 | tcg_gen_shli_i32(t0, t0, 4); | |
4175 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
4176 | tcg_gen_shli_i32(t0, t0, 4); | |
4177 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
4178 | tcg_gen_shli_i32(t0, t0, 4); | |
4179 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
4180 | tcg_gen_shli_i32(t0, t0, 4); | |
4181 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
4182 | tcg_gen_shli_i32(t0, t0, 4); | |
4183 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
4184 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4185 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 4186 | } |
79aceca5 FB |
4187 | } |
4188 | ||
4189 | /* mfmsr */ | |
99e300ef | 4190 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 4191 | { |
9a64fbe4 | 4192 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4193 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4194 | #else |
76db3ba4 | 4195 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4196 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4197 | return; |
9a64fbe4 | 4198 | } |
6527f6ea | 4199 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 4200 | #endif |
79aceca5 FB |
4201 | } |
4202 | ||
7b13448f | 4203 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3fc6c082 | 4204 | { |
7b13448f | 4205 | #if 0 |
3fc6c082 FB |
4206 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
4207 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 4208 | #endif |
3fc6c082 FB |
4209 | } |
4210 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 4211 | |
79aceca5 | 4212 | /* mfspr */ |
636aa200 | 4213 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 4214 | { |
45d827d2 | 4215 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
4216 | uint32_t sprn = SPR(ctx->opcode); |
4217 | ||
3fc6c082 | 4218 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4219 | if (ctx->mem_idx == 2) |
be147d08 | 4220 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 4221 | else if (ctx->mem_idx) |
3fc6c082 FB |
4222 | read_cb = ctx->spr_cb[sprn].oea_read; |
4223 | else | |
9a64fbe4 | 4224 | #endif |
3fc6c082 | 4225 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
4226 | if (likely(read_cb != NULL)) { |
4227 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4228 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4229 | } else { |
4230 | /* Privilege exception */ | |
9fceefa7 JM |
4231 | /* This is a hack to avoid warnings when running Linux: |
4232 | * this OS breaks the PowerPC virtualisation model, | |
4233 | * allowing userland application to read the PVR | |
4234 | */ | |
4235 | if (sprn != SPR_PVR) { | |
c05541ee AB |
4236 | qemu_log("Trying to read privileged spr %d (0x%03x) at " |
4237 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4238 | printf("Trying to read privileged spr %d (0x%03x) at " | |
4239 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
f24e5695 | 4240 | } |
e06fcd75 | 4241 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4242 | } |
3fc6c082 FB |
4243 | } else { |
4244 | /* Not defined */ | |
c05541ee AB |
4245 | qemu_log("Trying to read invalid spr %d (0x%03x) at " |
4246 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4247 | printf("Trying to read invalid spr %d (0x%03x) at " | |
4248 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4249 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4250 | } |
79aceca5 FB |
4251 | } |
4252 | ||
99e300ef | 4253 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4254 | { |
3fc6c082 | 4255 | gen_op_mfspr(ctx); |
76a66253 | 4256 | } |
3fc6c082 FB |
4257 | |
4258 | /* mftb */ | |
99e300ef | 4259 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4260 | { |
4261 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4262 | } |
4263 | ||
0cfe11ea | 4264 | /* mtcrf mtocrf*/ |
99e300ef | 4265 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4266 | { |
76a66253 | 4267 | uint32_t crm, crn; |
3b46e624 | 4268 | |
76a66253 | 4269 | crm = CRM(ctx->opcode); |
8dd640e4 | 4270 | if (likely((ctx->opcode & 0x00100000))) { |
4271 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4272 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 4273 | crn = ctz32 (crm); |
8dd640e4 | 4274 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4275 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4276 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4277 | tcg_temp_free_i32(temp); |
4278 | } | |
76a66253 | 4279 | } else { |
651721b2 AJ |
4280 | TCGv_i32 temp = tcg_temp_new_i32(); |
4281 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4282 | for (crn = 0 ; crn < 8 ; crn++) { | |
4283 | if (crm & (1 << crn)) { | |
4284 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4285 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4286 | } | |
4287 | } | |
a7812ae4 | 4288 | tcg_temp_free_i32(temp); |
76a66253 | 4289 | } |
79aceca5 FB |
4290 | } |
4291 | ||
4292 | /* mtmsr */ | |
426613db | 4293 | #if defined(TARGET_PPC64) |
99e300ef | 4294 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
4295 | { |
4296 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4297 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 4298 | #else |
76db3ba4 | 4299 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4300 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
4301 | return; |
4302 | } | |
be147d08 JM |
4303 | if (ctx->opcode & 0x00010000) { |
4304 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4305 | TCGv t0 = tcg_temp_new(); |
4306 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4307 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4308 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4309 | tcg_temp_free(t0); | |
be147d08 | 4310 | } else { |
056b05f8 JM |
4311 | /* XXX: we need to update nip before the store |
4312 | * if we enter power saving mode, we will exit the loop | |
4313 | * directly from ppc_store_msr | |
4314 | */ | |
be147d08 | 4315 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 4316 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
4317 | /* Must stop the translation as machine state (may have) changed */ |
4318 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 4319 | gen_stop_exception(ctx); |
be147d08 | 4320 | } |
426613db JM |
4321 | #endif |
4322 | } | |
4323 | #endif | |
4324 | ||
99e300ef | 4325 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4326 | { |
9a64fbe4 | 4327 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4328 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4329 | #else |
76db3ba4 | 4330 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4331 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4332 | return; |
9a64fbe4 | 4333 | } |
be147d08 JM |
4334 | if (ctx->opcode & 0x00010000) { |
4335 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4336 | TCGv t0 = tcg_temp_new(); |
4337 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4338 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4339 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4340 | tcg_temp_free(t0); | |
be147d08 | 4341 | } else { |
8018dc63 AG |
4342 | TCGv msr = tcg_temp_new(); |
4343 | ||
056b05f8 JM |
4344 | /* XXX: we need to update nip before the store |
4345 | * if we enter power saving mode, we will exit the loop | |
4346 | * directly from ppc_store_msr | |
4347 | */ | |
be147d08 | 4348 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 4349 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4350 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4351 | #else | |
4352 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4353 | #endif |
e5f17ac6 | 4354 | gen_helper_store_msr(cpu_env, msr); |
c80d1df5 | 4355 | tcg_temp_free(msr); |
be147d08 | 4356 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4357 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4358 | gen_stop_exception(ctx); |
be147d08 | 4359 | } |
9a64fbe4 | 4360 | #endif |
79aceca5 FB |
4361 | } |
4362 | ||
4363 | /* mtspr */ | |
99e300ef | 4364 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4365 | { |
45d827d2 | 4366 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
4367 | uint32_t sprn = SPR(ctx->opcode); |
4368 | ||
3fc6c082 | 4369 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4370 | if (ctx->mem_idx == 2) |
be147d08 | 4371 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 4372 | else if (ctx->mem_idx) |
3fc6c082 FB |
4373 | write_cb = ctx->spr_cb[sprn].oea_write; |
4374 | else | |
9a64fbe4 | 4375 | #endif |
3fc6c082 | 4376 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
4377 | if (likely(write_cb != NULL)) { |
4378 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4379 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4380 | } else { |
4381 | /* Privilege exception */ | |
c05541ee AB |
4382 | qemu_log("Trying to write privileged spr %d (0x%03x) at " |
4383 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4384 | printf("Trying to write privileged spr %d (0x%03x) at " | |
4385 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4386 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4387 | } |
3fc6c082 FB |
4388 | } else { |
4389 | /* Not defined */ | |
c05541ee AB |
4390 | qemu_log("Trying to write invalid spr %d (0x%03x) at " |
4391 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4392 | printf("Trying to write invalid spr %d (0x%03x) at " | |
4393 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4394 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4395 | } |
79aceca5 FB |
4396 | } |
4397 | ||
4398 | /*** Cache management ***/ | |
99e300ef | 4399 | |
54623277 | 4400 | /* dcbf */ |
99e300ef | 4401 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4402 | { |
dac454af | 4403 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4404 | TCGv t0; |
4405 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4406 | t0 = tcg_temp_new(); | |
4407 | gen_addr_reg_index(ctx, t0); | |
4408 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4409 | tcg_temp_free(t0); |
79aceca5 FB |
4410 | } |
4411 | ||
4412 | /* dcbi (Supervisor only) */ | |
99e300ef | 4413 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4414 | { |
a541f297 | 4415 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4416 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4417 | #else |
b61f2753 | 4418 | TCGv EA, val; |
76db3ba4 | 4419 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4420 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4421 | return; |
9a64fbe4 | 4422 | } |
a7812ae4 | 4423 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4424 | gen_set_access_type(ctx, ACCESS_CACHE); |
4425 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4426 | val = tcg_temp_new(); |
76a66253 | 4427 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4428 | gen_qemu_ld8u(ctx, val, EA); |
4429 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4430 | tcg_temp_free(val); |
4431 | tcg_temp_free(EA); | |
a541f297 | 4432 | #endif |
79aceca5 FB |
4433 | } |
4434 | ||
4435 | /* dcdst */ | |
99e300ef | 4436 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4437 | { |
76a66253 | 4438 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4439 | TCGv t0; |
4440 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4441 | t0 = tcg_temp_new(); | |
4442 | gen_addr_reg_index(ctx, t0); | |
4443 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4444 | tcg_temp_free(t0); |
79aceca5 FB |
4445 | } |
4446 | ||
4447 | /* dcbt */ | |
99e300ef | 4448 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4449 | { |
0db1b20e | 4450 | /* interpreted as no-op */ |
76a66253 JM |
4451 | /* XXX: specification say this is treated as a load by the MMU |
4452 | * but does not generate any exception | |
4453 | */ | |
79aceca5 FB |
4454 | } |
4455 | ||
4456 | /* dcbtst */ | |
99e300ef | 4457 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4458 | { |
0db1b20e | 4459 | /* interpreted as no-op */ |
76a66253 JM |
4460 | /* XXX: specification say this is treated as a load by the MMU |
4461 | * but does not generate any exception | |
4462 | */ | |
79aceca5 FB |
4463 | } |
4464 | ||
4d09d529 AG |
4465 | /* dcbtls */ |
4466 | static void gen_dcbtls(DisasContext *ctx) | |
4467 | { | |
4468 | /* Always fails locking the cache */ | |
4469 | TCGv t0 = tcg_temp_new(); | |
4470 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4471 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4472 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4473 | tcg_temp_free(t0); | |
4474 | } | |
4475 | ||
79aceca5 | 4476 | /* dcbz */ |
99e300ef | 4477 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4478 | { |
8e33944f AG |
4479 | TCGv tcgv_addr; |
4480 | TCGv_i32 tcgv_is_dcbzl; | |
4481 | int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; | |
d63001d1 | 4482 | |
76db3ba4 | 4483 | gen_set_access_type(ctx, ACCESS_CACHE); |
799a8c8d AJ |
4484 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4485 | gen_update_nip(ctx, ctx->nip - 4); | |
8e33944f AG |
4486 | tcgv_addr = tcg_temp_new(); |
4487 | tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); | |
4488 | ||
4489 | gen_addr_reg_index(ctx, tcgv_addr); | |
4490 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); | |
4491 | ||
4492 | tcg_temp_free(tcgv_addr); | |
4493 | tcg_temp_free_i32(tcgv_is_dcbzl); | |
79aceca5 FB |
4494 | } |
4495 | ||
ae1c1a3d | 4496 | /* dst / dstt */ |
99e300ef | 4497 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4498 | { |
4499 | if (rA(ctx->opcode) == 0) { | |
4500 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4501 | } else { | |
4502 | /* interpreted as no-op */ | |
4503 | } | |
4504 | } | |
4505 | ||
4506 | /* dstst /dststt */ | |
99e300ef | 4507 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4508 | { |
4509 | if (rA(ctx->opcode) == 0) { | |
4510 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4511 | } else { | |
4512 | /* interpreted as no-op */ | |
4513 | } | |
4514 | ||
4515 | } | |
4516 | ||
4517 | /* dss / dssall */ | |
99e300ef | 4518 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4519 | { |
4520 | /* interpreted as no-op */ | |
4521 | } | |
4522 | ||
79aceca5 | 4523 | /* icbi */ |
99e300ef | 4524 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4525 | { |
76db3ba4 AJ |
4526 | TCGv t0; |
4527 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4528 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4529 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4530 | t0 = tcg_temp_new(); |
4531 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4532 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4533 | tcg_temp_free(t0); |
79aceca5 FB |
4534 | } |
4535 | ||
4536 | /* Optional: */ | |
4537 | /* dcba */ | |
99e300ef | 4538 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4539 | { |
0db1b20e JM |
4540 | /* interpreted as no-op */ |
4541 | /* XXX: specification say this is treated as a store by the MMU | |
4542 | * but does not generate any exception | |
4543 | */ | |
79aceca5 FB |
4544 | } |
4545 | ||
4546 | /*** Segment register manipulation ***/ | |
4547 | /* Supervisor only: */ | |
99e300ef | 4548 | |
54623277 | 4549 | /* mfsr */ |
99e300ef | 4550 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4551 | { |
9a64fbe4 | 4552 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4553 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4554 | #else |
74d37793 | 4555 | TCGv t0; |
76db3ba4 | 4556 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4557 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4558 | return; |
9a64fbe4 | 4559 | } |
74d37793 | 4560 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4561 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4562 | tcg_temp_free(t0); |
9a64fbe4 | 4563 | #endif |
79aceca5 FB |
4564 | } |
4565 | ||
4566 | /* mfsrin */ | |
99e300ef | 4567 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4568 | { |
9a64fbe4 | 4569 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4570 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4571 | #else |
74d37793 | 4572 | TCGv t0; |
76db3ba4 | 4573 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4574 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4575 | return; |
9a64fbe4 | 4576 | } |
74d37793 AJ |
4577 | t0 = tcg_temp_new(); |
4578 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4579 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4580 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4581 | tcg_temp_free(t0); |
9a64fbe4 | 4582 | #endif |
79aceca5 FB |
4583 | } |
4584 | ||
4585 | /* mtsr */ | |
99e300ef | 4586 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4587 | { |
9a64fbe4 | 4588 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4589 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4590 | #else |
74d37793 | 4591 | TCGv t0; |
76db3ba4 | 4592 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4593 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4594 | return; |
9a64fbe4 | 4595 | } |
74d37793 | 4596 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4597 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4598 | tcg_temp_free(t0); |
9a64fbe4 | 4599 | #endif |
79aceca5 FB |
4600 | } |
4601 | ||
4602 | /* mtsrin */ | |
99e300ef | 4603 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4604 | { |
9a64fbe4 | 4605 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4606 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4607 | #else |
74d37793 | 4608 | TCGv t0; |
76db3ba4 | 4609 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4610 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4611 | return; |
9a64fbe4 | 4612 | } |
74d37793 AJ |
4613 | t0 = tcg_temp_new(); |
4614 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4615 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4616 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4617 | tcg_temp_free(t0); |
9a64fbe4 | 4618 | #endif |
79aceca5 FB |
4619 | } |
4620 | ||
12de9a39 JM |
4621 | #if defined(TARGET_PPC64) |
4622 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4623 | |
54623277 | 4624 | /* mfsr */ |
e8eaa2c0 | 4625 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4626 | { |
4627 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4628 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4629 | #else |
74d37793 | 4630 | TCGv t0; |
76db3ba4 | 4631 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4632 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4633 | return; |
4634 | } | |
74d37793 | 4635 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4636 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4637 | tcg_temp_free(t0); |
12de9a39 JM |
4638 | #endif |
4639 | } | |
4640 | ||
4641 | /* mfsrin */ | |
e8eaa2c0 | 4642 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4643 | { |
4644 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4645 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4646 | #else |
74d37793 | 4647 | TCGv t0; |
76db3ba4 | 4648 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4649 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4650 | return; |
4651 | } | |
74d37793 AJ |
4652 | t0 = tcg_temp_new(); |
4653 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4654 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4655 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4656 | tcg_temp_free(t0); |
12de9a39 JM |
4657 | #endif |
4658 | } | |
4659 | ||
4660 | /* mtsr */ | |
e8eaa2c0 | 4661 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4662 | { |
4663 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4664 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4665 | #else |
74d37793 | 4666 | TCGv t0; |
76db3ba4 | 4667 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4668 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4669 | return; |
4670 | } | |
74d37793 | 4671 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4672 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4673 | tcg_temp_free(t0); |
12de9a39 JM |
4674 | #endif |
4675 | } | |
4676 | ||
4677 | /* mtsrin */ | |
e8eaa2c0 | 4678 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4679 | { |
4680 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4681 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4682 | #else |
74d37793 | 4683 | TCGv t0; |
76db3ba4 | 4684 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4685 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4686 | return; |
4687 | } | |
74d37793 AJ |
4688 | t0 = tcg_temp_new(); |
4689 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4690 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4691 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4692 | tcg_temp_free(t0); |
12de9a39 JM |
4693 | #endif |
4694 | } | |
f6b868fc BS |
4695 | |
4696 | /* slbmte */ | |
e8eaa2c0 | 4697 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4698 | { |
4699 | #if defined(CONFIG_USER_ONLY) | |
4700 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4701 | #else | |
4702 | if (unlikely(!ctx->mem_idx)) { | |
4703 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4704 | return; | |
4705 | } | |
c6c7cf05 BS |
4706 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4707 | cpu_gpr[rS(ctx->opcode)]); | |
f6b868fc BS |
4708 | #endif |
4709 | } | |
4710 | ||
efdef95f DG |
4711 | static void gen_slbmfee(DisasContext *ctx) |
4712 | { | |
4713 | #if defined(CONFIG_USER_ONLY) | |
4714 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4715 | #else | |
4716 | if (unlikely(!ctx->mem_idx)) { | |
4717 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4718 | return; | |
4719 | } | |
c6c7cf05 | 4720 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4721 | cpu_gpr[rB(ctx->opcode)]); |
4722 | #endif | |
4723 | } | |
4724 | ||
4725 | static void gen_slbmfev(DisasContext *ctx) | |
4726 | { | |
4727 | #if defined(CONFIG_USER_ONLY) | |
4728 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4729 | #else | |
4730 | if (unlikely(!ctx->mem_idx)) { | |
4731 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4732 | return; | |
4733 | } | |
c6c7cf05 | 4734 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4735 | cpu_gpr[rB(ctx->opcode)]); |
4736 | #endif | |
4737 | } | |
12de9a39 JM |
4738 | #endif /* defined(TARGET_PPC64) */ |
4739 | ||
79aceca5 | 4740 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4741 | /* Optional & mem_idx only: */ |
99e300ef | 4742 | |
54623277 | 4743 | /* tlbia */ |
99e300ef | 4744 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4745 | { |
9a64fbe4 | 4746 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4747 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4748 | #else |
76db3ba4 | 4749 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4750 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4751 | return; |
9a64fbe4 | 4752 | } |
c6c7cf05 | 4753 | gen_helper_tlbia(cpu_env); |
9a64fbe4 | 4754 | #endif |
79aceca5 FB |
4755 | } |
4756 | ||
bf14b1ce | 4757 | /* tlbiel */ |
99e300ef | 4758 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4759 | { |
4760 | #if defined(CONFIG_USER_ONLY) | |
4761 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4762 | #else | |
4763 | if (unlikely(!ctx->mem_idx)) { | |
4764 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4765 | return; | |
4766 | } | |
c6c7cf05 | 4767 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
bf14b1ce BS |
4768 | #endif |
4769 | } | |
4770 | ||
79aceca5 | 4771 | /* tlbie */ |
99e300ef | 4772 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4773 | { |
9a64fbe4 | 4774 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4775 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4776 | #else |
76db3ba4 | 4777 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4778 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4779 | return; |
9a64fbe4 | 4780 | } |
9ca3f7f3 | 4781 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4782 | TCGv t0 = tcg_temp_new(); |
4783 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4784 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4785 | tcg_temp_free(t0); |
9ca3f7f3 | 4786 | } else { |
c6c7cf05 | 4787 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4788 | } |
9a64fbe4 | 4789 | #endif |
79aceca5 FB |
4790 | } |
4791 | ||
4792 | /* tlbsync */ | |
99e300ef | 4793 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4794 | { |
9a64fbe4 | 4795 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4796 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4797 | #else |
76db3ba4 | 4798 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4799 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4800 | return; |
9a64fbe4 FB |
4801 | } |
4802 | /* This has no effect: it should ensure that all previous | |
4803 | * tlbie have completed | |
4804 | */ | |
e06fcd75 | 4805 | gen_stop_exception(ctx); |
9a64fbe4 | 4806 | #endif |
79aceca5 FB |
4807 | } |
4808 | ||
426613db JM |
4809 | #if defined(TARGET_PPC64) |
4810 | /* slbia */ | |
99e300ef | 4811 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4812 | { |
4813 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4814 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4815 | #else |
76db3ba4 | 4816 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4817 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4818 | return; |
4819 | } | |
c6c7cf05 | 4820 | gen_helper_slbia(cpu_env); |
426613db JM |
4821 | #endif |
4822 | } | |
4823 | ||
4824 | /* slbie */ | |
99e300ef | 4825 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4826 | { |
4827 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4828 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4829 | #else |
76db3ba4 | 4830 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4831 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4832 | return; |
4833 | } | |
c6c7cf05 | 4834 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4835 | #endif |
4836 | } | |
4837 | #endif | |
4838 | ||
79aceca5 FB |
4839 | /*** External control ***/ |
4840 | /* Optional: */ | |
99e300ef | 4841 | |
54623277 | 4842 | /* eciwx */ |
99e300ef | 4843 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4844 | { |
76db3ba4 | 4845 | TCGv t0; |
fa407c03 | 4846 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4847 | gen_set_access_type(ctx, ACCESS_EXT); |
4848 | t0 = tcg_temp_new(); | |
4849 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4850 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4851 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4852 | tcg_temp_free(t0); |
76a66253 JM |
4853 | } |
4854 | ||
4855 | /* ecowx */ | |
99e300ef | 4856 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4857 | { |
76db3ba4 | 4858 | TCGv t0; |
fa407c03 | 4859 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4860 | gen_set_access_type(ctx, ACCESS_EXT); |
4861 | t0 = tcg_temp_new(); | |
4862 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4863 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4864 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4865 | tcg_temp_free(t0); |
76a66253 JM |
4866 | } |
4867 | ||
4868 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4869 | |
54623277 | 4870 | /* abs - abs. */ |
99e300ef | 4871 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4872 | { |
22e0e173 AJ |
4873 | int l1 = gen_new_label(); |
4874 | int l2 = gen_new_label(); | |
4875 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4876 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4877 | tcg_gen_br(l2); | |
4878 | gen_set_label(l1); | |
4879 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4880 | gen_set_label(l2); | |
76a66253 | 4881 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4882 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4883 | } |
4884 | ||
4885 | /* abso - abso. */ | |
99e300ef | 4886 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4887 | { |
22e0e173 AJ |
4888 | int l1 = gen_new_label(); |
4889 | int l2 = gen_new_label(); | |
4890 | int l3 = gen_new_label(); | |
4891 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4892 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4893 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4894 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4895 | tcg_gen_movi_tl(cpu_ov, 1); |
4896 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4897 | tcg_gen_br(l2); |
4898 | gen_set_label(l1); | |
4899 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4900 | tcg_gen_br(l3); | |
4901 | gen_set_label(l2); | |
4902 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4903 | gen_set_label(l3); | |
76a66253 | 4904 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4905 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4906 | } |
4907 | ||
4908 | /* clcs */ | |
99e300ef | 4909 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4910 | { |
22e0e173 | 4911 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4912 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4913 | tcg_temp_free_i32(t0); |
c7697e1f | 4914 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4915 | } |
4916 | ||
4917 | /* div - div. */ | |
99e300ef | 4918 | static void gen_div(DisasContext *ctx) |
76a66253 | 4919 | { |
d15f74fb BS |
4920 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4921 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4922 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4923 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4924 | } |
4925 | ||
4926 | /* divo - divo. */ | |
99e300ef | 4927 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4928 | { |
d15f74fb BS |
4929 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4930 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4931 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4932 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4933 | } |
4934 | ||
4935 | /* divs - divs. */ | |
99e300ef | 4936 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4937 | { |
d15f74fb BS |
4938 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4939 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4940 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4941 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4942 | } |
4943 | ||
4944 | /* divso - divso. */ | |
99e300ef | 4945 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4946 | { |
d15f74fb BS |
4947 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4948 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4949 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4950 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4951 | } |
4952 | ||
4953 | /* doz - doz. */ | |
99e300ef | 4954 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4955 | { |
22e0e173 AJ |
4956 | int l1 = gen_new_label(); |
4957 | int l2 = gen_new_label(); | |
4958 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4959 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4960 | tcg_gen_br(l2); | |
4961 | gen_set_label(l1); | |
4962 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4963 | gen_set_label(l2); | |
76a66253 | 4964 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4965 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4966 | } |
4967 | ||
4968 | /* dozo - dozo. */ | |
99e300ef | 4969 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4970 | { |
22e0e173 AJ |
4971 | int l1 = gen_new_label(); |
4972 | int l2 = gen_new_label(); | |
4973 | TCGv t0 = tcg_temp_new(); | |
4974 | TCGv t1 = tcg_temp_new(); | |
4975 | TCGv t2 = tcg_temp_new(); | |
4976 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4977 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4978 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4979 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4980 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4981 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4982 | tcg_gen_andc_tl(t1, t1, t2); | |
4983 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4984 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4985 | tcg_gen_movi_tl(cpu_ov, 1); |
4986 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4987 | tcg_gen_br(l2); |
4988 | gen_set_label(l1); | |
4989 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4990 | gen_set_label(l2); | |
4991 | tcg_temp_free(t0); | |
4992 | tcg_temp_free(t1); | |
4993 | tcg_temp_free(t2); | |
76a66253 | 4994 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4995 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4996 | } |
4997 | ||
4998 | /* dozi */ | |
99e300ef | 4999 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 5000 | { |
22e0e173 AJ |
5001 | target_long simm = SIMM(ctx->opcode); |
5002 | int l1 = gen_new_label(); | |
5003 | int l2 = gen_new_label(); | |
5004 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
5005 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
5006 | tcg_gen_br(l2); | |
5007 | gen_set_label(l1); | |
5008 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
5009 | gen_set_label(l2); | |
5010 | if (unlikely(Rc(ctx->opcode) != 0)) | |
5011 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
5012 | } |
5013 | ||
76a66253 | 5014 | /* lscbx - lscbx. */ |
99e300ef | 5015 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 5016 | { |
bdb4b689 AJ |
5017 | TCGv t0 = tcg_temp_new(); |
5018 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
5019 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
5020 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 5021 | |
76db3ba4 | 5022 | gen_addr_reg_index(ctx, t0); |
76a66253 | 5023 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 5024 | gen_update_nip(ctx, ctx->nip - 4); |
2f5a189c | 5025 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
5026 | tcg_temp_free_i32(t1); |
5027 | tcg_temp_free_i32(t2); | |
5028 | tcg_temp_free_i32(t3); | |
3d7b417e | 5029 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 5030 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 5031 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
5032 | gen_set_Rc0(ctx, t0); |
5033 | tcg_temp_free(t0); | |
76a66253 JM |
5034 | } |
5035 | ||
5036 | /* maskg - maskg. */ | |
99e300ef | 5037 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 5038 | { |
22e0e173 AJ |
5039 | int l1 = gen_new_label(); |
5040 | TCGv t0 = tcg_temp_new(); | |
5041 | TCGv t1 = tcg_temp_new(); | |
5042 | TCGv t2 = tcg_temp_new(); | |
5043 | TCGv t3 = tcg_temp_new(); | |
5044 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
5045 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5046 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
5047 | tcg_gen_addi_tl(t2, t0, 1); | |
5048 | tcg_gen_shr_tl(t2, t3, t2); | |
5049 | tcg_gen_shr_tl(t3, t3, t1); | |
5050 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
5051 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
5052 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5053 | gen_set_label(l1); | |
5054 | tcg_temp_free(t0); | |
5055 | tcg_temp_free(t1); | |
5056 | tcg_temp_free(t2); | |
5057 | tcg_temp_free(t3); | |
76a66253 | 5058 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5059 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5060 | } |
5061 | ||
5062 | /* maskir - maskir. */ | |
99e300ef | 5063 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 5064 | { |
22e0e173 AJ |
5065 | TCGv t0 = tcg_temp_new(); |
5066 | TCGv t1 = tcg_temp_new(); | |
5067 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5068 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5069 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5070 | tcg_temp_free(t0); | |
5071 | tcg_temp_free(t1); | |
76a66253 | 5072 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5073 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5074 | } |
5075 | ||
5076 | /* mul - mul. */ | |
99e300ef | 5077 | static void gen_mul(DisasContext *ctx) |
76a66253 | 5078 | { |
22e0e173 AJ |
5079 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5080 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5081 | TCGv t2 = tcg_temp_new(); | |
5082 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
5083 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5084 | tcg_gen_mul_i64(t0, t0, t1); | |
5085 | tcg_gen_trunc_i64_tl(t2, t0); | |
5086 | gen_store_spr(SPR_MQ, t2); | |
5087 | tcg_gen_shri_i64(t1, t0, 32); | |
5088 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5089 | tcg_temp_free_i64(t0); | |
5090 | tcg_temp_free_i64(t1); | |
5091 | tcg_temp_free(t2); | |
76a66253 | 5092 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5093 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5094 | } |
5095 | ||
5096 | /* mulo - mulo. */ | |
99e300ef | 5097 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 5098 | { |
22e0e173 AJ |
5099 | int l1 = gen_new_label(); |
5100 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
5101 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5102 | TCGv t2 = tcg_temp_new(); | |
5103 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5104 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
5105 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
5106 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5107 | tcg_gen_mul_i64(t0, t0, t1); | |
5108 | tcg_gen_trunc_i64_tl(t2, t0); | |
5109 | gen_store_spr(SPR_MQ, t2); | |
5110 | tcg_gen_shri_i64(t1, t0, 32); | |
5111 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5112 | tcg_gen_ext32s_i64(t1, t0); | |
5113 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
5114 | tcg_gen_movi_tl(cpu_ov, 1); |
5115 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
5116 | gen_set_label(l1); |
5117 | tcg_temp_free_i64(t0); | |
5118 | tcg_temp_free_i64(t1); | |
5119 | tcg_temp_free(t2); | |
76a66253 | 5120 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5121 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5122 | } |
5123 | ||
5124 | /* nabs - nabs. */ | |
99e300ef | 5125 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 5126 | { |
22e0e173 AJ |
5127 | int l1 = gen_new_label(); |
5128 | int l2 = gen_new_label(); | |
5129 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
5130 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5131 | tcg_gen_br(l2); | |
5132 | gen_set_label(l1); | |
5133 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5134 | gen_set_label(l2); | |
76a66253 | 5135 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5136 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5137 | } |
5138 | ||
5139 | /* nabso - nabso. */ | |
99e300ef | 5140 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 5141 | { |
22e0e173 AJ |
5142 | int l1 = gen_new_label(); |
5143 | int l2 = gen_new_label(); | |
5144 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
5145 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5146 | tcg_gen_br(l2); | |
5147 | gen_set_label(l1); | |
5148 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5149 | gen_set_label(l2); | |
5150 | /* nabs never overflows */ | |
da91a00f | 5151 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 5152 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5153 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5154 | } |
5155 | ||
5156 | /* rlmi - rlmi. */ | |
99e300ef | 5157 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 5158 | { |
7487953d AJ |
5159 | uint32_t mb = MB(ctx->opcode); |
5160 | uint32_t me = ME(ctx->opcode); | |
5161 | TCGv t0 = tcg_temp_new(); | |
5162 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5163 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5164 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
5165 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
5166 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
5167 | tcg_temp_free(t0); | |
76a66253 | 5168 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5169 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5170 | } |
5171 | ||
5172 | /* rrib - rrib. */ | |
99e300ef | 5173 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 5174 | { |
7487953d AJ |
5175 | TCGv t0 = tcg_temp_new(); |
5176 | TCGv t1 = tcg_temp_new(); | |
5177 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5178 | tcg_gen_movi_tl(t1, 0x80000000); | |
5179 | tcg_gen_shr_tl(t1, t1, t0); | |
5180 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5181 | tcg_gen_and_tl(t0, t0, t1); | |
5182 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
5183 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5184 | tcg_temp_free(t0); | |
5185 | tcg_temp_free(t1); | |
76a66253 | 5186 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5187 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5188 | } |
5189 | ||
5190 | /* sle - sle. */ | |
99e300ef | 5191 | static void gen_sle(DisasContext *ctx) |
76a66253 | 5192 | { |
7487953d AJ |
5193 | TCGv t0 = tcg_temp_new(); |
5194 | TCGv t1 = tcg_temp_new(); | |
5195 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5196 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5197 | tcg_gen_subfi_tl(t1, 32, t1); | |
5198 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5199 | tcg_gen_or_tl(t1, t0, t1); | |
5200 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5201 | gen_store_spr(SPR_MQ, t1); | |
5202 | tcg_temp_free(t0); | |
5203 | tcg_temp_free(t1); | |
76a66253 | 5204 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5205 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5206 | } |
5207 | ||
5208 | /* sleq - sleq. */ | |
99e300ef | 5209 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 5210 | { |
7487953d AJ |
5211 | TCGv t0 = tcg_temp_new(); |
5212 | TCGv t1 = tcg_temp_new(); | |
5213 | TCGv t2 = tcg_temp_new(); | |
5214 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5215 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
5216 | tcg_gen_shl_tl(t2, t2, t0); | |
5217 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5218 | gen_load_spr(t1, SPR_MQ); | |
5219 | gen_store_spr(SPR_MQ, t0); | |
5220 | tcg_gen_and_tl(t0, t0, t2); | |
5221 | tcg_gen_andc_tl(t1, t1, t2); | |
5222 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5223 | tcg_temp_free(t0); | |
5224 | tcg_temp_free(t1); | |
5225 | tcg_temp_free(t2); | |
76a66253 | 5226 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5227 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5228 | } |
5229 | ||
5230 | /* sliq - sliq. */ | |
99e300ef | 5231 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 5232 | { |
7487953d AJ |
5233 | int sh = SH(ctx->opcode); |
5234 | TCGv t0 = tcg_temp_new(); | |
5235 | TCGv t1 = tcg_temp_new(); | |
5236 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5237 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5238 | tcg_gen_or_tl(t1, t0, t1); | |
5239 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5240 | gen_store_spr(SPR_MQ, t1); | |
5241 | tcg_temp_free(t0); | |
5242 | tcg_temp_free(t1); | |
76a66253 | 5243 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5244 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5245 | } |
5246 | ||
5247 | /* slliq - slliq. */ | |
99e300ef | 5248 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5249 | { |
7487953d AJ |
5250 | int sh = SH(ctx->opcode); |
5251 | TCGv t0 = tcg_temp_new(); | |
5252 | TCGv t1 = tcg_temp_new(); | |
5253 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5254 | gen_load_spr(t1, SPR_MQ); | |
5255 | gen_store_spr(SPR_MQ, t0); | |
5256 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5257 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5258 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5259 | tcg_temp_free(t0); | |
5260 | tcg_temp_free(t1); | |
76a66253 | 5261 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5262 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5263 | } |
5264 | ||
5265 | /* sllq - sllq. */ | |
99e300ef | 5266 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5267 | { |
7487953d AJ |
5268 | int l1 = gen_new_label(); |
5269 | int l2 = gen_new_label(); | |
5270 | TCGv t0 = tcg_temp_local_new(); | |
5271 | TCGv t1 = tcg_temp_local_new(); | |
5272 | TCGv t2 = tcg_temp_local_new(); | |
5273 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5274 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5275 | tcg_gen_shl_tl(t1, t1, t2); | |
5276 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5277 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5278 | gen_load_spr(t0, SPR_MQ); | |
5279 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5280 | tcg_gen_br(l2); | |
5281 | gen_set_label(l1); | |
5282 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5283 | gen_load_spr(t2, SPR_MQ); | |
5284 | tcg_gen_andc_tl(t1, t2, t1); | |
5285 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5286 | gen_set_label(l2); | |
5287 | tcg_temp_free(t0); | |
5288 | tcg_temp_free(t1); | |
5289 | tcg_temp_free(t2); | |
76a66253 | 5290 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5291 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5292 | } |
5293 | ||
5294 | /* slq - slq. */ | |
99e300ef | 5295 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5296 | { |
7487953d AJ |
5297 | int l1 = gen_new_label(); |
5298 | TCGv t0 = tcg_temp_new(); | |
5299 | TCGv t1 = tcg_temp_new(); | |
5300 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5301 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5302 | tcg_gen_subfi_tl(t1, 32, t1); | |
5303 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5304 | tcg_gen_or_tl(t1, t0, t1); | |
5305 | gen_store_spr(SPR_MQ, t1); | |
5306 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5307 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5308 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5309 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5310 | gen_set_label(l1); | |
5311 | tcg_temp_free(t0); | |
5312 | tcg_temp_free(t1); | |
76a66253 | 5313 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5314 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5315 | } |
5316 | ||
d9bce9d9 | 5317 | /* sraiq - sraiq. */ |
99e300ef | 5318 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5319 | { |
7487953d AJ |
5320 | int sh = SH(ctx->opcode); |
5321 | int l1 = gen_new_label(); | |
5322 | TCGv t0 = tcg_temp_new(); | |
5323 | TCGv t1 = tcg_temp_new(); | |
5324 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5325 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5326 | tcg_gen_or_tl(t0, t0, t1); | |
5327 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 5328 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5329 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5330 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 5331 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5332 | gen_set_label(l1); |
5333 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5334 | tcg_temp_free(t0); | |
5335 | tcg_temp_free(t1); | |
76a66253 | 5336 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5337 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5338 | } |
5339 | ||
5340 | /* sraq - sraq. */ | |
99e300ef | 5341 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5342 | { |
7487953d AJ |
5343 | int l1 = gen_new_label(); |
5344 | int l2 = gen_new_label(); | |
5345 | TCGv t0 = tcg_temp_new(); | |
5346 | TCGv t1 = tcg_temp_local_new(); | |
5347 | TCGv t2 = tcg_temp_local_new(); | |
5348 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5349 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5350 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5351 | tcg_gen_subfi_tl(t2, 32, t2); | |
5352 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5353 | tcg_gen_or_tl(t0, t0, t2); | |
5354 | gen_store_spr(SPR_MQ, t0); | |
5355 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5356 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5357 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5358 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5359 | gen_set_label(l1); | |
5360 | tcg_temp_free(t0); | |
5361 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5362 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5363 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5364 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5365 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5366 | gen_set_label(l2); |
5367 | tcg_temp_free(t1); | |
5368 | tcg_temp_free(t2); | |
76a66253 | 5369 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5370 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5371 | } |
5372 | ||
5373 | /* sre - sre. */ | |
99e300ef | 5374 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5375 | { |
7487953d AJ |
5376 | TCGv t0 = tcg_temp_new(); |
5377 | TCGv t1 = tcg_temp_new(); | |
5378 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5379 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5380 | tcg_gen_subfi_tl(t1, 32, t1); | |
5381 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5382 | tcg_gen_or_tl(t1, t0, t1); | |
5383 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5384 | gen_store_spr(SPR_MQ, t1); | |
5385 | tcg_temp_free(t0); | |
5386 | tcg_temp_free(t1); | |
76a66253 | 5387 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5388 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5389 | } |
5390 | ||
5391 | /* srea - srea. */ | |
99e300ef | 5392 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5393 | { |
7487953d AJ |
5394 | TCGv t0 = tcg_temp_new(); |
5395 | TCGv t1 = tcg_temp_new(); | |
5396 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5397 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5398 | gen_store_spr(SPR_MQ, t0); | |
5399 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5400 | tcg_temp_free(t0); | |
5401 | tcg_temp_free(t1); | |
76a66253 | 5402 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5403 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5404 | } |
5405 | ||
5406 | /* sreq */ | |
99e300ef | 5407 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5408 | { |
7487953d AJ |
5409 | TCGv t0 = tcg_temp_new(); |
5410 | TCGv t1 = tcg_temp_new(); | |
5411 | TCGv t2 = tcg_temp_new(); | |
5412 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5413 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5414 | tcg_gen_shr_tl(t1, t1, t0); | |
5415 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5416 | gen_load_spr(t2, SPR_MQ); | |
5417 | gen_store_spr(SPR_MQ, t0); | |
5418 | tcg_gen_and_tl(t0, t0, t1); | |
5419 | tcg_gen_andc_tl(t2, t2, t1); | |
5420 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5421 | tcg_temp_free(t0); | |
5422 | tcg_temp_free(t1); | |
5423 | tcg_temp_free(t2); | |
76a66253 | 5424 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5425 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5426 | } |
5427 | ||
5428 | /* sriq */ | |
99e300ef | 5429 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5430 | { |
7487953d AJ |
5431 | int sh = SH(ctx->opcode); |
5432 | TCGv t0 = tcg_temp_new(); | |
5433 | TCGv t1 = tcg_temp_new(); | |
5434 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5435 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5436 | tcg_gen_or_tl(t1, t0, t1); | |
5437 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5438 | gen_store_spr(SPR_MQ, t1); | |
5439 | tcg_temp_free(t0); | |
5440 | tcg_temp_free(t1); | |
76a66253 | 5441 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5442 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5443 | } |
5444 | ||
5445 | /* srliq */ | |
99e300ef | 5446 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5447 | { |
7487953d AJ |
5448 | int sh = SH(ctx->opcode); |
5449 | TCGv t0 = tcg_temp_new(); | |
5450 | TCGv t1 = tcg_temp_new(); | |
5451 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5452 | gen_load_spr(t1, SPR_MQ); | |
5453 | gen_store_spr(SPR_MQ, t0); | |
5454 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5455 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5456 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5457 | tcg_temp_free(t0); | |
5458 | tcg_temp_free(t1); | |
76a66253 | 5459 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5460 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5461 | } |
5462 | ||
5463 | /* srlq */ | |
99e300ef | 5464 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5465 | { |
7487953d AJ |
5466 | int l1 = gen_new_label(); |
5467 | int l2 = gen_new_label(); | |
5468 | TCGv t0 = tcg_temp_local_new(); | |
5469 | TCGv t1 = tcg_temp_local_new(); | |
5470 | TCGv t2 = tcg_temp_local_new(); | |
5471 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5472 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5473 | tcg_gen_shr_tl(t2, t1, t2); | |
5474 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5475 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5476 | gen_load_spr(t0, SPR_MQ); | |
5477 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5478 | tcg_gen_br(l2); | |
5479 | gen_set_label(l1); | |
5480 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5481 | tcg_gen_and_tl(t0, t0, t2); | |
5482 | gen_load_spr(t1, SPR_MQ); | |
5483 | tcg_gen_andc_tl(t1, t1, t2); | |
5484 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5485 | gen_set_label(l2); | |
5486 | tcg_temp_free(t0); | |
5487 | tcg_temp_free(t1); | |
5488 | tcg_temp_free(t2); | |
76a66253 | 5489 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5490 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5491 | } |
5492 | ||
5493 | /* srq */ | |
99e300ef | 5494 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5495 | { |
7487953d AJ |
5496 | int l1 = gen_new_label(); |
5497 | TCGv t0 = tcg_temp_new(); | |
5498 | TCGv t1 = tcg_temp_new(); | |
5499 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5500 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5501 | tcg_gen_subfi_tl(t1, 32, t1); | |
5502 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5503 | tcg_gen_or_tl(t1, t0, t1); | |
5504 | gen_store_spr(SPR_MQ, t1); | |
5505 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5506 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5507 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5508 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5509 | gen_set_label(l1); | |
5510 | tcg_temp_free(t0); | |
5511 | tcg_temp_free(t1); | |
76a66253 | 5512 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5513 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5514 | } |
5515 | ||
5516 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5517 | |
54623277 | 5518 | /* dsa */ |
99e300ef | 5519 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5520 | { |
5521 | /* XXX: TODO */ | |
e06fcd75 | 5522 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5523 | } |
5524 | ||
5525 | /* esa */ | |
99e300ef | 5526 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5527 | { |
5528 | /* XXX: TODO */ | |
e06fcd75 | 5529 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5530 | } |
5531 | ||
5532 | /* mfrom */ | |
99e300ef | 5533 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5534 | { |
5535 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5536 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5537 | #else |
76db3ba4 | 5538 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5539 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5540 | return; |
5541 | } | |
cf02a65c | 5542 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5543 | #endif |
5544 | } | |
5545 | ||
5546 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5547 | |
54623277 | 5548 | /* tlbld */ |
e8eaa2c0 | 5549 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5550 | { |
5551 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5552 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5553 | #else |
76db3ba4 | 5554 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5555 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5556 | return; |
5557 | } | |
c6c7cf05 | 5558 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5559 | #endif |
5560 | } | |
5561 | ||
5562 | /* tlbli */ | |
e8eaa2c0 | 5563 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5564 | { |
5565 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5566 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5567 | #else |
76db3ba4 | 5568 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5569 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5570 | return; |
5571 | } | |
c6c7cf05 | 5572 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5573 | #endif |
5574 | } | |
5575 | ||
7dbe11ac | 5576 | /* 74xx TLB management */ |
e8eaa2c0 | 5577 | |
54623277 | 5578 | /* tlbld */ |
e8eaa2c0 | 5579 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5580 | { |
5581 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5582 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5583 | #else |
76db3ba4 | 5584 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5585 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5586 | return; |
5587 | } | |
c6c7cf05 | 5588 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5589 | #endif |
5590 | } | |
5591 | ||
5592 | /* tlbli */ | |
e8eaa2c0 | 5593 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5594 | { |
5595 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5596 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5597 | #else |
76db3ba4 | 5598 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5599 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5600 | return; |
5601 | } | |
c6c7cf05 | 5602 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5603 | #endif |
5604 | } | |
5605 | ||
76a66253 | 5606 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5607 | |
54623277 | 5608 | /* clf */ |
99e300ef | 5609 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5610 | { |
5611 | /* Cache line flush: implemented as no-op */ | |
5612 | } | |
5613 | ||
5614 | /* cli */ | |
99e300ef | 5615 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5616 | { |
7f75ffd3 | 5617 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5618 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5619 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5620 | #else |
76db3ba4 | 5621 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5622 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5623 | return; |
5624 | } | |
5625 | #endif | |
5626 | } | |
5627 | ||
5628 | /* dclst */ | |
99e300ef | 5629 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5630 | { |
5631 | /* Data cache line store: treated as no-op */ | |
5632 | } | |
5633 | ||
99e300ef | 5634 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5635 | { |
5636 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5637 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5638 | #else |
74d37793 AJ |
5639 | int ra = rA(ctx->opcode); |
5640 | int rd = rD(ctx->opcode); | |
5641 | TCGv t0; | |
76db3ba4 | 5642 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5643 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5644 | return; |
5645 | } | |
74d37793 | 5646 | t0 = tcg_temp_new(); |
76db3ba4 | 5647 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5648 | tcg_gen_shri_tl(t0, t0, 28); |
5649 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5650 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5651 | tcg_temp_free(t0); |
76a66253 | 5652 | if (ra != 0 && ra != rd) |
74d37793 | 5653 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5654 | #endif |
5655 | } | |
5656 | ||
99e300ef | 5657 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5658 | { |
5659 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5660 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5661 | #else |
22e0e173 | 5662 | TCGv t0; |
76db3ba4 | 5663 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5664 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5665 | return; |
5666 | } | |
22e0e173 | 5667 | t0 = tcg_temp_new(); |
76db3ba4 | 5668 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5669 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5670 | tcg_temp_free(t0); |
76a66253 JM |
5671 | #endif |
5672 | } | |
5673 | ||
99e300ef | 5674 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5675 | { |
5676 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5677 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5678 | #else |
76db3ba4 | 5679 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5680 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5681 | return; |
5682 | } | |
e5f17ac6 | 5683 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5684 | gen_sync_exception(ctx); |
76a66253 JM |
5685 | #endif |
5686 | } | |
5687 | ||
5688 | /* svc is not implemented for now */ | |
5689 | ||
5690 | /* POWER2 specific instructions */ | |
5691 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5692 | |
5693 | /* lfq */ | |
99e300ef | 5694 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5695 | { |
01a4afeb | 5696 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5697 | TCGv t0; |
5698 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5699 | t0 = tcg_temp_new(); | |
5700 | gen_addr_imm_index(ctx, t0, 0); | |
5701 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5702 | gen_addr_add(ctx, t0, t0, 8); | |
5703 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5704 | tcg_temp_free(t0); |
76a66253 JM |
5705 | } |
5706 | ||
5707 | /* lfqu */ | |
99e300ef | 5708 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5709 | { |
5710 | int ra = rA(ctx->opcode); | |
01a4afeb | 5711 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5712 | TCGv t0, t1; |
5713 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5714 | t0 = tcg_temp_new(); | |
5715 | t1 = tcg_temp_new(); | |
5716 | gen_addr_imm_index(ctx, t0, 0); | |
5717 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5718 | gen_addr_add(ctx, t1, t0, 8); | |
5719 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5720 | if (ra != 0) |
01a4afeb AJ |
5721 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5722 | tcg_temp_free(t0); | |
5723 | tcg_temp_free(t1); | |
76a66253 JM |
5724 | } |
5725 | ||
5726 | /* lfqux */ | |
99e300ef | 5727 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5728 | { |
5729 | int ra = rA(ctx->opcode); | |
01a4afeb | 5730 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5731 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5732 | TCGv t0, t1; | |
5733 | t0 = tcg_temp_new(); | |
5734 | gen_addr_reg_index(ctx, t0); | |
5735 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5736 | t1 = tcg_temp_new(); | |
5737 | gen_addr_add(ctx, t1, t0, 8); | |
5738 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5739 | tcg_temp_free(t1); | |
76a66253 | 5740 | if (ra != 0) |
01a4afeb AJ |
5741 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5742 | tcg_temp_free(t0); | |
76a66253 JM |
5743 | } |
5744 | ||
5745 | /* lfqx */ | |
99e300ef | 5746 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5747 | { |
01a4afeb | 5748 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5749 | TCGv t0; |
5750 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5751 | t0 = tcg_temp_new(); | |
5752 | gen_addr_reg_index(ctx, t0); | |
5753 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5754 | gen_addr_add(ctx, t0, t0, 8); | |
5755 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5756 | tcg_temp_free(t0); |
76a66253 JM |
5757 | } |
5758 | ||
5759 | /* stfq */ | |
99e300ef | 5760 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5761 | { |
01a4afeb | 5762 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5763 | TCGv t0; |
5764 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5765 | t0 = tcg_temp_new(); | |
5766 | gen_addr_imm_index(ctx, t0, 0); | |
5767 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5768 | gen_addr_add(ctx, t0, t0, 8); | |
5769 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5770 | tcg_temp_free(t0); |
76a66253 JM |
5771 | } |
5772 | ||
5773 | /* stfqu */ | |
99e300ef | 5774 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5775 | { |
5776 | int ra = rA(ctx->opcode); | |
01a4afeb | 5777 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5778 | TCGv t0, t1; |
5779 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5780 | t0 = tcg_temp_new(); | |
5781 | gen_addr_imm_index(ctx, t0, 0); | |
5782 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5783 | t1 = tcg_temp_new(); | |
5784 | gen_addr_add(ctx, t1, t0, 8); | |
5785 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5786 | tcg_temp_free(t1); | |
76a66253 | 5787 | if (ra != 0) |
01a4afeb AJ |
5788 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5789 | tcg_temp_free(t0); | |
76a66253 JM |
5790 | } |
5791 | ||
5792 | /* stfqux */ | |
99e300ef | 5793 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5794 | { |
5795 | int ra = rA(ctx->opcode); | |
01a4afeb | 5796 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5797 | TCGv t0, t1; |
5798 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5799 | t0 = tcg_temp_new(); | |
5800 | gen_addr_reg_index(ctx, t0); | |
5801 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5802 | t1 = tcg_temp_new(); | |
5803 | gen_addr_add(ctx, t1, t0, 8); | |
5804 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5805 | tcg_temp_free(t1); | |
76a66253 | 5806 | if (ra != 0) |
01a4afeb AJ |
5807 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5808 | tcg_temp_free(t0); | |
76a66253 JM |
5809 | } |
5810 | ||
5811 | /* stfqx */ | |
99e300ef | 5812 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5813 | { |
01a4afeb | 5814 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5815 | TCGv t0; |
5816 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5817 | t0 = tcg_temp_new(); | |
5818 | gen_addr_reg_index(ctx, t0); | |
5819 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5820 | gen_addr_add(ctx, t0, t0, 8); | |
5821 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5822 | tcg_temp_free(t0); |
76a66253 JM |
5823 | } |
5824 | ||
5825 | /* BookE specific instructions */ | |
99e300ef | 5826 | |
54623277 | 5827 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5828 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5829 | { |
5830 | /* XXX: TODO */ | |
e06fcd75 | 5831 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5832 | } |
5833 | ||
2662a059 | 5834 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5835 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5836 | { |
5837 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5838 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5839 | #else |
74d37793 | 5840 | TCGv t0; |
76db3ba4 | 5841 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5842 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5843 | return; |
5844 | } | |
ec72e276 | 5845 | t0 = tcg_temp_new(); |
76db3ba4 | 5846 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5847 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5848 | tcg_temp_free(t0); |
76a66253 JM |
5849 | #endif |
5850 | } | |
5851 | ||
5852 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5853 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5854 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5855 | { |
182608d4 AJ |
5856 | TCGv t0, t1; |
5857 | ||
a7812ae4 PB |
5858 | t0 = tcg_temp_local_new(); |
5859 | t1 = tcg_temp_local_new(); | |
182608d4 | 5860 | |
76a66253 JM |
5861 | switch (opc3 & 0x0D) { |
5862 | case 0x05: | |
5863 | /* macchw - macchw. - macchwo - macchwo. */ | |
5864 | /* macchws - macchws. - macchwso - macchwso. */ | |
5865 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5866 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5867 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5868 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5869 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5870 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5871 | break; |
5872 | case 0x04: | |
5873 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5874 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5875 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5876 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5877 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5878 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5879 | break; |
5880 | case 0x01: | |
5881 | /* machhw - machhw. - machhwo - machhwo. */ | |
5882 | /* machhws - machhws. - machhwso - machhwso. */ | |
5883 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5884 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5885 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5886 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5887 | tcg_gen_ext16s_tl(t0, t0); | |
5888 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5889 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5890 | break; |
5891 | case 0x00: | |
5892 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5893 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5894 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5895 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5896 | tcg_gen_ext16u_tl(t0, t0); | |
5897 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5898 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5899 | break; |
5900 | case 0x0D: | |
5901 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5902 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5903 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5904 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5905 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5906 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5907 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5908 | break; |
5909 | case 0x0C: | |
5910 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5911 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5912 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5913 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5914 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5915 | break; |
5916 | } | |
76a66253 | 5917 | if (opc2 & 0x04) { |
182608d4 AJ |
5918 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5919 | tcg_gen_mul_tl(t1, t0, t1); | |
5920 | if (opc2 & 0x02) { | |
5921 | /* nmultiply-and-accumulate (0x0E) */ | |
5922 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5923 | } else { | |
5924 | /* multiply-and-accumulate (0x0C) */ | |
5925 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5926 | } | |
5927 | ||
5928 | if (opc3 & 0x12) { | |
5929 | /* Check overflow and/or saturate */ | |
5930 | int l1 = gen_new_label(); | |
5931 | ||
5932 | if (opc3 & 0x10) { | |
5933 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5934 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5935 | } |
5936 | if (opc3 & 0x01) { | |
5937 | /* Signed */ | |
5938 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5939 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5940 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5941 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5942 | if (opc3 & 0x02) { |
182608d4 AJ |
5943 | /* Saturate */ |
5944 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5945 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5946 | } | |
5947 | } else { | |
5948 | /* Unsigned */ | |
5949 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5950 | if (opc3 & 0x02) { |
182608d4 AJ |
5951 | /* Saturate */ |
5952 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5953 | } | |
5954 | } | |
5955 | if (opc3 & 0x10) { | |
5956 | /* Check overflow */ | |
da91a00f RH |
5957 | tcg_gen_movi_tl(cpu_ov, 1); |
5958 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5959 | } |
5960 | gen_set_label(l1); | |
5961 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5962 | } | |
5963 | } else { | |
5964 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5965 | } |
182608d4 AJ |
5966 | tcg_temp_free(t0); |
5967 | tcg_temp_free(t1); | |
76a66253 JM |
5968 | if (unlikely(Rc) != 0) { |
5969 | /* Update Rc0 */ | |
182608d4 | 5970 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5971 | } |
5972 | } | |
5973 | ||
a750fc0b | 5974 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5975 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5976 | { \ |
5977 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5978 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5979 | } | |
5980 | ||
5981 | /* macchw - macchw. */ | |
a750fc0b | 5982 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5983 | /* macchwo - macchwo. */ |
a750fc0b | 5984 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5985 | /* macchws - macchws. */ |
a750fc0b | 5986 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5987 | /* macchwso - macchwso. */ |
a750fc0b | 5988 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5989 | /* macchwsu - macchwsu. */ |
a750fc0b | 5990 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5991 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5992 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5993 | /* macchwu - macchwu. */ |
a750fc0b | 5994 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5995 | /* macchwuo - macchwuo. */ |
a750fc0b | 5996 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5997 | /* machhw - machhw. */ |
a750fc0b | 5998 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5999 | /* machhwo - machhwo. */ |
a750fc0b | 6000 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 6001 | /* machhws - machhws. */ |
a750fc0b | 6002 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 6003 | /* machhwso - machhwso. */ |
a750fc0b | 6004 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 6005 | /* machhwsu - machhwsu. */ |
a750fc0b | 6006 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 6007 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 6008 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 6009 | /* machhwu - machhwu. */ |
a750fc0b | 6010 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 6011 | /* machhwuo - machhwuo. */ |
a750fc0b | 6012 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 6013 | /* maclhw - maclhw. */ |
a750fc0b | 6014 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 6015 | /* maclhwo - maclhwo. */ |
a750fc0b | 6016 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 6017 | /* maclhws - maclhws. */ |
a750fc0b | 6018 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 6019 | /* maclhwso - maclhwso. */ |
a750fc0b | 6020 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 6021 | /* maclhwu - maclhwu. */ |
a750fc0b | 6022 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 6023 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 6024 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 6025 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 6026 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 6027 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 6028 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 6029 | /* nmacchw - nmacchw. */ |
a750fc0b | 6030 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 6031 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 6032 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 6033 | /* nmacchws - nmacchws. */ |
a750fc0b | 6034 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 6035 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 6036 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 6037 | /* nmachhw - nmachhw. */ |
a750fc0b | 6038 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 6039 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 6040 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 6041 | /* nmachhws - nmachhws. */ |
a750fc0b | 6042 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 6043 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 6044 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 6045 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 6046 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 6047 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 6048 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 6049 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 6050 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 6051 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 6052 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
6053 | |
6054 | /* mulchw - mulchw. */ | |
a750fc0b | 6055 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 6056 | /* mulchwu - mulchwu. */ |
a750fc0b | 6057 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 6058 | /* mulhhw - mulhhw. */ |
a750fc0b | 6059 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 6060 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 6061 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 6062 | /* mullhw - mullhw. */ |
a750fc0b | 6063 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 6064 | /* mullhwu - mullhwu. */ |
a750fc0b | 6065 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
6066 | |
6067 | /* mfdcr */ | |
99e300ef | 6068 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
6069 | { |
6070 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6071 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 6072 | #else |
06dca6a7 | 6073 | TCGv dcrn; |
76db3ba4 | 6074 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6075 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
6076 | return; |
6077 | } | |
06dca6a7 AJ |
6078 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6079 | gen_update_nip(ctx, ctx->nip - 4); | |
6080 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 6081 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 6082 | tcg_temp_free(dcrn); |
76a66253 JM |
6083 | #endif |
6084 | } | |
6085 | ||
6086 | /* mtdcr */ | |
99e300ef | 6087 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
6088 | { |
6089 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6090 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 6091 | #else |
06dca6a7 | 6092 | TCGv dcrn; |
76db3ba4 | 6093 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6094 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
6095 | return; |
6096 | } | |
06dca6a7 AJ |
6097 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6098 | gen_update_nip(ctx, ctx->nip - 4); | |
6099 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 6100 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 6101 | tcg_temp_free(dcrn); |
a42bd6cc JM |
6102 | #endif |
6103 | } | |
6104 | ||
6105 | /* mfdcrx */ | |
2662a059 | 6106 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6107 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
6108 | { |
6109 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6110 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 6111 | #else |
76db3ba4 | 6112 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6113 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
6114 | return; |
6115 | } | |
06dca6a7 AJ |
6116 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6117 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
6118 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6119 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 6120 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
6121 | #endif |
6122 | } | |
6123 | ||
6124 | /* mtdcrx */ | |
2662a059 | 6125 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6126 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
6127 | { |
6128 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6129 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 6130 | #else |
76db3ba4 | 6131 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6132 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
6133 | return; |
6134 | } | |
06dca6a7 AJ |
6135 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6136 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
6137 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6138 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 6139 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
6140 | #endif |
6141 | } | |
6142 | ||
a750fc0b | 6143 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 6144 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 6145 | { |
06dca6a7 AJ |
6146 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6147 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
6148 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6149 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
6150 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6151 | } | |
6152 | ||
6153 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 6154 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 6155 | { |
06dca6a7 AJ |
6156 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6157 | gen_update_nip(ctx, ctx->nip - 4); | |
975e5463 | 6158 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 6159 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
6160 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6161 | } | |
6162 | ||
76a66253 | 6163 | /* dccci */ |
99e300ef | 6164 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
6165 | { |
6166 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6167 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6168 | #else |
76db3ba4 | 6169 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6170 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6171 | return; |
6172 | } | |
6173 | /* interpreted as no-op */ | |
6174 | #endif | |
6175 | } | |
6176 | ||
6177 | /* dcread */ | |
99e300ef | 6178 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
6179 | { |
6180 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6181 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6182 | #else |
b61f2753 | 6183 | TCGv EA, val; |
76db3ba4 | 6184 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6185 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6186 | return; |
6187 | } | |
76db3ba4 | 6188 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 6189 | EA = tcg_temp_new(); |
76db3ba4 | 6190 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 6191 | val = tcg_temp_new(); |
76db3ba4 | 6192 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
6193 | tcg_temp_free(val); |
6194 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
6195 | tcg_temp_free(EA); | |
76a66253 JM |
6196 | #endif |
6197 | } | |
6198 | ||
6199 | /* icbt */ | |
e8eaa2c0 | 6200 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
6201 | { |
6202 | /* interpreted as no-op */ | |
6203 | /* XXX: specification say this is treated as a load by the MMU | |
6204 | * but does not generate any exception | |
6205 | */ | |
6206 | } | |
6207 | ||
6208 | /* iccci */ | |
99e300ef | 6209 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
6210 | { |
6211 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6212 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6213 | #else |
76db3ba4 | 6214 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6215 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6216 | return; |
6217 | } | |
6218 | /* interpreted as no-op */ | |
6219 | #endif | |
6220 | } | |
6221 | ||
6222 | /* icread */ | |
99e300ef | 6223 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
6224 | { |
6225 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6226 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6227 | #else |
76db3ba4 | 6228 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6229 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6230 | return; |
6231 | } | |
6232 | /* interpreted as no-op */ | |
6233 | #endif | |
6234 | } | |
6235 | ||
76db3ba4 | 6236 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 6237 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
6238 | { |
6239 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6240 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6241 | #else |
76db3ba4 | 6242 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6243 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6244 | return; |
6245 | } | |
6246 | /* Restore CPU state */ | |
e5f17ac6 | 6247 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 6248 | gen_sync_exception(ctx); |
a42bd6cc JM |
6249 | #endif |
6250 | } | |
6251 | ||
99e300ef | 6252 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
6253 | { |
6254 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6255 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6256 | #else |
76db3ba4 | 6257 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6258 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6259 | return; |
6260 | } | |
6261 | /* Restore CPU state */ | |
e5f17ac6 | 6262 | gen_helper_rfci(cpu_env); |
e06fcd75 | 6263 | gen_sync_exception(ctx); |
a42bd6cc JM |
6264 | #endif |
6265 | } | |
6266 | ||
6267 | /* BookE specific */ | |
99e300ef | 6268 | |
54623277 | 6269 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6270 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
6271 | { |
6272 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6273 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6274 | #else |
76db3ba4 | 6275 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6276 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6277 | return; |
6278 | } | |
6279 | /* Restore CPU state */ | |
e5f17ac6 | 6280 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 6281 | gen_sync_exception(ctx); |
76a66253 JM |
6282 | #endif |
6283 | } | |
6284 | ||
2662a059 | 6285 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6286 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
6287 | { |
6288 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6289 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6290 | #else |
76db3ba4 | 6291 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6292 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6293 | return; |
6294 | } | |
6295 | /* Restore CPU state */ | |
e5f17ac6 | 6296 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 6297 | gen_sync_exception(ctx); |
a42bd6cc JM |
6298 | #endif |
6299 | } | |
5eb7995e | 6300 | |
d9bce9d9 | 6301 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 6302 | |
54623277 | 6303 | /* tlbre */ |
e8eaa2c0 | 6304 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
6305 | { |
6306 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6307 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6308 | #else |
76db3ba4 | 6309 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6310 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6311 | return; |
6312 | } | |
6313 | switch (rB(ctx->opcode)) { | |
6314 | case 0: | |
c6c7cf05 BS |
6315 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6316 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6317 | break; |
6318 | case 1: | |
c6c7cf05 BS |
6319 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6320 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6321 | break; |
6322 | default: | |
e06fcd75 | 6323 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6324 | break; |
9a64fbe4 | 6325 | } |
76a66253 JM |
6326 | #endif |
6327 | } | |
6328 | ||
d9bce9d9 | 6329 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 6330 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
6331 | { |
6332 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6333 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6334 | #else |
74d37793 | 6335 | TCGv t0; |
76db3ba4 | 6336 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6337 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6338 | return; |
6339 | } | |
74d37793 | 6340 | t0 = tcg_temp_new(); |
76db3ba4 | 6341 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6342 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6343 | tcg_temp_free(t0); |
6344 | if (Rc(ctx->opcode)) { | |
6345 | int l1 = gen_new_label(); | |
da91a00f | 6346 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6347 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6348 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6349 | gen_set_label(l1); | |
6350 | } | |
76a66253 | 6351 | #endif |
79aceca5 FB |
6352 | } |
6353 | ||
76a66253 | 6354 | /* tlbwe */ |
e8eaa2c0 | 6355 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6356 | { |
76a66253 | 6357 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 6358 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6359 | #else |
76db3ba4 | 6360 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6361 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6362 | return; |
6363 | } | |
6364 | switch (rB(ctx->opcode)) { | |
6365 | case 0: | |
c6c7cf05 BS |
6366 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6367 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6368 | break; |
6369 | case 1: | |
c6c7cf05 BS |
6370 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6371 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6372 | break; |
6373 | default: | |
e06fcd75 | 6374 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6375 | break; |
9a64fbe4 | 6376 | } |
76a66253 JM |
6377 | #endif |
6378 | } | |
6379 | ||
a4bb6c3e | 6380 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6381 | |
54623277 | 6382 | /* tlbre */ |
e8eaa2c0 | 6383 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6384 | { |
6385 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6386 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6387 | #else |
76db3ba4 | 6388 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6389 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6390 | return; |
6391 | } | |
6392 | switch (rB(ctx->opcode)) { | |
6393 | case 0: | |
5eb7995e | 6394 | case 1: |
5eb7995e | 6395 | case 2: |
74d37793 AJ |
6396 | { |
6397 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6398 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6399 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6400 | tcg_temp_free_i32(t0); |
6401 | } | |
5eb7995e JM |
6402 | break; |
6403 | default: | |
e06fcd75 | 6404 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6405 | break; |
6406 | } | |
6407 | #endif | |
6408 | } | |
6409 | ||
6410 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6411 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6412 | { |
6413 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6414 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6415 | #else |
74d37793 | 6416 | TCGv t0; |
76db3ba4 | 6417 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6418 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6419 | return; |
6420 | } | |
74d37793 | 6421 | t0 = tcg_temp_new(); |
76db3ba4 | 6422 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6423 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6424 | tcg_temp_free(t0); |
6425 | if (Rc(ctx->opcode)) { | |
6426 | int l1 = gen_new_label(); | |
da91a00f | 6427 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6428 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6429 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6430 | gen_set_label(l1); | |
6431 | } | |
5eb7995e JM |
6432 | #endif |
6433 | } | |
6434 | ||
6435 | /* tlbwe */ | |
e8eaa2c0 | 6436 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6437 | { |
6438 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6439 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6440 | #else |
76db3ba4 | 6441 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6442 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6443 | return; |
6444 | } | |
6445 | switch (rB(ctx->opcode)) { | |
6446 | case 0: | |
5eb7995e | 6447 | case 1: |
5eb7995e | 6448 | case 2: |
74d37793 AJ |
6449 | { |
6450 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6451 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6452 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6453 | tcg_temp_free_i32(t0); |
6454 | } | |
5eb7995e JM |
6455 | break; |
6456 | default: | |
e06fcd75 | 6457 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6458 | break; |
6459 | } | |
6460 | #endif | |
6461 | } | |
6462 | ||
01662f3e AG |
6463 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6464 | ||
6465 | /* tlbre */ | |
6466 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6467 | { | |
6468 | #if defined(CONFIG_USER_ONLY) | |
6469 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6470 | #else | |
6471 | if (unlikely(!ctx->mem_idx)) { | |
6472 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6473 | return; | |
6474 | } | |
6475 | ||
c6c7cf05 | 6476 | gen_helper_booke206_tlbre(cpu_env); |
01662f3e AG |
6477 | #endif |
6478 | } | |
6479 | ||
6480 | /* tlbsx - tlbsx. */ | |
6481 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6482 | { | |
6483 | #if defined(CONFIG_USER_ONLY) | |
6484 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6485 | #else | |
6486 | TCGv t0; | |
6487 | if (unlikely(!ctx->mem_idx)) { | |
6488 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6489 | return; | |
6490 | } | |
6491 | ||
6492 | if (rA(ctx->opcode)) { | |
6493 | t0 = tcg_temp_new(); | |
6494 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6495 | } else { | |
6496 | t0 = tcg_const_tl(0); | |
6497 | } | |
6498 | ||
6499 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6500 | gen_helper_booke206_tlbsx(cpu_env, t0); |
c80d1df5 | 6501 | tcg_temp_free(t0); |
01662f3e AG |
6502 | #endif |
6503 | } | |
6504 | ||
6505 | /* tlbwe */ | |
6506 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6507 | { | |
6508 | #if defined(CONFIG_USER_ONLY) | |
6509 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6510 | #else | |
6511 | if (unlikely(!ctx->mem_idx)) { | |
6512 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6513 | return; | |
6514 | } | |
3f162d11 | 6515 | gen_update_nip(ctx, ctx->nip - 4); |
c6c7cf05 | 6516 | gen_helper_booke206_tlbwe(cpu_env); |
01662f3e AG |
6517 | #endif |
6518 | } | |
6519 | ||
6520 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6521 | { | |
6522 | #if defined(CONFIG_USER_ONLY) | |
6523 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6524 | #else | |
6525 | TCGv t0; | |
6526 | if (unlikely(!ctx->mem_idx)) { | |
6527 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6528 | return; | |
6529 | } | |
6530 | ||
6531 | t0 = tcg_temp_new(); | |
6532 | gen_addr_reg_index(ctx, t0); | |
6533 | ||
c6c7cf05 | 6534 | gen_helper_booke206_tlbivax(cpu_env, t0); |
c80d1df5 | 6535 | tcg_temp_free(t0); |
01662f3e AG |
6536 | #endif |
6537 | } | |
6538 | ||
6d3db821 AG |
6539 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6540 | { | |
6541 | #if defined(CONFIG_USER_ONLY) | |
6542 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6543 | #else | |
6544 | TCGv t0; | |
6545 | if (unlikely(!ctx->mem_idx)) { | |
6546 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6547 | return; | |
6548 | } | |
6549 | ||
6550 | t0 = tcg_temp_new(); | |
6551 | gen_addr_reg_index(ctx, t0); | |
6552 | ||
6553 | switch((ctx->opcode >> 21) & 0x3) { | |
6554 | case 0: | |
c6c7cf05 | 6555 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6556 | break; |
6557 | case 1: | |
c6c7cf05 | 6558 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6559 | break; |
6560 | case 3: | |
c6c7cf05 | 6561 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6562 | break; |
6563 | default: | |
6564 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6565 | break; | |
6566 | } | |
6567 | ||
6568 | tcg_temp_free(t0); | |
6569 | #endif | |
6570 | } | |
6571 | ||
01662f3e | 6572 | |
76a66253 | 6573 | /* wrtee */ |
99e300ef | 6574 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6575 | { |
6576 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6577 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6578 | #else |
6527f6ea | 6579 | TCGv t0; |
76db3ba4 | 6580 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6581 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6582 | return; |
6583 | } | |
6527f6ea AJ |
6584 | t0 = tcg_temp_new(); |
6585 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6586 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6587 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6588 | tcg_temp_free(t0); | |
dee96f6c JM |
6589 | /* Stop translation to have a chance to raise an exception |
6590 | * if we just set msr_ee to 1 | |
6591 | */ | |
e06fcd75 | 6592 | gen_stop_exception(ctx); |
76a66253 JM |
6593 | #endif |
6594 | } | |
6595 | ||
6596 | /* wrteei */ | |
99e300ef | 6597 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6598 | { |
6599 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6600 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6601 | #else |
76db3ba4 | 6602 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6603 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6604 | return; |
6605 | } | |
fbe73008 | 6606 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6607 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6608 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6609 | gen_stop_exception(ctx); |
6527f6ea | 6610 | } else { |
1b6e5f99 | 6611 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6612 | } |
76a66253 JM |
6613 | #endif |
6614 | } | |
6615 | ||
08e46e54 | 6616 | /* PowerPC 440 specific instructions */ |
99e300ef | 6617 | |
54623277 | 6618 | /* dlmzb */ |
99e300ef | 6619 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6620 | { |
ef0d51af | 6621 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6622 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6623 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6624 | tcg_temp_free_i32(t0); |
76a66253 JM |
6625 | } |
6626 | ||
6627 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6628 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6629 | { |
6630 | /* interpreted as no-op */ | |
6631 | } | |
6632 | ||
6633 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6634 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6635 | { |
6636 | /* interpreted as no-op */ | |
6637 | } | |
6638 | ||
6639 | /* icbt */ | |
e8eaa2c0 | 6640 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6641 | { |
6642 | /* interpreted as no-op */ | |
6643 | /* XXX: specification say this is treated as a load by the MMU | |
6644 | * but does not generate any exception | |
6645 | */ | |
79aceca5 FB |
6646 | } |
6647 | ||
9e0b5cb1 AG |
6648 | /* Embedded.Processor Control */ |
6649 | ||
6650 | static void gen_msgclr(DisasContext *ctx) | |
6651 | { | |
6652 | #if defined(CONFIG_USER_ONLY) | |
6653 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6654 | #else | |
6655 | if (unlikely(ctx->mem_idx == 0)) { | |
6656 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6657 | return; | |
6658 | } | |
6659 | ||
e5f17ac6 | 6660 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9e0b5cb1 AG |
6661 | #endif |
6662 | } | |
6663 | ||
d5d11a39 AG |
6664 | static void gen_msgsnd(DisasContext *ctx) |
6665 | { | |
6666 | #if defined(CONFIG_USER_ONLY) | |
6667 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6668 | #else | |
6669 | if (unlikely(ctx->mem_idx == 0)) { | |
6670 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6671 | return; | |
6672 | } | |
6673 | ||
6674 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6675 | #endif | |
6676 | } | |
6677 | ||
a9d9eb8f JM |
6678 | /*** Altivec vector extension ***/ |
6679 | /* Altivec registers moves */ | |
a9d9eb8f | 6680 | |
636aa200 | 6681 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6682 | { |
e4704b3b | 6683 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6684 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6685 | return r; | |
6686 | } | |
6687 | ||
a9d9eb8f | 6688 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6689 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6690 | { \ |
fe1e5c53 | 6691 | TCGv EA; \ |
a9d9eb8f | 6692 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6693 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6694 | return; \ |
6695 | } \ | |
76db3ba4 | 6696 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6697 | EA = tcg_temp_new(); \ |
76db3ba4 | 6698 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6699 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
e22c357b DK |
6700 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \ |
6701 | 64-bit byteswap already. */ \ | |
76db3ba4 AJ |
6702 | if (ctx->le_mode) { \ |
6703 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6704 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6705 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6706 | } else { \ |
76db3ba4 | 6707 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6708 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6709 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6710 | } \ |
6711 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6712 | } |
6713 | ||
6714 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6715 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6716 | { \ |
fe1e5c53 | 6717 | TCGv EA; \ |
a9d9eb8f | 6718 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6719 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6720 | return; \ |
6721 | } \ | |
76db3ba4 | 6722 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6723 | EA = tcg_temp_new(); \ |
76db3ba4 | 6724 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6725 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
e22c357b DK |
6726 | /* We only need to swap high and low halves. gen_qemu_st64 does necessary \ |
6727 | 64-bit byteswap already. */ \ | |
76db3ba4 AJ |
6728 | if (ctx->le_mode) { \ |
6729 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6730 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6731 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6732 | } else { \ |
76db3ba4 | 6733 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6734 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6735 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6736 | } \ |
6737 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6738 | } |
6739 | ||
cbfb6ae9 | 6740 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef | 6741 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6742 | { \ |
6743 | TCGv EA; \ | |
6744 | TCGv_ptr rs; \ | |
6745 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6746 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6747 | return; \ | |
6748 | } \ | |
6749 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6750 | EA = tcg_temp_new(); \ | |
6751 | gen_addr_reg_index(ctx, EA); \ | |
6752 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6753 | gen_helper_lve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6754 | tcg_temp_free(EA); \ |
6755 | tcg_temp_free_ptr(rs); \ | |
6756 | } | |
6757 | ||
6758 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef | 6759 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6760 | { \ |
6761 | TCGv EA; \ | |
6762 | TCGv_ptr rs; \ | |
6763 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6764 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6765 | return; \ | |
6766 | } \ | |
6767 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6768 | EA = tcg_temp_new(); \ | |
6769 | gen_addr_reg_index(ctx, EA); \ | |
6770 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6771 | gen_helper_stve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6772 | tcg_temp_free(EA); \ |
6773 | tcg_temp_free_ptr(rs); \ | |
6774 | } | |
6775 | ||
fe1e5c53 | 6776 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6777 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6778 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6779 | |
cbfb6ae9 AJ |
6780 | GEN_VR_LVE(bx, 0x07, 0x00); |
6781 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6782 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6783 | ||
fe1e5c53 | 6784 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6785 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6786 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6787 | |
cbfb6ae9 AJ |
6788 | GEN_VR_STVE(bx, 0x07, 0x04); |
6789 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6790 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6791 | ||
99e300ef | 6792 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6793 | { |
6794 | TCGv_ptr rd; | |
6795 | TCGv EA; | |
6796 | if (unlikely(!ctx->altivec_enabled)) { | |
6797 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6798 | return; | |
6799 | } | |
6800 | EA = tcg_temp_new(); | |
6801 | gen_addr_reg_index(ctx, EA); | |
6802 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6803 | gen_helper_lvsl(rd, EA); | |
6804 | tcg_temp_free(EA); | |
6805 | tcg_temp_free_ptr(rd); | |
6806 | } | |
6807 | ||
99e300ef | 6808 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6809 | { |
6810 | TCGv_ptr rd; | |
6811 | TCGv EA; | |
6812 | if (unlikely(!ctx->altivec_enabled)) { | |
6813 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6814 | return; | |
6815 | } | |
6816 | EA = tcg_temp_new(); | |
6817 | gen_addr_reg_index(ctx, EA); | |
6818 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6819 | gen_helper_lvsr(rd, EA); | |
6820 | tcg_temp_free(EA); | |
6821 | tcg_temp_free_ptr(rd); | |
6822 | } | |
6823 | ||
99e300ef | 6824 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6825 | { |
6826 | TCGv_i32 t; | |
6827 | if (unlikely(!ctx->altivec_enabled)) { | |
6828 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6829 | return; | |
6830 | } | |
6831 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6832 | t = tcg_temp_new_i32(); | |
1328c2bf | 6833 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
785f451b | 6834 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
fce5ecb7 | 6835 | tcg_temp_free_i32(t); |
785f451b AJ |
6836 | } |
6837 | ||
99e300ef | 6838 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6839 | { |
6e87b7c7 | 6840 | TCGv_ptr p; |
785f451b AJ |
6841 | if (unlikely(!ctx->altivec_enabled)) { |
6842 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6843 | return; | |
6844 | } | |
6e87b7c7 | 6845 | p = gen_avr_ptr(rD(ctx->opcode)); |
d15f74fb | 6846 | gen_helper_mtvscr(cpu_env, p); |
6e87b7c7 | 6847 | tcg_temp_free_ptr(p); |
785f451b AJ |
6848 | } |
6849 | ||
7a9b96cf AJ |
6850 | /* Logical operations */ |
6851 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6852 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6853 | { \ |
6854 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6855 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6856 | return; \ | |
6857 | } \ | |
6858 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6859 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6860 | } | |
6861 | ||
6862 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6863 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6864 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6865 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6866 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
111c5f54 TM |
6867 | GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26); |
6868 | GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22); | |
6869 | GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21); | |
7a9b96cf | 6870 | |
8e27dd6f | 6871 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6872 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6873 | { \ |
6874 | TCGv_ptr ra, rb, rd; \ | |
6875 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6876 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6877 | return; \ | |
6878 | } \ | |
6879 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6880 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6881 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6882 | gen_helper_##name (rd, ra, rb); \ | |
6883 | tcg_temp_free_ptr(ra); \ | |
6884 | tcg_temp_free_ptr(rb); \ | |
6885 | tcg_temp_free_ptr(rd); \ | |
6886 | } | |
6887 | ||
d15f74fb BS |
6888 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
6889 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6890 | { \ | |
6891 | TCGv_ptr ra, rb, rd; \ | |
6892 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6893 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6894 | return; \ | |
6895 | } \ | |
6896 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6897 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6898 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
54cddd21 | 6899 | gen_helper_##name(cpu_env, rd, ra, rb); \ |
d15f74fb BS |
6900 | tcg_temp_free_ptr(ra); \ |
6901 | tcg_temp_free_ptr(rb); \ | |
6902 | tcg_temp_free_ptr(rd); \ | |
9b47bb49 TM |
6903 | } |
6904 | ||
6905 | #define GEN_VXFORM3(name, opc2, opc3) \ | |
6906 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6907 | { \ | |
6908 | TCGv_ptr ra, rb, rc, rd; \ | |
6909 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6910 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6911 | return; \ | |
6912 | } \ | |
6913 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6914 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6915 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6916 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6917 | gen_helper_##name(rd, ra, rb, rc); \ | |
6918 | tcg_temp_free_ptr(ra); \ | |
6919 | tcg_temp_free_ptr(rb); \ | |
6920 | tcg_temp_free_ptr(rc); \ | |
6921 | tcg_temp_free_ptr(rd); \ | |
d15f74fb BS |
6922 | } |
6923 | ||
5dffff5a TM |
6924 | /* |
6925 | * Support for Altivec instruction pairs that use bit 31 (Rc) as | |
6926 | * an opcode bit. In general, these pairs come from different | |
6927 | * versions of the ISA, so we must also support a pair of flags for | |
6928 | * each instruction. | |
6929 | */ | |
6930 | #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
6931 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
6932 | { \ | |
6933 | if ((Rc(ctx->opcode) == 0) && \ | |
6934 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
6935 | gen_##name0(ctx); \ | |
6936 | } else if ((Rc(ctx->opcode) == 1) && \ | |
6937 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
6938 | gen_##name1(ctx); \ | |
6939 | } else { \ | |
6940 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
6941 | } \ | |
6942 | } | |
6943 | ||
7872c51c AJ |
6944 | GEN_VXFORM(vaddubm, 0, 0); |
6945 | GEN_VXFORM(vadduhm, 0, 1); | |
6946 | GEN_VXFORM(vadduwm, 0, 2); | |
56eabc75 | 6947 | GEN_VXFORM(vaddudm, 0, 3); |
7872c51c AJ |
6948 | GEN_VXFORM(vsububm, 0, 16); |
6949 | GEN_VXFORM(vsubuhm, 0, 17); | |
6950 | GEN_VXFORM(vsubuwm, 0, 18); | |
56eabc75 | 6951 | GEN_VXFORM(vsubudm, 0, 19); |
e4039339 AJ |
6952 | GEN_VXFORM(vmaxub, 1, 0); |
6953 | GEN_VXFORM(vmaxuh, 1, 1); | |
6954 | GEN_VXFORM(vmaxuw, 1, 2); | |
8203e31b | 6955 | GEN_VXFORM(vmaxud, 1, 3); |
e4039339 AJ |
6956 | GEN_VXFORM(vmaxsb, 1, 4); |
6957 | GEN_VXFORM(vmaxsh, 1, 5); | |
6958 | GEN_VXFORM(vmaxsw, 1, 6); | |
8203e31b | 6959 | GEN_VXFORM(vmaxsd, 1, 7); |
e4039339 AJ |
6960 | GEN_VXFORM(vminub, 1, 8); |
6961 | GEN_VXFORM(vminuh, 1, 9); | |
6962 | GEN_VXFORM(vminuw, 1, 10); | |
8203e31b | 6963 | GEN_VXFORM(vminud, 1, 11); |
e4039339 AJ |
6964 | GEN_VXFORM(vminsb, 1, 12); |
6965 | GEN_VXFORM(vminsh, 1, 13); | |
6966 | GEN_VXFORM(vminsw, 1, 14); | |
8203e31b | 6967 | GEN_VXFORM(vminsd, 1, 15); |
fab3cbe9 AJ |
6968 | GEN_VXFORM(vavgub, 1, 16); |
6969 | GEN_VXFORM(vavguh, 1, 17); | |
6970 | GEN_VXFORM(vavguw, 1, 18); | |
6971 | GEN_VXFORM(vavgsb, 1, 20); | |
6972 | GEN_VXFORM(vavgsh, 1, 21); | |
6973 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6974 | GEN_VXFORM(vmrghb, 6, 0); |
6975 | GEN_VXFORM(vmrghh, 6, 1); | |
6976 | GEN_VXFORM(vmrghw, 6, 2); | |
6977 | GEN_VXFORM(vmrglb, 6, 4); | |
6978 | GEN_VXFORM(vmrglh, 6, 5); | |
6979 | GEN_VXFORM(vmrglw, 6, 6); | |
e0ffe77f TM |
6980 | |
6981 | static void gen_vmrgew(DisasContext *ctx) | |
6982 | { | |
6983 | TCGv_i64 tmp; | |
6984 | int VT, VA, VB; | |
6985 | if (unlikely(!ctx->altivec_enabled)) { | |
6986 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6987 | return; | |
6988 | } | |
6989 | VT = rD(ctx->opcode); | |
6990 | VA = rA(ctx->opcode); | |
6991 | VB = rB(ctx->opcode); | |
6992 | tmp = tcg_temp_new_i64(); | |
6993 | tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32); | |
6994 | tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32); | |
6995 | tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32); | |
6996 | tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32); | |
6997 | tcg_temp_free_i64(tmp); | |
6998 | } | |
6999 | ||
7000 | static void gen_vmrgow(DisasContext *ctx) | |
7001 | { | |
7002 | int VT, VA, VB; | |
7003 | if (unlikely(!ctx->altivec_enabled)) { | |
7004 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7005 | return; | |
7006 | } | |
7007 | VT = rD(ctx->opcode); | |
7008 | VA = rA(ctx->opcode); | |
7009 | VB = rB(ctx->opcode); | |
7010 | ||
7011 | tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32); | |
7012 | tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32); | |
7013 | } | |
7014 | ||
2c277908 AJ |
7015 | GEN_VXFORM(vmuloub, 4, 0); |
7016 | GEN_VXFORM(vmulouh, 4, 1); | |
63be0936 | 7017 | GEN_VXFORM(vmulouw, 4, 2); |
953f0f58 TM |
7018 | GEN_VXFORM(vmuluwm, 4, 2); |
7019 | GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE, | |
7020 | vmuluwm, PPC_NONE, PPC2_ALTIVEC_207) | |
2c277908 AJ |
7021 | GEN_VXFORM(vmulosb, 4, 4); |
7022 | GEN_VXFORM(vmulosh, 4, 5); | |
63be0936 | 7023 | GEN_VXFORM(vmulosw, 4, 6); |
2c277908 AJ |
7024 | GEN_VXFORM(vmuleub, 4, 8); |
7025 | GEN_VXFORM(vmuleuh, 4, 9); | |
63be0936 | 7026 | GEN_VXFORM(vmuleuw, 4, 10); |
2c277908 AJ |
7027 | GEN_VXFORM(vmulesb, 4, 12); |
7028 | GEN_VXFORM(vmulesh, 4, 13); | |
63be0936 | 7029 | GEN_VXFORM(vmulesw, 4, 14); |
d79f0809 AJ |
7030 | GEN_VXFORM(vslb, 2, 4); |
7031 | GEN_VXFORM(vslh, 2, 5); | |
7032 | GEN_VXFORM(vslw, 2, 6); | |
2fdf78e6 | 7033 | GEN_VXFORM(vsld, 2, 23); |
07ef34c3 AJ |
7034 | GEN_VXFORM(vsrb, 2, 8); |
7035 | GEN_VXFORM(vsrh, 2, 9); | |
7036 | GEN_VXFORM(vsrw, 2, 10); | |
2fdf78e6 | 7037 | GEN_VXFORM(vsrd, 2, 27); |
07ef34c3 AJ |
7038 | GEN_VXFORM(vsrab, 2, 12); |
7039 | GEN_VXFORM(vsrah, 2, 13); | |
7040 | GEN_VXFORM(vsraw, 2, 14); | |
2fdf78e6 | 7041 | GEN_VXFORM(vsrad, 2, 15); |
7b239bec AJ |
7042 | GEN_VXFORM(vslo, 6, 16); |
7043 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
7044 | GEN_VXFORM(vaddcuw, 0, 6); |
7045 | GEN_VXFORM(vsubcuw, 0, 22); | |
d15f74fb BS |
7046 | GEN_VXFORM_ENV(vaddubs, 0, 8); |
7047 | GEN_VXFORM_ENV(vadduhs, 0, 9); | |
7048 | GEN_VXFORM_ENV(vadduws, 0, 10); | |
7049 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
7050 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
7051 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
7052 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
7053 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
7054 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
7055 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
7056 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
7057 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
b41da4eb TM |
7058 | GEN_VXFORM(vadduqm, 0, 4); |
7059 | GEN_VXFORM(vaddcuq, 0, 5); | |
7060 | GEN_VXFORM3(vaddeuqm, 30, 0); | |
7061 | GEN_VXFORM3(vaddecuq, 30, 0); | |
7062 | GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7063 | vaddecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
7064 | GEN_VXFORM(vsubuqm, 0, 20); | |
7065 | GEN_VXFORM(vsubcuq, 0, 21); | |
7066 | GEN_VXFORM3(vsubeuqm, 31, 0); | |
7067 | GEN_VXFORM3(vsubecuq, 31, 0); | |
7068 | GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7069 | vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
5e1d0985 AJ |
7070 | GEN_VXFORM(vrlb, 2, 0); |
7071 | GEN_VXFORM(vrlh, 2, 1); | |
7072 | GEN_VXFORM(vrlw, 2, 2); | |
2fdf78e6 | 7073 | GEN_VXFORM(vrld, 2, 3); |
d9430add AJ |
7074 | GEN_VXFORM(vsl, 2, 7); |
7075 | GEN_VXFORM(vsr, 2, 11); | |
d15f74fb BS |
7076 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
7077 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
024215b2 | 7078 | GEN_VXFORM_ENV(vpkudum, 7, 17); |
d15f74fb BS |
7079 | GEN_VXFORM_ENV(vpkuhus, 7, 2); |
7080 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
024215b2 | 7081 | GEN_VXFORM_ENV(vpkudus, 7, 19); |
d15f74fb BS |
7082 | GEN_VXFORM_ENV(vpkshus, 7, 4); |
7083 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
024215b2 | 7084 | GEN_VXFORM_ENV(vpksdus, 7, 21); |
d15f74fb BS |
7085 | GEN_VXFORM_ENV(vpkshss, 7, 6); |
7086 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
024215b2 | 7087 | GEN_VXFORM_ENV(vpksdss, 7, 23); |
1dd9ffb9 | 7088 | GEN_VXFORM(vpkpx, 7, 12); |
d15f74fb BS |
7089 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
7090 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
7091 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
7092 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
7093 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
7094 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
7095 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
7096 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
7097 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
fab3cbe9 | 7098 | |
0cbcd906 | 7099 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 7100 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
7101 | { \ |
7102 | TCGv_ptr ra, rb, rd; \ | |
7103 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7104 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7105 | return; \ | |
7106 | } \ | |
7107 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7108 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7109 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
d15f74fb | 7110 | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
0cbcd906 AJ |
7111 | tcg_temp_free_ptr(ra); \ |
7112 | tcg_temp_free_ptr(rb); \ | |
7113 | tcg_temp_free_ptr(rd); \ | |
7114 | } | |
7115 | ||
7116 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
7117 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
7118 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
7119 | ||
a737d3eb TM |
7120 | /* |
7121 | * Support for Altivec instructions that use bit 31 (Rc) as an opcode | |
7122 | * bit but also use bit 21 as an actual Rc bit. In general, thse pairs | |
7123 | * come from different versions of the ISA, so we must also support a | |
7124 | * pair of flags for each instruction. | |
7125 | */ | |
7126 | #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
7127 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
7128 | { \ | |
7129 | if ((Rc(ctx->opcode) == 0) && \ | |
7130 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
7131 | if (Rc21(ctx->opcode) == 0) { \ | |
7132 | gen_##name0(ctx); \ | |
7133 | } else { \ | |
7134 | gen_##name0##_(ctx); \ | |
7135 | } \ | |
7136 | } else if ((Rc(ctx->opcode) == 1) && \ | |
7137 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
7138 | if (Rc21(ctx->opcode) == 0) { \ | |
7139 | gen_##name1(ctx); \ | |
7140 | } else { \ | |
7141 | gen_##name1##_(ctx); \ | |
7142 | } \ | |
7143 | } else { \ | |
7144 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
7145 | } \ | |
7146 | } | |
7147 | ||
1add6e23 AJ |
7148 | GEN_VXRFORM(vcmpequb, 3, 0) |
7149 | GEN_VXRFORM(vcmpequh, 3, 1) | |
7150 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6f3dab41 | 7151 | GEN_VXRFORM(vcmpequd, 3, 3) |
1add6e23 AJ |
7152 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
7153 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
7154 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6f3dab41 | 7155 | GEN_VXRFORM(vcmpgtsd, 3, 15) |
1add6e23 AJ |
7156 | GEN_VXRFORM(vcmpgtub, 3, 8) |
7157 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
7158 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
6f3dab41 | 7159 | GEN_VXRFORM(vcmpgtud, 3, 11) |
819ca121 AJ |
7160 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
7161 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
7162 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
7163 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 7164 | |
6f3dab41 TM |
7165 | GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \ |
7166 | vcmpequd, PPC_NONE, PPC2_ALTIVEC_207) | |
7167 | GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \ | |
7168 | vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207) | |
7169 | GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \ | |
7170 | vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207) | |
7171 | ||
c026766b | 7172 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 7173 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
7174 | { \ |
7175 | TCGv_ptr rd; \ | |
7176 | TCGv_i32 simm; \ | |
7177 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7178 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7179 | return; \ | |
7180 | } \ | |
7181 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
7182 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7183 | gen_helper_##name (rd, simm); \ | |
7184 | tcg_temp_free_i32(simm); \ | |
7185 | tcg_temp_free_ptr(rd); \ | |
7186 | } | |
7187 | ||
7188 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
7189 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
7190 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
7191 | ||
de5f2484 | 7192 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 7193 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
7194 | { \ |
7195 | TCGv_ptr rb, rd; \ | |
7196 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7197 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7198 | return; \ | |
7199 | } \ | |
7200 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7201 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7202 | gen_helper_##name (rd, rb); \ | |
7203 | tcg_temp_free_ptr(rb); \ | |
7204 | tcg_temp_free_ptr(rd); \ | |
7205 | } | |
7206 | ||
d15f74fb BS |
7207 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ |
7208 | static void glue(gen_, name)(DisasContext *ctx) \ | |
7209 | { \ | |
7210 | TCGv_ptr rb, rd; \ | |
7211 | \ | |
7212 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7213 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7214 | return; \ | |
7215 | } \ | |
7216 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7217 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7218 | gen_helper_##name(cpu_env, rd, rb); \ | |
7219 | tcg_temp_free_ptr(rb); \ | |
7220 | tcg_temp_free_ptr(rd); \ | |
7221 | } | |
7222 | ||
6cf1c6e5 AJ |
7223 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
7224 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
4430e076 | 7225 | GEN_VXFORM_NOA(vupkhsw, 7, 25); |
6cf1c6e5 AJ |
7226 | GEN_VXFORM_NOA(vupklsb, 7, 10); |
7227 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
4430e076 | 7228 | GEN_VXFORM_NOA(vupklsw, 7, 27); |
79f85c3a AJ |
7229 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
7230 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
d15f74fb BS |
7231 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
7232 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
7233 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
7234 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
7235 | GEN_VXFORM_NOA_ENV(vrfim, 5, 8); | |
7236 | GEN_VXFORM_NOA_ENV(vrfin, 5, 9); | |
7237 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
7238 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 11); | |
79f85c3a | 7239 | |
21d21583 | 7240 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 7241 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
7242 | { \ |
7243 | TCGv_ptr rd; \ | |
7244 | TCGv_i32 simm; \ | |
7245 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7246 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7247 | return; \ | |
7248 | } \ | |
7249 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
7250 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7251 | gen_helper_##name (rd, simm); \ | |
7252 | tcg_temp_free_i32(simm); \ | |
7253 | tcg_temp_free_ptr(rd); \ | |
7254 | } | |
7255 | ||
27a4edb3 | 7256 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 7257 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
7258 | { \ |
7259 | TCGv_ptr rb, rd; \ | |
7260 | TCGv_i32 uimm; \ | |
7261 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7262 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7263 | return; \ | |
7264 | } \ | |
7265 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
7266 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7267 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7268 | gen_helper_##name (rd, rb, uimm); \ | |
7269 | tcg_temp_free_i32(uimm); \ | |
7270 | tcg_temp_free_ptr(rb); \ | |
7271 | tcg_temp_free_ptr(rd); \ | |
7272 | } | |
7273 | ||
d15f74fb BS |
7274 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
7275 | static void glue(gen_, name)(DisasContext *ctx) \ | |
7276 | { \ | |
7277 | TCGv_ptr rb, rd; \ | |
7278 | TCGv_i32 uimm; \ | |
7279 | \ | |
7280 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7281 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7282 | return; \ | |
7283 | } \ | |
7284 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
7285 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7286 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7287 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
7288 | tcg_temp_free_i32(uimm); \ | |
7289 | tcg_temp_free_ptr(rb); \ | |
7290 | tcg_temp_free_ptr(rd); \ | |
7291 | } | |
7292 | ||
e4e6bee7 AJ |
7293 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
7294 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
7295 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
d15f74fb BS |
7296 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
7297 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
7298 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
7299 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
e4e6bee7 | 7300 | |
99e300ef | 7301 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
7302 | { |
7303 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 7304 | TCGv_i32 sh; |
cd633b10 AJ |
7305 | if (unlikely(!ctx->altivec_enabled)) { |
7306 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7307 | return; | |
7308 | } | |
7309 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
7310 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
7311 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
7312 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
7313 | gen_helper_vsldoi (rd, ra, rb, sh); | |
7314 | tcg_temp_free_ptr(ra); | |
7315 | tcg_temp_free_ptr(rb); | |
7316 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 7317 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
7318 | } |
7319 | ||
707cec33 | 7320 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
d15f74fb | 7321 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
7322 | { \ |
7323 | TCGv_ptr ra, rb, rc, rd; \ | |
7324 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7325 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7326 | return; \ | |
7327 | } \ | |
7328 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7329 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7330 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
7331 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7332 | if (Rc(ctx->opcode)) { \ | |
d15f74fb | 7333 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
707cec33 | 7334 | } else { \ |
d15f74fb | 7335 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
707cec33 AJ |
7336 | } \ |
7337 | tcg_temp_free_ptr(ra); \ | |
7338 | tcg_temp_free_ptr(rb); \ | |
7339 | tcg_temp_free_ptr(rc); \ | |
7340 | tcg_temp_free_ptr(rd); \ | |
7341 | } | |
7342 | ||
b161ae27 AJ |
7343 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
7344 | ||
99e300ef | 7345 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
7346 | { |
7347 | TCGv_ptr ra, rb, rc, rd; | |
7348 | if (unlikely(!ctx->altivec_enabled)) { | |
7349 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7350 | return; | |
7351 | } | |
7352 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
7353 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
7354 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
7355 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
7356 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
7357 | tcg_temp_free_ptr(ra); | |
7358 | tcg_temp_free_ptr(rb); | |
7359 | tcg_temp_free_ptr(rc); | |
7360 | tcg_temp_free_ptr(rd); | |
7361 | } | |
7362 | ||
b04ae981 | 7363 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 7364 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 7365 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 7366 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 7367 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 7368 | |
f293f04a TM |
7369 | GEN_VXFORM_NOA(vclzb, 1, 28) |
7370 | GEN_VXFORM_NOA(vclzh, 1, 29) | |
7371 | GEN_VXFORM_NOA(vclzw, 1, 30) | |
7372 | GEN_VXFORM_NOA(vclzd, 1, 31) | |
e13500b3 TM |
7373 | GEN_VXFORM_NOA(vpopcntb, 1, 28) |
7374 | GEN_VXFORM_NOA(vpopcnth, 1, 29) | |
7375 | GEN_VXFORM_NOA(vpopcntw, 1, 30) | |
7376 | GEN_VXFORM_NOA(vpopcntd, 1, 31) | |
7377 | GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7378 | vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) | |
7379 | GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7380 | vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) | |
7381 | GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7382 | vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) | |
7383 | GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7384 | vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) | |
4d82038e | 7385 | GEN_VXFORM(vbpermq, 6, 21); |
f1064f61 | 7386 | GEN_VXFORM_NOA(vgbbd, 6, 20); |
b8476fc7 TM |
7387 | GEN_VXFORM(vpmsumb, 4, 16) |
7388 | GEN_VXFORM(vpmsumh, 4, 17) | |
7389 | GEN_VXFORM(vpmsumw, 4, 18) | |
7390 | GEN_VXFORM(vpmsumd, 4, 19) | |
e13500b3 | 7391 | |
e8f7b27b TM |
7392 | #define GEN_BCD(op) \ |
7393 | static void gen_##op(DisasContext *ctx) \ | |
7394 | { \ | |
7395 | TCGv_ptr ra, rb, rd; \ | |
7396 | TCGv_i32 ps; \ | |
7397 | \ | |
7398 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7399 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7400 | return; \ | |
7401 | } \ | |
7402 | \ | |
7403 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7404 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7405 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7406 | \ | |
7407 | ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ | |
7408 | \ | |
7409 | gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ | |
7410 | \ | |
7411 | tcg_temp_free_ptr(ra); \ | |
7412 | tcg_temp_free_ptr(rb); \ | |
7413 | tcg_temp_free_ptr(rd); \ | |
7414 | tcg_temp_free_i32(ps); \ | |
7415 | } | |
7416 | ||
7417 | GEN_BCD(bcdadd) | |
7418 | GEN_BCD(bcdsub) | |
7419 | ||
7420 | GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ | |
7421 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
7422 | GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \ | |
7423 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
7424 | GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ | |
7425 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
7426 | GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \ | |
7427 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
7428 | ||
557d52fa TM |
7429 | static void gen_vsbox(DisasContext *ctx) |
7430 | { | |
7431 | TCGv_ptr ra, rd; | |
7432 | if (unlikely(!ctx->altivec_enabled)) { | |
7433 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7434 | return; | |
7435 | } | |
7436 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
7437 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
7438 | gen_helper_vsbox(rd, ra); | |
7439 | tcg_temp_free_ptr(ra); | |
7440 | tcg_temp_free_ptr(rd); | |
7441 | } | |
7442 | ||
7443 | GEN_VXFORM(vcipher, 4, 20) | |
7444 | GEN_VXFORM(vcipherlast, 4, 20) | |
7445 | GEN_VXFORM(vncipher, 4, 21) | |
7446 | GEN_VXFORM(vncipherlast, 4, 21) | |
7447 | ||
7448 | GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207, | |
7449 | vcipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
7450 | GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207, | |
7451 | vncipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
7452 | ||
57354f8f TM |
7453 | #define VSHASIGMA(op) \ |
7454 | static void gen_##op(DisasContext *ctx) \ | |
7455 | { \ | |
7456 | TCGv_ptr ra, rd; \ | |
7457 | TCGv_i32 st_six; \ | |
7458 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7459 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7460 | return; \ | |
7461 | } \ | |
7462 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7463 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7464 | st_six = tcg_const_i32(rB(ctx->opcode)); \ | |
7465 | gen_helper_##op(rd, ra, st_six); \ | |
7466 | tcg_temp_free_ptr(ra); \ | |
7467 | tcg_temp_free_ptr(rd); \ | |
7468 | tcg_temp_free_i32(st_six); \ | |
7469 | } | |
7470 | ||
7471 | VSHASIGMA(vshasigmaw) | |
7472 | VSHASIGMA(vshasigmad) | |
7473 | ||
ac174549 TM |
7474 | GEN_VXFORM3(vpermxor, 22, 0xFF) |
7475 | GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, | |
7476 | vpermxor, PPC_NONE, PPC2_ALTIVEC_207) | |
7477 | ||
472b24ce TM |
7478 | /*** VSX extension ***/ |
7479 | ||
7480 | static inline TCGv_i64 cpu_vsrh(int n) | |
7481 | { | |
7482 | if (n < 32) { | |
7483 | return cpu_fpr[n]; | |
7484 | } else { | |
7485 | return cpu_avrh[n-32]; | |
7486 | } | |
7487 | } | |
7488 | ||
7489 | static inline TCGv_i64 cpu_vsrl(int n) | |
7490 | { | |
7491 | if (n < 32) { | |
7492 | return cpu_vsr[n]; | |
7493 | } else { | |
7494 | return cpu_avrl[n-32]; | |
7495 | } | |
7496 | } | |
7497 | ||
e072fe79 TM |
7498 | #define VSX_LOAD_SCALAR(name, operation) \ |
7499 | static void gen_##name(DisasContext *ctx) \ | |
7500 | { \ | |
7501 | TCGv EA; \ | |
7502 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7503 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7504 | return; \ | |
7505 | } \ | |
7506 | gen_set_access_type(ctx, ACCESS_INT); \ | |
7507 | EA = tcg_temp_new(); \ | |
7508 | gen_addr_reg_index(ctx, EA); \ | |
7509 | gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \ | |
7510 | /* NOTE: cpu_vsrl is undefined */ \ | |
7511 | tcg_temp_free(EA); \ | |
7512 | } | |
7513 | ||
7514 | VSX_LOAD_SCALAR(lxsdx, ld64) | |
cac7f0ba TM |
7515 | VSX_LOAD_SCALAR(lxsiwax, ld32s_i64) |
7516 | VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64) | |
7517 | VSX_LOAD_SCALAR(lxsspx, ld32fs) | |
fa1832d7 | 7518 | |
304af367 TM |
7519 | static void gen_lxvd2x(DisasContext *ctx) |
7520 | { | |
7521 | TCGv EA; | |
7522 | if (unlikely(!ctx->vsx_enabled)) { | |
7523 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7524 | return; | |
7525 | } | |
7526 | gen_set_access_type(ctx, ACCESS_INT); | |
7527 | EA = tcg_temp_new(); | |
7528 | gen_addr_reg_index(ctx, EA); | |
7529 | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); | |
7530 | tcg_gen_addi_tl(EA, EA, 8); | |
7531 | gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA); | |
7532 | tcg_temp_free(EA); | |
7533 | } | |
7534 | ||
ca03b467 TM |
7535 | static void gen_lxvdsx(DisasContext *ctx) |
7536 | { | |
7537 | TCGv EA; | |
7538 | if (unlikely(!ctx->vsx_enabled)) { | |
7539 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7540 | return; | |
7541 | } | |
7542 | gen_set_access_type(ctx, ACCESS_INT); | |
7543 | EA = tcg_temp_new(); | |
7544 | gen_addr_reg_index(ctx, EA); | |
7545 | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); | |
f976b09e | 7546 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); |
ca03b467 TM |
7547 | tcg_temp_free(EA); |
7548 | } | |
7549 | ||
897e61d1 TM |
7550 | static void gen_lxvw4x(DisasContext *ctx) |
7551 | { | |
f976b09e AG |
7552 | TCGv EA; |
7553 | TCGv_i64 tmp; | |
897e61d1 TM |
7554 | TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); |
7555 | TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); | |
7556 | if (unlikely(!ctx->vsx_enabled)) { | |
7557 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7558 | return; | |
7559 | } | |
7560 | gen_set_access_type(ctx, ACCESS_INT); | |
7561 | EA = tcg_temp_new(); | |
f976b09e AG |
7562 | tmp = tcg_temp_new_i64(); |
7563 | ||
897e61d1 | 7564 | gen_addr_reg_index(ctx, EA); |
f976b09e | 7565 | gen_qemu_ld32u_i64(ctx, tmp, EA); |
897e61d1 | 7566 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7567 | gen_qemu_ld32u_i64(ctx, xth, EA); |
897e61d1 TM |
7568 | tcg_gen_deposit_i64(xth, xth, tmp, 32, 32); |
7569 | ||
7570 | tcg_gen_addi_tl(EA, EA, 4); | |
f976b09e | 7571 | gen_qemu_ld32u_i64(ctx, tmp, EA); |
897e61d1 | 7572 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7573 | gen_qemu_ld32u_i64(ctx, xtl, EA); |
897e61d1 TM |
7574 | tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32); |
7575 | ||
7576 | tcg_temp_free(EA); | |
f976b09e | 7577 | tcg_temp_free_i64(tmp); |
897e61d1 TM |
7578 | } |
7579 | ||
f026da78 TM |
7580 | #define VSX_STORE_SCALAR(name, operation) \ |
7581 | static void gen_##name(DisasContext *ctx) \ | |
7582 | { \ | |
7583 | TCGv EA; \ | |
7584 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7585 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7586 | return; \ | |
7587 | } \ | |
7588 | gen_set_access_type(ctx, ACCESS_INT); \ | |
7589 | EA = tcg_temp_new(); \ | |
7590 | gen_addr_reg_index(ctx, EA); \ | |
7591 | gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \ | |
7592 | tcg_temp_free(EA); \ | |
9231ba9e TM |
7593 | } |
7594 | ||
f026da78 | 7595 | VSX_STORE_SCALAR(stxsdx, st64) |
e16a626b TM |
7596 | VSX_STORE_SCALAR(stxsiwx, st32_i64) |
7597 | VSX_STORE_SCALAR(stxsspx, st32fs) | |
f026da78 | 7598 | |
fbed2478 TM |
7599 | static void gen_stxvd2x(DisasContext *ctx) |
7600 | { | |
7601 | TCGv EA; | |
7602 | if (unlikely(!ctx->vsx_enabled)) { | |
7603 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7604 | return; | |
7605 | } | |
7606 | gen_set_access_type(ctx, ACCESS_INT); | |
7607 | EA = tcg_temp_new(); | |
7608 | gen_addr_reg_index(ctx, EA); | |
7609 | gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); | |
7610 | tcg_gen_addi_tl(EA, EA, 8); | |
7611 | gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); | |
7612 | tcg_temp_free(EA); | |
7613 | } | |
7614 | ||
86e61ce3 TM |
7615 | static void gen_stxvw4x(DisasContext *ctx) |
7616 | { | |
f976b09e AG |
7617 | TCGv_i64 tmp; |
7618 | TCGv EA; | |
86e61ce3 TM |
7619 | if (unlikely(!ctx->vsx_enabled)) { |
7620 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7621 | return; | |
7622 | } | |
7623 | gen_set_access_type(ctx, ACCESS_INT); | |
7624 | EA = tcg_temp_new(); | |
7625 | gen_addr_reg_index(ctx, EA); | |
f976b09e | 7626 | tmp = tcg_temp_new_i64(); |
86e61ce3 TM |
7627 | |
7628 | tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32); | |
f976b09e | 7629 | gen_qemu_st32_i64(ctx, tmp, EA); |
86e61ce3 | 7630 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7631 | gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); |
86e61ce3 TM |
7632 | |
7633 | tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32); | |
7634 | tcg_gen_addi_tl(EA, EA, 4); | |
f976b09e | 7635 | gen_qemu_st32_i64(ctx, tmp, EA); |
86e61ce3 | 7636 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7637 | gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); |
86e61ce3 TM |
7638 | |
7639 | tcg_temp_free(EA); | |
f976b09e | 7640 | tcg_temp_free_i64(tmp); |
86e61ce3 TM |
7641 | } |
7642 | ||
f5c0f7f9 TM |
7643 | #define MV_VSRW(name, tcgop1, tcgop2, target, source) \ |
7644 | static void gen_##name(DisasContext *ctx) \ | |
7645 | { \ | |
7646 | if (xS(ctx->opcode) < 32) { \ | |
7647 | if (unlikely(!ctx->fpu_enabled)) { \ | |
7648 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
7649 | return; \ | |
7650 | } \ | |
7651 | } else { \ | |
7652 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7653 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7654 | return; \ | |
7655 | } \ | |
7656 | } \ | |
7657 | TCGv_i64 tmp = tcg_temp_new_i64(); \ | |
7658 | tcg_gen_##tcgop1(tmp, source); \ | |
7659 | tcg_gen_##tcgop2(target, tmp); \ | |
7660 | tcg_temp_free_i64(tmp); \ | |
7661 | } | |
7662 | ||
7663 | ||
7664 | MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \ | |
7665 | cpu_vsrh(xS(ctx->opcode))) | |
7666 | MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \ | |
7667 | cpu_gpr[rA(ctx->opcode)]) | |
7668 | MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \ | |
7669 | cpu_gpr[rA(ctx->opcode)]) | |
7670 | ||
7671 | #if defined(TARGET_PPC64) | |
7672 | #define MV_VSRD(name, target, source) \ | |
7673 | static void gen_##name(DisasContext *ctx) \ | |
7674 | { \ | |
7675 | if (xS(ctx->opcode) < 32) { \ | |
7676 | if (unlikely(!ctx->fpu_enabled)) { \ | |
7677 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
7678 | return; \ | |
7679 | } \ | |
7680 | } else { \ | |
7681 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7682 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7683 | return; \ | |
7684 | } \ | |
7685 | } \ | |
7686 | tcg_gen_mov_i64(target, source); \ | |
7687 | } | |
7688 | ||
7689 | MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode))) | |
7690 | MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]) | |
7691 | ||
7692 | #endif | |
7693 | ||
cd73f2c9 TM |
7694 | static void gen_xxpermdi(DisasContext *ctx) |
7695 | { | |
7696 | if (unlikely(!ctx->vsx_enabled)) { | |
7697 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7698 | return; | |
7699 | } | |
7700 | ||
f5bc1bfa TM |
7701 | if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) || |
7702 | (xT(ctx->opcode) == xB(ctx->opcode)))) { | |
7703 | TCGv_i64 xh, xl; | |
7704 | ||
7705 | xh = tcg_temp_new_i64(); | |
7706 | xl = tcg_temp_new_i64(); | |
7707 | ||
7708 | if ((DM(ctx->opcode) & 2) == 0) { | |
7709 | tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode))); | |
7710 | } else { | |
7711 | tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode))); | |
7712 | } | |
7713 | if ((DM(ctx->opcode) & 1) == 0) { | |
7714 | tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode))); | |
7715 | } else { | |
7716 | tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode))); | |
7717 | } | |
7718 | ||
7719 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh); | |
7720 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl); | |
7721 | ||
7722 | tcg_temp_free_i64(xh); | |
7723 | tcg_temp_free_i64(xl); | |
cd73f2c9 | 7724 | } else { |
f5bc1bfa TM |
7725 | if ((DM(ctx->opcode) & 2) == 0) { |
7726 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode))); | |
7727 | } else { | |
7728 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode))); | |
7729 | } | |
7730 | if ((DM(ctx->opcode) & 1) == 0) { | |
7731 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode))); | |
7732 | } else { | |
7733 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode))); | |
7734 | } | |
cd73f2c9 TM |
7735 | } |
7736 | } | |
7737 | ||
df020ce0 TM |
7738 | #define OP_ABS 1 |
7739 | #define OP_NABS 2 | |
7740 | #define OP_NEG 3 | |
7741 | #define OP_CPSGN 4 | |
e5d7d2b0 PM |
7742 | #define SGN_MASK_DP 0x8000000000000000ull |
7743 | #define SGN_MASK_SP 0x8000000080000000ull | |
df020ce0 TM |
7744 | |
7745 | #define VSX_SCALAR_MOVE(name, op, sgn_mask) \ | |
7746 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7747 | { \ | |
7748 | TCGv_i64 xb, sgm; \ | |
7749 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7750 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7751 | return; \ | |
7752 | } \ | |
f976b09e AG |
7753 | xb = tcg_temp_new_i64(); \ |
7754 | sgm = tcg_temp_new_i64(); \ | |
df020ce0 TM |
7755 | tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \ |
7756 | tcg_gen_movi_i64(sgm, sgn_mask); \ | |
7757 | switch (op) { \ | |
7758 | case OP_ABS: { \ | |
7759 | tcg_gen_andc_i64(xb, xb, sgm); \ | |
7760 | break; \ | |
7761 | } \ | |
7762 | case OP_NABS: { \ | |
7763 | tcg_gen_or_i64(xb, xb, sgm); \ | |
7764 | break; \ | |
7765 | } \ | |
7766 | case OP_NEG: { \ | |
7767 | tcg_gen_xor_i64(xb, xb, sgm); \ | |
7768 | break; \ | |
7769 | } \ | |
7770 | case OP_CPSGN: { \ | |
f976b09e | 7771 | TCGv_i64 xa = tcg_temp_new_i64(); \ |
df020ce0 TM |
7772 | tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \ |
7773 | tcg_gen_and_i64(xa, xa, sgm); \ | |
7774 | tcg_gen_andc_i64(xb, xb, sgm); \ | |
7775 | tcg_gen_or_i64(xb, xb, xa); \ | |
f976b09e | 7776 | tcg_temp_free_i64(xa); \ |
df020ce0 TM |
7777 | break; \ |
7778 | } \ | |
7779 | } \ | |
7780 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \ | |
f976b09e AG |
7781 | tcg_temp_free_i64(xb); \ |
7782 | tcg_temp_free_i64(sgm); \ | |
df020ce0 TM |
7783 | } |
7784 | ||
7785 | VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP) | |
7786 | VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP) | |
7787 | VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP) | |
7788 | VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP) | |
7789 | ||
be574920 TM |
7790 | #define VSX_VECTOR_MOVE(name, op, sgn_mask) \ |
7791 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7792 | { \ | |
7793 | TCGv_i64 xbh, xbl, sgm; \ | |
7794 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7795 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7796 | return; \ | |
7797 | } \ | |
f976b09e AG |
7798 | xbh = tcg_temp_new_i64(); \ |
7799 | xbl = tcg_temp_new_i64(); \ | |
7800 | sgm = tcg_temp_new_i64(); \ | |
be574920 TM |
7801 | tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \ |
7802 | tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \ | |
7803 | tcg_gen_movi_i64(sgm, sgn_mask); \ | |
7804 | switch (op) { \ | |
7805 | case OP_ABS: { \ | |
7806 | tcg_gen_andc_i64(xbh, xbh, sgm); \ | |
7807 | tcg_gen_andc_i64(xbl, xbl, sgm); \ | |
7808 | break; \ | |
7809 | } \ | |
7810 | case OP_NABS: { \ | |
7811 | tcg_gen_or_i64(xbh, xbh, sgm); \ | |
7812 | tcg_gen_or_i64(xbl, xbl, sgm); \ | |
7813 | break; \ | |
7814 | } \ | |
7815 | case OP_NEG: { \ | |
7816 | tcg_gen_xor_i64(xbh, xbh, sgm); \ | |
7817 | tcg_gen_xor_i64(xbl, xbl, sgm); \ | |
7818 | break; \ | |
7819 | } \ | |
7820 | case OP_CPSGN: { \ | |
f976b09e AG |
7821 | TCGv_i64 xah = tcg_temp_new_i64(); \ |
7822 | TCGv_i64 xal = tcg_temp_new_i64(); \ | |
be574920 TM |
7823 | tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \ |
7824 | tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \ | |
7825 | tcg_gen_and_i64(xah, xah, sgm); \ | |
7826 | tcg_gen_and_i64(xal, xal, sgm); \ | |
7827 | tcg_gen_andc_i64(xbh, xbh, sgm); \ | |
7828 | tcg_gen_andc_i64(xbl, xbl, sgm); \ | |
7829 | tcg_gen_or_i64(xbh, xbh, xah); \ | |
7830 | tcg_gen_or_i64(xbl, xbl, xal); \ | |
f976b09e AG |
7831 | tcg_temp_free_i64(xah); \ |
7832 | tcg_temp_free_i64(xal); \ | |
be574920 TM |
7833 | break; \ |
7834 | } \ | |
7835 | } \ | |
7836 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \ | |
7837 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \ | |
f976b09e AG |
7838 | tcg_temp_free_i64(xbh); \ |
7839 | tcg_temp_free_i64(xbl); \ | |
7840 | tcg_temp_free_i64(sgm); \ | |
be574920 TM |
7841 | } |
7842 | ||
7843 | VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP) | |
7844 | VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP) | |
7845 | VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP) | |
7846 | VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP) | |
7847 | VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP) | |
7848 | VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP) | |
7849 | VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP) | |
7850 | VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP) | |
7851 | ||
3c3cbbdc TM |
7852 | #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \ |
7853 | static void gen_##name(DisasContext * ctx) \ | |
7854 | { \ | |
7855 | TCGv_i32 opc; \ | |
7856 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7857 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7858 | return; \ | |
7859 | } \ | |
7860 | /* NIP cannot be restored if the memory exception comes from an helper */ \ | |
7861 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7862 | opc = tcg_const_i32(ctx->opcode); \ | |
7863 | gen_helper_##name(cpu_env, opc); \ | |
7864 | tcg_temp_free_i32(opc); \ | |
7865 | } | |
be574920 | 7866 | |
3d1140bf TM |
7867 | #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ |
7868 | static void gen_##name(DisasContext * ctx) \ | |
7869 | { \ | |
7870 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7871 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7872 | return; \ | |
7873 | } \ | |
7874 | /* NIP cannot be restored if the exception comes */ \ | |
7875 | /* from a helper. */ \ | |
7876 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7877 | \ | |
7878 | gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \ | |
7879 | cpu_vsrh(xB(ctx->opcode))); \ | |
7880 | } | |
7881 | ||
ee6e02c0 TM |
7882 | GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX) |
7883 | GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX) | |
5e591d88 | 7884 | GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) |
4b98eeef | 7885 | GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) |
2009227f | 7886 | GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX) |
d32404fe | 7887 | GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) |
d3f9df8f | 7888 | GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) |
bc80838f | 7889 | GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) |
5cb151ac | 7890 | GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) |
595c6eef TM |
7891 | GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) |
7892 | GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) | |
7893 | GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX) | |
7894 | GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX) | |
7895 | GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX) | |
7896 | GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX) | |
7897 | GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX) | |
7898 | GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX) | |
4f17e9c7 TM |
7899 | GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) |
7900 | GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) | |
959e9c9d TM |
7901 | GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) |
7902 | GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX) | |
ed8ac568 | 7903 | GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) |
7ee19fb9 | 7904 | GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) |
ed8ac568 | 7905 | GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) |
7ee19fb9 | 7906 | GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207) |
5177d2ca TM |
7907 | GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) |
7908 | GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) | |
7909 | GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) | |
7910 | GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) | |
7911 | GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) | |
7912 | GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) | |
88e33d08 TM |
7913 | GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) |
7914 | GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) | |
7915 | GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) | |
7916 | GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) | |
7917 | GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) | |
3d1140bf | 7918 | GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) |
ee6e02c0 | 7919 | |
3fd0aadf TM |
7920 | GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) |
7921 | GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) | |
ab9408a2 | 7922 | GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) |
b24d0b47 | 7923 | GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) |
2c0c52ae | 7924 | GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) |
cea4e574 | 7925 | GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) |
968e76bc | 7926 | GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) |
f53f81e0 TM |
7927 | GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207) |
7928 | GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207) | |
7929 | GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207) | |
7930 | GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207) | |
7931 | GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207) | |
7932 | GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207) | |
7933 | GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) | |
7934 | GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) | |
74698350 TM |
7935 | GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) |
7936 | GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) | |
3fd0aadf | 7937 | |
ee6e02c0 TM |
7938 | GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) |
7939 | GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) | |
5e591d88 | 7940 | GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) |
4b98eeef | 7941 | GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) |
2009227f | 7942 | GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) |
d32404fe | 7943 | GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) |
d3f9df8f | 7944 | GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) |
bc80838f | 7945 | GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) |
5cb151ac | 7946 | GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) |
595c6eef TM |
7947 | GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) |
7948 | GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) | |
7949 | GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX) | |
7950 | GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX) | |
7951 | GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX) | |
7952 | GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX) | |
7953 | GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX) | |
7954 | GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX) | |
959e9c9d TM |
7955 | GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) |
7956 | GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) | |
354a6dec TM |
7957 | GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX) |
7958 | GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX) | |
7959 | GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX) | |
ed8ac568 | 7960 | GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) |
5177d2ca TM |
7961 | GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) |
7962 | GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) | |
7963 | GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX) | |
7964 | GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX) | |
7965 | GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX) | |
7966 | GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX) | |
7967 | GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX) | |
7968 | GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX) | |
88e33d08 TM |
7969 | GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX) |
7970 | GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX) | |
7971 | GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX) | |
7972 | GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX) | |
7973 | GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX) | |
ee6e02c0 TM |
7974 | |
7975 | GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) | |
7976 | GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) | |
5e591d88 | 7977 | GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) |
4b98eeef | 7978 | GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) |
2009227f | 7979 | GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX) |
d32404fe | 7980 | GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) |
d3f9df8f | 7981 | GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) |
bc80838f | 7982 | GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) |
5cb151ac | 7983 | GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) |
595c6eef TM |
7984 | GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) |
7985 | GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) | |
7986 | GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX) | |
7987 | GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX) | |
7988 | GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX) | |
7989 | GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX) | |
7990 | GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX) | |
7991 | GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX) | |
959e9c9d TM |
7992 | GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) |
7993 | GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX) | |
354a6dec TM |
7994 | GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX) |
7995 | GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) | |
7996 | GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) | |
ed8ac568 | 7997 | GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) |
5177d2ca TM |
7998 | GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX) |
7999 | GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX) | |
8000 | GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX) | |
8001 | GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX) | |
8002 | GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX) | |
8003 | GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX) | |
8004 | GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX) | |
8005 | GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX) | |
88e33d08 TM |
8006 | GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX) |
8007 | GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX) | |
8008 | GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX) | |
8009 | GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) | |
8010 | GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) | |
ee6e02c0 | 8011 | |
79ca8a6a TM |
8012 | #define VSX_LOGICAL(name, tcg_op) \ |
8013 | static void glue(gen_, name)(DisasContext * ctx) \ | |
8014 | { \ | |
8015 | if (unlikely(!ctx->vsx_enabled)) { \ | |
8016 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
8017 | return; \ | |
8018 | } \ | |
8019 | tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \ | |
8020 | cpu_vsrh(xB(ctx->opcode))); \ | |
8021 | tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \ | |
8022 | cpu_vsrl(xB(ctx->opcode))); \ | |
8023 | } | |
8024 | ||
f976b09e AG |
8025 | VSX_LOGICAL(xxland, tcg_gen_and_i64) |
8026 | VSX_LOGICAL(xxlandc, tcg_gen_andc_i64) | |
8027 | VSX_LOGICAL(xxlor, tcg_gen_or_i64) | |
8028 | VSX_LOGICAL(xxlxor, tcg_gen_xor_i64) | |
8029 | VSX_LOGICAL(xxlnor, tcg_gen_nor_i64) | |
67a33f37 TM |
8030 | VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64) |
8031 | VSX_LOGICAL(xxlnand, tcg_gen_nand_i64) | |
8032 | VSX_LOGICAL(xxlorc, tcg_gen_orc_i64) | |
df020ce0 | 8033 | |
ce577d2e TM |
8034 | #define VSX_XXMRG(name, high) \ |
8035 | static void glue(gen_, name)(DisasContext * ctx) \ | |
8036 | { \ | |
8037 | TCGv_i64 a0, a1, b0, b1; \ | |
8038 | if (unlikely(!ctx->vsx_enabled)) { \ | |
8039 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
8040 | return; \ | |
8041 | } \ | |
f976b09e AG |
8042 | a0 = tcg_temp_new_i64(); \ |
8043 | a1 = tcg_temp_new_i64(); \ | |
8044 | b0 = tcg_temp_new_i64(); \ | |
8045 | b1 = tcg_temp_new_i64(); \ | |
ce577d2e TM |
8046 | if (high) { \ |
8047 | tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \ | |
8048 | tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \ | |
8049 | tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \ | |
8050 | tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \ | |
8051 | } else { \ | |
8052 | tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \ | |
8053 | tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \ | |
8054 | tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \ | |
8055 | tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \ | |
8056 | } \ | |
8057 | tcg_gen_shri_i64(a0, a0, 32); \ | |
8058 | tcg_gen_shri_i64(b0, b0, 32); \ | |
8059 | tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \ | |
8060 | b0, a0, 32, 32); \ | |
8061 | tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \ | |
8062 | b1, a1, 32, 32); \ | |
f976b09e AG |
8063 | tcg_temp_free_i64(a0); \ |
8064 | tcg_temp_free_i64(a1); \ | |
8065 | tcg_temp_free_i64(b0); \ | |
8066 | tcg_temp_free_i64(b1); \ | |
ce577d2e TM |
8067 | } |
8068 | ||
8069 | VSX_XXMRG(xxmrghw, 1) | |
8070 | VSX_XXMRG(xxmrglw, 0) | |
8071 | ||
551e3ef7 TM |
8072 | static void gen_xxsel(DisasContext * ctx) |
8073 | { | |
8074 | TCGv_i64 a, b, c; | |
8075 | if (unlikely(!ctx->vsx_enabled)) { | |
8076 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
8077 | return; | |
8078 | } | |
f976b09e AG |
8079 | a = tcg_temp_new_i64(); |
8080 | b = tcg_temp_new_i64(); | |
8081 | c = tcg_temp_new_i64(); | |
551e3ef7 TM |
8082 | |
8083 | tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode))); | |
8084 | tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode))); | |
8085 | tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode))); | |
8086 | ||
8087 | tcg_gen_and_i64(b, b, c); | |
8088 | tcg_gen_andc_i64(a, a, c); | |
8089 | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b); | |
8090 | ||
8091 | tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode))); | |
8092 | tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode))); | |
8093 | tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode))); | |
8094 | ||
8095 | tcg_gen_and_i64(b, b, c); | |
8096 | tcg_gen_andc_i64(a, a, c); | |
8097 | tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b); | |
8098 | ||
f976b09e AG |
8099 | tcg_temp_free_i64(a); |
8100 | tcg_temp_free_i64(b); | |
8101 | tcg_temp_free_i64(c); | |
551e3ef7 TM |
8102 | } |
8103 | ||
76c15fe0 TM |
8104 | static void gen_xxspltw(DisasContext *ctx) |
8105 | { | |
8106 | TCGv_i64 b, b2; | |
8107 | TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ? | |
8108 | cpu_vsrl(xB(ctx->opcode)) : | |
8109 | cpu_vsrh(xB(ctx->opcode)); | |
8110 | ||
8111 | if (unlikely(!ctx->vsx_enabled)) { | |
8112 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
8113 | return; | |
8114 | } | |
8115 | ||
f976b09e AG |
8116 | b = tcg_temp_new_i64(); |
8117 | b2 = tcg_temp_new_i64(); | |
76c15fe0 TM |
8118 | |
8119 | if (UIM(ctx->opcode) & 1) { | |
8120 | tcg_gen_ext32u_i64(b, vsr); | |
8121 | } else { | |
8122 | tcg_gen_shri_i64(b, vsr, 32); | |
8123 | } | |
8124 | ||
8125 | tcg_gen_shli_i64(b2, b, 32); | |
8126 | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2); | |
8127 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); | |
8128 | ||
f976b09e AG |
8129 | tcg_temp_free_i64(b); |
8130 | tcg_temp_free_i64(b2); | |
76c15fe0 TM |
8131 | } |
8132 | ||
acc42968 TM |
8133 | static void gen_xxsldwi(DisasContext *ctx) |
8134 | { | |
8135 | TCGv_i64 xth, xtl; | |
8136 | if (unlikely(!ctx->vsx_enabled)) { | |
8137 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
8138 | return; | |
8139 | } | |
f976b09e AG |
8140 | xth = tcg_temp_new_i64(); |
8141 | xtl = tcg_temp_new_i64(); | |
acc42968 TM |
8142 | |
8143 | switch (SHW(ctx->opcode)) { | |
8144 | case 0: { | |
8145 | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); | |
8146 | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); | |
8147 | break; | |
8148 | } | |
8149 | case 1: { | |
f976b09e | 8150 | TCGv_i64 t0 = tcg_temp_new_i64(); |
acc42968 TM |
8151 | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); |
8152 | tcg_gen_shli_i64(xth, xth, 32); | |
8153 | tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode))); | |
8154 | tcg_gen_shri_i64(t0, t0, 32); | |
8155 | tcg_gen_or_i64(xth, xth, t0); | |
8156 | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); | |
8157 | tcg_gen_shli_i64(xtl, xtl, 32); | |
8158 | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); | |
8159 | tcg_gen_shri_i64(t0, t0, 32); | |
8160 | tcg_gen_or_i64(xtl, xtl, t0); | |
f976b09e | 8161 | tcg_temp_free_i64(t0); |
acc42968 TM |
8162 | break; |
8163 | } | |
8164 | case 2: { | |
8165 | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); | |
8166 | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); | |
8167 | break; | |
8168 | } | |
8169 | case 3: { | |
f976b09e | 8170 | TCGv_i64 t0 = tcg_temp_new_i64(); |
acc42968 TM |
8171 | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); |
8172 | tcg_gen_shli_i64(xth, xth, 32); | |
8173 | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); | |
8174 | tcg_gen_shri_i64(t0, t0, 32); | |
8175 | tcg_gen_or_i64(xth, xth, t0); | |
8176 | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); | |
8177 | tcg_gen_shli_i64(xtl, xtl, 32); | |
8178 | tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode))); | |
8179 | tcg_gen_shri_i64(t0, t0, 32); | |
8180 | tcg_gen_or_i64(xtl, xtl, t0); | |
f976b09e | 8181 | tcg_temp_free_i64(t0); |
acc42968 TM |
8182 | break; |
8183 | } | |
8184 | } | |
8185 | ||
8186 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth); | |
8187 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl); | |
8188 | ||
f976b09e AG |
8189 | tcg_temp_free_i64(xth); |
8190 | tcg_temp_free_i64(xtl); | |
acc42968 TM |
8191 | } |
8192 | ||
f0b01f02 TM |
8193 | /*** Decimal Floating Point ***/ |
8194 | ||
8195 | static inline TCGv_ptr gen_fprp_ptr(int reg) | |
8196 | { | |
8197 | TCGv_ptr r = tcg_temp_new_ptr(); | |
8198 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg])); | |
8199 | return r; | |
8200 | } | |
8201 | ||
8202 | #if defined(TARGET_PPC64) | |
f0b01f02 TM |
8203 | static void gen_set_cr6_from_fpscr(DisasContext *ctx) |
8204 | { | |
8205 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
8206 | tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); | |
8207 | tcg_gen_shri_i32(cpu_crf[1], tmp, 28); | |
8208 | tcg_temp_free_i32(tmp); | |
8209 | } | |
8210 | #else | |
f0b01f02 TM |
8211 | static void gen_set_cr6_from_fpscr(DisasContext *ctx) |
8212 | { | |
8213 | tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); | |
8214 | } | |
8215 | #endif | |
8216 | ||
8217 | #define GEN_DFP_T_A_B_Rc(name) \ | |
8218 | static void gen_##name(DisasContext *ctx) \ | |
8219 | { \ | |
8220 | TCGv_ptr rd, ra, rb; \ | |
8221 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8222 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8223 | return; \ | |
8224 | } \ | |
8225 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8226 | rd = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8227 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8228 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8229 | gen_helper_##name(cpu_env, rd, ra, rb); \ | |
8230 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8231 | gen_set_cr6_from_fpscr(ctx); \ | |
8232 | } \ | |
8233 | tcg_temp_free_ptr(rd); \ | |
8234 | tcg_temp_free_ptr(ra); \ | |
8235 | tcg_temp_free_ptr(rb); \ | |
8236 | } | |
8237 | ||
8238 | #define GEN_DFP_BF_A_B(name) \ | |
8239 | static void gen_##name(DisasContext *ctx) \ | |
8240 | { \ | |
8241 | TCGv_ptr ra, rb; \ | |
8242 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8243 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8244 | return; \ | |
8245 | } \ | |
8246 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8247 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8248 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8249 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
8250 | cpu_env, ra, rb); \ | |
8251 | tcg_temp_free_ptr(ra); \ | |
8252 | tcg_temp_free_ptr(rb); \ | |
8253 | } | |
8254 | ||
8255 | #define GEN_DFP_BF_A_DCM(name) \ | |
8256 | static void gen_##name(DisasContext *ctx) \ | |
8257 | { \ | |
8258 | TCGv_ptr ra; \ | |
8259 | TCGv_i32 dcm; \ | |
8260 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8261 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8262 | return; \ | |
8263 | } \ | |
8264 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8265 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8266 | dcm = tcg_const_i32(DCM(ctx->opcode)); \ | |
8267 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
8268 | cpu_env, ra, dcm); \ | |
8269 | tcg_temp_free_ptr(ra); \ | |
8270 | tcg_temp_free_i32(dcm); \ | |
8271 | } | |
8272 | ||
8273 | #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \ | |
8274 | static void gen_##name(DisasContext *ctx) \ | |
8275 | { \ | |
8276 | TCGv_ptr rt, rb; \ | |
8277 | TCGv_i32 u32_1, u32_2; \ | |
8278 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8279 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8280 | return; \ | |
8281 | } \ | |
8282 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8283 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8284 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8285 | u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \ | |
8286 | u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \ | |
8287 | gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \ | |
8288 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8289 | gen_set_cr6_from_fpscr(ctx); \ | |
8290 | } \ | |
8291 | tcg_temp_free_ptr(rt); \ | |
8292 | tcg_temp_free_ptr(rb); \ | |
8293 | tcg_temp_free_i32(u32_1); \ | |
8294 | tcg_temp_free_i32(u32_2); \ | |
8295 | } | |
8296 | ||
8297 | #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \ | |
8298 | static void gen_##name(DisasContext *ctx) \ | |
8299 | { \ | |
8300 | TCGv_ptr rt, ra, rb; \ | |
8301 | TCGv_i32 i32; \ | |
8302 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8303 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8304 | return; \ | |
8305 | } \ | |
8306 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8307 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8308 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8309 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8310 | i32 = tcg_const_i32(i32fld(ctx->opcode)); \ | |
8311 | gen_helper_##name(cpu_env, rt, ra, rb, i32); \ | |
8312 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8313 | gen_set_cr6_from_fpscr(ctx); \ | |
8314 | } \ | |
8315 | tcg_temp_free_ptr(rt); \ | |
8316 | tcg_temp_free_ptr(rb); \ | |
8317 | tcg_temp_free_ptr(ra); \ | |
8318 | tcg_temp_free_i32(i32); \ | |
8319 | } | |
8320 | ||
8321 | #define GEN_DFP_T_B_Rc(name) \ | |
8322 | static void gen_##name(DisasContext *ctx) \ | |
8323 | { \ | |
8324 | TCGv_ptr rt, rb; \ | |
8325 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8326 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8327 | return; \ | |
8328 | } \ | |
8329 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8330 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8331 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8332 | gen_helper_##name(cpu_env, rt, rb); \ | |
8333 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8334 | gen_set_cr6_from_fpscr(ctx); \ | |
8335 | } \ | |
8336 | tcg_temp_free_ptr(rt); \ | |
8337 | tcg_temp_free_ptr(rb); \ | |
8338 | } | |
8339 | ||
8340 | #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \ | |
8341 | static void gen_##name(DisasContext *ctx) \ | |
8342 | { \ | |
8343 | TCGv_ptr rt, rs; \ | |
8344 | TCGv_i32 i32; \ | |
8345 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8346 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8347 | return; \ | |
8348 | } \ | |
8349 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8350 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8351 | rs = gen_fprp_ptr(fprfld(ctx->opcode)); \ | |
8352 | i32 = tcg_const_i32(i32fld(ctx->opcode)); \ | |
8353 | gen_helper_##name(cpu_env, rt, rs, i32); \ | |
8354 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8355 | gen_set_cr6_from_fpscr(ctx); \ | |
8356 | } \ | |
8357 | tcg_temp_free_ptr(rt); \ | |
8358 | tcg_temp_free_ptr(rs); \ | |
8359 | tcg_temp_free_i32(i32); \ | |
8360 | } | |
ce577d2e | 8361 | |
a9d7ba03 TM |
8362 | GEN_DFP_T_A_B_Rc(dadd) |
8363 | GEN_DFP_T_A_B_Rc(daddq) | |
2128f8a5 TM |
8364 | GEN_DFP_T_A_B_Rc(dsub) |
8365 | GEN_DFP_T_A_B_Rc(dsubq) | |
8de6a1cc TM |
8366 | GEN_DFP_T_A_B_Rc(dmul) |
8367 | GEN_DFP_T_A_B_Rc(dmulq) | |
9024ff40 TM |
8368 | GEN_DFP_T_A_B_Rc(ddiv) |
8369 | GEN_DFP_T_A_B_Rc(ddivq) | |
5833505b TM |
8370 | GEN_DFP_BF_A_B(dcmpu) |
8371 | GEN_DFP_BF_A_B(dcmpuq) | |
8372 | GEN_DFP_BF_A_B(dcmpo) | |
8373 | GEN_DFP_BF_A_B(dcmpoq) | |
e601c1ee TM |
8374 | GEN_DFP_BF_A_DCM(dtstdc) |
8375 | GEN_DFP_BF_A_DCM(dtstdcq) | |
1bf9c0e1 TM |
8376 | GEN_DFP_BF_A_DCM(dtstdg) |
8377 | GEN_DFP_BF_A_DCM(dtstdgq) | |
f3d2b0bc TM |
8378 | GEN_DFP_BF_A_B(dtstex) |
8379 | GEN_DFP_BF_A_B(dtstexq) | |
f6022a76 TM |
8380 | GEN_DFP_BF_A_B(dtstsf) |
8381 | GEN_DFP_BF_A_B(dtstsfq) | |
5826ebe2 TM |
8382 | GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC) |
8383 | GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC) | |
8384 | GEN_DFP_T_A_B_I32_Rc(dqua, RMC) | |
8385 | GEN_DFP_T_A_B_I32_Rc(dquaq, RMC) | |
512918aa TM |
8386 | GEN_DFP_T_A_B_I32_Rc(drrnd, RMC) |
8387 | GEN_DFP_T_A_B_I32_Rc(drrndq, RMC) | |
97c0d930 TM |
8388 | GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC) |
8389 | GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC) | |
8390 | GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC) | |
8391 | GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC) | |
290d9ee5 TM |
8392 | GEN_DFP_T_B_Rc(dctdp) |
8393 | GEN_DFP_T_B_Rc(dctqpq) | |
ca603eb4 TM |
8394 | GEN_DFP_T_B_Rc(drsp) |
8395 | GEN_DFP_T_B_Rc(drdpq) | |
f1214193 TM |
8396 | GEN_DFP_T_B_Rc(dcffix) |
8397 | GEN_DFP_T_B_Rc(dcffixq) | |
bea0dd79 TM |
8398 | GEN_DFP_T_B_Rc(dctfix) |
8399 | GEN_DFP_T_B_Rc(dctfixq) | |
7796676f TM |
8400 | GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP) |
8401 | GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP) | |
013c3ac0 TM |
8402 | GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP) |
8403 | GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP) | |
e8a48460 TM |
8404 | GEN_DFP_T_B_Rc(dxex) |
8405 | GEN_DFP_T_B_Rc(dxexq) | |
297666eb TM |
8406 | GEN_DFP_T_A_B_Rc(diex) |
8407 | GEN_DFP_T_A_B_Rc(diexq) | |
804e654a TM |
8408 | GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM) |
8409 | GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM) | |
8410 | GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM) | |
8411 | GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM) | |
8412 | ||
0487d6a8 | 8413 | /*** SPE extension ***/ |
0487d6a8 | 8414 | /* Register moves */ |
3cd7d1dd | 8415 | |
a0e13900 FC |
8416 | static inline void gen_evmra(DisasContext *ctx) |
8417 | { | |
8418 | ||
8419 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8420 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8421 | return; |
8422 | } | |
8423 | ||
a0e13900 FC |
8424 | TCGv_i64 tmp = tcg_temp_new_i64(); |
8425 | ||
8426 | /* tmp := rA_lo + rA_hi << 32 */ | |
13b6a455 | 8427 | tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
a0e13900 FC |
8428 | |
8429 | /* spe_acc := tmp */ | |
1328c2bf | 8430 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8431 | tcg_temp_free_i64(tmp); |
8432 | ||
8433 | /* rD := rA */ | |
13b6a455 AG |
8434 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8435 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
a0e13900 FC |
8436 | } |
8437 | ||
636aa200 BS |
8438 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
8439 | { | |
13b6a455 | 8440 | tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
f78fb44e | 8441 | } |
3cd7d1dd | 8442 | |
636aa200 BS |
8443 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
8444 | { | |
13b6a455 | 8445 | tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t); |
f78fb44e | 8446 | } |
3cd7d1dd | 8447 | |
70560da7 | 8448 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
99e300ef | 8449 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
8450 | { \ |
8451 | if (Rc(ctx->opcode)) \ | |
8452 | gen_##name1(ctx); \ | |
8453 | else \ | |
8454 | gen_##name0(ctx); \ | |
8455 | } | |
8456 | ||
8457 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 8458 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 8459 | { |
e06fcd75 | 8460 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
8461 | } |
8462 | ||
57951c27 | 8463 | /* SPE logic */ |
57951c27 | 8464 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ |
636aa200 | 8465 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8466 | { \ |
8467 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8468 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8469 | return; \ |
8470 | } \ | |
8471 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
8472 | cpu_gpr[rB(ctx->opcode)]); \ | |
8473 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
8474 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 8475 | } |
57951c27 AJ |
8476 | |
8477 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
8478 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
8479 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
8480 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
8481 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
8482 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
8483 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
8484 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 8485 | |
57951c27 | 8486 | /* SPE logic immediate */ |
57951c27 | 8487 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ |
636aa200 | 8488 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a | 8489 | { \ |
13b6a455 | 8490 | TCGv_i32 t0; \ |
3d3a6a0a | 8491 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8492 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
3d3a6a0a AJ |
8493 | return; \ |
8494 | } \ | |
13b6a455 AG |
8495 | t0 = tcg_temp_new_i32(); \ |
8496 | \ | |
8497 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8498 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
8499 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
8500 | \ | |
8501 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ | |
57951c27 | 8502 | tcg_opi(t0, t0, rB(ctx->opcode)); \ |
13b6a455 AG |
8503 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ |
8504 | \ | |
a7812ae4 | 8505 | tcg_temp_free_i32(t0); \ |
3d3a6a0a | 8506 | } |
57951c27 AJ |
8507 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); |
8508 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
8509 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
8510 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 8511 | |
57951c27 | 8512 | /* SPE arithmetic */ |
57951c27 | 8513 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 8514 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8515 | { \ |
13b6a455 | 8516 | TCGv_i32 t0; \ |
0487d6a8 | 8517 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8518 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
8519 | return; \ |
8520 | } \ | |
13b6a455 AG |
8521 | t0 = tcg_temp_new_i32(); \ |
8522 | \ | |
8523 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
57951c27 | 8524 | tcg_op(t0, t0); \ |
13b6a455 AG |
8525 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ |
8526 | \ | |
8527 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ | |
8528 | tcg_op(t0, t0); \ | |
8529 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ | |
8530 | \ | |
a7812ae4 | 8531 | tcg_temp_free_i32(t0); \ |
57951c27 | 8532 | } |
0487d6a8 | 8533 | |
636aa200 | 8534 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
8535 | { |
8536 | int l1 = gen_new_label(); | |
8537 | int l2 = gen_new_label(); | |
0487d6a8 | 8538 | |
57951c27 AJ |
8539 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
8540 | tcg_gen_neg_i32(ret, arg1); | |
8541 | tcg_gen_br(l2); | |
8542 | gen_set_label(l1); | |
a7812ae4 | 8543 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
8544 | gen_set_label(l2); |
8545 | } | |
8546 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
8547 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
8548 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
8549 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 8550 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 8551 | { |
57951c27 AJ |
8552 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
8553 | tcg_gen_ext16u_i32(ret, ret); | |
8554 | } | |
8555 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
8556 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
8557 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 8558 | |
57951c27 | 8559 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ |
636aa200 | 8560 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8561 | { \ |
13b6a455 | 8562 | TCGv_i32 t0, t1; \ |
0487d6a8 | 8563 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8564 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
8565 | return; \ |
8566 | } \ | |
13b6a455 AG |
8567 | t0 = tcg_temp_new_i32(); \ |
8568 | t1 = tcg_temp_new_i32(); \ | |
8569 | \ | |
8570 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8571 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8572 | tcg_op(t0, t0, t1); \ | |
8573 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
8574 | \ | |
8575 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ | |
8576 | tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \ | |
8577 | tcg_op(t0, t0, t1); \ | |
8578 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ | |
8579 | \ | |
a7812ae4 PB |
8580 | tcg_temp_free_i32(t0); \ |
8581 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 8582 | } |
0487d6a8 | 8583 | |
636aa200 | 8584 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8585 | { |
a7812ae4 | 8586 | TCGv_i32 t0; |
57951c27 | 8587 | int l1, l2; |
0487d6a8 | 8588 | |
57951c27 AJ |
8589 | l1 = gen_new_label(); |
8590 | l2 = gen_new_label(); | |
a7812ae4 | 8591 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
8592 | /* No error here: 6 bits are used */ |
8593 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
8594 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
8595 | tcg_gen_shr_i32(ret, arg1, t0); | |
8596 | tcg_gen_br(l2); | |
8597 | gen_set_label(l1); | |
8598 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 8599 | gen_set_label(l2); |
a7812ae4 | 8600 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8601 | } |
8602 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 8603 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8604 | { |
a7812ae4 | 8605 | TCGv_i32 t0; |
57951c27 AJ |
8606 | int l1, l2; |
8607 | ||
8608 | l1 = gen_new_label(); | |
8609 | l2 = gen_new_label(); | |
a7812ae4 | 8610 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
8611 | /* No error here: 6 bits are used */ |
8612 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
8613 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
8614 | tcg_gen_sar_i32(ret, arg1, t0); | |
8615 | tcg_gen_br(l2); | |
8616 | gen_set_label(l1); | |
8617 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 8618 | gen_set_label(l2); |
a7812ae4 | 8619 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8620 | } |
8621 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 8622 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8623 | { |
a7812ae4 | 8624 | TCGv_i32 t0; |
57951c27 AJ |
8625 | int l1, l2; |
8626 | ||
8627 | l1 = gen_new_label(); | |
8628 | l2 = gen_new_label(); | |
a7812ae4 | 8629 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
8630 | /* No error here: 6 bits are used */ |
8631 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
8632 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
8633 | tcg_gen_shl_i32(ret, arg1, t0); | |
8634 | tcg_gen_br(l2); | |
8635 | gen_set_label(l1); | |
8636 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 8637 | gen_set_label(l2); |
a7812ae4 | 8638 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8639 | } |
8640 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 8641 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8642 | { |
a7812ae4 | 8643 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
8644 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
8645 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 8646 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8647 | } |
8648 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 8649 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
8650 | { |
8651 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8652 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8653 | return; |
8654 | } | |
13b6a455 AG |
8655 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8656 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
57951c27 AJ |
8657 | } |
8658 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 8659 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 8660 | { |
57951c27 AJ |
8661 | tcg_gen_sub_i32(ret, arg2, arg1); |
8662 | } | |
8663 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 8664 | |
57951c27 | 8665 | /* SPE arithmetic immediate */ |
57951c27 | 8666 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ |
636aa200 | 8667 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8668 | { \ |
13b6a455 | 8669 | TCGv_i32 t0; \ |
57951c27 | 8670 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8671 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8672 | return; \ |
8673 | } \ | |
13b6a455 AG |
8674 | t0 = tcg_temp_new_i32(); \ |
8675 | \ | |
8676 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8677 | tcg_op(t0, t0, rA(ctx->opcode)); \ |
13b6a455 AG |
8678 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ |
8679 | \ | |
8680 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \ | |
8681 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
8682 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ | |
8683 | \ | |
a7812ae4 | 8684 | tcg_temp_free_i32(t0); \ |
57951c27 | 8685 | } |
57951c27 AJ |
8686 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); |
8687 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
8688 | ||
8689 | /* SPE comparison */ | |
57951c27 | 8690 | #define GEN_SPEOP_COMP(name, tcg_cond) \ |
636aa200 | 8691 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8692 | { \ |
8693 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8694 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8695 | return; \ |
8696 | } \ | |
8697 | int l1 = gen_new_label(); \ | |
8698 | int l2 = gen_new_label(); \ | |
8699 | int l3 = gen_new_label(); \ | |
8700 | int l4 = gen_new_label(); \ | |
8701 | \ | |
13b6a455 AG |
8702 | tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ |
8703 | tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
8704 | tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
8705 | tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \ | |
8706 | \ | |
8707 | tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
57951c27 | 8708 | cpu_gpr[rB(ctx->opcode)], l1); \ |
13b6a455 | 8709 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
8710 | tcg_gen_br(l2); \ |
8711 | gen_set_label(l1); \ | |
8712 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
8713 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
8714 | gen_set_label(l2); \ | |
13b6a455 | 8715 | tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ |
57951c27 AJ |
8716 | cpu_gprh[rB(ctx->opcode)], l3); \ |
8717 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
8718 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
8719 | tcg_gen_br(l4); \ | |
8720 | gen_set_label(l3); \ | |
8721 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
8722 | CRF_CH | CRF_CH_OR_CL); \ | |
8723 | gen_set_label(l4); \ | |
8724 | } | |
57951c27 AJ |
8725 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); |
8726 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
8727 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
8728 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
8729 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
8730 | ||
8731 | /* SPE misc */ | |
636aa200 | 8732 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
8733 | { |
8734 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
8735 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
8736 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 8737 | } |
636aa200 | 8738 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
8739 | { |
8740 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8741 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8742 | return; |
8743 | } | |
13b6a455 AG |
8744 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8745 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
57951c27 | 8746 | } |
636aa200 | 8747 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
8748 | { |
8749 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8750 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8751 | return; |
8752 | } | |
13b6a455 AG |
8753 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
8754 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
57951c27 | 8755 | } |
636aa200 | 8756 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
8757 | { |
8758 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8759 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8760 | return; |
8761 | } | |
33890b3e | 8762 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
13b6a455 AG |
8763 | TCGv tmp = tcg_temp_new(); |
8764 | tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]); | |
8765 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
8766 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp); | |
8767 | tcg_temp_free(tmp); | |
33890b3e | 8768 | } else { |
13b6a455 AG |
8769 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8770 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
33890b3e | 8771 | } |
57951c27 | 8772 | } |
636aa200 | 8773 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 8774 | { |
ae01847f | 8775 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 8776 | |
13b6a455 AG |
8777 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); |
8778 | tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); | |
57951c27 | 8779 | } |
636aa200 | 8780 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 8781 | { |
ae01847f | 8782 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 8783 | |
13b6a455 AG |
8784 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); |
8785 | tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); | |
0487d6a8 JM |
8786 | } |
8787 | ||
636aa200 | 8788 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 AJ |
8789 | { |
8790 | int l1 = gen_new_label(); | |
8791 | int l2 = gen_new_label(); | |
8792 | int l3 = gen_new_label(); | |
8793 | int l4 = gen_new_label(); | |
a7812ae4 | 8794 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
8795 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); |
8796 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
57951c27 | 8797 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
57951c27 AJ |
8798 | tcg_gen_br(l2); |
8799 | gen_set_label(l1); | |
57951c27 | 8800 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
57951c27 AJ |
8801 | gen_set_label(l2); |
8802 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
8803 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
57951c27 | 8804 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
8805 | tcg_gen_br(l4); |
8806 | gen_set_label(l3); | |
57951c27 | 8807 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 | 8808 | gen_set_label(l4); |
a7812ae4 | 8809 | tcg_temp_free_i32(t0); |
57951c27 | 8810 | } |
e8eaa2c0 BS |
8811 | |
8812 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
8813 | { |
8814 | gen_evsel(ctx); | |
8815 | } | |
e8eaa2c0 BS |
8816 | |
8817 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
8818 | { |
8819 | gen_evsel(ctx); | |
8820 | } | |
e8eaa2c0 BS |
8821 | |
8822 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
8823 | { |
8824 | gen_evsel(ctx); | |
8825 | } | |
e8eaa2c0 BS |
8826 | |
8827 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
8828 | { |
8829 | gen_evsel(ctx); | |
8830 | } | |
0487d6a8 | 8831 | |
a0e13900 FC |
8832 | /* Multiply */ |
8833 | ||
8834 | static inline void gen_evmwumi(DisasContext *ctx) | |
8835 | { | |
8836 | TCGv_i64 t0, t1; | |
8837 | ||
8838 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8839 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8840 | return; |
8841 | } | |
8842 | ||
8843 | t0 = tcg_temp_new_i64(); | |
8844 | t1 = tcg_temp_new_i64(); | |
8845 | ||
8846 | /* t0 := rA; t1 := rB */ | |
a0e13900 | 8847 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
13b6a455 | 8848 | tcg_gen_ext32u_i64(t0, t0); |
a0e13900 | 8849 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
13b6a455 | 8850 | tcg_gen_ext32u_i64(t1, t1); |
a0e13900 FC |
8851 | |
8852 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
8853 | ||
8854 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
8855 | ||
8856 | tcg_temp_free_i64(t0); | |
8857 | tcg_temp_free_i64(t1); | |
8858 | } | |
8859 | ||
8860 | static inline void gen_evmwumia(DisasContext *ctx) | |
8861 | { | |
8862 | TCGv_i64 tmp; | |
8863 | ||
8864 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8865 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8866 | return; |
8867 | } | |
8868 | ||
8869 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
8870 | ||
8871 | tmp = tcg_temp_new_i64(); | |
8872 | ||
8873 | /* acc := rD */ | |
8874 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 8875 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8876 | tcg_temp_free_i64(tmp); |
8877 | } | |
8878 | ||
8879 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
8880 | { | |
8881 | TCGv_i64 acc; | |
8882 | TCGv_i64 tmp; | |
8883 | ||
8884 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8885 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8886 | return; |
8887 | } | |
8888 | ||
8889 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
8890 | ||
8891 | acc = tcg_temp_new_i64(); | |
8892 | tmp = tcg_temp_new_i64(); | |
8893 | ||
8894 | /* tmp := rD */ | |
8895 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
8896 | ||
8897 | /* Load acc */ | |
1328c2bf | 8898 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8899 | |
8900 | /* acc := tmp + acc */ | |
8901 | tcg_gen_add_i64(acc, acc, tmp); | |
8902 | ||
8903 | /* Store acc */ | |
1328c2bf | 8904 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8905 | |
8906 | /* rD := acc */ | |
8907 | gen_store_gpr64(rD(ctx->opcode), acc); | |
8908 | ||
8909 | tcg_temp_free_i64(acc); | |
8910 | tcg_temp_free_i64(tmp); | |
8911 | } | |
8912 | ||
8913 | static inline void gen_evmwsmi(DisasContext *ctx) | |
8914 | { | |
8915 | TCGv_i64 t0, t1; | |
8916 | ||
8917 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8918 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8919 | return; |
8920 | } | |
8921 | ||
8922 | t0 = tcg_temp_new_i64(); | |
8923 | t1 = tcg_temp_new_i64(); | |
8924 | ||
8925 | /* t0 := rA; t1 := rB */ | |
13b6a455 AG |
8926 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
8927 | tcg_gen_ext32s_i64(t0, t0); | |
8928 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
8929 | tcg_gen_ext32s_i64(t1, t1); | |
a0e13900 FC |
8930 | |
8931 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
8932 | ||
8933 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
8934 | ||
8935 | tcg_temp_free_i64(t0); | |
8936 | tcg_temp_free_i64(t1); | |
8937 | } | |
8938 | ||
8939 | static inline void gen_evmwsmia(DisasContext *ctx) | |
8940 | { | |
8941 | TCGv_i64 tmp; | |
8942 | ||
8943 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
8944 | ||
8945 | tmp = tcg_temp_new_i64(); | |
8946 | ||
8947 | /* acc := rD */ | |
8948 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 8949 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8950 | |
8951 | tcg_temp_free_i64(tmp); | |
8952 | } | |
8953 | ||
8954 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
8955 | { | |
8956 | TCGv_i64 acc = tcg_temp_new_i64(); | |
8957 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
8958 | ||
8959 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
8960 | ||
8961 | acc = tcg_temp_new_i64(); | |
8962 | tmp = tcg_temp_new_i64(); | |
8963 | ||
8964 | /* tmp := rD */ | |
8965 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
8966 | ||
8967 | /* Load acc */ | |
1328c2bf | 8968 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8969 | |
8970 | /* acc := tmp + acc */ | |
8971 | tcg_gen_add_i64(acc, acc, tmp); | |
8972 | ||
8973 | /* Store acc */ | |
1328c2bf | 8974 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8975 | |
8976 | /* rD := acc */ | |
8977 | gen_store_gpr64(rD(ctx->opcode), acc); | |
8978 | ||
8979 | tcg_temp_free_i64(acc); | |
8980 | tcg_temp_free_i64(tmp); | |
8981 | } | |
8982 | ||
70560da7 FC |
8983 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
8984 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8985 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8986 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8987 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
8988 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
8989 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
8990 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // | |
8991 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); | |
8992 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
8993 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8994 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8995 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8996 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8997 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8998 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8999 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
9000 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
9001 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
9002 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); | |
9003 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
9004 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9005 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // | |
9006 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); | |
9007 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
9008 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
9009 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
9010 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
9011 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// | |
0487d6a8 | 9012 | |
6a6ae23f | 9013 | /* SPE load and stores */ |
636aa200 | 9014 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
9015 | { |
9016 | target_ulong uimm = rB(ctx->opcode); | |
9017 | ||
76db3ba4 | 9018 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 9019 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 9020 | } else { |
6a6ae23f | 9021 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
c791fe84 | 9022 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
9023 | tcg_gen_ext32u_tl(EA, EA); |
9024 | } | |
76db3ba4 | 9025 | } |
0487d6a8 | 9026 | } |
6a6ae23f | 9027 | |
636aa200 | 9028 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9029 | { |
6a6ae23f | 9030 | TCGv_i64 t0 = tcg_temp_new_i64(); |
76db3ba4 | 9031 | gen_qemu_ld64(ctx, t0, addr); |
13b6a455 | 9032 | gen_store_gpr64(rD(ctx->opcode), t0); |
6a6ae23f | 9033 | tcg_temp_free_i64(t0); |
0487d6a8 | 9034 | } |
6a6ae23f | 9035 | |
636aa200 | 9036 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9037 | { |
76db3ba4 AJ |
9038 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
9039 | gen_addr_add(ctx, addr, addr, 4); | |
9040 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
0487d6a8 | 9041 | } |
6a6ae23f | 9042 | |
636aa200 | 9043 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9044 | { |
9045 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9046 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 9047 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
9048 | gen_addr_add(ctx, addr, addr, 2); |
9049 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9050 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
9051 | gen_addr_add(ctx, addr, addr, 2); |
9052 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9053 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
9054 | gen_addr_add(ctx, addr, addr, 2); |
9055 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9056 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
6a6ae23f | 9057 | tcg_temp_free(t0); |
0487d6a8 JM |
9058 | } |
9059 | ||
636aa200 | 9060 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9061 | { |
9062 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9063 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
9064 | tcg_gen_shli_tl(t0, t0, 16); |
9065 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
9066 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f | 9067 | tcg_temp_free(t0); |
0487d6a8 JM |
9068 | } |
9069 | ||
636aa200 | 9070 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9071 | { |
9072 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9073 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
9074 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
9075 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f | 9076 | tcg_temp_free(t0); |
0487d6a8 JM |
9077 | } |
9078 | ||
636aa200 | 9079 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9080 | { |
9081 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9082 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
9083 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
9084 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f AJ |
9085 | tcg_temp_free(t0); |
9086 | } | |
9087 | ||
636aa200 | 9088 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9089 | { |
9090 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9091 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 9092 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
9093 | gen_addr_add(ctx, addr, addr, 2); |
9094 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9095 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
6a6ae23f AJ |
9096 | tcg_temp_free(t0); |
9097 | } | |
9098 | ||
636aa200 | 9099 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9100 | { |
76db3ba4 AJ |
9101 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
9102 | gen_addr_add(ctx, addr, addr, 2); | |
9103 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
9104 | } |
9105 | ||
636aa200 | 9106 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9107 | { |
76db3ba4 AJ |
9108 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
9109 | gen_addr_add(ctx, addr, addr, 2); | |
9110 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
9111 | } |
9112 | ||
636aa200 | 9113 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9114 | { |
9115 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9116 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f AJ |
9117 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
9118 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f AJ |
9119 | tcg_temp_free(t0); |
9120 | } | |
9121 | ||
636aa200 | 9122 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9123 | { |
9124 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9125 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
9126 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
9127 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
9128 | gen_addr_add(ctx, addr, addr, 2); |
9129 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
9130 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
9131 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
6a6ae23f AJ |
9132 | tcg_temp_free(t0); |
9133 | } | |
9134 | ||
636aa200 | 9135 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9136 | { |
6a6ae23f | 9137 | TCGv_i64 t0 = tcg_temp_new_i64(); |
13b6a455 | 9138 | gen_load_gpr64(t0, rS(ctx->opcode)); |
76db3ba4 | 9139 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f | 9140 | tcg_temp_free_i64(t0); |
6a6ae23f AJ |
9141 | } |
9142 | ||
636aa200 | 9143 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9144 | { |
76db3ba4 | 9145 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
76db3ba4 AJ |
9146 | gen_addr_add(ctx, addr, addr, 4); |
9147 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
9148 | } |
9149 | ||
636aa200 | 9150 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9151 | { |
9152 | TCGv t0 = tcg_temp_new(); | |
6a6ae23f | 9153 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); |
76db3ba4 AJ |
9154 | gen_qemu_st16(ctx, t0, addr); |
9155 | gen_addr_add(ctx, addr, addr, 2); | |
76db3ba4 | 9156 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
76db3ba4 | 9157 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 9158 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 9159 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 9160 | tcg_temp_free(t0); |
76db3ba4 AJ |
9161 | gen_addr_add(ctx, addr, addr, 2); |
9162 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
9163 | } |
9164 | ||
636aa200 | 9165 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9166 | { |
9167 | TCGv t0 = tcg_temp_new(); | |
6a6ae23f | 9168 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); |
76db3ba4 AJ |
9169 | gen_qemu_st16(ctx, t0, addr); |
9170 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 9171 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 9172 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
9173 | tcg_temp_free(t0); |
9174 | } | |
9175 | ||
636aa200 | 9176 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9177 | { |
76db3ba4 | 9178 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
76db3ba4 AJ |
9179 | gen_addr_add(ctx, addr, addr, 2); |
9180 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
9181 | } |
9182 | ||
636aa200 | 9183 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9184 | { |
76db3ba4 | 9185 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
9186 | } |
9187 | ||
636aa200 | 9188 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9189 | { |
76db3ba4 | 9190 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
9191 | } |
9192 | ||
9193 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 9194 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
9195 | { \ |
9196 | TCGv t0; \ | |
9197 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 9198 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
6a6ae23f AJ |
9199 | return; \ |
9200 | } \ | |
76db3ba4 | 9201 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
9202 | t0 = tcg_temp_new(); \ |
9203 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 9204 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 9205 | } else { \ |
76db3ba4 | 9206 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
9207 | } \ |
9208 | gen_op_##name(ctx, t0); \ | |
9209 | tcg_temp_free(t0); \ | |
9210 | } | |
9211 | ||
9212 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
9213 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
9214 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
9215 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
9216 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
9217 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
9218 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
9219 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
9220 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
9221 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
9222 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
9223 | ||
9224 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
9225 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
9226 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
9227 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
9228 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
9229 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
9230 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
9231 | |
9232 | /* Multiply and add - TODO */ | |
9233 | #if 0 | |
70560da7 FC |
9234 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
9235 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9236 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9237 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9238 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9239 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9240 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9241 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9242 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9243 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9244 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9245 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9246 | ||
9247 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9248 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9249 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
9250 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9251 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9252 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9253 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9254 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9255 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
9256 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9257 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9258 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9259 | ||
9260 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9261 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9262 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9263 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9264 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); | |
9265 | ||
9266 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9267 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9268 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9269 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9270 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9271 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9272 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9273 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9274 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9275 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9276 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9277 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9278 | ||
9279 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
9280 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
9281 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9282 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9283 | ||
9284 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9285 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9286 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9287 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9288 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9289 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9290 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9291 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9292 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9293 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9294 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9295 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9296 | ||
9297 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
9298 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
9299 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9300 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
9301 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
9302 | #endif |
9303 | ||
9304 | /*** SPE floating-point extension ***/ | |
1c97856d | 9305 | #define GEN_SPEFPUOP_CONV_32_32(name) \ |
636aa200 | 9306 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9307 | { \ |
9308 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
9309 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
13b6a455 AG |
9310 | gen_helper_##name(t0, cpu_env, t0); \ |
9311 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
1c97856d | 9312 | tcg_temp_free_i32(t0); \ |
57951c27 | 9313 | } |
1c97856d | 9314 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 9315 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9316 | { \ |
9317 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
13b6a455 | 9318 | TCGv_i32 t1 = tcg_temp_new_i32(); \ |
1c97856d | 9319 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
13b6a455 AG |
9320 | gen_helper_##name(t1, cpu_env, t0); \ |
9321 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \ | |
1c97856d | 9322 | tcg_temp_free_i64(t0); \ |
13b6a455 | 9323 | tcg_temp_free_i32(t1); \ |
1c97856d AJ |
9324 | } |
9325 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 9326 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9327 | { \ |
9328 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
13b6a455 AG |
9329 | TCGv_i32 t1 = tcg_temp_new_i32(); \ |
9330 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
9331 | gen_helper_##name(t0, cpu_env, t1); \ | |
1c97856d AJ |
9332 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9333 | tcg_temp_free_i64(t0); \ | |
13b6a455 | 9334 | tcg_temp_free_i32(t1); \ |
1c97856d AJ |
9335 | } |
9336 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 9337 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9338 | { \ |
9339 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
9340 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 9341 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
9342 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9343 | tcg_temp_free_i64(t0); \ | |
9344 | } | |
9345 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 9346 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 9347 | { \ |
13b6a455 | 9348 | TCGv_i32 t0, t1; \ |
1c97856d | 9349 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 9350 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9351 | return; \ |
9352 | } \ | |
13b6a455 AG |
9353 | t0 = tcg_temp_new_i32(); \ |
9354 | t1 = tcg_temp_new_i32(); \ | |
9355 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
9356 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
9357 | gen_helper_##name(t0, cpu_env, t0, t1); \ | |
9358 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
9359 | \ | |
9360 | tcg_temp_free_i32(t0); \ | |
9361 | tcg_temp_free_i32(t1); \ | |
1c97856d AJ |
9362 | } |
9363 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 9364 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9365 | { \ |
9366 | TCGv_i64 t0, t1; \ | |
9367 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 9368 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9369 | return; \ |
9370 | } \ | |
9371 | t0 = tcg_temp_new_i64(); \ | |
9372 | t1 = tcg_temp_new_i64(); \ | |
9373 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
9374 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 9375 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
9376 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9377 | tcg_temp_free_i64(t0); \ | |
9378 | tcg_temp_free_i64(t1); \ | |
9379 | } | |
9380 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 9381 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 9382 | { \ |
13b6a455 | 9383 | TCGv_i32 t0, t1; \ |
1c97856d | 9384 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 9385 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9386 | return; \ |
9387 | } \ | |
13b6a455 AG |
9388 | t0 = tcg_temp_new_i32(); \ |
9389 | t1 = tcg_temp_new_i32(); \ | |
9390 | \ | |
9391 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
9392 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
9393 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ | |
9394 | \ | |
9395 | tcg_temp_free_i32(t0); \ | |
9396 | tcg_temp_free_i32(t1); \ | |
1c97856d AJ |
9397 | } |
9398 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 9399 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9400 | { \ |
9401 | TCGv_i64 t0, t1; \ | |
9402 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 9403 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9404 | return; \ |
9405 | } \ | |
9406 | t0 = tcg_temp_new_i64(); \ | |
9407 | t1 = tcg_temp_new_i64(); \ | |
9408 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
9409 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 9410 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
9411 | tcg_temp_free_i64(t0); \ |
9412 | tcg_temp_free_i64(t1); \ | |
9413 | } | |
57951c27 | 9414 | |
0487d6a8 JM |
9415 | /* Single precision floating-point vectors operations */ |
9416 | /* Arithmetic */ | |
1c97856d AJ |
9417 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
9418 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
9419 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
9420 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 9421 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
9422 | { |
9423 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9424 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9425 | return; |
9426 | } | |
13b6a455 AG |
9427 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
9428 | ~0x80000000); | |
9429 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], | |
9430 | ~0x80000000); | |
1c97856d | 9431 | } |
636aa200 | 9432 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
9433 | { |
9434 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9435 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9436 | return; |
9437 | } | |
13b6a455 AG |
9438 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
9439 | 0x80000000); | |
9440 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], | |
9441 | 0x80000000); | |
1c97856d | 9442 | } |
636aa200 | 9443 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
9444 | { |
9445 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9446 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9447 | return; |
9448 | } | |
13b6a455 AG |
9449 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
9450 | 0x80000000); | |
9451 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], | |
9452 | 0x80000000); | |
1c97856d AJ |
9453 | } |
9454 | ||
0487d6a8 | 9455 | /* Conversion */ |
1c97856d AJ |
9456 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
9457 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
9458 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
9459 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
9460 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
9461 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
9462 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
9463 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
9464 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
9465 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
9466 | ||
0487d6a8 | 9467 | /* Comparison */ |
1c97856d AJ |
9468 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
9469 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
9470 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
9471 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
9472 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
9473 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
9474 | |
9475 | /* Opcodes definitions */ | |
70560da7 FC |
9476 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9477 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
9478 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9479 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
9480 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9481 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9482 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9483 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9484 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9485 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9486 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9487 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9488 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9489 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
9490 | |
9491 | /* Single precision floating-point operations */ | |
9492 | /* Arithmetic */ | |
1c97856d AJ |
9493 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
9494 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
9495 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
9496 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 9497 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
9498 | { |
9499 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9500 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9501 | return; |
9502 | } | |
6d5c34fa | 9503 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 9504 | } |
636aa200 | 9505 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
9506 | { |
9507 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9508 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9509 | return; |
9510 | } | |
6d5c34fa | 9511 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 9512 | } |
636aa200 | 9513 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
9514 | { |
9515 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9516 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9517 | return; |
9518 | } | |
6d5c34fa | 9519 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
9520 | } |
9521 | ||
0487d6a8 | 9522 | /* Conversion */ |
1c97856d AJ |
9523 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
9524 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
9525 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
9526 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
9527 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
9528 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
9529 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
9530 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
9531 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
9532 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
9533 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
9534 | ||
0487d6a8 | 9535 | /* Comparison */ |
1c97856d AJ |
9536 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
9537 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
9538 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
9539 | GEN_SPEFPUOP_COMP_32(efststgt); | |
9540 | GEN_SPEFPUOP_COMP_32(efststlt); | |
9541 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
9542 | |
9543 | /* Opcodes definitions */ | |
70560da7 FC |
9544 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9545 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
9546 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9547 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
9548 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9549 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // | |
9550 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9551 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9552 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9553 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9554 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9555 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9556 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9557 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
9558 | |
9559 | /* Double precision floating-point operations */ | |
9560 | /* Arithmetic */ | |
1c97856d AJ |
9561 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
9562 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
9563 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
9564 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 9565 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
9566 | { |
9567 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9568 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9569 | return; |
9570 | } | |
6d5c34fa | 9571 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
13b6a455 AG |
9572 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], |
9573 | ~0x80000000); | |
1c97856d | 9574 | } |
636aa200 | 9575 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
9576 | { |
9577 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9578 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9579 | return; |
9580 | } | |
6d5c34fa | 9581 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
13b6a455 AG |
9582 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], |
9583 | 0x80000000); | |
1c97856d | 9584 | } |
636aa200 | 9585 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
9586 | { |
9587 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9588 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9589 | return; |
9590 | } | |
6d5c34fa | 9591 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
13b6a455 AG |
9592 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], |
9593 | 0x80000000); | |
1c97856d AJ |
9594 | } |
9595 | ||
0487d6a8 | 9596 | /* Conversion */ |
1c97856d AJ |
9597 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
9598 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
9599 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
9600 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
9601 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
9602 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
9603 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
9604 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
9605 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
9606 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
9607 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
9608 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
9609 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
9610 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
9611 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 9612 | |
0487d6a8 | 9613 | /* Comparison */ |
1c97856d AJ |
9614 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
9615 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
9616 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
9617 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
9618 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
9619 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
9620 | |
9621 | /* Opcodes definitions */ | |
70560da7 FC |
9622 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
9623 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9624 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // | |
9625 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9626 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // | |
9627 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9628 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
9629 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // | |
9630 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9631 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9632 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9633 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9634 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9635 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9636 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
9637 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
0487d6a8 | 9638 | |
c227f099 | 9639 | static opcode_t opcodes[] = { |
5c55ff99 BS |
9640 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
9641 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
9642 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
9643 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
9644 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
fcfda20f | 9645 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
9646 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
9647 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9648 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9649 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9650 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9651 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
9652 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
9653 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
9654 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
9655 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9656 | #if defined(TARGET_PPC64) | |
9657 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
9658 | #endif | |
9659 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
9660 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
9661 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9662 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9663 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9664 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
9665 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
9666 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
9667 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9668 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9669 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9670 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 9671 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 9672 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 9673 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 9674 | #if defined(TARGET_PPC64) |
eaabeef2 | 9675 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 9676 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
725bcec2 | 9677 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 9678 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
9679 | #endif |
9680 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9681 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9682 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9683 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
9684 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
9685 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
9686 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
9687 | #if defined(TARGET_PPC64) | |
9688 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
9689 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
9690 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
9691 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
9692 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
9693 | #endif | |
9694 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
9695 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
9696 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
9697 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
9698 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
bf45a2e6 | 9699 | GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), |
5c55ff99 | 9700 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
bf45a2e6 AJ |
9701 | GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), |
9702 | GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), | |
f0332888 | 9703 | GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), |
097ec5d8 TM |
9704 | GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207), |
9705 | GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207), | |
5c55ff99 BS |
9706 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
9707 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
9708 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
9709 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
7d08d856 AJ |
9710 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT), |
9711 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT), | |
5c55ff99 BS |
9712 | #if defined(TARGET_PPC64) |
9713 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9714 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
9715 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9716 | #endif | |
9717 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9718 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9719 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
9720 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
9721 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
9722 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
9723 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
9724 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
5c77a786 TM |
9725 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9726 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 9727 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
587c51f7 TM |
9728 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9729 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
9730 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
9731 | #if defined(TARGET_PPC64) | |
f844c817 | 9732 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 9733 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 9734 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 9735 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
9736 | #endif |
9737 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
9738 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
9739 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9740 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9741 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
9742 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
52a4984d | 9743 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
9744 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
9745 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
9746 | #if defined(TARGET_PPC64) | |
9747 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
9748 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
9749 | #endif | |
9750 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
9751 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
9752 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9753 | #if defined(TARGET_PPC64) | |
9754 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
9755 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9756 | #endif | |
9757 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
9758 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
9759 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
9760 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
9761 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
9762 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
9763 | #if defined(TARGET_PPC64) | |
9764 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
9765 | #endif | |
9766 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
9767 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), | |
9768 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
9769 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
9770 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
3f34cf91 CLG |
9771 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
9772 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), | |
4d09d529 | 9773 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 9774 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
9775 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
9776 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
9777 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
9778 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
9779 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
9780 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
9781 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
9782 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
9783 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
9784 | #if defined(TARGET_PPC64) | |
9785 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
9786 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
9787 | PPC_SEGMENT_64B), | |
9788 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
9789 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
9790 | PPC_SEGMENT_64B), | |
efdef95f DG |
9791 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
9792 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
9793 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
9794 | #endif |
9795 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
9796 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
9797 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
9798 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
9799 | #if defined(TARGET_PPC64) | |
9800 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
9801 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
9802 | #endif | |
9803 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
9804 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
9805 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
9806 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
9807 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
9808 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
9809 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
9810 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
9811 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
9812 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
9813 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
9814 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
9815 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
9816 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
9817 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
9818 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
9819 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
9820 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
9821 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
9822 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
9823 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
9824 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
9825 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
9826 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
9827 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
9828 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
9829 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
9830 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
9831 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
9832 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
9833 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
9834 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
9835 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
9836 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
9837 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
9838 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
9839 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
9840 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
9841 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
9842 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
9843 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
9844 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
9845 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
9846 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
9847 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
9848 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
9849 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
9850 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
9851 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
9852 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9853 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9854 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
9855 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
9856 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9857 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9858 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
9859 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
9860 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
9861 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
9862 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
9863 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
9864 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
9865 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
9866 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
9867 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
9868 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
9869 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
9870 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
9871 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
9872 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
9873 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 9874 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
9875 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
9876 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
9877 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
9878 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
9879 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
9880 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
9881 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
9882 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
9883 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
9884 | PPC_NONE, PPC2_BOOKE206), | |
9885 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
9886 | PPC_NONE, PPC2_BOOKE206), | |
9887 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
9888 | PPC_NONE, PPC2_BOOKE206), | |
9889 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
9890 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
9891 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
9892 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
9893 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
9894 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
9895 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
9896 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 9897 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 9898 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 9899 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
9900 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
9901 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 9902 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
9903 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
9904 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
9905 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
9906 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
9907 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
9908 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
5c55ff99 BS |
9909 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
9910 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
9911 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
9912 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
9913 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
9914 | ||
9915 | #undef GEN_INT_ARITH_ADD | |
9916 | #undef GEN_INT_ARITH_ADD_CONST | |
9917 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
9918 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
9919 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
9920 | add_ca, compute_ca, compute_ov) \ | |
9921 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
9922 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
9923 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
9924 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
9925 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
9926 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
9927 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
9928 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
9929 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
9930 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
9931 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
9932 | ||
9933 | #undef GEN_INT_ARITH_DIVW | |
9934 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
9935 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
9936 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
9937 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
9938 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
9939 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
9940 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9941 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
9942 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9943 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
5c55ff99 BS |
9944 | |
9945 | #if defined(TARGET_PPC64) | |
9946 | #undef GEN_INT_ARITH_DIVD | |
9947 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
9948 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
9949 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
9950 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
9951 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
9952 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
9953 | ||
98d1eb27 TM |
9954 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9955 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
9956 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9957 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
98d1eb27 | 9958 | |
5c55ff99 BS |
9959 | #undef GEN_INT_ARITH_MUL_HELPER |
9960 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
9961 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
9962 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
9963 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
9964 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
9965 | #endif | |
9966 | ||
9967 | #undef GEN_INT_ARITH_SUBF | |
9968 | #undef GEN_INT_ARITH_SUBF_CONST | |
9969 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
9970 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
9971 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
9972 | add_ca, compute_ca, compute_ov) \ | |
9973 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
9974 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
9975 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
9976 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
9977 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
9978 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
9979 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
9980 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
9981 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
9982 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
9983 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
9984 | ||
9985 | #undef GEN_LOGICAL1 | |
9986 | #undef GEN_LOGICAL2 | |
9987 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
9988 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
9989 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
9990 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
9991 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
9992 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
9993 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
9994 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
9995 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
9996 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
9997 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
9998 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
9999 | #if defined(TARGET_PPC64) | |
10000 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
10001 | #endif | |
10002 | ||
10003 | #if defined(TARGET_PPC64) | |
10004 | #undef GEN_PPC64_R2 | |
10005 | #undef GEN_PPC64_R4 | |
10006 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
10007 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
10008 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
10009 | PPC_64B) | |
10010 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
10011 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
10012 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
10013 | PPC_64B), \ | |
10014 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
10015 | PPC_64B), \ | |
10016 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
10017 | PPC_64B) | |
10018 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
10019 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
10020 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
10021 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
10022 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
10023 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
10024 | #endif | |
10025 | ||
10026 | #undef _GEN_FLOAT_ACB | |
10027 | #undef GEN_FLOAT_ACB | |
10028 | #undef _GEN_FLOAT_AB | |
10029 | #undef GEN_FLOAT_AB | |
10030 | #undef _GEN_FLOAT_AC | |
10031 | #undef GEN_FLOAT_AC | |
10032 | #undef GEN_FLOAT_B | |
10033 | #undef GEN_FLOAT_BS | |
10034 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
10035 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
10036 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
10037 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
10038 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
10039 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
10040 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
10041 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
10042 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
10043 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
10044 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
10045 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
10046 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
10047 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
10048 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
10049 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
10050 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
10051 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
10052 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
10053 | ||
10054 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
10055 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
10056 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
10057 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
10058 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
10059 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
10060 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
10061 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
10062 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
10063 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
10064 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
10065 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
da29cb7b | 10066 | GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206), |
6d41d146 | 10067 | GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206), |
5c55ff99 | 10068 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), |
fab7fe42 | 10069 | GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 | 10070 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), |
fab7fe42 | 10071 | GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 BS |
10072 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), |
10073 | #if defined(TARGET_PPC64) | |
10074 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), | |
28288b48 TM |
10075 | GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
10076 | GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), | |
10077 | GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), | |
5c55ff99 | 10078 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), |
fab7fe42 | 10079 | GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 | 10080 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), |
fab7fe42 | 10081 | GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 BS |
10082 | #endif |
10083 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), | |
10084 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
10085 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
10086 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
5c55ff99 BS |
10087 | |
10088 | #undef GEN_LD | |
10089 | #undef GEN_LDU | |
10090 | #undef GEN_LDUX | |
cd6e9320 | 10091 | #undef GEN_LDX_E |
5c55ff99 BS |
10092 | #undef GEN_LDS |
10093 | #define GEN_LD(name, ldop, opc, type) \ | |
10094 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10095 | #define GEN_LDU(name, ldop, opc, type) \ | |
10096 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10097 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
10098 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
10099 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
10100 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
10101 | #define GEN_LDS(name, ldop, op, type) \ |
10102 | GEN_LD(name, ldop, op | 0x20, type) \ | |
10103 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
10104 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
10105 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
10106 | ||
10107 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
10108 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
10109 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
10110 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
10111 | #if defined(TARGET_PPC64) | |
10112 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
10113 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
10114 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
10115 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
cd6e9320 | 10116 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
10117 | #endif |
10118 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
10119 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
10120 | ||
10121 | #undef GEN_ST | |
10122 | #undef GEN_STU | |
10123 | #undef GEN_STUX | |
cd6e9320 | 10124 | #undef GEN_STX_E |
5c55ff99 BS |
10125 | #undef GEN_STS |
10126 | #define GEN_ST(name, stop, opc, type) \ | |
10127 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10128 | #define GEN_STU(name, stop, opc, type) \ | |
10129 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10130 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
10131 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
10132 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
10133 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
10134 | #define GEN_STS(name, stop, op, type) \ |
10135 | GEN_ST(name, stop, op | 0x20, type) \ | |
10136 | GEN_STU(name, stop, op | 0x21, type) \ | |
10137 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
10138 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
10139 | ||
10140 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
10141 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
10142 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
10143 | #if defined(TARGET_PPC64) | |
10144 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
10145 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
cd6e9320 | 10146 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
10147 | #endif |
10148 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
10149 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
10150 | ||
10151 | #undef GEN_LDF | |
10152 | #undef GEN_LDUF | |
10153 | #undef GEN_LDUXF | |
10154 | #undef GEN_LDXF | |
10155 | #undef GEN_LDFS | |
10156 | #define GEN_LDF(name, ldop, opc, type) \ | |
10157 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10158 | #define GEN_LDUF(name, ldop, opc, type) \ | |
10159 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10160 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
10161 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
10162 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
10163 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
10164 | #define GEN_LDFS(name, ldop, op, type) \ | |
10165 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
10166 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
10167 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
10168 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
10169 | ||
10170 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
10171 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
199f830d | 10172 | GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), |
66c3e328 | 10173 | GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206), |
05050ee8 AJ |
10174 | GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
10175 | GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
10176 | |
10177 | #undef GEN_STF | |
10178 | #undef GEN_STUF | |
10179 | #undef GEN_STUXF | |
10180 | #undef GEN_STXF | |
10181 | #undef GEN_STFS | |
10182 | #define GEN_STF(name, stop, opc, type) \ | |
10183 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10184 | #define GEN_STUF(name, stop, opc, type) \ | |
10185 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10186 | #define GEN_STUXF(name, stop, opc, type) \ | |
10187 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
10188 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
10189 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
10190 | #define GEN_STFS(name, stop, op, type) \ | |
10191 | GEN_STF(name, stop, op | 0x20, type) \ | |
10192 | GEN_STUF(name, stop, op | 0x21, type) \ | |
10193 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
10194 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
10195 | ||
10196 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
10197 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
10198 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
44bc0c4d AJ |
10199 | GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
10200 | GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
10201 | |
10202 | #undef GEN_CRLOGIC | |
10203 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
10204 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
10205 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
10206 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
10207 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
10208 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
10209 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
10210 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
10211 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
10212 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
10213 | ||
10214 | #undef GEN_MAC_HANDLER | |
10215 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
10216 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
10217 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
10218 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
10219 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
10220 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
10221 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
10222 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
10223 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
10224 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
10225 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
10226 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
10227 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
10228 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
10229 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
10230 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
10231 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
10232 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
10233 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
10234 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
10235 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
10236 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
10237 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
10238 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
10239 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
10240 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
10241 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
10242 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
10243 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
10244 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
10245 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
10246 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
10247 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
10248 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
10249 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
10250 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
10251 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
10252 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
10253 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
10254 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
10255 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
10256 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
10257 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
10258 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
10259 | ||
10260 | #undef GEN_VR_LDX | |
10261 | #undef GEN_VR_STX | |
10262 | #undef GEN_VR_LVE | |
10263 | #undef GEN_VR_STVE | |
10264 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
10265 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10266 | #define GEN_VR_STX(name, opc2, opc3) \ | |
10267 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10268 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
10269 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10270 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
10271 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10272 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
10273 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
10274 | GEN_VR_LVE(bx, 0x07, 0x00), | |
10275 | GEN_VR_LVE(hx, 0x07, 0x01), | |
10276 | GEN_VR_LVE(wx, 0x07, 0x02), | |
10277 | GEN_VR_STX(svx, 0x07, 0x07), | |
10278 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
10279 | GEN_VR_STVE(bx, 0x07, 0x04), | |
10280 | GEN_VR_STVE(hx, 0x07, 0x05), | |
10281 | GEN_VR_STVE(wx, 0x07, 0x06), | |
10282 | ||
10283 | #undef GEN_VX_LOGICAL | |
10284 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
10285 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
111c5f54 TM |
10286 | |
10287 | #undef GEN_VX_LOGICAL_207 | |
10288 | #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \ | |
10289 | GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) | |
10290 | ||
5c55ff99 BS |
10291 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), |
10292 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
10293 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
10294 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
10295 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
111c5f54 TM |
10296 | GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26), |
10297 | GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22), | |
10298 | GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21), | |
5c55ff99 BS |
10299 | |
10300 | #undef GEN_VXFORM | |
10301 | #define GEN_VXFORM(name, opc2, opc3) \ | |
10302 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
50f5fc0c TM |
10303 | |
10304 | #undef GEN_VXFORM_207 | |
10305 | #define GEN_VXFORM_207(name, opc2, opc3) \ | |
10306 | GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) | |
10307 | ||
5dffff5a TM |
10308 | #undef GEN_VXFORM_DUAL |
10309 | #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ | |
10310 | GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) | |
10311 | ||
a737d3eb TM |
10312 | #undef GEN_VXRFORM_DUAL |
10313 | #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \ | |
10314 | GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \ | |
10315 | GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1), | |
10316 | ||
5c55ff99 BS |
10317 | GEN_VXFORM(vaddubm, 0, 0), |
10318 | GEN_VXFORM(vadduhm, 0, 1), | |
10319 | GEN_VXFORM(vadduwm, 0, 2), | |
56eabc75 | 10320 | GEN_VXFORM_207(vaddudm, 0, 3), |
e8f7b27b TM |
10321 | GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), |
10322 | GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), | |
5c55ff99 | 10323 | GEN_VXFORM(vsubuwm, 0, 18), |
56eabc75 | 10324 | GEN_VXFORM_207(vsubudm, 0, 19), |
5c55ff99 BS |
10325 | GEN_VXFORM(vmaxub, 1, 0), |
10326 | GEN_VXFORM(vmaxuh, 1, 1), | |
10327 | GEN_VXFORM(vmaxuw, 1, 2), | |
8203e31b | 10328 | GEN_VXFORM_207(vmaxud, 1, 3), |
5c55ff99 BS |
10329 | GEN_VXFORM(vmaxsb, 1, 4), |
10330 | GEN_VXFORM(vmaxsh, 1, 5), | |
10331 | GEN_VXFORM(vmaxsw, 1, 6), | |
8203e31b | 10332 | GEN_VXFORM_207(vmaxsd, 1, 7), |
5c55ff99 BS |
10333 | GEN_VXFORM(vminub, 1, 8), |
10334 | GEN_VXFORM(vminuh, 1, 9), | |
10335 | GEN_VXFORM(vminuw, 1, 10), | |
8203e31b | 10336 | GEN_VXFORM_207(vminud, 1, 11), |
5c55ff99 BS |
10337 | GEN_VXFORM(vminsb, 1, 12), |
10338 | GEN_VXFORM(vminsh, 1, 13), | |
10339 | GEN_VXFORM(vminsw, 1, 14), | |
8203e31b | 10340 | GEN_VXFORM_207(vminsd, 1, 15), |
5c55ff99 BS |
10341 | GEN_VXFORM(vavgub, 1, 16), |
10342 | GEN_VXFORM(vavguh, 1, 17), | |
10343 | GEN_VXFORM(vavguw, 1, 18), | |
10344 | GEN_VXFORM(vavgsb, 1, 20), | |
10345 | GEN_VXFORM(vavgsh, 1, 21), | |
10346 | GEN_VXFORM(vavgsw, 1, 22), | |
10347 | GEN_VXFORM(vmrghb, 6, 0), | |
10348 | GEN_VXFORM(vmrghh, 6, 1), | |
10349 | GEN_VXFORM(vmrghw, 6, 2), | |
10350 | GEN_VXFORM(vmrglb, 6, 4), | |
10351 | GEN_VXFORM(vmrglh, 6, 5), | |
10352 | GEN_VXFORM(vmrglw, 6, 6), | |
e0ffe77f TM |
10353 | GEN_VXFORM_207(vmrgew, 6, 30), |
10354 | GEN_VXFORM_207(vmrgow, 6, 26), | |
5c55ff99 BS |
10355 | GEN_VXFORM(vmuloub, 4, 0), |
10356 | GEN_VXFORM(vmulouh, 4, 1), | |
953f0f58 | 10357 | GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE), |
5c55ff99 BS |
10358 | GEN_VXFORM(vmulosb, 4, 4), |
10359 | GEN_VXFORM(vmulosh, 4, 5), | |
63be0936 | 10360 | GEN_VXFORM_207(vmulosw, 4, 6), |
5c55ff99 BS |
10361 | GEN_VXFORM(vmuleub, 4, 8), |
10362 | GEN_VXFORM(vmuleuh, 4, 9), | |
63be0936 | 10363 | GEN_VXFORM_207(vmuleuw, 4, 10), |
5c55ff99 BS |
10364 | GEN_VXFORM(vmulesb, 4, 12), |
10365 | GEN_VXFORM(vmulesh, 4, 13), | |
63be0936 | 10366 | GEN_VXFORM_207(vmulesw, 4, 14), |
5c55ff99 BS |
10367 | GEN_VXFORM(vslb, 2, 4), |
10368 | GEN_VXFORM(vslh, 2, 5), | |
10369 | GEN_VXFORM(vslw, 2, 6), | |
2fdf78e6 | 10370 | GEN_VXFORM_207(vsld, 2, 23), |
5c55ff99 BS |
10371 | GEN_VXFORM(vsrb, 2, 8), |
10372 | GEN_VXFORM(vsrh, 2, 9), | |
10373 | GEN_VXFORM(vsrw, 2, 10), | |
2fdf78e6 | 10374 | GEN_VXFORM_207(vsrd, 2, 27), |
5c55ff99 BS |
10375 | GEN_VXFORM(vsrab, 2, 12), |
10376 | GEN_VXFORM(vsrah, 2, 13), | |
10377 | GEN_VXFORM(vsraw, 2, 14), | |
2fdf78e6 | 10378 | GEN_VXFORM_207(vsrad, 2, 15), |
5c55ff99 BS |
10379 | GEN_VXFORM(vslo, 6, 16), |
10380 | GEN_VXFORM(vsro, 6, 17), | |
10381 | GEN_VXFORM(vaddcuw, 0, 6), | |
10382 | GEN_VXFORM(vsubcuw, 0, 22), | |
10383 | GEN_VXFORM(vaddubs, 0, 8), | |
10384 | GEN_VXFORM(vadduhs, 0, 9), | |
10385 | GEN_VXFORM(vadduws, 0, 10), | |
10386 | GEN_VXFORM(vaddsbs, 0, 12), | |
10387 | GEN_VXFORM(vaddshs, 0, 13), | |
10388 | GEN_VXFORM(vaddsws, 0, 14), | |
e8f7b27b TM |
10389 | GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE), |
10390 | GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE), | |
5c55ff99 BS |
10391 | GEN_VXFORM(vsubuws, 0, 26), |
10392 | GEN_VXFORM(vsubsbs, 0, 28), | |
10393 | GEN_VXFORM(vsubshs, 0, 29), | |
10394 | GEN_VXFORM(vsubsws, 0, 30), | |
b41da4eb TM |
10395 | GEN_VXFORM_207(vadduqm, 0, 4), |
10396 | GEN_VXFORM_207(vaddcuq, 0, 5), | |
10397 | GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), | |
10398 | GEN_VXFORM_207(vsubuqm, 0, 20), | |
10399 | GEN_VXFORM_207(vsubcuq, 0, 21), | |
10400 | GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), | |
5c55ff99 BS |
10401 | GEN_VXFORM(vrlb, 2, 0), |
10402 | GEN_VXFORM(vrlh, 2, 1), | |
10403 | GEN_VXFORM(vrlw, 2, 2), | |
2fdf78e6 | 10404 | GEN_VXFORM_207(vrld, 2, 3), |
5c55ff99 BS |
10405 | GEN_VXFORM(vsl, 2, 7), |
10406 | GEN_VXFORM(vsr, 2, 11), | |
10407 | GEN_VXFORM(vpkuhum, 7, 0), | |
10408 | GEN_VXFORM(vpkuwum, 7, 1), | |
024215b2 | 10409 | GEN_VXFORM_207(vpkudum, 7, 17), |
5c55ff99 BS |
10410 | GEN_VXFORM(vpkuhus, 7, 2), |
10411 | GEN_VXFORM(vpkuwus, 7, 3), | |
024215b2 | 10412 | GEN_VXFORM_207(vpkudus, 7, 19), |
5c55ff99 BS |
10413 | GEN_VXFORM(vpkshus, 7, 4), |
10414 | GEN_VXFORM(vpkswus, 7, 5), | |
024215b2 | 10415 | GEN_VXFORM_207(vpksdus, 7, 21), |
5c55ff99 BS |
10416 | GEN_VXFORM(vpkshss, 7, 6), |
10417 | GEN_VXFORM(vpkswss, 7, 7), | |
024215b2 | 10418 | GEN_VXFORM_207(vpksdss, 7, 23), |
5c55ff99 BS |
10419 | GEN_VXFORM(vpkpx, 7, 12), |
10420 | GEN_VXFORM(vsum4ubs, 4, 24), | |
10421 | GEN_VXFORM(vsum4sbs, 4, 28), | |
10422 | GEN_VXFORM(vsum4shs, 4, 25), | |
10423 | GEN_VXFORM(vsum2sws, 4, 26), | |
10424 | GEN_VXFORM(vsumsws, 4, 30), | |
10425 | GEN_VXFORM(vaddfp, 5, 0), | |
10426 | GEN_VXFORM(vsubfp, 5, 1), | |
10427 | GEN_VXFORM(vmaxfp, 5, 16), | |
10428 | GEN_VXFORM(vminfp, 5, 17), | |
10429 | ||
10430 | #undef GEN_VXRFORM1 | |
10431 | #undef GEN_VXRFORM | |
10432 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
10433 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
10434 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
10435 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
10436 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
10437 | GEN_VXRFORM(vcmpequb, 3, 0) | |
10438 | GEN_VXRFORM(vcmpequh, 3, 1) | |
10439 | GEN_VXRFORM(vcmpequw, 3, 2) | |
10440 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
10441 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
10442 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
10443 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
10444 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
10445 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
6f3dab41 | 10446 | GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE) |
5c55ff99 | 10447 | GEN_VXRFORM(vcmpgefp, 3, 7) |
6f3dab41 TM |
10448 | GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE) |
10449 | GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE) | |
5c55ff99 BS |
10450 | |
10451 | #undef GEN_VXFORM_SIMM | |
10452 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
10453 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
10454 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
10455 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
10456 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
10457 | ||
10458 | #undef GEN_VXFORM_NOA | |
10459 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
10460 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
10461 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
10462 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
4430e076 | 10463 | GEN_VXFORM_207(vupkhsw, 7, 25), |
5c55ff99 BS |
10464 | GEN_VXFORM_NOA(vupklsb, 7, 10), |
10465 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
4430e076 | 10466 | GEN_VXFORM_207(vupklsw, 7, 27), |
5c55ff99 BS |
10467 | GEN_VXFORM_NOA(vupkhpx, 7, 13), |
10468 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
10469 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
10470 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 10471 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 BS |
10472 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
10473 | GEN_VXFORM_NOA(vrfim, 5, 8), | |
10474 | GEN_VXFORM_NOA(vrfin, 5, 9), | |
10475 | GEN_VXFORM_NOA(vrfip, 5, 10), | |
10476 | GEN_VXFORM_NOA(vrfiz, 5, 11), | |
10477 | ||
10478 | #undef GEN_VXFORM_UIMM | |
10479 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
10480 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
10481 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
10482 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
10483 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
10484 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
10485 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
10486 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
10487 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
10488 | ||
10489 | #undef GEN_VAFORM_PAIRED | |
10490 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
10491 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
10492 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
10493 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
10494 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
10495 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
10496 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
10497 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
10498 | ||
e13500b3 TM |
10499 | GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), |
10500 | GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207), | |
10501 | GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207), | |
10502 | GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207), | |
10503 | ||
4d82038e | 10504 | GEN_VXFORM_207(vbpermq, 6, 21), |
f1064f61 | 10505 | GEN_VXFORM_207(vgbbd, 6, 20), |
b8476fc7 TM |
10506 | GEN_VXFORM_207(vpmsumb, 4, 16), |
10507 | GEN_VXFORM_207(vpmsumh, 4, 17), | |
10508 | GEN_VXFORM_207(vpmsumw, 4, 18), | |
10509 | GEN_VXFORM_207(vpmsumd, 4, 19), | |
f293f04a | 10510 | |
557d52fa TM |
10511 | GEN_VXFORM_207(vsbox, 4, 23), |
10512 | ||
10513 | GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207), | |
10514 | GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207), | |
10515 | ||
57354f8f TM |
10516 | GEN_VXFORM_207(vshasigmaw, 1, 26), |
10517 | GEN_VXFORM_207(vshasigmad, 1, 27), | |
10518 | ||
ac174549 TM |
10519 | GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE), |
10520 | ||
fa1832d7 | 10521 | GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), |
cac7f0ba TM |
10522 | GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207), |
10523 | GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207), | |
10524 | GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207), | |
304af367 | 10525 | GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), |
ca03b467 | 10526 | GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX), |
897e61d1 | 10527 | GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX), |
304af367 | 10528 | |
9231ba9e | 10529 | GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX), |
e16a626b TM |
10530 | GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207), |
10531 | GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207), | |
fbed2478 | 10532 | GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), |
86e61ce3 | 10533 | GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), |
fbed2478 | 10534 | |
f5c0f7f9 TM |
10535 | GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207), |
10536 | GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10537 | GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10538 | #if defined(TARGET_PPC64) | |
10539 | GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10540 | GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10541 | #endif | |
10542 | ||
df020ce0 TM |
10543 | #undef GEN_XX2FORM |
10544 | #define GEN_XX2FORM(name, opc2, opc3, fl2) \ | |
10545 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ | |
10546 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) | |
10547 | ||
10548 | #undef GEN_XX3FORM | |
10549 | #define GEN_XX3FORM(name, opc2, opc3, fl2) \ | |
10550 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ | |
10551 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ | |
10552 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ | |
10553 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) | |
10554 | ||
354a6dec TM |
10555 | #undef GEN_XX3_RC_FORM |
10556 | #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \ | |
10557 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10558 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10559 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10560 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10561 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \ | |
10562 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \ | |
10563 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \ | |
10564 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2) | |
10565 | ||
cd73f2c9 TM |
10566 | #undef GEN_XX3FORM_DM |
10567 | #define GEN_XX3FORM_DM(name, opc2, opc3) \ | |
10568 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10569 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10570 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10571 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10572 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10573 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10574 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10575 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10576 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10577 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10578 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10579 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10580 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
10581 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
10582 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
10583 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX) | |
10584 | ||
df020ce0 TM |
10585 | GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX), |
10586 | GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX), | |
10587 | GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX), | |
10588 | GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX), | |
10589 | ||
be574920 TM |
10590 | GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), |
10591 | GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), | |
10592 | GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX), | |
10593 | GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX), | |
10594 | GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX), | |
10595 | GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX), | |
10596 | GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX), | |
10597 | GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), | |
79ca8a6a | 10598 | |
ee6e02c0 TM |
10599 | GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX), |
10600 | GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX), | |
5e591d88 | 10601 | GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX), |
4b98eeef | 10602 | GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX), |
2009227f | 10603 | GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX), |
d32404fe | 10604 | GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX), |
d3f9df8f | 10605 | GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX), |
bc80838f | 10606 | GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX), |
5cb151ac | 10607 | GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX), |
595c6eef TM |
10608 | GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX), |
10609 | GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX), | |
10610 | GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX), | |
10611 | GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX), | |
10612 | GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX), | |
10613 | GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX), | |
10614 | GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX), | |
10615 | GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX), | |
4f17e9c7 TM |
10616 | GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX), |
10617 | GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX), | |
959e9c9d TM |
10618 | GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX), |
10619 | GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX), | |
ed8ac568 | 10620 | GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), |
7ee19fb9 | 10621 | GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), |
ed8ac568 | 10622 | GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX), |
7ee19fb9 | 10623 | GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207), |
5177d2ca TM |
10624 | GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX), |
10625 | GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX), | |
10626 | GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX), | |
10627 | GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX), | |
10628 | GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX), | |
10629 | GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX), | |
88e33d08 TM |
10630 | GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX), |
10631 | GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX), | |
10632 | GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX), | |
10633 | GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), | |
10634 | GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), | |
ee6e02c0 | 10635 | |
3fd0aadf TM |
10636 | GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), |
10637 | GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), | |
ab9408a2 | 10638 | GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), |
b24d0b47 | 10639 | GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207), |
2c0c52ae | 10640 | GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), |
3d1140bf | 10641 | GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207), |
cea4e574 | 10642 | GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), |
968e76bc | 10643 | GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), |
f53f81e0 TM |
10644 | GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207), |
10645 | GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207), | |
10646 | GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207), | |
10647 | GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207), | |
10648 | GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207), | |
10649 | GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207), | |
10650 | GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207), | |
10651 | GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207), | |
74698350 TM |
10652 | GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207), |
10653 | GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207), | |
3fd0aadf | 10654 | |
ee6e02c0 TM |
10655 | GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), |
10656 | GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), | |
5e591d88 | 10657 | GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX), |
4b98eeef | 10658 | GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX), |
2009227f | 10659 | GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX), |
d32404fe | 10660 | GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), |
d3f9df8f | 10661 | GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX), |
bc80838f | 10662 | GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX), |
5cb151ac | 10663 | GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX), |
595c6eef TM |
10664 | GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX), |
10665 | GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX), | |
10666 | GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX), | |
10667 | GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX), | |
10668 | GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX), | |
10669 | GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX), | |
10670 | GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX), | |
10671 | GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX), | |
959e9c9d TM |
10672 | GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX), |
10673 | GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX), | |
354a6dec TM |
10674 | GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX), |
10675 | GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX), | |
10676 | GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX), | |
ed8ac568 | 10677 | GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX), |
5177d2ca TM |
10678 | GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX), |
10679 | GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX), | |
10680 | GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX), | |
10681 | GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX), | |
10682 | GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX), | |
10683 | GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX), | |
10684 | GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX), | |
10685 | GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX), | |
88e33d08 TM |
10686 | GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX), |
10687 | GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX), | |
10688 | GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX), | |
10689 | GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX), | |
10690 | GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX), | |
ee6e02c0 TM |
10691 | |
10692 | GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX), | |
10693 | GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX), | |
5e591d88 | 10694 | GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX), |
4b98eeef | 10695 | GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX), |
2009227f | 10696 | GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX), |
d32404fe | 10697 | GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX), |
d3f9df8f | 10698 | GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX), |
bc80838f | 10699 | GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX), |
5cb151ac | 10700 | GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX), |
595c6eef TM |
10701 | GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX), |
10702 | GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX), | |
10703 | GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX), | |
10704 | GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX), | |
10705 | GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX), | |
10706 | GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX), | |
10707 | GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX), | |
10708 | GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX), | |
959e9c9d TM |
10709 | GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX), |
10710 | GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX), | |
354a6dec TM |
10711 | GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX), |
10712 | GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX), | |
10713 | GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX), | |
ed8ac568 | 10714 | GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX), |
5177d2ca TM |
10715 | GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX), |
10716 | GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX), | |
10717 | GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX), | |
10718 | GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX), | |
10719 | GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX), | |
10720 | GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX), | |
10721 | GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX), | |
10722 | GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX), | |
88e33d08 TM |
10723 | GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX), |
10724 | GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX), | |
10725 | GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX), | |
10726 | GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX), | |
10727 | GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX), | |
ee6e02c0 | 10728 | |
79ca8a6a TM |
10729 | #undef VSX_LOGICAL |
10730 | #define VSX_LOGICAL(name, opc2, opc3, fl2) \ | |
10731 | GEN_XX3FORM(name, opc2, opc3, fl2) | |
10732 | ||
10733 | VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX), | |
10734 | VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX), | |
10735 | VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX), | |
10736 | VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), | |
10737 | VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), | |
67a33f37 TM |
10738 | VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207), |
10739 | VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207), | |
10740 | VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207), | |
ce577d2e TM |
10741 | GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), |
10742 | GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), | |
76c15fe0 | 10743 | GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), |
acc42968 | 10744 | GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), |
79ca8a6a | 10745 | |
551e3ef7 TM |
10746 | #define GEN_XXSEL_ROW(opc3) \ |
10747 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10748 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10749 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10750 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10751 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10752 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10753 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10754 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10755 | ||
10756 | GEN_XXSEL_ROW(0x00) | |
10757 | GEN_XXSEL_ROW(0x01) | |
10758 | GEN_XXSEL_ROW(0x02) | |
10759 | GEN_XXSEL_ROW(0x03) | |
10760 | GEN_XXSEL_ROW(0x04) | |
10761 | GEN_XXSEL_ROW(0x05) | |
10762 | GEN_XXSEL_ROW(0x06) | |
10763 | GEN_XXSEL_ROW(0x07) | |
10764 | GEN_XXSEL_ROW(0x08) | |
10765 | GEN_XXSEL_ROW(0x09) | |
10766 | GEN_XXSEL_ROW(0x0A) | |
10767 | GEN_XXSEL_ROW(0x0B) | |
10768 | GEN_XXSEL_ROW(0x0C) | |
10769 | GEN_XXSEL_ROW(0x0D) | |
10770 | GEN_XXSEL_ROW(0x0E) | |
10771 | GEN_XXSEL_ROW(0x0F) | |
10772 | GEN_XXSEL_ROW(0x10) | |
10773 | GEN_XXSEL_ROW(0x11) | |
10774 | GEN_XXSEL_ROW(0x12) | |
10775 | GEN_XXSEL_ROW(0x13) | |
10776 | GEN_XXSEL_ROW(0x14) | |
10777 | GEN_XXSEL_ROW(0x15) | |
10778 | GEN_XXSEL_ROW(0x16) | |
10779 | GEN_XXSEL_ROW(0x17) | |
10780 | GEN_XXSEL_ROW(0x18) | |
10781 | GEN_XXSEL_ROW(0x19) | |
10782 | GEN_XXSEL_ROW(0x1A) | |
10783 | GEN_XXSEL_ROW(0x1B) | |
10784 | GEN_XXSEL_ROW(0x1C) | |
10785 | GEN_XXSEL_ROW(0x1D) | |
10786 | GEN_XXSEL_ROW(0x1E) | |
10787 | GEN_XXSEL_ROW(0x1F) | |
10788 | ||
cd73f2c9 TM |
10789 | GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), |
10790 | ||
275e35c6 TM |
10791 | #undef GEN_DFP_T_A_B_Rc |
10792 | #undef GEN_DFP_BF_A_B | |
10793 | #undef GEN_DFP_BF_A_DCM | |
10794 | #undef GEN_DFP_T_B_U32_U32_Rc | |
10795 | #undef GEN_DFP_T_A_B_I32_Rc | |
10796 | #undef GEN_DFP_T_B_Rc | |
10797 | #undef GEN_DFP_T_FPR_I32_Rc | |
10798 | ||
10799 | #define _GEN_DFP_LONG(name, op1, op2, mask) \ | |
10800 | GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP) | |
10801 | ||
10802 | #define _GEN_DFP_LONGx2(name, op1, op2, mask) \ | |
10803 | GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10804 | GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) | |
10805 | ||
10806 | #define _GEN_DFP_LONGx4(name, op1, op2, mask) \ | |
10807 | GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10808 | GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10809 | GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10810 | GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) | |
10811 | ||
10812 | #define _GEN_DFP_QUAD(name, op1, op2, mask) \ | |
10813 | GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP) | |
10814 | ||
10815 | #define _GEN_DFP_QUADx2(name, op1, op2, mask) \ | |
10816 | GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10817 | GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) | |
10818 | ||
10819 | #define _GEN_DFP_QUADx4(name, op1, op2, mask) \ | |
10820 | GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10821 | GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10822 | GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10823 | GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) | |
10824 | ||
10825 | #define GEN_DFP_T_A_B_Rc(name, op1, op2) \ | |
10826 | _GEN_DFP_LONG(name, op1, op2, 0x00000000) | |
10827 | ||
10828 | #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \ | |
10829 | _GEN_DFP_QUAD(name, op1, op2, 0x00210800) | |
10830 | ||
10831 | #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \ | |
10832 | _GEN_DFP_QUAD(name, op1, op2, 0x00200800) | |
10833 | ||
10834 | #define GEN_DFP_T_B_Rc(name, op1, op2) \ | |
10835 | _GEN_DFP_LONG(name, op1, op2, 0x001F0000) | |
10836 | ||
10837 | #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \ | |
10838 | _GEN_DFP_QUAD(name, op1, op2, 0x003F0800) | |
10839 | ||
10840 | #define GEN_DFP_Tp_B_Rc(name, op1, op2) \ | |
10841 | _GEN_DFP_QUAD(name, op1, op2, 0x003F0000) | |
10842 | ||
10843 | #define GEN_DFP_T_Bp_Rc(name, op1, op2) \ | |
10844 | _GEN_DFP_QUAD(name, op1, op2, 0x001F0800) | |
10845 | ||
10846 | #define GEN_DFP_BF_A_B(name, op1, op2) \ | |
10847 | _GEN_DFP_LONG(name, op1, op2, 0x00000001) | |
10848 | ||
10849 | #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \ | |
10850 | _GEN_DFP_QUAD(name, op1, op2, 0x00610801) | |
10851 | ||
10852 | #define GEN_DFP_BF_A_Bp(name, op1, op2) \ | |
10853 | _GEN_DFP_QUAD(name, op1, op2, 0x00600801) | |
10854 | ||
10855 | #define GEN_DFP_BF_A_DCM(name, op1, op2) \ | |
10856 | _GEN_DFP_LONGx2(name, op1, op2, 0x00600001) | |
10857 | ||
10858 | #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \ | |
10859 | _GEN_DFP_QUADx2(name, op1, op2, 0x00610001) | |
10860 | ||
10861 | #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \ | |
10862 | _GEN_DFP_LONGx4(name, op1, op2, 0x00000000) | |
10863 | ||
10864 | #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \ | |
10865 | _GEN_DFP_QUADx4(name, op1, op2, 0x02010800) | |
10866 | ||
10867 | #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \ | |
10868 | _GEN_DFP_QUADx4(name, op1, op2, 0x02000800) | |
10869 | ||
10870 | #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \ | |
10871 | _GEN_DFP_LONGx4(name, op1, op2, 0x00000000) | |
10872 | ||
10873 | #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \ | |
10874 | _GEN_DFP_QUADx4(name, op1, op2, 0x00200800) | |
10875 | ||
10876 | #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \ | |
10877 | _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000) | |
10878 | ||
10879 | #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \ | |
10880 | _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800) | |
10881 | ||
10882 | #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \ | |
10883 | _GEN_DFP_LONG(name, op1, op2, 0x00070000) | |
10884 | ||
10885 | #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \ | |
10886 | _GEN_DFP_QUAD(name, op1, op2, 0x00270800) | |
10887 | ||
10888 | #define GEN_DFP_S_T_B_Rc(name, op1, op2) \ | |
10889 | _GEN_DFP_LONG(name, op1, op2, 0x000F0000) | |
10890 | ||
10891 | #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \ | |
10892 | _GEN_DFP_QUAD(name, op1, op2, 0x002F0800) | |
10893 | ||
10894 | #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \ | |
10895 | _GEN_DFP_LONGx2(name, op1, op2, 0x00000000) | |
10896 | ||
10897 | #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \ | |
10898 | _GEN_DFP_QUADx2(name, op1, op2, 0x00210000) | |
10899 | ||
a9d7ba03 TM |
10900 | GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00), |
10901 | GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00), | |
2128f8a5 TM |
10902 | GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10), |
10903 | GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10), | |
8de6a1cc TM |
10904 | GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01), |
10905 | GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01), | |
9024ff40 TM |
10906 | GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11), |
10907 | GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11), | |
5833505b TM |
10908 | GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14), |
10909 | GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14), | |
10910 | GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04), | |
10911 | GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04), | |
e601c1ee TM |
10912 | GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06), |
10913 | GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06), | |
1bf9c0e1 TM |
10914 | GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07), |
10915 | GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07), | |
f3d2b0bc TM |
10916 | GEN_DFP_BF_A_B(dtstex, 0x02, 0x05), |
10917 | GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05), | |
f6022a76 TM |
10918 | GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15), |
10919 | GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15), | |
5826ebe2 TM |
10920 | GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02), |
10921 | GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02), | |
10922 | GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00), | |
10923 | GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00), | |
512918aa TM |
10924 | GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01), |
10925 | GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01), | |
97c0d930 TM |
10926 | GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03), |
10927 | GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03), | |
10928 | GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07), | |
10929 | GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07), | |
290d9ee5 TM |
10930 | GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08), |
10931 | GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08), | |
ca603eb4 TM |
10932 | GEN_DFP_T_B_Rc(drsp, 0x02, 0x18), |
10933 | GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18), | |
f1214193 TM |
10934 | GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19), |
10935 | GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19), | |
bea0dd79 TM |
10936 | GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09), |
10937 | GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09), | |
7796676f TM |
10938 | GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a), |
10939 | GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a), | |
013c3ac0 TM |
10940 | GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a), |
10941 | GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a), | |
e8a48460 TM |
10942 | GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b), |
10943 | GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b), | |
297666eb TM |
10944 | GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b), |
10945 | GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b), | |
804e654a TM |
10946 | GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02), |
10947 | GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02), | |
10948 | GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03), | |
10949 | GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03), | |
10950 | ||
5c55ff99 | 10951 | #undef GEN_SPE |
70560da7 FC |
10952 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
10953 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) | |
10954 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10955 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10956 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10957 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10958 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
10959 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
10960 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
10961 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), | |
10962 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), | |
10963 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
10964 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10965 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10966 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10967 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
10968 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
10969 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), | |
10970 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
10971 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10972 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10973 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10974 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10975 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10976 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
10977 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
10978 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10979 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10980 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
10981 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
10982 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), | |
10983 | ||
10984 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10985 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
10986 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10987 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10988 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10989 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10990 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10991 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10992 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10993 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10994 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10995 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10996 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10997 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10998 | ||
10999 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
11000 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
11001 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11002 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
11003 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
11004 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), | |
11005 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11006 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11007 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11008 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
11009 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11010 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11011 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
11012 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
11013 | ||
11014 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
11015 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11016 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), | |
11017 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
11018 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
11019 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11020 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
11021 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), | |
11022 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11023 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11024 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11025 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11026 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
11027 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
11028 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
11029 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
5c55ff99 BS |
11030 | |
11031 | #undef GEN_SPEOP_LDST | |
11032 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
11033 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
11034 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
11035 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
11036 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
11037 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
11038 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
11039 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
11040 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
11041 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
11042 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
11043 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
11044 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
11045 | ||
11046 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
11047 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
11048 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
11049 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
11050 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
11051 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
11052 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
11053 | }; | |
11054 | ||
0411a972 | 11055 | #include "helper_regs.h" |
a1389542 | 11056 | #include "translate_init.c" |
79aceca5 | 11057 | |
9a64fbe4 | 11058 | /*****************************************************************************/ |
3fc6c082 | 11059 | /* Misc PowerPC helpers */ |
878096ee AF |
11060 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
11061 | int flags) | |
79aceca5 | 11062 | { |
3fc6c082 FB |
11063 | #define RGPL 4 |
11064 | #define RFPL 4 | |
3fc6c082 | 11065 | |
878096ee AF |
11066 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
11067 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
11068 | int i; |
11069 | ||
90e189ec | 11070 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9a78eead | 11071 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
da91a00f | 11072 | env->nip, env->lr, env->ctr, cpu_read_xer(env)); |
90e189ec BS |
11073 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
11074 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
11075 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 11076 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 11077 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 11078 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 11079 | " DECR %08" PRIu32 |
76a66253 JM |
11080 | #endif |
11081 | "\n", | |
077fc206 | 11082 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
11083 | #if !defined(CONFIG_USER_ONLY) |
11084 | , cpu_ppc_load_decr(env) | |
11085 | #endif | |
11086 | ); | |
077fc206 | 11087 | #endif |
76a66253 | 11088 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
11089 | if ((i & (RGPL - 1)) == 0) |
11090 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 11091 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 11092 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 11093 | cpu_fprintf(f, "\n"); |
76a66253 | 11094 | } |
3fc6c082 | 11095 | cpu_fprintf(f, "CR "); |
76a66253 | 11096 | for (i = 0; i < 8; i++) |
7fe48483 FB |
11097 | cpu_fprintf(f, "%01x", env->crf[i]); |
11098 | cpu_fprintf(f, " ["); | |
76a66253 JM |
11099 | for (i = 0; i < 8; i++) { |
11100 | char a = '-'; | |
11101 | if (env->crf[i] & 0x08) | |
11102 | a = 'L'; | |
11103 | else if (env->crf[i] & 0x04) | |
11104 | a = 'G'; | |
11105 | else if (env->crf[i] & 0x02) | |
11106 | a = 'E'; | |
7fe48483 | 11107 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 11108 | } |
90e189ec BS |
11109 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
11110 | env->reserve_addr); | |
3fc6c082 FB |
11111 | for (i = 0; i < 32; i++) { |
11112 | if ((i & (RFPL - 1)) == 0) | |
11113 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 11114 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 11115 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 11116 | cpu_fprintf(f, "\n"); |
79aceca5 | 11117 | } |
30304420 | 11118 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 11119 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
11120 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
11121 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
11122 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
11123 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
11124 | ||
11125 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
11126 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
11127 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
11128 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
11129 | ||
11130 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
11131 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
11132 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
11133 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
11134 | ||
11135 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
11136 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
11137 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
11138 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
11139 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
11140 | ||
11141 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
11142 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
11143 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
11144 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
11145 | ||
11146 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
11147 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
11148 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
11149 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
11150 | ||
11151 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
11152 | " EPR " TARGET_FMT_lx "\n", | |
11153 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
11154 | env->spr[SPR_BOOKE_EPR]); | |
11155 | ||
11156 | /* FSL-specific */ | |
11157 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
11158 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
11159 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
11160 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
11161 | ||
11162 | /* | |
11163 | * IVORs are left out as they are large and do not change often -- | |
11164 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
11165 | */ | |
11166 | } | |
11167 | ||
697ab892 DG |
11168 | #if defined(TARGET_PPC64) |
11169 | if (env->flags & POWERPC_FLAG_CFAR) { | |
11170 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
11171 | } | |
11172 | #endif | |
11173 | ||
90dc8812 SW |
11174 | switch (env->mmu_model) { |
11175 | case POWERPC_MMU_32B: | |
11176 | case POWERPC_MMU_601: | |
11177 | case POWERPC_MMU_SOFT_6xx: | |
11178 | case POWERPC_MMU_SOFT_74xx: | |
11179 | #if defined(TARGET_PPC64) | |
90dc8812 | 11180 | case POWERPC_MMU_64B: |
ca480de6 AB |
11181 | case POWERPC_MMU_2_06: |
11182 | case POWERPC_MMU_2_06a: | |
11183 | case POWERPC_MMU_2_06d: | |
90dc8812 | 11184 | #endif |
ca480de6 AB |
11185 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx |
11186 | " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], | |
11187 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); | |
90dc8812 | 11188 | break; |
01662f3e | 11189 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
11190 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
11191 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
11192 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
11193 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
11194 | ||
11195 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
11196 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
11197 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
11198 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
11199 | ||
11200 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
11201 | " TLB1CFG " TARGET_FMT_lx "\n", | |
11202 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
11203 | env->spr[SPR_BOOKE_TLB1CFG]); | |
11204 | break; | |
11205 | default: | |
11206 | break; | |
11207 | } | |
f2e63a42 | 11208 | #endif |
79aceca5 | 11209 | |
3fc6c082 FB |
11210 | #undef RGPL |
11211 | #undef RFPL | |
79aceca5 FB |
11212 | } |
11213 | ||
878096ee AF |
11214 | void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, |
11215 | fprintf_function cpu_fprintf, int flags) | |
76a66253 JM |
11216 | { |
11217 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 11218 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 11219 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
11220 | int op1, op2, op3; |
11221 | ||
878096ee | 11222 | t1 = cpu->env.opcodes; |
76a66253 JM |
11223 | for (op1 = 0; op1 < 64; op1++) { |
11224 | handler = t1[op1]; | |
11225 | if (is_indirect_opcode(handler)) { | |
11226 | t2 = ind_table(handler); | |
11227 | for (op2 = 0; op2 < 32; op2++) { | |
11228 | handler = t2[op2]; | |
11229 | if (is_indirect_opcode(handler)) { | |
11230 | t3 = ind_table(handler); | |
11231 | for (op3 = 0; op3 < 32; op3++) { | |
11232 | handler = t3[op3]; | |
11233 | if (handler->count == 0) | |
11234 | continue; | |
11235 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 11236 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
11237 | op1, op2, op3, op1, (op3 << 5) | op2, |
11238 | handler->oname, | |
11239 | handler->count, handler->count); | |
11240 | } | |
11241 | } else { | |
11242 | if (handler->count == 0) | |
11243 | continue; | |
11244 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 11245 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
11246 | op1, op2, op1, op2, handler->oname, |
11247 | handler->count, handler->count); | |
11248 | } | |
11249 | } | |
11250 | } else { | |
11251 | if (handler->count == 0) | |
11252 | continue; | |
0bfcd599 BS |
11253 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
11254 | " %" PRId64 "\n", | |
76a66253 JM |
11255 | op1, op1, handler->oname, |
11256 | handler->count, handler->count); | |
11257 | } | |
11258 | } | |
11259 | #endif | |
11260 | } | |
11261 | ||
9a64fbe4 | 11262 | /*****************************************************************************/ |
213fe1f5 | 11263 | static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, |
636aa200 | 11264 | TranslationBlock *tb, |
213fe1f5 | 11265 | bool search_pc) |
79aceca5 | 11266 | { |
ed2803da | 11267 | CPUState *cs = CPU(cpu); |
213fe1f5 | 11268 | CPUPPCState *env = &cpu->env; |
9fddaa0c | 11269 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 11270 | opc_handler_t **table, *handler; |
0fa85d43 | 11271 | target_ulong pc_start; |
79aceca5 | 11272 | uint16_t *gen_opc_end; |
a1d1bb31 | 11273 | CPUBreakpoint *bp; |
79aceca5 | 11274 | int j, lj = -1; |
2e70f6ef PB |
11275 | int num_insns; |
11276 | int max_insns; | |
79aceca5 FB |
11277 | |
11278 | pc_start = tb->pc; | |
92414b31 | 11279 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 11280 | ctx.nip = pc_start; |
79aceca5 | 11281 | ctx.tb = tb; |
e1833e1f | 11282 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 11283 | ctx.spr_cb = env->spr_cb; |
76db3ba4 | 11284 | ctx.mem_idx = env->mmu_idx; |
7d08d856 AJ |
11285 | ctx.insns_flags = env->insns_flags; |
11286 | ctx.insns_flags2 = env->insns_flags2; | |
76db3ba4 AJ |
11287 | ctx.access_type = -1; |
11288 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
e22c357b | 11289 | ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; |
d9bce9d9 | 11290 | #if defined(TARGET_PPC64) |
e42a61f1 | 11291 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 11292 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 11293 | #endif |
3cc62370 | 11294 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 11295 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
11296 | ctx.spe_enabled = msr_spe; |
11297 | else | |
11298 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
11299 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
11300 | ctx.altivec_enabled = msr_vr; | |
11301 | else | |
11302 | ctx.altivec_enabled = 0; | |
1f29871c TM |
11303 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
11304 | ctx.vsx_enabled = msr_vsx; | |
11305 | } else { | |
11306 | ctx.vsx_enabled = 0; | |
11307 | } | |
d26bfc9a | 11308 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 11309 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 11310 | else |
8cbcb4fa | 11311 | ctx.singlestep_enabled = 0; |
d26bfc9a | 11312 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa | 11313 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
ed2803da | 11314 | if (unlikely(cs->singlestep_enabled)) { |
8cbcb4fa | 11315 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
ed2803da | 11316 | } |
3fc6c082 | 11317 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
11318 | /* Single step trace mode */ |
11319 | msr_se = 1; | |
11320 | #endif | |
2e70f6ef PB |
11321 | num_insns = 0; |
11322 | max_insns = tb->cflags & CF_COUNT_MASK; | |
11323 | if (max_insns == 0) | |
11324 | max_insns = CF_COUNT_MASK; | |
11325 | ||
806f352d | 11326 | gen_tb_start(); |
3de31797 | 11327 | tcg_clear_temp_count(); |
9a64fbe4 | 11328 | /* Set env in case of segfault during code fetch */ |
efd7f486 EV |
11329 | while (ctx.exception == POWERPC_EXCP_NONE |
11330 | && tcg_ctx.gen_opc_ptr < gen_opc_end) { | |
f0c3c505 AF |
11331 | if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |
11332 | QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { | |
a1d1bb31 | 11333 | if (bp->pc == ctx.nip) { |
e06fcd75 | 11334 | gen_debug_exception(ctxp); |
ea4e754f FB |
11335 | break; |
11336 | } | |
11337 | } | |
11338 | } | |
76a66253 | 11339 | if (unlikely(search_pc)) { |
92414b31 | 11340 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
79aceca5 FB |
11341 | if (lj < j) { |
11342 | lj++; | |
11343 | while (lj < j) | |
ab1103de | 11344 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
79aceca5 | 11345 | } |
25983cad | 11346 | tcg_ctx.gen_opc_pc[lj] = ctx.nip; |
ab1103de | 11347 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 11348 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
79aceca5 | 11349 | } |
d12d51d5 | 11350 | LOG_DISAS("----------------\n"); |
90e189ec | 11351 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 11352 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
2e70f6ef PB |
11353 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
11354 | gen_io_start(); | |
e22c357b | 11355 | if (unlikely(need_byteswap(&ctx))) { |
2f5a189c | 11356 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 11357 | } else { |
2f5a189c | 11358 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 11359 | } |
d12d51d5 | 11360 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 11361 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
476b6d16 | 11362 | opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); |
fdefe51c | 11363 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
731c54f8 | 11364 | tcg_gen_debug_insn_start(ctx.nip); |
fdefe51c | 11365 | } |
046d6672 | 11366 | ctx.nip += 4; |
3fc6c082 | 11367 | table = env->opcodes; |
2e70f6ef | 11368 | num_insns++; |
79aceca5 FB |
11369 | handler = table[opc1(ctx.opcode)]; |
11370 | if (is_indirect_opcode(handler)) { | |
11371 | table = ind_table(handler); | |
11372 | handler = table[opc2(ctx.opcode)]; | |
11373 | if (is_indirect_opcode(handler)) { | |
11374 | table = ind_table(handler); | |
11375 | handler = table[opc3(ctx.opcode)]; | |
11376 | } | |
11377 | } | |
11378 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 11379 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
11380 | if (qemu_log_enabled()) { |
11381 | qemu_log("invalid/unsupported opcode: " | |
90e189ec BS |
11382 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
11383 | opc1(ctx.opcode), opc2(ctx.opcode), | |
11384 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa | 11385 | } |
76a66253 | 11386 | } else { |
70560da7 FC |
11387 | uint32_t inval; |
11388 | ||
11389 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
11390 | inval = handler->inval2; | |
11391 | } else { | |
11392 | inval = handler->inval1; | |
11393 | } | |
11394 | ||
11395 | if (unlikely((ctx.opcode & inval) != 0)) { | |
93fcfe39 AL |
11396 | if (qemu_log_enabled()) { |
11397 | qemu_log("invalid bits: %08x for opcode: " | |
90e189ec | 11398 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
70560da7 | 11399 | ctx.opcode & inval, opc1(ctx.opcode), |
90e189ec BS |
11400 | opc2(ctx.opcode), opc3(ctx.opcode), |
11401 | ctx.opcode, ctx.nip - 4); | |
76a66253 | 11402 | } |
e06fcd75 | 11403 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 11404 | break; |
79aceca5 | 11405 | } |
79aceca5 | 11406 | } |
4b3686fa | 11407 | (*(handler->handler))(&ctx); |
76a66253 JM |
11408 | #if defined(DO_PPC_STATISTICS) |
11409 | handler->count++; | |
11410 | #endif | |
9a64fbe4 | 11411 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
11412 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
11413 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
11414 | ctx.exception != POWERPC_SYSCALL && | |
11415 | ctx.exception != POWERPC_EXCP_TRAP && | |
11416 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 11417 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 11418 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
ed2803da | 11419 | (cs->singlestep_enabled) || |
1b530a6d | 11420 | singlestep || |
2e70f6ef | 11421 | num_insns >= max_insns)) { |
d26bfc9a JM |
11422 | /* if we reach a page boundary or are single stepping, stop |
11423 | * generation | |
11424 | */ | |
8dd4983c | 11425 | break; |
76a66253 | 11426 | } |
3de31797 AG |
11427 | if (tcg_check_temp_count()) { |
11428 | fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n", | |
11429 | opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), | |
11430 | ctx.opcode); | |
11431 | exit(1); | |
11432 | } | |
3fc6c082 | 11433 | } |
2e70f6ef PB |
11434 | if (tb->cflags & CF_LAST_IO) |
11435 | gen_io_end(); | |
e1833e1f | 11436 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 11437 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 11438 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
ed2803da | 11439 | if (unlikely(cs->singlestep_enabled)) { |
e06fcd75 | 11440 | gen_debug_exception(ctxp); |
8cbcb4fa | 11441 | } |
76a66253 | 11442 | /* Generate the return instruction */ |
57fec1fe | 11443 | tcg_gen_exit_tb(0); |
9a64fbe4 | 11444 | } |
806f352d | 11445 | gen_tb_end(tb, num_insns); |
efd7f486 | 11446 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
76a66253 | 11447 | if (unlikely(search_pc)) { |
92414b31 | 11448 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
9a64fbe4 FB |
11449 | lj++; |
11450 | while (lj <= j) | |
ab1103de | 11451 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
9a64fbe4 | 11452 | } else { |
046d6672 | 11453 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 11454 | tb->icount = num_insns; |
9a64fbe4 | 11455 | } |
d9bce9d9 | 11456 | #if defined(DEBUG_DISAS) |
8fec2b8c | 11457 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 11458 | int flags; |
237c0af0 | 11459 | flags = env->bfd_mach; |
76db3ba4 | 11460 | flags |= ctx.le_mode << 16; |
93fcfe39 | 11461 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
f4359b9f | 11462 | log_target_disas(env, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 11463 | qemu_log("\n"); |
9fddaa0c | 11464 | } |
79aceca5 | 11465 | #endif |
79aceca5 FB |
11466 | } |
11467 | ||
1328c2bf | 11468 | void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 11469 | { |
213fe1f5 | 11470 | gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false); |
79aceca5 FB |
11471 | } |
11472 | ||
1328c2bf | 11473 | void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 11474 | { |
213fe1f5 | 11475 | gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true); |
79aceca5 | 11476 | } |
d2856f1a | 11477 | |
1328c2bf | 11478 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 11479 | { |
25983cad | 11480 | env->nip = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 11481 | } |