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Commit | Line | Data |
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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | ||
79aceca5 | 26 | #include "cpu.h" |
c6a1c22b | 27 | #include "exec-all.h" |
79aceca5 | 28 | #include "disas.h" |
57fec1fe | 29 | #include "tcg-op.h" |
ca10f867 | 30 | #include "qemu-common.h" |
0cfe11ea | 31 | #include "host-utils.h" |
79aceca5 | 32 | |
a7812ae4 PB |
33 | #include "helper.h" |
34 | #define GEN_HELPER 1 | |
35 | #include "helper.h" | |
36 | ||
8cbcb4fa AJ |
37 | #define CPU_SINGLE_STEP 0x1 |
38 | #define CPU_BRANCH_STEP 0x2 | |
39 | #define GDBSTUB_SINGLE_STEP 0x4 | |
40 | ||
a750fc0b | 41 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 42 | //#define PPC_DEBUG_DISAS |
76a66253 | 43 | //#define DO_PPC_STATISTICS |
79aceca5 | 44 | |
d12d51d5 | 45 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 46 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
47 | #else |
48 | # define LOG_DISAS(...) do { } while (0) | |
49 | #endif | |
a750fc0b JM |
50 | /*****************************************************************************/ |
51 | /* Code translation helpers */ | |
c53be334 | 52 | |
f78fb44e | 53 | /* global register indexes */ |
a7812ae4 | 54 | static TCGv_ptr cpu_env; |
1d542695 | 55 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
f78fb44e | 56 | #if !defined(TARGET_PPC64) |
1d542695 | 57 | + 10*4 + 22*5 /* SPE GPRh */ |
f78fb44e | 58 | #endif |
a5e26afa | 59 | + 10*4 + 22*5 /* FPR */ |
47e4661c AJ |
60 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
61 | + 8*5 /* CRF */]; | |
f78fb44e AJ |
62 | static TCGv cpu_gpr[32]; |
63 | #if !defined(TARGET_PPC64) | |
64 | static TCGv cpu_gprh[32]; | |
65 | #endif | |
a7812ae4 PB |
66 | static TCGv_i64 cpu_fpr[32]; |
67 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
68 | static TCGv_i32 cpu_crf[8]; | |
bd568f18 | 69 | static TCGv cpu_nip; |
6527f6ea | 70 | static TCGv cpu_msr; |
cfdcd37a AJ |
71 | static TCGv cpu_ctr; |
72 | static TCGv cpu_lr; | |
3d7b417e | 73 | static TCGv cpu_xer; |
cf360a32 | 74 | static TCGv cpu_reserve; |
a7812ae4 | 75 | static TCGv_i32 cpu_fpscr; |
a7859e89 | 76 | static TCGv_i32 cpu_access_type; |
f78fb44e | 77 | |
2e70f6ef PB |
78 | #include "gen-icount.h" |
79 | ||
80 | void ppc_translate_init(void) | |
81 | { | |
f78fb44e AJ |
82 | int i; |
83 | char* p; | |
2dc766da | 84 | size_t cpu_reg_names_size; |
b2437bf2 | 85 | static int done_init = 0; |
f78fb44e | 86 | |
2e70f6ef PB |
87 | if (done_init) |
88 | return; | |
f78fb44e | 89 | |
a7812ae4 | 90 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 91 | |
f78fb44e | 92 | p = cpu_reg_names; |
2dc766da | 93 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
94 | |
95 | for (i = 0; i < 8; i++) { | |
2dc766da | 96 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 PB |
97 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
98 | offsetof(CPUState, crf[i]), p); | |
47e4661c | 99 | p += 5; |
2dc766da | 100 | cpu_reg_names_size -= 5; |
47e4661c AJ |
101 | } |
102 | ||
f78fb44e | 103 | for (i = 0; i < 32; i++) { |
2dc766da | 104 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 105 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
f78fb44e AJ |
106 | offsetof(CPUState, gpr[i]), p); |
107 | p += (i < 10) ? 3 : 4; | |
2dc766da | 108 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
f78fb44e | 109 | #if !defined(TARGET_PPC64) |
2dc766da | 110 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
a7812ae4 PB |
111 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
112 | offsetof(CPUState, gprh[i]), p); | |
f78fb44e | 113 | p += (i < 10) ? 4 : 5; |
2dc766da | 114 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 115 | #endif |
1d542695 | 116 | |
2dc766da | 117 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 PB |
118 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
119 | offsetof(CPUState, fpr[i]), p); | |
ec1ac72d | 120 | p += (i < 10) ? 4 : 5; |
2dc766da | 121 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 122 | |
2dc766da | 123 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 124 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 AJ |
125 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
126 | offsetof(CPUState, avr[i].u64[0]), p); | |
127 | #else | |
a7812ae4 | 128 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
fe1e5c53 AJ |
129 | offsetof(CPUState, avr[i].u64[1]), p); |
130 | #endif | |
1d542695 | 131 | p += (i < 10) ? 6 : 7; |
2dc766da | 132 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 133 | |
2dc766da | 134 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 135 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 AJ |
136 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
137 | offsetof(CPUState, avr[i].u64[1]), p); | |
138 | #else | |
a7812ae4 | 139 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
fe1e5c53 AJ |
140 | offsetof(CPUState, avr[i].u64[0]), p); |
141 | #endif | |
1d542695 | 142 | p += (i < 10) ? 6 : 7; |
2dc766da | 143 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
f78fb44e | 144 | } |
f10dc08e | 145 | |
a7812ae4 | 146 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
bd568f18 AJ |
147 | offsetof(CPUState, nip), "nip"); |
148 | ||
6527f6ea AJ |
149 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
150 | offsetof(CPUState, msr), "msr"); | |
151 | ||
a7812ae4 | 152 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
cfdcd37a AJ |
153 | offsetof(CPUState, ctr), "ctr"); |
154 | ||
a7812ae4 | 155 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
cfdcd37a AJ |
156 | offsetof(CPUState, lr), "lr"); |
157 | ||
a7812ae4 | 158 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
3d7b417e AJ |
159 | offsetof(CPUState, xer), "xer"); |
160 | ||
cf360a32 | 161 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
18b21a2f NF |
162 | offsetof(CPUState, reserve_addr), |
163 | "reserve_addr"); | |
cf360a32 | 164 | |
a7812ae4 PB |
165 | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
166 | offsetof(CPUState, fpscr), "fpscr"); | |
e1571908 | 167 | |
a7859e89 AJ |
168 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
169 | offsetof(CPUState, access_type), "access_type"); | |
170 | ||
f10dc08e | 171 | /* register helpers */ |
a7812ae4 | 172 | #define GEN_HELPER 2 |
f10dc08e AJ |
173 | #include "helper.h" |
174 | ||
2e70f6ef PB |
175 | done_init = 1; |
176 | } | |
177 | ||
79aceca5 FB |
178 | /* internal defines */ |
179 | typedef struct DisasContext { | |
180 | struct TranslationBlock *tb; | |
0fa85d43 | 181 | target_ulong nip; |
79aceca5 | 182 | uint32_t opcode; |
9a64fbe4 | 183 | uint32_t exception; |
3cc62370 FB |
184 | /* Routine used to access memory */ |
185 | int mem_idx; | |
76db3ba4 | 186 | int access_type; |
3cc62370 | 187 | /* Translation flags */ |
76db3ba4 | 188 | int le_mode; |
d9bce9d9 JM |
189 | #if defined(TARGET_PPC64) |
190 | int sf_mode; | |
9a64fbe4 | 191 | #endif |
3cc62370 | 192 | int fpu_enabled; |
a9d9eb8f | 193 | int altivec_enabled; |
0487d6a8 | 194 | int spe_enabled; |
c227f099 | 195 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 196 | int singlestep_enabled; |
79aceca5 FB |
197 | } DisasContext; |
198 | ||
c227f099 | 199 | struct opc_handler_t { |
79aceca5 FB |
200 | /* invalid bits */ |
201 | uint32_t inval; | |
9a64fbe4 | 202 | /* instruction type */ |
0487d6a8 | 203 | uint64_t type; |
79aceca5 FB |
204 | /* handler */ |
205 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 206 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 207 | const char *oname; |
a750fc0b JM |
208 | #endif |
209 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
210 | uint64_t count; |
211 | #endif | |
3fc6c082 | 212 | }; |
79aceca5 | 213 | |
636aa200 | 214 | static inline void gen_reset_fpstatus(void) |
7c58044c JM |
215 | { |
216 | #ifdef CONFIG_SOFTFLOAT | |
a44d2ce1 | 217 | gen_helper_reset_fpstatus(); |
7c58044c JM |
218 | #endif |
219 | } | |
220 | ||
636aa200 | 221 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 222 | { |
0f2f39c2 | 223 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 224 | |
7c58044c JM |
225 | if (set_fprf != 0) { |
226 | /* This case might be optimized later */ | |
0f2f39c2 | 227 | tcg_gen_movi_i32(t0, 1); |
af12906f | 228 | gen_helper_compute_fprf(t0, arg, t0); |
a7812ae4 | 229 | if (unlikely(set_rc)) { |
0f2f39c2 | 230 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 231 | } |
af12906f | 232 | gen_helper_float_check_status(); |
7c58044c JM |
233 | } else if (unlikely(set_rc)) { |
234 | /* We always need to compute fpcc */ | |
0f2f39c2 | 235 | tcg_gen_movi_i32(t0, 0); |
af12906f | 236 | gen_helper_compute_fprf(t0, arg, t0); |
0f2f39c2 | 237 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 238 | } |
af12906f | 239 | |
0f2f39c2 | 240 | tcg_temp_free_i32(t0); |
7c58044c JM |
241 | } |
242 | ||
636aa200 | 243 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 244 | { |
76db3ba4 AJ |
245 | if (ctx->access_type != access_type) { |
246 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
247 | ctx->access_type = access_type; | |
248 | } | |
a7859e89 AJ |
249 | } |
250 | ||
636aa200 | 251 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 JM |
252 | { |
253 | #if defined(TARGET_PPC64) | |
254 | if (ctx->sf_mode) | |
bd568f18 | 255 | tcg_gen_movi_tl(cpu_nip, nip); |
d9bce9d9 JM |
256 | else |
257 | #endif | |
bd568f18 | 258 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
d9bce9d9 JM |
259 | } |
260 | ||
636aa200 | 261 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
262 | { |
263 | TCGv_i32 t0, t1; | |
264 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
265 | gen_update_nip(ctx, ctx->nip); | |
266 | } | |
267 | t0 = tcg_const_i32(excp); | |
268 | t1 = tcg_const_i32(error); | |
269 | gen_helper_raise_exception_err(t0, t1); | |
270 | tcg_temp_free_i32(t0); | |
271 | tcg_temp_free_i32(t1); | |
272 | ctx->exception = (excp); | |
273 | } | |
e1833e1f | 274 | |
636aa200 | 275 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
276 | { |
277 | TCGv_i32 t0; | |
278 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
279 | gen_update_nip(ctx, ctx->nip); | |
280 | } | |
281 | t0 = tcg_const_i32(excp); | |
282 | gen_helper_raise_exception(t0); | |
283 | tcg_temp_free_i32(t0); | |
284 | ctx->exception = (excp); | |
285 | } | |
e1833e1f | 286 | |
636aa200 | 287 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
288 | { |
289 | TCGv_i32 t0; | |
5518f3a6 BS |
290 | |
291 | if (ctx->exception != POWERPC_EXCP_BRANCH) | |
292 | gen_update_nip(ctx, ctx->nip); | |
e06fcd75 AJ |
293 | t0 = tcg_const_i32(EXCP_DEBUG); |
294 | gen_helper_raise_exception(t0); | |
295 | tcg_temp_free_i32(t0); | |
296 | } | |
9a64fbe4 | 297 | |
636aa200 | 298 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
299 | { |
300 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
301 | } | |
a9d9eb8f | 302 | |
f24e5695 | 303 | /* Stop translation */ |
636aa200 | 304 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 305 | { |
d9bce9d9 | 306 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 307 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
308 | } |
309 | ||
f24e5695 | 310 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 311 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 312 | { |
e1833e1f | 313 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
314 | } |
315 | ||
79aceca5 | 316 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
5c55ff99 | 317 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type) |
79aceca5 | 318 | |
c7697e1f | 319 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
5c55ff99 | 320 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type) |
c7697e1f | 321 | |
c227f099 | 322 | typedef struct opcode_t { |
79aceca5 | 323 | unsigned char opc1, opc2, opc3; |
1235fc06 | 324 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
325 | unsigned char pad[5]; |
326 | #else | |
327 | unsigned char pad[1]; | |
328 | #endif | |
c227f099 | 329 | opc_handler_t handler; |
b55266b5 | 330 | const char *oname; |
c227f099 | 331 | } opcode_t; |
79aceca5 | 332 | |
a750fc0b | 333 | /*****************************************************************************/ |
79aceca5 FB |
334 | /*** Instruction decoding ***/ |
335 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 336 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
337 | { \ |
338 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
339 | } | |
340 | ||
341 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 342 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 343 | { \ |
18fba28c | 344 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
345 | } |
346 | ||
347 | /* Opcode part 1 */ | |
348 | EXTRACT_HELPER(opc1, 26, 6); | |
349 | /* Opcode part 2 */ | |
350 | EXTRACT_HELPER(opc2, 1, 5); | |
351 | /* Opcode part 3 */ | |
352 | EXTRACT_HELPER(opc3, 6, 5); | |
353 | /* Update Cr0 flags */ | |
354 | EXTRACT_HELPER(Rc, 0, 1); | |
355 | /* Destination */ | |
356 | EXTRACT_HELPER(rD, 21, 5); | |
357 | /* Source */ | |
358 | EXTRACT_HELPER(rS, 21, 5); | |
359 | /* First operand */ | |
360 | EXTRACT_HELPER(rA, 16, 5); | |
361 | /* Second operand */ | |
362 | EXTRACT_HELPER(rB, 11, 5); | |
363 | /* Third operand */ | |
364 | EXTRACT_HELPER(rC, 6, 5); | |
365 | /*** Get CRn ***/ | |
366 | EXTRACT_HELPER(crfD, 23, 3); | |
367 | EXTRACT_HELPER(crfS, 18, 3); | |
368 | EXTRACT_HELPER(crbD, 21, 5); | |
369 | EXTRACT_HELPER(crbA, 16, 5); | |
370 | EXTRACT_HELPER(crbB, 11, 5); | |
371 | /* SPR / TBL */ | |
3fc6c082 | 372 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 373 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
374 | { |
375 | uint32_t sprn = _SPR(opcode); | |
376 | ||
377 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
378 | } | |
79aceca5 FB |
379 | /*** Get constants ***/ |
380 | EXTRACT_HELPER(IMM, 12, 8); | |
381 | /* 16 bits signed immediate value */ | |
382 | EXTRACT_SHELPER(SIMM, 0, 16); | |
383 | /* 16 bits unsigned immediate value */ | |
384 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
385 | /* 5 bits signed immediate value */ |
386 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
387 | /* 5 bits signed immediate value */ |
388 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
389 | /* Bit count */ |
390 | EXTRACT_HELPER(NB, 11, 5); | |
391 | /* Shift count */ | |
392 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
393 | /* Vector shift count */ |
394 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
395 | /* Mask start */ |
396 | EXTRACT_HELPER(MB, 6, 5); | |
397 | /* Mask end */ | |
398 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
399 | /* Trap operand */ |
400 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
401 | |
402 | EXTRACT_HELPER(CRM, 12, 8); | |
403 | EXTRACT_HELPER(FM, 17, 8); | |
404 | EXTRACT_HELPER(SR, 16, 4); | |
e4bb997e | 405 | EXTRACT_HELPER(FPIMM, 12, 4); |
fb0eaffc | 406 | |
79aceca5 FB |
407 | /*** Jump target decoding ***/ |
408 | /* Displacement */ | |
409 | EXTRACT_SHELPER(d, 0, 16); | |
410 | /* Immediate address */ | |
636aa200 | 411 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
412 | { |
413 | return (opcode >> 0) & 0x03FFFFFC; | |
414 | } | |
415 | ||
636aa200 | 416 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
417 | { |
418 | return (opcode >> 0) & 0xFFFC; | |
419 | } | |
420 | ||
421 | EXTRACT_HELPER(BO, 21, 5); | |
422 | EXTRACT_HELPER(BI, 16, 5); | |
423 | /* Absolute/relative address */ | |
424 | EXTRACT_HELPER(AA, 1, 1); | |
425 | /* Link */ | |
426 | EXTRACT_HELPER(LK, 0, 1); | |
427 | ||
428 | /* Create a mask between <start> and <end> bits */ | |
636aa200 | 429 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 430 | { |
76a66253 | 431 | target_ulong ret; |
79aceca5 | 432 | |
76a66253 JM |
433 | #if defined(TARGET_PPC64) |
434 | if (likely(start == 0)) { | |
6f2d8978 | 435 | ret = UINT64_MAX << (63 - end); |
76a66253 | 436 | } else if (likely(end == 63)) { |
6f2d8978 | 437 | ret = UINT64_MAX >> start; |
76a66253 JM |
438 | } |
439 | #else | |
440 | if (likely(start == 0)) { | |
6f2d8978 | 441 | ret = UINT32_MAX << (31 - end); |
76a66253 | 442 | } else if (likely(end == 31)) { |
6f2d8978 | 443 | ret = UINT32_MAX >> start; |
76a66253 JM |
444 | } |
445 | #endif | |
446 | else { | |
447 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
448 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
449 | if (unlikely(start > end)) | |
450 | return ~ret; | |
451 | } | |
79aceca5 FB |
452 | |
453 | return ret; | |
454 | } | |
455 | ||
a750fc0b | 456 | /*****************************************************************************/ |
a750fc0b | 457 | /* PowerPC instructions table */ |
933dc6eb | 458 | |
76a66253 | 459 | #if defined(DO_PPC_STATISTICS) |
79aceca5 | 460 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ |
5c55ff99 | 461 | { \ |
79aceca5 FB |
462 | .opc1 = op1, \ |
463 | .opc2 = op2, \ | |
464 | .opc3 = op3, \ | |
18fba28c | 465 | .pad = { 0, }, \ |
79aceca5 FB |
466 | .handler = { \ |
467 | .inval = invl, \ | |
9a64fbe4 | 468 | .type = _typ, \ |
79aceca5 | 469 | .handler = &gen_##name, \ |
76a66253 | 470 | .oname = stringify(name), \ |
79aceca5 | 471 | }, \ |
3fc6c082 | 472 | .oname = stringify(name), \ |
79aceca5 | 473 | } |
c7697e1f | 474 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \ |
5c55ff99 | 475 | { \ |
c7697e1f JM |
476 | .opc1 = op1, \ |
477 | .opc2 = op2, \ | |
478 | .opc3 = op3, \ | |
479 | .pad = { 0, }, \ | |
480 | .handler = { \ | |
481 | .inval = invl, \ | |
482 | .type = _typ, \ | |
483 | .handler = &gen_##name, \ | |
484 | .oname = onam, \ | |
485 | }, \ | |
486 | .oname = onam, \ | |
487 | } | |
76a66253 JM |
488 | #else |
489 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ | |
5c55ff99 | 490 | { \ |
c7697e1f JM |
491 | .opc1 = op1, \ |
492 | .opc2 = op2, \ | |
493 | .opc3 = op3, \ | |
494 | .pad = { 0, }, \ | |
495 | .handler = { \ | |
496 | .inval = invl, \ | |
497 | .type = _typ, \ | |
498 | .handler = &gen_##name, \ | |
5c55ff99 BS |
499 | }, \ |
500 | .oname = stringify(name), \ | |
501 | } | |
502 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \ | |
503 | { \ | |
504 | .opc1 = op1, \ | |
505 | .opc2 = op2, \ | |
506 | .opc3 = op3, \ | |
507 | .pad = { 0, }, \ | |
508 | .handler = { \ | |
509 | .inval = invl, \ | |
510 | .type = _typ, \ | |
511 | .handler = &gen_##name, \ | |
512 | }, \ | |
513 | .oname = onam, \ | |
514 | } | |
515 | #endif | |
2e610050 | 516 | |
5c55ff99 | 517 | /* SPR load/store helpers */ |
636aa200 | 518 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 BS |
519 | { |
520 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg])); | |
521 | } | |
2e610050 | 522 | |
636aa200 | 523 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 BS |
524 | { |
525 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg])); | |
526 | } | |
2e610050 | 527 | |
54623277 | 528 | /* Invalid instruction */ |
99e300ef | 529 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 530 | { |
e06fcd75 | 531 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
532 | } |
533 | ||
c227f099 | 534 | static opc_handler_t invalid_handler = { |
79aceca5 | 535 | .inval = 0xFFFFFFFF, |
9a64fbe4 | 536 | .type = PPC_NONE, |
79aceca5 FB |
537 | .handler = gen_invalid, |
538 | }; | |
539 | ||
e1571908 AJ |
540 | /*** Integer comparison ***/ |
541 | ||
636aa200 | 542 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 AJ |
543 | { |
544 | int l1, l2, l3; | |
545 | ||
269f3e95 AJ |
546 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer); |
547 | tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO); | |
e1571908 AJ |
548 | tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1); |
549 | ||
550 | l1 = gen_new_label(); | |
551 | l2 = gen_new_label(); | |
552 | l3 = gen_new_label(); | |
553 | if (s) { | |
ea363694 AJ |
554 | tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1); |
555 | tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2); | |
e1571908 | 556 | } else { |
ea363694 AJ |
557 | tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1); |
558 | tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2); | |
e1571908 AJ |
559 | } |
560 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ); | |
561 | tcg_gen_br(l3); | |
562 | gen_set_label(l1); | |
563 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT); | |
564 | tcg_gen_br(l3); | |
565 | gen_set_label(l2); | |
566 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT); | |
567 | gen_set_label(l3); | |
568 | } | |
569 | ||
636aa200 | 570 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 571 | { |
ea363694 AJ |
572 | TCGv t0 = tcg_const_local_tl(arg1); |
573 | gen_op_cmp(arg0, t0, s, crf); | |
574 | tcg_temp_free(t0); | |
e1571908 AJ |
575 | } |
576 | ||
577 | #if defined(TARGET_PPC64) | |
636aa200 | 578 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 579 | { |
ea363694 | 580 | TCGv t0, t1; |
a7812ae4 PB |
581 | t0 = tcg_temp_local_new(); |
582 | t1 = tcg_temp_local_new(); | |
e1571908 | 583 | if (s) { |
ea363694 AJ |
584 | tcg_gen_ext32s_tl(t0, arg0); |
585 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 586 | } else { |
ea363694 AJ |
587 | tcg_gen_ext32u_tl(t0, arg0); |
588 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 589 | } |
ea363694 AJ |
590 | gen_op_cmp(t0, t1, s, crf); |
591 | tcg_temp_free(t1); | |
592 | tcg_temp_free(t0); | |
e1571908 AJ |
593 | } |
594 | ||
636aa200 | 595 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 596 | { |
ea363694 AJ |
597 | TCGv t0 = tcg_const_local_tl(arg1); |
598 | gen_op_cmp32(arg0, t0, s, crf); | |
599 | tcg_temp_free(t0); | |
e1571908 AJ |
600 | } |
601 | #endif | |
602 | ||
636aa200 | 603 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 AJ |
604 | { |
605 | #if defined(TARGET_PPC64) | |
606 | if (!(ctx->sf_mode)) | |
607 | gen_op_cmpi32(reg, 0, 1, 0); | |
608 | else | |
609 | #endif | |
610 | gen_op_cmpi(reg, 0, 1, 0); | |
611 | } | |
612 | ||
613 | /* cmp */ | |
99e300ef | 614 | static void gen_cmp(DisasContext *ctx) |
e1571908 AJ |
615 | { |
616 | #if defined(TARGET_PPC64) | |
617 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
618 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
619 | 1, crfD(ctx->opcode)); | |
620 | else | |
621 | #endif | |
622 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
623 | 1, crfD(ctx->opcode)); | |
624 | } | |
625 | ||
626 | /* cmpi */ | |
99e300ef | 627 | static void gen_cmpi(DisasContext *ctx) |
e1571908 AJ |
628 | { |
629 | #if defined(TARGET_PPC64) | |
630 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
631 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
632 | 1, crfD(ctx->opcode)); | |
633 | else | |
634 | #endif | |
635 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
636 | 1, crfD(ctx->opcode)); | |
637 | } | |
638 | ||
639 | /* cmpl */ | |
99e300ef | 640 | static void gen_cmpl(DisasContext *ctx) |
e1571908 AJ |
641 | { |
642 | #if defined(TARGET_PPC64) | |
643 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
644 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
645 | 0, crfD(ctx->opcode)); | |
646 | else | |
647 | #endif | |
648 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
649 | 0, crfD(ctx->opcode)); | |
650 | } | |
651 | ||
652 | /* cmpli */ | |
99e300ef | 653 | static void gen_cmpli(DisasContext *ctx) |
e1571908 AJ |
654 | { |
655 | #if defined(TARGET_PPC64) | |
656 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
657 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
658 | 0, crfD(ctx->opcode)); | |
659 | else | |
660 | #endif | |
661 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
662 | 0, crfD(ctx->opcode)); | |
663 | } | |
664 | ||
665 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 666 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
667 | { |
668 | int l1, l2; | |
669 | uint32_t bi = rC(ctx->opcode); | |
670 | uint32_t mask; | |
a7812ae4 | 671 | TCGv_i32 t0; |
e1571908 AJ |
672 | |
673 | l1 = gen_new_label(); | |
674 | l2 = gen_new_label(); | |
675 | ||
676 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 677 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
678 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
679 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
680 | if (rA(ctx->opcode) == 0) |
681 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
682 | else | |
683 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
684 | tcg_gen_br(l2); | |
685 | gen_set_label(l1); | |
686 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
687 | gen_set_label(l2); | |
a7812ae4 | 688 | tcg_temp_free_i32(t0); |
e1571908 AJ |
689 | } |
690 | ||
79aceca5 | 691 | /*** Integer arithmetic ***/ |
79aceca5 | 692 | |
636aa200 BS |
693 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
694 | TCGv arg1, TCGv arg2, int sub) | |
74637406 AJ |
695 | { |
696 | int l1; | |
697 | TCGv t0; | |
79aceca5 | 698 | |
74637406 AJ |
699 | l1 = gen_new_label(); |
700 | /* Start with XER OV disabled, the most likely case */ | |
701 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
a7812ae4 | 702 | t0 = tcg_temp_local_new(); |
74637406 AJ |
703 | tcg_gen_xor_tl(t0, arg0, arg1); |
704 | #if defined(TARGET_PPC64) | |
705 | if (!ctx->sf_mode) | |
706 | tcg_gen_ext32s_tl(t0, t0); | |
707 | #endif | |
708 | if (sub) | |
709 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); | |
710 | else | |
711 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
712 | tcg_gen_xor_tl(t0, arg1, arg2); | |
713 | #if defined(TARGET_PPC64) | |
714 | if (!ctx->sf_mode) | |
715 | tcg_gen_ext32s_tl(t0, t0); | |
716 | #endif | |
717 | if (sub) | |
718 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
719 | else | |
720 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); | |
721 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
722 | gen_set_label(l1); | |
723 | tcg_temp_free(t0); | |
79aceca5 FB |
724 | } |
725 | ||
636aa200 BS |
726 | static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, |
727 | TCGv arg2, int sub) | |
74637406 AJ |
728 | { |
729 | int l1 = gen_new_label(); | |
d9bce9d9 JM |
730 | |
731 | #if defined(TARGET_PPC64) | |
74637406 AJ |
732 | if (!(ctx->sf_mode)) { |
733 | TCGv t0, t1; | |
a7812ae4 PB |
734 | t0 = tcg_temp_new(); |
735 | t1 = tcg_temp_new(); | |
d9bce9d9 | 736 | |
74637406 AJ |
737 | tcg_gen_ext32u_tl(t0, arg1); |
738 | tcg_gen_ext32u_tl(t1, arg2); | |
739 | if (sub) { | |
740 | tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); | |
bdc4e053 | 741 | } else { |
74637406 AJ |
742 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
743 | } | |
a9730017 AJ |
744 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
745 | gen_set_label(l1); | |
746 | tcg_temp_free(t0); | |
747 | tcg_temp_free(t1); | |
74637406 AJ |
748 | } else |
749 | #endif | |
a9730017 AJ |
750 | { |
751 | if (sub) { | |
752 | tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1); | |
753 | } else { | |
754 | tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1); | |
755 | } | |
756 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); | |
757 | gen_set_label(l1); | |
74637406 | 758 | } |
d9bce9d9 JM |
759 | } |
760 | ||
74637406 | 761 | /* Common add function */ |
636aa200 BS |
762 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
763 | TCGv arg2, int add_ca, int compute_ca, | |
764 | int compute_ov) | |
74637406 AJ |
765 | { |
766 | TCGv t0, t1; | |
d9bce9d9 | 767 | |
74637406 | 768 | if ((!compute_ca && !compute_ov) || |
a7812ae4 | 769 | (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) { |
74637406 AJ |
770 | t0 = ret; |
771 | } else { | |
a7812ae4 | 772 | t0 = tcg_temp_local_new(); |
74637406 | 773 | } |
79aceca5 | 774 | |
74637406 | 775 | if (add_ca) { |
a7812ae4 | 776 | t1 = tcg_temp_local_new(); |
74637406 AJ |
777 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); |
778 | tcg_gen_shri_tl(t1, t1, XER_CA); | |
d2e9fd8f | 779 | } else { |
780 | TCGV_UNUSED(t1); | |
74637406 | 781 | } |
79aceca5 | 782 | |
74637406 AJ |
783 | if (compute_ca && compute_ov) { |
784 | /* Start with XER CA and OV disabled, the most likely case */ | |
785 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); | |
786 | } else if (compute_ca) { | |
787 | /* Start with XER CA disabled, the most likely case */ | |
788 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
789 | } else if (compute_ov) { | |
790 | /* Start with XER OV disabled, the most likely case */ | |
791 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
792 | } | |
79aceca5 | 793 | |
74637406 AJ |
794 | tcg_gen_add_tl(t0, arg1, arg2); |
795 | ||
796 | if (compute_ca) { | |
797 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
798 | } | |
799 | if (add_ca) { | |
800 | tcg_gen_add_tl(t0, t0, t1); | |
801 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
802 | tcg_temp_free(t1); | |
803 | } | |
804 | if (compute_ov) { | |
805 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
806 | } | |
807 | ||
808 | if (unlikely(Rc(ctx->opcode) != 0)) | |
809 | gen_set_Rc0(ctx, t0); | |
810 | ||
a7812ae4 | 811 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
812 | tcg_gen_mov_tl(ret, t0); |
813 | tcg_temp_free(t0); | |
814 | } | |
39dd32ee | 815 | } |
74637406 AJ |
816 | /* Add functions with two operands */ |
817 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
99e300ef | 818 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
819 | { \ |
820 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
821 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
822 | add_ca, compute_ca, compute_ov); \ | |
823 | } | |
824 | /* Add functions with one operand and one immediate */ | |
825 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
826 | add_ca, compute_ca, compute_ov) \ | |
99e300ef | 827 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
828 | { \ |
829 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
830 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
831 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
832 | add_ca, compute_ca, compute_ov); \ | |
833 | tcg_temp_free(t0); \ | |
834 | } | |
835 | ||
836 | /* add add. addo addo. */ | |
837 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
838 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
839 | /* addc addc. addco addco. */ | |
840 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
841 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
842 | /* adde adde. addeo addeo. */ | |
843 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
844 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
845 | /* addme addme. addmeo addmeo. */ | |
846 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
847 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
848 | /* addze addze. addzeo addzeo.*/ | |
849 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
850 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
851 | /* addi */ | |
99e300ef | 852 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 853 | { |
74637406 AJ |
854 | target_long simm = SIMM(ctx->opcode); |
855 | ||
856 | if (rA(ctx->opcode) == 0) { | |
857 | /* li case */ | |
858 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
859 | } else { | |
860 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm); | |
861 | } | |
d9bce9d9 | 862 | } |
74637406 | 863 | /* addic addic.*/ |
636aa200 BS |
864 | static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1, |
865 | int compute_Rc0) | |
d9bce9d9 | 866 | { |
74637406 AJ |
867 | target_long simm = SIMM(ctx->opcode); |
868 | ||
869 | /* Start with XER CA and OV disabled, the most likely case */ | |
870 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
871 | ||
872 | if (likely(simm != 0)) { | |
a7812ae4 | 873 | TCGv t0 = tcg_temp_local_new(); |
74637406 AJ |
874 | tcg_gen_addi_tl(t0, arg1, simm); |
875 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
876 | tcg_gen_mov_tl(ret, t0); | |
877 | tcg_temp_free(t0); | |
878 | } else { | |
879 | tcg_gen_mov_tl(ret, arg1); | |
880 | } | |
881 | if (compute_Rc0) { | |
882 | gen_set_Rc0(ctx, ret); | |
883 | } | |
d9bce9d9 | 884 | } |
99e300ef BS |
885 | |
886 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 887 | { |
74637406 | 888 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
d9bce9d9 | 889 | } |
e8eaa2c0 BS |
890 | |
891 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 892 | { |
74637406 | 893 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
d9bce9d9 | 894 | } |
99e300ef | 895 | |
54623277 | 896 | /* addis */ |
99e300ef | 897 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 898 | { |
74637406 AJ |
899 | target_long simm = SIMM(ctx->opcode); |
900 | ||
901 | if (rA(ctx->opcode) == 0) { | |
902 | /* lis case */ | |
903 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
904 | } else { | |
905 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16); | |
906 | } | |
d9bce9d9 | 907 | } |
74637406 | 908 | |
636aa200 BS |
909 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
910 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 911 | { |
2ef1b120 AJ |
912 | int l1 = gen_new_label(); |
913 | int l2 = gen_new_label(); | |
a7812ae4 PB |
914 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
915 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 916 | |
2ef1b120 AJ |
917 | tcg_gen_trunc_tl_i32(t0, arg1); |
918 | tcg_gen_trunc_tl_i32(t1, arg2); | |
919 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 920 | if (sign) { |
2ef1b120 AJ |
921 | int l3 = gen_new_label(); |
922 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
923 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 924 | gen_set_label(l3); |
2ef1b120 | 925 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 926 | } else { |
2ef1b120 | 927 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
928 | } |
929 | if (compute_ov) { | |
930 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
931 | } | |
932 | tcg_gen_br(l2); | |
933 | gen_set_label(l1); | |
934 | if (sign) { | |
2ef1b120 | 935 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
936 | } else { |
937 | tcg_gen_movi_i32(t0, 0); | |
938 | } | |
939 | if (compute_ov) { | |
940 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
941 | } | |
942 | gen_set_label(l2); | |
2ef1b120 | 943 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
944 | tcg_temp_free_i32(t0); |
945 | tcg_temp_free_i32(t1); | |
74637406 AJ |
946 | if (unlikely(Rc(ctx->opcode) != 0)) |
947 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 948 | } |
74637406 AJ |
949 | /* Div functions */ |
950 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 951 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
952 | { \ |
953 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
954 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
955 | sign, compute_ov); \ | |
956 | } | |
957 | /* divwu divwu. divwuo divwuo. */ | |
958 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
959 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
960 | /* divw divw. divwo divwo. */ | |
961 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
962 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
d9bce9d9 | 963 | #if defined(TARGET_PPC64) |
636aa200 BS |
964 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
965 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 966 | { |
2ef1b120 AJ |
967 | int l1 = gen_new_label(); |
968 | int l2 = gen_new_label(); | |
74637406 AJ |
969 | |
970 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
971 | if (sign) { | |
2ef1b120 | 972 | int l3 = gen_new_label(); |
74637406 AJ |
973 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
974 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
975 | gen_set_label(l3); | |
74637406 AJ |
976 | tcg_gen_div_i64(ret, arg1, arg2); |
977 | } else { | |
978 | tcg_gen_divu_i64(ret, arg1, arg2); | |
979 | } | |
980 | if (compute_ov) { | |
981 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
982 | } | |
983 | tcg_gen_br(l2); | |
984 | gen_set_label(l1); | |
985 | if (sign) { | |
986 | tcg_gen_sari_i64(ret, arg1, 63); | |
987 | } else { | |
988 | tcg_gen_movi_i64(ret, 0); | |
989 | } | |
990 | if (compute_ov) { | |
991 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
992 | } | |
993 | gen_set_label(l2); | |
994 | if (unlikely(Rc(ctx->opcode) != 0)) | |
995 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 996 | } |
74637406 | 997 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 998 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 999 | { \ |
2ef1b120 AJ |
1000 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1001 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1002 | sign, compute_ov); \ | |
74637406 AJ |
1003 | } |
1004 | /* divwu divwu. divwuo divwuo. */ | |
1005 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1006 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1007 | /* divw divw. divwo divwo. */ | |
1008 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1009 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
d9bce9d9 | 1010 | #endif |
74637406 AJ |
1011 | |
1012 | /* mulhw mulhw. */ | |
99e300ef | 1013 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1014 | { |
a7812ae4 | 1015 | TCGv_i64 t0, t1; |
74637406 | 1016 | |
a7812ae4 PB |
1017 | t0 = tcg_temp_new_i64(); |
1018 | t1 = tcg_temp_new_i64(); | |
74637406 AJ |
1019 | #if defined(TARGET_PPC64) |
1020 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1021 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1022 | tcg_gen_mul_i64(t0, t0, t1); | |
1023 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
1024 | #else | |
1025 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1026 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1027 | tcg_gen_mul_i64(t0, t0, t1); | |
1028 | tcg_gen_shri_i64(t0, t0, 32); | |
1029 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1030 | #endif | |
a7812ae4 PB |
1031 | tcg_temp_free_i64(t0); |
1032 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1033 | if (unlikely(Rc(ctx->opcode) != 0)) |
1034 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1035 | } |
99e300ef | 1036 | |
54623277 | 1037 | /* mulhwu mulhwu. */ |
99e300ef | 1038 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1039 | { |
a7812ae4 | 1040 | TCGv_i64 t0, t1; |
74637406 | 1041 | |
a7812ae4 PB |
1042 | t0 = tcg_temp_new_i64(); |
1043 | t1 = tcg_temp_new_i64(); | |
d9bce9d9 | 1044 | #if defined(TARGET_PPC64) |
74637406 AJ |
1045 | tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1046 | tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1047 | tcg_gen_mul_i64(t0, t0, t1); | |
1048 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
1049 | #else | |
1050 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1051 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1052 | tcg_gen_mul_i64(t0, t0, t1); | |
1053 | tcg_gen_shri_i64(t0, t0, 32); | |
1054 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1055 | #endif | |
a7812ae4 PB |
1056 | tcg_temp_free_i64(t0); |
1057 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1058 | if (unlikely(Rc(ctx->opcode) != 0)) |
1059 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1060 | } |
99e300ef | 1061 | |
54623277 | 1062 | /* mullw mullw. */ |
99e300ef | 1063 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1064 | { |
74637406 AJ |
1065 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1066 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1067 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
74637406 AJ |
1068 | if (unlikely(Rc(ctx->opcode) != 0)) |
1069 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1070 | } |
99e300ef | 1071 | |
54623277 | 1072 | /* mullwo mullwo. */ |
99e300ef | 1073 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1074 | { |
74637406 | 1075 | int l1; |
a7812ae4 | 1076 | TCGv_i64 t0, t1; |
74637406 | 1077 | |
a7812ae4 PB |
1078 | t0 = tcg_temp_new_i64(); |
1079 | t1 = tcg_temp_new_i64(); | |
74637406 AJ |
1080 | l1 = gen_new_label(); |
1081 | /* Start with XER OV disabled, the most likely case */ | |
1082 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1083 | #if defined(TARGET_PPC64) | |
1084 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1085 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1086 | #else | |
1087 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1088 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
d9bce9d9 | 1089 | #endif |
74637406 AJ |
1090 | tcg_gen_mul_i64(t0, t0, t1); |
1091 | #if defined(TARGET_PPC64) | |
1092 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1093 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); | |
1094 | #else | |
1095 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1096 | tcg_gen_ext32s_i64(t1, t0); | |
1097 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
1098 | #endif | |
1099 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1100 | gen_set_label(l1); | |
a7812ae4 PB |
1101 | tcg_temp_free_i64(t0); |
1102 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1103 | if (unlikely(Rc(ctx->opcode) != 0)) |
1104 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1105 | } |
99e300ef | 1106 | |
54623277 | 1107 | /* mulli */ |
99e300ef | 1108 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1109 | { |
74637406 AJ |
1110 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1111 | SIMM(ctx->opcode)); | |
d9bce9d9 JM |
1112 | } |
1113 | #if defined(TARGET_PPC64) | |
74637406 | 1114 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ |
99e300ef | 1115 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1116 | { \ |
a7812ae4 | 1117 | gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \ |
74637406 AJ |
1118 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
1119 | if (unlikely(Rc(ctx->opcode) != 0)) \ | |
1120 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
d9bce9d9 | 1121 | } |
74637406 AJ |
1122 | /* mulhd mulhd. */ |
1123 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00); | |
1124 | /* mulhdu mulhdu. */ | |
1125 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02); | |
99e300ef | 1126 | |
54623277 | 1127 | /* mulld mulld. */ |
99e300ef | 1128 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1129 | { |
74637406 AJ |
1130 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1131 | cpu_gpr[rB(ctx->opcode)]); | |
1132 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1133 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1134 | } |
74637406 AJ |
1135 | /* mulldo mulldo. */ |
1136 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17); | |
d9bce9d9 | 1137 | #endif |
74637406 AJ |
1138 | |
1139 | /* neg neg. nego nego. */ | |
636aa200 BS |
1140 | static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1, |
1141 | int ov_check) | |
d9bce9d9 | 1142 | { |
ec6469a3 AJ |
1143 | int l1 = gen_new_label(); |
1144 | int l2 = gen_new_label(); | |
a7812ae4 | 1145 | TCGv t0 = tcg_temp_local_new(); |
d9bce9d9 | 1146 | #if defined(TARGET_PPC64) |
74637406 | 1147 | if (ctx->sf_mode) { |
741a7444 | 1148 | tcg_gen_mov_tl(t0, arg1); |
ec6469a3 AJ |
1149 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); |
1150 | } else | |
1151 | #endif | |
1152 | { | |
1153 | tcg_gen_ext32s_tl(t0, arg1); | |
74637406 AJ |
1154 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); |
1155 | } | |
74637406 AJ |
1156 | tcg_gen_neg_tl(ret, arg1); |
1157 | if (ov_check) { | |
1158 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1159 | } | |
1160 | tcg_gen_br(l2); | |
1161 | gen_set_label(l1); | |
ec6469a3 | 1162 | tcg_gen_mov_tl(ret, t0); |
74637406 AJ |
1163 | if (ov_check) { |
1164 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1165 | } | |
1166 | gen_set_label(l2); | |
ec6469a3 | 1167 | tcg_temp_free(t0); |
74637406 AJ |
1168 | if (unlikely(Rc(ctx->opcode) != 0)) |
1169 | gen_set_Rc0(ctx, ret); | |
1170 | } | |
99e300ef BS |
1171 | |
1172 | static void gen_neg(DisasContext *ctx) | |
d9bce9d9 | 1173 | { |
ec6469a3 | 1174 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
d9bce9d9 | 1175 | } |
99e300ef BS |
1176 | |
1177 | static void gen_nego(DisasContext *ctx) | |
79aceca5 | 1178 | { |
ec6469a3 | 1179 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
79aceca5 | 1180 | } |
74637406 AJ |
1181 | |
1182 | /* Common subf function */ | |
636aa200 BS |
1183 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
1184 | TCGv arg2, int add_ca, int compute_ca, | |
1185 | int compute_ov) | |
79aceca5 | 1186 | { |
74637406 | 1187 | TCGv t0, t1; |
76a66253 | 1188 | |
74637406 | 1189 | if ((!compute_ca && !compute_ov) || |
a7812ae4 | 1190 | (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) { |
74637406 | 1191 | t0 = ret; |
e864cabd | 1192 | } else { |
a7812ae4 | 1193 | t0 = tcg_temp_local_new(); |
d9bce9d9 | 1194 | } |
76a66253 | 1195 | |
74637406 | 1196 | if (add_ca) { |
a7812ae4 | 1197 | t1 = tcg_temp_local_new(); |
74637406 AJ |
1198 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); |
1199 | tcg_gen_shri_tl(t1, t1, XER_CA); | |
d2e9fd8f | 1200 | } else { |
1201 | TCGV_UNUSED(t1); | |
d9bce9d9 | 1202 | } |
79aceca5 | 1203 | |
74637406 AJ |
1204 | if (compute_ca && compute_ov) { |
1205 | /* Start with XER CA and OV disabled, the most likely case */ | |
1206 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); | |
1207 | } else if (compute_ca) { | |
1208 | /* Start with XER CA disabled, the most likely case */ | |
1209 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1210 | } else if (compute_ov) { | |
1211 | /* Start with XER OV disabled, the most likely case */ | |
1212 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1213 | } | |
1214 | ||
1215 | if (add_ca) { | |
1216 | tcg_gen_not_tl(t0, arg1); | |
1217 | tcg_gen_add_tl(t0, t0, arg2); | |
1218 | gen_op_arith_compute_ca(ctx, t0, arg2, 0); | |
1219 | tcg_gen_add_tl(t0, t0, t1); | |
1220 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
1221 | tcg_temp_free(t1); | |
79aceca5 | 1222 | } else { |
74637406 AJ |
1223 | tcg_gen_sub_tl(t0, arg2, arg1); |
1224 | if (compute_ca) { | |
1225 | gen_op_arith_compute_ca(ctx, t0, arg2, 1); | |
1226 | } | |
1227 | } | |
1228 | if (compute_ov) { | |
1229 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1230 | } | |
1231 | ||
1232 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1233 | gen_set_Rc0(ctx, t0); | |
1234 | ||
a7812ae4 | 1235 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1236 | tcg_gen_mov_tl(ret, t0); |
1237 | tcg_temp_free(t0); | |
79aceca5 | 1238 | } |
79aceca5 | 1239 | } |
74637406 AJ |
1240 | /* Sub functions with Two operands functions */ |
1241 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
99e300ef | 1242 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1243 | { \ |
1244 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1245 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1246 | add_ca, compute_ca, compute_ov); \ | |
1247 | } | |
1248 | /* Sub functions with one operand and one immediate */ | |
1249 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1250 | add_ca, compute_ca, compute_ov) \ | |
99e300ef | 1251 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1252 | { \ |
1253 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
1254 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1255 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
1256 | add_ca, compute_ca, compute_ov); \ | |
1257 | tcg_temp_free(t0); \ | |
1258 | } | |
1259 | /* subf subf. subfo subfo. */ | |
1260 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1261 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1262 | /* subfc subfc. subfco subfco. */ | |
1263 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1264 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1265 | /* subfe subfe. subfeo subfo. */ | |
1266 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1267 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1268 | /* subfme subfme. subfmeo subfmeo. */ | |
1269 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1270 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1271 | /* subfze subfze. subfzeo subfzeo.*/ | |
1272 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1273 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1274 | |
54623277 | 1275 | /* subfic */ |
99e300ef | 1276 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1277 | { |
74637406 AJ |
1278 | /* Start with XER CA and OV disabled, the most likely case */ |
1279 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
a7812ae4 | 1280 | TCGv t0 = tcg_temp_local_new(); |
74637406 AJ |
1281 | TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode)); |
1282 | tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]); | |
1283 | gen_op_arith_compute_ca(ctx, t0, t1, 1); | |
1284 | tcg_temp_free(t1); | |
1285 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1286 | tcg_temp_free(t0); | |
79aceca5 FB |
1287 | } |
1288 | ||
79aceca5 | 1289 | /*** Integer logical ***/ |
26d67362 | 1290 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1291 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1292 | { \ |
26d67362 AJ |
1293 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1294 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1295 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1296 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1297 | } |
79aceca5 | 1298 | |
26d67362 | 1299 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1300 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1301 | { \ |
26d67362 | 1302 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1303 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1304 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1305 | } |
1306 | ||
1307 | /* and & and. */ | |
26d67362 | 1308 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1309 | /* andc & andc. */ |
26d67362 | 1310 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1311 | |
54623277 | 1312 | /* andi. */ |
e8eaa2c0 | 1313 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1314 | { |
26d67362 AJ |
1315 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1316 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1317 | } |
e8eaa2c0 | 1318 | |
54623277 | 1319 | /* andis. */ |
e8eaa2c0 | 1320 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1321 | { |
26d67362 AJ |
1322 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1323 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1324 | } |
99e300ef | 1325 | |
54623277 | 1326 | /* cntlzw */ |
99e300ef | 1327 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1328 | { |
a7812ae4 | 1329 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1330 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1331 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1332 | } |
79aceca5 | 1333 | /* eqv & eqv. */ |
26d67362 | 1334 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1335 | /* extsb & extsb. */ |
26d67362 | 1336 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1337 | /* extsh & extsh. */ |
26d67362 | 1338 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1339 | /* nand & nand. */ |
26d67362 | 1340 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1341 | /* nor & nor. */ |
26d67362 | 1342 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1343 | |
54623277 | 1344 | /* or & or. */ |
99e300ef | 1345 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1346 | { |
76a66253 JM |
1347 | int rs, ra, rb; |
1348 | ||
1349 | rs = rS(ctx->opcode); | |
1350 | ra = rA(ctx->opcode); | |
1351 | rb = rB(ctx->opcode); | |
1352 | /* Optimisation for mr. ri case */ | |
1353 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1354 | if (rs != rb) |
1355 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1356 | else | |
1357 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1358 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1359 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1360 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1361 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1362 | #if defined(TARGET_PPC64) |
1363 | } else { | |
26d67362 AJ |
1364 | int prio = 0; |
1365 | ||
c80f84e3 JM |
1366 | switch (rs) { |
1367 | case 1: | |
1368 | /* Set process priority to low */ | |
26d67362 | 1369 | prio = 2; |
c80f84e3 JM |
1370 | break; |
1371 | case 6: | |
1372 | /* Set process priority to medium-low */ | |
26d67362 | 1373 | prio = 3; |
c80f84e3 JM |
1374 | break; |
1375 | case 2: | |
1376 | /* Set process priority to normal */ | |
26d67362 | 1377 | prio = 4; |
c80f84e3 | 1378 | break; |
be147d08 JM |
1379 | #if !defined(CONFIG_USER_ONLY) |
1380 | case 31: | |
76db3ba4 | 1381 | if (ctx->mem_idx > 0) { |
be147d08 | 1382 | /* Set process priority to very low */ |
26d67362 | 1383 | prio = 1; |
be147d08 JM |
1384 | } |
1385 | break; | |
1386 | case 5: | |
76db3ba4 | 1387 | if (ctx->mem_idx > 0) { |
be147d08 | 1388 | /* Set process priority to medium-hight */ |
26d67362 | 1389 | prio = 5; |
be147d08 JM |
1390 | } |
1391 | break; | |
1392 | case 3: | |
76db3ba4 | 1393 | if (ctx->mem_idx > 0) { |
be147d08 | 1394 | /* Set process priority to high */ |
26d67362 | 1395 | prio = 6; |
be147d08 JM |
1396 | } |
1397 | break; | |
be147d08 | 1398 | case 7: |
76db3ba4 | 1399 | if (ctx->mem_idx > 1) { |
be147d08 | 1400 | /* Set process priority to very high */ |
26d67362 | 1401 | prio = 7; |
be147d08 JM |
1402 | } |
1403 | break; | |
be147d08 | 1404 | #endif |
c80f84e3 JM |
1405 | default: |
1406 | /* nop */ | |
1407 | break; | |
1408 | } | |
26d67362 | 1409 | if (prio) { |
a7812ae4 | 1410 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1411 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1412 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1413 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1414 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1415 | tcg_temp_free(t0); |
26d67362 | 1416 | } |
c80f84e3 | 1417 | #endif |
9a64fbe4 | 1418 | } |
9a64fbe4 | 1419 | } |
79aceca5 | 1420 | /* orc & orc. */ |
26d67362 | 1421 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1422 | |
54623277 | 1423 | /* xor & xor. */ |
99e300ef | 1424 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1425 | { |
9a64fbe4 | 1426 | /* Optimisation for "set to zero" case */ |
26d67362 | 1427 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1428 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1429 | else |
1430 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1431 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1432 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1433 | } |
99e300ef | 1434 | |
54623277 | 1435 | /* ori */ |
99e300ef | 1436 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1437 | { |
76a66253 | 1438 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1439 | |
9a64fbe4 FB |
1440 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1441 | /* NOP */ | |
76a66253 | 1442 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1443 | return; |
76a66253 | 1444 | } |
26d67362 | 1445 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1446 | } |
99e300ef | 1447 | |
54623277 | 1448 | /* oris */ |
99e300ef | 1449 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1450 | { |
76a66253 | 1451 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1452 | |
9a64fbe4 FB |
1453 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1454 | /* NOP */ | |
1455 | return; | |
76a66253 | 1456 | } |
26d67362 | 1457 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1458 | } |
99e300ef | 1459 | |
54623277 | 1460 | /* xori */ |
99e300ef | 1461 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1462 | { |
76a66253 | 1463 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1464 | |
1465 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1466 | /* NOP */ | |
1467 | return; | |
1468 | } | |
26d67362 | 1469 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1470 | } |
99e300ef | 1471 | |
54623277 | 1472 | /* xoris */ |
99e300ef | 1473 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1474 | { |
76a66253 | 1475 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1476 | |
1477 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1478 | /* NOP */ | |
1479 | return; | |
1480 | } | |
26d67362 | 1481 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1482 | } |
99e300ef | 1483 | |
54623277 | 1484 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1485 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1486 | { |
eaabeef2 DG |
1487 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1488 | } | |
1489 | ||
1490 | static void gen_popcntw(DisasContext *ctx) | |
1491 | { | |
1492 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1493 | } | |
1494 | ||
d9bce9d9 | 1495 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1496 | /* popcntd: PowerPC 2.06 specification */ |
1497 | static void gen_popcntd(DisasContext *ctx) | |
1498 | { | |
1499 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1500 | } |
eaabeef2 | 1501 | #endif |
d9bce9d9 JM |
1502 | |
1503 | #if defined(TARGET_PPC64) | |
1504 | /* extsw & extsw. */ | |
26d67362 | 1505 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1506 | |
54623277 | 1507 | /* cntlzd */ |
99e300ef | 1508 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1509 | { |
a7812ae4 | 1510 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1511 | if (unlikely(Rc(ctx->opcode) != 0)) |
1512 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1513 | } | |
d9bce9d9 JM |
1514 | #endif |
1515 | ||
79aceca5 | 1516 | /*** Integer rotate ***/ |
99e300ef | 1517 | |
54623277 | 1518 | /* rlwimi & rlwimi. */ |
99e300ef | 1519 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1520 | { |
76a66253 | 1521 | uint32_t mb, me, sh; |
79aceca5 FB |
1522 | |
1523 | mb = MB(ctx->opcode); | |
1524 | me = ME(ctx->opcode); | |
76a66253 | 1525 | sh = SH(ctx->opcode); |
d03ef511 AJ |
1526 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1527 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1528 | } else { | |
d03ef511 | 1529 | target_ulong mask; |
a7812ae4 PB |
1530 | TCGv t1; |
1531 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1532 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1533 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1534 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1535 | tcg_gen_rotli_i32(t2, t2, sh); | |
1536 | tcg_gen_extu_i32_i64(t0, t2); | |
1537 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1538 | #else |
1539 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1540 | #endif | |
76a66253 | 1541 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1542 | mb += 32; |
1543 | me += 32; | |
76a66253 | 1544 | #endif |
d03ef511 | 1545 | mask = MASK(mb, me); |
a7812ae4 | 1546 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1547 | tcg_gen_andi_tl(t0, t0, mask); |
1548 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1549 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1550 | tcg_temp_free(t0); | |
1551 | tcg_temp_free(t1); | |
1552 | } | |
76a66253 | 1553 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1554 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1555 | } |
99e300ef | 1556 | |
54623277 | 1557 | /* rlwinm & rlwinm. */ |
99e300ef | 1558 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1559 | { |
1560 | uint32_t mb, me, sh; | |
3b46e624 | 1561 | |
79aceca5 FB |
1562 | sh = SH(ctx->opcode); |
1563 | mb = MB(ctx->opcode); | |
1564 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1565 | |
1566 | if (likely(mb == 0 && me == (31 - sh))) { | |
1567 | if (likely(sh == 0)) { | |
1568 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1569 | } else { | |
a7812ae4 | 1570 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1571 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1572 | tcg_gen_shli_tl(t0, t0, sh); | |
1573 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1574 | tcg_temp_free(t0); | |
79aceca5 | 1575 | } |
d03ef511 | 1576 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1577 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1578 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1579 | tcg_gen_shri_tl(t0, t0, mb); | |
1580 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1581 | tcg_temp_free(t0); | |
1582 | } else { | |
a7812ae4 | 1583 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1584 | #if defined(TARGET_PPC64) |
a7812ae4 | 1585 | TCGv_i32 t1 = tcg_temp_new_i32(); |
54843a58 AJ |
1586 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1587 | tcg_gen_rotli_i32(t1, t1, sh); | |
1588 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 | 1589 | tcg_temp_free_i32(t1); |
54843a58 AJ |
1590 | #else |
1591 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1592 | #endif | |
76a66253 | 1593 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1594 | mb += 32; |
1595 | me += 32; | |
76a66253 | 1596 | #endif |
d03ef511 AJ |
1597 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1598 | tcg_temp_free(t0); | |
1599 | } | |
76a66253 | 1600 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1601 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1602 | } |
99e300ef | 1603 | |
54623277 | 1604 | /* rlwnm & rlwnm. */ |
99e300ef | 1605 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1606 | { |
1607 | uint32_t mb, me; | |
54843a58 AJ |
1608 | TCGv t0; |
1609 | #if defined(TARGET_PPC64) | |
a7812ae4 | 1610 | TCGv_i32 t1, t2; |
54843a58 | 1611 | #endif |
79aceca5 FB |
1612 | |
1613 | mb = MB(ctx->opcode); | |
1614 | me = ME(ctx->opcode); | |
a7812ae4 | 1615 | t0 = tcg_temp_new(); |
d03ef511 | 1616 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1617 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1618 | t1 = tcg_temp_new_i32(); |
1619 | t2 = tcg_temp_new_i32(); | |
54843a58 AJ |
1620 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1621 | tcg_gen_trunc_i64_i32(t2, t0); | |
1622 | tcg_gen_rotl_i32(t1, t1, t2); | |
1623 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 PB |
1624 | tcg_temp_free_i32(t1); |
1625 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1626 | #else |
1627 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1628 | #endif | |
76a66253 JM |
1629 | if (unlikely(mb != 0 || me != 31)) { |
1630 | #if defined(TARGET_PPC64) | |
1631 | mb += 32; | |
1632 | me += 32; | |
1633 | #endif | |
54843a58 | 1634 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1635 | } else { |
54843a58 | 1636 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1637 | } |
54843a58 | 1638 | tcg_temp_free(t0); |
76a66253 | 1639 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1640 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1641 | } |
1642 | ||
d9bce9d9 JM |
1643 | #if defined(TARGET_PPC64) |
1644 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1645 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1646 | { \ |
1647 | gen_##name(ctx, 0); \ | |
1648 | } \ | |
e8eaa2c0 BS |
1649 | \ |
1650 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1651 | { \ |
1652 | gen_##name(ctx, 1); \ | |
1653 | } | |
1654 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1655 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1656 | { \ |
1657 | gen_##name(ctx, 0, 0); \ | |
1658 | } \ | |
e8eaa2c0 BS |
1659 | \ |
1660 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1661 | { \ |
1662 | gen_##name(ctx, 0, 1); \ | |
1663 | } \ | |
e8eaa2c0 BS |
1664 | \ |
1665 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1666 | { \ |
1667 | gen_##name(ctx, 1, 0); \ | |
1668 | } \ | |
e8eaa2c0 BS |
1669 | \ |
1670 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1671 | { \ |
1672 | gen_##name(ctx, 1, 1); \ | |
1673 | } | |
51789c41 | 1674 | |
636aa200 BS |
1675 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1676 | uint32_t sh) | |
51789c41 | 1677 | { |
d03ef511 AJ |
1678 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1679 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1680 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1681 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1682 | } else { | |
a7812ae4 | 1683 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1684 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1685 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1686 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1687 | } else { |
1688 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1689 | } |
d03ef511 | 1690 | tcg_temp_free(t0); |
51789c41 | 1691 | } |
51789c41 | 1692 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1693 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1694 | } |
d9bce9d9 | 1695 | /* rldicl - rldicl. */ |
636aa200 | 1696 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1697 | { |
51789c41 | 1698 | uint32_t sh, mb; |
d9bce9d9 | 1699 | |
9d53c753 JM |
1700 | sh = SH(ctx->opcode) | (shn << 5); |
1701 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1702 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1703 | } |
51789c41 | 1704 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1705 | /* rldicr - rldicr. */ |
636aa200 | 1706 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1707 | { |
51789c41 | 1708 | uint32_t sh, me; |
d9bce9d9 | 1709 | |
9d53c753 JM |
1710 | sh = SH(ctx->opcode) | (shn << 5); |
1711 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1712 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1713 | } |
51789c41 | 1714 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1715 | /* rldic - rldic. */ |
636aa200 | 1716 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1717 | { |
51789c41 | 1718 | uint32_t sh, mb; |
d9bce9d9 | 1719 | |
9d53c753 JM |
1720 | sh = SH(ctx->opcode) | (shn << 5); |
1721 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1722 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1723 | } | |
1724 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1725 | ||
636aa200 | 1726 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1727 | { |
54843a58 | 1728 | TCGv t0; |
d03ef511 AJ |
1729 | |
1730 | mb = MB(ctx->opcode); | |
1731 | me = ME(ctx->opcode); | |
a7812ae4 | 1732 | t0 = tcg_temp_new(); |
d03ef511 | 1733 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1734 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1735 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1736 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1737 | } else { | |
1738 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1739 | } | |
1740 | tcg_temp_free(t0); | |
51789c41 | 1741 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1742 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1743 | } |
51789c41 | 1744 | |
d9bce9d9 | 1745 | /* rldcl - rldcl. */ |
636aa200 | 1746 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1747 | { |
51789c41 | 1748 | uint32_t mb; |
d9bce9d9 | 1749 | |
9d53c753 | 1750 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1751 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1752 | } |
36081602 | 1753 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1754 | /* rldcr - rldcr. */ |
636aa200 | 1755 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1756 | { |
51789c41 | 1757 | uint32_t me; |
d9bce9d9 | 1758 | |
9d53c753 | 1759 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1760 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1761 | } |
36081602 | 1762 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1763 | /* rldimi - rldimi. */ |
636aa200 | 1764 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1765 | { |
271a916e | 1766 | uint32_t sh, mb, me; |
d9bce9d9 | 1767 | |
9d53c753 JM |
1768 | sh = SH(ctx->opcode) | (shn << 5); |
1769 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1770 | me = 63 - sh; |
d03ef511 AJ |
1771 | if (unlikely(sh == 0 && mb == 0)) { |
1772 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1773 | } else { | |
1774 | TCGv t0, t1; | |
1775 | target_ulong mask; | |
1776 | ||
a7812ae4 | 1777 | t0 = tcg_temp_new(); |
54843a58 | 1778 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1779 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1780 | mask = MASK(mb, me); |
1781 | tcg_gen_andi_tl(t0, t0, mask); | |
1782 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1783 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1784 | tcg_temp_free(t0); | |
1785 | tcg_temp_free(t1); | |
51789c41 | 1786 | } |
51789c41 | 1787 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1788 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1789 | } |
36081602 | 1790 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1791 | #endif |
1792 | ||
79aceca5 | 1793 | /*** Integer shift ***/ |
99e300ef | 1794 | |
54623277 | 1795 | /* slw & slw. */ |
99e300ef | 1796 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1797 | { |
7fd6bf7d | 1798 | TCGv t0, t1; |
26d67362 | 1799 | |
7fd6bf7d AJ |
1800 | t0 = tcg_temp_new(); |
1801 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1802 | #if defined(TARGET_PPC64) | |
1803 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1804 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1805 | #else | |
1806 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1807 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1808 | #endif | |
1809 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1810 | t1 = tcg_temp_new(); | |
1811 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1812 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1813 | tcg_temp_free(t1); | |
fea0c503 | 1814 | tcg_temp_free(t0); |
7fd6bf7d | 1815 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1816 | if (unlikely(Rc(ctx->opcode) != 0)) |
1817 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1818 | } | |
99e300ef | 1819 | |
54623277 | 1820 | /* sraw & sraw. */ |
99e300ef | 1821 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1822 | { |
a7812ae4 PB |
1823 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], |
1824 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
26d67362 AJ |
1825 | if (unlikely(Rc(ctx->opcode) != 0)) |
1826 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1827 | } | |
99e300ef | 1828 | |
54623277 | 1829 | /* srawi & srawi. */ |
99e300ef | 1830 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1831 | { |
26d67362 AJ |
1832 | int sh = SH(ctx->opcode); |
1833 | if (sh != 0) { | |
1834 | int l1, l2; | |
fea0c503 | 1835 | TCGv t0; |
26d67362 AJ |
1836 | l1 = gen_new_label(); |
1837 | l2 = gen_new_label(); | |
a7812ae4 | 1838 | t0 = tcg_temp_local_new(); |
fea0c503 AJ |
1839 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1840 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
1841 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); | |
1842 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
269f3e95 | 1843 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
26d67362 AJ |
1844 | tcg_gen_br(l2); |
1845 | gen_set_label(l1); | |
269f3e95 | 1846 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
26d67362 | 1847 | gen_set_label(l2); |
fea0c503 AJ |
1848 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1849 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); | |
1850 | tcg_temp_free(t0); | |
26d67362 AJ |
1851 | } else { |
1852 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
269f3e95 | 1853 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
d9bce9d9 | 1854 | } |
76a66253 | 1855 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1856 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1857 | } |
99e300ef | 1858 | |
54623277 | 1859 | /* srw & srw. */ |
99e300ef | 1860 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1861 | { |
fea0c503 | 1862 | TCGv t0, t1; |
d9bce9d9 | 1863 | |
7fd6bf7d AJ |
1864 | t0 = tcg_temp_new(); |
1865 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1866 | #if defined(TARGET_PPC64) | |
1867 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1868 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1869 | #else | |
1870 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1871 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1872 | #endif | |
1873 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1874 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1875 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1876 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1877 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1878 | tcg_temp_free(t1); |
fea0c503 | 1879 | tcg_temp_free(t0); |
26d67362 AJ |
1880 | if (unlikely(Rc(ctx->opcode) != 0)) |
1881 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1882 | } | |
54623277 | 1883 | |
d9bce9d9 JM |
1884 | #if defined(TARGET_PPC64) |
1885 | /* sld & sld. */ | |
99e300ef | 1886 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1887 | { |
7fd6bf7d | 1888 | TCGv t0, t1; |
26d67362 | 1889 | |
7fd6bf7d AJ |
1890 | t0 = tcg_temp_new(); |
1891 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1892 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1893 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1894 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1895 | t1 = tcg_temp_new(); | |
1896 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1897 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1898 | tcg_temp_free(t1); | |
fea0c503 | 1899 | tcg_temp_free(t0); |
26d67362 AJ |
1900 | if (unlikely(Rc(ctx->opcode) != 0)) |
1901 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1902 | } | |
99e300ef | 1903 | |
54623277 | 1904 | /* srad & srad. */ |
99e300ef | 1905 | static void gen_srad(DisasContext *ctx) |
26d67362 | 1906 | { |
a7812ae4 PB |
1907 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], |
1908 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
26d67362 AJ |
1909 | if (unlikely(Rc(ctx->opcode) != 0)) |
1910 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1911 | } | |
d9bce9d9 | 1912 | /* sradi & sradi. */ |
636aa200 | 1913 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 1914 | { |
26d67362 | 1915 | int sh = SH(ctx->opcode) + (n << 5); |
d9bce9d9 | 1916 | if (sh != 0) { |
26d67362 | 1917 | int l1, l2; |
fea0c503 | 1918 | TCGv t0; |
26d67362 AJ |
1919 | l1 = gen_new_label(); |
1920 | l2 = gen_new_label(); | |
a7812ae4 | 1921 | t0 = tcg_temp_local_new(); |
26d67362 | 1922 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); |
fea0c503 AJ |
1923 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1924 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
269f3e95 | 1925 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
26d67362 AJ |
1926 | tcg_gen_br(l2); |
1927 | gen_set_label(l1); | |
269f3e95 | 1928 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
26d67362 | 1929 | gen_set_label(l2); |
a9730017 | 1930 | tcg_temp_free(t0); |
26d67362 AJ |
1931 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1932 | } else { | |
1933 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
269f3e95 | 1934 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
d9bce9d9 | 1935 | } |
d9bce9d9 | 1936 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1937 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1938 | } |
e8eaa2c0 BS |
1939 | |
1940 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
1941 | { |
1942 | gen_sradi(ctx, 0); | |
1943 | } | |
e8eaa2c0 BS |
1944 | |
1945 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
1946 | { |
1947 | gen_sradi(ctx, 1); | |
1948 | } | |
99e300ef | 1949 | |
54623277 | 1950 | /* srd & srd. */ |
99e300ef | 1951 | static void gen_srd(DisasContext *ctx) |
26d67362 | 1952 | { |
7fd6bf7d | 1953 | TCGv t0, t1; |
26d67362 | 1954 | |
7fd6bf7d AJ |
1955 | t0 = tcg_temp_new(); |
1956 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1957 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1958 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1959 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1960 | t1 = tcg_temp_new(); | |
1961 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1962 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1963 | tcg_temp_free(t1); | |
fea0c503 | 1964 | tcg_temp_free(t0); |
26d67362 AJ |
1965 | if (unlikely(Rc(ctx->opcode) != 0)) |
1966 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1967 | } | |
d9bce9d9 | 1968 | #endif |
79aceca5 FB |
1969 | |
1970 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 1971 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 1972 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1973 | { \ |
76a66253 | 1974 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1975 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1976 | return; \ |
1977 | } \ | |
eb44b959 AJ |
1978 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
1979 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 1980 | gen_reset_fpstatus(); \ |
af12906f AJ |
1981 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
1982 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ | |
4ecc3190 | 1983 | if (isfloat) { \ |
af12906f | 1984 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
4ecc3190 | 1985 | } \ |
af12906f AJ |
1986 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
1987 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
1988 | } |
1989 | ||
7c58044c JM |
1990 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
1991 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
1992 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 1993 | |
7c58044c | 1994 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 1995 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 1996 | { \ |
76a66253 | 1997 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 1998 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
1999 | return; \ |
2000 | } \ | |
eb44b959 AJ |
2001 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2002 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2003 | gen_reset_fpstatus(); \ |
af12906f AJ |
2004 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
2005 | cpu_fpr[rB(ctx->opcode)]); \ | |
4ecc3190 | 2006 | if (isfloat) { \ |
af12906f | 2007 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
4ecc3190 | 2008 | } \ |
af12906f AJ |
2009 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2010 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2011 | } |
7c58044c JM |
2012 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2013 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2014 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2015 | |
7c58044c | 2016 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2017 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2018 | { \ |
76a66253 | 2019 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2020 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2021 | return; \ |
2022 | } \ | |
eb44b959 AJ |
2023 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2024 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2025 | gen_reset_fpstatus(); \ |
af12906f AJ |
2026 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
2027 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2028 | if (isfloat) { \ |
af12906f | 2029 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
4ecc3190 | 2030 | } \ |
af12906f AJ |
2031 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2032 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2033 | } |
7c58044c JM |
2034 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2035 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2036 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2037 | |
7c58044c | 2038 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 2039 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2040 | { \ |
76a66253 | 2041 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2042 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2043 | return; \ |
2044 | } \ | |
eb44b959 AJ |
2045 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2046 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2047 | gen_reset_fpstatus(); \ |
af12906f AJ |
2048 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2049 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ | |
2050 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2051 | } |
2052 | ||
7c58044c | 2053 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2054 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2055 | { \ |
76a66253 | 2056 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2057 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2058 | return; \ |
2059 | } \ | |
eb44b959 AJ |
2060 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2061 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2062 | gen_reset_fpstatus(); \ |
af12906f AJ |
2063 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2064 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ | |
2065 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2066 | } |
2067 | ||
9a64fbe4 | 2068 | /* fadd - fadds */ |
7c58044c | 2069 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2070 | /* fdiv - fdivs */ |
7c58044c | 2071 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2072 | /* fmul - fmuls */ |
7c58044c | 2073 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2074 | |
d7e4b87e | 2075 | /* fre */ |
7c58044c | 2076 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2077 | |
a750fc0b | 2078 | /* fres */ |
7c58044c | 2079 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2080 | |
a750fc0b | 2081 | /* frsqrte */ |
7c58044c JM |
2082 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2083 | ||
2084 | /* frsqrtes */ | |
99e300ef | 2085 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2086 | { |
af12906f | 2087 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2088 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2089 | return; |
2090 | } | |
eb44b959 AJ |
2091 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2092 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f AJ |
2093 | gen_reset_fpstatus(); |
2094 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2095 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); | |
2096 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); | |
7c58044c | 2097 | } |
79aceca5 | 2098 | |
a750fc0b | 2099 | /* fsel */ |
7c58044c | 2100 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2101 | /* fsub - fsubs */ |
7c58044c | 2102 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2103 | /* Optional: */ |
99e300ef | 2104 | |
54623277 | 2105 | /* fsqrt */ |
99e300ef | 2106 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2107 | { |
76a66253 | 2108 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2109 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2110 | return; |
2111 | } | |
eb44b959 AJ |
2112 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2113 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2114 | gen_reset_fpstatus(); |
af12906f AJ |
2115 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2116 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); | |
c7d344af | 2117 | } |
79aceca5 | 2118 | |
99e300ef | 2119 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2120 | { |
76a66253 | 2121 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2122 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2123 | return; |
2124 | } | |
eb44b959 AJ |
2125 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2126 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2127 | gen_reset_fpstatus(); |
af12906f AJ |
2128 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2129 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); | |
2130 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); | |
79aceca5 FB |
2131 | } |
2132 | ||
2133 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2134 | /* fmadd - fmadds */ |
7c58044c | 2135 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2136 | /* fmsub - fmsubs */ |
7c58044c | 2137 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2138 | /* fnmadd - fnmadds */ |
7c58044c | 2139 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2140 | /* fnmsub - fnmsubs */ |
7c58044c | 2141 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2142 | |
2143 | /*** Floating-Point round & convert ***/ | |
2144 | /* fctiw */ | |
7c58044c | 2145 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2146 | /* fctiwz */ |
7c58044c | 2147 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2148 | /* frsp */ |
7c58044c | 2149 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2150 | #if defined(TARGET_PPC64) |
2151 | /* fcfid */ | |
7c58044c | 2152 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
426613db | 2153 | /* fctid */ |
7c58044c | 2154 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
426613db | 2155 | /* fctidz */ |
7c58044c | 2156 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
426613db | 2157 | #endif |
79aceca5 | 2158 | |
d7e4b87e | 2159 | /* frin */ |
7c58044c | 2160 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2161 | /* friz */ |
7c58044c | 2162 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2163 | /* frip */ |
7c58044c | 2164 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2165 | /* frim */ |
7c58044c | 2166 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2167 | |
79aceca5 | 2168 | /*** Floating-Point compare ***/ |
99e300ef | 2169 | |
54623277 | 2170 | /* fcmpo */ |
99e300ef | 2171 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2172 | { |
330c483b | 2173 | TCGv_i32 crf; |
76a66253 | 2174 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2175 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2176 | return; |
2177 | } | |
eb44b959 AJ |
2178 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2179 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2180 | gen_reset_fpstatus(); |
9a819377 AJ |
2181 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2182 | gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2183 | tcg_temp_free_i32(crf); |
af12906f | 2184 | gen_helper_float_check_status(); |
79aceca5 FB |
2185 | } |
2186 | ||
2187 | /* fcmpu */ | |
99e300ef | 2188 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2189 | { |
330c483b | 2190 | TCGv_i32 crf; |
76a66253 | 2191 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2192 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2193 | return; |
2194 | } | |
eb44b959 AJ |
2195 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2196 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2197 | gen_reset_fpstatus(); |
9a819377 AJ |
2198 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2199 | gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2200 | tcg_temp_free_i32(crf); |
af12906f | 2201 | gen_helper_float_check_status(); |
79aceca5 FB |
2202 | } |
2203 | ||
9a64fbe4 FB |
2204 | /*** Floating-point move ***/ |
2205 | /* fabs */ | |
7c58044c JM |
2206 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
2207 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); | |
9a64fbe4 FB |
2208 | |
2209 | /* fmr - fmr. */ | |
7c58044c | 2210 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2211 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2212 | { |
76a66253 | 2213 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2214 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2215 | return; |
2216 | } | |
af12906f AJ |
2217 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2218 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2219 | } |
2220 | ||
2221 | /* fnabs */ | |
7c58044c JM |
2222 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
2223 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); | |
9a64fbe4 | 2224 | /* fneg */ |
7c58044c JM |
2225 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
2226 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); | |
9a64fbe4 | 2227 | |
79aceca5 | 2228 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2229 | |
54623277 | 2230 | /* mcrfs */ |
99e300ef | 2231 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2232 | { |
7c58044c JM |
2233 | int bfa; |
2234 | ||
76a66253 | 2235 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2236 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2237 | return; |
2238 | } | |
7c58044c | 2239 | bfa = 4 * (7 - crfS(ctx->opcode)); |
e1571908 AJ |
2240 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); |
2241 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); | |
af12906f | 2242 | tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2243 | } |
2244 | ||
2245 | /* mffs */ | |
99e300ef | 2246 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2247 | { |
76a66253 | 2248 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2249 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2250 | return; |
2251 | } | |
7c58044c | 2252 | gen_reset_fpstatus(); |
af12906f AJ |
2253 | tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
2254 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
79aceca5 FB |
2255 | } |
2256 | ||
2257 | /* mtfsb0 */ | |
99e300ef | 2258 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2259 | { |
fb0eaffc | 2260 | uint8_t crb; |
3b46e624 | 2261 | |
76a66253 | 2262 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2263 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2264 | return; |
2265 | } | |
6e35d524 | 2266 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2267 | gen_reset_fpstatus(); |
6e35d524 | 2268 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2269 | TCGv_i32 t0; |
2270 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2271 | gen_update_nip(ctx, ctx->nip - 4); | |
2272 | t0 = tcg_const_i32(crb); | |
6e35d524 AJ |
2273 | gen_helper_fpscr_clrbit(t0); |
2274 | tcg_temp_free_i32(t0); | |
2275 | } | |
7c58044c | 2276 | if (unlikely(Rc(ctx->opcode) != 0)) { |
e1571908 | 2277 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
7c58044c | 2278 | } |
79aceca5 FB |
2279 | } |
2280 | ||
2281 | /* mtfsb1 */ | |
99e300ef | 2282 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2283 | { |
fb0eaffc | 2284 | uint8_t crb; |
3b46e624 | 2285 | |
76a66253 | 2286 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2287 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2288 | return; |
2289 | } | |
6e35d524 | 2290 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2291 | gen_reset_fpstatus(); |
2292 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2293 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2294 | TCGv_i32 t0; |
2295 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2296 | gen_update_nip(ctx, ctx->nip - 4); | |
2297 | t0 = tcg_const_i32(crb); | |
af12906f | 2298 | gen_helper_fpscr_setbit(t0); |
0f2f39c2 | 2299 | tcg_temp_free_i32(t0); |
af12906f | 2300 | } |
7c58044c | 2301 | if (unlikely(Rc(ctx->opcode) != 0)) { |
e1571908 | 2302 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
7c58044c JM |
2303 | } |
2304 | /* We can raise a differed exception */ | |
af12906f | 2305 | gen_helper_float_check_status(); |
79aceca5 FB |
2306 | } |
2307 | ||
2308 | /* mtfsf */ | |
99e300ef | 2309 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2310 | { |
0f2f39c2 | 2311 | TCGv_i32 t0; |
4911012d | 2312 | int L = ctx->opcode & 0x02000000; |
af12906f | 2313 | |
76a66253 | 2314 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2315 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2316 | return; |
2317 | } | |
eb44b959 AJ |
2318 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2319 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2320 | gen_reset_fpstatus(); |
4911012d BS |
2321 | if (L) |
2322 | t0 = tcg_const_i32(0xff); | |
2323 | else | |
2324 | t0 = tcg_const_i32(FM(ctx->opcode)); | |
af12906f | 2325 | gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2326 | tcg_temp_free_i32(t0); |
7c58044c | 2327 | if (unlikely(Rc(ctx->opcode) != 0)) { |
e1571908 | 2328 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
7c58044c JM |
2329 | } |
2330 | /* We can raise a differed exception */ | |
af12906f | 2331 | gen_helper_float_check_status(); |
79aceca5 FB |
2332 | } |
2333 | ||
2334 | /* mtfsfi */ | |
99e300ef | 2335 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2336 | { |
7c58044c | 2337 | int bf, sh; |
0f2f39c2 AJ |
2338 | TCGv_i64 t0; |
2339 | TCGv_i32 t1; | |
7c58044c | 2340 | |
76a66253 | 2341 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2342 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2343 | return; |
2344 | } | |
7c58044c JM |
2345 | bf = crbD(ctx->opcode) >> 2; |
2346 | sh = 7 - bf; | |
eb44b959 AJ |
2347 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2348 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2349 | gen_reset_fpstatus(); |
0f2f39c2 | 2350 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); |
af12906f AJ |
2351 | t1 = tcg_const_i32(1 << sh); |
2352 | gen_helper_store_fpscr(t0, t1); | |
0f2f39c2 AJ |
2353 | tcg_temp_free_i64(t0); |
2354 | tcg_temp_free_i32(t1); | |
7c58044c | 2355 | if (unlikely(Rc(ctx->opcode) != 0)) { |
e1571908 | 2356 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
7c58044c JM |
2357 | } |
2358 | /* We can raise a differed exception */ | |
af12906f | 2359 | gen_helper_float_check_status(); |
79aceca5 FB |
2360 | } |
2361 | ||
76a66253 JM |
2362 | /*** Addressing modes ***/ |
2363 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2364 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2365 | target_long maskl) | |
76a66253 JM |
2366 | { |
2367 | target_long simm = SIMM(ctx->opcode); | |
2368 | ||
be147d08 | 2369 | simm &= ~maskl; |
76db3ba4 AJ |
2370 | if (rA(ctx->opcode) == 0) { |
2371 | #if defined(TARGET_PPC64) | |
2372 | if (!ctx->sf_mode) { | |
2373 | tcg_gen_movi_tl(EA, (uint32_t)simm); | |
2374 | } else | |
2375 | #endif | |
e2be8d8d | 2376 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2377 | } else if (likely(simm != 0)) { |
e2be8d8d | 2378 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
76db3ba4 AJ |
2379 | #if defined(TARGET_PPC64) |
2380 | if (!ctx->sf_mode) { | |
2381 | tcg_gen_ext32u_tl(EA, EA); | |
2382 | } | |
2383 | #endif | |
2384 | } else { | |
2385 | #if defined(TARGET_PPC64) | |
2386 | if (!ctx->sf_mode) { | |
2387 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2388 | } else | |
2389 | #endif | |
e2be8d8d | 2390 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 | 2391 | } |
76a66253 JM |
2392 | } |
2393 | ||
636aa200 | 2394 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2395 | { |
76db3ba4 AJ |
2396 | if (rA(ctx->opcode) == 0) { |
2397 | #if defined(TARGET_PPC64) | |
2398 | if (!ctx->sf_mode) { | |
2399 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2400 | } else | |
2401 | #endif | |
e2be8d8d | 2402 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 | 2403 | } else { |
e2be8d8d | 2404 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 AJ |
2405 | #if defined(TARGET_PPC64) |
2406 | if (!ctx->sf_mode) { | |
2407 | tcg_gen_ext32u_tl(EA, EA); | |
2408 | } | |
2409 | #endif | |
2410 | } | |
76a66253 JM |
2411 | } |
2412 | ||
636aa200 | 2413 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2414 | { |
76db3ba4 | 2415 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2416 | tcg_gen_movi_tl(EA, 0); |
76db3ba4 AJ |
2417 | } else { |
2418 | #if defined(TARGET_PPC64) | |
2419 | if (!ctx->sf_mode) { | |
2420 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2421 | } else | |
2422 | #endif | |
2423 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2424 | } | |
2425 | } | |
2426 | ||
636aa200 BS |
2427 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2428 | target_long val) | |
76db3ba4 AJ |
2429 | { |
2430 | tcg_gen_addi_tl(ret, arg1, val); | |
2431 | #if defined(TARGET_PPC64) | |
2432 | if (!ctx->sf_mode) { | |
2433 | tcg_gen_ext32u_tl(ret, ret); | |
2434 | } | |
2435 | #endif | |
76a66253 JM |
2436 | } |
2437 | ||
636aa200 | 2438 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 AJ |
2439 | { |
2440 | int l1 = gen_new_label(); | |
2441 | TCGv t0 = tcg_temp_new(); | |
2442 | TCGv_i32 t1, t2; | |
2443 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2444 | gen_update_nip(ctx, ctx->nip - 4); | |
2445 | tcg_gen_andi_tl(t0, EA, mask); | |
2446 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2447 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2448 | t2 = tcg_const_i32(0); | |
2449 | gen_helper_raise_exception_err(t1, t2); | |
2450 | tcg_temp_free_i32(t1); | |
2451 | tcg_temp_free_i32(t2); | |
2452 | gen_set_label(l1); | |
2453 | tcg_temp_free(t0); | |
2454 | } | |
2455 | ||
7863667f | 2456 | /*** Integer load ***/ |
636aa200 | 2457 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2458 | { |
2459 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2460 | } | |
2461 | ||
636aa200 | 2462 | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2463 | { |
2464 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); | |
2465 | } | |
2466 | ||
636aa200 | 2467 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2468 | { |
2469 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); | |
2470 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2471 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2472 | } |
b61f2753 AJ |
2473 | } |
2474 | ||
636aa200 | 2475 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2476 | { |
76db3ba4 | 2477 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2478 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
fa3966a3 | 2479 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2480 | tcg_gen_ext16s_tl(arg1, arg1); |
76db3ba4 AJ |
2481 | } else { |
2482 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); | |
2483 | } | |
b61f2753 AJ |
2484 | } |
2485 | ||
636aa200 | 2486 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2487 | { |
76db3ba4 AJ |
2488 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2489 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2490 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2491 | } |
b61f2753 AJ |
2492 | } |
2493 | ||
76db3ba4 | 2494 | #if defined(TARGET_PPC64) |
636aa200 | 2495 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2496 | { |
a457e7ee | 2497 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2498 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
fa3966a3 AJ |
2499 | tcg_gen_bswap32_tl(arg1, arg1); |
2500 | tcg_gen_ext32s_tl(arg1, arg1); | |
b61f2753 | 2501 | } else |
76db3ba4 | 2502 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
b61f2753 | 2503 | } |
76db3ba4 | 2504 | #endif |
b61f2753 | 2505 | |
636aa200 | 2506 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2507 | { |
76db3ba4 AJ |
2508 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2509 | if (unlikely(ctx->le_mode)) { | |
66896cb8 | 2510 | tcg_gen_bswap64_i64(arg1, arg1); |
76db3ba4 | 2511 | } |
b61f2753 AJ |
2512 | } |
2513 | ||
636aa200 | 2514 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2515 | { |
76db3ba4 | 2516 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2517 | } |
2518 | ||
636aa200 | 2519 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2520 | { |
76db3ba4 | 2521 | if (unlikely(ctx->le_mode)) { |
76db3ba4 AJ |
2522 | TCGv t0 = tcg_temp_new(); |
2523 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2524 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2525 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2526 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2527 | } else { |
2528 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2529 | } | |
b61f2753 AJ |
2530 | } |
2531 | ||
636aa200 | 2532 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2533 | { |
76db3ba4 | 2534 | if (unlikely(ctx->le_mode)) { |
fa3966a3 AJ |
2535 | TCGv t0 = tcg_temp_new(); |
2536 | tcg_gen_ext32u_tl(t0, arg1); | |
2537 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2538 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2539 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2540 | } else { |
2541 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2542 | } | |
b61f2753 AJ |
2543 | } |
2544 | ||
636aa200 | 2545 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2546 | { |
76db3ba4 | 2547 | if (unlikely(ctx->le_mode)) { |
a7812ae4 | 2548 | TCGv_i64 t0 = tcg_temp_new_i64(); |
66896cb8 | 2549 | tcg_gen_bswap64_i64(t0, arg1); |
76db3ba4 | 2550 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
a7812ae4 | 2551 | tcg_temp_free_i64(t0); |
b61f2753 | 2552 | } else |
76db3ba4 | 2553 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2554 | } |
2555 | ||
0c8aacd4 | 2556 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2557 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2558 | { \ |
76db3ba4 AJ |
2559 | TCGv EA; \ |
2560 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2561 | EA = tcg_temp_new(); \ | |
2562 | gen_addr_imm_index(ctx, EA, 0); \ | |
2563 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2564 | tcg_temp_free(EA); \ |
79aceca5 FB |
2565 | } |
2566 | ||
0c8aacd4 | 2567 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2568 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2569 | { \ |
b61f2753 | 2570 | TCGv EA; \ |
76a66253 JM |
2571 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2572 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2573 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2574 | return; \ |
9a64fbe4 | 2575 | } \ |
76db3ba4 | 2576 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2577 | EA = tcg_temp_new(); \ |
9d53c753 | 2578 | if (type == PPC_64B) \ |
76db3ba4 | 2579 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2580 | else \ |
76db3ba4 AJ |
2581 | gen_addr_imm_index(ctx, EA, 0); \ |
2582 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2583 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2584 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2585 | } |
2586 | ||
0c8aacd4 | 2587 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2588 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2589 | { \ |
b61f2753 | 2590 | TCGv EA; \ |
76a66253 JM |
2591 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2592 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2593 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2594 | return; \ |
9a64fbe4 | 2595 | } \ |
76db3ba4 | 2596 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2597 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2598 | gen_addr_reg_index(ctx, EA); \ |
2599 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2600 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2601 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2602 | } |
2603 | ||
0c8aacd4 | 2604 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2605 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2606 | { \ |
76db3ba4 AJ |
2607 | TCGv EA; \ |
2608 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2609 | EA = tcg_temp_new(); \ | |
2610 | gen_addr_reg_index(ctx, EA); \ | |
2611 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2612 | tcg_temp_free(EA); \ |
79aceca5 FB |
2613 | } |
2614 | ||
0c8aacd4 AJ |
2615 | #define GEN_LDS(name, ldop, op, type) \ |
2616 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2617 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2618 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2619 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2620 | |
2621 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2622 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2623 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2624 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2625 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2626 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2627 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2628 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2629 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2630 | /* lwaux */ |
0c8aacd4 | 2631 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2632 | /* lwax */ |
0c8aacd4 | 2633 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2634 | /* ldux */ |
0c8aacd4 | 2635 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2636 | /* ldx */ |
0c8aacd4 | 2637 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2638 | |
2639 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2640 | { |
b61f2753 | 2641 | TCGv EA; |
d9bce9d9 JM |
2642 | if (Rc(ctx->opcode)) { |
2643 | if (unlikely(rA(ctx->opcode) == 0 || | |
2644 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2645 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2646 | return; |
2647 | } | |
2648 | } | |
76db3ba4 | 2649 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2650 | EA = tcg_temp_new(); |
76db3ba4 | 2651 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2652 | if (ctx->opcode & 0x02) { |
2653 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2654 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2655 | } else { |
2656 | /* ld - ldu */ | |
76db3ba4 | 2657 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2658 | } |
d9bce9d9 | 2659 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2660 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2661 | tcg_temp_free(EA); | |
d9bce9d9 | 2662 | } |
99e300ef | 2663 | |
54623277 | 2664 | /* lq */ |
99e300ef | 2665 | static void gen_lq(DisasContext *ctx) |
be147d08 JM |
2666 | { |
2667 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2668 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2669 | #else |
2670 | int ra, rd; | |
b61f2753 | 2671 | TCGv EA; |
be147d08 JM |
2672 | |
2673 | /* Restore CPU state */ | |
76db3ba4 | 2674 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2675 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2676 | return; |
2677 | } | |
2678 | ra = rA(ctx->opcode); | |
2679 | rd = rD(ctx->opcode); | |
2680 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2681 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2682 | return; |
2683 | } | |
76db3ba4 | 2684 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2685 | /* Little-endian mode is not handled */ |
e06fcd75 | 2686 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2687 | return; |
2688 | } | |
76db3ba4 | 2689 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2690 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2691 | gen_addr_imm_index(ctx, EA, 0x0F); |
2692 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2693 | gen_addr_add(ctx, EA, EA, 8); | |
2694 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
b61f2753 | 2695 | tcg_temp_free(EA); |
be147d08 JM |
2696 | #endif |
2697 | } | |
d9bce9d9 | 2698 | #endif |
79aceca5 FB |
2699 | |
2700 | /*** Integer store ***/ | |
0c8aacd4 | 2701 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2702 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2703 | { \ |
76db3ba4 AJ |
2704 | TCGv EA; \ |
2705 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2706 | EA = tcg_temp_new(); \ | |
2707 | gen_addr_imm_index(ctx, EA, 0); \ | |
2708 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2709 | tcg_temp_free(EA); \ |
79aceca5 FB |
2710 | } |
2711 | ||
0c8aacd4 | 2712 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2713 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2714 | { \ |
b61f2753 | 2715 | TCGv EA; \ |
76a66253 | 2716 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2717 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2718 | return; \ |
9a64fbe4 | 2719 | } \ |
76db3ba4 | 2720 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2721 | EA = tcg_temp_new(); \ |
9d53c753 | 2722 | if (type == PPC_64B) \ |
76db3ba4 | 2723 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2724 | else \ |
76db3ba4 AJ |
2725 | gen_addr_imm_index(ctx, EA, 0); \ |
2726 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2727 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2728 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2729 | } |
2730 | ||
0c8aacd4 | 2731 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2732 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2733 | { \ |
b61f2753 | 2734 | TCGv EA; \ |
76a66253 | 2735 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2736 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2737 | return; \ |
9a64fbe4 | 2738 | } \ |
76db3ba4 | 2739 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2740 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2741 | gen_addr_reg_index(ctx, EA); \ |
2742 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2743 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2744 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2745 | } |
2746 | ||
0c8aacd4 | 2747 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
99e300ef | 2748 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2749 | { \ |
76db3ba4 AJ |
2750 | TCGv EA; \ |
2751 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2752 | EA = tcg_temp_new(); \ | |
2753 | gen_addr_reg_index(ctx, EA); \ | |
2754 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2755 | tcg_temp_free(EA); \ |
79aceca5 FB |
2756 | } |
2757 | ||
0c8aacd4 AJ |
2758 | #define GEN_STS(name, stop, op, type) \ |
2759 | GEN_ST(name, stop, op | 0x20, type); \ | |
2760 | GEN_STU(name, stop, op | 0x21, type); \ | |
2761 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2762 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2763 | |
2764 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2765 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2766 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2767 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2768 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2769 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2770 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
2771 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2772 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
2773 | |
2774 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2775 | { |
be147d08 | 2776 | int rs; |
b61f2753 | 2777 | TCGv EA; |
be147d08 JM |
2778 | |
2779 | rs = rS(ctx->opcode); | |
2780 | if ((ctx->opcode & 0x3) == 0x2) { | |
2781 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2782 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2783 | #else |
2784 | /* stq */ | |
76db3ba4 | 2785 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2786 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2787 | return; |
2788 | } | |
2789 | if (unlikely(rs & 1)) { | |
e06fcd75 | 2790 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2791 | return; |
2792 | } | |
76db3ba4 | 2793 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2794 | /* Little-endian mode is not handled */ |
e06fcd75 | 2795 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2796 | return; |
2797 | } | |
76db3ba4 | 2798 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2799 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2800 | gen_addr_imm_index(ctx, EA, 0x03); |
2801 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
2802 | gen_addr_add(ctx, EA, EA, 8); | |
2803 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
b61f2753 | 2804 | tcg_temp_free(EA); |
be147d08 JM |
2805 | #endif |
2806 | } else { | |
2807 | /* std / stdu */ | |
2808 | if (Rc(ctx->opcode)) { | |
2809 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2810 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2811 | return; |
2812 | } | |
2813 | } | |
76db3ba4 | 2814 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2815 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2816 | gen_addr_imm_index(ctx, EA, 0x03); |
2817 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 2818 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2819 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2820 | tcg_temp_free(EA); | |
d9bce9d9 | 2821 | } |
d9bce9d9 JM |
2822 | } |
2823 | #endif | |
79aceca5 FB |
2824 | /*** Integer load and store with byte reverse ***/ |
2825 | /* lhbrx */ | |
86178a57 | 2826 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2827 | { |
76db3ba4 AJ |
2828 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2829 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2830 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2831 | } |
b61f2753 | 2832 | } |
0c8aacd4 | 2833 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2834 | |
79aceca5 | 2835 | /* lwbrx */ |
86178a57 | 2836 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2837 | { |
76db3ba4 AJ |
2838 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2839 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2840 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2841 | } |
b61f2753 | 2842 | } |
0c8aacd4 | 2843 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2844 | |
79aceca5 | 2845 | /* sthbrx */ |
86178a57 | 2846 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2847 | { |
76db3ba4 | 2848 | if (likely(!ctx->le_mode)) { |
76db3ba4 AJ |
2849 | TCGv t0 = tcg_temp_new(); |
2850 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2851 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2852 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2853 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2854 | } else { |
2855 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2856 | } | |
b61f2753 | 2857 | } |
0c8aacd4 | 2858 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 2859 | |
79aceca5 | 2860 | /* stwbrx */ |
86178a57 | 2861 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2862 | { |
76db3ba4 | 2863 | if (likely(!ctx->le_mode)) { |
fa3966a3 AJ |
2864 | TCGv t0 = tcg_temp_new(); |
2865 | tcg_gen_ext32u_tl(t0, arg1); | |
2866 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2867 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2868 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2869 | } else { |
2870 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2871 | } | |
b61f2753 | 2872 | } |
0c8aacd4 | 2873 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 FB |
2874 | |
2875 | /*** Integer load and store multiple ***/ | |
99e300ef | 2876 | |
54623277 | 2877 | /* lmw */ |
99e300ef | 2878 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2879 | { |
76db3ba4 AJ |
2880 | TCGv t0; |
2881 | TCGv_i32 t1; | |
2882 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2883 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2884 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2885 | t0 = tcg_temp_new(); |
2886 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2887 | gen_addr_imm_index(ctx, t0, 0); | |
ff4a62cd AJ |
2888 | gen_helper_lmw(t0, t1); |
2889 | tcg_temp_free(t0); | |
2890 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2891 | } |
2892 | ||
2893 | /* stmw */ | |
99e300ef | 2894 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2895 | { |
76db3ba4 AJ |
2896 | TCGv t0; |
2897 | TCGv_i32 t1; | |
2898 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2899 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2900 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2901 | t0 = tcg_temp_new(); |
2902 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2903 | gen_addr_imm_index(ctx, t0, 0); | |
ff4a62cd AJ |
2904 | gen_helper_stmw(t0, t1); |
2905 | tcg_temp_free(t0); | |
2906 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2907 | } |
2908 | ||
2909 | /*** Integer load and store strings ***/ | |
54623277 | 2910 | |
79aceca5 | 2911 | /* lswi */ |
3fc6c082 | 2912 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
2913 | * rA is in the range of registers to be loaded. |
2914 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
2915 | * For now, I'll follow the spec... | |
2916 | */ | |
99e300ef | 2917 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 2918 | { |
dfbc799d AJ |
2919 | TCGv t0; |
2920 | TCGv_i32 t1, t2; | |
79aceca5 FB |
2921 | int nb = NB(ctx->opcode); |
2922 | int start = rD(ctx->opcode); | |
9a64fbe4 | 2923 | int ra = rA(ctx->opcode); |
79aceca5 FB |
2924 | int nr; |
2925 | ||
2926 | if (nb == 0) | |
2927 | nb = 32; | |
2928 | nr = nb / 4; | |
76a66253 JM |
2929 | if (unlikely(((start + nr) > 32 && |
2930 | start <= ra && (start + nr - 32) > ra) || | |
2931 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 2932 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 2933 | return; |
297d8e62 | 2934 | } |
76db3ba4 | 2935 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 2936 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2937 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 2938 | t0 = tcg_temp_new(); |
76db3ba4 | 2939 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
2940 | t1 = tcg_const_i32(nb); |
2941 | t2 = tcg_const_i32(start); | |
2942 | gen_helper_lsw(t0, t1, t2); | |
2943 | tcg_temp_free(t0); | |
2944 | tcg_temp_free_i32(t1); | |
2945 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2946 | } |
2947 | ||
2948 | /* lswx */ | |
99e300ef | 2949 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 2950 | { |
76db3ba4 AJ |
2951 | TCGv t0; |
2952 | TCGv_i32 t1, t2, t3; | |
2953 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2954 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2955 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2956 | t0 = tcg_temp_new(); |
2957 | gen_addr_reg_index(ctx, t0); | |
2958 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2959 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
2960 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
dfbc799d AJ |
2961 | gen_helper_lswx(t0, t1, t2, t3); |
2962 | tcg_temp_free(t0); | |
2963 | tcg_temp_free_i32(t1); | |
2964 | tcg_temp_free_i32(t2); | |
2965 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
2966 | } |
2967 | ||
2968 | /* stswi */ | |
99e300ef | 2969 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 2970 | { |
76db3ba4 AJ |
2971 | TCGv t0; |
2972 | TCGv_i32 t1, t2; | |
4b3686fa | 2973 | int nb = NB(ctx->opcode); |
76db3ba4 | 2974 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 2975 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2976 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2977 | t0 = tcg_temp_new(); |
2978 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
2979 | if (nb == 0) |
2980 | nb = 32; | |
dfbc799d | 2981 | t1 = tcg_const_i32(nb); |
76db3ba4 | 2982 | t2 = tcg_const_i32(rS(ctx->opcode)); |
dfbc799d AJ |
2983 | gen_helper_stsw(t0, t1, t2); |
2984 | tcg_temp_free(t0); | |
2985 | tcg_temp_free_i32(t1); | |
2986 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2987 | } |
2988 | ||
2989 | /* stswx */ | |
99e300ef | 2990 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 2991 | { |
76db3ba4 AJ |
2992 | TCGv t0; |
2993 | TCGv_i32 t1, t2; | |
2994 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 2995 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 2996 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2997 | t0 = tcg_temp_new(); |
2998 | gen_addr_reg_index(ctx, t0); | |
2999 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3000 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3001 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3002 | t2 = tcg_const_i32(rS(ctx->opcode)); |
dfbc799d AJ |
3003 | gen_helper_stsw(t0, t1, t2); |
3004 | tcg_temp_free(t0); | |
3005 | tcg_temp_free_i32(t1); | |
3006 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3007 | } |
3008 | ||
3009 | /*** Memory synchronisation ***/ | |
3010 | /* eieio */ | |
99e300ef | 3011 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3012 | { |
79aceca5 FB |
3013 | } |
3014 | ||
3015 | /* isync */ | |
99e300ef | 3016 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3017 | { |
e06fcd75 | 3018 | gen_stop_exception(ctx); |
79aceca5 FB |
3019 | } |
3020 | ||
111bfab3 | 3021 | /* lwarx */ |
99e300ef | 3022 | static void gen_lwarx(DisasContext *ctx) |
79aceca5 | 3023 | { |
76db3ba4 | 3024 | TCGv t0; |
18b21a2f | 3025 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3026 | gen_set_access_type(ctx, ACCESS_RES); |
3027 | t0 = tcg_temp_local_new(); | |
3028 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3029 | gen_check_align(ctx, t0, 0x03); |
18b21a2f | 3030 | gen_qemu_ld32u(ctx, gpr, t0); |
cf360a32 | 3031 | tcg_gen_mov_tl(cpu_reserve, t0); |
18b21a2f | 3032 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
cf360a32 | 3033 | tcg_temp_free(t0); |
79aceca5 FB |
3034 | } |
3035 | ||
4425265b NF |
3036 | #if defined(CONFIG_USER_ONLY) |
3037 | static void gen_conditional_store (DisasContext *ctx, TCGv EA, | |
3038 | int reg, int size) | |
3039 | { | |
3040 | TCGv t0 = tcg_temp_new(); | |
3041 | uint32_t save_exception = ctx->exception; | |
3042 | ||
3043 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea)); | |
3044 | tcg_gen_movi_tl(t0, (size << 5) | reg); | |
3045 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info)); | |
3046 | tcg_temp_free(t0); | |
3047 | gen_update_nip(ctx, ctx->nip-4); | |
3048 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3049 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3050 | ctx->exception = save_exception; | |
3051 | } | |
3052 | #endif | |
3053 | ||
79aceca5 | 3054 | /* stwcx. */ |
e8eaa2c0 | 3055 | static void gen_stwcx_(DisasContext *ctx) |
79aceca5 | 3056 | { |
76db3ba4 AJ |
3057 | TCGv t0; |
3058 | gen_set_access_type(ctx, ACCESS_RES); | |
3059 | t0 = tcg_temp_local_new(); | |
3060 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3061 | gen_check_align(ctx, t0, 0x03); |
4425265b NF |
3062 | #if defined(CONFIG_USER_ONLY) |
3063 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); | |
3064 | #else | |
3065 | { | |
3066 | int l1; | |
3067 | ||
3068 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
3069 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
3070 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
3071 | l1 = gen_new_label(); | |
3072 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3073 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3074 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3075 | gen_set_label(l1); | |
3076 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3077 | } | |
3078 | #endif | |
cf360a32 | 3079 | tcg_temp_free(t0); |
79aceca5 FB |
3080 | } |
3081 | ||
426613db | 3082 | #if defined(TARGET_PPC64) |
426613db | 3083 | /* ldarx */ |
99e300ef | 3084 | static void gen_ldarx(DisasContext *ctx) |
426613db | 3085 | { |
76db3ba4 | 3086 | TCGv t0; |
18b21a2f | 3087 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3088 | gen_set_access_type(ctx, ACCESS_RES); |
3089 | t0 = tcg_temp_local_new(); | |
3090 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3091 | gen_check_align(ctx, t0, 0x07); |
18b21a2f | 3092 | gen_qemu_ld64(ctx, gpr, t0); |
cf360a32 | 3093 | tcg_gen_mov_tl(cpu_reserve, t0); |
18b21a2f | 3094 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
cf360a32 | 3095 | tcg_temp_free(t0); |
426613db JM |
3096 | } |
3097 | ||
3098 | /* stdcx. */ | |
e8eaa2c0 | 3099 | static void gen_stdcx_(DisasContext *ctx) |
426613db | 3100 | { |
76db3ba4 AJ |
3101 | TCGv t0; |
3102 | gen_set_access_type(ctx, ACCESS_RES); | |
3103 | t0 = tcg_temp_local_new(); | |
3104 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3105 | gen_check_align(ctx, t0, 0x07); |
4425265b NF |
3106 | #if defined(CONFIG_USER_ONLY) |
3107 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); | |
3108 | #else | |
3109 | { | |
3110 | int l1; | |
3111 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
3112 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
3113 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
3114 | l1 = gen_new_label(); | |
3115 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3116 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3117 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3118 | gen_set_label(l1); | |
3119 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3120 | } | |
3121 | #endif | |
cf360a32 | 3122 | tcg_temp_free(t0); |
426613db JM |
3123 | } |
3124 | #endif /* defined(TARGET_PPC64) */ | |
3125 | ||
79aceca5 | 3126 | /* sync */ |
99e300ef | 3127 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3128 | { |
79aceca5 FB |
3129 | } |
3130 | ||
0db1b20e | 3131 | /* wait */ |
99e300ef | 3132 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3133 | { |
931ff272 AJ |
3134 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3135 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted)); | |
3136 | tcg_temp_free_i32(t0); | |
0db1b20e | 3137 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3138 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3139 | } |
3140 | ||
79aceca5 | 3141 | /*** Floating-point load ***/ |
a0d7d5a7 | 3142 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3143 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3144 | { \ |
a0d7d5a7 | 3145 | TCGv EA; \ |
76a66253 | 3146 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3147 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3148 | return; \ |
3149 | } \ | |
76db3ba4 | 3150 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3151 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3152 | gen_addr_imm_index(ctx, EA, 0); \ |
3153 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3154 | tcg_temp_free(EA); \ |
79aceca5 FB |
3155 | } |
3156 | ||
a0d7d5a7 | 3157 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3158 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3159 | { \ |
a0d7d5a7 | 3160 | TCGv EA; \ |
76a66253 | 3161 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3162 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3163 | return; \ |
3164 | } \ | |
76a66253 | 3165 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3166 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3167 | return; \ |
9a64fbe4 | 3168 | } \ |
76db3ba4 | 3169 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3170 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3171 | gen_addr_imm_index(ctx, EA, 0); \ |
3172 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3173 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3174 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3175 | } |
3176 | ||
a0d7d5a7 | 3177 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3178 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3179 | { \ |
a0d7d5a7 | 3180 | TCGv EA; \ |
76a66253 | 3181 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3182 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3183 | return; \ |
3184 | } \ | |
76a66253 | 3185 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3186 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3187 | return; \ |
9a64fbe4 | 3188 | } \ |
76db3ba4 | 3189 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3190 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3191 | gen_addr_reg_index(ctx, EA); \ |
3192 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3193 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3194 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3195 | } |
3196 | ||
a0d7d5a7 | 3197 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3198 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3199 | { \ |
a0d7d5a7 | 3200 | TCGv EA; \ |
76a66253 | 3201 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3202 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3203 | return; \ |
3204 | } \ | |
76db3ba4 | 3205 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3206 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3207 | gen_addr_reg_index(ctx, EA); \ |
3208 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3209 | tcg_temp_free(EA); \ |
79aceca5 FB |
3210 | } |
3211 | ||
a0d7d5a7 AJ |
3212 | #define GEN_LDFS(name, ldop, op, type) \ |
3213 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3214 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3215 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3216 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3217 | ||
636aa200 | 3218 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3219 | { |
3220 | TCGv t0 = tcg_temp_new(); | |
3221 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3222 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3223 | tcg_gen_trunc_tl_i32(t1, t0); |
3224 | tcg_temp_free(t0); | |
3225 | gen_helper_float32_to_float64(arg1, t1); | |
3226 | tcg_temp_free_i32(t1); | |
3227 | } | |
79aceca5 | 3228 | |
a0d7d5a7 AJ |
3229 | /* lfd lfdu lfdux lfdx */ |
3230 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3231 | /* lfs lfsu lfsux lfsx */ | |
3232 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 FB |
3233 | |
3234 | /*** Floating-point store ***/ | |
a0d7d5a7 | 3235 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3236 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3237 | { \ |
a0d7d5a7 | 3238 | TCGv EA; \ |
76a66253 | 3239 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3240 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3241 | return; \ |
3242 | } \ | |
76db3ba4 | 3243 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3244 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3245 | gen_addr_imm_index(ctx, EA, 0); \ |
3246 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3247 | tcg_temp_free(EA); \ |
79aceca5 FB |
3248 | } |
3249 | ||
a0d7d5a7 | 3250 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3251 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3252 | { \ |
a0d7d5a7 | 3253 | TCGv EA; \ |
76a66253 | 3254 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3255 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3256 | return; \ |
3257 | } \ | |
76a66253 | 3258 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3259 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3260 | return; \ |
9a64fbe4 | 3261 | } \ |
76db3ba4 | 3262 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3263 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3264 | gen_addr_imm_index(ctx, EA, 0); \ |
3265 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3266 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3267 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3268 | } |
3269 | ||
a0d7d5a7 | 3270 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3271 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3272 | { \ |
a0d7d5a7 | 3273 | TCGv EA; \ |
76a66253 | 3274 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3275 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3276 | return; \ |
3277 | } \ | |
76a66253 | 3278 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3279 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3280 | return; \ |
9a64fbe4 | 3281 | } \ |
76db3ba4 | 3282 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3283 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3284 | gen_addr_reg_index(ctx, EA); \ |
3285 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3286 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3287 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3288 | } |
3289 | ||
a0d7d5a7 | 3290 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3291 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3292 | { \ |
a0d7d5a7 | 3293 | TCGv EA; \ |
76a66253 | 3294 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3295 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3296 | return; \ |
3297 | } \ | |
76db3ba4 | 3298 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3299 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3300 | gen_addr_reg_index(ctx, EA); \ |
3301 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3302 | tcg_temp_free(EA); \ |
79aceca5 FB |
3303 | } |
3304 | ||
a0d7d5a7 AJ |
3305 | #define GEN_STFS(name, stop, op, type) \ |
3306 | GEN_STF(name, stop, op | 0x20, type); \ | |
3307 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3308 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3309 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3310 | ||
636aa200 | 3311 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3312 | { |
3313 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3314 | TCGv t1 = tcg_temp_new(); | |
3315 | gen_helper_float64_to_float32(t0, arg1); | |
3316 | tcg_gen_extu_i32_tl(t1, t0); | |
3317 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3318 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3319 | tcg_temp_free(t1); |
3320 | } | |
79aceca5 FB |
3321 | |
3322 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3323 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3324 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3325 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 FB |
3326 | |
3327 | /* Optional: */ | |
636aa200 | 3328 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3329 | { |
3330 | TCGv t0 = tcg_temp_new(); | |
3331 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3332 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3333 | tcg_temp_free(t0); |
3334 | } | |
79aceca5 | 3335 | /* stfiwx */ |
a0d7d5a7 | 3336 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 FB |
3337 | |
3338 | /*** Branch ***/ | |
636aa200 | 3339 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 FB |
3340 | { |
3341 | TranslationBlock *tb; | |
3342 | tb = ctx->tb; | |
a2ffb812 AJ |
3343 | #if defined(TARGET_PPC64) |
3344 | if (!ctx->sf_mode) | |
3345 | dest = (uint32_t) dest; | |
3346 | #endif | |
57fec1fe | 3347 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3348 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3349 | tcg_gen_goto_tb(n); |
a2ffb812 | 3350 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
4b4a72e5 | 3351 | tcg_gen_exit_tb((tcg_target_long)tb + n); |
c1942362 | 3352 | } else { |
a2ffb812 | 3353 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3354 | if (unlikely(ctx->singlestep_enabled)) { |
3355 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3356 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
8cbcb4fa AJ |
3357 | ctx->exception == POWERPC_EXCP_BRANCH) { |
3358 | target_ulong tmp = ctx->nip; | |
3359 | ctx->nip = dest; | |
e06fcd75 | 3360 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3361 | ctx->nip = tmp; |
3362 | } | |
3363 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3364 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3365 | } |
3366 | } | |
57fec1fe | 3367 | tcg_gen_exit_tb(0); |
c1942362 | 3368 | } |
c53be334 FB |
3369 | } |
3370 | ||
636aa200 | 3371 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f JM |
3372 | { |
3373 | #if defined(TARGET_PPC64) | |
a2ffb812 AJ |
3374 | if (ctx->sf_mode == 0) |
3375 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); | |
e1833e1f JM |
3376 | else |
3377 | #endif | |
a2ffb812 | 3378 | tcg_gen_movi_tl(cpu_lr, nip); |
e1833e1f JM |
3379 | } |
3380 | ||
79aceca5 | 3381 | /* b ba bl bla */ |
99e300ef | 3382 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3383 | { |
76a66253 | 3384 | target_ulong li, target; |
38a64f9d | 3385 | |
8cbcb4fa | 3386 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3387 | /* sign extend LI */ |
76a66253 | 3388 | #if defined(TARGET_PPC64) |
d9bce9d9 JM |
3389 | if (ctx->sf_mode) |
3390 | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; | |
3391 | else | |
76a66253 | 3392 | #endif |
d9bce9d9 | 3393 | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
76a66253 | 3394 | if (likely(AA(ctx->opcode) == 0)) |
046d6672 | 3395 | target = ctx->nip + li - 4; |
79aceca5 | 3396 | else |
9a64fbe4 | 3397 | target = li; |
e1833e1f JM |
3398 | if (LK(ctx->opcode)) |
3399 | gen_setlr(ctx, ctx->nip); | |
c1942362 | 3400 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3401 | } |
3402 | ||
e98a6e40 FB |
3403 | #define BCOND_IM 0 |
3404 | #define BCOND_LR 1 | |
3405 | #define BCOND_CTR 2 | |
3406 | ||
636aa200 | 3407 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3408 | { |
d9bce9d9 | 3409 | uint32_t bo = BO(ctx->opcode); |
05f92404 | 3410 | int l1; |
a2ffb812 | 3411 | TCGv target; |
e98a6e40 | 3412 | |
8cbcb4fa | 3413 | ctx->exception = POWERPC_EXCP_BRANCH; |
a2ffb812 | 3414 | if (type == BCOND_LR || type == BCOND_CTR) { |
a7812ae4 | 3415 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3416 | if (type == BCOND_CTR) |
3417 | tcg_gen_mov_tl(target, cpu_ctr); | |
3418 | else | |
3419 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3420 | } else { |
3421 | TCGV_UNUSED(target); | |
e98a6e40 | 3422 | } |
e1833e1f JM |
3423 | if (LK(ctx->opcode)) |
3424 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3425 | l1 = gen_new_label(); |
3426 | if ((bo & 0x4) == 0) { | |
3427 | /* Decrement and test CTR */ | |
a7812ae4 | 3428 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3429 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3430 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3431 | return; |
3432 | } | |
3433 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
d9bce9d9 | 3434 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3435 | if (!ctx->sf_mode) |
3436 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3437 | else | |
d9bce9d9 | 3438 | #endif |
a2ffb812 AJ |
3439 | tcg_gen_mov_tl(temp, cpu_ctr); |
3440 | if (bo & 0x2) { | |
3441 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3442 | } else { | |
3443 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3444 | } |
a7812ae4 | 3445 | tcg_temp_free(temp); |
a2ffb812 AJ |
3446 | } |
3447 | if ((bo & 0x10) == 0) { | |
3448 | /* Test CR */ | |
3449 | uint32_t bi = BI(ctx->opcode); | |
3450 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3451 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3452 | |
d9bce9d9 | 3453 | if (bo & 0x8) { |
a2ffb812 AJ |
3454 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3455 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3456 | } else { |
a2ffb812 AJ |
3457 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3458 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3459 | } |
a7812ae4 | 3460 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3461 | } |
e98a6e40 | 3462 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3463 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3464 | if (likely(AA(ctx->opcode) == 0)) { | |
3465 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3466 | } else { | |
3467 | gen_goto_tb(ctx, 0, li); | |
3468 | } | |
c53be334 | 3469 | gen_set_label(l1); |
c1942362 | 3470 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3471 | } else { |
d9bce9d9 | 3472 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3473 | if (!(ctx->sf_mode)) |
3474 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); | |
3475 | else | |
3476 | #endif | |
3477 | tcg_gen_andi_tl(cpu_nip, target, ~3); | |
3478 | tcg_gen_exit_tb(0); | |
3479 | gen_set_label(l1); | |
3480 | #if defined(TARGET_PPC64) | |
3481 | if (!(ctx->sf_mode)) | |
3482 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); | |
d9bce9d9 JM |
3483 | else |
3484 | #endif | |
a2ffb812 | 3485 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
57fec1fe | 3486 | tcg_gen_exit_tb(0); |
08e46e54 | 3487 | } |
e98a6e40 FB |
3488 | } |
3489 | ||
99e300ef | 3490 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3491 | { |
e98a6e40 FB |
3492 | gen_bcond(ctx, BCOND_IM); |
3493 | } | |
3494 | ||
99e300ef | 3495 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3496 | { |
e98a6e40 FB |
3497 | gen_bcond(ctx, BCOND_CTR); |
3498 | } | |
3499 | ||
99e300ef | 3500 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3501 | { |
e98a6e40 FB |
3502 | gen_bcond(ctx, BCOND_LR); |
3503 | } | |
79aceca5 FB |
3504 | |
3505 | /*** Condition register logical ***/ | |
e1571908 | 3506 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3507 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3508 | { \ |
fc0d441e JM |
3509 | uint8_t bitmask; \ |
3510 | int sh; \ | |
a7812ae4 | 3511 | TCGv_i32 t0, t1; \ |
fc0d441e | 3512 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3513 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3514 | if (sh > 0) \ |
fea0c503 | 3515 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3516 | else if (sh < 0) \ |
fea0c503 | 3517 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3518 | else \ |
fea0c503 | 3519 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3520 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3521 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3522 | if (sh > 0) \ | |
fea0c503 | 3523 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3524 | else if (sh < 0) \ |
fea0c503 | 3525 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3526 | else \ |
fea0c503 AJ |
3527 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3528 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3529 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3530 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3531 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3532 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3533 | tcg_temp_free_i32(t0); \ |
3534 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3535 | } |
3536 | ||
3537 | /* crand */ | |
e1571908 | 3538 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3539 | /* crandc */ |
e1571908 | 3540 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3541 | /* creqv */ |
e1571908 | 3542 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3543 | /* crnand */ |
e1571908 | 3544 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3545 | /* crnor */ |
e1571908 | 3546 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3547 | /* cror */ |
e1571908 | 3548 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3549 | /* crorc */ |
e1571908 | 3550 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3551 | /* crxor */ |
e1571908 | 3552 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3553 | |
54623277 | 3554 | /* mcrf */ |
99e300ef | 3555 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3556 | { |
47e4661c | 3557 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3558 | } |
3559 | ||
3560 | /*** System linkage ***/ | |
99e300ef | 3561 | |
54623277 | 3562 | /* rfi (mem_idx only) */ |
99e300ef | 3563 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3564 | { |
9a64fbe4 | 3565 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3566 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3567 | #else |
3568 | /* Restore CPU state */ | |
76db3ba4 | 3569 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3570 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3571 | return; |
9a64fbe4 | 3572 | } |
d72a19f7 | 3573 | gen_helper_rfi(); |
e06fcd75 | 3574 | gen_sync_exception(ctx); |
9a64fbe4 | 3575 | #endif |
79aceca5 FB |
3576 | } |
3577 | ||
426613db | 3578 | #if defined(TARGET_PPC64) |
99e300ef | 3579 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3580 | { |
3581 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3582 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3583 | #else |
3584 | /* Restore CPU state */ | |
76db3ba4 | 3585 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3586 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3587 | return; |
3588 | } | |
d72a19f7 | 3589 | gen_helper_rfid(); |
e06fcd75 | 3590 | gen_sync_exception(ctx); |
426613db JM |
3591 | #endif |
3592 | } | |
426613db | 3593 | |
99e300ef | 3594 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3595 | { |
3596 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3597 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3598 | #else |
3599 | /* Restore CPU state */ | |
76db3ba4 | 3600 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 3601 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3602 | return; |
3603 | } | |
d72a19f7 | 3604 | gen_helper_hrfid(); |
e06fcd75 | 3605 | gen_sync_exception(ctx); |
be147d08 JM |
3606 | #endif |
3607 | } | |
3608 | #endif | |
3609 | ||
79aceca5 | 3610 | /* sc */ |
417bf010 JM |
3611 | #if defined(CONFIG_USER_ONLY) |
3612 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3613 | #else | |
3614 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3615 | #endif | |
99e300ef | 3616 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3617 | { |
e1833e1f JM |
3618 | uint32_t lev; |
3619 | ||
3620 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3621 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3622 | } |
3623 | ||
3624 | /*** Trap ***/ | |
99e300ef | 3625 | |
54623277 | 3626 | /* tw */ |
99e300ef | 3627 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3628 | { |
cab3bee2 | 3629 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3630 | /* Update the nip since this might generate a trap exception */ |
3631 | gen_update_nip(ctx, ctx->nip); | |
cab3bee2 AJ |
3632 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3633 | tcg_temp_free_i32(t0); | |
79aceca5 FB |
3634 | } |
3635 | ||
3636 | /* twi */ | |
99e300ef | 3637 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3638 | { |
cab3bee2 AJ |
3639 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3640 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3641 | /* Update the nip since this might generate a trap exception */ |
3642 | gen_update_nip(ctx, ctx->nip); | |
cab3bee2 AJ |
3643 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3644 | tcg_temp_free(t0); | |
3645 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3646 | } |
3647 | ||
d9bce9d9 JM |
3648 | #if defined(TARGET_PPC64) |
3649 | /* td */ | |
99e300ef | 3650 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3651 | { |
cab3bee2 | 3652 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3653 | /* Update the nip since this might generate a trap exception */ |
3654 | gen_update_nip(ctx, ctx->nip); | |
cab3bee2 AJ |
3655 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3656 | tcg_temp_free_i32(t0); | |
d9bce9d9 JM |
3657 | } |
3658 | ||
3659 | /* tdi */ | |
99e300ef | 3660 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3661 | { |
cab3bee2 AJ |
3662 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3663 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3664 | /* Update the nip since this might generate a trap exception */ |
3665 | gen_update_nip(ctx, ctx->nip); | |
cab3bee2 AJ |
3666 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3667 | tcg_temp_free(t0); | |
3668 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3669 | } |
3670 | #endif | |
3671 | ||
79aceca5 | 3672 | /*** Processor control ***/ |
99e300ef | 3673 | |
54623277 | 3674 | /* mcrxr */ |
99e300ef | 3675 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3676 | { |
3d7b417e AJ |
3677 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer); |
3678 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA); | |
269f3e95 | 3679 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); |
79aceca5 FB |
3680 | } |
3681 | ||
0cfe11ea | 3682 | /* mfcr mfocrf */ |
99e300ef | 3683 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3684 | { |
76a66253 | 3685 | uint32_t crm, crn; |
3b46e624 | 3686 | |
76a66253 JM |
3687 | if (likely(ctx->opcode & 0x00100000)) { |
3688 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3689 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3690 | crn = ctz32 (crm); |
e1571908 | 3691 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3692 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3693 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3694 | } |
d9bce9d9 | 3695 | } else { |
651721b2 AJ |
3696 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3697 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3698 | tcg_gen_shli_i32(t0, t0, 4); | |
3699 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3700 | tcg_gen_shli_i32(t0, t0, 4); | |
3701 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3702 | tcg_gen_shli_i32(t0, t0, 4); | |
3703 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3704 | tcg_gen_shli_i32(t0, t0, 4); | |
3705 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3706 | tcg_gen_shli_i32(t0, t0, 4); | |
3707 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3708 | tcg_gen_shli_i32(t0, t0, 4); | |
3709 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3710 | tcg_gen_shli_i32(t0, t0, 4); | |
3711 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3712 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3713 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3714 | } |
79aceca5 FB |
3715 | } |
3716 | ||
3717 | /* mfmsr */ | |
99e300ef | 3718 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3719 | { |
9a64fbe4 | 3720 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3721 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3722 | #else |
76db3ba4 | 3723 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3724 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3725 | return; |
9a64fbe4 | 3726 | } |
6527f6ea | 3727 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 3728 | #endif |
79aceca5 FB |
3729 | } |
3730 | ||
7b13448f | 3731 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3fc6c082 | 3732 | { |
7b13448f | 3733 | #if 0 |
3fc6c082 FB |
3734 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3735 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3736 | #endif |
3fc6c082 FB |
3737 | } |
3738 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3739 | |
79aceca5 | 3740 | /* mfspr */ |
636aa200 | 3741 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 3742 | { |
45d827d2 | 3743 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
3744 | uint32_t sprn = SPR(ctx->opcode); |
3745 | ||
3fc6c082 | 3746 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 3747 | if (ctx->mem_idx == 2) |
be147d08 | 3748 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 3749 | else if (ctx->mem_idx) |
3fc6c082 FB |
3750 | read_cb = ctx->spr_cb[sprn].oea_read; |
3751 | else | |
9a64fbe4 | 3752 | #endif |
3fc6c082 | 3753 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
3754 | if (likely(read_cb != NULL)) { |
3755 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 3756 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
3757 | } else { |
3758 | /* Privilege exception */ | |
9fceefa7 JM |
3759 | /* This is a hack to avoid warnings when running Linux: |
3760 | * this OS breaks the PowerPC virtualisation model, | |
3761 | * allowing userland application to read the PVR | |
3762 | */ | |
3763 | if (sprn != SPR_PVR) { | |
93fcfe39 | 3764 | qemu_log("Trying to read privileged spr %d %03x at " |
90e189ec BS |
3765 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3766 | printf("Trying to read privileged spr %d %03x at " | |
3767 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); | |
f24e5695 | 3768 | } |
e06fcd75 | 3769 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 3770 | } |
3fc6c082 FB |
3771 | } else { |
3772 | /* Not defined */ | |
93fcfe39 | 3773 | qemu_log("Trying to read invalid spr %d %03x at " |
90e189ec BS |
3774 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3775 | printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 3776 | sprn, sprn, ctx->nip); |
e06fcd75 | 3777 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 3778 | } |
79aceca5 FB |
3779 | } |
3780 | ||
99e300ef | 3781 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 3782 | { |
3fc6c082 | 3783 | gen_op_mfspr(ctx); |
76a66253 | 3784 | } |
3fc6c082 FB |
3785 | |
3786 | /* mftb */ | |
99e300ef | 3787 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
3788 | { |
3789 | gen_op_mfspr(ctx); | |
79aceca5 FB |
3790 | } |
3791 | ||
0cfe11ea | 3792 | /* mtcrf mtocrf*/ |
99e300ef | 3793 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 3794 | { |
76a66253 | 3795 | uint32_t crm, crn; |
3b46e624 | 3796 | |
76a66253 | 3797 | crm = CRM(ctx->opcode); |
8dd640e4 | 3798 | if (likely((ctx->opcode & 0x00100000))) { |
3799 | if (crm && ((crm & (crm - 1)) == 0)) { | |
3800 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 3801 | crn = ctz32 (crm); |
8dd640e4 | 3802 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
3803 | tcg_gen_shri_i32(temp, temp, crn * 4); |
3804 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 3805 | tcg_temp_free_i32(temp); |
3806 | } | |
76a66253 | 3807 | } else { |
651721b2 AJ |
3808 | TCGv_i32 temp = tcg_temp_new_i32(); |
3809 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
3810 | for (crn = 0 ; crn < 8 ; crn++) { | |
3811 | if (crm & (1 << crn)) { | |
3812 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
3813 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
3814 | } | |
3815 | } | |
a7812ae4 | 3816 | tcg_temp_free_i32(temp); |
76a66253 | 3817 | } |
79aceca5 FB |
3818 | } |
3819 | ||
3820 | /* mtmsr */ | |
426613db | 3821 | #if defined(TARGET_PPC64) |
99e300ef | 3822 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
3823 | { |
3824 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3825 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 3826 | #else |
76db3ba4 | 3827 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3828 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
3829 | return; |
3830 | } | |
be147d08 JM |
3831 | if (ctx->opcode & 0x00010000) { |
3832 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3833 | TCGv t0 = tcg_temp_new(); |
3834 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
3835 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
3836 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
3837 | tcg_temp_free(t0); | |
be147d08 | 3838 | } else { |
056b05f8 JM |
3839 | /* XXX: we need to update nip before the store |
3840 | * if we enter power saving mode, we will exit the loop | |
3841 | * directly from ppc_store_msr | |
3842 | */ | |
be147d08 | 3843 | gen_update_nip(ctx, ctx->nip); |
6527f6ea | 3844 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
3845 | /* Must stop the translation as machine state (may have) changed */ |
3846 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 3847 | gen_stop_exception(ctx); |
be147d08 | 3848 | } |
426613db JM |
3849 | #endif |
3850 | } | |
3851 | #endif | |
3852 | ||
99e300ef | 3853 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 3854 | { |
9a64fbe4 | 3855 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3856 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3857 | #else |
76db3ba4 | 3858 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3859 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3860 | return; |
9a64fbe4 | 3861 | } |
be147d08 JM |
3862 | if (ctx->opcode & 0x00010000) { |
3863 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3864 | TCGv t0 = tcg_temp_new(); |
3865 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
3866 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
3867 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
3868 | tcg_temp_free(t0); | |
be147d08 | 3869 | } else { |
056b05f8 JM |
3870 | /* XXX: we need to update nip before the store |
3871 | * if we enter power saving mode, we will exit the loop | |
3872 | * directly from ppc_store_msr | |
3873 | */ | |
be147d08 | 3874 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 3875 | #if defined(TARGET_PPC64) |
6527f6ea AJ |
3876 | if (!ctx->sf_mode) { |
3877 | TCGv t0 = tcg_temp_new(); | |
3878 | TCGv t1 = tcg_temp_new(); | |
3879 | tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL); | |
3880 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); | |
3881 | tcg_gen_or_tl(t0, t0, t1); | |
3882 | tcg_temp_free(t1); | |
3883 | gen_helper_store_msr(t0); | |
3884 | tcg_temp_free(t0); | |
3885 | } else | |
d9bce9d9 | 3886 | #endif |
6527f6ea | 3887 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
be147d08 | 3888 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 3889 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 3890 | gen_stop_exception(ctx); |
be147d08 | 3891 | } |
9a64fbe4 | 3892 | #endif |
79aceca5 FB |
3893 | } |
3894 | ||
3895 | /* mtspr */ | |
99e300ef | 3896 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 3897 | { |
45d827d2 | 3898 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
3899 | uint32_t sprn = SPR(ctx->opcode); |
3900 | ||
3fc6c082 | 3901 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 3902 | if (ctx->mem_idx == 2) |
be147d08 | 3903 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 3904 | else if (ctx->mem_idx) |
3fc6c082 FB |
3905 | write_cb = ctx->spr_cb[sprn].oea_write; |
3906 | else | |
9a64fbe4 | 3907 | #endif |
3fc6c082 | 3908 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
3909 | if (likely(write_cb != NULL)) { |
3910 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 3911 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
3912 | } else { |
3913 | /* Privilege exception */ | |
93fcfe39 | 3914 | qemu_log("Trying to write privileged spr %d %03x at " |
90e189ec BS |
3915 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3916 | printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx | |
3917 | "\n", sprn, sprn, ctx->nip); | |
e06fcd75 | 3918 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 3919 | } |
3fc6c082 FB |
3920 | } else { |
3921 | /* Not defined */ | |
93fcfe39 | 3922 | qemu_log("Trying to write invalid spr %d %03x at " |
90e189ec BS |
3923 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3924 | printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 3925 | sprn, sprn, ctx->nip); |
e06fcd75 | 3926 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 3927 | } |
79aceca5 FB |
3928 | } |
3929 | ||
3930 | /*** Cache management ***/ | |
99e300ef | 3931 | |
54623277 | 3932 | /* dcbf */ |
99e300ef | 3933 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 3934 | { |
dac454af | 3935 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
3936 | TCGv t0; |
3937 | gen_set_access_type(ctx, ACCESS_CACHE); | |
3938 | t0 = tcg_temp_new(); | |
3939 | gen_addr_reg_index(ctx, t0); | |
3940 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 3941 | tcg_temp_free(t0); |
79aceca5 FB |
3942 | } |
3943 | ||
3944 | /* dcbi (Supervisor only) */ | |
99e300ef | 3945 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 3946 | { |
a541f297 | 3947 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3948 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 3949 | #else |
b61f2753 | 3950 | TCGv EA, val; |
76db3ba4 | 3951 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3952 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3953 | return; |
9a64fbe4 | 3954 | } |
a7812ae4 | 3955 | EA = tcg_temp_new(); |
76db3ba4 AJ |
3956 | gen_set_access_type(ctx, ACCESS_CACHE); |
3957 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 3958 | val = tcg_temp_new(); |
76a66253 | 3959 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
3960 | gen_qemu_ld8u(ctx, val, EA); |
3961 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
3962 | tcg_temp_free(val); |
3963 | tcg_temp_free(EA); | |
a541f297 | 3964 | #endif |
79aceca5 FB |
3965 | } |
3966 | ||
3967 | /* dcdst */ | |
99e300ef | 3968 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 3969 | { |
76a66253 | 3970 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
3971 | TCGv t0; |
3972 | gen_set_access_type(ctx, ACCESS_CACHE); | |
3973 | t0 = tcg_temp_new(); | |
3974 | gen_addr_reg_index(ctx, t0); | |
3975 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 3976 | tcg_temp_free(t0); |
79aceca5 FB |
3977 | } |
3978 | ||
3979 | /* dcbt */ | |
99e300ef | 3980 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 3981 | { |
0db1b20e | 3982 | /* interpreted as no-op */ |
76a66253 JM |
3983 | /* XXX: specification say this is treated as a load by the MMU |
3984 | * but does not generate any exception | |
3985 | */ | |
79aceca5 FB |
3986 | } |
3987 | ||
3988 | /* dcbtst */ | |
99e300ef | 3989 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 3990 | { |
0db1b20e | 3991 | /* interpreted as no-op */ |
76a66253 JM |
3992 | /* XXX: specification say this is treated as a load by the MMU |
3993 | * but does not generate any exception | |
3994 | */ | |
79aceca5 FB |
3995 | } |
3996 | ||
3997 | /* dcbz */ | |
99e300ef | 3998 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 3999 | { |
76db3ba4 AJ |
4000 | TCGv t0; |
4001 | gen_set_access_type(ctx, ACCESS_CACHE); | |
799a8c8d AJ |
4002 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4003 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4004 | t0 = tcg_temp_new(); |
4005 | gen_addr_reg_index(ctx, t0); | |
799a8c8d AJ |
4006 | gen_helper_dcbz(t0); |
4007 | tcg_temp_free(t0); | |
d63001d1 JM |
4008 | } |
4009 | ||
e8eaa2c0 | 4010 | static void gen_dcbz_970(DisasContext *ctx) |
d63001d1 | 4011 | { |
76db3ba4 AJ |
4012 | TCGv t0; |
4013 | gen_set_access_type(ctx, ACCESS_CACHE); | |
799a8c8d AJ |
4014 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4015 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4016 | t0 = tcg_temp_new(); |
4017 | gen_addr_reg_index(ctx, t0); | |
d63001d1 | 4018 | if (ctx->opcode & 0x00200000) |
799a8c8d | 4019 | gen_helper_dcbz(t0); |
d63001d1 | 4020 | else |
799a8c8d AJ |
4021 | gen_helper_dcbz_970(t0); |
4022 | tcg_temp_free(t0); | |
79aceca5 FB |
4023 | } |
4024 | ||
ae1c1a3d | 4025 | /* dst / dstt */ |
99e300ef | 4026 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4027 | { |
4028 | if (rA(ctx->opcode) == 0) { | |
4029 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4030 | } else { | |
4031 | /* interpreted as no-op */ | |
4032 | } | |
4033 | } | |
4034 | ||
4035 | /* dstst /dststt */ | |
99e300ef | 4036 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4037 | { |
4038 | if (rA(ctx->opcode) == 0) { | |
4039 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4040 | } else { | |
4041 | /* interpreted as no-op */ | |
4042 | } | |
4043 | ||
4044 | } | |
4045 | ||
4046 | /* dss / dssall */ | |
99e300ef | 4047 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4048 | { |
4049 | /* interpreted as no-op */ | |
4050 | } | |
4051 | ||
79aceca5 | 4052 | /* icbi */ |
99e300ef | 4053 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4054 | { |
76db3ba4 AJ |
4055 | TCGv t0; |
4056 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4057 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4058 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4059 | t0 = tcg_temp_new(); |
4060 | gen_addr_reg_index(ctx, t0); | |
37d269df AJ |
4061 | gen_helper_icbi(t0); |
4062 | tcg_temp_free(t0); | |
79aceca5 FB |
4063 | } |
4064 | ||
4065 | /* Optional: */ | |
4066 | /* dcba */ | |
99e300ef | 4067 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4068 | { |
0db1b20e JM |
4069 | /* interpreted as no-op */ |
4070 | /* XXX: specification say this is treated as a store by the MMU | |
4071 | * but does not generate any exception | |
4072 | */ | |
79aceca5 FB |
4073 | } |
4074 | ||
4075 | /*** Segment register manipulation ***/ | |
4076 | /* Supervisor only: */ | |
99e300ef | 4077 | |
54623277 | 4078 | /* mfsr */ |
99e300ef | 4079 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4080 | { |
9a64fbe4 | 4081 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4082 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4083 | #else |
74d37793 | 4084 | TCGv t0; |
76db3ba4 | 4085 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4086 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4087 | return; |
9a64fbe4 | 4088 | } |
74d37793 AJ |
4089 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4090 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); | |
4091 | tcg_temp_free(t0); | |
9a64fbe4 | 4092 | #endif |
79aceca5 FB |
4093 | } |
4094 | ||
4095 | /* mfsrin */ | |
99e300ef | 4096 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4097 | { |
9a64fbe4 | 4098 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4099 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4100 | #else |
74d37793 | 4101 | TCGv t0; |
76db3ba4 | 4102 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4103 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4104 | return; |
9a64fbe4 | 4105 | } |
74d37793 AJ |
4106 | t0 = tcg_temp_new(); |
4107 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4108 | tcg_gen_andi_tl(t0, t0, 0xF); | |
4109 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); | |
4110 | tcg_temp_free(t0); | |
9a64fbe4 | 4111 | #endif |
79aceca5 FB |
4112 | } |
4113 | ||
4114 | /* mtsr */ | |
99e300ef | 4115 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4116 | { |
9a64fbe4 | 4117 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4118 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4119 | #else |
74d37793 | 4120 | TCGv t0; |
76db3ba4 | 4121 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4122 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4123 | return; |
9a64fbe4 | 4124 | } |
74d37793 AJ |
4125 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4126 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); | |
4127 | tcg_temp_free(t0); | |
9a64fbe4 | 4128 | #endif |
79aceca5 FB |
4129 | } |
4130 | ||
4131 | /* mtsrin */ | |
99e300ef | 4132 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4133 | { |
9a64fbe4 | 4134 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4135 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4136 | #else |
74d37793 | 4137 | TCGv t0; |
76db3ba4 | 4138 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4139 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4140 | return; |
9a64fbe4 | 4141 | } |
74d37793 AJ |
4142 | t0 = tcg_temp_new(); |
4143 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4144 | tcg_gen_andi_tl(t0, t0, 0xF); | |
4145 | gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]); | |
4146 | tcg_temp_free(t0); | |
9a64fbe4 | 4147 | #endif |
79aceca5 FB |
4148 | } |
4149 | ||
12de9a39 JM |
4150 | #if defined(TARGET_PPC64) |
4151 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4152 | |
54623277 | 4153 | /* mfsr */ |
e8eaa2c0 | 4154 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4155 | { |
4156 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4157 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4158 | #else |
74d37793 | 4159 | TCGv t0; |
76db3ba4 | 4160 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4161 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4162 | return; |
4163 | } | |
74d37793 | 4164 | t0 = tcg_const_tl(SR(ctx->opcode)); |
f6b868fc | 4165 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
74d37793 | 4166 | tcg_temp_free(t0); |
12de9a39 JM |
4167 | #endif |
4168 | } | |
4169 | ||
4170 | /* mfsrin */ | |
e8eaa2c0 | 4171 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4172 | { |
4173 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4174 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4175 | #else |
74d37793 | 4176 | TCGv t0; |
76db3ba4 | 4177 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4178 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4179 | return; |
4180 | } | |
74d37793 AJ |
4181 | t0 = tcg_temp_new(); |
4182 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4183 | tcg_gen_andi_tl(t0, t0, 0xF); | |
f6b868fc | 4184 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
74d37793 | 4185 | tcg_temp_free(t0); |
12de9a39 JM |
4186 | #endif |
4187 | } | |
4188 | ||
4189 | /* mtsr */ | |
e8eaa2c0 | 4190 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4191 | { |
4192 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4193 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4194 | #else |
74d37793 | 4195 | TCGv t0; |
76db3ba4 | 4196 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4197 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4198 | return; |
4199 | } | |
74d37793 | 4200 | t0 = tcg_const_tl(SR(ctx->opcode)); |
f6b868fc | 4201 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4202 | tcg_temp_free(t0); |
12de9a39 JM |
4203 | #endif |
4204 | } | |
4205 | ||
4206 | /* mtsrin */ | |
e8eaa2c0 | 4207 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4208 | { |
4209 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4210 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4211 | #else |
74d37793 | 4212 | TCGv t0; |
76db3ba4 | 4213 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4214 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4215 | return; |
4216 | } | |
74d37793 AJ |
4217 | t0 = tcg_temp_new(); |
4218 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4219 | tcg_gen_andi_tl(t0, t0, 0xF); | |
f6b868fc | 4220 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4221 | tcg_temp_free(t0); |
12de9a39 JM |
4222 | #endif |
4223 | } | |
f6b868fc BS |
4224 | |
4225 | /* slbmte */ | |
e8eaa2c0 | 4226 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4227 | { |
4228 | #if defined(CONFIG_USER_ONLY) | |
4229 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4230 | #else | |
4231 | if (unlikely(!ctx->mem_idx)) { | |
4232 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4233 | return; | |
4234 | } | |
4235 | gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
4236 | #endif | |
4237 | } | |
4238 | ||
efdef95f DG |
4239 | static void gen_slbmfee(DisasContext *ctx) |
4240 | { | |
4241 | #if defined(CONFIG_USER_ONLY) | |
4242 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4243 | #else | |
4244 | if (unlikely(!ctx->mem_idx)) { | |
4245 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4246 | return; | |
4247 | } | |
4248 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], | |
4249 | cpu_gpr[rB(ctx->opcode)]); | |
4250 | #endif | |
4251 | } | |
4252 | ||
4253 | static void gen_slbmfev(DisasContext *ctx) | |
4254 | { | |
4255 | #if defined(CONFIG_USER_ONLY) | |
4256 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4257 | #else | |
4258 | if (unlikely(!ctx->mem_idx)) { | |
4259 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4260 | return; | |
4261 | } | |
4262 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], | |
4263 | cpu_gpr[rB(ctx->opcode)]); | |
4264 | #endif | |
4265 | } | |
12de9a39 JM |
4266 | #endif /* defined(TARGET_PPC64) */ |
4267 | ||
79aceca5 | 4268 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4269 | /* Optional & mem_idx only: */ |
99e300ef | 4270 | |
54623277 | 4271 | /* tlbia */ |
99e300ef | 4272 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4273 | { |
9a64fbe4 | 4274 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4275 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4276 | #else |
76db3ba4 | 4277 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4278 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4279 | return; |
9a64fbe4 | 4280 | } |
74d37793 | 4281 | gen_helper_tlbia(); |
9a64fbe4 | 4282 | #endif |
79aceca5 FB |
4283 | } |
4284 | ||
bf14b1ce | 4285 | /* tlbiel */ |
99e300ef | 4286 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4287 | { |
4288 | #if defined(CONFIG_USER_ONLY) | |
4289 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4290 | #else | |
4291 | if (unlikely(!ctx->mem_idx)) { | |
4292 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4293 | return; | |
4294 | } | |
4295 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); | |
4296 | #endif | |
4297 | } | |
4298 | ||
79aceca5 | 4299 | /* tlbie */ |
99e300ef | 4300 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4301 | { |
9a64fbe4 | 4302 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4303 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4304 | #else |
76db3ba4 | 4305 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4306 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4307 | return; |
9a64fbe4 | 4308 | } |
d9bce9d9 | 4309 | #if defined(TARGET_PPC64) |
74d37793 AJ |
4310 | if (!ctx->sf_mode) { |
4311 | TCGv t0 = tcg_temp_new(); | |
4312 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
4313 | gen_helper_tlbie(t0); | |
4314 | tcg_temp_free(t0); | |
4315 | } else | |
d9bce9d9 | 4316 | #endif |
74d37793 | 4317 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
9a64fbe4 | 4318 | #endif |
79aceca5 FB |
4319 | } |
4320 | ||
4321 | /* tlbsync */ | |
99e300ef | 4322 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4323 | { |
9a64fbe4 | 4324 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4325 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4326 | #else |
76db3ba4 | 4327 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4328 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4329 | return; |
9a64fbe4 FB |
4330 | } |
4331 | /* This has no effect: it should ensure that all previous | |
4332 | * tlbie have completed | |
4333 | */ | |
e06fcd75 | 4334 | gen_stop_exception(ctx); |
9a64fbe4 | 4335 | #endif |
79aceca5 FB |
4336 | } |
4337 | ||
426613db JM |
4338 | #if defined(TARGET_PPC64) |
4339 | /* slbia */ | |
99e300ef | 4340 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4341 | { |
4342 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4343 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4344 | #else |
76db3ba4 | 4345 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4346 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4347 | return; |
4348 | } | |
74d37793 | 4349 | gen_helper_slbia(); |
426613db JM |
4350 | #endif |
4351 | } | |
4352 | ||
4353 | /* slbie */ | |
99e300ef | 4354 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4355 | { |
4356 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4357 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4358 | #else |
76db3ba4 | 4359 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4360 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4361 | return; |
4362 | } | |
74d37793 | 4363 | gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4364 | #endif |
4365 | } | |
4366 | #endif | |
4367 | ||
79aceca5 FB |
4368 | /*** External control ***/ |
4369 | /* Optional: */ | |
99e300ef | 4370 | |
54623277 | 4371 | /* eciwx */ |
99e300ef | 4372 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4373 | { |
76db3ba4 | 4374 | TCGv t0; |
fa407c03 | 4375 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4376 | gen_set_access_type(ctx, ACCESS_EXT); |
4377 | t0 = tcg_temp_new(); | |
4378 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4379 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4380 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4381 | tcg_temp_free(t0); |
76a66253 JM |
4382 | } |
4383 | ||
4384 | /* ecowx */ | |
99e300ef | 4385 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4386 | { |
76db3ba4 | 4387 | TCGv t0; |
fa407c03 | 4388 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4389 | gen_set_access_type(ctx, ACCESS_EXT); |
4390 | t0 = tcg_temp_new(); | |
4391 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4392 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4393 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4394 | tcg_temp_free(t0); |
76a66253 JM |
4395 | } |
4396 | ||
4397 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4398 | |
54623277 | 4399 | /* abs - abs. */ |
99e300ef | 4400 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4401 | { |
22e0e173 AJ |
4402 | int l1 = gen_new_label(); |
4403 | int l2 = gen_new_label(); | |
4404 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4405 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4406 | tcg_gen_br(l2); | |
4407 | gen_set_label(l1); | |
4408 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4409 | gen_set_label(l2); | |
76a66253 | 4410 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4411 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4412 | } |
4413 | ||
4414 | /* abso - abso. */ | |
99e300ef | 4415 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4416 | { |
22e0e173 AJ |
4417 | int l1 = gen_new_label(); |
4418 | int l2 = gen_new_label(); | |
4419 | int l3 = gen_new_label(); | |
4420 | /* Start with XER OV disabled, the most likely case */ | |
4421 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
4422 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); | |
4423 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
4424 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
4425 | tcg_gen_br(l2); | |
4426 | gen_set_label(l1); | |
4427 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4428 | tcg_gen_br(l3); | |
4429 | gen_set_label(l2); | |
4430 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4431 | gen_set_label(l3); | |
76a66253 | 4432 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4433 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4434 | } |
4435 | ||
4436 | /* clcs */ | |
99e300ef | 4437 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4438 | { |
22e0e173 AJ |
4439 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
4440 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0); | |
4441 | tcg_temp_free_i32(t0); | |
c7697e1f | 4442 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4443 | } |
4444 | ||
4445 | /* div - div. */ | |
99e300ef | 4446 | static void gen_div(DisasContext *ctx) |
76a66253 | 4447 | { |
22e0e173 | 4448 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76a66253 | 4449 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4450 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4451 | } |
4452 | ||
4453 | /* divo - divo. */ | |
99e300ef | 4454 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4455 | { |
22e0e173 | 4456 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76a66253 | 4457 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4458 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4459 | } |
4460 | ||
4461 | /* divs - divs. */ | |
99e300ef | 4462 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4463 | { |
22e0e173 | 4464 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76a66253 | 4465 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4466 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4467 | } |
4468 | ||
4469 | /* divso - divso. */ | |
99e300ef | 4470 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4471 | { |
22e0e173 | 4472 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76a66253 | 4473 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4474 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4475 | } |
4476 | ||
4477 | /* doz - doz. */ | |
99e300ef | 4478 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4479 | { |
22e0e173 AJ |
4480 | int l1 = gen_new_label(); |
4481 | int l2 = gen_new_label(); | |
4482 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4483 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4484 | tcg_gen_br(l2); | |
4485 | gen_set_label(l1); | |
4486 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4487 | gen_set_label(l2); | |
76a66253 | 4488 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4489 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4490 | } |
4491 | ||
4492 | /* dozo - dozo. */ | |
99e300ef | 4493 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4494 | { |
22e0e173 AJ |
4495 | int l1 = gen_new_label(); |
4496 | int l2 = gen_new_label(); | |
4497 | TCGv t0 = tcg_temp_new(); | |
4498 | TCGv t1 = tcg_temp_new(); | |
4499 | TCGv t2 = tcg_temp_new(); | |
4500 | /* Start with XER OV disabled, the most likely case */ | |
4501 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
4502 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4503 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4504 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4505 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4506 | tcg_gen_andc_tl(t1, t1, t2); | |
4507 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4508 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
4509 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
4510 | tcg_gen_br(l2); | |
4511 | gen_set_label(l1); | |
4512 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4513 | gen_set_label(l2); | |
4514 | tcg_temp_free(t0); | |
4515 | tcg_temp_free(t1); | |
4516 | tcg_temp_free(t2); | |
76a66253 | 4517 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4518 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4519 | } |
4520 | ||
4521 | /* dozi */ | |
99e300ef | 4522 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4523 | { |
22e0e173 AJ |
4524 | target_long simm = SIMM(ctx->opcode); |
4525 | int l1 = gen_new_label(); | |
4526 | int l2 = gen_new_label(); | |
4527 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
4528 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4529 | tcg_gen_br(l2); | |
4530 | gen_set_label(l1); | |
4531 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4532 | gen_set_label(l2); | |
4533 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4534 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4535 | } |
4536 | ||
76a66253 | 4537 | /* lscbx - lscbx. */ |
99e300ef | 4538 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4539 | { |
bdb4b689 AJ |
4540 | TCGv t0 = tcg_temp_new(); |
4541 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4542 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4543 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4544 | |
76db3ba4 | 4545 | gen_addr_reg_index(ctx, t0); |
76a66253 | 4546 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 4547 | gen_update_nip(ctx, ctx->nip - 4); |
bdb4b689 AJ |
4548 | gen_helper_lscbx(t0, t0, t1, t2, t3); |
4549 | tcg_temp_free_i32(t1); | |
4550 | tcg_temp_free_i32(t2); | |
4551 | tcg_temp_free_i32(t3); | |
3d7b417e | 4552 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4553 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4554 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4555 | gen_set_Rc0(ctx, t0); |
4556 | tcg_temp_free(t0); | |
76a66253 JM |
4557 | } |
4558 | ||
4559 | /* maskg - maskg. */ | |
99e300ef | 4560 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4561 | { |
22e0e173 AJ |
4562 | int l1 = gen_new_label(); |
4563 | TCGv t0 = tcg_temp_new(); | |
4564 | TCGv t1 = tcg_temp_new(); | |
4565 | TCGv t2 = tcg_temp_new(); | |
4566 | TCGv t3 = tcg_temp_new(); | |
4567 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4568 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4569 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4570 | tcg_gen_addi_tl(t2, t0, 1); | |
4571 | tcg_gen_shr_tl(t2, t3, t2); | |
4572 | tcg_gen_shr_tl(t3, t3, t1); | |
4573 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4574 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4575 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4576 | gen_set_label(l1); | |
4577 | tcg_temp_free(t0); | |
4578 | tcg_temp_free(t1); | |
4579 | tcg_temp_free(t2); | |
4580 | tcg_temp_free(t3); | |
76a66253 | 4581 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4582 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4583 | } |
4584 | ||
4585 | /* maskir - maskir. */ | |
99e300ef | 4586 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4587 | { |
22e0e173 AJ |
4588 | TCGv t0 = tcg_temp_new(); |
4589 | TCGv t1 = tcg_temp_new(); | |
4590 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4591 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4592 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4593 | tcg_temp_free(t0); | |
4594 | tcg_temp_free(t1); | |
76a66253 | 4595 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4596 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4597 | } |
4598 | ||
4599 | /* mul - mul. */ | |
99e300ef | 4600 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4601 | { |
22e0e173 AJ |
4602 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4603 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4604 | TCGv t2 = tcg_temp_new(); | |
4605 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4606 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4607 | tcg_gen_mul_i64(t0, t0, t1); | |
4608 | tcg_gen_trunc_i64_tl(t2, t0); | |
4609 | gen_store_spr(SPR_MQ, t2); | |
4610 | tcg_gen_shri_i64(t1, t0, 32); | |
4611 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4612 | tcg_temp_free_i64(t0); | |
4613 | tcg_temp_free_i64(t1); | |
4614 | tcg_temp_free(t2); | |
76a66253 | 4615 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4616 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4617 | } |
4618 | ||
4619 | /* mulo - mulo. */ | |
99e300ef | 4620 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4621 | { |
22e0e173 AJ |
4622 | int l1 = gen_new_label(); |
4623 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
4624 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4625 | TCGv t2 = tcg_temp_new(); | |
4626 | /* Start with XER OV disabled, the most likely case */ | |
4627 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
4628 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4629 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4630 | tcg_gen_mul_i64(t0, t0, t1); | |
4631 | tcg_gen_trunc_i64_tl(t2, t0); | |
4632 | gen_store_spr(SPR_MQ, t2); | |
4633 | tcg_gen_shri_i64(t1, t0, 32); | |
4634 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4635 | tcg_gen_ext32s_i64(t1, t0); | |
4636 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
4637 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
4638 | gen_set_label(l1); | |
4639 | tcg_temp_free_i64(t0); | |
4640 | tcg_temp_free_i64(t1); | |
4641 | tcg_temp_free(t2); | |
76a66253 | 4642 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4643 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4644 | } |
4645 | ||
4646 | /* nabs - nabs. */ | |
99e300ef | 4647 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4648 | { |
22e0e173 AJ |
4649 | int l1 = gen_new_label(); |
4650 | int l2 = gen_new_label(); | |
4651 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4652 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4653 | tcg_gen_br(l2); | |
4654 | gen_set_label(l1); | |
4655 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4656 | gen_set_label(l2); | |
76a66253 | 4657 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4658 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4659 | } |
4660 | ||
4661 | /* nabso - nabso. */ | |
99e300ef | 4662 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4663 | { |
22e0e173 AJ |
4664 | int l1 = gen_new_label(); |
4665 | int l2 = gen_new_label(); | |
4666 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4667 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4668 | tcg_gen_br(l2); | |
4669 | gen_set_label(l1); | |
4670 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4671 | gen_set_label(l2); | |
4672 | /* nabs never overflows */ | |
4673 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
76a66253 | 4674 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4675 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4676 | } |
4677 | ||
4678 | /* rlmi - rlmi. */ | |
99e300ef | 4679 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4680 | { |
7487953d AJ |
4681 | uint32_t mb = MB(ctx->opcode); |
4682 | uint32_t me = ME(ctx->opcode); | |
4683 | TCGv t0 = tcg_temp_new(); | |
4684 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4685 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4686 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4687 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4688 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4689 | tcg_temp_free(t0); | |
76a66253 | 4690 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4691 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4692 | } |
4693 | ||
4694 | /* rrib - rrib. */ | |
99e300ef | 4695 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4696 | { |
7487953d AJ |
4697 | TCGv t0 = tcg_temp_new(); |
4698 | TCGv t1 = tcg_temp_new(); | |
4699 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4700 | tcg_gen_movi_tl(t1, 0x80000000); | |
4701 | tcg_gen_shr_tl(t1, t1, t0); | |
4702 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4703 | tcg_gen_and_tl(t0, t0, t1); | |
4704 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4705 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4706 | tcg_temp_free(t0); | |
4707 | tcg_temp_free(t1); | |
76a66253 | 4708 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4709 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4710 | } |
4711 | ||
4712 | /* sle - sle. */ | |
99e300ef | 4713 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4714 | { |
7487953d AJ |
4715 | TCGv t0 = tcg_temp_new(); |
4716 | TCGv t1 = tcg_temp_new(); | |
4717 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4718 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4719 | tcg_gen_subfi_tl(t1, 32, t1); | |
4720 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4721 | tcg_gen_or_tl(t1, t0, t1); | |
4722 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4723 | gen_store_spr(SPR_MQ, t1); | |
4724 | tcg_temp_free(t0); | |
4725 | tcg_temp_free(t1); | |
76a66253 | 4726 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4727 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4728 | } |
4729 | ||
4730 | /* sleq - sleq. */ | |
99e300ef | 4731 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4732 | { |
7487953d AJ |
4733 | TCGv t0 = tcg_temp_new(); |
4734 | TCGv t1 = tcg_temp_new(); | |
4735 | TCGv t2 = tcg_temp_new(); | |
4736 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4737 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
4738 | tcg_gen_shl_tl(t2, t2, t0); | |
4739 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4740 | gen_load_spr(t1, SPR_MQ); | |
4741 | gen_store_spr(SPR_MQ, t0); | |
4742 | tcg_gen_and_tl(t0, t0, t2); | |
4743 | tcg_gen_andc_tl(t1, t1, t2); | |
4744 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4745 | tcg_temp_free(t0); | |
4746 | tcg_temp_free(t1); | |
4747 | tcg_temp_free(t2); | |
76a66253 | 4748 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4749 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4750 | } |
4751 | ||
4752 | /* sliq - sliq. */ | |
99e300ef | 4753 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 4754 | { |
7487953d AJ |
4755 | int sh = SH(ctx->opcode); |
4756 | TCGv t0 = tcg_temp_new(); | |
4757 | TCGv t1 = tcg_temp_new(); | |
4758 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4759 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4760 | tcg_gen_or_tl(t1, t0, t1); | |
4761 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4762 | gen_store_spr(SPR_MQ, t1); | |
4763 | tcg_temp_free(t0); | |
4764 | tcg_temp_free(t1); | |
76a66253 | 4765 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4766 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4767 | } |
4768 | ||
4769 | /* slliq - slliq. */ | |
99e300ef | 4770 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 4771 | { |
7487953d AJ |
4772 | int sh = SH(ctx->opcode); |
4773 | TCGv t0 = tcg_temp_new(); | |
4774 | TCGv t1 = tcg_temp_new(); | |
4775 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4776 | gen_load_spr(t1, SPR_MQ); | |
4777 | gen_store_spr(SPR_MQ, t0); | |
4778 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
4779 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
4780 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4781 | tcg_temp_free(t0); | |
4782 | tcg_temp_free(t1); | |
76a66253 | 4783 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4784 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4785 | } |
4786 | ||
4787 | /* sllq - sllq. */ | |
99e300ef | 4788 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 4789 | { |
7487953d AJ |
4790 | int l1 = gen_new_label(); |
4791 | int l2 = gen_new_label(); | |
4792 | TCGv t0 = tcg_temp_local_new(); | |
4793 | TCGv t1 = tcg_temp_local_new(); | |
4794 | TCGv t2 = tcg_temp_local_new(); | |
4795 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4796 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4797 | tcg_gen_shl_tl(t1, t1, t2); | |
4798 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4799 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
4800 | gen_load_spr(t0, SPR_MQ); | |
4801 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4802 | tcg_gen_br(l2); | |
4803 | gen_set_label(l1); | |
4804 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4805 | gen_load_spr(t2, SPR_MQ); | |
4806 | tcg_gen_andc_tl(t1, t2, t1); | |
4807 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4808 | gen_set_label(l2); | |
4809 | tcg_temp_free(t0); | |
4810 | tcg_temp_free(t1); | |
4811 | tcg_temp_free(t2); | |
76a66253 | 4812 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4813 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4814 | } |
4815 | ||
4816 | /* slq - slq. */ | |
99e300ef | 4817 | static void gen_slq(DisasContext *ctx) |
76a66253 | 4818 | { |
7487953d AJ |
4819 | int l1 = gen_new_label(); |
4820 | TCGv t0 = tcg_temp_new(); | |
4821 | TCGv t1 = tcg_temp_new(); | |
4822 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4823 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4824 | tcg_gen_subfi_tl(t1, 32, t1); | |
4825 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4826 | tcg_gen_or_tl(t1, t0, t1); | |
4827 | gen_store_spr(SPR_MQ, t1); | |
4828 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4829 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4830 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
4831 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
4832 | gen_set_label(l1); | |
4833 | tcg_temp_free(t0); | |
4834 | tcg_temp_free(t1); | |
76a66253 | 4835 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4836 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4837 | } |
4838 | ||
d9bce9d9 | 4839 | /* sraiq - sraiq. */ |
99e300ef | 4840 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 4841 | { |
7487953d AJ |
4842 | int sh = SH(ctx->opcode); |
4843 | int l1 = gen_new_label(); | |
4844 | TCGv t0 = tcg_temp_new(); | |
4845 | TCGv t1 = tcg_temp_new(); | |
4846 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4847 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4848 | tcg_gen_or_tl(t0, t0, t1); | |
4849 | gen_store_spr(SPR_MQ, t0); | |
4850 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
4851 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
4852 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
4853 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA)); | |
4854 | gen_set_label(l1); | |
4855 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
4856 | tcg_temp_free(t0); | |
4857 | tcg_temp_free(t1); | |
76a66253 | 4858 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4859 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4860 | } |
4861 | ||
4862 | /* sraq - sraq. */ | |
99e300ef | 4863 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 4864 | { |
7487953d AJ |
4865 | int l1 = gen_new_label(); |
4866 | int l2 = gen_new_label(); | |
4867 | TCGv t0 = tcg_temp_new(); | |
4868 | TCGv t1 = tcg_temp_local_new(); | |
4869 | TCGv t2 = tcg_temp_local_new(); | |
4870 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4871 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4872 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
4873 | tcg_gen_subfi_tl(t2, 32, t2); | |
4874 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
4875 | tcg_gen_or_tl(t0, t0, t2); | |
4876 | gen_store_spr(SPR_MQ, t0); | |
4877 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4878 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
4879 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
4880 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
4881 | gen_set_label(l1); | |
4882 | tcg_temp_free(t0); | |
4883 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
4884 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
4885 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
4886 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
4887 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA)); | |
4888 | gen_set_label(l2); | |
4889 | tcg_temp_free(t1); | |
4890 | tcg_temp_free(t2); | |
76a66253 | 4891 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4892 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4893 | } |
4894 | ||
4895 | /* sre - sre. */ | |
99e300ef | 4896 | static void gen_sre(DisasContext *ctx) |
76a66253 | 4897 | { |
7487953d AJ |
4898 | TCGv t0 = tcg_temp_new(); |
4899 | TCGv t1 = tcg_temp_new(); | |
4900 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4901 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4902 | tcg_gen_subfi_tl(t1, 32, t1); | |
4903 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4904 | tcg_gen_or_tl(t1, t0, t1); | |
4905 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4906 | gen_store_spr(SPR_MQ, t1); | |
4907 | tcg_temp_free(t0); | |
4908 | tcg_temp_free(t1); | |
76a66253 | 4909 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4910 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4911 | } |
4912 | ||
4913 | /* srea - srea. */ | |
99e300ef | 4914 | static void gen_srea(DisasContext *ctx) |
76a66253 | 4915 | { |
7487953d AJ |
4916 | TCGv t0 = tcg_temp_new(); |
4917 | TCGv t1 = tcg_temp_new(); | |
4918 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4919 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4920 | gen_store_spr(SPR_MQ, t0); | |
4921 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
4922 | tcg_temp_free(t0); | |
4923 | tcg_temp_free(t1); | |
76a66253 | 4924 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4925 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4926 | } |
4927 | ||
4928 | /* sreq */ | |
99e300ef | 4929 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 4930 | { |
7487953d AJ |
4931 | TCGv t0 = tcg_temp_new(); |
4932 | TCGv t1 = tcg_temp_new(); | |
4933 | TCGv t2 = tcg_temp_new(); | |
4934 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4935 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4936 | tcg_gen_shr_tl(t1, t1, t0); | |
4937 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4938 | gen_load_spr(t2, SPR_MQ); | |
4939 | gen_store_spr(SPR_MQ, t0); | |
4940 | tcg_gen_and_tl(t0, t0, t1); | |
4941 | tcg_gen_andc_tl(t2, t2, t1); | |
4942 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
4943 | tcg_temp_free(t0); | |
4944 | tcg_temp_free(t1); | |
4945 | tcg_temp_free(t2); | |
76a66253 | 4946 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4947 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4948 | } |
4949 | ||
4950 | /* sriq */ | |
99e300ef | 4951 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 4952 | { |
7487953d AJ |
4953 | int sh = SH(ctx->opcode); |
4954 | TCGv t0 = tcg_temp_new(); | |
4955 | TCGv t1 = tcg_temp_new(); | |
4956 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4957 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4958 | tcg_gen_or_tl(t1, t0, t1); | |
4959 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4960 | gen_store_spr(SPR_MQ, t1); | |
4961 | tcg_temp_free(t0); | |
4962 | tcg_temp_free(t1); | |
76a66253 | 4963 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4964 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4965 | } |
4966 | ||
4967 | /* srliq */ | |
99e300ef | 4968 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 4969 | { |
7487953d AJ |
4970 | int sh = SH(ctx->opcode); |
4971 | TCGv t0 = tcg_temp_new(); | |
4972 | TCGv t1 = tcg_temp_new(); | |
4973 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4974 | gen_load_spr(t1, SPR_MQ); | |
4975 | gen_store_spr(SPR_MQ, t0); | |
4976 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
4977 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
4978 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4979 | tcg_temp_free(t0); | |
4980 | tcg_temp_free(t1); | |
76a66253 | 4981 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4982 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4983 | } |
4984 | ||
4985 | /* srlq */ | |
99e300ef | 4986 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 4987 | { |
7487953d AJ |
4988 | int l1 = gen_new_label(); |
4989 | int l2 = gen_new_label(); | |
4990 | TCGv t0 = tcg_temp_local_new(); | |
4991 | TCGv t1 = tcg_temp_local_new(); | |
4992 | TCGv t2 = tcg_temp_local_new(); | |
4993 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4994 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4995 | tcg_gen_shr_tl(t2, t1, t2); | |
4996 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4997 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
4998 | gen_load_spr(t0, SPR_MQ); | |
4999 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5000 | tcg_gen_br(l2); | |
5001 | gen_set_label(l1); | |
5002 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5003 | tcg_gen_and_tl(t0, t0, t2); | |
5004 | gen_load_spr(t1, SPR_MQ); | |
5005 | tcg_gen_andc_tl(t1, t1, t2); | |
5006 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5007 | gen_set_label(l2); | |
5008 | tcg_temp_free(t0); | |
5009 | tcg_temp_free(t1); | |
5010 | tcg_temp_free(t2); | |
76a66253 | 5011 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5012 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5013 | } |
5014 | ||
5015 | /* srq */ | |
99e300ef | 5016 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5017 | { |
7487953d AJ |
5018 | int l1 = gen_new_label(); |
5019 | TCGv t0 = tcg_temp_new(); | |
5020 | TCGv t1 = tcg_temp_new(); | |
5021 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5022 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5023 | tcg_gen_subfi_tl(t1, 32, t1); | |
5024 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5025 | tcg_gen_or_tl(t1, t0, t1); | |
5026 | gen_store_spr(SPR_MQ, t1); | |
5027 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5028 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5029 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5030 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5031 | gen_set_label(l1); | |
5032 | tcg_temp_free(t0); | |
5033 | tcg_temp_free(t1); | |
76a66253 | 5034 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5035 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5036 | } |
5037 | ||
5038 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5039 | |
54623277 | 5040 | /* dsa */ |
99e300ef | 5041 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5042 | { |
5043 | /* XXX: TODO */ | |
e06fcd75 | 5044 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5045 | } |
5046 | ||
5047 | /* esa */ | |
99e300ef | 5048 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5049 | { |
5050 | /* XXX: TODO */ | |
e06fcd75 | 5051 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5052 | } |
5053 | ||
5054 | /* mfrom */ | |
99e300ef | 5055 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5056 | { |
5057 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5058 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5059 | #else |
76db3ba4 | 5060 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5061 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5062 | return; |
5063 | } | |
cf02a65c | 5064 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5065 | #endif |
5066 | } | |
5067 | ||
5068 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5069 | |
54623277 | 5070 | /* tlbld */ |
e8eaa2c0 | 5071 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5072 | { |
5073 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5074 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5075 | #else |
76db3ba4 | 5076 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5077 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5078 | return; |
5079 | } | |
74d37793 | 5080 | gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5081 | #endif |
5082 | } | |
5083 | ||
5084 | /* tlbli */ | |
e8eaa2c0 | 5085 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5086 | { |
5087 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5088 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5089 | #else |
76db3ba4 | 5090 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5091 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5092 | return; |
5093 | } | |
74d37793 | 5094 | gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5095 | #endif |
5096 | } | |
5097 | ||
7dbe11ac | 5098 | /* 74xx TLB management */ |
e8eaa2c0 | 5099 | |
54623277 | 5100 | /* tlbld */ |
e8eaa2c0 | 5101 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5102 | { |
5103 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5104 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5105 | #else |
76db3ba4 | 5106 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5107 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5108 | return; |
5109 | } | |
74d37793 | 5110 | gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5111 | #endif |
5112 | } | |
5113 | ||
5114 | /* tlbli */ | |
e8eaa2c0 | 5115 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5116 | { |
5117 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5118 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5119 | #else |
76db3ba4 | 5120 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5121 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5122 | return; |
5123 | } | |
74d37793 | 5124 | gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5125 | #endif |
5126 | } | |
5127 | ||
76a66253 | 5128 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5129 | |
54623277 | 5130 | /* clf */ |
99e300ef | 5131 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5132 | { |
5133 | /* Cache line flush: implemented as no-op */ | |
5134 | } | |
5135 | ||
5136 | /* cli */ | |
99e300ef | 5137 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5138 | { |
7f75ffd3 | 5139 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5140 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5141 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5142 | #else |
76db3ba4 | 5143 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5144 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5145 | return; |
5146 | } | |
5147 | #endif | |
5148 | } | |
5149 | ||
5150 | /* dclst */ | |
99e300ef | 5151 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5152 | { |
5153 | /* Data cache line store: treated as no-op */ | |
5154 | } | |
5155 | ||
99e300ef | 5156 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5157 | { |
5158 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5159 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5160 | #else |
74d37793 AJ |
5161 | int ra = rA(ctx->opcode); |
5162 | int rd = rD(ctx->opcode); | |
5163 | TCGv t0; | |
76db3ba4 | 5164 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5165 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5166 | return; |
5167 | } | |
74d37793 | 5168 | t0 = tcg_temp_new(); |
76db3ba4 | 5169 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5170 | tcg_gen_shri_tl(t0, t0, 28); |
5171 | tcg_gen_andi_tl(t0, t0, 0xF); | |
5172 | gen_helper_load_sr(cpu_gpr[rd], t0); | |
5173 | tcg_temp_free(t0); | |
76a66253 | 5174 | if (ra != 0 && ra != rd) |
74d37793 | 5175 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5176 | #endif |
5177 | } | |
5178 | ||
99e300ef | 5179 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5180 | { |
5181 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5182 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5183 | #else |
22e0e173 | 5184 | TCGv t0; |
76db3ba4 | 5185 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5186 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5187 | return; |
5188 | } | |
22e0e173 | 5189 | t0 = tcg_temp_new(); |
76db3ba4 | 5190 | gen_addr_reg_index(ctx, t0); |
22e0e173 AJ |
5191 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0); |
5192 | tcg_temp_free(t0); | |
76a66253 JM |
5193 | #endif |
5194 | } | |
5195 | ||
99e300ef | 5196 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5197 | { |
5198 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5199 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5200 | #else |
76db3ba4 | 5201 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5202 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5203 | return; |
5204 | } | |
d72a19f7 | 5205 | gen_helper_rfsvc(); |
e06fcd75 | 5206 | gen_sync_exception(ctx); |
76a66253 JM |
5207 | #endif |
5208 | } | |
5209 | ||
5210 | /* svc is not implemented for now */ | |
5211 | ||
5212 | /* POWER2 specific instructions */ | |
5213 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5214 | |
5215 | /* lfq */ | |
99e300ef | 5216 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5217 | { |
01a4afeb | 5218 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5219 | TCGv t0; |
5220 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5221 | t0 = tcg_temp_new(); | |
5222 | gen_addr_imm_index(ctx, t0, 0); | |
5223 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5224 | gen_addr_add(ctx, t0, t0, 8); | |
5225 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5226 | tcg_temp_free(t0); |
76a66253 JM |
5227 | } |
5228 | ||
5229 | /* lfqu */ | |
99e300ef | 5230 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5231 | { |
5232 | int ra = rA(ctx->opcode); | |
01a4afeb | 5233 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5234 | TCGv t0, t1; |
5235 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5236 | t0 = tcg_temp_new(); | |
5237 | t1 = tcg_temp_new(); | |
5238 | gen_addr_imm_index(ctx, t0, 0); | |
5239 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5240 | gen_addr_add(ctx, t1, t0, 8); | |
5241 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5242 | if (ra != 0) |
01a4afeb AJ |
5243 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5244 | tcg_temp_free(t0); | |
5245 | tcg_temp_free(t1); | |
76a66253 JM |
5246 | } |
5247 | ||
5248 | /* lfqux */ | |
99e300ef | 5249 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5250 | { |
5251 | int ra = rA(ctx->opcode); | |
01a4afeb | 5252 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5253 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5254 | TCGv t0, t1; | |
5255 | t0 = tcg_temp_new(); | |
5256 | gen_addr_reg_index(ctx, t0); | |
5257 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5258 | t1 = tcg_temp_new(); | |
5259 | gen_addr_add(ctx, t1, t0, 8); | |
5260 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5261 | tcg_temp_free(t1); | |
76a66253 | 5262 | if (ra != 0) |
01a4afeb AJ |
5263 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5264 | tcg_temp_free(t0); | |
76a66253 JM |
5265 | } |
5266 | ||
5267 | /* lfqx */ | |
99e300ef | 5268 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5269 | { |
01a4afeb | 5270 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5271 | TCGv t0; |
5272 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5273 | t0 = tcg_temp_new(); | |
5274 | gen_addr_reg_index(ctx, t0); | |
5275 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5276 | gen_addr_add(ctx, t0, t0, 8); | |
5277 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5278 | tcg_temp_free(t0); |
76a66253 JM |
5279 | } |
5280 | ||
5281 | /* stfq */ | |
99e300ef | 5282 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5283 | { |
01a4afeb | 5284 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5285 | TCGv t0; |
5286 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5287 | t0 = tcg_temp_new(); | |
5288 | gen_addr_imm_index(ctx, t0, 0); | |
5289 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5290 | gen_addr_add(ctx, t0, t0, 8); | |
5291 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5292 | tcg_temp_free(t0); |
76a66253 JM |
5293 | } |
5294 | ||
5295 | /* stfqu */ | |
99e300ef | 5296 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5297 | { |
5298 | int ra = rA(ctx->opcode); | |
01a4afeb | 5299 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5300 | TCGv t0, t1; |
5301 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5302 | t0 = tcg_temp_new(); | |
5303 | gen_addr_imm_index(ctx, t0, 0); | |
5304 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5305 | t1 = tcg_temp_new(); | |
5306 | gen_addr_add(ctx, t1, t0, 8); | |
5307 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5308 | tcg_temp_free(t1); | |
76a66253 | 5309 | if (ra != 0) |
01a4afeb AJ |
5310 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5311 | tcg_temp_free(t0); | |
76a66253 JM |
5312 | } |
5313 | ||
5314 | /* stfqux */ | |
99e300ef | 5315 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5316 | { |
5317 | int ra = rA(ctx->opcode); | |
01a4afeb | 5318 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5319 | TCGv t0, t1; |
5320 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5321 | t0 = tcg_temp_new(); | |
5322 | gen_addr_reg_index(ctx, t0); | |
5323 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5324 | t1 = tcg_temp_new(); | |
5325 | gen_addr_add(ctx, t1, t0, 8); | |
5326 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5327 | tcg_temp_free(t1); | |
76a66253 | 5328 | if (ra != 0) |
01a4afeb AJ |
5329 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5330 | tcg_temp_free(t0); | |
76a66253 JM |
5331 | } |
5332 | ||
5333 | /* stfqx */ | |
99e300ef | 5334 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5335 | { |
01a4afeb | 5336 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5337 | TCGv t0; |
5338 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5339 | t0 = tcg_temp_new(); | |
5340 | gen_addr_reg_index(ctx, t0); | |
5341 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5342 | gen_addr_add(ctx, t0, t0, 8); | |
5343 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5344 | tcg_temp_free(t0); |
76a66253 JM |
5345 | } |
5346 | ||
5347 | /* BookE specific instructions */ | |
99e300ef | 5348 | |
54623277 | 5349 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5350 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5351 | { |
5352 | /* XXX: TODO */ | |
e06fcd75 | 5353 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5354 | } |
5355 | ||
2662a059 | 5356 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5357 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5358 | { |
5359 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5360 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5361 | #else |
74d37793 | 5362 | TCGv t0; |
76db3ba4 | 5363 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5364 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5365 | return; |
5366 | } | |
ec72e276 | 5367 | t0 = tcg_temp_new(); |
76db3ba4 | 5368 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5369 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
5370 | tcg_temp_free(t0); | |
76a66253 JM |
5371 | #endif |
5372 | } | |
5373 | ||
5374 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5375 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5376 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5377 | { |
182608d4 AJ |
5378 | TCGv t0, t1; |
5379 | ||
a7812ae4 PB |
5380 | t0 = tcg_temp_local_new(); |
5381 | t1 = tcg_temp_local_new(); | |
182608d4 | 5382 | |
76a66253 JM |
5383 | switch (opc3 & 0x0D) { |
5384 | case 0x05: | |
5385 | /* macchw - macchw. - macchwo - macchwo. */ | |
5386 | /* macchws - macchws. - macchwso - macchwso. */ | |
5387 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5388 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5389 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5390 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5391 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5392 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5393 | break; |
5394 | case 0x04: | |
5395 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5396 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5397 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5398 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5399 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5400 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5401 | break; |
5402 | case 0x01: | |
5403 | /* machhw - machhw. - machhwo - machhwo. */ | |
5404 | /* machhws - machhws. - machhwso - machhwso. */ | |
5405 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5406 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5407 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5408 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5409 | tcg_gen_ext16s_tl(t0, t0); | |
5410 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5411 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5412 | break; |
5413 | case 0x00: | |
5414 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5415 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5416 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5417 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5418 | tcg_gen_ext16u_tl(t0, t0); | |
5419 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5420 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5421 | break; |
5422 | case 0x0D: | |
5423 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5424 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5425 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5426 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5427 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5428 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5429 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5430 | break; |
5431 | case 0x0C: | |
5432 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5433 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5434 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5435 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5436 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5437 | break; |
5438 | } | |
76a66253 | 5439 | if (opc2 & 0x04) { |
182608d4 AJ |
5440 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5441 | tcg_gen_mul_tl(t1, t0, t1); | |
5442 | if (opc2 & 0x02) { | |
5443 | /* nmultiply-and-accumulate (0x0E) */ | |
5444 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5445 | } else { | |
5446 | /* multiply-and-accumulate (0x0C) */ | |
5447 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5448 | } | |
5449 | ||
5450 | if (opc3 & 0x12) { | |
5451 | /* Check overflow and/or saturate */ | |
5452 | int l1 = gen_new_label(); | |
5453 | ||
5454 | if (opc3 & 0x10) { | |
5455 | /* Start with XER OV disabled, the most likely case */ | |
5456 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
5457 | } | |
5458 | if (opc3 & 0x01) { | |
5459 | /* Signed */ | |
5460 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5461 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5462 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5463 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5464 | if (opc3 & 0x02) { |
182608d4 AJ |
5465 | /* Saturate */ |
5466 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5467 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5468 | } | |
5469 | } else { | |
5470 | /* Unsigned */ | |
5471 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5472 | if (opc3 & 0x02) { |
182608d4 AJ |
5473 | /* Saturate */ |
5474 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5475 | } | |
5476 | } | |
5477 | if (opc3 & 0x10) { | |
5478 | /* Check overflow */ | |
5479 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
5480 | } | |
5481 | gen_set_label(l1); | |
5482 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5483 | } | |
5484 | } else { | |
5485 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5486 | } |
182608d4 AJ |
5487 | tcg_temp_free(t0); |
5488 | tcg_temp_free(t1); | |
76a66253 JM |
5489 | if (unlikely(Rc) != 0) { |
5490 | /* Update Rc0 */ | |
182608d4 | 5491 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5492 | } |
5493 | } | |
5494 | ||
a750fc0b | 5495 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5496 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5497 | { \ |
5498 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5499 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5500 | } | |
5501 | ||
5502 | /* macchw - macchw. */ | |
a750fc0b | 5503 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5504 | /* macchwo - macchwo. */ |
a750fc0b | 5505 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5506 | /* macchws - macchws. */ |
a750fc0b | 5507 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5508 | /* macchwso - macchwso. */ |
a750fc0b | 5509 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5510 | /* macchwsu - macchwsu. */ |
a750fc0b | 5511 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5512 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5513 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5514 | /* macchwu - macchwu. */ |
a750fc0b | 5515 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5516 | /* macchwuo - macchwuo. */ |
a750fc0b | 5517 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5518 | /* machhw - machhw. */ |
a750fc0b | 5519 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5520 | /* machhwo - machhwo. */ |
a750fc0b | 5521 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5522 | /* machhws - machhws. */ |
a750fc0b | 5523 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5524 | /* machhwso - machhwso. */ |
a750fc0b | 5525 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5526 | /* machhwsu - machhwsu. */ |
a750fc0b | 5527 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5528 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5529 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5530 | /* machhwu - machhwu. */ |
a750fc0b | 5531 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5532 | /* machhwuo - machhwuo. */ |
a750fc0b | 5533 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5534 | /* maclhw - maclhw. */ |
a750fc0b | 5535 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5536 | /* maclhwo - maclhwo. */ |
a750fc0b | 5537 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5538 | /* maclhws - maclhws. */ |
a750fc0b | 5539 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5540 | /* maclhwso - maclhwso. */ |
a750fc0b | 5541 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5542 | /* maclhwu - maclhwu. */ |
a750fc0b | 5543 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5544 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5545 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5546 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5547 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5548 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5549 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5550 | /* nmacchw - nmacchw. */ |
a750fc0b | 5551 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5552 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5553 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5554 | /* nmacchws - nmacchws. */ |
a750fc0b | 5555 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5556 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5557 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5558 | /* nmachhw - nmachhw. */ |
a750fc0b | 5559 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5560 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5561 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5562 | /* nmachhws - nmachhws. */ |
a750fc0b | 5563 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5564 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5565 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5566 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5567 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5568 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5569 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5570 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5571 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5572 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5573 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5574 | |
5575 | /* mulchw - mulchw. */ | |
a750fc0b | 5576 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5577 | /* mulchwu - mulchwu. */ |
a750fc0b | 5578 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5579 | /* mulhhw - mulhhw. */ |
a750fc0b | 5580 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5581 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5582 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5583 | /* mullhw - mullhw. */ |
a750fc0b | 5584 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5585 | /* mullhwu - mullhwu. */ |
a750fc0b | 5586 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5587 | |
5588 | /* mfdcr */ | |
99e300ef | 5589 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5590 | { |
5591 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5592 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5593 | #else |
06dca6a7 | 5594 | TCGv dcrn; |
76db3ba4 | 5595 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5596 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5597 | return; |
5598 | } | |
06dca6a7 AJ |
5599 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5600 | gen_update_nip(ctx, ctx->nip - 4); | |
5601 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
5602 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn); | |
5603 | tcg_temp_free(dcrn); | |
76a66253 JM |
5604 | #endif |
5605 | } | |
5606 | ||
5607 | /* mtdcr */ | |
99e300ef | 5608 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5609 | { |
5610 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5611 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5612 | #else |
06dca6a7 | 5613 | TCGv dcrn; |
76db3ba4 | 5614 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5615 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5616 | return; |
5617 | } | |
06dca6a7 AJ |
5618 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5619 | gen_update_nip(ctx, ctx->nip - 4); | |
5620 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
5621 | gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]); | |
5622 | tcg_temp_free(dcrn); | |
a42bd6cc JM |
5623 | #endif |
5624 | } | |
5625 | ||
5626 | /* mfdcrx */ | |
2662a059 | 5627 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5628 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5629 | { |
5630 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5631 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5632 | #else |
76db3ba4 | 5633 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5634 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5635 | return; |
5636 | } | |
06dca6a7 AJ |
5637 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5638 | gen_update_nip(ctx, ctx->nip - 4); | |
5639 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5640 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
5641 | #endif |
5642 | } | |
5643 | ||
5644 | /* mtdcrx */ | |
2662a059 | 5645 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5646 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5647 | { |
5648 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5649 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5650 | #else |
76db3ba4 | 5651 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5652 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5653 | return; |
5654 | } | |
06dca6a7 AJ |
5655 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5656 | gen_update_nip(ctx, ctx->nip - 4); | |
5657 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5658 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
5659 | #endif |
5660 | } | |
5661 | ||
a750fc0b | 5662 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5663 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5664 | { |
06dca6a7 AJ |
5665 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5666 | gen_update_nip(ctx, ctx->nip - 4); | |
5667 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5668 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5669 | } | |
5670 | ||
5671 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5672 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5673 | { |
06dca6a7 AJ |
5674 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5675 | gen_update_nip(ctx, ctx->nip - 4); | |
5676 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b JM |
5677 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5678 | } | |
5679 | ||
76a66253 | 5680 | /* dccci */ |
99e300ef | 5681 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
5682 | { |
5683 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5684 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5685 | #else |
76db3ba4 | 5686 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5687 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5688 | return; |
5689 | } | |
5690 | /* interpreted as no-op */ | |
5691 | #endif | |
5692 | } | |
5693 | ||
5694 | /* dcread */ | |
99e300ef | 5695 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5696 | { |
5697 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5698 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5699 | #else |
b61f2753 | 5700 | TCGv EA, val; |
76db3ba4 | 5701 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5702 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5703 | return; |
5704 | } | |
76db3ba4 | 5705 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5706 | EA = tcg_temp_new(); |
76db3ba4 | 5707 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5708 | val = tcg_temp_new(); |
76db3ba4 | 5709 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5710 | tcg_temp_free(val); |
5711 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5712 | tcg_temp_free(EA); | |
76a66253 JM |
5713 | #endif |
5714 | } | |
5715 | ||
5716 | /* icbt */ | |
e8eaa2c0 | 5717 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5718 | { |
5719 | /* interpreted as no-op */ | |
5720 | /* XXX: specification say this is treated as a load by the MMU | |
5721 | * but does not generate any exception | |
5722 | */ | |
5723 | } | |
5724 | ||
5725 | /* iccci */ | |
99e300ef | 5726 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
5727 | { |
5728 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5729 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5730 | #else |
76db3ba4 | 5731 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5732 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5733 | return; |
5734 | } | |
5735 | /* interpreted as no-op */ | |
5736 | #endif | |
5737 | } | |
5738 | ||
5739 | /* icread */ | |
99e300ef | 5740 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
5741 | { |
5742 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5743 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5744 | #else |
76db3ba4 | 5745 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5746 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5747 | return; |
5748 | } | |
5749 | /* interpreted as no-op */ | |
5750 | #endif | |
5751 | } | |
5752 | ||
76db3ba4 | 5753 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 5754 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5755 | { |
5756 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5757 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5758 | #else |
76db3ba4 | 5759 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5760 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5761 | return; |
5762 | } | |
5763 | /* Restore CPU state */ | |
d72a19f7 | 5764 | gen_helper_40x_rfci(); |
e06fcd75 | 5765 | gen_sync_exception(ctx); |
a42bd6cc JM |
5766 | #endif |
5767 | } | |
5768 | ||
99e300ef | 5769 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5770 | { |
5771 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5772 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5773 | #else |
76db3ba4 | 5774 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5775 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5776 | return; |
5777 | } | |
5778 | /* Restore CPU state */ | |
d72a19f7 | 5779 | gen_helper_rfci(); |
e06fcd75 | 5780 | gen_sync_exception(ctx); |
a42bd6cc JM |
5781 | #endif |
5782 | } | |
5783 | ||
5784 | /* BookE specific */ | |
99e300ef | 5785 | |
54623277 | 5786 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5787 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5788 | { |
5789 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5790 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5791 | #else |
76db3ba4 | 5792 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5793 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5794 | return; |
5795 | } | |
5796 | /* Restore CPU state */ | |
d72a19f7 | 5797 | gen_helper_rfdi(); |
e06fcd75 | 5798 | gen_sync_exception(ctx); |
76a66253 JM |
5799 | #endif |
5800 | } | |
5801 | ||
2662a059 | 5802 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5803 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5804 | { |
5805 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5806 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5807 | #else |
76db3ba4 | 5808 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5809 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5810 | return; |
5811 | } | |
5812 | /* Restore CPU state */ | |
d72a19f7 | 5813 | gen_helper_rfmci(); |
e06fcd75 | 5814 | gen_sync_exception(ctx); |
a42bd6cc JM |
5815 | #endif |
5816 | } | |
5eb7995e | 5817 | |
d9bce9d9 | 5818 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5819 | |
54623277 | 5820 | /* tlbre */ |
e8eaa2c0 | 5821 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5822 | { |
5823 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5824 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5825 | #else |
76db3ba4 | 5826 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5827 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5828 | return; |
5829 | } | |
5830 | switch (rB(ctx->opcode)) { | |
5831 | case 0: | |
74d37793 | 5832 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5833 | break; |
5834 | case 1: | |
74d37793 | 5835 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5836 | break; |
5837 | default: | |
e06fcd75 | 5838 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5839 | break; |
9a64fbe4 | 5840 | } |
76a66253 JM |
5841 | #endif |
5842 | } | |
5843 | ||
d9bce9d9 | 5844 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5845 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5846 | { |
5847 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5848 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5849 | #else |
74d37793 | 5850 | TCGv t0; |
76db3ba4 | 5851 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5852 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5853 | return; |
5854 | } | |
74d37793 | 5855 | t0 = tcg_temp_new(); |
76db3ba4 | 5856 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5857 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
5858 | tcg_temp_free(t0); | |
5859 | if (Rc(ctx->opcode)) { | |
5860 | int l1 = gen_new_label(); | |
5861 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
5862 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
5863 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
5864 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); | |
5865 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5866 | gen_set_label(l1); | |
5867 | } | |
76a66253 | 5868 | #endif |
79aceca5 FB |
5869 | } |
5870 | ||
76a66253 | 5871 | /* tlbwe */ |
e8eaa2c0 | 5872 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 5873 | { |
76a66253 | 5874 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5875 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5876 | #else |
76db3ba4 | 5877 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5878 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5879 | return; |
5880 | } | |
5881 | switch (rB(ctx->opcode)) { | |
5882 | case 0: | |
74d37793 | 5883 | gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
76a66253 JM |
5884 | break; |
5885 | case 1: | |
74d37793 | 5886 | gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
76a66253 JM |
5887 | break; |
5888 | default: | |
e06fcd75 | 5889 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5890 | break; |
9a64fbe4 | 5891 | } |
76a66253 JM |
5892 | #endif |
5893 | } | |
5894 | ||
a4bb6c3e | 5895 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 5896 | |
54623277 | 5897 | /* tlbre */ |
e8eaa2c0 | 5898 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
5899 | { |
5900 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5901 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 5902 | #else |
76db3ba4 | 5903 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5904 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
5905 | return; |
5906 | } | |
5907 | switch (rB(ctx->opcode)) { | |
5908 | case 0: | |
5eb7995e | 5909 | case 1: |
5eb7995e | 5910 | case 2: |
74d37793 AJ |
5911 | { |
5912 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
5823947f | 5913 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]); |
74d37793 AJ |
5914 | tcg_temp_free_i32(t0); |
5915 | } | |
5eb7995e JM |
5916 | break; |
5917 | default: | |
e06fcd75 | 5918 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5919 | break; |
5920 | } | |
5921 | #endif | |
5922 | } | |
5923 | ||
5924 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 5925 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
5926 | { |
5927 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5928 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 5929 | #else |
74d37793 | 5930 | TCGv t0; |
76db3ba4 | 5931 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5932 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
5933 | return; |
5934 | } | |
74d37793 | 5935 | t0 = tcg_temp_new(); |
76db3ba4 | 5936 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5937 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
5938 | tcg_temp_free(t0); | |
5939 | if (Rc(ctx->opcode)) { | |
5940 | int l1 = gen_new_label(); | |
5941 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
5942 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
5943 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
5944 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); | |
5945 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5946 | gen_set_label(l1); | |
5947 | } | |
5eb7995e JM |
5948 | #endif |
5949 | } | |
5950 | ||
5951 | /* tlbwe */ | |
e8eaa2c0 | 5952 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
5953 | { |
5954 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5955 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 5956 | #else |
76db3ba4 | 5957 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5958 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
5959 | return; |
5960 | } | |
5961 | switch (rB(ctx->opcode)) { | |
5962 | case 0: | |
5eb7995e | 5963 | case 1: |
5eb7995e | 5964 | case 2: |
74d37793 AJ |
5965 | { |
5966 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
5967 | gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
5968 | tcg_temp_free_i32(t0); | |
5969 | } | |
5eb7995e JM |
5970 | break; |
5971 | default: | |
e06fcd75 | 5972 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5973 | break; |
5974 | } | |
5975 | #endif | |
5976 | } | |
5977 | ||
76a66253 | 5978 | /* wrtee */ |
99e300ef | 5979 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
5980 | { |
5981 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5982 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5983 | #else |
6527f6ea | 5984 | TCGv t0; |
76db3ba4 | 5985 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5986 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5987 | return; |
5988 | } | |
6527f6ea AJ |
5989 | t0 = tcg_temp_new(); |
5990 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
5991 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
5992 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
5993 | tcg_temp_free(t0); | |
dee96f6c JM |
5994 | /* Stop translation to have a chance to raise an exception |
5995 | * if we just set msr_ee to 1 | |
5996 | */ | |
e06fcd75 | 5997 | gen_stop_exception(ctx); |
76a66253 JM |
5998 | #endif |
5999 | } | |
6000 | ||
6001 | /* wrteei */ | |
99e300ef | 6002 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6003 | { |
6004 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6005 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6006 | #else |
76db3ba4 | 6007 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6008 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6009 | return; |
6010 | } | |
fbe73008 | 6011 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6012 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6013 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6014 | gen_stop_exception(ctx); |
6527f6ea | 6015 | } else { |
1b6e5f99 | 6016 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6017 | } |
76a66253 JM |
6018 | #endif |
6019 | } | |
6020 | ||
08e46e54 | 6021 | /* PowerPC 440 specific instructions */ |
99e300ef | 6022 | |
54623277 | 6023 | /* dlmzb */ |
99e300ef | 6024 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6025 | { |
ef0d51af AJ |
6026 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
6027 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
6028 | cpu_gpr[rB(ctx->opcode)], t0); | |
6029 | tcg_temp_free_i32(t0); | |
76a66253 JM |
6030 | } |
6031 | ||
6032 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6033 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6034 | { |
6035 | /* interpreted as no-op */ | |
6036 | } | |
6037 | ||
6038 | /* msync replaces sync on 440 */ | |
99e300ef | 6039 | static void gen_msync(DisasContext *ctx) |
76a66253 JM |
6040 | { |
6041 | /* interpreted as no-op */ | |
6042 | } | |
6043 | ||
6044 | /* icbt */ | |
e8eaa2c0 | 6045 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6046 | { |
6047 | /* interpreted as no-op */ | |
6048 | /* XXX: specification say this is treated as a load by the MMU | |
6049 | * but does not generate any exception | |
6050 | */ | |
79aceca5 FB |
6051 | } |
6052 | ||
a9d9eb8f JM |
6053 | /*** Altivec vector extension ***/ |
6054 | /* Altivec registers moves */ | |
a9d9eb8f | 6055 | |
636aa200 | 6056 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6057 | { |
e4704b3b | 6058 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6059 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6060 | return r; | |
6061 | } | |
6062 | ||
a9d9eb8f | 6063 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6064 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6065 | { \ |
fe1e5c53 | 6066 | TCGv EA; \ |
a9d9eb8f | 6067 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6068 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6069 | return; \ |
6070 | } \ | |
76db3ba4 | 6071 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6072 | EA = tcg_temp_new(); \ |
76db3ba4 | 6073 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6074 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6075 | if (ctx->le_mode) { \ |
6076 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6077 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6078 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6079 | } else { \ |
76db3ba4 | 6080 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6081 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6082 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6083 | } \ |
6084 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6085 | } |
6086 | ||
6087 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6088 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6089 | { \ |
fe1e5c53 | 6090 | TCGv EA; \ |
a9d9eb8f | 6091 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6092 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6093 | return; \ |
6094 | } \ | |
76db3ba4 | 6095 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6096 | EA = tcg_temp_new(); \ |
76db3ba4 | 6097 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6098 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6099 | if (ctx->le_mode) { \ |
6100 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6101 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6102 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6103 | } else { \ |
76db3ba4 | 6104 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6105 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6106 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6107 | } \ |
6108 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6109 | } |
6110 | ||
cbfb6ae9 | 6111 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef | 6112 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6113 | { \ |
6114 | TCGv EA; \ | |
6115 | TCGv_ptr rs; \ | |
6116 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6117 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6118 | return; \ | |
6119 | } \ | |
6120 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6121 | EA = tcg_temp_new(); \ | |
6122 | gen_addr_reg_index(ctx, EA); \ | |
6123 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
6124 | gen_helper_lve##name (rs, EA); \ | |
6125 | tcg_temp_free(EA); \ | |
6126 | tcg_temp_free_ptr(rs); \ | |
6127 | } | |
6128 | ||
6129 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef | 6130 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6131 | { \ |
6132 | TCGv EA; \ | |
6133 | TCGv_ptr rs; \ | |
6134 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6135 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6136 | return; \ | |
6137 | } \ | |
6138 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6139 | EA = tcg_temp_new(); \ | |
6140 | gen_addr_reg_index(ctx, EA); \ | |
6141 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
6142 | gen_helper_stve##name (rs, EA); \ | |
6143 | tcg_temp_free(EA); \ | |
6144 | tcg_temp_free_ptr(rs); \ | |
6145 | } | |
6146 | ||
fe1e5c53 | 6147 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6148 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6149 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6150 | |
cbfb6ae9 AJ |
6151 | GEN_VR_LVE(bx, 0x07, 0x00); |
6152 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6153 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6154 | ||
fe1e5c53 | 6155 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6156 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6157 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6158 | |
cbfb6ae9 AJ |
6159 | GEN_VR_STVE(bx, 0x07, 0x04); |
6160 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6161 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6162 | ||
99e300ef | 6163 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6164 | { |
6165 | TCGv_ptr rd; | |
6166 | TCGv EA; | |
6167 | if (unlikely(!ctx->altivec_enabled)) { | |
6168 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6169 | return; | |
6170 | } | |
6171 | EA = tcg_temp_new(); | |
6172 | gen_addr_reg_index(ctx, EA); | |
6173 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6174 | gen_helper_lvsl(rd, EA); | |
6175 | tcg_temp_free(EA); | |
6176 | tcg_temp_free_ptr(rd); | |
6177 | } | |
6178 | ||
99e300ef | 6179 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6180 | { |
6181 | TCGv_ptr rd; | |
6182 | TCGv EA; | |
6183 | if (unlikely(!ctx->altivec_enabled)) { | |
6184 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6185 | return; | |
6186 | } | |
6187 | EA = tcg_temp_new(); | |
6188 | gen_addr_reg_index(ctx, EA); | |
6189 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6190 | gen_helper_lvsr(rd, EA); | |
6191 | tcg_temp_free(EA); | |
6192 | tcg_temp_free_ptr(rd); | |
6193 | } | |
6194 | ||
99e300ef | 6195 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6196 | { |
6197 | TCGv_i32 t; | |
6198 | if (unlikely(!ctx->altivec_enabled)) { | |
6199 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6200 | return; | |
6201 | } | |
6202 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6203 | t = tcg_temp_new_i32(); | |
6204 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr)); | |
6205 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); | |
fce5ecb7 | 6206 | tcg_temp_free_i32(t); |
785f451b AJ |
6207 | } |
6208 | ||
99e300ef | 6209 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6210 | { |
6e87b7c7 | 6211 | TCGv_ptr p; |
785f451b AJ |
6212 | if (unlikely(!ctx->altivec_enabled)) { |
6213 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6214 | return; | |
6215 | } | |
6e87b7c7 AJ |
6216 | p = gen_avr_ptr(rD(ctx->opcode)); |
6217 | gen_helper_mtvscr(p); | |
6218 | tcg_temp_free_ptr(p); | |
785f451b AJ |
6219 | } |
6220 | ||
7a9b96cf AJ |
6221 | /* Logical operations */ |
6222 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6223 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6224 | { \ |
6225 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6226 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6227 | return; \ | |
6228 | } \ | |
6229 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6230 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6231 | } | |
6232 | ||
6233 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6234 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6235 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6236 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6237 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
6238 | ||
8e27dd6f | 6239 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6240 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6241 | { \ |
6242 | TCGv_ptr ra, rb, rd; \ | |
6243 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6244 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6245 | return; \ | |
6246 | } \ | |
6247 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6248 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6249 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6250 | gen_helper_##name (rd, ra, rb); \ | |
6251 | tcg_temp_free_ptr(ra); \ | |
6252 | tcg_temp_free_ptr(rb); \ | |
6253 | tcg_temp_free_ptr(rd); \ | |
6254 | } | |
6255 | ||
7872c51c AJ |
6256 | GEN_VXFORM(vaddubm, 0, 0); |
6257 | GEN_VXFORM(vadduhm, 0, 1); | |
6258 | GEN_VXFORM(vadduwm, 0, 2); | |
6259 | GEN_VXFORM(vsububm, 0, 16); | |
6260 | GEN_VXFORM(vsubuhm, 0, 17); | |
6261 | GEN_VXFORM(vsubuwm, 0, 18); | |
e4039339 AJ |
6262 | GEN_VXFORM(vmaxub, 1, 0); |
6263 | GEN_VXFORM(vmaxuh, 1, 1); | |
6264 | GEN_VXFORM(vmaxuw, 1, 2); | |
6265 | GEN_VXFORM(vmaxsb, 1, 4); | |
6266 | GEN_VXFORM(vmaxsh, 1, 5); | |
6267 | GEN_VXFORM(vmaxsw, 1, 6); | |
6268 | GEN_VXFORM(vminub, 1, 8); | |
6269 | GEN_VXFORM(vminuh, 1, 9); | |
6270 | GEN_VXFORM(vminuw, 1, 10); | |
6271 | GEN_VXFORM(vminsb, 1, 12); | |
6272 | GEN_VXFORM(vminsh, 1, 13); | |
6273 | GEN_VXFORM(vminsw, 1, 14); | |
fab3cbe9 AJ |
6274 | GEN_VXFORM(vavgub, 1, 16); |
6275 | GEN_VXFORM(vavguh, 1, 17); | |
6276 | GEN_VXFORM(vavguw, 1, 18); | |
6277 | GEN_VXFORM(vavgsb, 1, 20); | |
6278 | GEN_VXFORM(vavgsh, 1, 21); | |
6279 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6280 | GEN_VXFORM(vmrghb, 6, 0); |
6281 | GEN_VXFORM(vmrghh, 6, 1); | |
6282 | GEN_VXFORM(vmrghw, 6, 2); | |
6283 | GEN_VXFORM(vmrglb, 6, 4); | |
6284 | GEN_VXFORM(vmrglh, 6, 5); | |
6285 | GEN_VXFORM(vmrglw, 6, 6); | |
2c277908 AJ |
6286 | GEN_VXFORM(vmuloub, 4, 0); |
6287 | GEN_VXFORM(vmulouh, 4, 1); | |
6288 | GEN_VXFORM(vmulosb, 4, 4); | |
6289 | GEN_VXFORM(vmulosh, 4, 5); | |
6290 | GEN_VXFORM(vmuleub, 4, 8); | |
6291 | GEN_VXFORM(vmuleuh, 4, 9); | |
6292 | GEN_VXFORM(vmulesb, 4, 12); | |
6293 | GEN_VXFORM(vmulesh, 4, 13); | |
d79f0809 AJ |
6294 | GEN_VXFORM(vslb, 2, 4); |
6295 | GEN_VXFORM(vslh, 2, 5); | |
6296 | GEN_VXFORM(vslw, 2, 6); | |
07ef34c3 AJ |
6297 | GEN_VXFORM(vsrb, 2, 8); |
6298 | GEN_VXFORM(vsrh, 2, 9); | |
6299 | GEN_VXFORM(vsrw, 2, 10); | |
6300 | GEN_VXFORM(vsrab, 2, 12); | |
6301 | GEN_VXFORM(vsrah, 2, 13); | |
6302 | GEN_VXFORM(vsraw, 2, 14); | |
7b239bec AJ |
6303 | GEN_VXFORM(vslo, 6, 16); |
6304 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
6305 | GEN_VXFORM(vaddcuw, 0, 6); |
6306 | GEN_VXFORM(vsubcuw, 0, 22); | |
5ab09f33 AJ |
6307 | GEN_VXFORM(vaddubs, 0, 8); |
6308 | GEN_VXFORM(vadduhs, 0, 9); | |
6309 | GEN_VXFORM(vadduws, 0, 10); | |
6310 | GEN_VXFORM(vaddsbs, 0, 12); | |
6311 | GEN_VXFORM(vaddshs, 0, 13); | |
6312 | GEN_VXFORM(vaddsws, 0, 14); | |
6313 | GEN_VXFORM(vsububs, 0, 24); | |
6314 | GEN_VXFORM(vsubuhs, 0, 25); | |
6315 | GEN_VXFORM(vsubuws, 0, 26); | |
6316 | GEN_VXFORM(vsubsbs, 0, 28); | |
6317 | GEN_VXFORM(vsubshs, 0, 29); | |
6318 | GEN_VXFORM(vsubsws, 0, 30); | |
5e1d0985 AJ |
6319 | GEN_VXFORM(vrlb, 2, 0); |
6320 | GEN_VXFORM(vrlh, 2, 1); | |
6321 | GEN_VXFORM(vrlw, 2, 2); | |
d9430add AJ |
6322 | GEN_VXFORM(vsl, 2, 7); |
6323 | GEN_VXFORM(vsr, 2, 11); | |
5335a145 AJ |
6324 | GEN_VXFORM(vpkuhum, 7, 0); |
6325 | GEN_VXFORM(vpkuwum, 7, 1); | |
6326 | GEN_VXFORM(vpkuhus, 7, 2); | |
6327 | GEN_VXFORM(vpkuwus, 7, 3); | |
6328 | GEN_VXFORM(vpkshus, 7, 4); | |
6329 | GEN_VXFORM(vpkswus, 7, 5); | |
6330 | GEN_VXFORM(vpkshss, 7, 6); | |
6331 | GEN_VXFORM(vpkswss, 7, 7); | |
1dd9ffb9 | 6332 | GEN_VXFORM(vpkpx, 7, 12); |
8142cddd AJ |
6333 | GEN_VXFORM(vsum4ubs, 4, 24); |
6334 | GEN_VXFORM(vsum4sbs, 4, 28); | |
6335 | GEN_VXFORM(vsum4shs, 4, 25); | |
6336 | GEN_VXFORM(vsum2sws, 4, 26); | |
6337 | GEN_VXFORM(vsumsws, 4, 30); | |
56fdd213 AJ |
6338 | GEN_VXFORM(vaddfp, 5, 0); |
6339 | GEN_VXFORM(vsubfp, 5, 1); | |
1536ff64 AJ |
6340 | GEN_VXFORM(vmaxfp, 5, 16); |
6341 | GEN_VXFORM(vminfp, 5, 17); | |
fab3cbe9 | 6342 | |
0cbcd906 | 6343 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 6344 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
6345 | { \ |
6346 | TCGv_ptr ra, rb, rd; \ | |
6347 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6348 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6349 | return; \ | |
6350 | } \ | |
6351 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6352 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6353 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6354 | gen_helper_##opname (rd, ra, rb); \ | |
6355 | tcg_temp_free_ptr(ra); \ | |
6356 | tcg_temp_free_ptr(rb); \ | |
6357 | tcg_temp_free_ptr(rd); \ | |
6358 | } | |
6359 | ||
6360 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
6361 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
6362 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
6363 | ||
1add6e23 AJ |
6364 | GEN_VXRFORM(vcmpequb, 3, 0) |
6365 | GEN_VXRFORM(vcmpequh, 3, 1) | |
6366 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6367 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
6368 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
6369 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6370 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
6371 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
6372 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
819ca121 AJ |
6373 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6374 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
6375 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
6376 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 6377 | |
c026766b | 6378 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6379 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
6380 | { \ |
6381 | TCGv_ptr rd; \ | |
6382 | TCGv_i32 simm; \ | |
6383 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6384 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6385 | return; \ | |
6386 | } \ | |
6387 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6388 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6389 | gen_helper_##name (rd, simm); \ | |
6390 | tcg_temp_free_i32(simm); \ | |
6391 | tcg_temp_free_ptr(rd); \ | |
6392 | } | |
6393 | ||
6394 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
6395 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
6396 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
6397 | ||
de5f2484 | 6398 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 6399 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
6400 | { \ |
6401 | TCGv_ptr rb, rd; \ | |
6402 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6403 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6404 | return; \ | |
6405 | } \ | |
6406 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6407 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6408 | gen_helper_##name (rd, rb); \ | |
6409 | tcg_temp_free_ptr(rb); \ | |
6410 | tcg_temp_free_ptr(rd); \ | |
6411 | } | |
6412 | ||
6cf1c6e5 AJ |
6413 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6414 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
6415 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
6416 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
79f85c3a AJ |
6417 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6418 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
bdfbac35 | 6419 | GEN_VXFORM_NOA(vrefp, 5, 4); |
071fc3b1 | 6420 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5); |
0bffbc6c | 6421 | GEN_VXFORM_NOA(vexptefp, 5, 6); |
b580763f | 6422 | GEN_VXFORM_NOA(vlogefp, 5, 7); |
f6b19645 AJ |
6423 | GEN_VXFORM_NOA(vrfim, 5, 8); |
6424 | GEN_VXFORM_NOA(vrfin, 5, 9); | |
6425 | GEN_VXFORM_NOA(vrfip, 5, 10); | |
6426 | GEN_VXFORM_NOA(vrfiz, 5, 11); | |
79f85c3a | 6427 | |
21d21583 | 6428 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6429 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
6430 | { \ |
6431 | TCGv_ptr rd; \ | |
6432 | TCGv_i32 simm; \ | |
6433 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6434 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6435 | return; \ | |
6436 | } \ | |
6437 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6438 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6439 | gen_helper_##name (rd, simm); \ | |
6440 | tcg_temp_free_i32(simm); \ | |
6441 | tcg_temp_free_ptr(rd); \ | |
6442 | } | |
6443 | ||
27a4edb3 | 6444 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 6445 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
6446 | { \ |
6447 | TCGv_ptr rb, rd; \ | |
6448 | TCGv_i32 uimm; \ | |
6449 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6450 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6451 | return; \ | |
6452 | } \ | |
6453 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6454 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6455 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6456 | gen_helper_##name (rd, rb, uimm); \ | |
6457 | tcg_temp_free_i32(uimm); \ | |
6458 | tcg_temp_free_ptr(rb); \ | |
6459 | tcg_temp_free_ptr(rd); \ | |
6460 | } | |
6461 | ||
e4e6bee7 AJ |
6462 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6463 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
6464 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
e140632e AJ |
6465 | GEN_VXFORM_UIMM(vcfux, 5, 12); |
6466 | GEN_VXFORM_UIMM(vcfsx, 5, 13); | |
875b31db AJ |
6467 | GEN_VXFORM_UIMM(vctuxs, 5, 14); |
6468 | GEN_VXFORM_UIMM(vctsxs, 5, 15); | |
e4e6bee7 | 6469 | |
99e300ef | 6470 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
6471 | { |
6472 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 6473 | TCGv_i32 sh; |
cd633b10 AJ |
6474 | if (unlikely(!ctx->altivec_enabled)) { |
6475 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6476 | return; | |
6477 | } | |
6478 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6479 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6480 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6481 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
6482 | gen_helper_vsldoi (rd, ra, rb, sh); | |
6483 | tcg_temp_free_ptr(ra); | |
6484 | tcg_temp_free_ptr(rb); | |
6485 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 6486 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
6487 | } |
6488 | ||
707cec33 | 6489 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
99e300ef | 6490 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
6491 | { \ |
6492 | TCGv_ptr ra, rb, rc, rd; \ | |
6493 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6494 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6495 | return; \ | |
6496 | } \ | |
6497 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6498 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6499 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6500 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6501 | if (Rc(ctx->opcode)) { \ | |
6502 | gen_helper_##name1 (rd, ra, rb, rc); \ | |
6503 | } else { \ | |
6504 | gen_helper_##name0 (rd, ra, rb, rc); \ | |
6505 | } \ | |
6506 | tcg_temp_free_ptr(ra); \ | |
6507 | tcg_temp_free_ptr(rb); \ | |
6508 | tcg_temp_free_ptr(rc); \ | |
6509 | tcg_temp_free_ptr(rd); \ | |
6510 | } | |
6511 | ||
b161ae27 AJ |
6512 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
6513 | ||
99e300ef | 6514 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
6515 | { |
6516 | TCGv_ptr ra, rb, rc, rd; | |
6517 | if (unlikely(!ctx->altivec_enabled)) { | |
6518 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6519 | return; | |
6520 | } | |
6521 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6522 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6523 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
6524 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6525 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
6526 | tcg_temp_free_ptr(ra); | |
6527 | tcg_temp_free_ptr(rb); | |
6528 | tcg_temp_free_ptr(rc); | |
6529 | tcg_temp_free_ptr(rd); | |
6530 | } | |
6531 | ||
b04ae981 | 6532 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 6533 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 6534 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 6535 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 6536 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 6537 | |
0487d6a8 | 6538 | /*** SPE extension ***/ |
0487d6a8 | 6539 | /* Register moves */ |
3cd7d1dd | 6540 | |
a0e13900 FC |
6541 | |
6542 | static inline void gen_evmra(DisasContext *ctx) | |
6543 | { | |
6544 | ||
6545 | if (unlikely(!ctx->spe_enabled)) { | |
6546 | gen_exception(ctx, POWERPC_EXCP_APU); | |
6547 | return; | |
6548 | } | |
6549 | ||
6550 | #if defined(TARGET_PPC64) | |
6551 | /* rD := rA */ | |
6552 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6553 | ||
6554 | /* spe_acc := rA */ | |
6555 | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], | |
6556 | cpu_env, | |
6557 | offsetof(CPUState, spe_acc)); | |
6558 | #else | |
6559 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
6560 | ||
6561 | /* tmp := rA_lo + rA_hi << 32 */ | |
6562 | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6563 | ||
6564 | /* spe_acc := tmp */ | |
6565 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); | |
6566 | tcg_temp_free_i64(tmp); | |
6567 | ||
6568 | /* rD := rA */ | |
6569 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6570 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6571 | #endif | |
6572 | } | |
6573 | ||
636aa200 BS |
6574 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
6575 | { | |
f78fb44e AJ |
6576 | #if defined(TARGET_PPC64) |
6577 | tcg_gen_mov_i64(t, cpu_gpr[reg]); | |
6578 | #else | |
36aa55dc | 6579 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
3cd7d1dd | 6580 | #endif |
f78fb44e | 6581 | } |
3cd7d1dd | 6582 | |
636aa200 BS |
6583 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
6584 | { | |
f78fb44e AJ |
6585 | #if defined(TARGET_PPC64) |
6586 | tcg_gen_mov_i64(cpu_gpr[reg], t); | |
6587 | #else | |
a7812ae4 | 6588 | TCGv_i64 tmp = tcg_temp_new_i64(); |
f78fb44e | 6589 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
f78fb44e AJ |
6590 | tcg_gen_shri_i64(tmp, t, 32); |
6591 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); | |
a7812ae4 | 6592 | tcg_temp_free_i64(tmp); |
3cd7d1dd | 6593 | #endif |
f78fb44e | 6594 | } |
3cd7d1dd | 6595 | |
0487d6a8 | 6596 | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \ |
99e300ef | 6597 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
6598 | { \ |
6599 | if (Rc(ctx->opcode)) \ | |
6600 | gen_##name1(ctx); \ | |
6601 | else \ | |
6602 | gen_##name0(ctx); \ | |
6603 | } | |
6604 | ||
6605 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 6606 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 6607 | { |
e06fcd75 | 6608 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
6609 | } |
6610 | ||
57951c27 AJ |
6611 | /* SPE logic */ |
6612 | #if defined(TARGET_PPC64) | |
6613 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6614 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6615 | { \ |
6616 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6617 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
6618 | return; \ |
6619 | } \ | |
57951c27 AJ |
6620 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6621 | cpu_gpr[rB(ctx->opcode)]); \ | |
6622 | } | |
6623 | #else | |
6624 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6625 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6626 | { \ |
6627 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6628 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
6629 | return; \ |
6630 | } \ | |
6631 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
6632 | cpu_gpr[rB(ctx->opcode)]); \ | |
6633 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6634 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 6635 | } |
57951c27 AJ |
6636 | #endif |
6637 | ||
6638 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
6639 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
6640 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
6641 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
6642 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
6643 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
6644 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
6645 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 6646 | |
57951c27 AJ |
6647 | /* SPE logic immediate */ |
6648 | #if defined(TARGET_PPC64) | |
6649 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 6650 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a AJ |
6651 | { \ |
6652 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6653 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
3d3a6a0a AJ |
6654 | return; \ |
6655 | } \ | |
a7812ae4 PB |
6656 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6657 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6658 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6659 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6660 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
6661 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6662 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6663 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6664 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
6665 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6666 | tcg_temp_free_i32(t0); \ |
6667 | tcg_temp_free_i32(t1); \ | |
3d3a6a0a | 6668 | } |
57951c27 AJ |
6669 | #else |
6670 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 6671 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6672 | { \ |
6673 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6674 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
6675 | return; \ |
6676 | } \ | |
57951c27 AJ |
6677 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6678 | rB(ctx->opcode)); \ | |
6679 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6680 | rB(ctx->opcode)); \ | |
0487d6a8 | 6681 | } |
57951c27 AJ |
6682 | #endif |
6683 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); | |
6684 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
6685 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
6686 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 6687 | |
57951c27 AJ |
6688 | /* SPE arithmetic */ |
6689 | #if defined(TARGET_PPC64) | |
6690 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
636aa200 | 6691 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6692 | { \ |
6693 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6694 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
6695 | return; \ |
6696 | } \ | |
a7812ae4 PB |
6697 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6698 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6699 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6700 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6701 | tcg_op(t0, t0); \ | |
6702 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6703 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6704 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6705 | tcg_op(t1, t1); \ |
6706 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6707 | tcg_temp_free_i32(t0); \ |
6708 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 6709 | } |
57951c27 | 6710 | #else |
a7812ae4 | 6711 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 6712 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6713 | { \ |
6714 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6715 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
6716 | return; \ |
6717 | } \ | |
6718 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ | |
6719 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
6720 | } | |
6721 | #endif | |
0487d6a8 | 6722 | |
636aa200 | 6723 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
6724 | { |
6725 | int l1 = gen_new_label(); | |
6726 | int l2 = gen_new_label(); | |
0487d6a8 | 6727 | |
57951c27 AJ |
6728 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
6729 | tcg_gen_neg_i32(ret, arg1); | |
6730 | tcg_gen_br(l2); | |
6731 | gen_set_label(l1); | |
a7812ae4 | 6732 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
6733 | gen_set_label(l2); |
6734 | } | |
6735 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
6736 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
6737 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
6738 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 6739 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 6740 | { |
57951c27 AJ |
6741 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
6742 | tcg_gen_ext16u_i32(ret, ret); | |
6743 | } | |
6744 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
6745 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
6746 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 6747 | |
57951c27 AJ |
6748 | #if defined(TARGET_PPC64) |
6749 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 6750 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6751 | { \ |
6752 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6753 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
6754 | return; \ |
6755 | } \ | |
a7812ae4 PB |
6756 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6757 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6758 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ | |
501e23c4 | 6759 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
57951c27 AJ |
6760 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6761 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ | |
6762 | tcg_op(t0, t0, t2); \ | |
6763 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6764 | tcg_gen_trunc_i64_i32(t1, t3); \ | |
6765 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ | |
6766 | tcg_gen_trunc_i64_i32(t2, t3); \ | |
a7812ae4 | 6767 | tcg_temp_free_i64(t3); \ |
57951c27 | 6768 | tcg_op(t1, t1, t2); \ |
a7812ae4 | 6769 | tcg_temp_free_i32(t2); \ |
57951c27 | 6770 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
a7812ae4 PB |
6771 | tcg_temp_free_i32(t0); \ |
6772 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 6773 | } |
57951c27 AJ |
6774 | #else |
6775 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 6776 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6777 | { \ |
6778 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6779 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
6780 | return; \ |
6781 | } \ | |
57951c27 AJ |
6782 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6783 | cpu_gpr[rB(ctx->opcode)]); \ | |
6784 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6785 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 6786 | } |
57951c27 | 6787 | #endif |
0487d6a8 | 6788 | |
636aa200 | 6789 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 6790 | { |
a7812ae4 | 6791 | TCGv_i32 t0; |
57951c27 | 6792 | int l1, l2; |
0487d6a8 | 6793 | |
57951c27 AJ |
6794 | l1 = gen_new_label(); |
6795 | l2 = gen_new_label(); | |
a7812ae4 | 6796 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
6797 | /* No error here: 6 bits are used */ |
6798 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
6799 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
6800 | tcg_gen_shr_i32(ret, arg1, t0); | |
6801 | tcg_gen_br(l2); | |
6802 | gen_set_label(l1); | |
6803 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 6804 | gen_set_label(l2); |
a7812ae4 | 6805 | tcg_temp_free_i32(t0); |
57951c27 AJ |
6806 | } |
6807 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 6808 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 6809 | { |
a7812ae4 | 6810 | TCGv_i32 t0; |
57951c27 AJ |
6811 | int l1, l2; |
6812 | ||
6813 | l1 = gen_new_label(); | |
6814 | l2 = gen_new_label(); | |
a7812ae4 | 6815 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
6816 | /* No error here: 6 bits are used */ |
6817 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
6818 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
6819 | tcg_gen_sar_i32(ret, arg1, t0); | |
6820 | tcg_gen_br(l2); | |
6821 | gen_set_label(l1); | |
6822 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 6823 | gen_set_label(l2); |
a7812ae4 | 6824 | tcg_temp_free_i32(t0); |
57951c27 AJ |
6825 | } |
6826 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 6827 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 6828 | { |
a7812ae4 | 6829 | TCGv_i32 t0; |
57951c27 AJ |
6830 | int l1, l2; |
6831 | ||
6832 | l1 = gen_new_label(); | |
6833 | l2 = gen_new_label(); | |
a7812ae4 | 6834 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
6835 | /* No error here: 6 bits are used */ |
6836 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
6837 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
6838 | tcg_gen_shl_i32(ret, arg1, t0); | |
6839 | tcg_gen_br(l2); | |
6840 | gen_set_label(l1); | |
6841 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 6842 | gen_set_label(l2); |
a7812ae4 | 6843 | tcg_temp_free_i32(t0); |
57951c27 AJ |
6844 | } |
6845 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 6846 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 6847 | { |
a7812ae4 | 6848 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
6849 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
6850 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 6851 | tcg_temp_free_i32(t0); |
57951c27 AJ |
6852 | } |
6853 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 6854 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
6855 | { |
6856 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 6857 | gen_exception(ctx, POWERPC_EXCP_APU); |
57951c27 AJ |
6858 | return; |
6859 | } | |
6860 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
6861 | TCGv t0 = tcg_temp_new(); |
6862 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
6863 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
6864 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
6865 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
6866 | tcg_temp_free(t0); | |
6867 | tcg_temp_free(t1); | |
6868 | #else | |
6869 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
6870 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6871 | #endif | |
6872 | } | |
6873 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 6874 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 6875 | { |
57951c27 AJ |
6876 | tcg_gen_sub_i32(ret, arg2, arg1); |
6877 | } | |
6878 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 6879 | |
57951c27 AJ |
6880 | /* SPE arithmetic immediate */ |
6881 | #if defined(TARGET_PPC64) | |
6882 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 6883 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6884 | { \ |
6885 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6886 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
6887 | return; \ |
6888 | } \ | |
a7812ae4 PB |
6889 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6890 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6891 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6892 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
6893 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
6894 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
6895 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
e06fcd75 | 6896 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6897 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
6898 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6899 | tcg_temp_free_i32(t0); \ |
6900 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
6901 | } |
6902 | #else | |
6903 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 6904 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6905 | { \ |
6906 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6907 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
6908 | return; \ |
6909 | } \ | |
6910 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
6911 | rA(ctx->opcode)); \ | |
6912 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ | |
6913 | rA(ctx->opcode)); \ | |
6914 | } | |
6915 | #endif | |
6916 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); | |
6917 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
6918 | ||
6919 | /* SPE comparison */ | |
6920 | #if defined(TARGET_PPC64) | |
6921 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 6922 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6923 | { \ |
6924 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6925 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
6926 | return; \ |
6927 | } \ | |
6928 | int l1 = gen_new_label(); \ | |
6929 | int l2 = gen_new_label(); \ | |
6930 | int l3 = gen_new_label(); \ | |
6931 | int l4 = gen_new_label(); \ | |
a7812ae4 PB |
6932 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6933 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6934 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6935 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6936 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
6937 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ | |
a7812ae4 | 6938 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
6939 | tcg_gen_br(l2); \ |
6940 | gen_set_label(l1); \ | |
6941 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
6942 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
6943 | gen_set_label(l2); \ | |
6944 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6945 | tcg_gen_trunc_i64_i32(t0, t2); \ | |
6946 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
6947 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6948 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6949 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
6950 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
6951 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
6952 | tcg_gen_br(l4); \ | |
6953 | gen_set_label(l3); \ | |
6954 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
6955 | CRF_CH | CRF_CH_OR_CL); \ | |
6956 | gen_set_label(l4); \ | |
a7812ae4 PB |
6957 | tcg_temp_free_i32(t0); \ |
6958 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
6959 | } |
6960 | #else | |
6961 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 6962 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6963 | { \ |
6964 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6965 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
6966 | return; \ |
6967 | } \ | |
6968 | int l1 = gen_new_label(); \ | |
6969 | int l2 = gen_new_label(); \ | |
6970 | int l3 = gen_new_label(); \ | |
6971 | int l4 = gen_new_label(); \ | |
6972 | \ | |
6973 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
6974 | cpu_gpr[rB(ctx->opcode)], l1); \ | |
6975 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ | |
6976 | tcg_gen_br(l2); \ | |
6977 | gen_set_label(l1); \ | |
6978 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
6979 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
6980 | gen_set_label(l2); \ | |
6981 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ | |
6982 | cpu_gprh[rB(ctx->opcode)], l3); \ | |
6983 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
6984 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
6985 | tcg_gen_br(l4); \ | |
6986 | gen_set_label(l3); \ | |
6987 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
6988 | CRF_CH | CRF_CH_OR_CL); \ | |
6989 | gen_set_label(l4); \ | |
6990 | } | |
6991 | #endif | |
6992 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); | |
6993 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
6994 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
6995 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
6996 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
6997 | ||
6998 | /* SPE misc */ | |
636aa200 | 6999 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
7000 | { |
7001 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
7002 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
7003 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 7004 | } |
636aa200 | 7005 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
7006 | { |
7007 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 7008 | gen_exception(ctx, POWERPC_EXCP_APU); |
57951c27 AJ |
7009 | return; |
7010 | } | |
7011 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7012 | TCGv t0 = tcg_temp_new(); |
7013 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7014 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7015 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); |
7016 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7017 | tcg_temp_free(t0); | |
7018 | tcg_temp_free(t1); | |
7019 | #else | |
57951c27 | 7020 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
33890b3e | 7021 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7022 | #endif |
7023 | } | |
636aa200 | 7024 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
7025 | { |
7026 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 7027 | gen_exception(ctx, POWERPC_EXCP_APU); |
57951c27 AJ |
7028 | return; |
7029 | } | |
7030 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7031 | TCGv t0 = tcg_temp_new(); |
7032 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7033 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7034 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); |
7035 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7036 | tcg_temp_free(t0); | |
7037 | tcg_temp_free(t1); | |
7038 | #else | |
7039 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7040 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7041 | #endif | |
7042 | } | |
636aa200 | 7043 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
7044 | { |
7045 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 7046 | gen_exception(ctx, POWERPC_EXCP_APU); |
57951c27 AJ |
7047 | return; |
7048 | } | |
7049 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7050 | TCGv t0 = tcg_temp_new(); |
7051 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7052 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7053 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
7054 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7055 | tcg_temp_free(t0); | |
7056 | tcg_temp_free(t1); | |
7057 | #else | |
33890b3e NF |
7058 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
7059 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
7060 | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); | |
7061 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7062 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); | |
7063 | tcg_temp_free_i32(tmp); | |
7064 | } else { | |
7065 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7066 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7067 | } | |
57951c27 AJ |
7068 | #endif |
7069 | } | |
636aa200 | 7070 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 7071 | { |
ae01847f | 7072 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 7073 | |
57951c27 | 7074 | #if defined(TARGET_PPC64) |
38d14952 | 7075 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7076 | #else |
7077 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7078 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7079 | #endif | |
7080 | } | |
636aa200 | 7081 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 7082 | { |
ae01847f | 7083 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 7084 | |
57951c27 | 7085 | #if defined(TARGET_PPC64) |
38d14952 | 7086 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7087 | #else |
7088 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7089 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7090 | #endif | |
0487d6a8 JM |
7091 | } |
7092 | ||
636aa200 | 7093 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 AJ |
7094 | { |
7095 | int l1 = gen_new_label(); | |
7096 | int l2 = gen_new_label(); | |
7097 | int l3 = gen_new_label(); | |
7098 | int l4 = gen_new_label(); | |
a7812ae4 | 7099 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 | 7100 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
7101 | TCGv t1 = tcg_temp_local_new(); |
7102 | TCGv t2 = tcg_temp_local_new(); | |
57951c27 AJ |
7103 | #endif |
7104 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); | |
7105 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
7106 | #if defined(TARGET_PPC64) | |
7107 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7108 | #else | |
7109 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7110 | #endif | |
7111 | tcg_gen_br(l2); | |
7112 | gen_set_label(l1); | |
7113 | #if defined(TARGET_PPC64) | |
7114 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7115 | #else | |
7116 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7117 | #endif | |
7118 | gen_set_label(l2); | |
7119 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
7120 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
7121 | #if defined(TARGET_PPC64) | |
17d9b3af | 7122 | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
7123 | #else |
7124 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7125 | #endif | |
7126 | tcg_gen_br(l4); | |
7127 | gen_set_label(l3); | |
7128 | #if defined(TARGET_PPC64) | |
17d9b3af | 7129 | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7130 | #else |
7131 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7132 | #endif | |
7133 | gen_set_label(l4); | |
a7812ae4 | 7134 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7135 | #if defined(TARGET_PPC64) |
7136 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); | |
7137 | tcg_temp_free(t1); | |
7138 | tcg_temp_free(t2); | |
7139 | #endif | |
7140 | } | |
e8eaa2c0 BS |
7141 | |
7142 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
7143 | { |
7144 | gen_evsel(ctx); | |
7145 | } | |
e8eaa2c0 BS |
7146 | |
7147 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
7148 | { |
7149 | gen_evsel(ctx); | |
7150 | } | |
e8eaa2c0 BS |
7151 | |
7152 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
7153 | { |
7154 | gen_evsel(ctx); | |
7155 | } | |
e8eaa2c0 BS |
7156 | |
7157 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
7158 | { |
7159 | gen_evsel(ctx); | |
7160 | } | |
0487d6a8 | 7161 | |
a0e13900 FC |
7162 | /* Multiply */ |
7163 | ||
7164 | static inline void gen_evmwumi(DisasContext *ctx) | |
7165 | { | |
7166 | TCGv_i64 t0, t1; | |
7167 | ||
7168 | if (unlikely(!ctx->spe_enabled)) { | |
7169 | gen_exception(ctx, POWERPC_EXCP_APU); | |
7170 | return; | |
7171 | } | |
7172 | ||
7173 | t0 = tcg_temp_new_i64(); | |
7174 | t1 = tcg_temp_new_i64(); | |
7175 | ||
7176 | /* t0 := rA; t1 := rB */ | |
7177 | #if defined(TARGET_PPC64) | |
7178 | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7179 | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7180 | #else | |
7181 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7182 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7183 | #endif | |
7184 | ||
7185 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7186 | ||
7187 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7188 | ||
7189 | tcg_temp_free_i64(t0); | |
7190 | tcg_temp_free_i64(t1); | |
7191 | } | |
7192 | ||
7193 | static inline void gen_evmwumia(DisasContext *ctx) | |
7194 | { | |
7195 | TCGv_i64 tmp; | |
7196 | ||
7197 | if (unlikely(!ctx->spe_enabled)) { | |
7198 | gen_exception(ctx, POWERPC_EXCP_APU); | |
7199 | return; | |
7200 | } | |
7201 | ||
7202 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7203 | ||
7204 | tmp = tcg_temp_new_i64(); | |
7205 | ||
7206 | /* acc := rD */ | |
7207 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7208 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); | |
7209 | tcg_temp_free_i64(tmp); | |
7210 | } | |
7211 | ||
7212 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
7213 | { | |
7214 | TCGv_i64 acc; | |
7215 | TCGv_i64 tmp; | |
7216 | ||
7217 | if (unlikely(!ctx->spe_enabled)) { | |
7218 | gen_exception(ctx, POWERPC_EXCP_APU); | |
7219 | return; | |
7220 | } | |
7221 | ||
7222 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7223 | ||
7224 | acc = tcg_temp_new_i64(); | |
7225 | tmp = tcg_temp_new_i64(); | |
7226 | ||
7227 | /* tmp := rD */ | |
7228 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7229 | ||
7230 | /* Load acc */ | |
7231 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); | |
7232 | ||
7233 | /* acc := tmp + acc */ | |
7234 | tcg_gen_add_i64(acc, acc, tmp); | |
7235 | ||
7236 | /* Store acc */ | |
7237 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); | |
7238 | ||
7239 | /* rD := acc */ | |
7240 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7241 | ||
7242 | tcg_temp_free_i64(acc); | |
7243 | tcg_temp_free_i64(tmp); | |
7244 | } | |
7245 | ||
7246 | static inline void gen_evmwsmi(DisasContext *ctx) | |
7247 | { | |
7248 | TCGv_i64 t0, t1; | |
7249 | ||
7250 | if (unlikely(!ctx->spe_enabled)) { | |
7251 | gen_exception(ctx, POWERPC_EXCP_APU); | |
7252 | return; | |
7253 | } | |
7254 | ||
7255 | t0 = tcg_temp_new_i64(); | |
7256 | t1 = tcg_temp_new_i64(); | |
7257 | ||
7258 | /* t0 := rA; t1 := rB */ | |
7259 | #if defined(TARGET_PPC64) | |
7260 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7261 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7262 | #else | |
7263 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7264 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7265 | #endif | |
7266 | ||
7267 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7268 | ||
7269 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7270 | ||
7271 | tcg_temp_free_i64(t0); | |
7272 | tcg_temp_free_i64(t1); | |
7273 | } | |
7274 | ||
7275 | static inline void gen_evmwsmia(DisasContext *ctx) | |
7276 | { | |
7277 | TCGv_i64 tmp; | |
7278 | ||
7279 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7280 | ||
7281 | tmp = tcg_temp_new_i64(); | |
7282 | ||
7283 | /* acc := rD */ | |
7284 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7285 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); | |
7286 | ||
7287 | tcg_temp_free_i64(tmp); | |
7288 | } | |
7289 | ||
7290 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
7291 | { | |
7292 | TCGv_i64 acc = tcg_temp_new_i64(); | |
7293 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
7294 | ||
7295 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7296 | ||
7297 | acc = tcg_temp_new_i64(); | |
7298 | tmp = tcg_temp_new_i64(); | |
7299 | ||
7300 | /* tmp := rD */ | |
7301 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7302 | ||
7303 | /* Load acc */ | |
7304 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); | |
7305 | ||
7306 | /* acc := tmp + acc */ | |
7307 | tcg_gen_add_i64(acc, acc, tmp); | |
7308 | ||
7309 | /* Store acc */ | |
7310 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); | |
7311 | ||
7312 | /* rD := acc */ | |
7313 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7314 | ||
7315 | tcg_temp_free_i64(acc); | |
7316 | tcg_temp_free_i64(tmp); | |
7317 | } | |
7318 | ||
0487d6a8 JM |
7319 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); //// |
7320 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE); | |
7321 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); //// | |
7322 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE); | |
7323 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); //// | |
7324 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); //// | |
7325 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); //// | |
7326 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); // | |
a0e13900 | 7327 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE); |
0487d6a8 JM |
7328 | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); //// |
7329 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); //// | |
7330 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); //// | |
7331 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); //// | |
a0e13900 FC |
7332 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE); |
7333 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE); | |
7334 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
7335 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); //// |
7336 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); //// | |
7337 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); //// | |
7338 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE); | |
7339 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); //// | |
7340 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE); | |
7341 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); // | |
7342 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE); | |
7343 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); //// | |
7344 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); //// | |
7345 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); //// | |
7346 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// | |
7347 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// | |
7348 | ||
6a6ae23f | 7349 | /* SPE load and stores */ |
636aa200 | 7350 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
7351 | { |
7352 | target_ulong uimm = rB(ctx->opcode); | |
7353 | ||
76db3ba4 | 7354 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 7355 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 7356 | } else { |
6a6ae23f | 7357 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
76db3ba4 AJ |
7358 | #if defined(TARGET_PPC64) |
7359 | if (!ctx->sf_mode) { | |
7360 | tcg_gen_ext32u_tl(EA, EA); | |
7361 | } | |
7362 | #endif | |
7363 | } | |
0487d6a8 | 7364 | } |
6a6ae23f | 7365 | |
636aa200 | 7366 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7367 | { |
7368 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7369 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
6a6ae23f AJ |
7370 | #else |
7371 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
76db3ba4 | 7372 | gen_qemu_ld64(ctx, t0, addr); |
6a6ae23f AJ |
7373 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7374 | tcg_gen_shri_i64(t0, t0, 32); | |
7375 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); | |
7376 | tcg_temp_free_i64(t0); | |
7377 | #endif | |
0487d6a8 | 7378 | } |
6a6ae23f | 7379 | |
636aa200 | 7380 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7381 | { |
0487d6a8 | 7382 | #if defined(TARGET_PPC64) |
6a6ae23f | 7383 | TCGv t0 = tcg_temp_new(); |
76db3ba4 | 7384 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f | 7385 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
76db3ba4 AJ |
7386 | gen_addr_add(ctx, addr, addr, 4); |
7387 | gen_qemu_ld32u(ctx, t0, addr); | |
6a6ae23f AJ |
7388 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7389 | tcg_temp_free(t0); | |
7390 | #else | |
76db3ba4 AJ |
7391 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7392 | gen_addr_add(ctx, addr, addr, 4); | |
7393 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f | 7394 | #endif |
0487d6a8 | 7395 | } |
6a6ae23f | 7396 | |
636aa200 | 7397 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7398 | { |
7399 | TCGv t0 = tcg_temp_new(); | |
7400 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7401 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7402 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7403 | gen_addr_add(ctx, addr, addr, 2); |
7404 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7405 | tcg_gen_shli_tl(t0, t0, 32); |
7406 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7407 | gen_addr_add(ctx, addr, addr, 2); |
7408 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7409 | tcg_gen_shli_tl(t0, t0, 16); |
7410 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7411 | gen_addr_add(ctx, addr, addr, 2); |
7412 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7413 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7414 | #else |
76db3ba4 | 7415 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7416 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7417 | gen_addr_add(ctx, addr, addr, 2); |
7418 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7419 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7420 | gen_addr_add(ctx, addr, addr, 2); |
7421 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7422 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7423 | gen_addr_add(ctx, addr, addr, 2); |
7424 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7425 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7426 | #endif |
6a6ae23f | 7427 | tcg_temp_free(t0); |
0487d6a8 JM |
7428 | } |
7429 | ||
636aa200 | 7430 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7431 | { |
7432 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7433 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7434 | #if defined(TARGET_PPC64) |
7435 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
7436 | tcg_gen_shli_tl(t0, t0, 16); | |
7437 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7438 | #else | |
7439 | tcg_gen_shli_tl(t0, t0, 16); | |
7440 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7441 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7442 | #endif | |
7443 | tcg_temp_free(t0); | |
0487d6a8 JM |
7444 | } |
7445 | ||
636aa200 | 7446 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7447 | { |
7448 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7449 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7450 | #if defined(TARGET_PPC64) |
7451 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7452 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7453 | #else | |
7454 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7455 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7456 | #endif | |
7457 | tcg_temp_free(t0); | |
0487d6a8 JM |
7458 | } |
7459 | ||
636aa200 | 7460 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7461 | { |
7462 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7463 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
7464 | #if defined(TARGET_PPC64) |
7465 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7466 | tcg_gen_ext32u_tl(t0, t0); | |
7467 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7468 | #else | |
7469 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7470 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7471 | #endif | |
7472 | tcg_temp_free(t0); | |
7473 | } | |
7474 | ||
636aa200 | 7475 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7476 | { |
7477 | TCGv t0 = tcg_temp_new(); | |
7478 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7479 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7480 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7481 | gen_addr_add(ctx, addr, addr, 2); |
7482 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7483 | tcg_gen_shli_tl(t0, t0, 16); |
7484 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7485 | #else | |
76db3ba4 | 7486 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7487 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7488 | gen_addr_add(ctx, addr, addr, 2); |
7489 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7490 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7491 | #endif | |
7492 | tcg_temp_free(t0); | |
7493 | } | |
7494 | ||
636aa200 | 7495 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7496 | { |
7497 | #if defined(TARGET_PPC64) | |
7498 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 AJ |
7499 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7500 | gen_addr_add(ctx, addr, addr, 2); | |
7501 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7502 | tcg_gen_shli_tl(t0, t0, 32); |
7503 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7504 | tcg_temp_free(t0); | |
7505 | #else | |
76db3ba4 AJ |
7506 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7507 | gen_addr_add(ctx, addr, addr, 2); | |
7508 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7509 | #endif |
7510 | } | |
7511 | ||
636aa200 | 7512 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7513 | { |
7514 | #if defined(TARGET_PPC64) | |
7515 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7516 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f | 7517 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7518 | gen_addr_add(ctx, addr, addr, 2); |
7519 | gen_qemu_ld16s(ctx, t0, addr); | |
6a6ae23f AJ |
7520 | tcg_gen_shli_tl(t0, t0, 32); |
7521 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7522 | tcg_temp_free(t0); | |
7523 | #else | |
76db3ba4 AJ |
7524 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7525 | gen_addr_add(ctx, addr, addr, 2); | |
7526 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7527 | #endif |
7528 | } | |
7529 | ||
636aa200 | 7530 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7531 | { |
7532 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7533 | gen_qemu_ld32u(ctx, t0, addr); |
0487d6a8 | 7534 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7535 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
7536 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7537 | #else | |
7538 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7539 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7540 | #endif | |
7541 | tcg_temp_free(t0); | |
7542 | } | |
7543 | ||
636aa200 | 7544 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7545 | { |
7546 | TCGv t0 = tcg_temp_new(); | |
7547 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7548 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7549 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
7550 | tcg_gen_shli_tl(t0, t0, 32); | |
7551 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7552 | gen_addr_add(ctx, addr, addr, 2); |
7553 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7554 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7555 | tcg_gen_shli_tl(t0, t0, 16); | |
7556 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7557 | #else | |
76db3ba4 | 7558 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7559 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
7560 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7561 | gen_addr_add(ctx, addr, addr, 2); |
7562 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7563 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7564 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
0487d6a8 | 7565 | #endif |
6a6ae23f AJ |
7566 | tcg_temp_free(t0); |
7567 | } | |
7568 | ||
636aa200 | 7569 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7570 | { |
7571 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7572 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
0487d6a8 | 7573 | #else |
6a6ae23f AJ |
7574 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7575 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); | |
76db3ba4 | 7576 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f AJ |
7577 | tcg_temp_free_i64(t0); |
7578 | #endif | |
7579 | } | |
7580 | ||
636aa200 | 7581 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7582 | { |
0487d6a8 | 7583 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7584 | TCGv t0 = tcg_temp_new(); |
7585 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7586 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7587 | tcg_temp_free(t0); |
7588 | #else | |
76db3ba4 | 7589 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7590 | #endif |
76db3ba4 AJ |
7591 | gen_addr_add(ctx, addr, addr, 4); |
7592 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7593 | } |
7594 | ||
636aa200 | 7595 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7596 | { |
7597 | TCGv t0 = tcg_temp_new(); | |
7598 | #if defined(TARGET_PPC64) | |
7599 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7600 | #else | |
7601 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7602 | #endif | |
76db3ba4 AJ |
7603 | gen_qemu_st16(ctx, t0, addr); |
7604 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f AJ |
7605 | #if defined(TARGET_PPC64) |
7606 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7607 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7608 | #else |
76db3ba4 | 7609 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7610 | #endif |
76db3ba4 | 7611 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 7612 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7613 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7614 | tcg_temp_free(t0); |
76db3ba4 AJ |
7615 | gen_addr_add(ctx, addr, addr, 2); |
7616 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7617 | } |
7618 | ||
636aa200 | 7619 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7620 | { |
7621 | TCGv t0 = tcg_temp_new(); | |
7622 | #if defined(TARGET_PPC64) | |
7623 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7624 | #else | |
7625 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7626 | #endif | |
76db3ba4 AJ |
7627 | gen_qemu_st16(ctx, t0, addr); |
7628 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 7629 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7630 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7631 | tcg_temp_free(t0); |
7632 | } | |
7633 | ||
636aa200 | 7634 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7635 | { |
7636 | #if defined(TARGET_PPC64) | |
7637 | TCGv t0 = tcg_temp_new(); | |
7638 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7639 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7640 | tcg_temp_free(t0); |
7641 | #else | |
76db3ba4 | 7642 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7643 | #endif |
76db3ba4 AJ |
7644 | gen_addr_add(ctx, addr, addr, 2); |
7645 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7646 | } |
7647 | ||
636aa200 | 7648 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7649 | { |
7650 | #if defined(TARGET_PPC64) | |
7651 | TCGv t0 = tcg_temp_new(); | |
7652 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7653 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7654 | tcg_temp_free(t0); |
7655 | #else | |
76db3ba4 | 7656 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7657 | #endif |
7658 | } | |
7659 | ||
636aa200 | 7660 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7661 | { |
76db3ba4 | 7662 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7663 | } |
7664 | ||
7665 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 7666 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
7667 | { \ |
7668 | TCGv t0; \ | |
7669 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7670 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6a6ae23f AJ |
7671 | return; \ |
7672 | } \ | |
76db3ba4 | 7673 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
7674 | t0 = tcg_temp_new(); \ |
7675 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 7676 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 7677 | } else { \ |
76db3ba4 | 7678 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
7679 | } \ |
7680 | gen_op_##name(ctx, t0); \ | |
7681 | tcg_temp_free(t0); \ | |
7682 | } | |
7683 | ||
7684 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
7685 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
7686 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
7687 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
7688 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
7689 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
7690 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
7691 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
7692 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
7693 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
7694 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
7695 | ||
7696 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
7697 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
7698 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
7699 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
7700 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
7701 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
7702 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
7703 | |
7704 | /* Multiply and add - TODO */ | |
7705 | #if 0 | |
7706 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE); | |
7707 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE); | |
7708 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE); | |
7709 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE); | |
7710 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE); | |
7711 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE); | |
7712 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE); | |
7713 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE); | |
7714 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE); | |
7715 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE); | |
7716 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE); | |
7717 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE); | |
7718 | ||
7719 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE); | |
7720 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE); | |
7721 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE); | |
7722 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE); | |
7723 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
7724 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE); |
7725 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE); | |
7726 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE); | |
7727 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE); | |
7728 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE); | |
7729 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
7730 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE); |
7731 | ||
7732 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE); | |
7733 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE); | |
7734 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE); | |
7735 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE); | |
7736 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
7737 | |
7738 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE); | |
7739 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE); | |
7740 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE); | |
7741 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE); | |
7742 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE); | |
7743 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE); | |
7744 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE); | |
7745 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE); | |
7746 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE); | |
7747 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE); | |
7748 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE); | |
7749 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE); | |
7750 | ||
7751 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE); | |
7752 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE); | |
7753 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
7754 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE); |
7755 | ||
7756 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE); | |
7757 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE); | |
7758 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE); | |
7759 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE); | |
7760 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE); | |
7761 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE); | |
7762 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE); | |
7763 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE); | |
7764 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE); | |
7765 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE); | |
7766 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE); | |
7767 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE); | |
7768 | ||
7769 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE); | |
7770 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE); | |
7771 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE); | |
7772 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE); | |
7773 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE); | |
7774 | #endif | |
7775 | ||
7776 | /*** SPE floating-point extension ***/ | |
1c97856d AJ |
7777 | #if defined(TARGET_PPC64) |
7778 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 7779 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 7780 | { \ |
1c97856d AJ |
7781 | TCGv_i32 t0; \ |
7782 | TCGv t1; \ | |
7783 | t0 = tcg_temp_new_i32(); \ | |
7784 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
7785 | gen_helper_##name(t0, t0); \ | |
7786 | t1 = tcg_temp_new(); \ | |
7787 | tcg_gen_extu_i32_tl(t1, t0); \ | |
7788 | tcg_temp_free_i32(t0); \ | |
7789 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
7790 | 0xFFFFFFFF00000000ULL); \ | |
7791 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
7792 | tcg_temp_free(t1); \ | |
0487d6a8 | 7793 | } |
1c97856d | 7794 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 7795 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7796 | { \ |
7797 | TCGv_i32 t0; \ | |
7798 | TCGv t1; \ | |
7799 | t0 = tcg_temp_new_i32(); \ | |
7800 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
7801 | t1 = tcg_temp_new(); \ | |
7802 | tcg_gen_extu_i32_tl(t1, t0); \ | |
7803 | tcg_temp_free_i32(t0); \ | |
7804 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
7805 | 0xFFFFFFFF00000000ULL); \ | |
7806 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
7807 | tcg_temp_free(t1); \ | |
7808 | } | |
7809 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 7810 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7811 | { \ |
7812 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
7813 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
7814 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ | |
7815 | tcg_temp_free_i32(t0); \ | |
7816 | } | |
7817 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 7818 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7819 | { \ |
7820 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
7821 | } | |
7822 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 7823 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 7824 | { \ |
1c97856d AJ |
7825 | TCGv_i32 t0, t1; \ |
7826 | TCGv_i64 t2; \ | |
57951c27 | 7827 | if (unlikely(!ctx->spe_enabled)) { \ |
e06fcd75 | 7828 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7829 | return; \ |
7830 | } \ | |
1c97856d AJ |
7831 | t0 = tcg_temp_new_i32(); \ |
7832 | t1 = tcg_temp_new_i32(); \ | |
7833 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
7834 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7835 | gen_helper_##name(t0, t0, t1); \ | |
7836 | tcg_temp_free_i32(t1); \ | |
7837 | t2 = tcg_temp_new(); \ | |
7838 | tcg_gen_extu_i32_tl(t2, t0); \ | |
7839 | tcg_temp_free_i32(t0); \ | |
7840 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
7841 | 0xFFFFFFFF00000000ULL); \ | |
7842 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ | |
7843 | tcg_temp_free(t2); \ | |
57951c27 | 7844 | } |
1c97856d | 7845 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
636aa200 | 7846 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7847 | { \ |
7848 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7849 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7850 | return; \ |
7851 | } \ | |
1c97856d AJ |
7852 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7853 | cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 7854 | } |
1c97856d | 7855 | #define GEN_SPEFPUOP_COMP_32(name) \ |
636aa200 | 7856 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 7857 | { \ |
1c97856d | 7858 | TCGv_i32 t0, t1; \ |
57951c27 | 7859 | if (unlikely(!ctx->spe_enabled)) { \ |
e06fcd75 | 7860 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7861 | return; \ |
7862 | } \ | |
1c97856d AJ |
7863 | t0 = tcg_temp_new_i32(); \ |
7864 | t1 = tcg_temp_new_i32(); \ | |
7865 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
7866 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7867 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ | |
7868 | tcg_temp_free_i32(t0); \ | |
7869 | tcg_temp_free_i32(t1); \ | |
7870 | } | |
7871 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 7872 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7873 | { \ |
7874 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7875 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
7876 | return; \ |
7877 | } \ | |
7878 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
7879 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
7880 | } | |
7881 | #else | |
7882 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 7883 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7884 | { \ |
7885 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 7886 | } |
1c97856d | 7887 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 7888 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7889 | { \ |
7890 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
7891 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
7892 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ | |
7893 | tcg_temp_free_i64(t0); \ | |
7894 | } | |
7895 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 7896 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7897 | { \ |
7898 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
7899 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
7900 | gen_store_gpr64(rD(ctx->opcode), t0); \ | |
7901 | tcg_temp_free_i64(t0); \ | |
7902 | } | |
7903 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 7904 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7905 | { \ |
7906 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
7907 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
7908 | gen_helper_##name(t0, t0); \ | |
7909 | gen_store_gpr64(rD(ctx->opcode), t0); \ | |
7910 | tcg_temp_free_i64(t0); \ | |
7911 | } | |
7912 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 7913 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7914 | { \ |
7915 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7916 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
7917 | return; \ |
7918 | } \ | |
7919 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \ | |
7920 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
7921 | } | |
7922 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 7923 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7924 | { \ |
7925 | TCGv_i64 t0, t1; \ | |
7926 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7927 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
7928 | return; \ |
7929 | } \ | |
7930 | t0 = tcg_temp_new_i64(); \ | |
7931 | t1 = tcg_temp_new_i64(); \ | |
7932 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
7933 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
7934 | gen_helper_##name(t0, t0, t1); \ | |
7935 | gen_store_gpr64(rD(ctx->opcode), t0); \ | |
7936 | tcg_temp_free_i64(t0); \ | |
7937 | tcg_temp_free_i64(t1); \ | |
7938 | } | |
7939 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 7940 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7941 | { \ |
7942 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7943 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
7944 | return; \ |
7945 | } \ | |
7946 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
7947 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
7948 | } | |
7949 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 7950 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
7951 | { \ |
7952 | TCGv_i64 t0, t1; \ | |
7953 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7954 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
7955 | return; \ |
7956 | } \ | |
7957 | t0 = tcg_temp_new_i64(); \ | |
7958 | t1 = tcg_temp_new_i64(); \ | |
7959 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
7960 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
7961 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ | |
7962 | tcg_temp_free_i64(t0); \ | |
7963 | tcg_temp_free_i64(t1); \ | |
7964 | } | |
7965 | #endif | |
57951c27 | 7966 | |
0487d6a8 JM |
7967 | /* Single precision floating-point vectors operations */ |
7968 | /* Arithmetic */ | |
1c97856d AJ |
7969 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
7970 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
7971 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
7972 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 7973 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
7974 | { |
7975 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 7976 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
7977 | return; |
7978 | } | |
7979 | #if defined(TARGET_PPC64) | |
6d5c34fa | 7980 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); |
1c97856d | 7981 | #else |
6d5c34fa MP |
7982 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); |
7983 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
7984 | #endif |
7985 | } | |
636aa200 | 7986 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
7987 | { |
7988 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 7989 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
7990 | return; |
7991 | } | |
7992 | #if defined(TARGET_PPC64) | |
6d5c34fa | 7993 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 7994 | #else |
6d5c34fa MP |
7995 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
7996 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
7997 | #endif |
7998 | } | |
636aa200 | 7999 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
8000 | { |
8001 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8002 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8003 | return; |
8004 | } | |
8005 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8006 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8007 | #else |
6d5c34fa MP |
8008 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8009 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8010 | #endif |
8011 | } | |
8012 | ||
0487d6a8 | 8013 | /* Conversion */ |
1c97856d AJ |
8014 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8015 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
8016 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
8017 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
8018 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
8019 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
8020 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
8021 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
8022 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
8023 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
8024 | ||
0487d6a8 | 8025 | /* Comparison */ |
1c97856d AJ |
8026 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8027 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
8028 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
8029 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
8030 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
8031 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
8032 | |
8033 | /* Opcodes definitions */ | |
40569b7e AJ |
8034 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); // |
8035 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // | |
8036 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // | |
8037 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); // | |
8038 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); // | |
8039 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); // | |
8040 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8041 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8042 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8043 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8044 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8045 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8046 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); // | |
8047 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8048 | |
8049 | /* Single precision floating-point operations */ | |
8050 | /* Arithmetic */ | |
1c97856d AJ |
8051 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8052 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
8053 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
8054 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 8055 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
8056 | { |
8057 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8058 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8059 | return; |
8060 | } | |
6d5c34fa | 8061 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 8062 | } |
636aa200 | 8063 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
8064 | { |
8065 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8066 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8067 | return; |
8068 | } | |
6d5c34fa | 8069 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 8070 | } |
636aa200 | 8071 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
8072 | { |
8073 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8074 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8075 | return; |
8076 | } | |
6d5c34fa | 8077 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
8078 | } |
8079 | ||
0487d6a8 | 8080 | /* Conversion */ |
1c97856d AJ |
8081 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8082 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
8083 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
8084 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
8085 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
8086 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
8087 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
8088 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
8089 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
8090 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
8091 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
8092 | ||
0487d6a8 | 8093 | /* Comparison */ |
1c97856d AJ |
8094 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
8095 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
8096 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
8097 | GEN_SPEFPUOP_COMP_32(efststgt); | |
8098 | GEN_SPEFPUOP_COMP_32(efststlt); | |
8099 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
8100 | |
8101 | /* Opcodes definitions */ | |
40569b7e AJ |
8102 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); // |
8103 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // | |
8104 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // | |
8105 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); // | |
8106 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); // | |
8107 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); // | |
8108 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8109 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8110 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8111 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8112 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8113 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8114 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); // | |
8115 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8116 | |
8117 | /* Double precision floating-point operations */ | |
8118 | /* Arithmetic */ | |
1c97856d AJ |
8119 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
8120 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
8121 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
8122 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 8123 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
8124 | { |
8125 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8126 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8127 | return; |
8128 | } | |
8129 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8130 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); |
1c97856d | 8131 | #else |
6d5c34fa MP |
8132 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8133 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8134 | #endif |
8135 | } | |
636aa200 | 8136 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
8137 | { |
8138 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8139 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8140 | return; |
8141 | } | |
8142 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8143 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8144 | #else |
6d5c34fa MP |
8145 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8146 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8147 | #endif |
8148 | } | |
636aa200 | 8149 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
8150 | { |
8151 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8152 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8153 | return; |
8154 | } | |
8155 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8156 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8157 | #else |
6d5c34fa MP |
8158 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8159 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8160 | #endif |
8161 | } | |
8162 | ||
0487d6a8 | 8163 | /* Conversion */ |
1c97856d AJ |
8164 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
8165 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
8166 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
8167 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
8168 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
8169 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
8170 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
8171 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
8172 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
8173 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
8174 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
8175 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
8176 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
8177 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
8178 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 8179 | |
0487d6a8 | 8180 | /* Comparison */ |
1c97856d AJ |
8181 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
8182 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
8183 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
8184 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
8185 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
8186 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
8187 | |
8188 | /* Opcodes definitions */ | |
40569b7e AJ |
8189 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // |
8190 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8191 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // | |
8192 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // | |
8193 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // | |
8194 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8195 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // | |
8196 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // | |
8197 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8198 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8199 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8200 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8201 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8202 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8203 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // | |
8204 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // | |
0487d6a8 | 8205 | |
c227f099 | 8206 | static opcode_t opcodes[] = { |
5c55ff99 BS |
8207 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
8208 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
8209 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8210 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
8211 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8212 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), | |
8213 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8214 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8215 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8216 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8217 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
8218 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
8219 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
8220 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
8221 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8222 | #if defined(TARGET_PPC64) | |
8223 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
8224 | #endif | |
8225 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
8226 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
8227 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8228 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8229 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8230 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
8231 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
8232 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
8233 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8234 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8235 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8236 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8237 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), | |
eaabeef2 | 8238 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 8239 | #if defined(TARGET_PPC64) |
eaabeef2 | 8240 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 BS |
8241 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
8242 | #endif | |
8243 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8244 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8245 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8246 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
8247 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
8248 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
8249 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
8250 | #if defined(TARGET_PPC64) | |
8251 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
8252 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
8253 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
8254 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
8255 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
8256 | #endif | |
8257 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
8258 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8259 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8260 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
8261 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
8262 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), | |
8263 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), | |
8264 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
8265 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
8266 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
8267 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT), | |
8268 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT), | |
8269 | #if defined(TARGET_PPC64) | |
8270 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8271 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
8272 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8273 | #endif | |
8274 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8275 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8276 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
8277 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
8278 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
8279 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
8280 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
8281 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
f844c817 | 8282 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
5c55ff99 BS |
8283 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
8284 | #if defined(TARGET_PPC64) | |
f844c817 | 8285 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
5c55ff99 BS |
8286 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
8287 | #endif | |
8288 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
8289 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
8290 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8291 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8292 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
8293 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
8294 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), | |
8295 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
8296 | #if defined(TARGET_PPC64) | |
8297 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
8298 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
8299 | #endif | |
8300 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
8301 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
8302 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8303 | #if defined(TARGET_PPC64) | |
8304 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
8305 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8306 | #endif | |
8307 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
8308 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
8309 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
8310 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
8311 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
8312 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
8313 | #if defined(TARGET_PPC64) | |
8314 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
8315 | #endif | |
8316 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
8317 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), | |
8318 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
8319 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
8320 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
8321 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), | |
8322 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), | |
8323 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ), | |
8324 | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT), | |
8325 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), | |
8326 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
8327 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
8328 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
8329 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
8330 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
8331 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
8332 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
8333 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
8334 | #if defined(TARGET_PPC64) | |
8335 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
8336 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
8337 | PPC_SEGMENT_64B), | |
8338 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
8339 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
8340 | PPC_SEGMENT_64B), | |
efdef95f DG |
8341 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
8342 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
8343 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
8344 | #endif |
8345 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
8346 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
8347 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
8348 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
8349 | #if defined(TARGET_PPC64) | |
8350 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
8351 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
8352 | #endif | |
8353 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
8354 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
8355 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
8356 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
8357 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
8358 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
8359 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
8360 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
8361 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
8362 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
8363 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
8364 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8365 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
8366 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
8367 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
8368 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
8369 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
8370 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
8371 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
8372 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8373 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
8374 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
8375 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
8376 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
8377 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
8378 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
8379 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
8380 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
8381 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
8382 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
8383 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
8384 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
8385 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
8386 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
8387 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
8388 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
8389 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
8390 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
8391 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
8392 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
8393 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
8394 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
8395 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
8396 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
8397 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
8398 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
8399 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
8400 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
8401 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
8402 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8403 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8404 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
8405 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
8406 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8407 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8408 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
8409 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
8410 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
8411 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
8412 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
8413 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
8414 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
8415 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
8416 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
8417 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
8418 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
8419 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
8420 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
8421 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
8422 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
8423 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
8424 | GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE), | |
8425 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), | |
8426 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
8427 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
8428 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
8429 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
8430 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
8431 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
8432 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
8433 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), | |
fbe73008 | 8434 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 BS |
8435 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
8436 | GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE), | |
8437 | GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), | |
8438 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE), | |
8439 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), | |
8440 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
8441 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
8442 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
8443 | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), | |
8444 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), | |
8445 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
8446 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
8447 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
8448 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
8449 | ||
8450 | #undef GEN_INT_ARITH_ADD | |
8451 | #undef GEN_INT_ARITH_ADD_CONST | |
8452 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8453 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
8454 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
8455 | add_ca, compute_ca, compute_ov) \ | |
8456 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
8457 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
8458 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
8459 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
8460 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
8461 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
8462 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
8463 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
8464 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
8465 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
8466 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
8467 | ||
8468 | #undef GEN_INT_ARITH_DIVW | |
8469 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
8470 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
8471 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
8472 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
8473 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
8474 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
8475 | ||
8476 | #if defined(TARGET_PPC64) | |
8477 | #undef GEN_INT_ARITH_DIVD | |
8478 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
8479 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8480 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
8481 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
8482 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
8483 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
8484 | ||
8485 | #undef GEN_INT_ARITH_MUL_HELPER | |
8486 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
8487 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8488 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
8489 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
8490 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
8491 | #endif | |
8492 | ||
8493 | #undef GEN_INT_ARITH_SUBF | |
8494 | #undef GEN_INT_ARITH_SUBF_CONST | |
8495 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8496 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
8497 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
8498 | add_ca, compute_ca, compute_ov) \ | |
8499 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
8500 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
8501 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
8502 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
8503 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
8504 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
8505 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
8506 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
8507 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
8508 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
8509 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
8510 | ||
8511 | #undef GEN_LOGICAL1 | |
8512 | #undef GEN_LOGICAL2 | |
8513 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
8514 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
8515 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
8516 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
8517 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
8518 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
8519 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
8520 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
8521 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
8522 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
8523 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
8524 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
8525 | #if defined(TARGET_PPC64) | |
8526 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
8527 | #endif | |
8528 | ||
8529 | #if defined(TARGET_PPC64) | |
8530 | #undef GEN_PPC64_R2 | |
8531 | #undef GEN_PPC64_R4 | |
8532 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
8533 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8534 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8535 | PPC_64B) | |
8536 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
8537 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8538 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
8539 | PPC_64B), \ | |
8540 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8541 | PPC_64B), \ | |
8542 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
8543 | PPC_64B) | |
8544 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
8545 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
8546 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
8547 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
8548 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
8549 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
8550 | #endif | |
8551 | ||
8552 | #undef _GEN_FLOAT_ACB | |
8553 | #undef GEN_FLOAT_ACB | |
8554 | #undef _GEN_FLOAT_AB | |
8555 | #undef GEN_FLOAT_AB | |
8556 | #undef _GEN_FLOAT_AC | |
8557 | #undef GEN_FLOAT_AC | |
8558 | #undef GEN_FLOAT_B | |
8559 | #undef GEN_FLOAT_BS | |
8560 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
8561 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
8562 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
8563 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
8564 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
8565 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8566 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8567 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
8568 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8569 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8570 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8571 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8572 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
8573 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8574 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8575 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
8576 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
8577 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
8578 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
8579 | ||
8580 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
8581 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
8582 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
8583 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
8584 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
8585 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
8586 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
8587 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
8588 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
8589 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
8590 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
8591 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
8592 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), | |
8593 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), | |
8594 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), | |
8595 | #if defined(TARGET_PPC64) | |
8596 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), | |
8597 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), | |
8598 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), | |
8599 | #endif | |
8600 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), | |
8601 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
8602 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
8603 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
8604 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT), | |
8605 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT), | |
8606 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT), | |
8607 | ||
8608 | #undef GEN_LD | |
8609 | #undef GEN_LDU | |
8610 | #undef GEN_LDUX | |
8611 | #undef GEN_LDX | |
8612 | #undef GEN_LDS | |
8613 | #define GEN_LD(name, ldop, opc, type) \ | |
8614 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8615 | #define GEN_LDU(name, ldop, opc, type) \ | |
8616 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8617 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
8618 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
8619 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ | |
8620 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
8621 | #define GEN_LDS(name, ldop, op, type) \ | |
8622 | GEN_LD(name, ldop, op | 0x20, type) \ | |
8623 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
8624 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
8625 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
8626 | ||
8627 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
8628 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
8629 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
8630 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
8631 | #if defined(TARGET_PPC64) | |
8632 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
8633 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
8634 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
8635 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
8636 | #endif | |
8637 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
8638 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
8639 | ||
8640 | #undef GEN_ST | |
8641 | #undef GEN_STU | |
8642 | #undef GEN_STUX | |
8643 | #undef GEN_STX | |
8644 | #undef GEN_STS | |
8645 | #define GEN_ST(name, stop, opc, type) \ | |
8646 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8647 | #define GEN_STU(name, stop, opc, type) \ | |
8648 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8649 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
8650 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
8651 | #define GEN_STX(name, stop, opc2, opc3, type) \ | |
8652 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
8653 | #define GEN_STS(name, stop, op, type) \ | |
8654 | GEN_ST(name, stop, op | 0x20, type) \ | |
8655 | GEN_STU(name, stop, op | 0x21, type) \ | |
8656 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
8657 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
8658 | ||
8659 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
8660 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
8661 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
8662 | #if defined(TARGET_PPC64) | |
8663 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
8664 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
8665 | #endif | |
8666 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
8667 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
8668 | ||
8669 | #undef GEN_LDF | |
8670 | #undef GEN_LDUF | |
8671 | #undef GEN_LDUXF | |
8672 | #undef GEN_LDXF | |
8673 | #undef GEN_LDFS | |
8674 | #define GEN_LDF(name, ldop, opc, type) \ | |
8675 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8676 | #define GEN_LDUF(name, ldop, opc, type) \ | |
8677 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8678 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
8679 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
8680 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
8681 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
8682 | #define GEN_LDFS(name, ldop, op, type) \ | |
8683 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
8684 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
8685 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
8686 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
8687 | ||
8688 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
8689 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
8690 | ||
8691 | #undef GEN_STF | |
8692 | #undef GEN_STUF | |
8693 | #undef GEN_STUXF | |
8694 | #undef GEN_STXF | |
8695 | #undef GEN_STFS | |
8696 | #define GEN_STF(name, stop, opc, type) \ | |
8697 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8698 | #define GEN_STUF(name, stop, opc, type) \ | |
8699 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8700 | #define GEN_STUXF(name, stop, opc, type) \ | |
8701 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
8702 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
8703 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
8704 | #define GEN_STFS(name, stop, op, type) \ | |
8705 | GEN_STF(name, stop, op | 0x20, type) \ | |
8706 | GEN_STUF(name, stop, op | 0x21, type) \ | |
8707 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
8708 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
8709 | ||
8710 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
8711 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
8712 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
8713 | ||
8714 | #undef GEN_CRLOGIC | |
8715 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
8716 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
8717 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
8718 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
8719 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
8720 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
8721 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
8722 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
8723 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
8724 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
8725 | ||
8726 | #undef GEN_MAC_HANDLER | |
8727 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
8728 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
8729 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
8730 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
8731 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
8732 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
8733 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
8734 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
8735 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
8736 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
8737 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
8738 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
8739 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
8740 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
8741 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
8742 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
8743 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
8744 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
8745 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
8746 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
8747 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
8748 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
8749 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
8750 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
8751 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
8752 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
8753 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
8754 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
8755 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
8756 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
8757 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
8758 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
8759 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
8760 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
8761 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
8762 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
8763 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
8764 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
8765 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
8766 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
8767 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
8768 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
8769 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
8770 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
8771 | ||
8772 | #undef GEN_VR_LDX | |
8773 | #undef GEN_VR_STX | |
8774 | #undef GEN_VR_LVE | |
8775 | #undef GEN_VR_STVE | |
8776 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
8777 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
8778 | #define GEN_VR_STX(name, opc2, opc3) \ | |
8779 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
8780 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
8781 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
8782 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
8783 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
8784 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
8785 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
8786 | GEN_VR_LVE(bx, 0x07, 0x00), | |
8787 | GEN_VR_LVE(hx, 0x07, 0x01), | |
8788 | GEN_VR_LVE(wx, 0x07, 0x02), | |
8789 | GEN_VR_STX(svx, 0x07, 0x07), | |
8790 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
8791 | GEN_VR_STVE(bx, 0x07, 0x04), | |
8792 | GEN_VR_STVE(hx, 0x07, 0x05), | |
8793 | GEN_VR_STVE(wx, 0x07, 0x06), | |
8794 | ||
8795 | #undef GEN_VX_LOGICAL | |
8796 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
8797 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
8798 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), | |
8799 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
8800 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
8801 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
8802 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
8803 | ||
8804 | #undef GEN_VXFORM | |
8805 | #define GEN_VXFORM(name, opc2, opc3) \ | |
8806 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
8807 | GEN_VXFORM(vaddubm, 0, 0), | |
8808 | GEN_VXFORM(vadduhm, 0, 1), | |
8809 | GEN_VXFORM(vadduwm, 0, 2), | |
8810 | GEN_VXFORM(vsububm, 0, 16), | |
8811 | GEN_VXFORM(vsubuhm, 0, 17), | |
8812 | GEN_VXFORM(vsubuwm, 0, 18), | |
8813 | GEN_VXFORM(vmaxub, 1, 0), | |
8814 | GEN_VXFORM(vmaxuh, 1, 1), | |
8815 | GEN_VXFORM(vmaxuw, 1, 2), | |
8816 | GEN_VXFORM(vmaxsb, 1, 4), | |
8817 | GEN_VXFORM(vmaxsh, 1, 5), | |
8818 | GEN_VXFORM(vmaxsw, 1, 6), | |
8819 | GEN_VXFORM(vminub, 1, 8), | |
8820 | GEN_VXFORM(vminuh, 1, 9), | |
8821 | GEN_VXFORM(vminuw, 1, 10), | |
8822 | GEN_VXFORM(vminsb, 1, 12), | |
8823 | GEN_VXFORM(vminsh, 1, 13), | |
8824 | GEN_VXFORM(vminsw, 1, 14), | |
8825 | GEN_VXFORM(vavgub, 1, 16), | |
8826 | GEN_VXFORM(vavguh, 1, 17), | |
8827 | GEN_VXFORM(vavguw, 1, 18), | |
8828 | GEN_VXFORM(vavgsb, 1, 20), | |
8829 | GEN_VXFORM(vavgsh, 1, 21), | |
8830 | GEN_VXFORM(vavgsw, 1, 22), | |
8831 | GEN_VXFORM(vmrghb, 6, 0), | |
8832 | GEN_VXFORM(vmrghh, 6, 1), | |
8833 | GEN_VXFORM(vmrghw, 6, 2), | |
8834 | GEN_VXFORM(vmrglb, 6, 4), | |
8835 | GEN_VXFORM(vmrglh, 6, 5), | |
8836 | GEN_VXFORM(vmrglw, 6, 6), | |
8837 | GEN_VXFORM(vmuloub, 4, 0), | |
8838 | GEN_VXFORM(vmulouh, 4, 1), | |
8839 | GEN_VXFORM(vmulosb, 4, 4), | |
8840 | GEN_VXFORM(vmulosh, 4, 5), | |
8841 | GEN_VXFORM(vmuleub, 4, 8), | |
8842 | GEN_VXFORM(vmuleuh, 4, 9), | |
8843 | GEN_VXFORM(vmulesb, 4, 12), | |
8844 | GEN_VXFORM(vmulesh, 4, 13), | |
8845 | GEN_VXFORM(vslb, 2, 4), | |
8846 | GEN_VXFORM(vslh, 2, 5), | |
8847 | GEN_VXFORM(vslw, 2, 6), | |
8848 | GEN_VXFORM(vsrb, 2, 8), | |
8849 | GEN_VXFORM(vsrh, 2, 9), | |
8850 | GEN_VXFORM(vsrw, 2, 10), | |
8851 | GEN_VXFORM(vsrab, 2, 12), | |
8852 | GEN_VXFORM(vsrah, 2, 13), | |
8853 | GEN_VXFORM(vsraw, 2, 14), | |
8854 | GEN_VXFORM(vslo, 6, 16), | |
8855 | GEN_VXFORM(vsro, 6, 17), | |
8856 | GEN_VXFORM(vaddcuw, 0, 6), | |
8857 | GEN_VXFORM(vsubcuw, 0, 22), | |
8858 | GEN_VXFORM(vaddubs, 0, 8), | |
8859 | GEN_VXFORM(vadduhs, 0, 9), | |
8860 | GEN_VXFORM(vadduws, 0, 10), | |
8861 | GEN_VXFORM(vaddsbs, 0, 12), | |
8862 | GEN_VXFORM(vaddshs, 0, 13), | |
8863 | GEN_VXFORM(vaddsws, 0, 14), | |
8864 | GEN_VXFORM(vsububs, 0, 24), | |
8865 | GEN_VXFORM(vsubuhs, 0, 25), | |
8866 | GEN_VXFORM(vsubuws, 0, 26), | |
8867 | GEN_VXFORM(vsubsbs, 0, 28), | |
8868 | GEN_VXFORM(vsubshs, 0, 29), | |
8869 | GEN_VXFORM(vsubsws, 0, 30), | |
8870 | GEN_VXFORM(vrlb, 2, 0), | |
8871 | GEN_VXFORM(vrlh, 2, 1), | |
8872 | GEN_VXFORM(vrlw, 2, 2), | |
8873 | GEN_VXFORM(vsl, 2, 7), | |
8874 | GEN_VXFORM(vsr, 2, 11), | |
8875 | GEN_VXFORM(vpkuhum, 7, 0), | |
8876 | GEN_VXFORM(vpkuwum, 7, 1), | |
8877 | GEN_VXFORM(vpkuhus, 7, 2), | |
8878 | GEN_VXFORM(vpkuwus, 7, 3), | |
8879 | GEN_VXFORM(vpkshus, 7, 4), | |
8880 | GEN_VXFORM(vpkswus, 7, 5), | |
8881 | GEN_VXFORM(vpkshss, 7, 6), | |
8882 | GEN_VXFORM(vpkswss, 7, 7), | |
8883 | GEN_VXFORM(vpkpx, 7, 12), | |
8884 | GEN_VXFORM(vsum4ubs, 4, 24), | |
8885 | GEN_VXFORM(vsum4sbs, 4, 28), | |
8886 | GEN_VXFORM(vsum4shs, 4, 25), | |
8887 | GEN_VXFORM(vsum2sws, 4, 26), | |
8888 | GEN_VXFORM(vsumsws, 4, 30), | |
8889 | GEN_VXFORM(vaddfp, 5, 0), | |
8890 | GEN_VXFORM(vsubfp, 5, 1), | |
8891 | GEN_VXFORM(vmaxfp, 5, 16), | |
8892 | GEN_VXFORM(vminfp, 5, 17), | |
8893 | ||
8894 | #undef GEN_VXRFORM1 | |
8895 | #undef GEN_VXRFORM | |
8896 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
8897 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
8898 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
8899 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
8900 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
8901 | GEN_VXRFORM(vcmpequb, 3, 0) | |
8902 | GEN_VXRFORM(vcmpequh, 3, 1) | |
8903 | GEN_VXRFORM(vcmpequw, 3, 2) | |
8904 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
8905 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
8906 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
8907 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
8908 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
8909 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
8910 | GEN_VXRFORM(vcmpeqfp, 3, 3) | |
8911 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
8912 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
8913 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
8914 | ||
8915 | #undef GEN_VXFORM_SIMM | |
8916 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
8917 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
8918 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
8919 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
8920 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
8921 | ||
8922 | #undef GEN_VXFORM_NOA | |
8923 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
8924 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
8925 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
8926 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
8927 | GEN_VXFORM_NOA(vupklsb, 7, 10), | |
8928 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
8929 | GEN_VXFORM_NOA(vupkhpx, 7, 13), | |
8930 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
8931 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
8932 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 8933 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 BS |
8934 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
8935 | GEN_VXFORM_NOA(vrfim, 5, 8), | |
8936 | GEN_VXFORM_NOA(vrfin, 5, 9), | |
8937 | GEN_VXFORM_NOA(vrfip, 5, 10), | |
8938 | GEN_VXFORM_NOA(vrfiz, 5, 11), | |
8939 | ||
8940 | #undef GEN_VXFORM_UIMM | |
8941 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
8942 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
8943 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
8944 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
8945 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
8946 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
8947 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
8948 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
8949 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
8950 | ||
8951 | #undef GEN_VAFORM_PAIRED | |
8952 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
8953 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
8954 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
8955 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
8956 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
8957 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
8958 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
8959 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
8960 | ||
8961 | #undef GEN_SPE | |
8962 | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \ | |
8963 | GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) | |
8964 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE), | |
8965 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE), | |
8966 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE), | |
8967 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE), | |
8968 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE), | |
8969 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE), | |
8970 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE), | |
8971 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE), | |
a0e13900 | 8972 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE), |
5c55ff99 BS |
8973 | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE), |
8974 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE), | |
8975 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE), | |
8976 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE), | |
a0e13900 FC |
8977 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE), |
8978 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE), | |
8979 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE), | |
5c55ff99 BS |
8980 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE), |
8981 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE), | |
8982 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE), | |
8983 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE), | |
8984 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE), | |
8985 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE), | |
8986 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE), | |
8987 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE), | |
8988 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE), | |
8989 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE), | |
8990 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE), | |
8991 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE), | |
8992 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE), | |
8993 | ||
8994 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE), | |
8995 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE), | |
8996 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE), | |
8997 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE), | |
8998 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE), | |
8999 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE), | |
9000 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE), | |
9001 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE), | |
9002 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE), | |
9003 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE), | |
9004 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE), | |
9005 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE), | |
9006 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE), | |
9007 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE), | |
9008 | ||
9009 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE), | |
9010 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE), | |
9011 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE), | |
9012 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE), | |
9013 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE), | |
9014 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE), | |
9015 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE), | |
9016 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE), | |
9017 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE), | |
9018 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE), | |
9019 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE), | |
9020 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE), | |
9021 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE), | |
9022 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE), | |
9023 | ||
9024 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE), | |
9025 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE), | |
9026 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE), | |
9027 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE), | |
9028 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE), | |
9029 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE), | |
9030 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE), | |
9031 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE), | |
9032 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE), | |
9033 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE), | |
9034 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE), | |
9035 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE), | |
9036 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE), | |
9037 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE), | |
9038 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE), | |
9039 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE), | |
9040 | ||
9041 | #undef GEN_SPEOP_LDST | |
9042 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
9043 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
9044 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
9045 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
9046 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
9047 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
9048 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
9049 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
9050 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
9051 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
9052 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
9053 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
9054 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
9055 | ||
9056 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
9057 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
9058 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
9059 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
9060 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
9061 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
9062 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
9063 | }; | |
9064 | ||
3fc6c082 | 9065 | #include "translate_init.c" |
0411a972 | 9066 | #include "helper_regs.h" |
79aceca5 | 9067 | |
9a64fbe4 | 9068 | /*****************************************************************************/ |
3fc6c082 | 9069 | /* Misc PowerPC helpers */ |
9a78eead | 9070 | void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf, |
36081602 | 9071 | int flags) |
79aceca5 | 9072 | { |
3fc6c082 FB |
9073 | #define RGPL 4 |
9074 | #define RFPL 4 | |
3fc6c082 | 9075 | |
79aceca5 FB |
9076 | int i; |
9077 | ||
90e189ec | 9078 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9a78eead SW |
9079 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
9080 | env->nip, env->lr, env->ctr, env->xer); | |
90e189ec BS |
9081 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9082 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
9083 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 9084 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 9085 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 9086 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 9087 | " DECR %08" PRIu32 |
76a66253 JM |
9088 | #endif |
9089 | "\n", | |
077fc206 | 9090 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
9091 | #if !defined(CONFIG_USER_ONLY) |
9092 | , cpu_ppc_load_decr(env) | |
9093 | #endif | |
9094 | ); | |
077fc206 | 9095 | #endif |
76a66253 | 9096 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
9097 | if ((i & (RGPL - 1)) == 0) |
9098 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 9099 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 9100 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 9101 | cpu_fprintf(f, "\n"); |
76a66253 | 9102 | } |
3fc6c082 | 9103 | cpu_fprintf(f, "CR "); |
76a66253 | 9104 | for (i = 0; i < 8; i++) |
7fe48483 FB |
9105 | cpu_fprintf(f, "%01x", env->crf[i]); |
9106 | cpu_fprintf(f, " ["); | |
76a66253 JM |
9107 | for (i = 0; i < 8; i++) { |
9108 | char a = '-'; | |
9109 | if (env->crf[i] & 0x08) | |
9110 | a = 'L'; | |
9111 | else if (env->crf[i] & 0x04) | |
9112 | a = 'G'; | |
9113 | else if (env->crf[i] & 0x02) | |
9114 | a = 'E'; | |
7fe48483 | 9115 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 9116 | } |
90e189ec BS |
9117 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
9118 | env->reserve_addr); | |
3fc6c082 FB |
9119 | for (i = 0; i < 32; i++) { |
9120 | if ((i & (RFPL - 1)) == 0) | |
9121 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 9122 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 9123 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 9124 | cpu_fprintf(f, "\n"); |
79aceca5 | 9125 | } |
7889270a | 9126 | cpu_fprintf(f, "FPSCR %08x\n", env->fpscr); |
f2e63a42 | 9127 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
9128 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
9129 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
9130 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
9131 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
9132 | ||
9133 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
9134 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
9135 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
9136 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
9137 | ||
9138 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
9139 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
9140 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
9141 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
9142 | ||
9143 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
9144 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
9145 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
9146 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
9147 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
9148 | ||
9149 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
9150 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
9151 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
9152 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
9153 | ||
9154 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
9155 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
9156 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
9157 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
9158 | ||
9159 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
9160 | " EPR " TARGET_FMT_lx "\n", | |
9161 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
9162 | env->spr[SPR_BOOKE_EPR]); | |
9163 | ||
9164 | /* FSL-specific */ | |
9165 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
9166 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
9167 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
9168 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
9169 | ||
9170 | /* | |
9171 | * IVORs are left out as they are large and do not change often -- | |
9172 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
9173 | */ | |
9174 | } | |
9175 | ||
9176 | switch (env->mmu_model) { | |
9177 | case POWERPC_MMU_32B: | |
9178 | case POWERPC_MMU_601: | |
9179 | case POWERPC_MMU_SOFT_6xx: | |
9180 | case POWERPC_MMU_SOFT_74xx: | |
9181 | #if defined(TARGET_PPC64) | |
9182 | case POWERPC_MMU_620: | |
9183 | case POWERPC_MMU_64B: | |
9184 | #endif | |
9185 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); | |
9186 | break; | |
9187 | case POWERPC_MMU_BOOKE_FSL: | |
9188 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx | |
9189 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
9190 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
9191 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
9192 | ||
9193 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
9194 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
9195 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
9196 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
9197 | ||
9198 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
9199 | " TLB1CFG " TARGET_FMT_lx "\n", | |
9200 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
9201 | env->spr[SPR_BOOKE_TLB1CFG]); | |
9202 | break; | |
9203 | default: | |
9204 | break; | |
9205 | } | |
f2e63a42 | 9206 | #endif |
79aceca5 | 9207 | |
3fc6c082 FB |
9208 | #undef RGPL |
9209 | #undef RFPL | |
79aceca5 FB |
9210 | } |
9211 | ||
9a78eead | 9212 | void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf, |
76a66253 JM |
9213 | int flags) |
9214 | { | |
9215 | #if defined(DO_PPC_STATISTICS) | |
c227f099 | 9216 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
9217 | int op1, op2, op3; |
9218 | ||
9219 | t1 = env->opcodes; | |
9220 | for (op1 = 0; op1 < 64; op1++) { | |
9221 | handler = t1[op1]; | |
9222 | if (is_indirect_opcode(handler)) { | |
9223 | t2 = ind_table(handler); | |
9224 | for (op2 = 0; op2 < 32; op2++) { | |
9225 | handler = t2[op2]; | |
9226 | if (is_indirect_opcode(handler)) { | |
9227 | t3 = ind_table(handler); | |
9228 | for (op3 = 0; op3 < 32; op3++) { | |
9229 | handler = t3[op3]; | |
9230 | if (handler->count == 0) | |
9231 | continue; | |
9232 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9233 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9234 | op1, op2, op3, op1, (op3 << 5) | op2, |
9235 | handler->oname, | |
9236 | handler->count, handler->count); | |
9237 | } | |
9238 | } else { | |
9239 | if (handler->count == 0) | |
9240 | continue; | |
9241 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9242 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9243 | op1, op2, op1, op2, handler->oname, |
9244 | handler->count, handler->count); | |
9245 | } | |
9246 | } | |
9247 | } else { | |
9248 | if (handler->count == 0) | |
9249 | continue; | |
0bfcd599 BS |
9250 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
9251 | " %" PRId64 "\n", | |
76a66253 JM |
9252 | op1, op1, handler->oname, |
9253 | handler->count, handler->count); | |
9254 | } | |
9255 | } | |
9256 | #endif | |
9257 | } | |
9258 | ||
9a64fbe4 | 9259 | /*****************************************************************************/ |
636aa200 BS |
9260 | static inline void gen_intermediate_code_internal(CPUState *env, |
9261 | TranslationBlock *tb, | |
9262 | int search_pc) | |
79aceca5 | 9263 | { |
9fddaa0c | 9264 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 9265 | opc_handler_t **table, *handler; |
0fa85d43 | 9266 | target_ulong pc_start; |
79aceca5 | 9267 | uint16_t *gen_opc_end; |
a1d1bb31 | 9268 | CPUBreakpoint *bp; |
79aceca5 | 9269 | int j, lj = -1; |
2e70f6ef PB |
9270 | int num_insns; |
9271 | int max_insns; | |
79aceca5 FB |
9272 | |
9273 | pc_start = tb->pc; | |
79aceca5 | 9274 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 9275 | ctx.nip = pc_start; |
79aceca5 | 9276 | ctx.tb = tb; |
e1833e1f | 9277 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 9278 | ctx.spr_cb = env->spr_cb; |
76db3ba4 AJ |
9279 | ctx.mem_idx = env->mmu_idx; |
9280 | ctx.access_type = -1; | |
9281 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
d9bce9d9 JM |
9282 | #if defined(TARGET_PPC64) |
9283 | ctx.sf_mode = msr_sf; | |
9a64fbe4 | 9284 | #endif |
3cc62370 | 9285 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 9286 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
9287 | ctx.spe_enabled = msr_spe; |
9288 | else | |
9289 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
9290 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
9291 | ctx.altivec_enabled = msr_vr; | |
9292 | else | |
9293 | ctx.altivec_enabled = 0; | |
d26bfc9a | 9294 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 9295 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 9296 | else |
8cbcb4fa | 9297 | ctx.singlestep_enabled = 0; |
d26bfc9a | 9298 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa AJ |
9299 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
9300 | if (unlikely(env->singlestep_enabled)) | |
9301 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
3fc6c082 | 9302 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
9303 | /* Single step trace mode */ |
9304 | msr_se = 1; | |
9305 | #endif | |
2e70f6ef PB |
9306 | num_insns = 0; |
9307 | max_insns = tb->cflags & CF_COUNT_MASK; | |
9308 | if (max_insns == 0) | |
9309 | max_insns = CF_COUNT_MASK; | |
9310 | ||
9311 | gen_icount_start(); | |
9a64fbe4 | 9312 | /* Set env in case of segfault during code fetch */ |
e1833e1f | 9313 | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) { |
72cf2d4f BS |
9314 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
9315 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 9316 | if (bp->pc == ctx.nip) { |
e06fcd75 | 9317 | gen_debug_exception(ctxp); |
ea4e754f FB |
9318 | break; |
9319 | } | |
9320 | } | |
9321 | } | |
76a66253 | 9322 | if (unlikely(search_pc)) { |
79aceca5 FB |
9323 | j = gen_opc_ptr - gen_opc_buf; |
9324 | if (lj < j) { | |
9325 | lj++; | |
9326 | while (lj < j) | |
9327 | gen_opc_instr_start[lj++] = 0; | |
79aceca5 | 9328 | } |
af4b6c54 AJ |
9329 | gen_opc_pc[lj] = ctx.nip; |
9330 | gen_opc_instr_start[lj] = 1; | |
9331 | gen_opc_icount[lj] = num_insns; | |
79aceca5 | 9332 | } |
d12d51d5 | 9333 | LOG_DISAS("----------------\n"); |
90e189ec | 9334 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 9335 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
2e70f6ef PB |
9336 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9337 | gen_io_start(); | |
76db3ba4 | 9338 | if (unlikely(ctx.le_mode)) { |
056401ea JM |
9339 | ctx.opcode = bswap32(ldl_code(ctx.nip)); |
9340 | } else { | |
9341 | ctx.opcode = ldl_code(ctx.nip); | |
111bfab3 | 9342 | } |
d12d51d5 | 9343 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 9344 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
056401ea | 9345 | opc3(ctx.opcode), little_endian ? "little" : "big"); |
731c54f8 AJ |
9346 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) |
9347 | tcg_gen_debug_insn_start(ctx.nip); | |
046d6672 | 9348 | ctx.nip += 4; |
3fc6c082 | 9349 | table = env->opcodes; |
2e70f6ef | 9350 | num_insns++; |
79aceca5 FB |
9351 | handler = table[opc1(ctx.opcode)]; |
9352 | if (is_indirect_opcode(handler)) { | |
9353 | table = ind_table(handler); | |
9354 | handler = table[opc2(ctx.opcode)]; | |
9355 | if (is_indirect_opcode(handler)) { | |
9356 | table = ind_table(handler); | |
9357 | handler = table[opc3(ctx.opcode)]; | |
9358 | } | |
9359 | } | |
9360 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 9361 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
9362 | if (qemu_log_enabled()) { |
9363 | qemu_log("invalid/unsupported opcode: " | |
90e189ec BS |
9364 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
9365 | opc1(ctx.opcode), opc2(ctx.opcode), | |
9366 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa | 9367 | } |
76a66253 JM |
9368 | } else { |
9369 | if (unlikely((ctx.opcode & handler->inval) != 0)) { | |
93fcfe39 AL |
9370 | if (qemu_log_enabled()) { |
9371 | qemu_log("invalid bits: %08x for opcode: " | |
90e189ec BS |
9372 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
9373 | ctx.opcode & handler->inval, opc1(ctx.opcode), | |
9374 | opc2(ctx.opcode), opc3(ctx.opcode), | |
9375 | ctx.opcode, ctx.nip - 4); | |
76a66253 | 9376 | } |
e06fcd75 | 9377 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 9378 | break; |
79aceca5 | 9379 | } |
79aceca5 | 9380 | } |
4b3686fa | 9381 | (*(handler->handler))(&ctx); |
76a66253 JM |
9382 | #if defined(DO_PPC_STATISTICS) |
9383 | handler->count++; | |
9384 | #endif | |
9a64fbe4 | 9385 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
9386 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
9387 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
9388 | ctx.exception != POWERPC_SYSCALL && | |
9389 | ctx.exception != POWERPC_EXCP_TRAP && | |
9390 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 9391 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 9392 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
2e70f6ef | 9393 | (env->singlestep_enabled) || |
1b530a6d | 9394 | singlestep || |
2e70f6ef | 9395 | num_insns >= max_insns)) { |
d26bfc9a JM |
9396 | /* if we reach a page boundary or are single stepping, stop |
9397 | * generation | |
9398 | */ | |
8dd4983c | 9399 | break; |
76a66253 | 9400 | } |
3fc6c082 | 9401 | } |
2e70f6ef PB |
9402 | if (tb->cflags & CF_LAST_IO) |
9403 | gen_io_end(); | |
e1833e1f | 9404 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 9405 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 9406 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
8cbcb4fa | 9407 | if (unlikely(env->singlestep_enabled)) { |
e06fcd75 | 9408 | gen_debug_exception(ctxp); |
8cbcb4fa | 9409 | } |
76a66253 | 9410 | /* Generate the return instruction */ |
57fec1fe | 9411 | tcg_gen_exit_tb(0); |
9a64fbe4 | 9412 | } |
2e70f6ef | 9413 | gen_icount_end(tb, num_insns); |
79aceca5 | 9414 | *gen_opc_ptr = INDEX_op_end; |
76a66253 | 9415 | if (unlikely(search_pc)) { |
9a64fbe4 FB |
9416 | j = gen_opc_ptr - gen_opc_buf; |
9417 | lj++; | |
9418 | while (lj <= j) | |
9419 | gen_opc_instr_start[lj++] = 0; | |
9a64fbe4 | 9420 | } else { |
046d6672 | 9421 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 9422 | tb->icount = num_insns; |
9a64fbe4 | 9423 | } |
d9bce9d9 | 9424 | #if defined(DEBUG_DISAS) |
8fec2b8c | 9425 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 9426 | int flags; |
237c0af0 | 9427 | flags = env->bfd_mach; |
76db3ba4 | 9428 | flags |= ctx.le_mode << 16; |
93fcfe39 AL |
9429 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
9430 | log_target_disas(pc_start, ctx.nip - pc_start, flags); | |
9431 | qemu_log("\n"); | |
9fddaa0c | 9432 | } |
79aceca5 | 9433 | #endif |
79aceca5 FB |
9434 | } |
9435 | ||
2cfc5f17 | 9436 | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
79aceca5 | 9437 | { |
2cfc5f17 | 9438 | gen_intermediate_code_internal(env, tb, 0); |
79aceca5 FB |
9439 | } |
9440 | ||
2cfc5f17 | 9441 | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
79aceca5 | 9442 | { |
2cfc5f17 | 9443 | gen_intermediate_code_internal(env, tb, 1); |
79aceca5 | 9444 | } |
d2856f1a | 9445 | |
e87b7cb0 | 9446 | void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 9447 | { |
d2856f1a | 9448 | env->nip = gen_opc_pc[pc_pos]; |
d2856f1a | 9449 | } |