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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
79aceca5 | 21 | #include "cpu.h" |
79aceca5 | 22 | #include "disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
0cfe11ea | 24 | #include "host-utils.h" |
79aceca5 | 25 | |
a7812ae4 PB |
26 | #include "helper.h" |
27 | #define GEN_HELPER 1 | |
28 | #include "helper.h" | |
29 | ||
8cbcb4fa AJ |
30 | #define CPU_SINGLE_STEP 0x1 |
31 | #define CPU_BRANCH_STEP 0x2 | |
32 | #define GDBSTUB_SINGLE_STEP 0x4 | |
33 | ||
a750fc0b | 34 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 35 | //#define PPC_DEBUG_DISAS |
76a66253 | 36 | //#define DO_PPC_STATISTICS |
79aceca5 | 37 | |
d12d51d5 | 38 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 39 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
40 | #else |
41 | # define LOG_DISAS(...) do { } while (0) | |
42 | #endif | |
a750fc0b JM |
43 | /*****************************************************************************/ |
44 | /* Code translation helpers */ | |
c53be334 | 45 | |
f78fb44e | 46 | /* global register indexes */ |
a7812ae4 | 47 | static TCGv_ptr cpu_env; |
1d542695 | 48 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
f78fb44e | 49 | #if !defined(TARGET_PPC64) |
1d542695 | 50 | + 10*4 + 22*5 /* SPE GPRh */ |
f78fb44e | 51 | #endif |
a5e26afa | 52 | + 10*4 + 22*5 /* FPR */ |
47e4661c AJ |
53 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
54 | + 8*5 /* CRF */]; | |
f78fb44e AJ |
55 | static TCGv cpu_gpr[32]; |
56 | #if !defined(TARGET_PPC64) | |
57 | static TCGv cpu_gprh[32]; | |
58 | #endif | |
a7812ae4 PB |
59 | static TCGv_i64 cpu_fpr[32]; |
60 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
61 | static TCGv_i32 cpu_crf[8]; | |
bd568f18 | 62 | static TCGv cpu_nip; |
6527f6ea | 63 | static TCGv cpu_msr; |
cfdcd37a AJ |
64 | static TCGv cpu_ctr; |
65 | static TCGv cpu_lr; | |
697ab892 DG |
66 | #if defined(TARGET_PPC64) |
67 | static TCGv cpu_cfar; | |
68 | #endif | |
3d7b417e | 69 | static TCGv cpu_xer; |
cf360a32 | 70 | static TCGv cpu_reserve; |
30304420 | 71 | static TCGv cpu_fpscr; |
a7859e89 | 72 | static TCGv_i32 cpu_access_type; |
f78fb44e | 73 | |
2e70f6ef PB |
74 | #include "gen-icount.h" |
75 | ||
76 | void ppc_translate_init(void) | |
77 | { | |
f78fb44e AJ |
78 | int i; |
79 | char* p; | |
2dc766da | 80 | size_t cpu_reg_names_size; |
b2437bf2 | 81 | static int done_init = 0; |
f78fb44e | 82 | |
2e70f6ef PB |
83 | if (done_init) |
84 | return; | |
f78fb44e | 85 | |
a7812ae4 | 86 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 87 | |
f78fb44e | 88 | p = cpu_reg_names; |
2dc766da | 89 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
90 | |
91 | for (i = 0; i < 8; i++) { | |
2dc766da | 92 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 | 93 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 94 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 95 | p += 5; |
2dc766da | 96 | cpu_reg_names_size -= 5; |
47e4661c AJ |
97 | } |
98 | ||
f78fb44e | 99 | for (i = 0; i < 32; i++) { |
2dc766da | 100 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 101 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 102 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 103 | p += (i < 10) ? 3 : 4; |
2dc766da | 104 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
f78fb44e | 105 | #if !defined(TARGET_PPC64) |
2dc766da | 106 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
a7812ae4 | 107 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 108 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 109 | p += (i < 10) ? 4 : 5; |
2dc766da | 110 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 111 | #endif |
1d542695 | 112 | |
2dc766da | 113 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 | 114 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 115 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 116 | p += (i < 10) ? 4 : 5; |
2dc766da | 117 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 118 | |
2dc766da | 119 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 120 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 121 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 122 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 123 | #else |
a7812ae4 | 124 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 125 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 126 | #endif |
1d542695 | 127 | p += (i < 10) ? 6 : 7; |
2dc766da | 128 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 129 | |
2dc766da | 130 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 131 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 132 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 133 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 134 | #else |
a7812ae4 | 135 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 136 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 137 | #endif |
1d542695 | 138 | p += (i < 10) ? 6 : 7; |
2dc766da | 139 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
f78fb44e | 140 | } |
f10dc08e | 141 | |
a7812ae4 | 142 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 143 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 144 | |
6527f6ea | 145 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 146 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 147 | |
a7812ae4 | 148 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 149 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 150 | |
a7812ae4 | 151 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 152 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 153 | |
697ab892 DG |
154 | #if defined(TARGET_PPC64) |
155 | cpu_cfar = tcg_global_mem_new(TCG_AREG0, | |
1328c2bf | 156 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
157 | #endif |
158 | ||
a7812ae4 | 159 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 160 | offsetof(CPUPPCState, xer), "xer"); |
3d7b417e | 161 | |
cf360a32 | 162 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 163 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 164 | "reserve_addr"); |
cf360a32 | 165 | |
30304420 DG |
166 | cpu_fpscr = tcg_global_mem_new(TCG_AREG0, |
167 | offsetof(CPUPPCState, fpscr), "fpscr"); | |
e1571908 | 168 | |
a7859e89 | 169 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 170 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 171 | |
f10dc08e | 172 | /* register helpers */ |
a7812ae4 | 173 | #define GEN_HELPER 2 |
f10dc08e AJ |
174 | #include "helper.h" |
175 | ||
2e70f6ef PB |
176 | done_init = 1; |
177 | } | |
178 | ||
79aceca5 FB |
179 | /* internal defines */ |
180 | typedef struct DisasContext { | |
181 | struct TranslationBlock *tb; | |
0fa85d43 | 182 | target_ulong nip; |
79aceca5 | 183 | uint32_t opcode; |
9a64fbe4 | 184 | uint32_t exception; |
3cc62370 FB |
185 | /* Routine used to access memory */ |
186 | int mem_idx; | |
76db3ba4 | 187 | int access_type; |
3cc62370 | 188 | /* Translation flags */ |
76db3ba4 | 189 | int le_mode; |
d9bce9d9 JM |
190 | #if defined(TARGET_PPC64) |
191 | int sf_mode; | |
697ab892 | 192 | int has_cfar; |
9a64fbe4 | 193 | #endif |
3cc62370 | 194 | int fpu_enabled; |
a9d9eb8f | 195 | int altivec_enabled; |
0487d6a8 | 196 | int spe_enabled; |
c227f099 | 197 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 198 | int singlestep_enabled; |
79aceca5 FB |
199 | } DisasContext; |
200 | ||
c227f099 | 201 | struct opc_handler_t { |
70560da7 FC |
202 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
203 | uint32_t inval1; | |
204 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
205 | uint32_t inval2; | |
9a64fbe4 | 206 | /* instruction type */ |
0487d6a8 | 207 | uint64_t type; |
a5858d7a AG |
208 | /* extended instruction type */ |
209 | uint64_t type2; | |
79aceca5 FB |
210 | /* handler */ |
211 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 212 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 213 | const char *oname; |
a750fc0b JM |
214 | #endif |
215 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
216 | uint64_t count; |
217 | #endif | |
3fc6c082 | 218 | }; |
79aceca5 | 219 | |
636aa200 | 220 | static inline void gen_reset_fpstatus(void) |
7c58044c | 221 | { |
8e703949 | 222 | gen_helper_reset_fpstatus(cpu_env); |
7c58044c JM |
223 | } |
224 | ||
636aa200 | 225 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 226 | { |
0f2f39c2 | 227 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 228 | |
7c58044c JM |
229 | if (set_fprf != 0) { |
230 | /* This case might be optimized later */ | |
0f2f39c2 | 231 | tcg_gen_movi_i32(t0, 1); |
8e703949 | 232 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
a7812ae4 | 233 | if (unlikely(set_rc)) { |
0f2f39c2 | 234 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 235 | } |
8e703949 | 236 | gen_helper_float_check_status(cpu_env); |
7c58044c JM |
237 | } else if (unlikely(set_rc)) { |
238 | /* We always need to compute fpcc */ | |
0f2f39c2 | 239 | tcg_gen_movi_i32(t0, 0); |
8e703949 | 240 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
0f2f39c2 | 241 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 242 | } |
af12906f | 243 | |
0f2f39c2 | 244 | tcg_temp_free_i32(t0); |
7c58044c JM |
245 | } |
246 | ||
636aa200 | 247 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 248 | { |
76db3ba4 AJ |
249 | if (ctx->access_type != access_type) { |
250 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
251 | ctx->access_type = access_type; | |
252 | } | |
a7859e89 AJ |
253 | } |
254 | ||
636aa200 | 255 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 JM |
256 | { |
257 | #if defined(TARGET_PPC64) | |
258 | if (ctx->sf_mode) | |
bd568f18 | 259 | tcg_gen_movi_tl(cpu_nip, nip); |
d9bce9d9 JM |
260 | else |
261 | #endif | |
bd568f18 | 262 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
d9bce9d9 JM |
263 | } |
264 | ||
636aa200 | 265 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
266 | { |
267 | TCGv_i32 t0, t1; | |
268 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
269 | gen_update_nip(ctx, ctx->nip); | |
270 | } | |
271 | t0 = tcg_const_i32(excp); | |
272 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 273 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
274 | tcg_temp_free_i32(t0); |
275 | tcg_temp_free_i32(t1); | |
276 | ctx->exception = (excp); | |
277 | } | |
e1833e1f | 278 | |
636aa200 | 279 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
280 | { |
281 | TCGv_i32 t0; | |
282 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
283 | gen_update_nip(ctx, ctx->nip); | |
284 | } | |
285 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 286 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
287 | tcg_temp_free_i32(t0); |
288 | ctx->exception = (excp); | |
289 | } | |
e1833e1f | 290 | |
636aa200 | 291 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
292 | { |
293 | TCGv_i32 t0; | |
5518f3a6 | 294 | |
ee2b3994 SB |
295 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
296 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
5518f3a6 | 297 | gen_update_nip(ctx, ctx->nip); |
ee2b3994 | 298 | } |
e06fcd75 | 299 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 300 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
301 | tcg_temp_free_i32(t0); |
302 | } | |
9a64fbe4 | 303 | |
636aa200 | 304 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
305 | { |
306 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
307 | } | |
a9d9eb8f | 308 | |
f24e5695 | 309 | /* Stop translation */ |
636aa200 | 310 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 311 | { |
d9bce9d9 | 312 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 313 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
314 | } |
315 | ||
f24e5695 | 316 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 317 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 318 | { |
e1833e1f | 319 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
320 | } |
321 | ||
79aceca5 | 322 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
323 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
324 | ||
325 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
326 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 327 | |
c7697e1f | 328 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
329 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
330 | ||
331 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
332 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 333 | |
c227f099 | 334 | typedef struct opcode_t { |
79aceca5 | 335 | unsigned char opc1, opc2, opc3; |
1235fc06 | 336 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
337 | unsigned char pad[5]; |
338 | #else | |
339 | unsigned char pad[1]; | |
340 | #endif | |
c227f099 | 341 | opc_handler_t handler; |
b55266b5 | 342 | const char *oname; |
c227f099 | 343 | } opcode_t; |
79aceca5 | 344 | |
a750fc0b | 345 | /*****************************************************************************/ |
79aceca5 FB |
346 | /*** Instruction decoding ***/ |
347 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 348 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
349 | { \ |
350 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
351 | } | |
352 | ||
353 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 354 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 355 | { \ |
18fba28c | 356 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
357 | } |
358 | ||
359 | /* Opcode part 1 */ | |
360 | EXTRACT_HELPER(opc1, 26, 6); | |
361 | /* Opcode part 2 */ | |
362 | EXTRACT_HELPER(opc2, 1, 5); | |
363 | /* Opcode part 3 */ | |
364 | EXTRACT_HELPER(opc3, 6, 5); | |
365 | /* Update Cr0 flags */ | |
366 | EXTRACT_HELPER(Rc, 0, 1); | |
367 | /* Destination */ | |
368 | EXTRACT_HELPER(rD, 21, 5); | |
369 | /* Source */ | |
370 | EXTRACT_HELPER(rS, 21, 5); | |
371 | /* First operand */ | |
372 | EXTRACT_HELPER(rA, 16, 5); | |
373 | /* Second operand */ | |
374 | EXTRACT_HELPER(rB, 11, 5); | |
375 | /* Third operand */ | |
376 | EXTRACT_HELPER(rC, 6, 5); | |
377 | /*** Get CRn ***/ | |
378 | EXTRACT_HELPER(crfD, 23, 3); | |
379 | EXTRACT_HELPER(crfS, 18, 3); | |
380 | EXTRACT_HELPER(crbD, 21, 5); | |
381 | EXTRACT_HELPER(crbA, 16, 5); | |
382 | EXTRACT_HELPER(crbB, 11, 5); | |
383 | /* SPR / TBL */ | |
3fc6c082 | 384 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 385 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
386 | { |
387 | uint32_t sprn = _SPR(opcode); | |
388 | ||
389 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
390 | } | |
79aceca5 FB |
391 | /*** Get constants ***/ |
392 | EXTRACT_HELPER(IMM, 12, 8); | |
393 | /* 16 bits signed immediate value */ | |
394 | EXTRACT_SHELPER(SIMM, 0, 16); | |
395 | /* 16 bits unsigned immediate value */ | |
396 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
397 | /* 5 bits signed immediate value */ |
398 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
399 | /* 5 bits signed immediate value */ |
400 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
401 | /* Bit count */ |
402 | EXTRACT_HELPER(NB, 11, 5); | |
403 | /* Shift count */ | |
404 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
405 | /* Vector shift count */ |
406 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
407 | /* Mask start */ |
408 | EXTRACT_HELPER(MB, 6, 5); | |
409 | /* Mask end */ | |
410 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
411 | /* Trap operand */ |
412 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
413 | |
414 | EXTRACT_HELPER(CRM, 12, 8); | |
415 | EXTRACT_HELPER(FM, 17, 8); | |
416 | EXTRACT_HELPER(SR, 16, 4); | |
e4bb997e | 417 | EXTRACT_HELPER(FPIMM, 12, 4); |
fb0eaffc | 418 | |
79aceca5 FB |
419 | /*** Jump target decoding ***/ |
420 | /* Displacement */ | |
421 | EXTRACT_SHELPER(d, 0, 16); | |
422 | /* Immediate address */ | |
636aa200 | 423 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
424 | { |
425 | return (opcode >> 0) & 0x03FFFFFC; | |
426 | } | |
427 | ||
636aa200 | 428 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
429 | { |
430 | return (opcode >> 0) & 0xFFFC; | |
431 | } | |
432 | ||
433 | EXTRACT_HELPER(BO, 21, 5); | |
434 | EXTRACT_HELPER(BI, 16, 5); | |
435 | /* Absolute/relative address */ | |
436 | EXTRACT_HELPER(AA, 1, 1); | |
437 | /* Link */ | |
438 | EXTRACT_HELPER(LK, 0, 1); | |
439 | ||
440 | /* Create a mask between <start> and <end> bits */ | |
636aa200 | 441 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 442 | { |
76a66253 | 443 | target_ulong ret; |
79aceca5 | 444 | |
76a66253 JM |
445 | #if defined(TARGET_PPC64) |
446 | if (likely(start == 0)) { | |
6f2d8978 | 447 | ret = UINT64_MAX << (63 - end); |
76a66253 | 448 | } else if (likely(end == 63)) { |
6f2d8978 | 449 | ret = UINT64_MAX >> start; |
76a66253 JM |
450 | } |
451 | #else | |
452 | if (likely(start == 0)) { | |
6f2d8978 | 453 | ret = UINT32_MAX << (31 - end); |
76a66253 | 454 | } else if (likely(end == 31)) { |
6f2d8978 | 455 | ret = UINT32_MAX >> start; |
76a66253 JM |
456 | } |
457 | #endif | |
458 | else { | |
459 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
460 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
461 | if (unlikely(start > end)) | |
462 | return ~ret; | |
463 | } | |
79aceca5 FB |
464 | |
465 | return ret; | |
466 | } | |
467 | ||
a750fc0b | 468 | /*****************************************************************************/ |
a750fc0b | 469 | /* PowerPC instructions table */ |
933dc6eb | 470 | |
76a66253 | 471 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 472 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 473 | { \ |
79aceca5 FB |
474 | .opc1 = op1, \ |
475 | .opc2 = op2, \ | |
476 | .opc3 = op3, \ | |
18fba28c | 477 | .pad = { 0, }, \ |
79aceca5 | 478 | .handler = { \ |
70560da7 FC |
479 | .inval1 = invl, \ |
480 | .type = _typ, \ | |
481 | .type2 = _typ2, \ | |
482 | .handler = &gen_##name, \ | |
483 | .oname = stringify(name), \ | |
484 | }, \ | |
485 | .oname = stringify(name), \ | |
486 | } | |
487 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
488 | { \ | |
489 | .opc1 = op1, \ | |
490 | .opc2 = op2, \ | |
491 | .opc3 = op3, \ | |
492 | .pad = { 0, }, \ | |
493 | .handler = { \ | |
494 | .inval1 = invl1, \ | |
495 | .inval2 = invl2, \ | |
9a64fbe4 | 496 | .type = _typ, \ |
a5858d7a | 497 | .type2 = _typ2, \ |
79aceca5 | 498 | .handler = &gen_##name, \ |
76a66253 | 499 | .oname = stringify(name), \ |
79aceca5 | 500 | }, \ |
3fc6c082 | 501 | .oname = stringify(name), \ |
79aceca5 | 502 | } |
a5858d7a | 503 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 504 | { \ |
c7697e1f JM |
505 | .opc1 = op1, \ |
506 | .opc2 = op2, \ | |
507 | .opc3 = op3, \ | |
508 | .pad = { 0, }, \ | |
509 | .handler = { \ | |
70560da7 | 510 | .inval1 = invl, \ |
c7697e1f | 511 | .type = _typ, \ |
a5858d7a | 512 | .type2 = _typ2, \ |
c7697e1f JM |
513 | .handler = &gen_##name, \ |
514 | .oname = onam, \ | |
515 | }, \ | |
516 | .oname = onam, \ | |
517 | } | |
76a66253 | 518 | #else |
a5858d7a | 519 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 520 | { \ |
c7697e1f JM |
521 | .opc1 = op1, \ |
522 | .opc2 = op2, \ | |
523 | .opc3 = op3, \ | |
524 | .pad = { 0, }, \ | |
525 | .handler = { \ | |
70560da7 FC |
526 | .inval1 = invl, \ |
527 | .type = _typ, \ | |
528 | .type2 = _typ2, \ | |
529 | .handler = &gen_##name, \ | |
530 | }, \ | |
531 | .oname = stringify(name), \ | |
532 | } | |
533 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
534 | { \ | |
535 | .opc1 = op1, \ | |
536 | .opc2 = op2, \ | |
537 | .opc3 = op3, \ | |
538 | .pad = { 0, }, \ | |
539 | .handler = { \ | |
540 | .inval1 = invl1, \ | |
541 | .inval2 = invl2, \ | |
c7697e1f | 542 | .type = _typ, \ |
a5858d7a | 543 | .type2 = _typ2, \ |
c7697e1f | 544 | .handler = &gen_##name, \ |
5c55ff99 BS |
545 | }, \ |
546 | .oname = stringify(name), \ | |
547 | } | |
a5858d7a | 548 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
549 | { \ |
550 | .opc1 = op1, \ | |
551 | .opc2 = op2, \ | |
552 | .opc3 = op3, \ | |
553 | .pad = { 0, }, \ | |
554 | .handler = { \ | |
70560da7 | 555 | .inval1 = invl, \ |
5c55ff99 | 556 | .type = _typ, \ |
a5858d7a | 557 | .type2 = _typ2, \ |
5c55ff99 BS |
558 | .handler = &gen_##name, \ |
559 | }, \ | |
560 | .oname = onam, \ | |
561 | } | |
562 | #endif | |
2e610050 | 563 | |
5c55ff99 | 564 | /* SPR load/store helpers */ |
636aa200 | 565 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 566 | { |
1328c2bf | 567 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 568 | } |
2e610050 | 569 | |
636aa200 | 570 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 571 | { |
1328c2bf | 572 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 573 | } |
2e610050 | 574 | |
54623277 | 575 | /* Invalid instruction */ |
99e300ef | 576 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 577 | { |
e06fcd75 | 578 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
579 | } |
580 | ||
c227f099 | 581 | static opc_handler_t invalid_handler = { |
70560da7 FC |
582 | .inval1 = 0xFFFFFFFF, |
583 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 584 | .type = PPC_NONE, |
a5858d7a | 585 | .type2 = PPC_NONE, |
79aceca5 FB |
586 | .handler = gen_invalid, |
587 | }; | |
588 | ||
e1571908 AJ |
589 | /*** Integer comparison ***/ |
590 | ||
636aa200 | 591 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 AJ |
592 | { |
593 | int l1, l2, l3; | |
594 | ||
269f3e95 AJ |
595 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer); |
596 | tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO); | |
e1571908 AJ |
597 | tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1); |
598 | ||
599 | l1 = gen_new_label(); | |
600 | l2 = gen_new_label(); | |
601 | l3 = gen_new_label(); | |
602 | if (s) { | |
ea363694 AJ |
603 | tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1); |
604 | tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2); | |
e1571908 | 605 | } else { |
ea363694 AJ |
606 | tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1); |
607 | tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2); | |
e1571908 AJ |
608 | } |
609 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ); | |
610 | tcg_gen_br(l3); | |
611 | gen_set_label(l1); | |
612 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT); | |
613 | tcg_gen_br(l3); | |
614 | gen_set_label(l2); | |
615 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT); | |
616 | gen_set_label(l3); | |
617 | } | |
618 | ||
636aa200 | 619 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 620 | { |
ea363694 AJ |
621 | TCGv t0 = tcg_const_local_tl(arg1); |
622 | gen_op_cmp(arg0, t0, s, crf); | |
623 | tcg_temp_free(t0); | |
e1571908 AJ |
624 | } |
625 | ||
626 | #if defined(TARGET_PPC64) | |
636aa200 | 627 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 628 | { |
ea363694 | 629 | TCGv t0, t1; |
a7812ae4 PB |
630 | t0 = tcg_temp_local_new(); |
631 | t1 = tcg_temp_local_new(); | |
e1571908 | 632 | if (s) { |
ea363694 AJ |
633 | tcg_gen_ext32s_tl(t0, arg0); |
634 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 635 | } else { |
ea363694 AJ |
636 | tcg_gen_ext32u_tl(t0, arg0); |
637 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 638 | } |
ea363694 AJ |
639 | gen_op_cmp(t0, t1, s, crf); |
640 | tcg_temp_free(t1); | |
641 | tcg_temp_free(t0); | |
e1571908 AJ |
642 | } |
643 | ||
636aa200 | 644 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 645 | { |
ea363694 AJ |
646 | TCGv t0 = tcg_const_local_tl(arg1); |
647 | gen_op_cmp32(arg0, t0, s, crf); | |
648 | tcg_temp_free(t0); | |
e1571908 AJ |
649 | } |
650 | #endif | |
651 | ||
636aa200 | 652 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 AJ |
653 | { |
654 | #if defined(TARGET_PPC64) | |
655 | if (!(ctx->sf_mode)) | |
656 | gen_op_cmpi32(reg, 0, 1, 0); | |
657 | else | |
658 | #endif | |
659 | gen_op_cmpi(reg, 0, 1, 0); | |
660 | } | |
661 | ||
662 | /* cmp */ | |
99e300ef | 663 | static void gen_cmp(DisasContext *ctx) |
e1571908 AJ |
664 | { |
665 | #if defined(TARGET_PPC64) | |
666 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
667 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
668 | 1, crfD(ctx->opcode)); | |
669 | else | |
670 | #endif | |
671 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
672 | 1, crfD(ctx->opcode)); | |
673 | } | |
674 | ||
675 | /* cmpi */ | |
99e300ef | 676 | static void gen_cmpi(DisasContext *ctx) |
e1571908 AJ |
677 | { |
678 | #if defined(TARGET_PPC64) | |
679 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
680 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
681 | 1, crfD(ctx->opcode)); | |
682 | else | |
683 | #endif | |
684 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
685 | 1, crfD(ctx->opcode)); | |
686 | } | |
687 | ||
688 | /* cmpl */ | |
99e300ef | 689 | static void gen_cmpl(DisasContext *ctx) |
e1571908 AJ |
690 | { |
691 | #if defined(TARGET_PPC64) | |
692 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
693 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
694 | 0, crfD(ctx->opcode)); | |
695 | else | |
696 | #endif | |
697 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
698 | 0, crfD(ctx->opcode)); | |
699 | } | |
700 | ||
701 | /* cmpli */ | |
99e300ef | 702 | static void gen_cmpli(DisasContext *ctx) |
e1571908 AJ |
703 | { |
704 | #if defined(TARGET_PPC64) | |
705 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
706 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
707 | 0, crfD(ctx->opcode)); | |
708 | else | |
709 | #endif | |
710 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
711 | 0, crfD(ctx->opcode)); | |
712 | } | |
713 | ||
714 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 715 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
716 | { |
717 | int l1, l2; | |
718 | uint32_t bi = rC(ctx->opcode); | |
719 | uint32_t mask; | |
a7812ae4 | 720 | TCGv_i32 t0; |
e1571908 AJ |
721 | |
722 | l1 = gen_new_label(); | |
723 | l2 = gen_new_label(); | |
724 | ||
725 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 726 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
727 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
728 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
729 | if (rA(ctx->opcode) == 0) |
730 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
731 | else | |
732 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
733 | tcg_gen_br(l2); | |
734 | gen_set_label(l1); | |
735 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
736 | gen_set_label(l2); | |
a7812ae4 | 737 | tcg_temp_free_i32(t0); |
e1571908 AJ |
738 | } |
739 | ||
79aceca5 | 740 | /*** Integer arithmetic ***/ |
79aceca5 | 741 | |
636aa200 BS |
742 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
743 | TCGv arg1, TCGv arg2, int sub) | |
74637406 AJ |
744 | { |
745 | int l1; | |
746 | TCGv t0; | |
79aceca5 | 747 | |
74637406 AJ |
748 | l1 = gen_new_label(); |
749 | /* Start with XER OV disabled, the most likely case */ | |
750 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
a7812ae4 | 751 | t0 = tcg_temp_local_new(); |
74637406 AJ |
752 | tcg_gen_xor_tl(t0, arg0, arg1); |
753 | #if defined(TARGET_PPC64) | |
754 | if (!ctx->sf_mode) | |
755 | tcg_gen_ext32s_tl(t0, t0); | |
756 | #endif | |
757 | if (sub) | |
758 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); | |
759 | else | |
760 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
761 | tcg_gen_xor_tl(t0, arg1, arg2); | |
762 | #if defined(TARGET_PPC64) | |
763 | if (!ctx->sf_mode) | |
764 | tcg_gen_ext32s_tl(t0, t0); | |
765 | #endif | |
766 | if (sub) | |
767 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
768 | else | |
769 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); | |
770 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
771 | gen_set_label(l1); | |
772 | tcg_temp_free(t0); | |
79aceca5 FB |
773 | } |
774 | ||
636aa200 BS |
775 | static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, |
776 | TCGv arg2, int sub) | |
74637406 AJ |
777 | { |
778 | int l1 = gen_new_label(); | |
d9bce9d9 JM |
779 | |
780 | #if defined(TARGET_PPC64) | |
74637406 AJ |
781 | if (!(ctx->sf_mode)) { |
782 | TCGv t0, t1; | |
a7812ae4 PB |
783 | t0 = tcg_temp_new(); |
784 | t1 = tcg_temp_new(); | |
d9bce9d9 | 785 | |
74637406 AJ |
786 | tcg_gen_ext32u_tl(t0, arg1); |
787 | tcg_gen_ext32u_tl(t1, arg2); | |
788 | if (sub) { | |
789 | tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); | |
bdc4e053 | 790 | } else { |
74637406 AJ |
791 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
792 | } | |
a9730017 AJ |
793 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
794 | gen_set_label(l1); | |
795 | tcg_temp_free(t0); | |
796 | tcg_temp_free(t1); | |
74637406 AJ |
797 | } else |
798 | #endif | |
a9730017 AJ |
799 | { |
800 | if (sub) { | |
801 | tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1); | |
802 | } else { | |
803 | tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1); | |
804 | } | |
805 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); | |
806 | gen_set_label(l1); | |
74637406 | 807 | } |
d9bce9d9 JM |
808 | } |
809 | ||
74637406 | 810 | /* Common add function */ |
636aa200 BS |
811 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
812 | TCGv arg2, int add_ca, int compute_ca, | |
813 | int compute_ov) | |
74637406 AJ |
814 | { |
815 | TCGv t0, t1; | |
d9bce9d9 | 816 | |
74637406 | 817 | if ((!compute_ca && !compute_ov) || |
a7812ae4 | 818 | (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) { |
74637406 AJ |
819 | t0 = ret; |
820 | } else { | |
a7812ae4 | 821 | t0 = tcg_temp_local_new(); |
74637406 | 822 | } |
79aceca5 | 823 | |
74637406 | 824 | if (add_ca) { |
a7812ae4 | 825 | t1 = tcg_temp_local_new(); |
74637406 AJ |
826 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); |
827 | tcg_gen_shri_tl(t1, t1, XER_CA); | |
d2e9fd8f | 828 | } else { |
829 | TCGV_UNUSED(t1); | |
74637406 | 830 | } |
79aceca5 | 831 | |
74637406 AJ |
832 | if (compute_ca && compute_ov) { |
833 | /* Start with XER CA and OV disabled, the most likely case */ | |
834 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); | |
835 | } else if (compute_ca) { | |
836 | /* Start with XER CA disabled, the most likely case */ | |
837 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
838 | } else if (compute_ov) { | |
839 | /* Start with XER OV disabled, the most likely case */ | |
840 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
841 | } | |
79aceca5 | 842 | |
74637406 AJ |
843 | tcg_gen_add_tl(t0, arg1, arg2); |
844 | ||
845 | if (compute_ca) { | |
846 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
847 | } | |
848 | if (add_ca) { | |
849 | tcg_gen_add_tl(t0, t0, t1); | |
850 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
851 | tcg_temp_free(t1); | |
852 | } | |
853 | if (compute_ov) { | |
854 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
855 | } | |
856 | ||
857 | if (unlikely(Rc(ctx->opcode) != 0)) | |
858 | gen_set_Rc0(ctx, t0); | |
859 | ||
a7812ae4 | 860 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
861 | tcg_gen_mov_tl(ret, t0); |
862 | tcg_temp_free(t0); | |
863 | } | |
39dd32ee | 864 | } |
74637406 AJ |
865 | /* Add functions with two operands */ |
866 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
99e300ef | 867 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
868 | { \ |
869 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
870 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
871 | add_ca, compute_ca, compute_ov); \ | |
872 | } | |
873 | /* Add functions with one operand and one immediate */ | |
874 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
875 | add_ca, compute_ca, compute_ov) \ | |
99e300ef | 876 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
877 | { \ |
878 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
879 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
880 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
881 | add_ca, compute_ca, compute_ov); \ | |
882 | tcg_temp_free(t0); \ | |
883 | } | |
884 | ||
885 | /* add add. addo addo. */ | |
886 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
887 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
888 | /* addc addc. addco addco. */ | |
889 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
890 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
891 | /* adde adde. addeo addeo. */ | |
892 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
893 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
894 | /* addme addme. addmeo addmeo. */ | |
895 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
896 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
897 | /* addze addze. addzeo addzeo.*/ | |
898 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
899 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
900 | /* addi */ | |
99e300ef | 901 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 902 | { |
74637406 AJ |
903 | target_long simm = SIMM(ctx->opcode); |
904 | ||
905 | if (rA(ctx->opcode) == 0) { | |
906 | /* li case */ | |
907 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
908 | } else { | |
909 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm); | |
910 | } | |
d9bce9d9 | 911 | } |
74637406 | 912 | /* addic addic.*/ |
636aa200 BS |
913 | static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1, |
914 | int compute_Rc0) | |
d9bce9d9 | 915 | { |
74637406 AJ |
916 | target_long simm = SIMM(ctx->opcode); |
917 | ||
918 | /* Start with XER CA and OV disabled, the most likely case */ | |
919 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
920 | ||
921 | if (likely(simm != 0)) { | |
a7812ae4 | 922 | TCGv t0 = tcg_temp_local_new(); |
74637406 AJ |
923 | tcg_gen_addi_tl(t0, arg1, simm); |
924 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
925 | tcg_gen_mov_tl(ret, t0); | |
926 | tcg_temp_free(t0); | |
927 | } else { | |
928 | tcg_gen_mov_tl(ret, arg1); | |
929 | } | |
930 | if (compute_Rc0) { | |
931 | gen_set_Rc0(ctx, ret); | |
932 | } | |
d9bce9d9 | 933 | } |
99e300ef BS |
934 | |
935 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 936 | { |
74637406 | 937 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
d9bce9d9 | 938 | } |
e8eaa2c0 BS |
939 | |
940 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 941 | { |
74637406 | 942 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
d9bce9d9 | 943 | } |
99e300ef | 944 | |
54623277 | 945 | /* addis */ |
99e300ef | 946 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 947 | { |
74637406 AJ |
948 | target_long simm = SIMM(ctx->opcode); |
949 | ||
950 | if (rA(ctx->opcode) == 0) { | |
951 | /* lis case */ | |
952 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
953 | } else { | |
954 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16); | |
955 | } | |
d9bce9d9 | 956 | } |
74637406 | 957 | |
636aa200 BS |
958 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
959 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 960 | { |
2ef1b120 AJ |
961 | int l1 = gen_new_label(); |
962 | int l2 = gen_new_label(); | |
a7812ae4 PB |
963 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
964 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 965 | |
2ef1b120 AJ |
966 | tcg_gen_trunc_tl_i32(t0, arg1); |
967 | tcg_gen_trunc_tl_i32(t1, arg2); | |
968 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 969 | if (sign) { |
2ef1b120 AJ |
970 | int l3 = gen_new_label(); |
971 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
972 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 973 | gen_set_label(l3); |
2ef1b120 | 974 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 975 | } else { |
2ef1b120 | 976 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
977 | } |
978 | if (compute_ov) { | |
979 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
980 | } | |
981 | tcg_gen_br(l2); | |
982 | gen_set_label(l1); | |
983 | if (sign) { | |
2ef1b120 | 984 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
985 | } else { |
986 | tcg_gen_movi_i32(t0, 0); | |
987 | } | |
988 | if (compute_ov) { | |
989 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
990 | } | |
991 | gen_set_label(l2); | |
2ef1b120 | 992 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
993 | tcg_temp_free_i32(t0); |
994 | tcg_temp_free_i32(t1); | |
74637406 AJ |
995 | if (unlikely(Rc(ctx->opcode) != 0)) |
996 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 997 | } |
74637406 AJ |
998 | /* Div functions */ |
999 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 1000 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1001 | { \ |
1002 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1003 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1004 | sign, compute_ov); \ | |
1005 | } | |
1006 | /* divwu divwu. divwuo divwuo. */ | |
1007 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1008 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1009 | /* divw divw. divwo divwo. */ | |
1010 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1011 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
d9bce9d9 | 1012 | #if defined(TARGET_PPC64) |
636aa200 BS |
1013 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1014 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1015 | { |
2ef1b120 AJ |
1016 | int l1 = gen_new_label(); |
1017 | int l2 = gen_new_label(); | |
74637406 AJ |
1018 | |
1019 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
1020 | if (sign) { | |
2ef1b120 | 1021 | int l3 = gen_new_label(); |
74637406 AJ |
1022 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
1023 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
1024 | gen_set_label(l3); | |
74637406 AJ |
1025 | tcg_gen_div_i64(ret, arg1, arg2); |
1026 | } else { | |
1027 | tcg_gen_divu_i64(ret, arg1, arg2); | |
1028 | } | |
1029 | if (compute_ov) { | |
1030 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1031 | } | |
1032 | tcg_gen_br(l2); | |
1033 | gen_set_label(l1); | |
1034 | if (sign) { | |
1035 | tcg_gen_sari_i64(ret, arg1, 63); | |
1036 | } else { | |
1037 | tcg_gen_movi_i64(ret, 0); | |
1038 | } | |
1039 | if (compute_ov) { | |
1040 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1041 | } | |
1042 | gen_set_label(l2); | |
1043 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1044 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1045 | } |
74637406 | 1046 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1047 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1048 | { \ |
2ef1b120 AJ |
1049 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1050 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1051 | sign, compute_ov); \ | |
74637406 AJ |
1052 | } |
1053 | /* divwu divwu. divwuo divwuo. */ | |
1054 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1055 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1056 | /* divw divw. divwo divwo. */ | |
1057 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1058 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
d9bce9d9 | 1059 | #endif |
74637406 AJ |
1060 | |
1061 | /* mulhw mulhw. */ | |
99e300ef | 1062 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1063 | { |
a7812ae4 | 1064 | TCGv_i64 t0, t1; |
74637406 | 1065 | |
a7812ae4 PB |
1066 | t0 = tcg_temp_new_i64(); |
1067 | t1 = tcg_temp_new_i64(); | |
74637406 AJ |
1068 | #if defined(TARGET_PPC64) |
1069 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1070 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1071 | tcg_gen_mul_i64(t0, t0, t1); | |
1072 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
1073 | #else | |
1074 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1075 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1076 | tcg_gen_mul_i64(t0, t0, t1); | |
1077 | tcg_gen_shri_i64(t0, t0, 32); | |
1078 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1079 | #endif | |
a7812ae4 PB |
1080 | tcg_temp_free_i64(t0); |
1081 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1082 | if (unlikely(Rc(ctx->opcode) != 0)) |
1083 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1084 | } |
99e300ef | 1085 | |
54623277 | 1086 | /* mulhwu mulhwu. */ |
99e300ef | 1087 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1088 | { |
a7812ae4 | 1089 | TCGv_i64 t0, t1; |
74637406 | 1090 | |
a7812ae4 PB |
1091 | t0 = tcg_temp_new_i64(); |
1092 | t1 = tcg_temp_new_i64(); | |
d9bce9d9 | 1093 | #if defined(TARGET_PPC64) |
74637406 AJ |
1094 | tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1095 | tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1096 | tcg_gen_mul_i64(t0, t0, t1); | |
1097 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
1098 | #else | |
1099 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1100 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1101 | tcg_gen_mul_i64(t0, t0, t1); | |
1102 | tcg_gen_shri_i64(t0, t0, 32); | |
1103 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1104 | #endif | |
a7812ae4 PB |
1105 | tcg_temp_free_i64(t0); |
1106 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1107 | if (unlikely(Rc(ctx->opcode) != 0)) |
1108 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1109 | } |
99e300ef | 1110 | |
54623277 | 1111 | /* mullw mullw. */ |
99e300ef | 1112 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1113 | { |
74637406 AJ |
1114 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1115 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1116 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
74637406 AJ |
1117 | if (unlikely(Rc(ctx->opcode) != 0)) |
1118 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1119 | } |
99e300ef | 1120 | |
54623277 | 1121 | /* mullwo mullwo. */ |
99e300ef | 1122 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1123 | { |
74637406 | 1124 | int l1; |
a7812ae4 | 1125 | TCGv_i64 t0, t1; |
74637406 | 1126 | |
a7812ae4 PB |
1127 | t0 = tcg_temp_new_i64(); |
1128 | t1 = tcg_temp_new_i64(); | |
74637406 AJ |
1129 | l1 = gen_new_label(); |
1130 | /* Start with XER OV disabled, the most likely case */ | |
1131 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1132 | #if defined(TARGET_PPC64) | |
1133 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1134 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1135 | #else | |
1136 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1137 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
d9bce9d9 | 1138 | #endif |
74637406 AJ |
1139 | tcg_gen_mul_i64(t0, t0, t1); |
1140 | #if defined(TARGET_PPC64) | |
1141 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1142 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); | |
1143 | #else | |
1144 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1145 | tcg_gen_ext32s_i64(t1, t0); | |
1146 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
1147 | #endif | |
1148 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1149 | gen_set_label(l1); | |
a7812ae4 PB |
1150 | tcg_temp_free_i64(t0); |
1151 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1152 | if (unlikely(Rc(ctx->opcode) != 0)) |
1153 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1154 | } |
99e300ef | 1155 | |
54623277 | 1156 | /* mulli */ |
99e300ef | 1157 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1158 | { |
74637406 AJ |
1159 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1160 | SIMM(ctx->opcode)); | |
d9bce9d9 JM |
1161 | } |
1162 | #if defined(TARGET_PPC64) | |
74637406 | 1163 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ |
99e300ef | 1164 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1165 | { \ |
a7812ae4 | 1166 | gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \ |
74637406 AJ |
1167 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
1168 | if (unlikely(Rc(ctx->opcode) != 0)) \ | |
1169 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
d9bce9d9 | 1170 | } |
74637406 AJ |
1171 | /* mulhd mulhd. */ |
1172 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00); | |
1173 | /* mulhdu mulhdu. */ | |
1174 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02); | |
99e300ef | 1175 | |
54623277 | 1176 | /* mulld mulld. */ |
99e300ef | 1177 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1178 | { |
74637406 AJ |
1179 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1180 | cpu_gpr[rB(ctx->opcode)]); | |
1181 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1182 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1183 | } |
d15f74fb | 1184 | |
74637406 | 1185 | /* mulldo mulldo. */ |
d15f74fb BS |
1186 | static void gen_mulldo(DisasContext *ctx) |
1187 | { | |
1188 | gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env, | |
1189 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1190 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1191 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1192 | } | |
1193 | } | |
d9bce9d9 | 1194 | #endif |
74637406 AJ |
1195 | |
1196 | /* neg neg. nego nego. */ | |
636aa200 BS |
1197 | static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1, |
1198 | int ov_check) | |
d9bce9d9 | 1199 | { |
ec6469a3 AJ |
1200 | int l1 = gen_new_label(); |
1201 | int l2 = gen_new_label(); | |
a7812ae4 | 1202 | TCGv t0 = tcg_temp_local_new(); |
d9bce9d9 | 1203 | #if defined(TARGET_PPC64) |
74637406 | 1204 | if (ctx->sf_mode) { |
741a7444 | 1205 | tcg_gen_mov_tl(t0, arg1); |
ec6469a3 AJ |
1206 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); |
1207 | } else | |
1208 | #endif | |
1209 | { | |
1210 | tcg_gen_ext32s_tl(t0, arg1); | |
74637406 AJ |
1211 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); |
1212 | } | |
74637406 AJ |
1213 | tcg_gen_neg_tl(ret, arg1); |
1214 | if (ov_check) { | |
1215 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1216 | } | |
1217 | tcg_gen_br(l2); | |
1218 | gen_set_label(l1); | |
ec6469a3 | 1219 | tcg_gen_mov_tl(ret, t0); |
74637406 AJ |
1220 | if (ov_check) { |
1221 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1222 | } | |
1223 | gen_set_label(l2); | |
ec6469a3 | 1224 | tcg_temp_free(t0); |
74637406 AJ |
1225 | if (unlikely(Rc(ctx->opcode) != 0)) |
1226 | gen_set_Rc0(ctx, ret); | |
1227 | } | |
99e300ef BS |
1228 | |
1229 | static void gen_neg(DisasContext *ctx) | |
d9bce9d9 | 1230 | { |
ec6469a3 | 1231 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
d9bce9d9 | 1232 | } |
99e300ef BS |
1233 | |
1234 | static void gen_nego(DisasContext *ctx) | |
79aceca5 | 1235 | { |
ec6469a3 | 1236 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
79aceca5 | 1237 | } |
74637406 AJ |
1238 | |
1239 | /* Common subf function */ | |
636aa200 BS |
1240 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
1241 | TCGv arg2, int add_ca, int compute_ca, | |
1242 | int compute_ov) | |
79aceca5 | 1243 | { |
74637406 | 1244 | TCGv t0, t1; |
76a66253 | 1245 | |
74637406 | 1246 | if ((!compute_ca && !compute_ov) || |
a7812ae4 | 1247 | (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) { |
74637406 | 1248 | t0 = ret; |
e864cabd | 1249 | } else { |
a7812ae4 | 1250 | t0 = tcg_temp_local_new(); |
d9bce9d9 | 1251 | } |
76a66253 | 1252 | |
74637406 | 1253 | if (add_ca) { |
a7812ae4 | 1254 | t1 = tcg_temp_local_new(); |
74637406 AJ |
1255 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); |
1256 | tcg_gen_shri_tl(t1, t1, XER_CA); | |
d2e9fd8f | 1257 | } else { |
1258 | TCGV_UNUSED(t1); | |
d9bce9d9 | 1259 | } |
79aceca5 | 1260 | |
74637406 AJ |
1261 | if (compute_ca && compute_ov) { |
1262 | /* Start with XER CA and OV disabled, the most likely case */ | |
1263 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); | |
1264 | } else if (compute_ca) { | |
1265 | /* Start with XER CA disabled, the most likely case */ | |
1266 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1267 | } else if (compute_ov) { | |
1268 | /* Start with XER OV disabled, the most likely case */ | |
1269 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1270 | } | |
1271 | ||
1272 | if (add_ca) { | |
1273 | tcg_gen_not_tl(t0, arg1); | |
1274 | tcg_gen_add_tl(t0, t0, arg2); | |
1275 | gen_op_arith_compute_ca(ctx, t0, arg2, 0); | |
1276 | tcg_gen_add_tl(t0, t0, t1); | |
1277 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
1278 | tcg_temp_free(t1); | |
79aceca5 | 1279 | } else { |
74637406 AJ |
1280 | tcg_gen_sub_tl(t0, arg2, arg1); |
1281 | if (compute_ca) { | |
1282 | gen_op_arith_compute_ca(ctx, t0, arg2, 1); | |
1283 | } | |
1284 | } | |
1285 | if (compute_ov) { | |
1286 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1287 | } | |
1288 | ||
1289 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1290 | gen_set_Rc0(ctx, t0); | |
1291 | ||
a7812ae4 | 1292 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1293 | tcg_gen_mov_tl(ret, t0); |
1294 | tcg_temp_free(t0); | |
79aceca5 | 1295 | } |
79aceca5 | 1296 | } |
74637406 AJ |
1297 | /* Sub functions with Two operands functions */ |
1298 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
99e300ef | 1299 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1300 | { \ |
1301 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1302 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1303 | add_ca, compute_ca, compute_ov); \ | |
1304 | } | |
1305 | /* Sub functions with one operand and one immediate */ | |
1306 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1307 | add_ca, compute_ca, compute_ov) \ | |
99e300ef | 1308 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1309 | { \ |
1310 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
1311 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1312 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
1313 | add_ca, compute_ca, compute_ov); \ | |
1314 | tcg_temp_free(t0); \ | |
1315 | } | |
1316 | /* subf subf. subfo subfo. */ | |
1317 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1318 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1319 | /* subfc subfc. subfco subfco. */ | |
1320 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1321 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1322 | /* subfe subfe. subfeo subfo. */ | |
1323 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1324 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1325 | /* subfme subfme. subfmeo subfmeo. */ | |
1326 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1327 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1328 | /* subfze subfze. subfzeo subfzeo.*/ | |
1329 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1330 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1331 | |
54623277 | 1332 | /* subfic */ |
99e300ef | 1333 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1334 | { |
74637406 AJ |
1335 | /* Start with XER CA and OV disabled, the most likely case */ |
1336 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
a7812ae4 | 1337 | TCGv t0 = tcg_temp_local_new(); |
74637406 AJ |
1338 | TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode)); |
1339 | tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]); | |
1340 | gen_op_arith_compute_ca(ctx, t0, t1, 1); | |
1341 | tcg_temp_free(t1); | |
1342 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1343 | tcg_temp_free(t0); | |
79aceca5 FB |
1344 | } |
1345 | ||
79aceca5 | 1346 | /*** Integer logical ***/ |
26d67362 | 1347 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1348 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1349 | { \ |
26d67362 AJ |
1350 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1351 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1352 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1353 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1354 | } |
79aceca5 | 1355 | |
26d67362 | 1356 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1357 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1358 | { \ |
26d67362 | 1359 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1360 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1361 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1362 | } |
1363 | ||
1364 | /* and & and. */ | |
26d67362 | 1365 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1366 | /* andc & andc. */ |
26d67362 | 1367 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1368 | |
54623277 | 1369 | /* andi. */ |
e8eaa2c0 | 1370 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1371 | { |
26d67362 AJ |
1372 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1373 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1374 | } |
e8eaa2c0 | 1375 | |
54623277 | 1376 | /* andis. */ |
e8eaa2c0 | 1377 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1378 | { |
26d67362 AJ |
1379 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1380 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1381 | } |
99e300ef | 1382 | |
54623277 | 1383 | /* cntlzw */ |
99e300ef | 1384 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1385 | { |
a7812ae4 | 1386 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1387 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1388 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1389 | } |
79aceca5 | 1390 | /* eqv & eqv. */ |
26d67362 | 1391 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1392 | /* extsb & extsb. */ |
26d67362 | 1393 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1394 | /* extsh & extsh. */ |
26d67362 | 1395 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1396 | /* nand & nand. */ |
26d67362 | 1397 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1398 | /* nor & nor. */ |
26d67362 | 1399 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1400 | |
54623277 | 1401 | /* or & or. */ |
99e300ef | 1402 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1403 | { |
76a66253 JM |
1404 | int rs, ra, rb; |
1405 | ||
1406 | rs = rS(ctx->opcode); | |
1407 | ra = rA(ctx->opcode); | |
1408 | rb = rB(ctx->opcode); | |
1409 | /* Optimisation for mr. ri case */ | |
1410 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1411 | if (rs != rb) |
1412 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1413 | else | |
1414 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1415 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1416 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1417 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1418 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1419 | #if defined(TARGET_PPC64) |
1420 | } else { | |
26d67362 AJ |
1421 | int prio = 0; |
1422 | ||
c80f84e3 JM |
1423 | switch (rs) { |
1424 | case 1: | |
1425 | /* Set process priority to low */ | |
26d67362 | 1426 | prio = 2; |
c80f84e3 JM |
1427 | break; |
1428 | case 6: | |
1429 | /* Set process priority to medium-low */ | |
26d67362 | 1430 | prio = 3; |
c80f84e3 JM |
1431 | break; |
1432 | case 2: | |
1433 | /* Set process priority to normal */ | |
26d67362 | 1434 | prio = 4; |
c80f84e3 | 1435 | break; |
be147d08 JM |
1436 | #if !defined(CONFIG_USER_ONLY) |
1437 | case 31: | |
76db3ba4 | 1438 | if (ctx->mem_idx > 0) { |
be147d08 | 1439 | /* Set process priority to very low */ |
26d67362 | 1440 | prio = 1; |
be147d08 JM |
1441 | } |
1442 | break; | |
1443 | case 5: | |
76db3ba4 | 1444 | if (ctx->mem_idx > 0) { |
be147d08 | 1445 | /* Set process priority to medium-hight */ |
26d67362 | 1446 | prio = 5; |
be147d08 JM |
1447 | } |
1448 | break; | |
1449 | case 3: | |
76db3ba4 | 1450 | if (ctx->mem_idx > 0) { |
be147d08 | 1451 | /* Set process priority to high */ |
26d67362 | 1452 | prio = 6; |
be147d08 JM |
1453 | } |
1454 | break; | |
be147d08 | 1455 | case 7: |
76db3ba4 | 1456 | if (ctx->mem_idx > 1) { |
be147d08 | 1457 | /* Set process priority to very high */ |
26d67362 | 1458 | prio = 7; |
be147d08 JM |
1459 | } |
1460 | break; | |
be147d08 | 1461 | #endif |
c80f84e3 JM |
1462 | default: |
1463 | /* nop */ | |
1464 | break; | |
1465 | } | |
26d67362 | 1466 | if (prio) { |
a7812ae4 | 1467 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1468 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1469 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1470 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1471 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1472 | tcg_temp_free(t0); |
26d67362 | 1473 | } |
c80f84e3 | 1474 | #endif |
9a64fbe4 | 1475 | } |
9a64fbe4 | 1476 | } |
79aceca5 | 1477 | /* orc & orc. */ |
26d67362 | 1478 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1479 | |
54623277 | 1480 | /* xor & xor. */ |
99e300ef | 1481 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1482 | { |
9a64fbe4 | 1483 | /* Optimisation for "set to zero" case */ |
26d67362 | 1484 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1485 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1486 | else |
1487 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1488 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1489 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1490 | } |
99e300ef | 1491 | |
54623277 | 1492 | /* ori */ |
99e300ef | 1493 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1494 | { |
76a66253 | 1495 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1496 | |
9a64fbe4 FB |
1497 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1498 | /* NOP */ | |
76a66253 | 1499 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1500 | return; |
76a66253 | 1501 | } |
26d67362 | 1502 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1503 | } |
99e300ef | 1504 | |
54623277 | 1505 | /* oris */ |
99e300ef | 1506 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1507 | { |
76a66253 | 1508 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1509 | |
9a64fbe4 FB |
1510 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1511 | /* NOP */ | |
1512 | return; | |
76a66253 | 1513 | } |
26d67362 | 1514 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1515 | } |
99e300ef | 1516 | |
54623277 | 1517 | /* xori */ |
99e300ef | 1518 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1519 | { |
76a66253 | 1520 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1521 | |
1522 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1523 | /* NOP */ | |
1524 | return; | |
1525 | } | |
26d67362 | 1526 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1527 | } |
99e300ef | 1528 | |
54623277 | 1529 | /* xoris */ |
99e300ef | 1530 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1531 | { |
76a66253 | 1532 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1533 | |
1534 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1535 | /* NOP */ | |
1536 | return; | |
1537 | } | |
26d67362 | 1538 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1539 | } |
99e300ef | 1540 | |
54623277 | 1541 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1542 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1543 | { |
eaabeef2 DG |
1544 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1545 | } | |
1546 | ||
1547 | static void gen_popcntw(DisasContext *ctx) | |
1548 | { | |
1549 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1550 | } | |
1551 | ||
d9bce9d9 | 1552 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1553 | /* popcntd: PowerPC 2.06 specification */ |
1554 | static void gen_popcntd(DisasContext *ctx) | |
1555 | { | |
1556 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1557 | } |
eaabeef2 | 1558 | #endif |
d9bce9d9 JM |
1559 | |
1560 | #if defined(TARGET_PPC64) | |
1561 | /* extsw & extsw. */ | |
26d67362 | 1562 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1563 | |
54623277 | 1564 | /* cntlzd */ |
99e300ef | 1565 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1566 | { |
a7812ae4 | 1567 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1568 | if (unlikely(Rc(ctx->opcode) != 0)) |
1569 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1570 | } | |
d9bce9d9 JM |
1571 | #endif |
1572 | ||
79aceca5 | 1573 | /*** Integer rotate ***/ |
99e300ef | 1574 | |
54623277 | 1575 | /* rlwimi & rlwimi. */ |
99e300ef | 1576 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1577 | { |
76a66253 | 1578 | uint32_t mb, me, sh; |
79aceca5 FB |
1579 | |
1580 | mb = MB(ctx->opcode); | |
1581 | me = ME(ctx->opcode); | |
76a66253 | 1582 | sh = SH(ctx->opcode); |
d03ef511 AJ |
1583 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1584 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1585 | } else { | |
d03ef511 | 1586 | target_ulong mask; |
a7812ae4 PB |
1587 | TCGv t1; |
1588 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1589 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1590 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1591 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1592 | tcg_gen_rotli_i32(t2, t2, sh); | |
1593 | tcg_gen_extu_i32_i64(t0, t2); | |
1594 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1595 | #else |
1596 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1597 | #endif | |
76a66253 | 1598 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1599 | mb += 32; |
1600 | me += 32; | |
76a66253 | 1601 | #endif |
d03ef511 | 1602 | mask = MASK(mb, me); |
a7812ae4 | 1603 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1604 | tcg_gen_andi_tl(t0, t0, mask); |
1605 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1606 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1607 | tcg_temp_free(t0); | |
1608 | tcg_temp_free(t1); | |
1609 | } | |
76a66253 | 1610 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1611 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1612 | } |
99e300ef | 1613 | |
54623277 | 1614 | /* rlwinm & rlwinm. */ |
99e300ef | 1615 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1616 | { |
1617 | uint32_t mb, me, sh; | |
3b46e624 | 1618 | |
79aceca5 FB |
1619 | sh = SH(ctx->opcode); |
1620 | mb = MB(ctx->opcode); | |
1621 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1622 | |
1623 | if (likely(mb == 0 && me == (31 - sh))) { | |
1624 | if (likely(sh == 0)) { | |
1625 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1626 | } else { | |
a7812ae4 | 1627 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1628 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1629 | tcg_gen_shli_tl(t0, t0, sh); | |
1630 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1631 | tcg_temp_free(t0); | |
79aceca5 | 1632 | } |
d03ef511 | 1633 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1634 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1635 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1636 | tcg_gen_shri_tl(t0, t0, mb); | |
1637 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1638 | tcg_temp_free(t0); | |
1639 | } else { | |
a7812ae4 | 1640 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1641 | #if defined(TARGET_PPC64) |
a7812ae4 | 1642 | TCGv_i32 t1 = tcg_temp_new_i32(); |
54843a58 AJ |
1643 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1644 | tcg_gen_rotli_i32(t1, t1, sh); | |
1645 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 | 1646 | tcg_temp_free_i32(t1); |
54843a58 AJ |
1647 | #else |
1648 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1649 | #endif | |
76a66253 | 1650 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1651 | mb += 32; |
1652 | me += 32; | |
76a66253 | 1653 | #endif |
d03ef511 AJ |
1654 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1655 | tcg_temp_free(t0); | |
1656 | } | |
76a66253 | 1657 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1658 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1659 | } |
99e300ef | 1660 | |
54623277 | 1661 | /* rlwnm & rlwnm. */ |
99e300ef | 1662 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1663 | { |
1664 | uint32_t mb, me; | |
54843a58 AJ |
1665 | TCGv t0; |
1666 | #if defined(TARGET_PPC64) | |
a7812ae4 | 1667 | TCGv_i32 t1, t2; |
54843a58 | 1668 | #endif |
79aceca5 FB |
1669 | |
1670 | mb = MB(ctx->opcode); | |
1671 | me = ME(ctx->opcode); | |
a7812ae4 | 1672 | t0 = tcg_temp_new(); |
d03ef511 | 1673 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1674 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1675 | t1 = tcg_temp_new_i32(); |
1676 | t2 = tcg_temp_new_i32(); | |
54843a58 AJ |
1677 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1678 | tcg_gen_trunc_i64_i32(t2, t0); | |
1679 | tcg_gen_rotl_i32(t1, t1, t2); | |
1680 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 PB |
1681 | tcg_temp_free_i32(t1); |
1682 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1683 | #else |
1684 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1685 | #endif | |
76a66253 JM |
1686 | if (unlikely(mb != 0 || me != 31)) { |
1687 | #if defined(TARGET_PPC64) | |
1688 | mb += 32; | |
1689 | me += 32; | |
1690 | #endif | |
54843a58 | 1691 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1692 | } else { |
54843a58 | 1693 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1694 | } |
54843a58 | 1695 | tcg_temp_free(t0); |
76a66253 | 1696 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1697 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1698 | } |
1699 | ||
d9bce9d9 JM |
1700 | #if defined(TARGET_PPC64) |
1701 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1702 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1703 | { \ |
1704 | gen_##name(ctx, 0); \ | |
1705 | } \ | |
e8eaa2c0 BS |
1706 | \ |
1707 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1708 | { \ |
1709 | gen_##name(ctx, 1); \ | |
1710 | } | |
1711 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1712 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1713 | { \ |
1714 | gen_##name(ctx, 0, 0); \ | |
1715 | } \ | |
e8eaa2c0 BS |
1716 | \ |
1717 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1718 | { \ |
1719 | gen_##name(ctx, 0, 1); \ | |
1720 | } \ | |
e8eaa2c0 BS |
1721 | \ |
1722 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1723 | { \ |
1724 | gen_##name(ctx, 1, 0); \ | |
1725 | } \ | |
e8eaa2c0 BS |
1726 | \ |
1727 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1728 | { \ |
1729 | gen_##name(ctx, 1, 1); \ | |
1730 | } | |
51789c41 | 1731 | |
636aa200 BS |
1732 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1733 | uint32_t sh) | |
51789c41 | 1734 | { |
d03ef511 AJ |
1735 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1736 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1737 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1738 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1739 | } else { | |
a7812ae4 | 1740 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1741 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1742 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1743 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1744 | } else { |
1745 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1746 | } |
d03ef511 | 1747 | tcg_temp_free(t0); |
51789c41 | 1748 | } |
51789c41 | 1749 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1750 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1751 | } |
d9bce9d9 | 1752 | /* rldicl - rldicl. */ |
636aa200 | 1753 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1754 | { |
51789c41 | 1755 | uint32_t sh, mb; |
d9bce9d9 | 1756 | |
9d53c753 JM |
1757 | sh = SH(ctx->opcode) | (shn << 5); |
1758 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1759 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1760 | } |
51789c41 | 1761 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1762 | /* rldicr - rldicr. */ |
636aa200 | 1763 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1764 | { |
51789c41 | 1765 | uint32_t sh, me; |
d9bce9d9 | 1766 | |
9d53c753 JM |
1767 | sh = SH(ctx->opcode) | (shn << 5); |
1768 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1769 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1770 | } |
51789c41 | 1771 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1772 | /* rldic - rldic. */ |
636aa200 | 1773 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1774 | { |
51789c41 | 1775 | uint32_t sh, mb; |
d9bce9d9 | 1776 | |
9d53c753 JM |
1777 | sh = SH(ctx->opcode) | (shn << 5); |
1778 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1779 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1780 | } | |
1781 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1782 | ||
636aa200 | 1783 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1784 | { |
54843a58 | 1785 | TCGv t0; |
d03ef511 AJ |
1786 | |
1787 | mb = MB(ctx->opcode); | |
1788 | me = ME(ctx->opcode); | |
a7812ae4 | 1789 | t0 = tcg_temp_new(); |
d03ef511 | 1790 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1791 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1792 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1793 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1794 | } else { | |
1795 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1796 | } | |
1797 | tcg_temp_free(t0); | |
51789c41 | 1798 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1799 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1800 | } |
51789c41 | 1801 | |
d9bce9d9 | 1802 | /* rldcl - rldcl. */ |
636aa200 | 1803 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1804 | { |
51789c41 | 1805 | uint32_t mb; |
d9bce9d9 | 1806 | |
9d53c753 | 1807 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1808 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1809 | } |
36081602 | 1810 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1811 | /* rldcr - rldcr. */ |
636aa200 | 1812 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1813 | { |
51789c41 | 1814 | uint32_t me; |
d9bce9d9 | 1815 | |
9d53c753 | 1816 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1817 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1818 | } |
36081602 | 1819 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1820 | /* rldimi - rldimi. */ |
636aa200 | 1821 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1822 | { |
271a916e | 1823 | uint32_t sh, mb, me; |
d9bce9d9 | 1824 | |
9d53c753 JM |
1825 | sh = SH(ctx->opcode) | (shn << 5); |
1826 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1827 | me = 63 - sh; |
d03ef511 AJ |
1828 | if (unlikely(sh == 0 && mb == 0)) { |
1829 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1830 | } else { | |
1831 | TCGv t0, t1; | |
1832 | target_ulong mask; | |
1833 | ||
a7812ae4 | 1834 | t0 = tcg_temp_new(); |
54843a58 | 1835 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1836 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1837 | mask = MASK(mb, me); |
1838 | tcg_gen_andi_tl(t0, t0, mask); | |
1839 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1840 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1841 | tcg_temp_free(t0); | |
1842 | tcg_temp_free(t1); | |
51789c41 | 1843 | } |
51789c41 | 1844 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1845 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1846 | } |
36081602 | 1847 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1848 | #endif |
1849 | ||
79aceca5 | 1850 | /*** Integer shift ***/ |
99e300ef | 1851 | |
54623277 | 1852 | /* slw & slw. */ |
99e300ef | 1853 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1854 | { |
7fd6bf7d | 1855 | TCGv t0, t1; |
26d67362 | 1856 | |
7fd6bf7d AJ |
1857 | t0 = tcg_temp_new(); |
1858 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1859 | #if defined(TARGET_PPC64) | |
1860 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1861 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1862 | #else | |
1863 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1864 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1865 | #endif | |
1866 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1867 | t1 = tcg_temp_new(); | |
1868 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1869 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1870 | tcg_temp_free(t1); | |
fea0c503 | 1871 | tcg_temp_free(t0); |
7fd6bf7d | 1872 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1873 | if (unlikely(Rc(ctx->opcode) != 0)) |
1874 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1875 | } | |
99e300ef | 1876 | |
54623277 | 1877 | /* sraw & sraw. */ |
99e300ef | 1878 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1879 | { |
d15f74fb | 1880 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1881 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1882 | if (unlikely(Rc(ctx->opcode) != 0)) |
1883 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1884 | } | |
99e300ef | 1885 | |
54623277 | 1886 | /* srawi & srawi. */ |
99e300ef | 1887 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1888 | { |
26d67362 AJ |
1889 | int sh = SH(ctx->opcode); |
1890 | if (sh != 0) { | |
1891 | int l1, l2; | |
fea0c503 | 1892 | TCGv t0; |
26d67362 AJ |
1893 | l1 = gen_new_label(); |
1894 | l2 = gen_new_label(); | |
a7812ae4 | 1895 | t0 = tcg_temp_local_new(); |
fea0c503 AJ |
1896 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1897 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
1898 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); | |
1899 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
269f3e95 | 1900 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
26d67362 AJ |
1901 | tcg_gen_br(l2); |
1902 | gen_set_label(l1); | |
269f3e95 | 1903 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
26d67362 | 1904 | gen_set_label(l2); |
fea0c503 AJ |
1905 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1906 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); | |
1907 | tcg_temp_free(t0); | |
26d67362 AJ |
1908 | } else { |
1909 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
269f3e95 | 1910 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
d9bce9d9 | 1911 | } |
76a66253 | 1912 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1913 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1914 | } |
99e300ef | 1915 | |
54623277 | 1916 | /* srw & srw. */ |
99e300ef | 1917 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1918 | { |
fea0c503 | 1919 | TCGv t0, t1; |
d9bce9d9 | 1920 | |
7fd6bf7d AJ |
1921 | t0 = tcg_temp_new(); |
1922 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1923 | #if defined(TARGET_PPC64) | |
1924 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1925 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1926 | #else | |
1927 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1928 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1929 | #endif | |
1930 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1931 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1932 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1933 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1934 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1935 | tcg_temp_free(t1); |
fea0c503 | 1936 | tcg_temp_free(t0); |
26d67362 AJ |
1937 | if (unlikely(Rc(ctx->opcode) != 0)) |
1938 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1939 | } | |
54623277 | 1940 | |
d9bce9d9 JM |
1941 | #if defined(TARGET_PPC64) |
1942 | /* sld & sld. */ | |
99e300ef | 1943 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1944 | { |
7fd6bf7d | 1945 | TCGv t0, t1; |
26d67362 | 1946 | |
7fd6bf7d AJ |
1947 | t0 = tcg_temp_new(); |
1948 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1949 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1950 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1951 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1952 | t1 = tcg_temp_new(); | |
1953 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1954 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1955 | tcg_temp_free(t1); | |
fea0c503 | 1956 | tcg_temp_free(t0); |
26d67362 AJ |
1957 | if (unlikely(Rc(ctx->opcode) != 0)) |
1958 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1959 | } | |
99e300ef | 1960 | |
54623277 | 1961 | /* srad & srad. */ |
99e300ef | 1962 | static void gen_srad(DisasContext *ctx) |
26d67362 | 1963 | { |
d15f74fb | 1964 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1965 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1966 | if (unlikely(Rc(ctx->opcode) != 0)) |
1967 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1968 | } | |
d9bce9d9 | 1969 | /* sradi & sradi. */ |
636aa200 | 1970 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 1971 | { |
26d67362 | 1972 | int sh = SH(ctx->opcode) + (n << 5); |
d9bce9d9 | 1973 | if (sh != 0) { |
26d67362 | 1974 | int l1, l2; |
fea0c503 | 1975 | TCGv t0; |
26d67362 AJ |
1976 | l1 = gen_new_label(); |
1977 | l2 = gen_new_label(); | |
a7812ae4 | 1978 | t0 = tcg_temp_local_new(); |
26d67362 | 1979 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); |
fea0c503 AJ |
1980 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
1981 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
269f3e95 | 1982 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
26d67362 AJ |
1983 | tcg_gen_br(l2); |
1984 | gen_set_label(l1); | |
269f3e95 | 1985 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
26d67362 | 1986 | gen_set_label(l2); |
a9730017 | 1987 | tcg_temp_free(t0); |
26d67362 AJ |
1988 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1989 | } else { | |
1990 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
269f3e95 | 1991 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
d9bce9d9 | 1992 | } |
d9bce9d9 | 1993 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1994 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1995 | } |
e8eaa2c0 BS |
1996 | |
1997 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
1998 | { |
1999 | gen_sradi(ctx, 0); | |
2000 | } | |
e8eaa2c0 BS |
2001 | |
2002 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2003 | { |
2004 | gen_sradi(ctx, 1); | |
2005 | } | |
99e300ef | 2006 | |
54623277 | 2007 | /* srd & srd. */ |
99e300ef | 2008 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2009 | { |
7fd6bf7d | 2010 | TCGv t0, t1; |
26d67362 | 2011 | |
7fd6bf7d AJ |
2012 | t0 = tcg_temp_new(); |
2013 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2014 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2015 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2016 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2017 | t1 = tcg_temp_new(); | |
2018 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2019 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2020 | tcg_temp_free(t1); | |
fea0c503 | 2021 | tcg_temp_free(t0); |
26d67362 AJ |
2022 | if (unlikely(Rc(ctx->opcode) != 0)) |
2023 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2024 | } | |
d9bce9d9 | 2025 | #endif |
79aceca5 FB |
2026 | |
2027 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 2028 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 2029 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2030 | { \ |
76a66253 | 2031 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2032 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2033 | return; \ |
2034 | } \ | |
eb44b959 AJ |
2035 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2036 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2037 | gen_reset_fpstatus(); \ |
8e703949 BS |
2038 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2039 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2040 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2041 | if (isfloat) { \ |
8e703949 BS |
2042 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2043 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2044 | } \ |
af12906f AJ |
2045 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
2046 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
2047 | } |
2048 | ||
7c58044c JM |
2049 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
2050 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
2051 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 2052 | |
7c58044c | 2053 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2054 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2055 | { \ |
76a66253 | 2056 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2057 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2058 | return; \ |
2059 | } \ | |
eb44b959 AJ |
2060 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2061 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2062 | gen_reset_fpstatus(); \ |
8e703949 BS |
2063 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2064 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2065 | cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2066 | if (isfloat) { \ |
8e703949 BS |
2067 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2068 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2069 | } \ |
af12906f AJ |
2070 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2071 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2072 | } |
7c58044c JM |
2073 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2074 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2075 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2076 | |
7c58044c | 2077 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2078 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2079 | { \ |
76a66253 | 2080 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2081 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2082 | return; \ |
2083 | } \ | |
eb44b959 AJ |
2084 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2085 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2086 | gen_reset_fpstatus(); \ |
8e703949 BS |
2087 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2088 | cpu_fpr[rA(ctx->opcode)], \ | |
2089 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2090 | if (isfloat) { \ |
8e703949 BS |
2091 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2092 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2093 | } \ |
af12906f AJ |
2094 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2095 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2096 | } |
7c58044c JM |
2097 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2098 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2099 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2100 | |
7c58044c | 2101 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 2102 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2103 | { \ |
76a66253 | 2104 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2105 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2106 | return; \ |
2107 | } \ | |
eb44b959 AJ |
2108 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2109 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2110 | gen_reset_fpstatus(); \ |
8e703949 BS |
2111 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2112 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2113 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2114 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2115 | } |
2116 | ||
7c58044c | 2117 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2118 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2119 | { \ |
76a66253 | 2120 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2121 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2122 | return; \ |
2123 | } \ | |
eb44b959 AJ |
2124 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2125 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2126 | gen_reset_fpstatus(); \ |
8e703949 BS |
2127 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2128 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2129 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2130 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2131 | } |
2132 | ||
9a64fbe4 | 2133 | /* fadd - fadds */ |
7c58044c | 2134 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2135 | /* fdiv - fdivs */ |
7c58044c | 2136 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2137 | /* fmul - fmuls */ |
7c58044c | 2138 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2139 | |
d7e4b87e | 2140 | /* fre */ |
7c58044c | 2141 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2142 | |
a750fc0b | 2143 | /* fres */ |
7c58044c | 2144 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2145 | |
a750fc0b | 2146 | /* frsqrte */ |
7c58044c JM |
2147 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2148 | ||
2149 | /* frsqrtes */ | |
99e300ef | 2150 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2151 | { |
af12906f | 2152 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2153 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2154 | return; |
2155 | } | |
eb44b959 AJ |
2156 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2157 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f | 2158 | gen_reset_fpstatus(); |
8e703949 BS |
2159 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2160 | cpu_fpr[rB(ctx->opcode)]); | |
2161 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2162 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2163 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
7c58044c | 2164 | } |
79aceca5 | 2165 | |
a750fc0b | 2166 | /* fsel */ |
7c58044c | 2167 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2168 | /* fsub - fsubs */ |
7c58044c | 2169 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2170 | /* Optional: */ |
99e300ef | 2171 | |
54623277 | 2172 | /* fsqrt */ |
99e300ef | 2173 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2174 | { |
76a66253 | 2175 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2176 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2177 | return; |
2178 | } | |
eb44b959 AJ |
2179 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2180 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2181 | gen_reset_fpstatus(); |
8e703949 BS |
2182 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2183 | cpu_fpr[rB(ctx->opcode)]); | |
af12906f | 2184 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
c7d344af | 2185 | } |
79aceca5 | 2186 | |
99e300ef | 2187 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2188 | { |
76a66253 | 2189 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2190 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2191 | return; |
2192 | } | |
eb44b959 AJ |
2193 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2194 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2195 | gen_reset_fpstatus(); |
8e703949 BS |
2196 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2197 | cpu_fpr[rB(ctx->opcode)]); | |
2198 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2199 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2200 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2201 | } |
2202 | ||
2203 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2204 | /* fmadd - fmadds */ |
7c58044c | 2205 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2206 | /* fmsub - fmsubs */ |
7c58044c | 2207 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2208 | /* fnmadd - fnmadds */ |
7c58044c | 2209 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2210 | /* fnmsub - fnmsubs */ |
7c58044c | 2211 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2212 | |
2213 | /*** Floating-Point round & convert ***/ | |
2214 | /* fctiw */ | |
7c58044c | 2215 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2216 | /* fctiwz */ |
7c58044c | 2217 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2218 | /* frsp */ |
7c58044c | 2219 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2220 | #if defined(TARGET_PPC64) |
2221 | /* fcfid */ | |
7c58044c | 2222 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
426613db | 2223 | /* fctid */ |
7c58044c | 2224 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
426613db | 2225 | /* fctidz */ |
7c58044c | 2226 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
426613db | 2227 | #endif |
79aceca5 | 2228 | |
d7e4b87e | 2229 | /* frin */ |
7c58044c | 2230 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2231 | /* friz */ |
7c58044c | 2232 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2233 | /* frip */ |
7c58044c | 2234 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2235 | /* frim */ |
7c58044c | 2236 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2237 | |
79aceca5 | 2238 | /*** Floating-Point compare ***/ |
99e300ef | 2239 | |
54623277 | 2240 | /* fcmpo */ |
99e300ef | 2241 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2242 | { |
330c483b | 2243 | TCGv_i32 crf; |
76a66253 | 2244 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2245 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2246 | return; |
2247 | } | |
eb44b959 AJ |
2248 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2249 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2250 | gen_reset_fpstatus(); |
9a819377 | 2251 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2252 | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2253 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2254 | tcg_temp_free_i32(crf); |
8e703949 | 2255 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2256 | } |
2257 | ||
2258 | /* fcmpu */ | |
99e300ef | 2259 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2260 | { |
330c483b | 2261 | TCGv_i32 crf; |
76a66253 | 2262 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2263 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2264 | return; |
2265 | } | |
eb44b959 AJ |
2266 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2267 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2268 | gen_reset_fpstatus(); |
9a819377 | 2269 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2270 | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2271 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2272 | tcg_temp_free_i32(crf); |
8e703949 | 2273 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2274 | } |
2275 | ||
9a64fbe4 FB |
2276 | /*** Floating-point move ***/ |
2277 | /* fabs */ | |
7c58044c JM |
2278 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
2279 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); | |
9a64fbe4 FB |
2280 | |
2281 | /* fmr - fmr. */ | |
7c58044c | 2282 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2283 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2284 | { |
76a66253 | 2285 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2286 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2287 | return; |
2288 | } | |
af12906f AJ |
2289 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2290 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2291 | } |
2292 | ||
2293 | /* fnabs */ | |
7c58044c JM |
2294 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
2295 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); | |
9a64fbe4 | 2296 | /* fneg */ |
7c58044c JM |
2297 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
2298 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); | |
9a64fbe4 | 2299 | |
79aceca5 | 2300 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2301 | |
54623277 | 2302 | /* mcrfs */ |
99e300ef | 2303 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2304 | { |
30304420 | 2305 | TCGv tmp = tcg_temp_new(); |
7c58044c JM |
2306 | int bfa; |
2307 | ||
76a66253 | 2308 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2309 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2310 | return; |
2311 | } | |
7c58044c | 2312 | bfa = 4 * (7 - crfS(ctx->opcode)); |
30304420 DG |
2313 | tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); |
2314 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); | |
2315 | tcg_temp_free(tmp); | |
e1571908 | 2316 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
30304420 | 2317 | tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2318 | } |
2319 | ||
2320 | /* mffs */ | |
99e300ef | 2321 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2322 | { |
76a66253 | 2323 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2324 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2325 | return; |
2326 | } | |
7c58044c | 2327 | gen_reset_fpstatus(); |
30304420 | 2328 | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
af12906f | 2329 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2330 | } |
2331 | ||
2332 | /* mtfsb0 */ | |
99e300ef | 2333 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2334 | { |
fb0eaffc | 2335 | uint8_t crb; |
3b46e624 | 2336 | |
76a66253 | 2337 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2338 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2339 | return; |
2340 | } | |
6e35d524 | 2341 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2342 | gen_reset_fpstatus(); |
6e35d524 | 2343 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2344 | TCGv_i32 t0; |
2345 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2346 | gen_update_nip(ctx, ctx->nip - 4); | |
2347 | t0 = tcg_const_i32(crb); | |
8e703949 | 2348 | gen_helper_fpscr_clrbit(cpu_env, t0); |
6e35d524 AJ |
2349 | tcg_temp_free_i32(t0); |
2350 | } | |
7c58044c | 2351 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2352 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2353 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c | 2354 | } |
79aceca5 FB |
2355 | } |
2356 | ||
2357 | /* mtfsb1 */ | |
99e300ef | 2358 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2359 | { |
fb0eaffc | 2360 | uint8_t crb; |
3b46e624 | 2361 | |
76a66253 | 2362 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2363 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2364 | return; |
2365 | } | |
6e35d524 | 2366 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2367 | gen_reset_fpstatus(); |
2368 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2369 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2370 | TCGv_i32 t0; |
2371 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2372 | gen_update_nip(ctx, ctx->nip - 4); | |
2373 | t0 = tcg_const_i32(crb); | |
8e703949 | 2374 | gen_helper_fpscr_setbit(cpu_env, t0); |
0f2f39c2 | 2375 | tcg_temp_free_i32(t0); |
af12906f | 2376 | } |
7c58044c | 2377 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2378 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2379 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2380 | } |
2381 | /* We can raise a differed exception */ | |
8e703949 | 2382 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2383 | } |
2384 | ||
2385 | /* mtfsf */ | |
99e300ef | 2386 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2387 | { |
0f2f39c2 | 2388 | TCGv_i32 t0; |
4911012d | 2389 | int L = ctx->opcode & 0x02000000; |
af12906f | 2390 | |
76a66253 | 2391 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2392 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2393 | return; |
2394 | } | |
eb44b959 AJ |
2395 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2396 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2397 | gen_reset_fpstatus(); |
4911012d BS |
2398 | if (L) |
2399 | t0 = tcg_const_i32(0xff); | |
2400 | else | |
2401 | t0 = tcg_const_i32(FM(ctx->opcode)); | |
8e703949 | 2402 | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2403 | tcg_temp_free_i32(t0); |
7c58044c | 2404 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2405 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2406 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2407 | } |
2408 | /* We can raise a differed exception */ | |
8e703949 | 2409 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2410 | } |
2411 | ||
2412 | /* mtfsfi */ | |
99e300ef | 2413 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2414 | { |
7c58044c | 2415 | int bf, sh; |
0f2f39c2 AJ |
2416 | TCGv_i64 t0; |
2417 | TCGv_i32 t1; | |
7c58044c | 2418 | |
76a66253 | 2419 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2420 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2421 | return; |
2422 | } | |
7c58044c JM |
2423 | bf = crbD(ctx->opcode) >> 2; |
2424 | sh = 7 - bf; | |
eb44b959 AJ |
2425 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2426 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2427 | gen_reset_fpstatus(); |
0f2f39c2 | 2428 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); |
af12906f | 2429 | t1 = tcg_const_i32(1 << sh); |
8e703949 | 2430 | gen_helper_store_fpscr(cpu_env, t0, t1); |
0f2f39c2 AJ |
2431 | tcg_temp_free_i64(t0); |
2432 | tcg_temp_free_i32(t1); | |
7c58044c | 2433 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2434 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2435 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2436 | } |
2437 | /* We can raise a differed exception */ | |
8e703949 | 2438 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2439 | } |
2440 | ||
76a66253 JM |
2441 | /*** Addressing modes ***/ |
2442 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2443 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2444 | target_long maskl) | |
76a66253 JM |
2445 | { |
2446 | target_long simm = SIMM(ctx->opcode); | |
2447 | ||
be147d08 | 2448 | simm &= ~maskl; |
76db3ba4 AJ |
2449 | if (rA(ctx->opcode) == 0) { |
2450 | #if defined(TARGET_PPC64) | |
2451 | if (!ctx->sf_mode) { | |
2452 | tcg_gen_movi_tl(EA, (uint32_t)simm); | |
2453 | } else | |
2454 | #endif | |
e2be8d8d | 2455 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2456 | } else if (likely(simm != 0)) { |
e2be8d8d | 2457 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
76db3ba4 AJ |
2458 | #if defined(TARGET_PPC64) |
2459 | if (!ctx->sf_mode) { | |
2460 | tcg_gen_ext32u_tl(EA, EA); | |
2461 | } | |
2462 | #endif | |
2463 | } else { | |
2464 | #if defined(TARGET_PPC64) | |
2465 | if (!ctx->sf_mode) { | |
2466 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2467 | } else | |
2468 | #endif | |
e2be8d8d | 2469 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 | 2470 | } |
76a66253 JM |
2471 | } |
2472 | ||
636aa200 | 2473 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2474 | { |
76db3ba4 AJ |
2475 | if (rA(ctx->opcode) == 0) { |
2476 | #if defined(TARGET_PPC64) | |
2477 | if (!ctx->sf_mode) { | |
2478 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2479 | } else | |
2480 | #endif | |
e2be8d8d | 2481 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 | 2482 | } else { |
e2be8d8d | 2483 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 AJ |
2484 | #if defined(TARGET_PPC64) |
2485 | if (!ctx->sf_mode) { | |
2486 | tcg_gen_ext32u_tl(EA, EA); | |
2487 | } | |
2488 | #endif | |
2489 | } | |
76a66253 JM |
2490 | } |
2491 | ||
636aa200 | 2492 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2493 | { |
76db3ba4 | 2494 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2495 | tcg_gen_movi_tl(EA, 0); |
76db3ba4 AJ |
2496 | } else { |
2497 | #if defined(TARGET_PPC64) | |
2498 | if (!ctx->sf_mode) { | |
2499 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2500 | } else | |
2501 | #endif | |
2502 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2503 | } | |
2504 | } | |
2505 | ||
636aa200 BS |
2506 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2507 | target_long val) | |
76db3ba4 AJ |
2508 | { |
2509 | tcg_gen_addi_tl(ret, arg1, val); | |
2510 | #if defined(TARGET_PPC64) | |
2511 | if (!ctx->sf_mode) { | |
2512 | tcg_gen_ext32u_tl(ret, ret); | |
2513 | } | |
2514 | #endif | |
76a66253 JM |
2515 | } |
2516 | ||
636aa200 | 2517 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 AJ |
2518 | { |
2519 | int l1 = gen_new_label(); | |
2520 | TCGv t0 = tcg_temp_new(); | |
2521 | TCGv_i32 t1, t2; | |
2522 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2523 | gen_update_nip(ctx, ctx->nip - 4); | |
2524 | tcg_gen_andi_tl(t0, EA, mask); | |
2525 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2526 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2527 | t2 = tcg_const_i32(0); | |
e5f17ac6 | 2528 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2529 | tcg_temp_free_i32(t1); |
2530 | tcg_temp_free_i32(t2); | |
2531 | gen_set_label(l1); | |
2532 | tcg_temp_free(t0); | |
2533 | } | |
2534 | ||
7863667f | 2535 | /*** Integer load ***/ |
636aa200 | 2536 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2537 | { |
2538 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2539 | } | |
2540 | ||
636aa200 | 2541 | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2542 | { |
2543 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); | |
2544 | } | |
2545 | ||
636aa200 | 2546 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2547 | { |
2548 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); | |
2549 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2550 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2551 | } |
b61f2753 AJ |
2552 | } |
2553 | ||
636aa200 | 2554 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2555 | { |
76db3ba4 | 2556 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2557 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
fa3966a3 | 2558 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2559 | tcg_gen_ext16s_tl(arg1, arg1); |
76db3ba4 AJ |
2560 | } else { |
2561 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); | |
2562 | } | |
b61f2753 AJ |
2563 | } |
2564 | ||
636aa200 | 2565 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2566 | { |
76db3ba4 AJ |
2567 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2568 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2569 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2570 | } |
b61f2753 AJ |
2571 | } |
2572 | ||
76db3ba4 | 2573 | #if defined(TARGET_PPC64) |
636aa200 | 2574 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2575 | { |
a457e7ee | 2576 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2577 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
fa3966a3 AJ |
2578 | tcg_gen_bswap32_tl(arg1, arg1); |
2579 | tcg_gen_ext32s_tl(arg1, arg1); | |
b61f2753 | 2580 | } else |
76db3ba4 | 2581 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
b61f2753 | 2582 | } |
76db3ba4 | 2583 | #endif |
b61f2753 | 2584 | |
636aa200 | 2585 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2586 | { |
76db3ba4 AJ |
2587 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2588 | if (unlikely(ctx->le_mode)) { | |
66896cb8 | 2589 | tcg_gen_bswap64_i64(arg1, arg1); |
76db3ba4 | 2590 | } |
b61f2753 AJ |
2591 | } |
2592 | ||
636aa200 | 2593 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2594 | { |
76db3ba4 | 2595 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2596 | } |
2597 | ||
636aa200 | 2598 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2599 | { |
76db3ba4 | 2600 | if (unlikely(ctx->le_mode)) { |
76db3ba4 AJ |
2601 | TCGv t0 = tcg_temp_new(); |
2602 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2603 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2604 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2605 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2606 | } else { |
2607 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2608 | } | |
b61f2753 AJ |
2609 | } |
2610 | ||
636aa200 | 2611 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2612 | { |
76db3ba4 | 2613 | if (unlikely(ctx->le_mode)) { |
fa3966a3 AJ |
2614 | TCGv t0 = tcg_temp_new(); |
2615 | tcg_gen_ext32u_tl(t0, arg1); | |
2616 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2617 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2618 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2619 | } else { |
2620 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2621 | } | |
b61f2753 AJ |
2622 | } |
2623 | ||
636aa200 | 2624 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2625 | { |
76db3ba4 | 2626 | if (unlikely(ctx->le_mode)) { |
a7812ae4 | 2627 | TCGv_i64 t0 = tcg_temp_new_i64(); |
66896cb8 | 2628 | tcg_gen_bswap64_i64(t0, arg1); |
76db3ba4 | 2629 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
a7812ae4 | 2630 | tcg_temp_free_i64(t0); |
b61f2753 | 2631 | } else |
76db3ba4 | 2632 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2633 | } |
2634 | ||
0c8aacd4 | 2635 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2636 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2637 | { \ |
76db3ba4 AJ |
2638 | TCGv EA; \ |
2639 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2640 | EA = tcg_temp_new(); \ | |
2641 | gen_addr_imm_index(ctx, EA, 0); \ | |
2642 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2643 | tcg_temp_free(EA); \ |
79aceca5 FB |
2644 | } |
2645 | ||
0c8aacd4 | 2646 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2647 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2648 | { \ |
b61f2753 | 2649 | TCGv EA; \ |
76a66253 JM |
2650 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2651 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2652 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2653 | return; \ |
9a64fbe4 | 2654 | } \ |
76db3ba4 | 2655 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2656 | EA = tcg_temp_new(); \ |
9d53c753 | 2657 | if (type == PPC_64B) \ |
76db3ba4 | 2658 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2659 | else \ |
76db3ba4 AJ |
2660 | gen_addr_imm_index(ctx, EA, 0); \ |
2661 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2662 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2663 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2664 | } |
2665 | ||
0c8aacd4 | 2666 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2667 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2668 | { \ |
b61f2753 | 2669 | TCGv EA; \ |
76a66253 JM |
2670 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2671 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2672 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2673 | return; \ |
9a64fbe4 | 2674 | } \ |
76db3ba4 | 2675 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2676 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2677 | gen_addr_reg_index(ctx, EA); \ |
2678 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2679 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2680 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2681 | } |
2682 | ||
cd6e9320 | 2683 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
99e300ef | 2684 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2685 | { \ |
76db3ba4 AJ |
2686 | TCGv EA; \ |
2687 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2688 | EA = tcg_temp_new(); \ | |
2689 | gen_addr_reg_index(ctx, EA); \ | |
2690 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2691 | tcg_temp_free(EA); \ |
79aceca5 | 2692 | } |
cd6e9320 TH |
2693 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2694 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2695 | |
0c8aacd4 AJ |
2696 | #define GEN_LDS(name, ldop, op, type) \ |
2697 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2698 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2699 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2700 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2701 | |
2702 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2703 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2704 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2705 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2706 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2707 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2708 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2709 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2710 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2711 | /* lwaux */ |
0c8aacd4 | 2712 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2713 | /* lwax */ |
0c8aacd4 | 2714 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2715 | /* ldux */ |
0c8aacd4 | 2716 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2717 | /* ldx */ |
0c8aacd4 | 2718 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2719 | |
2720 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2721 | { |
b61f2753 | 2722 | TCGv EA; |
d9bce9d9 JM |
2723 | if (Rc(ctx->opcode)) { |
2724 | if (unlikely(rA(ctx->opcode) == 0 || | |
2725 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2726 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2727 | return; |
2728 | } | |
2729 | } | |
76db3ba4 | 2730 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2731 | EA = tcg_temp_new(); |
76db3ba4 | 2732 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2733 | if (ctx->opcode & 0x02) { |
2734 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2735 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2736 | } else { |
2737 | /* ld - ldu */ | |
76db3ba4 | 2738 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2739 | } |
d9bce9d9 | 2740 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2741 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2742 | tcg_temp_free(EA); | |
d9bce9d9 | 2743 | } |
99e300ef | 2744 | |
54623277 | 2745 | /* lq */ |
99e300ef | 2746 | static void gen_lq(DisasContext *ctx) |
be147d08 JM |
2747 | { |
2748 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2749 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2750 | #else |
2751 | int ra, rd; | |
b61f2753 | 2752 | TCGv EA; |
be147d08 JM |
2753 | |
2754 | /* Restore CPU state */ | |
76db3ba4 | 2755 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2756 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2757 | return; |
2758 | } | |
2759 | ra = rA(ctx->opcode); | |
2760 | rd = rD(ctx->opcode); | |
2761 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2762 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2763 | return; |
2764 | } | |
76db3ba4 | 2765 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2766 | /* Little-endian mode is not handled */ |
e06fcd75 | 2767 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2768 | return; |
2769 | } | |
76db3ba4 | 2770 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2771 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2772 | gen_addr_imm_index(ctx, EA, 0x0F); |
2773 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2774 | gen_addr_add(ctx, EA, EA, 8); | |
2775 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
b61f2753 | 2776 | tcg_temp_free(EA); |
be147d08 JM |
2777 | #endif |
2778 | } | |
d9bce9d9 | 2779 | #endif |
79aceca5 FB |
2780 | |
2781 | /*** Integer store ***/ | |
0c8aacd4 | 2782 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2783 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2784 | { \ |
76db3ba4 AJ |
2785 | TCGv EA; \ |
2786 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2787 | EA = tcg_temp_new(); \ | |
2788 | gen_addr_imm_index(ctx, EA, 0); \ | |
2789 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2790 | tcg_temp_free(EA); \ |
79aceca5 FB |
2791 | } |
2792 | ||
0c8aacd4 | 2793 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2794 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2795 | { \ |
b61f2753 | 2796 | TCGv EA; \ |
76a66253 | 2797 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2798 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2799 | return; \ |
9a64fbe4 | 2800 | } \ |
76db3ba4 | 2801 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2802 | EA = tcg_temp_new(); \ |
9d53c753 | 2803 | if (type == PPC_64B) \ |
76db3ba4 | 2804 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2805 | else \ |
76db3ba4 AJ |
2806 | gen_addr_imm_index(ctx, EA, 0); \ |
2807 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2808 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2809 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2810 | } |
2811 | ||
0c8aacd4 | 2812 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2813 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2814 | { \ |
b61f2753 | 2815 | TCGv EA; \ |
76a66253 | 2816 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2817 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2818 | return; \ |
9a64fbe4 | 2819 | } \ |
76db3ba4 | 2820 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2821 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2822 | gen_addr_reg_index(ctx, EA); \ |
2823 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2824 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2825 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2826 | } |
2827 | ||
cd6e9320 TH |
2828 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
2829 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 2830 | { \ |
76db3ba4 AJ |
2831 | TCGv EA; \ |
2832 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2833 | EA = tcg_temp_new(); \ | |
2834 | gen_addr_reg_index(ctx, EA); \ | |
2835 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2836 | tcg_temp_free(EA); \ |
79aceca5 | 2837 | } |
cd6e9320 TH |
2838 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
2839 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2840 | |
0c8aacd4 AJ |
2841 | #define GEN_STS(name, stop, op, type) \ |
2842 | GEN_ST(name, stop, op | 0x20, type); \ | |
2843 | GEN_STU(name, stop, op | 0x21, type); \ | |
2844 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2845 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2846 | |
2847 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2848 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2849 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2850 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2851 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2852 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2853 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
2854 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2855 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
2856 | |
2857 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2858 | { |
be147d08 | 2859 | int rs; |
b61f2753 | 2860 | TCGv EA; |
be147d08 JM |
2861 | |
2862 | rs = rS(ctx->opcode); | |
2863 | if ((ctx->opcode & 0x3) == 0x2) { | |
2864 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2865 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2866 | #else |
2867 | /* stq */ | |
76db3ba4 | 2868 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2869 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2870 | return; |
2871 | } | |
2872 | if (unlikely(rs & 1)) { | |
e06fcd75 | 2873 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2874 | return; |
2875 | } | |
76db3ba4 | 2876 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2877 | /* Little-endian mode is not handled */ |
e06fcd75 | 2878 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2879 | return; |
2880 | } | |
76db3ba4 | 2881 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2882 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2883 | gen_addr_imm_index(ctx, EA, 0x03); |
2884 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
2885 | gen_addr_add(ctx, EA, EA, 8); | |
2886 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
b61f2753 | 2887 | tcg_temp_free(EA); |
be147d08 JM |
2888 | #endif |
2889 | } else { | |
2890 | /* std / stdu */ | |
2891 | if (Rc(ctx->opcode)) { | |
2892 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2893 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2894 | return; |
2895 | } | |
2896 | } | |
76db3ba4 | 2897 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2898 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2899 | gen_addr_imm_index(ctx, EA, 0x03); |
2900 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 2901 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2902 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2903 | tcg_temp_free(EA); | |
d9bce9d9 | 2904 | } |
d9bce9d9 JM |
2905 | } |
2906 | #endif | |
79aceca5 FB |
2907 | /*** Integer load and store with byte reverse ***/ |
2908 | /* lhbrx */ | |
86178a57 | 2909 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2910 | { |
76db3ba4 AJ |
2911 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2912 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2913 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2914 | } |
b61f2753 | 2915 | } |
0c8aacd4 | 2916 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2917 | |
79aceca5 | 2918 | /* lwbrx */ |
86178a57 | 2919 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2920 | { |
76db3ba4 AJ |
2921 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2922 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 2923 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2924 | } |
b61f2753 | 2925 | } |
0c8aacd4 | 2926 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2927 | |
cd6e9320 TH |
2928 | #if defined(TARGET_PPC64) |
2929 | /* ldbrx */ | |
2930 | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2931 | { | |
2932 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); | |
2933 | if (likely(!ctx->le_mode)) { | |
2934 | tcg_gen_bswap64_tl(arg1, arg1); | |
2935 | } | |
2936 | } | |
2937 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); | |
2938 | #endif /* TARGET_PPC64 */ | |
2939 | ||
79aceca5 | 2940 | /* sthbrx */ |
86178a57 | 2941 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2942 | { |
76db3ba4 | 2943 | if (likely(!ctx->le_mode)) { |
76db3ba4 AJ |
2944 | TCGv t0 = tcg_temp_new(); |
2945 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2946 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2947 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2948 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2949 | } else { |
2950 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2951 | } | |
b61f2753 | 2952 | } |
0c8aacd4 | 2953 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 2954 | |
79aceca5 | 2955 | /* stwbrx */ |
86178a57 | 2956 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2957 | { |
76db3ba4 | 2958 | if (likely(!ctx->le_mode)) { |
fa3966a3 AJ |
2959 | TCGv t0 = tcg_temp_new(); |
2960 | tcg_gen_ext32u_tl(t0, arg1); | |
2961 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2962 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2963 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2964 | } else { |
2965 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2966 | } | |
b61f2753 | 2967 | } |
0c8aacd4 | 2968 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 | 2969 | |
cd6e9320 TH |
2970 | #if defined(TARGET_PPC64) |
2971 | /* stdbrx */ | |
2972 | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2973 | { | |
2974 | if (likely(!ctx->le_mode)) { | |
2975 | TCGv t0 = tcg_temp_new(); | |
2976 | tcg_gen_bswap64_tl(t0, arg1); | |
2977 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); | |
2978 | tcg_temp_free(t0); | |
2979 | } else { | |
2980 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); | |
2981 | } | |
2982 | } | |
2983 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); | |
2984 | #endif /* TARGET_PPC64 */ | |
2985 | ||
79aceca5 | 2986 | /*** Integer load and store multiple ***/ |
99e300ef | 2987 | |
54623277 | 2988 | /* lmw */ |
99e300ef | 2989 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2990 | { |
76db3ba4 AJ |
2991 | TCGv t0; |
2992 | TCGv_i32 t1; | |
2993 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 2994 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 2995 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
2996 | t0 = tcg_temp_new(); |
2997 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2998 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2999 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
3000 | tcg_temp_free(t0); |
3001 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3002 | } |
3003 | ||
3004 | /* stmw */ | |
99e300ef | 3005 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 3006 | { |
76db3ba4 AJ |
3007 | TCGv t0; |
3008 | TCGv_i32 t1; | |
3009 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3010 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3011 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3012 | t0 = tcg_temp_new(); |
3013 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
3014 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 3015 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
3016 | tcg_temp_free(t0); |
3017 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3018 | } |
3019 | ||
3020 | /*** Integer load and store strings ***/ | |
54623277 | 3021 | |
79aceca5 | 3022 | /* lswi */ |
3fc6c082 | 3023 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
3024 | * rA is in the range of registers to be loaded. |
3025 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
3026 | * For now, I'll follow the spec... | |
3027 | */ | |
99e300ef | 3028 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 3029 | { |
dfbc799d AJ |
3030 | TCGv t0; |
3031 | TCGv_i32 t1, t2; | |
79aceca5 FB |
3032 | int nb = NB(ctx->opcode); |
3033 | int start = rD(ctx->opcode); | |
9a64fbe4 | 3034 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3035 | int nr; |
3036 | ||
3037 | if (nb == 0) | |
3038 | nb = 32; | |
3039 | nr = nb / 4; | |
76a66253 JM |
3040 | if (unlikely(((start + nr) > 32 && |
3041 | start <= ra && (start + nr - 32) > ra) || | |
3042 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 3043 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3044 | return; |
297d8e62 | 3045 | } |
76db3ba4 | 3046 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 3047 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3048 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 3049 | t0 = tcg_temp_new(); |
76db3ba4 | 3050 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
3051 | t1 = tcg_const_i32(nb); |
3052 | t2 = tcg_const_i32(start); | |
2f5a189c | 3053 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3054 | tcg_temp_free(t0); |
3055 | tcg_temp_free_i32(t1); | |
3056 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3057 | } |
3058 | ||
3059 | /* lswx */ | |
99e300ef | 3060 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3061 | { |
76db3ba4 AJ |
3062 | TCGv t0; |
3063 | TCGv_i32 t1, t2, t3; | |
3064 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3065 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3066 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3067 | t0 = tcg_temp_new(); |
3068 | gen_addr_reg_index(ctx, t0); | |
3069 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3070 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3071 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 3072 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
3073 | tcg_temp_free(t0); |
3074 | tcg_temp_free_i32(t1); | |
3075 | tcg_temp_free_i32(t2); | |
3076 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3077 | } |
3078 | ||
3079 | /* stswi */ | |
99e300ef | 3080 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3081 | { |
76db3ba4 AJ |
3082 | TCGv t0; |
3083 | TCGv_i32 t1, t2; | |
4b3686fa | 3084 | int nb = NB(ctx->opcode); |
76db3ba4 | 3085 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 3086 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3087 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3088 | t0 = tcg_temp_new(); |
3089 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3090 | if (nb == 0) |
3091 | nb = 32; | |
dfbc799d | 3092 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3093 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3094 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3095 | tcg_temp_free(t0); |
3096 | tcg_temp_free_i32(t1); | |
3097 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3098 | } |
3099 | ||
3100 | /* stswx */ | |
99e300ef | 3101 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3102 | { |
76db3ba4 AJ |
3103 | TCGv t0; |
3104 | TCGv_i32 t1, t2; | |
3105 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3106 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3107 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3108 | t0 = tcg_temp_new(); |
3109 | gen_addr_reg_index(ctx, t0); | |
3110 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3111 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3112 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3113 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3114 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3115 | tcg_temp_free(t0); |
3116 | tcg_temp_free_i32(t1); | |
3117 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3118 | } |
3119 | ||
3120 | /*** Memory synchronisation ***/ | |
3121 | /* eieio */ | |
99e300ef | 3122 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3123 | { |
79aceca5 FB |
3124 | } |
3125 | ||
3126 | /* isync */ | |
99e300ef | 3127 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3128 | { |
e06fcd75 | 3129 | gen_stop_exception(ctx); |
79aceca5 FB |
3130 | } |
3131 | ||
111bfab3 | 3132 | /* lwarx */ |
99e300ef | 3133 | static void gen_lwarx(DisasContext *ctx) |
79aceca5 | 3134 | { |
76db3ba4 | 3135 | TCGv t0; |
18b21a2f | 3136 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3137 | gen_set_access_type(ctx, ACCESS_RES); |
3138 | t0 = tcg_temp_local_new(); | |
3139 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3140 | gen_check_align(ctx, t0, 0x03); |
18b21a2f | 3141 | gen_qemu_ld32u(ctx, gpr, t0); |
cf360a32 | 3142 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3143 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3144 | tcg_temp_free(t0); |
79aceca5 FB |
3145 | } |
3146 | ||
4425265b NF |
3147 | #if defined(CONFIG_USER_ONLY) |
3148 | static void gen_conditional_store (DisasContext *ctx, TCGv EA, | |
3149 | int reg, int size) | |
3150 | { | |
3151 | TCGv t0 = tcg_temp_new(); | |
3152 | uint32_t save_exception = ctx->exception; | |
3153 | ||
1328c2bf | 3154 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
4425265b | 3155 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
1328c2bf | 3156 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b NF |
3157 | tcg_temp_free(t0); |
3158 | gen_update_nip(ctx, ctx->nip-4); | |
3159 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3160 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3161 | ctx->exception = save_exception; | |
3162 | } | |
3163 | #endif | |
3164 | ||
79aceca5 | 3165 | /* stwcx. */ |
e8eaa2c0 | 3166 | static void gen_stwcx_(DisasContext *ctx) |
79aceca5 | 3167 | { |
76db3ba4 AJ |
3168 | TCGv t0; |
3169 | gen_set_access_type(ctx, ACCESS_RES); | |
3170 | t0 = tcg_temp_local_new(); | |
3171 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3172 | gen_check_align(ctx, t0, 0x03); |
4425265b NF |
3173 | #if defined(CONFIG_USER_ONLY) |
3174 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); | |
3175 | #else | |
3176 | { | |
3177 | int l1; | |
3178 | ||
3179 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
3180 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
3181 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
3182 | l1 = gen_new_label(); | |
3183 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3184 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3185 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3186 | gen_set_label(l1); | |
3187 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3188 | } | |
3189 | #endif | |
cf360a32 | 3190 | tcg_temp_free(t0); |
79aceca5 FB |
3191 | } |
3192 | ||
426613db | 3193 | #if defined(TARGET_PPC64) |
426613db | 3194 | /* ldarx */ |
99e300ef | 3195 | static void gen_ldarx(DisasContext *ctx) |
426613db | 3196 | { |
76db3ba4 | 3197 | TCGv t0; |
18b21a2f | 3198 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
76db3ba4 AJ |
3199 | gen_set_access_type(ctx, ACCESS_RES); |
3200 | t0 = tcg_temp_local_new(); | |
3201 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3202 | gen_check_align(ctx, t0, 0x07); |
18b21a2f | 3203 | gen_qemu_ld64(ctx, gpr, t0); |
cf360a32 | 3204 | tcg_gen_mov_tl(cpu_reserve, t0); |
1328c2bf | 3205 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); |
cf360a32 | 3206 | tcg_temp_free(t0); |
426613db JM |
3207 | } |
3208 | ||
3209 | /* stdcx. */ | |
e8eaa2c0 | 3210 | static void gen_stdcx_(DisasContext *ctx) |
426613db | 3211 | { |
76db3ba4 AJ |
3212 | TCGv t0; |
3213 | gen_set_access_type(ctx, ACCESS_RES); | |
3214 | t0 = tcg_temp_local_new(); | |
3215 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3216 | gen_check_align(ctx, t0, 0x07); |
4425265b NF |
3217 | #if defined(CONFIG_USER_ONLY) |
3218 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); | |
3219 | #else | |
3220 | { | |
3221 | int l1; | |
3222 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
3223 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
3224 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
3225 | l1 = gen_new_label(); | |
3226 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); | |
3227 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3228 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); | |
3229 | gen_set_label(l1); | |
3230 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3231 | } | |
3232 | #endif | |
cf360a32 | 3233 | tcg_temp_free(t0); |
426613db JM |
3234 | } |
3235 | #endif /* defined(TARGET_PPC64) */ | |
3236 | ||
79aceca5 | 3237 | /* sync */ |
99e300ef | 3238 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3239 | { |
79aceca5 FB |
3240 | } |
3241 | ||
0db1b20e | 3242 | /* wait */ |
99e300ef | 3243 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3244 | { |
931ff272 | 3245 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1328c2bf | 3246 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted)); |
931ff272 | 3247 | tcg_temp_free_i32(t0); |
0db1b20e | 3248 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3249 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3250 | } |
3251 | ||
79aceca5 | 3252 | /*** Floating-point load ***/ |
a0d7d5a7 | 3253 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3254 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3255 | { \ |
a0d7d5a7 | 3256 | TCGv EA; \ |
76a66253 | 3257 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3258 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3259 | return; \ |
3260 | } \ | |
76db3ba4 | 3261 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3262 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3263 | gen_addr_imm_index(ctx, EA, 0); \ |
3264 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3265 | tcg_temp_free(EA); \ |
79aceca5 FB |
3266 | } |
3267 | ||
a0d7d5a7 | 3268 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3269 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3270 | { \ |
a0d7d5a7 | 3271 | TCGv EA; \ |
76a66253 | 3272 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3273 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3274 | return; \ |
3275 | } \ | |
76a66253 | 3276 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3277 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3278 | return; \ |
9a64fbe4 | 3279 | } \ |
76db3ba4 | 3280 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3281 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3282 | gen_addr_imm_index(ctx, EA, 0); \ |
3283 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3284 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3285 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3286 | } |
3287 | ||
a0d7d5a7 | 3288 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3289 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3290 | { \ |
a0d7d5a7 | 3291 | TCGv EA; \ |
76a66253 | 3292 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3293 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3294 | return; \ |
3295 | } \ | |
76a66253 | 3296 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3297 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3298 | return; \ |
9a64fbe4 | 3299 | } \ |
76db3ba4 | 3300 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3301 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3302 | gen_addr_reg_index(ctx, EA); \ |
3303 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3304 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3305 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3306 | } |
3307 | ||
a0d7d5a7 | 3308 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3309 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3310 | { \ |
a0d7d5a7 | 3311 | TCGv EA; \ |
76a66253 | 3312 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3313 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3314 | return; \ |
3315 | } \ | |
76db3ba4 | 3316 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3317 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3318 | gen_addr_reg_index(ctx, EA); \ |
3319 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3320 | tcg_temp_free(EA); \ |
79aceca5 FB |
3321 | } |
3322 | ||
a0d7d5a7 AJ |
3323 | #define GEN_LDFS(name, ldop, op, type) \ |
3324 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3325 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3326 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3327 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3328 | ||
636aa200 | 3329 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3330 | { |
3331 | TCGv t0 = tcg_temp_new(); | |
3332 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3333 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3334 | tcg_gen_trunc_tl_i32(t1, t0); |
3335 | tcg_temp_free(t0); | |
8e703949 | 3336 | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
a0d7d5a7 AJ |
3337 | tcg_temp_free_i32(t1); |
3338 | } | |
79aceca5 | 3339 | |
a0d7d5a7 AJ |
3340 | /* lfd lfdu lfdux lfdx */ |
3341 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3342 | /* lfs lfsu lfsux lfsx */ | |
3343 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 FB |
3344 | |
3345 | /*** Floating-point store ***/ | |
a0d7d5a7 | 3346 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3347 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3348 | { \ |
a0d7d5a7 | 3349 | TCGv EA; \ |
76a66253 | 3350 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3351 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3352 | return; \ |
3353 | } \ | |
76db3ba4 | 3354 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3355 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3356 | gen_addr_imm_index(ctx, EA, 0); \ |
3357 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3358 | tcg_temp_free(EA); \ |
79aceca5 FB |
3359 | } |
3360 | ||
a0d7d5a7 | 3361 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3362 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3363 | { \ |
a0d7d5a7 | 3364 | TCGv EA; \ |
76a66253 | 3365 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3366 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3367 | return; \ |
3368 | } \ | |
76a66253 | 3369 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3370 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3371 | return; \ |
9a64fbe4 | 3372 | } \ |
76db3ba4 | 3373 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3374 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3375 | gen_addr_imm_index(ctx, EA, 0); \ |
3376 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3377 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3378 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3379 | } |
3380 | ||
a0d7d5a7 | 3381 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3382 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3383 | { \ |
a0d7d5a7 | 3384 | TCGv EA; \ |
76a66253 | 3385 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3386 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3387 | return; \ |
3388 | } \ | |
76a66253 | 3389 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3390 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3391 | return; \ |
9a64fbe4 | 3392 | } \ |
76db3ba4 | 3393 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3394 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3395 | gen_addr_reg_index(ctx, EA); \ |
3396 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3397 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3398 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3399 | } |
3400 | ||
a0d7d5a7 | 3401 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3402 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3403 | { \ |
a0d7d5a7 | 3404 | TCGv EA; \ |
76a66253 | 3405 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3406 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3407 | return; \ |
3408 | } \ | |
76db3ba4 | 3409 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3410 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3411 | gen_addr_reg_index(ctx, EA); \ |
3412 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3413 | tcg_temp_free(EA); \ |
79aceca5 FB |
3414 | } |
3415 | ||
a0d7d5a7 AJ |
3416 | #define GEN_STFS(name, stop, op, type) \ |
3417 | GEN_STF(name, stop, op | 0x20, type); \ | |
3418 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3419 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3420 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3421 | ||
636aa200 | 3422 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3423 | { |
3424 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3425 | TCGv t1 = tcg_temp_new(); | |
8e703949 | 3426 | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
a0d7d5a7 AJ |
3427 | tcg_gen_extu_i32_tl(t1, t0); |
3428 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3429 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3430 | tcg_temp_free(t1); |
3431 | } | |
79aceca5 FB |
3432 | |
3433 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3434 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3435 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3436 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 FB |
3437 | |
3438 | /* Optional: */ | |
636aa200 | 3439 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3440 | { |
3441 | TCGv t0 = tcg_temp_new(); | |
3442 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3443 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3444 | tcg_temp_free(t0); |
3445 | } | |
79aceca5 | 3446 | /* stfiwx */ |
a0d7d5a7 | 3447 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 | 3448 | |
697ab892 DG |
3449 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3450 | { | |
3451 | #if defined(TARGET_PPC64) | |
3452 | if (ctx->has_cfar) | |
3453 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3454 | #endif | |
3455 | } | |
3456 | ||
79aceca5 | 3457 | /*** Branch ***/ |
636aa200 | 3458 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 FB |
3459 | { |
3460 | TranslationBlock *tb; | |
3461 | tb = ctx->tb; | |
a2ffb812 AJ |
3462 | #if defined(TARGET_PPC64) |
3463 | if (!ctx->sf_mode) | |
3464 | dest = (uint32_t) dest; | |
3465 | #endif | |
57fec1fe | 3466 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3467 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3468 | tcg_gen_goto_tb(n); |
a2ffb812 | 3469 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
4b4a72e5 | 3470 | tcg_gen_exit_tb((tcg_target_long)tb + n); |
c1942362 | 3471 | } else { |
a2ffb812 | 3472 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3473 | if (unlikely(ctx->singlestep_enabled)) { |
3474 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3475 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
8cbcb4fa AJ |
3476 | ctx->exception == POWERPC_EXCP_BRANCH) { |
3477 | target_ulong tmp = ctx->nip; | |
3478 | ctx->nip = dest; | |
e06fcd75 | 3479 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3480 | ctx->nip = tmp; |
3481 | } | |
3482 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3483 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3484 | } |
3485 | } | |
57fec1fe | 3486 | tcg_gen_exit_tb(0); |
c1942362 | 3487 | } |
c53be334 FB |
3488 | } |
3489 | ||
636aa200 | 3490 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f JM |
3491 | { |
3492 | #if defined(TARGET_PPC64) | |
a2ffb812 AJ |
3493 | if (ctx->sf_mode == 0) |
3494 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); | |
e1833e1f JM |
3495 | else |
3496 | #endif | |
a2ffb812 | 3497 | tcg_gen_movi_tl(cpu_lr, nip); |
e1833e1f JM |
3498 | } |
3499 | ||
79aceca5 | 3500 | /* b ba bl bla */ |
99e300ef | 3501 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3502 | { |
76a66253 | 3503 | target_ulong li, target; |
38a64f9d | 3504 | |
8cbcb4fa | 3505 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3506 | /* sign extend LI */ |
76a66253 | 3507 | #if defined(TARGET_PPC64) |
d9bce9d9 JM |
3508 | if (ctx->sf_mode) |
3509 | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; | |
3510 | else | |
76a66253 | 3511 | #endif |
d9bce9d9 | 3512 | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
76a66253 | 3513 | if (likely(AA(ctx->opcode) == 0)) |
046d6672 | 3514 | target = ctx->nip + li - 4; |
79aceca5 | 3515 | else |
9a64fbe4 | 3516 | target = li; |
e1833e1f JM |
3517 | if (LK(ctx->opcode)) |
3518 | gen_setlr(ctx, ctx->nip); | |
697ab892 | 3519 | gen_update_cfar(ctx, ctx->nip); |
c1942362 | 3520 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3521 | } |
3522 | ||
e98a6e40 FB |
3523 | #define BCOND_IM 0 |
3524 | #define BCOND_LR 1 | |
3525 | #define BCOND_CTR 2 | |
3526 | ||
636aa200 | 3527 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3528 | { |
d9bce9d9 | 3529 | uint32_t bo = BO(ctx->opcode); |
05f92404 | 3530 | int l1; |
a2ffb812 | 3531 | TCGv target; |
e98a6e40 | 3532 | |
8cbcb4fa | 3533 | ctx->exception = POWERPC_EXCP_BRANCH; |
a2ffb812 | 3534 | if (type == BCOND_LR || type == BCOND_CTR) { |
a7812ae4 | 3535 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3536 | if (type == BCOND_CTR) |
3537 | tcg_gen_mov_tl(target, cpu_ctr); | |
3538 | else | |
3539 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3540 | } else { |
3541 | TCGV_UNUSED(target); | |
e98a6e40 | 3542 | } |
e1833e1f JM |
3543 | if (LK(ctx->opcode)) |
3544 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3545 | l1 = gen_new_label(); |
3546 | if ((bo & 0x4) == 0) { | |
3547 | /* Decrement and test CTR */ | |
a7812ae4 | 3548 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3549 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3550 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3551 | return; |
3552 | } | |
3553 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
d9bce9d9 | 3554 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3555 | if (!ctx->sf_mode) |
3556 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3557 | else | |
d9bce9d9 | 3558 | #endif |
a2ffb812 AJ |
3559 | tcg_gen_mov_tl(temp, cpu_ctr); |
3560 | if (bo & 0x2) { | |
3561 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3562 | } else { | |
3563 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3564 | } |
a7812ae4 | 3565 | tcg_temp_free(temp); |
a2ffb812 AJ |
3566 | } |
3567 | if ((bo & 0x10) == 0) { | |
3568 | /* Test CR */ | |
3569 | uint32_t bi = BI(ctx->opcode); | |
3570 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3571 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3572 | |
d9bce9d9 | 3573 | if (bo & 0x8) { |
a2ffb812 AJ |
3574 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3575 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3576 | } else { |
a2ffb812 AJ |
3577 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3578 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3579 | } |
a7812ae4 | 3580 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3581 | } |
697ab892 | 3582 | gen_update_cfar(ctx, ctx->nip); |
e98a6e40 | 3583 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3584 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3585 | if (likely(AA(ctx->opcode) == 0)) { | |
3586 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3587 | } else { | |
3588 | gen_goto_tb(ctx, 0, li); | |
3589 | } | |
c53be334 | 3590 | gen_set_label(l1); |
c1942362 | 3591 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3592 | } else { |
d9bce9d9 | 3593 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3594 | if (!(ctx->sf_mode)) |
3595 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); | |
3596 | else | |
3597 | #endif | |
3598 | tcg_gen_andi_tl(cpu_nip, target, ~3); | |
3599 | tcg_gen_exit_tb(0); | |
3600 | gen_set_label(l1); | |
3601 | #if defined(TARGET_PPC64) | |
3602 | if (!(ctx->sf_mode)) | |
3603 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); | |
d9bce9d9 JM |
3604 | else |
3605 | #endif | |
a2ffb812 | 3606 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
57fec1fe | 3607 | tcg_gen_exit_tb(0); |
08e46e54 | 3608 | } |
e98a6e40 FB |
3609 | } |
3610 | ||
99e300ef | 3611 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3612 | { |
e98a6e40 FB |
3613 | gen_bcond(ctx, BCOND_IM); |
3614 | } | |
3615 | ||
99e300ef | 3616 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3617 | { |
e98a6e40 FB |
3618 | gen_bcond(ctx, BCOND_CTR); |
3619 | } | |
3620 | ||
99e300ef | 3621 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3622 | { |
e98a6e40 FB |
3623 | gen_bcond(ctx, BCOND_LR); |
3624 | } | |
79aceca5 FB |
3625 | |
3626 | /*** Condition register logical ***/ | |
e1571908 | 3627 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3628 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3629 | { \ |
fc0d441e JM |
3630 | uint8_t bitmask; \ |
3631 | int sh; \ | |
a7812ae4 | 3632 | TCGv_i32 t0, t1; \ |
fc0d441e | 3633 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3634 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3635 | if (sh > 0) \ |
fea0c503 | 3636 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3637 | else if (sh < 0) \ |
fea0c503 | 3638 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3639 | else \ |
fea0c503 | 3640 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3641 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3642 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3643 | if (sh > 0) \ | |
fea0c503 | 3644 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3645 | else if (sh < 0) \ |
fea0c503 | 3646 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3647 | else \ |
fea0c503 AJ |
3648 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3649 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3650 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3651 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3652 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3653 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3654 | tcg_temp_free_i32(t0); \ |
3655 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3656 | } |
3657 | ||
3658 | /* crand */ | |
e1571908 | 3659 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3660 | /* crandc */ |
e1571908 | 3661 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3662 | /* creqv */ |
e1571908 | 3663 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3664 | /* crnand */ |
e1571908 | 3665 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3666 | /* crnor */ |
e1571908 | 3667 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3668 | /* cror */ |
e1571908 | 3669 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3670 | /* crorc */ |
e1571908 | 3671 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3672 | /* crxor */ |
e1571908 | 3673 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3674 | |
54623277 | 3675 | /* mcrf */ |
99e300ef | 3676 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3677 | { |
47e4661c | 3678 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3679 | } |
3680 | ||
3681 | /*** System linkage ***/ | |
99e300ef | 3682 | |
54623277 | 3683 | /* rfi (mem_idx only) */ |
99e300ef | 3684 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3685 | { |
9a64fbe4 | 3686 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3687 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3688 | #else |
3689 | /* Restore CPU state */ | |
76db3ba4 | 3690 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3691 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3692 | return; |
9a64fbe4 | 3693 | } |
697ab892 | 3694 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3695 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3696 | gen_sync_exception(ctx); |
9a64fbe4 | 3697 | #endif |
79aceca5 FB |
3698 | } |
3699 | ||
426613db | 3700 | #if defined(TARGET_PPC64) |
99e300ef | 3701 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3702 | { |
3703 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3704 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3705 | #else |
3706 | /* Restore CPU state */ | |
76db3ba4 | 3707 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3708 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3709 | return; |
3710 | } | |
697ab892 | 3711 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3712 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3713 | gen_sync_exception(ctx); |
426613db JM |
3714 | #endif |
3715 | } | |
426613db | 3716 | |
99e300ef | 3717 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3718 | { |
3719 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3720 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3721 | #else |
3722 | /* Restore CPU state */ | |
76db3ba4 | 3723 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 3724 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3725 | return; |
3726 | } | |
e5f17ac6 | 3727 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3728 | gen_sync_exception(ctx); |
be147d08 JM |
3729 | #endif |
3730 | } | |
3731 | #endif | |
3732 | ||
79aceca5 | 3733 | /* sc */ |
417bf010 JM |
3734 | #if defined(CONFIG_USER_ONLY) |
3735 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3736 | #else | |
3737 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3738 | #endif | |
99e300ef | 3739 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3740 | { |
e1833e1f JM |
3741 | uint32_t lev; |
3742 | ||
3743 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3744 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3745 | } |
3746 | ||
3747 | /*** Trap ***/ | |
99e300ef | 3748 | |
54623277 | 3749 | /* tw */ |
99e300ef | 3750 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3751 | { |
cab3bee2 | 3752 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3753 | /* Update the nip since this might generate a trap exception */ |
3754 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3755 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3756 | t0); | |
cab3bee2 | 3757 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3758 | } |
3759 | ||
3760 | /* twi */ | |
99e300ef | 3761 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3762 | { |
cab3bee2 AJ |
3763 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3764 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3765 | /* Update the nip since this might generate a trap exception */ |
3766 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3767 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3768 | tcg_temp_free(t0); |
3769 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3770 | } |
3771 | ||
d9bce9d9 JM |
3772 | #if defined(TARGET_PPC64) |
3773 | /* td */ | |
99e300ef | 3774 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3775 | { |
cab3bee2 | 3776 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
3777 | /* Update the nip since this might generate a trap exception */ |
3778 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
3779 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3780 | t0); | |
cab3bee2 | 3781 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3782 | } |
3783 | ||
3784 | /* tdi */ | |
99e300ef | 3785 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3786 | { |
cab3bee2 AJ |
3787 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3788 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
3789 | /* Update the nip since this might generate a trap exception */ |
3790 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 3791 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3792 | tcg_temp_free(t0); |
3793 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3794 | } |
3795 | #endif | |
3796 | ||
79aceca5 | 3797 | /*** Processor control ***/ |
99e300ef | 3798 | |
54623277 | 3799 | /* mcrxr */ |
99e300ef | 3800 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3801 | { |
3d7b417e AJ |
3802 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer); |
3803 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA); | |
269f3e95 | 3804 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); |
79aceca5 FB |
3805 | } |
3806 | ||
0cfe11ea | 3807 | /* mfcr mfocrf */ |
99e300ef | 3808 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3809 | { |
76a66253 | 3810 | uint32_t crm, crn; |
3b46e624 | 3811 | |
76a66253 JM |
3812 | if (likely(ctx->opcode & 0x00100000)) { |
3813 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3814 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3815 | crn = ctz32 (crm); |
e1571908 | 3816 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3817 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3818 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3819 | } |
d9bce9d9 | 3820 | } else { |
651721b2 AJ |
3821 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3822 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3823 | tcg_gen_shli_i32(t0, t0, 4); | |
3824 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3825 | tcg_gen_shli_i32(t0, t0, 4); | |
3826 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3827 | tcg_gen_shli_i32(t0, t0, 4); | |
3828 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3829 | tcg_gen_shli_i32(t0, t0, 4); | |
3830 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3831 | tcg_gen_shli_i32(t0, t0, 4); | |
3832 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3833 | tcg_gen_shli_i32(t0, t0, 4); | |
3834 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3835 | tcg_gen_shli_i32(t0, t0, 4); | |
3836 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3837 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3838 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3839 | } |
79aceca5 FB |
3840 | } |
3841 | ||
3842 | /* mfmsr */ | |
99e300ef | 3843 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3844 | { |
9a64fbe4 | 3845 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3846 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3847 | #else |
76db3ba4 | 3848 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3849 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3850 | return; |
9a64fbe4 | 3851 | } |
6527f6ea | 3852 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 3853 | #endif |
79aceca5 FB |
3854 | } |
3855 | ||
7b13448f | 3856 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3fc6c082 | 3857 | { |
7b13448f | 3858 | #if 0 |
3fc6c082 FB |
3859 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3860 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3861 | #endif |
3fc6c082 FB |
3862 | } |
3863 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3864 | |
79aceca5 | 3865 | /* mfspr */ |
636aa200 | 3866 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 3867 | { |
45d827d2 | 3868 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
3869 | uint32_t sprn = SPR(ctx->opcode); |
3870 | ||
3fc6c082 | 3871 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 3872 | if (ctx->mem_idx == 2) |
be147d08 | 3873 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 3874 | else if (ctx->mem_idx) |
3fc6c082 FB |
3875 | read_cb = ctx->spr_cb[sprn].oea_read; |
3876 | else | |
9a64fbe4 | 3877 | #endif |
3fc6c082 | 3878 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
3879 | if (likely(read_cb != NULL)) { |
3880 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 3881 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
3882 | } else { |
3883 | /* Privilege exception */ | |
9fceefa7 JM |
3884 | /* This is a hack to avoid warnings when running Linux: |
3885 | * this OS breaks the PowerPC virtualisation model, | |
3886 | * allowing userland application to read the PVR | |
3887 | */ | |
3888 | if (sprn != SPR_PVR) { | |
93fcfe39 | 3889 | qemu_log("Trying to read privileged spr %d %03x at " |
90e189ec BS |
3890 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3891 | printf("Trying to read privileged spr %d %03x at " | |
3892 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); | |
f24e5695 | 3893 | } |
e06fcd75 | 3894 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 3895 | } |
3fc6c082 FB |
3896 | } else { |
3897 | /* Not defined */ | |
93fcfe39 | 3898 | qemu_log("Trying to read invalid spr %d %03x at " |
90e189ec BS |
3899 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
3900 | printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 3901 | sprn, sprn, ctx->nip); |
e06fcd75 | 3902 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 3903 | } |
79aceca5 FB |
3904 | } |
3905 | ||
99e300ef | 3906 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 3907 | { |
3fc6c082 | 3908 | gen_op_mfspr(ctx); |
76a66253 | 3909 | } |
3fc6c082 FB |
3910 | |
3911 | /* mftb */ | |
99e300ef | 3912 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
3913 | { |
3914 | gen_op_mfspr(ctx); | |
79aceca5 FB |
3915 | } |
3916 | ||
0cfe11ea | 3917 | /* mtcrf mtocrf*/ |
99e300ef | 3918 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 3919 | { |
76a66253 | 3920 | uint32_t crm, crn; |
3b46e624 | 3921 | |
76a66253 | 3922 | crm = CRM(ctx->opcode); |
8dd640e4 | 3923 | if (likely((ctx->opcode & 0x00100000))) { |
3924 | if (crm && ((crm & (crm - 1)) == 0)) { | |
3925 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 3926 | crn = ctz32 (crm); |
8dd640e4 | 3927 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
3928 | tcg_gen_shri_i32(temp, temp, crn * 4); |
3929 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 3930 | tcg_temp_free_i32(temp); |
3931 | } | |
76a66253 | 3932 | } else { |
651721b2 AJ |
3933 | TCGv_i32 temp = tcg_temp_new_i32(); |
3934 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
3935 | for (crn = 0 ; crn < 8 ; crn++) { | |
3936 | if (crm & (1 << crn)) { | |
3937 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
3938 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
3939 | } | |
3940 | } | |
a7812ae4 | 3941 | tcg_temp_free_i32(temp); |
76a66253 | 3942 | } |
79aceca5 FB |
3943 | } |
3944 | ||
3945 | /* mtmsr */ | |
426613db | 3946 | #if defined(TARGET_PPC64) |
99e300ef | 3947 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
3948 | { |
3949 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3950 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 3951 | #else |
76db3ba4 | 3952 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3953 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
3954 | return; |
3955 | } | |
be147d08 JM |
3956 | if (ctx->opcode & 0x00010000) { |
3957 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3958 | TCGv t0 = tcg_temp_new(); |
3959 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
3960 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
3961 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
3962 | tcg_temp_free(t0); | |
be147d08 | 3963 | } else { |
056b05f8 JM |
3964 | /* XXX: we need to update nip before the store |
3965 | * if we enter power saving mode, we will exit the loop | |
3966 | * directly from ppc_store_msr | |
3967 | */ | |
be147d08 | 3968 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 3969 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
3970 | /* Must stop the translation as machine state (may have) changed */ |
3971 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 3972 | gen_stop_exception(ctx); |
be147d08 | 3973 | } |
426613db JM |
3974 | #endif |
3975 | } | |
3976 | #endif | |
3977 | ||
99e300ef | 3978 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 3979 | { |
9a64fbe4 | 3980 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3981 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 3982 | #else |
76db3ba4 | 3983 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3984 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 3985 | return; |
9a64fbe4 | 3986 | } |
be147d08 JM |
3987 | if (ctx->opcode & 0x00010000) { |
3988 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3989 | TCGv t0 = tcg_temp_new(); |
3990 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
3991 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
3992 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
3993 | tcg_temp_free(t0); | |
be147d08 | 3994 | } else { |
8018dc63 AG |
3995 | TCGv msr = tcg_temp_new(); |
3996 | ||
056b05f8 JM |
3997 | /* XXX: we need to update nip before the store |
3998 | * if we enter power saving mode, we will exit the loop | |
3999 | * directly from ppc_store_msr | |
4000 | */ | |
be147d08 | 4001 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 4002 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4003 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4004 | #else | |
4005 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4006 | #endif |
e5f17ac6 | 4007 | gen_helper_store_msr(cpu_env, msr); |
be147d08 | 4008 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4009 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4010 | gen_stop_exception(ctx); |
be147d08 | 4011 | } |
9a64fbe4 | 4012 | #endif |
79aceca5 FB |
4013 | } |
4014 | ||
4015 | /* mtspr */ | |
99e300ef | 4016 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4017 | { |
45d827d2 | 4018 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
4019 | uint32_t sprn = SPR(ctx->opcode); |
4020 | ||
3fc6c082 | 4021 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4022 | if (ctx->mem_idx == 2) |
be147d08 | 4023 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 4024 | else if (ctx->mem_idx) |
3fc6c082 FB |
4025 | write_cb = ctx->spr_cb[sprn].oea_write; |
4026 | else | |
9a64fbe4 | 4027 | #endif |
3fc6c082 | 4028 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
4029 | if (likely(write_cb != NULL)) { |
4030 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4031 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4032 | } else { |
4033 | /* Privilege exception */ | |
93fcfe39 | 4034 | qemu_log("Trying to write privileged spr %d %03x at " |
90e189ec BS |
4035 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
4036 | printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx | |
4037 | "\n", sprn, sprn, ctx->nip); | |
e06fcd75 | 4038 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4039 | } |
3fc6c082 FB |
4040 | } else { |
4041 | /* Not defined */ | |
93fcfe39 | 4042 | qemu_log("Trying to write invalid spr %d %03x at " |
90e189ec BS |
4043 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
4044 | printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n", | |
077fc206 | 4045 | sprn, sprn, ctx->nip); |
e06fcd75 | 4046 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4047 | } |
79aceca5 FB |
4048 | } |
4049 | ||
4050 | /*** Cache management ***/ | |
99e300ef | 4051 | |
54623277 | 4052 | /* dcbf */ |
99e300ef | 4053 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4054 | { |
dac454af | 4055 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4056 | TCGv t0; |
4057 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4058 | t0 = tcg_temp_new(); | |
4059 | gen_addr_reg_index(ctx, t0); | |
4060 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4061 | tcg_temp_free(t0); |
79aceca5 FB |
4062 | } |
4063 | ||
4064 | /* dcbi (Supervisor only) */ | |
99e300ef | 4065 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4066 | { |
a541f297 | 4067 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4068 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4069 | #else |
b61f2753 | 4070 | TCGv EA, val; |
76db3ba4 | 4071 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4072 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4073 | return; |
9a64fbe4 | 4074 | } |
a7812ae4 | 4075 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4076 | gen_set_access_type(ctx, ACCESS_CACHE); |
4077 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4078 | val = tcg_temp_new(); |
76a66253 | 4079 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4080 | gen_qemu_ld8u(ctx, val, EA); |
4081 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4082 | tcg_temp_free(val); |
4083 | tcg_temp_free(EA); | |
a541f297 | 4084 | #endif |
79aceca5 FB |
4085 | } |
4086 | ||
4087 | /* dcdst */ | |
99e300ef | 4088 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4089 | { |
76a66253 | 4090 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4091 | TCGv t0; |
4092 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4093 | t0 = tcg_temp_new(); | |
4094 | gen_addr_reg_index(ctx, t0); | |
4095 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4096 | tcg_temp_free(t0); |
79aceca5 FB |
4097 | } |
4098 | ||
4099 | /* dcbt */ | |
99e300ef | 4100 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4101 | { |
0db1b20e | 4102 | /* interpreted as no-op */ |
76a66253 JM |
4103 | /* XXX: specification say this is treated as a load by the MMU |
4104 | * but does not generate any exception | |
4105 | */ | |
79aceca5 FB |
4106 | } |
4107 | ||
4108 | /* dcbtst */ | |
99e300ef | 4109 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4110 | { |
0db1b20e | 4111 | /* interpreted as no-op */ |
76a66253 JM |
4112 | /* XXX: specification say this is treated as a load by the MMU |
4113 | * but does not generate any exception | |
4114 | */ | |
79aceca5 FB |
4115 | } |
4116 | ||
4117 | /* dcbz */ | |
99e300ef | 4118 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4119 | { |
76db3ba4 AJ |
4120 | TCGv t0; |
4121 | gen_set_access_type(ctx, ACCESS_CACHE); | |
799a8c8d AJ |
4122 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4123 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4124 | t0 = tcg_temp_new(); |
4125 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4126 | gen_helper_dcbz(cpu_env, t0); |
799a8c8d | 4127 | tcg_temp_free(t0); |
d63001d1 JM |
4128 | } |
4129 | ||
e8eaa2c0 | 4130 | static void gen_dcbz_970(DisasContext *ctx) |
d63001d1 | 4131 | { |
76db3ba4 AJ |
4132 | TCGv t0; |
4133 | gen_set_access_type(ctx, ACCESS_CACHE); | |
799a8c8d AJ |
4134 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4135 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4136 | t0 = tcg_temp_new(); |
4137 | gen_addr_reg_index(ctx, t0); | |
d63001d1 | 4138 | if (ctx->opcode & 0x00200000) |
2f5a189c | 4139 | gen_helper_dcbz(cpu_env, t0); |
d63001d1 | 4140 | else |
2f5a189c | 4141 | gen_helper_dcbz_970(cpu_env, t0); |
799a8c8d | 4142 | tcg_temp_free(t0); |
79aceca5 FB |
4143 | } |
4144 | ||
ae1c1a3d | 4145 | /* dst / dstt */ |
99e300ef | 4146 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4147 | { |
4148 | if (rA(ctx->opcode) == 0) { | |
4149 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4150 | } else { | |
4151 | /* interpreted as no-op */ | |
4152 | } | |
4153 | } | |
4154 | ||
4155 | /* dstst /dststt */ | |
99e300ef | 4156 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4157 | { |
4158 | if (rA(ctx->opcode) == 0) { | |
4159 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4160 | } else { | |
4161 | /* interpreted as no-op */ | |
4162 | } | |
4163 | ||
4164 | } | |
4165 | ||
4166 | /* dss / dssall */ | |
99e300ef | 4167 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4168 | { |
4169 | /* interpreted as no-op */ | |
4170 | } | |
4171 | ||
79aceca5 | 4172 | /* icbi */ |
99e300ef | 4173 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4174 | { |
76db3ba4 AJ |
4175 | TCGv t0; |
4176 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4177 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4178 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4179 | t0 = tcg_temp_new(); |
4180 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4181 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4182 | tcg_temp_free(t0); |
79aceca5 FB |
4183 | } |
4184 | ||
4185 | /* Optional: */ | |
4186 | /* dcba */ | |
99e300ef | 4187 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4188 | { |
0db1b20e JM |
4189 | /* interpreted as no-op */ |
4190 | /* XXX: specification say this is treated as a store by the MMU | |
4191 | * but does not generate any exception | |
4192 | */ | |
79aceca5 FB |
4193 | } |
4194 | ||
4195 | /*** Segment register manipulation ***/ | |
4196 | /* Supervisor only: */ | |
99e300ef | 4197 | |
54623277 | 4198 | /* mfsr */ |
99e300ef | 4199 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4200 | { |
9a64fbe4 | 4201 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4202 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4203 | #else |
74d37793 | 4204 | TCGv t0; |
76db3ba4 | 4205 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4206 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4207 | return; |
9a64fbe4 | 4208 | } |
74d37793 | 4209 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4210 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4211 | tcg_temp_free(t0); |
9a64fbe4 | 4212 | #endif |
79aceca5 FB |
4213 | } |
4214 | ||
4215 | /* mfsrin */ | |
99e300ef | 4216 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4217 | { |
9a64fbe4 | 4218 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4219 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4220 | #else |
74d37793 | 4221 | TCGv t0; |
76db3ba4 | 4222 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4223 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4224 | return; |
9a64fbe4 | 4225 | } |
74d37793 AJ |
4226 | t0 = tcg_temp_new(); |
4227 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4228 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4229 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4230 | tcg_temp_free(t0); |
9a64fbe4 | 4231 | #endif |
79aceca5 FB |
4232 | } |
4233 | ||
4234 | /* mtsr */ | |
99e300ef | 4235 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4236 | { |
9a64fbe4 | 4237 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4238 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4239 | #else |
74d37793 | 4240 | TCGv t0; |
76db3ba4 | 4241 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4242 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4243 | return; |
9a64fbe4 | 4244 | } |
74d37793 | 4245 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4246 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4247 | tcg_temp_free(t0); |
9a64fbe4 | 4248 | #endif |
79aceca5 FB |
4249 | } |
4250 | ||
4251 | /* mtsrin */ | |
99e300ef | 4252 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4253 | { |
9a64fbe4 | 4254 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4255 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4256 | #else |
74d37793 | 4257 | TCGv t0; |
76db3ba4 | 4258 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4259 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4260 | return; |
9a64fbe4 | 4261 | } |
74d37793 AJ |
4262 | t0 = tcg_temp_new(); |
4263 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4264 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4265 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4266 | tcg_temp_free(t0); |
9a64fbe4 | 4267 | #endif |
79aceca5 FB |
4268 | } |
4269 | ||
12de9a39 JM |
4270 | #if defined(TARGET_PPC64) |
4271 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4272 | |
54623277 | 4273 | /* mfsr */ |
e8eaa2c0 | 4274 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4275 | { |
4276 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4277 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4278 | #else |
74d37793 | 4279 | TCGv t0; |
76db3ba4 | 4280 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4281 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4282 | return; |
4283 | } | |
74d37793 | 4284 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4285 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4286 | tcg_temp_free(t0); |
12de9a39 JM |
4287 | #endif |
4288 | } | |
4289 | ||
4290 | /* mfsrin */ | |
e8eaa2c0 | 4291 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4292 | { |
4293 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4294 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4295 | #else |
74d37793 | 4296 | TCGv t0; |
76db3ba4 | 4297 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4298 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4299 | return; |
4300 | } | |
74d37793 AJ |
4301 | t0 = tcg_temp_new(); |
4302 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4303 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4304 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4305 | tcg_temp_free(t0); |
12de9a39 JM |
4306 | #endif |
4307 | } | |
4308 | ||
4309 | /* mtsr */ | |
e8eaa2c0 | 4310 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4311 | { |
4312 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4313 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4314 | #else |
74d37793 | 4315 | TCGv t0; |
76db3ba4 | 4316 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4317 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4318 | return; |
4319 | } | |
74d37793 | 4320 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4321 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4322 | tcg_temp_free(t0); |
12de9a39 JM |
4323 | #endif |
4324 | } | |
4325 | ||
4326 | /* mtsrin */ | |
e8eaa2c0 | 4327 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4328 | { |
4329 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4330 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4331 | #else |
74d37793 | 4332 | TCGv t0; |
76db3ba4 | 4333 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4334 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4335 | return; |
4336 | } | |
74d37793 AJ |
4337 | t0 = tcg_temp_new(); |
4338 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4339 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4340 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4341 | tcg_temp_free(t0); |
12de9a39 JM |
4342 | #endif |
4343 | } | |
f6b868fc BS |
4344 | |
4345 | /* slbmte */ | |
e8eaa2c0 | 4346 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4347 | { |
4348 | #if defined(CONFIG_USER_ONLY) | |
4349 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4350 | #else | |
4351 | if (unlikely(!ctx->mem_idx)) { | |
4352 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4353 | return; | |
4354 | } | |
c6c7cf05 BS |
4355 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4356 | cpu_gpr[rS(ctx->opcode)]); | |
f6b868fc BS |
4357 | #endif |
4358 | } | |
4359 | ||
efdef95f DG |
4360 | static void gen_slbmfee(DisasContext *ctx) |
4361 | { | |
4362 | #if defined(CONFIG_USER_ONLY) | |
4363 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4364 | #else | |
4365 | if (unlikely(!ctx->mem_idx)) { | |
4366 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4367 | return; | |
4368 | } | |
c6c7cf05 | 4369 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4370 | cpu_gpr[rB(ctx->opcode)]); |
4371 | #endif | |
4372 | } | |
4373 | ||
4374 | static void gen_slbmfev(DisasContext *ctx) | |
4375 | { | |
4376 | #if defined(CONFIG_USER_ONLY) | |
4377 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4378 | #else | |
4379 | if (unlikely(!ctx->mem_idx)) { | |
4380 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4381 | return; | |
4382 | } | |
c6c7cf05 | 4383 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4384 | cpu_gpr[rB(ctx->opcode)]); |
4385 | #endif | |
4386 | } | |
12de9a39 JM |
4387 | #endif /* defined(TARGET_PPC64) */ |
4388 | ||
79aceca5 | 4389 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4390 | /* Optional & mem_idx only: */ |
99e300ef | 4391 | |
54623277 | 4392 | /* tlbia */ |
99e300ef | 4393 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4394 | { |
9a64fbe4 | 4395 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4396 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4397 | #else |
76db3ba4 | 4398 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4399 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4400 | return; |
9a64fbe4 | 4401 | } |
c6c7cf05 | 4402 | gen_helper_tlbia(cpu_env); |
9a64fbe4 | 4403 | #endif |
79aceca5 FB |
4404 | } |
4405 | ||
bf14b1ce | 4406 | /* tlbiel */ |
99e300ef | 4407 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4408 | { |
4409 | #if defined(CONFIG_USER_ONLY) | |
4410 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4411 | #else | |
4412 | if (unlikely(!ctx->mem_idx)) { | |
4413 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4414 | return; | |
4415 | } | |
c6c7cf05 | 4416 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
bf14b1ce BS |
4417 | #endif |
4418 | } | |
4419 | ||
79aceca5 | 4420 | /* tlbie */ |
99e300ef | 4421 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4422 | { |
9a64fbe4 | 4423 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4424 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4425 | #else |
76db3ba4 | 4426 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4427 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4428 | return; |
9a64fbe4 | 4429 | } |
d9bce9d9 | 4430 | #if defined(TARGET_PPC64) |
74d37793 AJ |
4431 | if (!ctx->sf_mode) { |
4432 | TCGv t0 = tcg_temp_new(); | |
4433 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4434 | gen_helper_tlbie(cpu_env, t0); |
74d37793 AJ |
4435 | tcg_temp_free(t0); |
4436 | } else | |
d9bce9d9 | 4437 | #endif |
c6c7cf05 | 4438 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9a64fbe4 | 4439 | #endif |
79aceca5 FB |
4440 | } |
4441 | ||
4442 | /* tlbsync */ | |
99e300ef | 4443 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4444 | { |
9a64fbe4 | 4445 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4446 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4447 | #else |
76db3ba4 | 4448 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4449 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4450 | return; |
9a64fbe4 FB |
4451 | } |
4452 | /* This has no effect: it should ensure that all previous | |
4453 | * tlbie have completed | |
4454 | */ | |
e06fcd75 | 4455 | gen_stop_exception(ctx); |
9a64fbe4 | 4456 | #endif |
79aceca5 FB |
4457 | } |
4458 | ||
426613db JM |
4459 | #if defined(TARGET_PPC64) |
4460 | /* slbia */ | |
99e300ef | 4461 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4462 | { |
4463 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4464 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4465 | #else |
76db3ba4 | 4466 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4467 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4468 | return; |
4469 | } | |
c6c7cf05 | 4470 | gen_helper_slbia(cpu_env); |
426613db JM |
4471 | #endif |
4472 | } | |
4473 | ||
4474 | /* slbie */ | |
99e300ef | 4475 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4476 | { |
4477 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4478 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4479 | #else |
76db3ba4 | 4480 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4481 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4482 | return; |
4483 | } | |
c6c7cf05 | 4484 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4485 | #endif |
4486 | } | |
4487 | #endif | |
4488 | ||
79aceca5 FB |
4489 | /*** External control ***/ |
4490 | /* Optional: */ | |
99e300ef | 4491 | |
54623277 | 4492 | /* eciwx */ |
99e300ef | 4493 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4494 | { |
76db3ba4 | 4495 | TCGv t0; |
fa407c03 | 4496 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4497 | gen_set_access_type(ctx, ACCESS_EXT); |
4498 | t0 = tcg_temp_new(); | |
4499 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4500 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4501 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4502 | tcg_temp_free(t0); |
76a66253 JM |
4503 | } |
4504 | ||
4505 | /* ecowx */ | |
99e300ef | 4506 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4507 | { |
76db3ba4 | 4508 | TCGv t0; |
fa407c03 | 4509 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4510 | gen_set_access_type(ctx, ACCESS_EXT); |
4511 | t0 = tcg_temp_new(); | |
4512 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4513 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4514 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4515 | tcg_temp_free(t0); |
76a66253 JM |
4516 | } |
4517 | ||
4518 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4519 | |
54623277 | 4520 | /* abs - abs. */ |
99e300ef | 4521 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4522 | { |
22e0e173 AJ |
4523 | int l1 = gen_new_label(); |
4524 | int l2 = gen_new_label(); | |
4525 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4526 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4527 | tcg_gen_br(l2); | |
4528 | gen_set_label(l1); | |
4529 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4530 | gen_set_label(l2); | |
76a66253 | 4531 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4532 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4533 | } |
4534 | ||
4535 | /* abso - abso. */ | |
99e300ef | 4536 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4537 | { |
22e0e173 AJ |
4538 | int l1 = gen_new_label(); |
4539 | int l2 = gen_new_label(); | |
4540 | int l3 = gen_new_label(); | |
4541 | /* Start with XER OV disabled, the most likely case */ | |
4542 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
4543 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); | |
4544 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
4545 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
4546 | tcg_gen_br(l2); | |
4547 | gen_set_label(l1); | |
4548 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4549 | tcg_gen_br(l3); | |
4550 | gen_set_label(l2); | |
4551 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4552 | gen_set_label(l3); | |
76a66253 | 4553 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4554 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4555 | } |
4556 | ||
4557 | /* clcs */ | |
99e300ef | 4558 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4559 | { |
22e0e173 | 4560 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4561 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4562 | tcg_temp_free_i32(t0); |
c7697e1f | 4563 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4564 | } |
4565 | ||
4566 | /* div - div. */ | |
99e300ef | 4567 | static void gen_div(DisasContext *ctx) |
76a66253 | 4568 | { |
d15f74fb BS |
4569 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4570 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4571 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4572 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4573 | } |
4574 | ||
4575 | /* divo - divo. */ | |
99e300ef | 4576 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4577 | { |
d15f74fb BS |
4578 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4579 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4580 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4581 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4582 | } |
4583 | ||
4584 | /* divs - divs. */ | |
99e300ef | 4585 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4586 | { |
d15f74fb BS |
4587 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4588 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4589 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4590 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4591 | } |
4592 | ||
4593 | /* divso - divso. */ | |
99e300ef | 4594 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4595 | { |
d15f74fb BS |
4596 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4597 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4598 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4599 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4600 | } |
4601 | ||
4602 | /* doz - doz. */ | |
99e300ef | 4603 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4604 | { |
22e0e173 AJ |
4605 | int l1 = gen_new_label(); |
4606 | int l2 = gen_new_label(); | |
4607 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4608 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4609 | tcg_gen_br(l2); | |
4610 | gen_set_label(l1); | |
4611 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4612 | gen_set_label(l2); | |
76a66253 | 4613 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4614 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4615 | } |
4616 | ||
4617 | /* dozo - dozo. */ | |
99e300ef | 4618 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4619 | { |
22e0e173 AJ |
4620 | int l1 = gen_new_label(); |
4621 | int l2 = gen_new_label(); | |
4622 | TCGv t0 = tcg_temp_new(); | |
4623 | TCGv t1 = tcg_temp_new(); | |
4624 | TCGv t2 = tcg_temp_new(); | |
4625 | /* Start with XER OV disabled, the most likely case */ | |
4626 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
4627 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4628 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4629 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4630 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4631 | tcg_gen_andc_tl(t1, t1, t2); | |
4632 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4633 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
4634 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
4635 | tcg_gen_br(l2); | |
4636 | gen_set_label(l1); | |
4637 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4638 | gen_set_label(l2); | |
4639 | tcg_temp_free(t0); | |
4640 | tcg_temp_free(t1); | |
4641 | tcg_temp_free(t2); | |
76a66253 | 4642 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4643 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4644 | } |
4645 | ||
4646 | /* dozi */ | |
99e300ef | 4647 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4648 | { |
22e0e173 AJ |
4649 | target_long simm = SIMM(ctx->opcode); |
4650 | int l1 = gen_new_label(); | |
4651 | int l2 = gen_new_label(); | |
4652 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
4653 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4654 | tcg_gen_br(l2); | |
4655 | gen_set_label(l1); | |
4656 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4657 | gen_set_label(l2); | |
4658 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4659 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4660 | } |
4661 | ||
76a66253 | 4662 | /* lscbx - lscbx. */ |
99e300ef | 4663 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4664 | { |
bdb4b689 AJ |
4665 | TCGv t0 = tcg_temp_new(); |
4666 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4667 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4668 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4669 | |
76db3ba4 | 4670 | gen_addr_reg_index(ctx, t0); |
76a66253 | 4671 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 4672 | gen_update_nip(ctx, ctx->nip - 4); |
2f5a189c | 4673 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4674 | tcg_temp_free_i32(t1); |
4675 | tcg_temp_free_i32(t2); | |
4676 | tcg_temp_free_i32(t3); | |
3d7b417e | 4677 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4678 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4679 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4680 | gen_set_Rc0(ctx, t0); |
4681 | tcg_temp_free(t0); | |
76a66253 JM |
4682 | } |
4683 | ||
4684 | /* maskg - maskg. */ | |
99e300ef | 4685 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4686 | { |
22e0e173 AJ |
4687 | int l1 = gen_new_label(); |
4688 | TCGv t0 = tcg_temp_new(); | |
4689 | TCGv t1 = tcg_temp_new(); | |
4690 | TCGv t2 = tcg_temp_new(); | |
4691 | TCGv t3 = tcg_temp_new(); | |
4692 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4693 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4694 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4695 | tcg_gen_addi_tl(t2, t0, 1); | |
4696 | tcg_gen_shr_tl(t2, t3, t2); | |
4697 | tcg_gen_shr_tl(t3, t3, t1); | |
4698 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4699 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4700 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4701 | gen_set_label(l1); | |
4702 | tcg_temp_free(t0); | |
4703 | tcg_temp_free(t1); | |
4704 | tcg_temp_free(t2); | |
4705 | tcg_temp_free(t3); | |
76a66253 | 4706 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4707 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4708 | } |
4709 | ||
4710 | /* maskir - maskir. */ | |
99e300ef | 4711 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4712 | { |
22e0e173 AJ |
4713 | TCGv t0 = tcg_temp_new(); |
4714 | TCGv t1 = tcg_temp_new(); | |
4715 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4716 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4717 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4718 | tcg_temp_free(t0); | |
4719 | tcg_temp_free(t1); | |
76a66253 | 4720 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4721 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4722 | } |
4723 | ||
4724 | /* mul - mul. */ | |
99e300ef | 4725 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4726 | { |
22e0e173 AJ |
4727 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4728 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4729 | TCGv t2 = tcg_temp_new(); | |
4730 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4731 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4732 | tcg_gen_mul_i64(t0, t0, t1); | |
4733 | tcg_gen_trunc_i64_tl(t2, t0); | |
4734 | gen_store_spr(SPR_MQ, t2); | |
4735 | tcg_gen_shri_i64(t1, t0, 32); | |
4736 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4737 | tcg_temp_free_i64(t0); | |
4738 | tcg_temp_free_i64(t1); | |
4739 | tcg_temp_free(t2); | |
76a66253 | 4740 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4741 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4742 | } |
4743 | ||
4744 | /* mulo - mulo. */ | |
99e300ef | 4745 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4746 | { |
22e0e173 AJ |
4747 | int l1 = gen_new_label(); |
4748 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
4749 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4750 | TCGv t2 = tcg_temp_new(); | |
4751 | /* Start with XER OV disabled, the most likely case */ | |
4752 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
4753 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4754 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4755 | tcg_gen_mul_i64(t0, t0, t1); | |
4756 | tcg_gen_trunc_i64_tl(t2, t0); | |
4757 | gen_store_spr(SPR_MQ, t2); | |
4758 | tcg_gen_shri_i64(t1, t0, 32); | |
4759 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4760 | tcg_gen_ext32s_i64(t1, t0); | |
4761 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
4762 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
4763 | gen_set_label(l1); | |
4764 | tcg_temp_free_i64(t0); | |
4765 | tcg_temp_free_i64(t1); | |
4766 | tcg_temp_free(t2); | |
76a66253 | 4767 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4768 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4769 | } |
4770 | ||
4771 | /* nabs - nabs. */ | |
99e300ef | 4772 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4773 | { |
22e0e173 AJ |
4774 | int l1 = gen_new_label(); |
4775 | int l2 = gen_new_label(); | |
4776 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4777 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4778 | tcg_gen_br(l2); | |
4779 | gen_set_label(l1); | |
4780 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4781 | gen_set_label(l2); | |
76a66253 | 4782 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4783 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4784 | } |
4785 | ||
4786 | /* nabso - nabso. */ | |
99e300ef | 4787 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4788 | { |
22e0e173 AJ |
4789 | int l1 = gen_new_label(); |
4790 | int l2 = gen_new_label(); | |
4791 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4792 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4793 | tcg_gen_br(l2); | |
4794 | gen_set_label(l1); | |
4795 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4796 | gen_set_label(l2); | |
4797 | /* nabs never overflows */ | |
4798 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
76a66253 | 4799 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4800 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4801 | } |
4802 | ||
4803 | /* rlmi - rlmi. */ | |
99e300ef | 4804 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4805 | { |
7487953d AJ |
4806 | uint32_t mb = MB(ctx->opcode); |
4807 | uint32_t me = ME(ctx->opcode); | |
4808 | TCGv t0 = tcg_temp_new(); | |
4809 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4810 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4811 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4812 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4813 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4814 | tcg_temp_free(t0); | |
76a66253 | 4815 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4816 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4817 | } |
4818 | ||
4819 | /* rrib - rrib. */ | |
99e300ef | 4820 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4821 | { |
7487953d AJ |
4822 | TCGv t0 = tcg_temp_new(); |
4823 | TCGv t1 = tcg_temp_new(); | |
4824 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4825 | tcg_gen_movi_tl(t1, 0x80000000); | |
4826 | tcg_gen_shr_tl(t1, t1, t0); | |
4827 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4828 | tcg_gen_and_tl(t0, t0, t1); | |
4829 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4830 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4831 | tcg_temp_free(t0); | |
4832 | tcg_temp_free(t1); | |
76a66253 | 4833 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4834 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4835 | } |
4836 | ||
4837 | /* sle - sle. */ | |
99e300ef | 4838 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4839 | { |
7487953d AJ |
4840 | TCGv t0 = tcg_temp_new(); |
4841 | TCGv t1 = tcg_temp_new(); | |
4842 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4843 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4844 | tcg_gen_subfi_tl(t1, 32, t1); | |
4845 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4846 | tcg_gen_or_tl(t1, t0, t1); | |
4847 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4848 | gen_store_spr(SPR_MQ, t1); | |
4849 | tcg_temp_free(t0); | |
4850 | tcg_temp_free(t1); | |
76a66253 | 4851 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4852 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4853 | } |
4854 | ||
4855 | /* sleq - sleq. */ | |
99e300ef | 4856 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4857 | { |
7487953d AJ |
4858 | TCGv t0 = tcg_temp_new(); |
4859 | TCGv t1 = tcg_temp_new(); | |
4860 | TCGv t2 = tcg_temp_new(); | |
4861 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4862 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
4863 | tcg_gen_shl_tl(t2, t2, t0); | |
4864 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4865 | gen_load_spr(t1, SPR_MQ); | |
4866 | gen_store_spr(SPR_MQ, t0); | |
4867 | tcg_gen_and_tl(t0, t0, t2); | |
4868 | tcg_gen_andc_tl(t1, t1, t2); | |
4869 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4870 | tcg_temp_free(t0); | |
4871 | tcg_temp_free(t1); | |
4872 | tcg_temp_free(t2); | |
76a66253 | 4873 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4874 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4875 | } |
4876 | ||
4877 | /* sliq - sliq. */ | |
99e300ef | 4878 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 4879 | { |
7487953d AJ |
4880 | int sh = SH(ctx->opcode); |
4881 | TCGv t0 = tcg_temp_new(); | |
4882 | TCGv t1 = tcg_temp_new(); | |
4883 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4884 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4885 | tcg_gen_or_tl(t1, t0, t1); | |
4886 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4887 | gen_store_spr(SPR_MQ, t1); | |
4888 | tcg_temp_free(t0); | |
4889 | tcg_temp_free(t1); | |
76a66253 | 4890 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4891 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4892 | } |
4893 | ||
4894 | /* slliq - slliq. */ | |
99e300ef | 4895 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 4896 | { |
7487953d AJ |
4897 | int sh = SH(ctx->opcode); |
4898 | TCGv t0 = tcg_temp_new(); | |
4899 | TCGv t1 = tcg_temp_new(); | |
4900 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4901 | gen_load_spr(t1, SPR_MQ); | |
4902 | gen_store_spr(SPR_MQ, t0); | |
4903 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
4904 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
4905 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4906 | tcg_temp_free(t0); | |
4907 | tcg_temp_free(t1); | |
76a66253 | 4908 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4909 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4910 | } |
4911 | ||
4912 | /* sllq - sllq. */ | |
99e300ef | 4913 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 4914 | { |
7487953d AJ |
4915 | int l1 = gen_new_label(); |
4916 | int l2 = gen_new_label(); | |
4917 | TCGv t0 = tcg_temp_local_new(); | |
4918 | TCGv t1 = tcg_temp_local_new(); | |
4919 | TCGv t2 = tcg_temp_local_new(); | |
4920 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4921 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4922 | tcg_gen_shl_tl(t1, t1, t2); | |
4923 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4924 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
4925 | gen_load_spr(t0, SPR_MQ); | |
4926 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4927 | tcg_gen_br(l2); | |
4928 | gen_set_label(l1); | |
4929 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4930 | gen_load_spr(t2, SPR_MQ); | |
4931 | tcg_gen_andc_tl(t1, t2, t1); | |
4932 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4933 | gen_set_label(l2); | |
4934 | tcg_temp_free(t0); | |
4935 | tcg_temp_free(t1); | |
4936 | tcg_temp_free(t2); | |
76a66253 | 4937 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4938 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4939 | } |
4940 | ||
4941 | /* slq - slq. */ | |
99e300ef | 4942 | static void gen_slq(DisasContext *ctx) |
76a66253 | 4943 | { |
7487953d AJ |
4944 | int l1 = gen_new_label(); |
4945 | TCGv t0 = tcg_temp_new(); | |
4946 | TCGv t1 = tcg_temp_new(); | |
4947 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4948 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4949 | tcg_gen_subfi_tl(t1, 32, t1); | |
4950 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4951 | tcg_gen_or_tl(t1, t0, t1); | |
4952 | gen_store_spr(SPR_MQ, t1); | |
4953 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4954 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4955 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
4956 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
4957 | gen_set_label(l1); | |
4958 | tcg_temp_free(t0); | |
4959 | tcg_temp_free(t1); | |
76a66253 | 4960 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4961 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4962 | } |
4963 | ||
d9bce9d9 | 4964 | /* sraiq - sraiq. */ |
99e300ef | 4965 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 4966 | { |
7487953d AJ |
4967 | int sh = SH(ctx->opcode); |
4968 | int l1 = gen_new_label(); | |
4969 | TCGv t0 = tcg_temp_new(); | |
4970 | TCGv t1 = tcg_temp_new(); | |
4971 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4972 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4973 | tcg_gen_or_tl(t0, t0, t1); | |
4974 | gen_store_spr(SPR_MQ, t0); | |
4975 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
4976 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
4977 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
4978 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA)); | |
4979 | gen_set_label(l1); | |
4980 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
4981 | tcg_temp_free(t0); | |
4982 | tcg_temp_free(t1); | |
76a66253 | 4983 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4984 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4985 | } |
4986 | ||
4987 | /* sraq - sraq. */ | |
99e300ef | 4988 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 4989 | { |
7487953d AJ |
4990 | int l1 = gen_new_label(); |
4991 | int l2 = gen_new_label(); | |
4992 | TCGv t0 = tcg_temp_new(); | |
4993 | TCGv t1 = tcg_temp_local_new(); | |
4994 | TCGv t2 = tcg_temp_local_new(); | |
4995 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4996 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4997 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
4998 | tcg_gen_subfi_tl(t2, 32, t2); | |
4999 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5000 | tcg_gen_or_tl(t0, t0, t2); | |
5001 | gen_store_spr(SPR_MQ, t0); | |
5002 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5003 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5004 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5005 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5006 | gen_set_label(l1); | |
5007 | tcg_temp_free(t0); | |
5008 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
5009 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
5010 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
5011 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
5012 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA)); | |
5013 | gen_set_label(l2); | |
5014 | tcg_temp_free(t1); | |
5015 | tcg_temp_free(t2); | |
76a66253 | 5016 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5017 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5018 | } |
5019 | ||
5020 | /* sre - sre. */ | |
99e300ef | 5021 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5022 | { |
7487953d AJ |
5023 | TCGv t0 = tcg_temp_new(); |
5024 | TCGv t1 = tcg_temp_new(); | |
5025 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5026 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5027 | tcg_gen_subfi_tl(t1, 32, t1); | |
5028 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5029 | tcg_gen_or_tl(t1, t0, t1); | |
5030 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5031 | gen_store_spr(SPR_MQ, t1); | |
5032 | tcg_temp_free(t0); | |
5033 | tcg_temp_free(t1); | |
76a66253 | 5034 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5035 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5036 | } |
5037 | ||
5038 | /* srea - srea. */ | |
99e300ef | 5039 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5040 | { |
7487953d AJ |
5041 | TCGv t0 = tcg_temp_new(); |
5042 | TCGv t1 = tcg_temp_new(); | |
5043 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5044 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5045 | gen_store_spr(SPR_MQ, t0); | |
5046 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5047 | tcg_temp_free(t0); | |
5048 | tcg_temp_free(t1); | |
76a66253 | 5049 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5050 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5051 | } |
5052 | ||
5053 | /* sreq */ | |
99e300ef | 5054 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5055 | { |
7487953d AJ |
5056 | TCGv t0 = tcg_temp_new(); |
5057 | TCGv t1 = tcg_temp_new(); | |
5058 | TCGv t2 = tcg_temp_new(); | |
5059 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5060 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5061 | tcg_gen_shr_tl(t1, t1, t0); | |
5062 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5063 | gen_load_spr(t2, SPR_MQ); | |
5064 | gen_store_spr(SPR_MQ, t0); | |
5065 | tcg_gen_and_tl(t0, t0, t1); | |
5066 | tcg_gen_andc_tl(t2, t2, t1); | |
5067 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5068 | tcg_temp_free(t0); | |
5069 | tcg_temp_free(t1); | |
5070 | tcg_temp_free(t2); | |
76a66253 | 5071 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5072 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5073 | } |
5074 | ||
5075 | /* sriq */ | |
99e300ef | 5076 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5077 | { |
7487953d AJ |
5078 | int sh = SH(ctx->opcode); |
5079 | TCGv t0 = tcg_temp_new(); | |
5080 | TCGv t1 = tcg_temp_new(); | |
5081 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5082 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5083 | tcg_gen_or_tl(t1, t0, t1); | |
5084 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5085 | gen_store_spr(SPR_MQ, t1); | |
5086 | tcg_temp_free(t0); | |
5087 | tcg_temp_free(t1); | |
76a66253 | 5088 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5089 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5090 | } |
5091 | ||
5092 | /* srliq */ | |
99e300ef | 5093 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5094 | { |
7487953d AJ |
5095 | int sh = SH(ctx->opcode); |
5096 | TCGv t0 = tcg_temp_new(); | |
5097 | TCGv t1 = tcg_temp_new(); | |
5098 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5099 | gen_load_spr(t1, SPR_MQ); | |
5100 | gen_store_spr(SPR_MQ, t0); | |
5101 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5102 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5103 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5104 | tcg_temp_free(t0); | |
5105 | tcg_temp_free(t1); | |
76a66253 | 5106 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5107 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5108 | } |
5109 | ||
5110 | /* srlq */ | |
99e300ef | 5111 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5112 | { |
7487953d AJ |
5113 | int l1 = gen_new_label(); |
5114 | int l2 = gen_new_label(); | |
5115 | TCGv t0 = tcg_temp_local_new(); | |
5116 | TCGv t1 = tcg_temp_local_new(); | |
5117 | TCGv t2 = tcg_temp_local_new(); | |
5118 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5119 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5120 | tcg_gen_shr_tl(t2, t1, t2); | |
5121 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5122 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5123 | gen_load_spr(t0, SPR_MQ); | |
5124 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5125 | tcg_gen_br(l2); | |
5126 | gen_set_label(l1); | |
5127 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5128 | tcg_gen_and_tl(t0, t0, t2); | |
5129 | gen_load_spr(t1, SPR_MQ); | |
5130 | tcg_gen_andc_tl(t1, t1, t2); | |
5131 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5132 | gen_set_label(l2); | |
5133 | tcg_temp_free(t0); | |
5134 | tcg_temp_free(t1); | |
5135 | tcg_temp_free(t2); | |
76a66253 | 5136 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5137 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5138 | } |
5139 | ||
5140 | /* srq */ | |
99e300ef | 5141 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5142 | { |
7487953d AJ |
5143 | int l1 = gen_new_label(); |
5144 | TCGv t0 = tcg_temp_new(); | |
5145 | TCGv t1 = tcg_temp_new(); | |
5146 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5147 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5148 | tcg_gen_subfi_tl(t1, 32, t1); | |
5149 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5150 | tcg_gen_or_tl(t1, t0, t1); | |
5151 | gen_store_spr(SPR_MQ, t1); | |
5152 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5153 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5154 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5155 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5156 | gen_set_label(l1); | |
5157 | tcg_temp_free(t0); | |
5158 | tcg_temp_free(t1); | |
76a66253 | 5159 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5160 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5161 | } |
5162 | ||
5163 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5164 | |
54623277 | 5165 | /* dsa */ |
99e300ef | 5166 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5167 | { |
5168 | /* XXX: TODO */ | |
e06fcd75 | 5169 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5170 | } |
5171 | ||
5172 | /* esa */ | |
99e300ef | 5173 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5174 | { |
5175 | /* XXX: TODO */ | |
e06fcd75 | 5176 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5177 | } |
5178 | ||
5179 | /* mfrom */ | |
99e300ef | 5180 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5181 | { |
5182 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5183 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5184 | #else |
76db3ba4 | 5185 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5186 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5187 | return; |
5188 | } | |
cf02a65c | 5189 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5190 | #endif |
5191 | } | |
5192 | ||
5193 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5194 | |
54623277 | 5195 | /* tlbld */ |
e8eaa2c0 | 5196 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5197 | { |
5198 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5199 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5200 | #else |
76db3ba4 | 5201 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5202 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5203 | return; |
5204 | } | |
c6c7cf05 | 5205 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5206 | #endif |
5207 | } | |
5208 | ||
5209 | /* tlbli */ | |
e8eaa2c0 | 5210 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5211 | { |
5212 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5213 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5214 | #else |
76db3ba4 | 5215 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5216 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5217 | return; |
5218 | } | |
c6c7cf05 | 5219 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5220 | #endif |
5221 | } | |
5222 | ||
7dbe11ac | 5223 | /* 74xx TLB management */ |
e8eaa2c0 | 5224 | |
54623277 | 5225 | /* tlbld */ |
e8eaa2c0 | 5226 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5227 | { |
5228 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5229 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5230 | #else |
76db3ba4 | 5231 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5232 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5233 | return; |
5234 | } | |
c6c7cf05 | 5235 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5236 | #endif |
5237 | } | |
5238 | ||
5239 | /* tlbli */ | |
e8eaa2c0 | 5240 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5241 | { |
5242 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5243 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5244 | #else |
76db3ba4 | 5245 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5246 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5247 | return; |
5248 | } | |
c6c7cf05 | 5249 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5250 | #endif |
5251 | } | |
5252 | ||
76a66253 | 5253 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5254 | |
54623277 | 5255 | /* clf */ |
99e300ef | 5256 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5257 | { |
5258 | /* Cache line flush: implemented as no-op */ | |
5259 | } | |
5260 | ||
5261 | /* cli */ | |
99e300ef | 5262 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5263 | { |
7f75ffd3 | 5264 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5265 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5266 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5267 | #else |
76db3ba4 | 5268 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5269 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5270 | return; |
5271 | } | |
5272 | #endif | |
5273 | } | |
5274 | ||
5275 | /* dclst */ | |
99e300ef | 5276 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5277 | { |
5278 | /* Data cache line store: treated as no-op */ | |
5279 | } | |
5280 | ||
99e300ef | 5281 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5282 | { |
5283 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5284 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5285 | #else |
74d37793 AJ |
5286 | int ra = rA(ctx->opcode); |
5287 | int rd = rD(ctx->opcode); | |
5288 | TCGv t0; | |
76db3ba4 | 5289 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5290 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5291 | return; |
5292 | } | |
74d37793 | 5293 | t0 = tcg_temp_new(); |
76db3ba4 | 5294 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5295 | tcg_gen_shri_tl(t0, t0, 28); |
5296 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5297 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5298 | tcg_temp_free(t0); |
76a66253 | 5299 | if (ra != 0 && ra != rd) |
74d37793 | 5300 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5301 | #endif |
5302 | } | |
5303 | ||
99e300ef | 5304 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5305 | { |
5306 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5307 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5308 | #else |
22e0e173 | 5309 | TCGv t0; |
76db3ba4 | 5310 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5311 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5312 | return; |
5313 | } | |
22e0e173 | 5314 | t0 = tcg_temp_new(); |
76db3ba4 | 5315 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5316 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5317 | tcg_temp_free(t0); |
76a66253 JM |
5318 | #endif |
5319 | } | |
5320 | ||
99e300ef | 5321 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5322 | { |
5323 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5324 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5325 | #else |
76db3ba4 | 5326 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5327 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5328 | return; |
5329 | } | |
e5f17ac6 | 5330 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5331 | gen_sync_exception(ctx); |
76a66253 JM |
5332 | #endif |
5333 | } | |
5334 | ||
5335 | /* svc is not implemented for now */ | |
5336 | ||
5337 | /* POWER2 specific instructions */ | |
5338 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5339 | |
5340 | /* lfq */ | |
99e300ef | 5341 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5342 | { |
01a4afeb | 5343 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5344 | TCGv t0; |
5345 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5346 | t0 = tcg_temp_new(); | |
5347 | gen_addr_imm_index(ctx, t0, 0); | |
5348 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5349 | gen_addr_add(ctx, t0, t0, 8); | |
5350 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5351 | tcg_temp_free(t0); |
76a66253 JM |
5352 | } |
5353 | ||
5354 | /* lfqu */ | |
99e300ef | 5355 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5356 | { |
5357 | int ra = rA(ctx->opcode); | |
01a4afeb | 5358 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5359 | TCGv t0, t1; |
5360 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5361 | t0 = tcg_temp_new(); | |
5362 | t1 = tcg_temp_new(); | |
5363 | gen_addr_imm_index(ctx, t0, 0); | |
5364 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5365 | gen_addr_add(ctx, t1, t0, 8); | |
5366 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5367 | if (ra != 0) |
01a4afeb AJ |
5368 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5369 | tcg_temp_free(t0); | |
5370 | tcg_temp_free(t1); | |
76a66253 JM |
5371 | } |
5372 | ||
5373 | /* lfqux */ | |
99e300ef | 5374 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5375 | { |
5376 | int ra = rA(ctx->opcode); | |
01a4afeb | 5377 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5378 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5379 | TCGv t0, t1; | |
5380 | t0 = tcg_temp_new(); | |
5381 | gen_addr_reg_index(ctx, t0); | |
5382 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5383 | t1 = tcg_temp_new(); | |
5384 | gen_addr_add(ctx, t1, t0, 8); | |
5385 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5386 | tcg_temp_free(t1); | |
76a66253 | 5387 | if (ra != 0) |
01a4afeb AJ |
5388 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5389 | tcg_temp_free(t0); | |
76a66253 JM |
5390 | } |
5391 | ||
5392 | /* lfqx */ | |
99e300ef | 5393 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5394 | { |
01a4afeb | 5395 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5396 | TCGv t0; |
5397 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5398 | t0 = tcg_temp_new(); | |
5399 | gen_addr_reg_index(ctx, t0); | |
5400 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5401 | gen_addr_add(ctx, t0, t0, 8); | |
5402 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5403 | tcg_temp_free(t0); |
76a66253 JM |
5404 | } |
5405 | ||
5406 | /* stfq */ | |
99e300ef | 5407 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5408 | { |
01a4afeb | 5409 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5410 | TCGv t0; |
5411 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5412 | t0 = tcg_temp_new(); | |
5413 | gen_addr_imm_index(ctx, t0, 0); | |
5414 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5415 | gen_addr_add(ctx, t0, t0, 8); | |
5416 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5417 | tcg_temp_free(t0); |
76a66253 JM |
5418 | } |
5419 | ||
5420 | /* stfqu */ | |
99e300ef | 5421 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5422 | { |
5423 | int ra = rA(ctx->opcode); | |
01a4afeb | 5424 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5425 | TCGv t0, t1; |
5426 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5427 | t0 = tcg_temp_new(); | |
5428 | gen_addr_imm_index(ctx, t0, 0); | |
5429 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5430 | t1 = tcg_temp_new(); | |
5431 | gen_addr_add(ctx, t1, t0, 8); | |
5432 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5433 | tcg_temp_free(t1); | |
76a66253 | 5434 | if (ra != 0) |
01a4afeb AJ |
5435 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5436 | tcg_temp_free(t0); | |
76a66253 JM |
5437 | } |
5438 | ||
5439 | /* stfqux */ | |
99e300ef | 5440 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5441 | { |
5442 | int ra = rA(ctx->opcode); | |
01a4afeb | 5443 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5444 | TCGv t0, t1; |
5445 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5446 | t0 = tcg_temp_new(); | |
5447 | gen_addr_reg_index(ctx, t0); | |
5448 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5449 | t1 = tcg_temp_new(); | |
5450 | gen_addr_add(ctx, t1, t0, 8); | |
5451 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5452 | tcg_temp_free(t1); | |
76a66253 | 5453 | if (ra != 0) |
01a4afeb AJ |
5454 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5455 | tcg_temp_free(t0); | |
76a66253 JM |
5456 | } |
5457 | ||
5458 | /* stfqx */ | |
99e300ef | 5459 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5460 | { |
01a4afeb | 5461 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5462 | TCGv t0; |
5463 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5464 | t0 = tcg_temp_new(); | |
5465 | gen_addr_reg_index(ctx, t0); | |
5466 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5467 | gen_addr_add(ctx, t0, t0, 8); | |
5468 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5469 | tcg_temp_free(t0); |
76a66253 JM |
5470 | } |
5471 | ||
5472 | /* BookE specific instructions */ | |
99e300ef | 5473 | |
54623277 | 5474 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5475 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5476 | { |
5477 | /* XXX: TODO */ | |
e06fcd75 | 5478 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5479 | } |
5480 | ||
2662a059 | 5481 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5482 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5483 | { |
5484 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5485 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5486 | #else |
74d37793 | 5487 | TCGv t0; |
76db3ba4 | 5488 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5489 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5490 | return; |
5491 | } | |
ec72e276 | 5492 | t0 = tcg_temp_new(); |
76db3ba4 | 5493 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5494 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5495 | tcg_temp_free(t0); |
76a66253 JM |
5496 | #endif |
5497 | } | |
5498 | ||
5499 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5500 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5501 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5502 | { |
182608d4 AJ |
5503 | TCGv t0, t1; |
5504 | ||
a7812ae4 PB |
5505 | t0 = tcg_temp_local_new(); |
5506 | t1 = tcg_temp_local_new(); | |
182608d4 | 5507 | |
76a66253 JM |
5508 | switch (opc3 & 0x0D) { |
5509 | case 0x05: | |
5510 | /* macchw - macchw. - macchwo - macchwo. */ | |
5511 | /* macchws - macchws. - macchwso - macchwso. */ | |
5512 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5513 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5514 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5515 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5516 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5517 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5518 | break; |
5519 | case 0x04: | |
5520 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5521 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5522 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5523 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5524 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5525 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5526 | break; |
5527 | case 0x01: | |
5528 | /* machhw - machhw. - machhwo - machhwo. */ | |
5529 | /* machhws - machhws. - machhwso - machhwso. */ | |
5530 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5531 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5532 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5533 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5534 | tcg_gen_ext16s_tl(t0, t0); | |
5535 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5536 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5537 | break; |
5538 | case 0x00: | |
5539 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5540 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5541 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5542 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5543 | tcg_gen_ext16u_tl(t0, t0); | |
5544 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5545 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5546 | break; |
5547 | case 0x0D: | |
5548 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5549 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5550 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5551 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5552 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5553 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5554 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5555 | break; |
5556 | case 0x0C: | |
5557 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5558 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5559 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5560 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5561 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5562 | break; |
5563 | } | |
76a66253 | 5564 | if (opc2 & 0x04) { |
182608d4 AJ |
5565 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5566 | tcg_gen_mul_tl(t1, t0, t1); | |
5567 | if (opc2 & 0x02) { | |
5568 | /* nmultiply-and-accumulate (0x0E) */ | |
5569 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5570 | } else { | |
5571 | /* multiply-and-accumulate (0x0C) */ | |
5572 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5573 | } | |
5574 | ||
5575 | if (opc3 & 0x12) { | |
5576 | /* Check overflow and/or saturate */ | |
5577 | int l1 = gen_new_label(); | |
5578 | ||
5579 | if (opc3 & 0x10) { | |
5580 | /* Start with XER OV disabled, the most likely case */ | |
5581 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
5582 | } | |
5583 | if (opc3 & 0x01) { | |
5584 | /* Signed */ | |
5585 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5586 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5587 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5588 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5589 | if (opc3 & 0x02) { |
182608d4 AJ |
5590 | /* Saturate */ |
5591 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5592 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5593 | } | |
5594 | } else { | |
5595 | /* Unsigned */ | |
5596 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5597 | if (opc3 & 0x02) { |
182608d4 AJ |
5598 | /* Saturate */ |
5599 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5600 | } | |
5601 | } | |
5602 | if (opc3 & 0x10) { | |
5603 | /* Check overflow */ | |
5604 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
5605 | } | |
5606 | gen_set_label(l1); | |
5607 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5608 | } | |
5609 | } else { | |
5610 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5611 | } |
182608d4 AJ |
5612 | tcg_temp_free(t0); |
5613 | tcg_temp_free(t1); | |
76a66253 JM |
5614 | if (unlikely(Rc) != 0) { |
5615 | /* Update Rc0 */ | |
182608d4 | 5616 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5617 | } |
5618 | } | |
5619 | ||
a750fc0b | 5620 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5621 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5622 | { \ |
5623 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5624 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5625 | } | |
5626 | ||
5627 | /* macchw - macchw. */ | |
a750fc0b | 5628 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5629 | /* macchwo - macchwo. */ |
a750fc0b | 5630 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5631 | /* macchws - macchws. */ |
a750fc0b | 5632 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5633 | /* macchwso - macchwso. */ |
a750fc0b | 5634 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5635 | /* macchwsu - macchwsu. */ |
a750fc0b | 5636 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5637 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5638 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5639 | /* macchwu - macchwu. */ |
a750fc0b | 5640 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5641 | /* macchwuo - macchwuo. */ |
a750fc0b | 5642 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5643 | /* machhw - machhw. */ |
a750fc0b | 5644 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5645 | /* machhwo - machhwo. */ |
a750fc0b | 5646 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5647 | /* machhws - machhws. */ |
a750fc0b | 5648 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5649 | /* machhwso - machhwso. */ |
a750fc0b | 5650 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5651 | /* machhwsu - machhwsu. */ |
a750fc0b | 5652 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5653 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5654 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5655 | /* machhwu - machhwu. */ |
a750fc0b | 5656 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5657 | /* machhwuo - machhwuo. */ |
a750fc0b | 5658 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5659 | /* maclhw - maclhw. */ |
a750fc0b | 5660 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5661 | /* maclhwo - maclhwo. */ |
a750fc0b | 5662 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5663 | /* maclhws - maclhws. */ |
a750fc0b | 5664 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5665 | /* maclhwso - maclhwso. */ |
a750fc0b | 5666 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5667 | /* maclhwu - maclhwu. */ |
a750fc0b | 5668 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5669 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5670 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5671 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5672 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5673 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5674 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5675 | /* nmacchw - nmacchw. */ |
a750fc0b | 5676 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5677 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5678 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5679 | /* nmacchws - nmacchws. */ |
a750fc0b | 5680 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5681 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5682 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5683 | /* nmachhw - nmachhw. */ |
a750fc0b | 5684 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5685 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5686 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5687 | /* nmachhws - nmachhws. */ |
a750fc0b | 5688 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5689 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5690 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5691 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5692 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5693 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5694 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5695 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5696 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5697 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5698 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5699 | |
5700 | /* mulchw - mulchw. */ | |
a750fc0b | 5701 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5702 | /* mulchwu - mulchwu. */ |
a750fc0b | 5703 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5704 | /* mulhhw - mulhhw. */ |
a750fc0b | 5705 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5706 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5707 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5708 | /* mullhw - mullhw. */ |
a750fc0b | 5709 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5710 | /* mullhwu - mullhwu. */ |
a750fc0b | 5711 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5712 | |
5713 | /* mfdcr */ | |
99e300ef | 5714 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5715 | { |
5716 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5717 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5718 | #else |
06dca6a7 | 5719 | TCGv dcrn; |
76db3ba4 | 5720 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5721 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5722 | return; |
5723 | } | |
06dca6a7 AJ |
5724 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5725 | gen_update_nip(ctx, ctx->nip - 4); | |
5726 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5727 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5728 | tcg_temp_free(dcrn); |
76a66253 JM |
5729 | #endif |
5730 | } | |
5731 | ||
5732 | /* mtdcr */ | |
99e300ef | 5733 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5734 | { |
5735 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5736 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5737 | #else |
06dca6a7 | 5738 | TCGv dcrn; |
76db3ba4 | 5739 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5740 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5741 | return; |
5742 | } | |
06dca6a7 AJ |
5743 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5744 | gen_update_nip(ctx, ctx->nip - 4); | |
5745 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 5746 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5747 | tcg_temp_free(dcrn); |
a42bd6cc JM |
5748 | #endif |
5749 | } | |
5750 | ||
5751 | /* mfdcrx */ | |
2662a059 | 5752 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5753 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5754 | { |
5755 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5756 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5757 | #else |
76db3ba4 | 5758 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5759 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5760 | return; |
5761 | } | |
06dca6a7 AJ |
5762 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5763 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5764 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5765 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5766 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
5767 | #endif |
5768 | } | |
5769 | ||
5770 | /* mtdcrx */ | |
2662a059 | 5771 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5772 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5773 | { |
5774 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5775 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5776 | #else |
76db3ba4 | 5777 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5778 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5779 | return; |
5780 | } | |
06dca6a7 AJ |
5781 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5782 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5783 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5784 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5785 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
5786 | #endif |
5787 | } | |
5788 | ||
a750fc0b | 5789 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5790 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5791 | { |
06dca6a7 AJ |
5792 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5793 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
5794 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5795 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5796 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5797 | } | |
5798 | ||
5799 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5800 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5801 | { |
06dca6a7 AJ |
5802 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5803 | gen_update_nip(ctx, ctx->nip - 4); | |
975e5463 | 5804 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5805 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5806 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5807 | } | |
5808 | ||
76a66253 | 5809 | /* dccci */ |
99e300ef | 5810 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
5811 | { |
5812 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5813 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5814 | #else |
76db3ba4 | 5815 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5816 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5817 | return; |
5818 | } | |
5819 | /* interpreted as no-op */ | |
5820 | #endif | |
5821 | } | |
5822 | ||
5823 | /* dcread */ | |
99e300ef | 5824 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5825 | { |
5826 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5827 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5828 | #else |
b61f2753 | 5829 | TCGv EA, val; |
76db3ba4 | 5830 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5831 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5832 | return; |
5833 | } | |
76db3ba4 | 5834 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5835 | EA = tcg_temp_new(); |
76db3ba4 | 5836 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5837 | val = tcg_temp_new(); |
76db3ba4 | 5838 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5839 | tcg_temp_free(val); |
5840 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5841 | tcg_temp_free(EA); | |
76a66253 JM |
5842 | #endif |
5843 | } | |
5844 | ||
5845 | /* icbt */ | |
e8eaa2c0 | 5846 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5847 | { |
5848 | /* interpreted as no-op */ | |
5849 | /* XXX: specification say this is treated as a load by the MMU | |
5850 | * but does not generate any exception | |
5851 | */ | |
5852 | } | |
5853 | ||
5854 | /* iccci */ | |
99e300ef | 5855 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
5856 | { |
5857 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5858 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5859 | #else |
76db3ba4 | 5860 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5861 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5862 | return; |
5863 | } | |
5864 | /* interpreted as no-op */ | |
5865 | #endif | |
5866 | } | |
5867 | ||
5868 | /* icread */ | |
99e300ef | 5869 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
5870 | { |
5871 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5872 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5873 | #else |
76db3ba4 | 5874 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5875 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5876 | return; |
5877 | } | |
5878 | /* interpreted as no-op */ | |
5879 | #endif | |
5880 | } | |
5881 | ||
76db3ba4 | 5882 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 5883 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5884 | { |
5885 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5886 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5887 | #else |
76db3ba4 | 5888 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5889 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5890 | return; |
5891 | } | |
5892 | /* Restore CPU state */ | |
e5f17ac6 | 5893 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 5894 | gen_sync_exception(ctx); |
a42bd6cc JM |
5895 | #endif |
5896 | } | |
5897 | ||
99e300ef | 5898 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5899 | { |
5900 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5901 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5902 | #else |
76db3ba4 | 5903 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5904 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5905 | return; |
5906 | } | |
5907 | /* Restore CPU state */ | |
e5f17ac6 | 5908 | gen_helper_rfci(cpu_env); |
e06fcd75 | 5909 | gen_sync_exception(ctx); |
a42bd6cc JM |
5910 | #endif |
5911 | } | |
5912 | ||
5913 | /* BookE specific */ | |
99e300ef | 5914 | |
54623277 | 5915 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5916 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5917 | { |
5918 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5919 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5920 | #else |
76db3ba4 | 5921 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5922 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5923 | return; |
5924 | } | |
5925 | /* Restore CPU state */ | |
e5f17ac6 | 5926 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 5927 | gen_sync_exception(ctx); |
76a66253 JM |
5928 | #endif |
5929 | } | |
5930 | ||
2662a059 | 5931 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5932 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5933 | { |
5934 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5935 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 5936 | #else |
76db3ba4 | 5937 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5938 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
5939 | return; |
5940 | } | |
5941 | /* Restore CPU state */ | |
e5f17ac6 | 5942 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 5943 | gen_sync_exception(ctx); |
a42bd6cc JM |
5944 | #endif |
5945 | } | |
5eb7995e | 5946 | |
d9bce9d9 | 5947 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5948 | |
54623277 | 5949 | /* tlbre */ |
e8eaa2c0 | 5950 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5951 | { |
5952 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5953 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5954 | #else |
76db3ba4 | 5955 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5956 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5957 | return; |
5958 | } | |
5959 | switch (rB(ctx->opcode)) { | |
5960 | case 0: | |
c6c7cf05 BS |
5961 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5962 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5963 | break; |
5964 | case 1: | |
c6c7cf05 BS |
5965 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5966 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5967 | break; |
5968 | default: | |
e06fcd75 | 5969 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5970 | break; |
9a64fbe4 | 5971 | } |
76a66253 JM |
5972 | #endif |
5973 | } | |
5974 | ||
d9bce9d9 | 5975 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5976 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5977 | { |
5978 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5979 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5980 | #else |
74d37793 | 5981 | TCGv t0; |
76db3ba4 | 5982 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5983 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5984 | return; |
5985 | } | |
74d37793 | 5986 | t0 = tcg_temp_new(); |
76db3ba4 | 5987 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5988 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
5989 | tcg_temp_free(t0); |
5990 | if (Rc(ctx->opcode)) { | |
5991 | int l1 = gen_new_label(); | |
5992 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
5993 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
5994 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
5995 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); | |
5996 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5997 | gen_set_label(l1); | |
5998 | } | |
76a66253 | 5999 | #endif |
79aceca5 FB |
6000 | } |
6001 | ||
76a66253 | 6002 | /* tlbwe */ |
e8eaa2c0 | 6003 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6004 | { |
76a66253 | 6005 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 6006 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6007 | #else |
76db3ba4 | 6008 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6009 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6010 | return; |
6011 | } | |
6012 | switch (rB(ctx->opcode)) { | |
6013 | case 0: | |
c6c7cf05 BS |
6014 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6015 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6016 | break; |
6017 | case 1: | |
c6c7cf05 BS |
6018 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6019 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6020 | break; |
6021 | default: | |
e06fcd75 | 6022 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6023 | break; |
9a64fbe4 | 6024 | } |
76a66253 JM |
6025 | #endif |
6026 | } | |
6027 | ||
a4bb6c3e | 6028 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6029 | |
54623277 | 6030 | /* tlbre */ |
e8eaa2c0 | 6031 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6032 | { |
6033 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6034 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6035 | #else |
76db3ba4 | 6036 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6037 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6038 | return; |
6039 | } | |
6040 | switch (rB(ctx->opcode)) { | |
6041 | case 0: | |
5eb7995e | 6042 | case 1: |
5eb7995e | 6043 | case 2: |
74d37793 AJ |
6044 | { |
6045 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6046 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6047 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6048 | tcg_temp_free_i32(t0); |
6049 | } | |
5eb7995e JM |
6050 | break; |
6051 | default: | |
e06fcd75 | 6052 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6053 | break; |
6054 | } | |
6055 | #endif | |
6056 | } | |
6057 | ||
6058 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6059 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6060 | { |
6061 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6062 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6063 | #else |
74d37793 | 6064 | TCGv t0; |
76db3ba4 | 6065 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6066 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6067 | return; |
6068 | } | |
74d37793 | 6069 | t0 = tcg_temp_new(); |
76db3ba4 | 6070 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6071 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6072 | tcg_temp_free(t0); |
6073 | if (Rc(ctx->opcode)) { | |
6074 | int l1 = gen_new_label(); | |
6075 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
6076 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
6077 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
6078 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); | |
6079 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6080 | gen_set_label(l1); | |
6081 | } | |
5eb7995e JM |
6082 | #endif |
6083 | } | |
6084 | ||
6085 | /* tlbwe */ | |
e8eaa2c0 | 6086 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6087 | { |
6088 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6089 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6090 | #else |
76db3ba4 | 6091 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6092 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6093 | return; |
6094 | } | |
6095 | switch (rB(ctx->opcode)) { | |
6096 | case 0: | |
5eb7995e | 6097 | case 1: |
5eb7995e | 6098 | case 2: |
74d37793 AJ |
6099 | { |
6100 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6101 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6102 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6103 | tcg_temp_free_i32(t0); |
6104 | } | |
5eb7995e JM |
6105 | break; |
6106 | default: | |
e06fcd75 | 6107 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6108 | break; |
6109 | } | |
6110 | #endif | |
6111 | } | |
6112 | ||
01662f3e AG |
6113 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6114 | ||
6115 | /* tlbre */ | |
6116 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6117 | { | |
6118 | #if defined(CONFIG_USER_ONLY) | |
6119 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6120 | #else | |
6121 | if (unlikely(!ctx->mem_idx)) { | |
6122 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6123 | return; | |
6124 | } | |
6125 | ||
c6c7cf05 | 6126 | gen_helper_booke206_tlbre(cpu_env); |
01662f3e AG |
6127 | #endif |
6128 | } | |
6129 | ||
6130 | /* tlbsx - tlbsx. */ | |
6131 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6132 | { | |
6133 | #if defined(CONFIG_USER_ONLY) | |
6134 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6135 | #else | |
6136 | TCGv t0; | |
6137 | if (unlikely(!ctx->mem_idx)) { | |
6138 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6139 | return; | |
6140 | } | |
6141 | ||
6142 | if (rA(ctx->opcode)) { | |
6143 | t0 = tcg_temp_new(); | |
6144 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6145 | } else { | |
6146 | t0 = tcg_const_tl(0); | |
6147 | } | |
6148 | ||
6149 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6150 | gen_helper_booke206_tlbsx(cpu_env, t0); |
01662f3e AG |
6151 | #endif |
6152 | } | |
6153 | ||
6154 | /* tlbwe */ | |
6155 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6156 | { | |
6157 | #if defined(CONFIG_USER_ONLY) | |
6158 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6159 | #else | |
6160 | if (unlikely(!ctx->mem_idx)) { | |
6161 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6162 | return; | |
6163 | } | |
3f162d11 | 6164 | gen_update_nip(ctx, ctx->nip - 4); |
c6c7cf05 | 6165 | gen_helper_booke206_tlbwe(cpu_env); |
01662f3e AG |
6166 | #endif |
6167 | } | |
6168 | ||
6169 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6170 | { | |
6171 | #if defined(CONFIG_USER_ONLY) | |
6172 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6173 | #else | |
6174 | TCGv t0; | |
6175 | if (unlikely(!ctx->mem_idx)) { | |
6176 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6177 | return; | |
6178 | } | |
6179 | ||
6180 | t0 = tcg_temp_new(); | |
6181 | gen_addr_reg_index(ctx, t0); | |
6182 | ||
c6c7cf05 | 6183 | gen_helper_booke206_tlbivax(cpu_env, t0); |
01662f3e AG |
6184 | #endif |
6185 | } | |
6186 | ||
6d3db821 AG |
6187 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6188 | { | |
6189 | #if defined(CONFIG_USER_ONLY) | |
6190 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6191 | #else | |
6192 | TCGv t0; | |
6193 | if (unlikely(!ctx->mem_idx)) { | |
6194 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6195 | return; | |
6196 | } | |
6197 | ||
6198 | t0 = tcg_temp_new(); | |
6199 | gen_addr_reg_index(ctx, t0); | |
6200 | ||
6201 | switch((ctx->opcode >> 21) & 0x3) { | |
6202 | case 0: | |
c6c7cf05 | 6203 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6204 | break; |
6205 | case 1: | |
c6c7cf05 | 6206 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6207 | break; |
6208 | case 3: | |
c6c7cf05 | 6209 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6210 | break; |
6211 | default: | |
6212 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6213 | break; | |
6214 | } | |
6215 | ||
6216 | tcg_temp_free(t0); | |
6217 | #endif | |
6218 | } | |
6219 | ||
01662f3e | 6220 | |
76a66253 | 6221 | /* wrtee */ |
99e300ef | 6222 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6223 | { |
6224 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6225 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6226 | #else |
6527f6ea | 6227 | TCGv t0; |
76db3ba4 | 6228 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6229 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6230 | return; |
6231 | } | |
6527f6ea AJ |
6232 | t0 = tcg_temp_new(); |
6233 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6234 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6235 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6236 | tcg_temp_free(t0); | |
dee96f6c JM |
6237 | /* Stop translation to have a chance to raise an exception |
6238 | * if we just set msr_ee to 1 | |
6239 | */ | |
e06fcd75 | 6240 | gen_stop_exception(ctx); |
76a66253 JM |
6241 | #endif |
6242 | } | |
6243 | ||
6244 | /* wrteei */ | |
99e300ef | 6245 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6246 | { |
6247 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6248 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6249 | #else |
76db3ba4 | 6250 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6251 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6252 | return; |
6253 | } | |
fbe73008 | 6254 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6255 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6256 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6257 | gen_stop_exception(ctx); |
6527f6ea | 6258 | } else { |
1b6e5f99 | 6259 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6260 | } |
76a66253 JM |
6261 | #endif |
6262 | } | |
6263 | ||
08e46e54 | 6264 | /* PowerPC 440 specific instructions */ |
99e300ef | 6265 | |
54623277 | 6266 | /* dlmzb */ |
99e300ef | 6267 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6268 | { |
ef0d51af | 6269 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6270 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6271 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6272 | tcg_temp_free_i32(t0); |
76a66253 JM |
6273 | } |
6274 | ||
6275 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6276 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6277 | { |
6278 | /* interpreted as no-op */ | |
6279 | } | |
6280 | ||
6281 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6282 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6283 | { |
6284 | /* interpreted as no-op */ | |
6285 | } | |
6286 | ||
6287 | /* icbt */ | |
e8eaa2c0 | 6288 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6289 | { |
6290 | /* interpreted as no-op */ | |
6291 | /* XXX: specification say this is treated as a load by the MMU | |
6292 | * but does not generate any exception | |
6293 | */ | |
79aceca5 FB |
6294 | } |
6295 | ||
9e0b5cb1 AG |
6296 | /* Embedded.Processor Control */ |
6297 | ||
6298 | static void gen_msgclr(DisasContext *ctx) | |
6299 | { | |
6300 | #if defined(CONFIG_USER_ONLY) | |
6301 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6302 | #else | |
6303 | if (unlikely(ctx->mem_idx == 0)) { | |
6304 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6305 | return; | |
6306 | } | |
6307 | ||
e5f17ac6 | 6308 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9e0b5cb1 AG |
6309 | #endif |
6310 | } | |
6311 | ||
d5d11a39 AG |
6312 | static void gen_msgsnd(DisasContext *ctx) |
6313 | { | |
6314 | #if defined(CONFIG_USER_ONLY) | |
6315 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6316 | #else | |
6317 | if (unlikely(ctx->mem_idx == 0)) { | |
6318 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6319 | return; | |
6320 | } | |
6321 | ||
6322 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6323 | #endif | |
6324 | } | |
6325 | ||
a9d9eb8f JM |
6326 | /*** Altivec vector extension ***/ |
6327 | /* Altivec registers moves */ | |
a9d9eb8f | 6328 | |
636aa200 | 6329 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6330 | { |
e4704b3b | 6331 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6332 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6333 | return r; | |
6334 | } | |
6335 | ||
a9d9eb8f | 6336 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6337 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6338 | { \ |
fe1e5c53 | 6339 | TCGv EA; \ |
a9d9eb8f | 6340 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6341 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6342 | return; \ |
6343 | } \ | |
76db3ba4 | 6344 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6345 | EA = tcg_temp_new(); \ |
76db3ba4 | 6346 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6347 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6348 | if (ctx->le_mode) { \ |
6349 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6350 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6351 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6352 | } else { \ |
76db3ba4 | 6353 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6354 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6355 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6356 | } \ |
6357 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6358 | } |
6359 | ||
6360 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6361 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6362 | { \ |
fe1e5c53 | 6363 | TCGv EA; \ |
a9d9eb8f | 6364 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6365 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6366 | return; \ |
6367 | } \ | |
76db3ba4 | 6368 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6369 | EA = tcg_temp_new(); \ |
76db3ba4 | 6370 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6371 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6372 | if (ctx->le_mode) { \ |
6373 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6374 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6375 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6376 | } else { \ |
76db3ba4 | 6377 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6378 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6379 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6380 | } \ |
6381 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6382 | } |
6383 | ||
cbfb6ae9 | 6384 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef | 6385 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6386 | { \ |
6387 | TCGv EA; \ | |
6388 | TCGv_ptr rs; \ | |
6389 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6390 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6391 | return; \ | |
6392 | } \ | |
6393 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6394 | EA = tcg_temp_new(); \ | |
6395 | gen_addr_reg_index(ctx, EA); \ | |
6396 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6397 | gen_helper_lve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6398 | tcg_temp_free(EA); \ |
6399 | tcg_temp_free_ptr(rs); \ | |
6400 | } | |
6401 | ||
6402 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef | 6403 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6404 | { \ |
6405 | TCGv EA; \ | |
6406 | TCGv_ptr rs; \ | |
6407 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6408 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6409 | return; \ | |
6410 | } \ | |
6411 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6412 | EA = tcg_temp_new(); \ | |
6413 | gen_addr_reg_index(ctx, EA); \ | |
6414 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6415 | gen_helper_stve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6416 | tcg_temp_free(EA); \ |
6417 | tcg_temp_free_ptr(rs); \ | |
6418 | } | |
6419 | ||
fe1e5c53 | 6420 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6421 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6422 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6423 | |
cbfb6ae9 AJ |
6424 | GEN_VR_LVE(bx, 0x07, 0x00); |
6425 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6426 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6427 | ||
fe1e5c53 | 6428 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6429 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6430 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6431 | |
cbfb6ae9 AJ |
6432 | GEN_VR_STVE(bx, 0x07, 0x04); |
6433 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6434 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6435 | ||
99e300ef | 6436 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6437 | { |
6438 | TCGv_ptr rd; | |
6439 | TCGv EA; | |
6440 | if (unlikely(!ctx->altivec_enabled)) { | |
6441 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6442 | return; | |
6443 | } | |
6444 | EA = tcg_temp_new(); | |
6445 | gen_addr_reg_index(ctx, EA); | |
6446 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6447 | gen_helper_lvsl(rd, EA); | |
6448 | tcg_temp_free(EA); | |
6449 | tcg_temp_free_ptr(rd); | |
6450 | } | |
6451 | ||
99e300ef | 6452 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6453 | { |
6454 | TCGv_ptr rd; | |
6455 | TCGv EA; | |
6456 | if (unlikely(!ctx->altivec_enabled)) { | |
6457 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6458 | return; | |
6459 | } | |
6460 | EA = tcg_temp_new(); | |
6461 | gen_addr_reg_index(ctx, EA); | |
6462 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6463 | gen_helper_lvsr(rd, EA); | |
6464 | tcg_temp_free(EA); | |
6465 | tcg_temp_free_ptr(rd); | |
6466 | } | |
6467 | ||
99e300ef | 6468 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6469 | { |
6470 | TCGv_i32 t; | |
6471 | if (unlikely(!ctx->altivec_enabled)) { | |
6472 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6473 | return; | |
6474 | } | |
6475 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6476 | t = tcg_temp_new_i32(); | |
1328c2bf | 6477 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
785f451b | 6478 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
fce5ecb7 | 6479 | tcg_temp_free_i32(t); |
785f451b AJ |
6480 | } |
6481 | ||
99e300ef | 6482 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6483 | { |
6e87b7c7 | 6484 | TCGv_ptr p; |
785f451b AJ |
6485 | if (unlikely(!ctx->altivec_enabled)) { |
6486 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6487 | return; | |
6488 | } | |
6e87b7c7 | 6489 | p = gen_avr_ptr(rD(ctx->opcode)); |
d15f74fb | 6490 | gen_helper_mtvscr(cpu_env, p); |
6e87b7c7 | 6491 | tcg_temp_free_ptr(p); |
785f451b AJ |
6492 | } |
6493 | ||
7a9b96cf AJ |
6494 | /* Logical operations */ |
6495 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6496 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6497 | { \ |
6498 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6499 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6500 | return; \ | |
6501 | } \ | |
6502 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6503 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6504 | } | |
6505 | ||
6506 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6507 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6508 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6509 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6510 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
6511 | ||
8e27dd6f | 6512 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6513 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6514 | { \ |
6515 | TCGv_ptr ra, rb, rd; \ | |
6516 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6517 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6518 | return; \ | |
6519 | } \ | |
6520 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6521 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6522 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6523 | gen_helper_##name (rd, ra, rb); \ | |
6524 | tcg_temp_free_ptr(ra); \ | |
6525 | tcg_temp_free_ptr(rb); \ | |
6526 | tcg_temp_free_ptr(rd); \ | |
6527 | } | |
6528 | ||
d15f74fb BS |
6529 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
6530 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6531 | { \ | |
6532 | TCGv_ptr ra, rb, rd; \ | |
6533 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6534 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6535 | return; \ | |
6536 | } \ | |
6537 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6538 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6539 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
54cddd21 | 6540 | gen_helper_##name(cpu_env, rd, ra, rb); \ |
d15f74fb BS |
6541 | tcg_temp_free_ptr(ra); \ |
6542 | tcg_temp_free_ptr(rb); \ | |
6543 | tcg_temp_free_ptr(rd); \ | |
6544 | } | |
6545 | ||
7872c51c AJ |
6546 | GEN_VXFORM(vaddubm, 0, 0); |
6547 | GEN_VXFORM(vadduhm, 0, 1); | |
6548 | GEN_VXFORM(vadduwm, 0, 2); | |
6549 | GEN_VXFORM(vsububm, 0, 16); | |
6550 | GEN_VXFORM(vsubuhm, 0, 17); | |
6551 | GEN_VXFORM(vsubuwm, 0, 18); | |
e4039339 AJ |
6552 | GEN_VXFORM(vmaxub, 1, 0); |
6553 | GEN_VXFORM(vmaxuh, 1, 1); | |
6554 | GEN_VXFORM(vmaxuw, 1, 2); | |
6555 | GEN_VXFORM(vmaxsb, 1, 4); | |
6556 | GEN_VXFORM(vmaxsh, 1, 5); | |
6557 | GEN_VXFORM(vmaxsw, 1, 6); | |
6558 | GEN_VXFORM(vminub, 1, 8); | |
6559 | GEN_VXFORM(vminuh, 1, 9); | |
6560 | GEN_VXFORM(vminuw, 1, 10); | |
6561 | GEN_VXFORM(vminsb, 1, 12); | |
6562 | GEN_VXFORM(vminsh, 1, 13); | |
6563 | GEN_VXFORM(vminsw, 1, 14); | |
fab3cbe9 AJ |
6564 | GEN_VXFORM(vavgub, 1, 16); |
6565 | GEN_VXFORM(vavguh, 1, 17); | |
6566 | GEN_VXFORM(vavguw, 1, 18); | |
6567 | GEN_VXFORM(vavgsb, 1, 20); | |
6568 | GEN_VXFORM(vavgsh, 1, 21); | |
6569 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6570 | GEN_VXFORM(vmrghb, 6, 0); |
6571 | GEN_VXFORM(vmrghh, 6, 1); | |
6572 | GEN_VXFORM(vmrghw, 6, 2); | |
6573 | GEN_VXFORM(vmrglb, 6, 4); | |
6574 | GEN_VXFORM(vmrglh, 6, 5); | |
6575 | GEN_VXFORM(vmrglw, 6, 6); | |
2c277908 AJ |
6576 | GEN_VXFORM(vmuloub, 4, 0); |
6577 | GEN_VXFORM(vmulouh, 4, 1); | |
6578 | GEN_VXFORM(vmulosb, 4, 4); | |
6579 | GEN_VXFORM(vmulosh, 4, 5); | |
6580 | GEN_VXFORM(vmuleub, 4, 8); | |
6581 | GEN_VXFORM(vmuleuh, 4, 9); | |
6582 | GEN_VXFORM(vmulesb, 4, 12); | |
6583 | GEN_VXFORM(vmulesh, 4, 13); | |
d79f0809 AJ |
6584 | GEN_VXFORM(vslb, 2, 4); |
6585 | GEN_VXFORM(vslh, 2, 5); | |
6586 | GEN_VXFORM(vslw, 2, 6); | |
07ef34c3 AJ |
6587 | GEN_VXFORM(vsrb, 2, 8); |
6588 | GEN_VXFORM(vsrh, 2, 9); | |
6589 | GEN_VXFORM(vsrw, 2, 10); | |
6590 | GEN_VXFORM(vsrab, 2, 12); | |
6591 | GEN_VXFORM(vsrah, 2, 13); | |
6592 | GEN_VXFORM(vsraw, 2, 14); | |
7b239bec AJ |
6593 | GEN_VXFORM(vslo, 6, 16); |
6594 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
6595 | GEN_VXFORM(vaddcuw, 0, 6); |
6596 | GEN_VXFORM(vsubcuw, 0, 22); | |
d15f74fb BS |
6597 | GEN_VXFORM_ENV(vaddubs, 0, 8); |
6598 | GEN_VXFORM_ENV(vadduhs, 0, 9); | |
6599 | GEN_VXFORM_ENV(vadduws, 0, 10); | |
6600 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
6601 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
6602 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
6603 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
6604 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
6605 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
6606 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
6607 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
6608 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
5e1d0985 AJ |
6609 | GEN_VXFORM(vrlb, 2, 0); |
6610 | GEN_VXFORM(vrlh, 2, 1); | |
6611 | GEN_VXFORM(vrlw, 2, 2); | |
d9430add AJ |
6612 | GEN_VXFORM(vsl, 2, 7); |
6613 | GEN_VXFORM(vsr, 2, 11); | |
d15f74fb BS |
6614 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
6615 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
6616 | GEN_VXFORM_ENV(vpkuhus, 7, 2); | |
6617 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
6618 | GEN_VXFORM_ENV(vpkshus, 7, 4); | |
6619 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
6620 | GEN_VXFORM_ENV(vpkshss, 7, 6); | |
6621 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
1dd9ffb9 | 6622 | GEN_VXFORM(vpkpx, 7, 12); |
d15f74fb BS |
6623 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
6624 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
6625 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
6626 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
6627 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
6628 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
6629 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
6630 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
6631 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
fab3cbe9 | 6632 | |
0cbcd906 | 6633 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 6634 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
6635 | { \ |
6636 | TCGv_ptr ra, rb, rd; \ | |
6637 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6638 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6639 | return; \ | |
6640 | } \ | |
6641 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6642 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6643 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
d15f74fb | 6644 | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
0cbcd906 AJ |
6645 | tcg_temp_free_ptr(ra); \ |
6646 | tcg_temp_free_ptr(rb); \ | |
6647 | tcg_temp_free_ptr(rd); \ | |
6648 | } | |
6649 | ||
6650 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
6651 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
6652 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
6653 | ||
1add6e23 AJ |
6654 | GEN_VXRFORM(vcmpequb, 3, 0) |
6655 | GEN_VXRFORM(vcmpequh, 3, 1) | |
6656 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6657 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
6658 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
6659 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6660 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
6661 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
6662 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
819ca121 AJ |
6663 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6664 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
6665 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
6666 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 6667 | |
c026766b | 6668 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6669 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
6670 | { \ |
6671 | TCGv_ptr rd; \ | |
6672 | TCGv_i32 simm; \ | |
6673 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6674 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6675 | return; \ | |
6676 | } \ | |
6677 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6678 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6679 | gen_helper_##name (rd, simm); \ | |
6680 | tcg_temp_free_i32(simm); \ | |
6681 | tcg_temp_free_ptr(rd); \ | |
6682 | } | |
6683 | ||
6684 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
6685 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
6686 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
6687 | ||
de5f2484 | 6688 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 6689 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
6690 | { \ |
6691 | TCGv_ptr rb, rd; \ | |
6692 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6693 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6694 | return; \ | |
6695 | } \ | |
6696 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6697 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6698 | gen_helper_##name (rd, rb); \ | |
6699 | tcg_temp_free_ptr(rb); \ | |
6700 | tcg_temp_free_ptr(rd); \ | |
6701 | } | |
6702 | ||
d15f74fb BS |
6703 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ |
6704 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6705 | { \ | |
6706 | TCGv_ptr rb, rd; \ | |
6707 | \ | |
6708 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6709 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6710 | return; \ | |
6711 | } \ | |
6712 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6713 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6714 | gen_helper_##name(cpu_env, rd, rb); \ | |
6715 | tcg_temp_free_ptr(rb); \ | |
6716 | tcg_temp_free_ptr(rd); \ | |
6717 | } | |
6718 | ||
6cf1c6e5 AJ |
6719 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6720 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
6721 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
6722 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
79f85c3a AJ |
6723 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6724 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
d15f74fb BS |
6725 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
6726 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
6727 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
6728 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
6729 | GEN_VXFORM_NOA_ENV(vrfim, 5, 8); | |
6730 | GEN_VXFORM_NOA_ENV(vrfin, 5, 9); | |
6731 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
6732 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 11); | |
79f85c3a | 6733 | |
21d21583 | 6734 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 6735 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
6736 | { \ |
6737 | TCGv_ptr rd; \ | |
6738 | TCGv_i32 simm; \ | |
6739 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6740 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6741 | return; \ | |
6742 | } \ | |
6743 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6744 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6745 | gen_helper_##name (rd, simm); \ | |
6746 | tcg_temp_free_i32(simm); \ | |
6747 | tcg_temp_free_ptr(rd); \ | |
6748 | } | |
6749 | ||
27a4edb3 | 6750 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 6751 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
6752 | { \ |
6753 | TCGv_ptr rb, rd; \ | |
6754 | TCGv_i32 uimm; \ | |
6755 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6756 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6757 | return; \ | |
6758 | } \ | |
6759 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6760 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6761 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6762 | gen_helper_##name (rd, rb, uimm); \ | |
6763 | tcg_temp_free_i32(uimm); \ | |
6764 | tcg_temp_free_ptr(rb); \ | |
6765 | tcg_temp_free_ptr(rd); \ | |
6766 | } | |
6767 | ||
d15f74fb BS |
6768 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
6769 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6770 | { \ | |
6771 | TCGv_ptr rb, rd; \ | |
6772 | TCGv_i32 uimm; \ | |
6773 | \ | |
6774 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6775 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6776 | return; \ | |
6777 | } \ | |
6778 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6779 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6780 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6781 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
6782 | tcg_temp_free_i32(uimm); \ | |
6783 | tcg_temp_free_ptr(rb); \ | |
6784 | tcg_temp_free_ptr(rd); \ | |
6785 | } | |
6786 | ||
e4e6bee7 AJ |
6787 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6788 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
6789 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
d15f74fb BS |
6790 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
6791 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
6792 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
6793 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
e4e6bee7 | 6794 | |
99e300ef | 6795 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
6796 | { |
6797 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 6798 | TCGv_i32 sh; |
cd633b10 AJ |
6799 | if (unlikely(!ctx->altivec_enabled)) { |
6800 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6801 | return; | |
6802 | } | |
6803 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6804 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6805 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6806 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
6807 | gen_helper_vsldoi (rd, ra, rb, sh); | |
6808 | tcg_temp_free_ptr(ra); | |
6809 | tcg_temp_free_ptr(rb); | |
6810 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 6811 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
6812 | } |
6813 | ||
707cec33 | 6814 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
d15f74fb | 6815 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
6816 | { \ |
6817 | TCGv_ptr ra, rb, rc, rd; \ | |
6818 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6819 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6820 | return; \ | |
6821 | } \ | |
6822 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6823 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6824 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6825 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6826 | if (Rc(ctx->opcode)) { \ | |
d15f74fb | 6827 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
707cec33 | 6828 | } else { \ |
d15f74fb | 6829 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
707cec33 AJ |
6830 | } \ |
6831 | tcg_temp_free_ptr(ra); \ | |
6832 | tcg_temp_free_ptr(rb); \ | |
6833 | tcg_temp_free_ptr(rc); \ | |
6834 | tcg_temp_free_ptr(rd); \ | |
6835 | } | |
6836 | ||
b161ae27 AJ |
6837 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
6838 | ||
99e300ef | 6839 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
6840 | { |
6841 | TCGv_ptr ra, rb, rc, rd; | |
6842 | if (unlikely(!ctx->altivec_enabled)) { | |
6843 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6844 | return; | |
6845 | } | |
6846 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6847 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6848 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
6849 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6850 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
6851 | tcg_temp_free_ptr(ra); | |
6852 | tcg_temp_free_ptr(rb); | |
6853 | tcg_temp_free_ptr(rc); | |
6854 | tcg_temp_free_ptr(rd); | |
6855 | } | |
6856 | ||
b04ae981 | 6857 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 6858 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 6859 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 6860 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 6861 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 6862 | |
0487d6a8 | 6863 | /*** SPE extension ***/ |
0487d6a8 | 6864 | /* Register moves */ |
3cd7d1dd | 6865 | |
a0e13900 FC |
6866 | |
6867 | static inline void gen_evmra(DisasContext *ctx) | |
6868 | { | |
6869 | ||
6870 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 6871 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
6872 | return; |
6873 | } | |
6874 | ||
6875 | #if defined(TARGET_PPC64) | |
6876 | /* rD := rA */ | |
6877 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6878 | ||
6879 | /* spe_acc := rA */ | |
6880 | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], | |
6881 | cpu_env, | |
1328c2bf | 6882 | offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
6883 | #else |
6884 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
6885 | ||
6886 | /* tmp := rA_lo + rA_hi << 32 */ | |
6887 | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6888 | ||
6889 | /* spe_acc := tmp */ | |
1328c2bf | 6890 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
6891 | tcg_temp_free_i64(tmp); |
6892 | ||
6893 | /* rD := rA */ | |
6894 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6895 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
6896 | #endif | |
6897 | } | |
6898 | ||
636aa200 BS |
6899 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
6900 | { | |
f78fb44e AJ |
6901 | #if defined(TARGET_PPC64) |
6902 | tcg_gen_mov_i64(t, cpu_gpr[reg]); | |
6903 | #else | |
36aa55dc | 6904 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
3cd7d1dd | 6905 | #endif |
f78fb44e | 6906 | } |
3cd7d1dd | 6907 | |
636aa200 BS |
6908 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
6909 | { | |
f78fb44e AJ |
6910 | #if defined(TARGET_PPC64) |
6911 | tcg_gen_mov_i64(cpu_gpr[reg], t); | |
6912 | #else | |
a7812ae4 | 6913 | TCGv_i64 tmp = tcg_temp_new_i64(); |
f78fb44e | 6914 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
f78fb44e AJ |
6915 | tcg_gen_shri_i64(tmp, t, 32); |
6916 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); | |
a7812ae4 | 6917 | tcg_temp_free_i64(tmp); |
3cd7d1dd | 6918 | #endif |
f78fb44e | 6919 | } |
3cd7d1dd | 6920 | |
70560da7 | 6921 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
99e300ef | 6922 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
6923 | { \ |
6924 | if (Rc(ctx->opcode)) \ | |
6925 | gen_##name1(ctx); \ | |
6926 | else \ | |
6927 | gen_##name0(ctx); \ | |
6928 | } | |
6929 | ||
6930 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 6931 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 6932 | { |
e06fcd75 | 6933 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
6934 | } |
6935 | ||
57951c27 AJ |
6936 | /* SPE logic */ |
6937 | #if defined(TARGET_PPC64) | |
6938 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6939 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6940 | { \ |
6941 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6942 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
6943 | return; \ |
6944 | } \ | |
57951c27 AJ |
6945 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6946 | cpu_gpr[rB(ctx->opcode)]); \ | |
6947 | } | |
6948 | #else | |
6949 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
636aa200 | 6950 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
6951 | { \ |
6952 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6953 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
6954 | return; \ |
6955 | } \ | |
6956 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
6957 | cpu_gpr[rB(ctx->opcode)]); \ | |
6958 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6959 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 6960 | } |
57951c27 AJ |
6961 | #endif |
6962 | ||
6963 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
6964 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
6965 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
6966 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
6967 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
6968 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
6969 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
6970 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 6971 | |
57951c27 AJ |
6972 | /* SPE logic immediate */ |
6973 | #if defined(TARGET_PPC64) | |
6974 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 6975 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a AJ |
6976 | { \ |
6977 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6978 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
3d3a6a0a AJ |
6979 | return; \ |
6980 | } \ | |
a7812ae4 PB |
6981 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6982 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6983 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6984 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6985 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
6986 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6987 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6988 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6989 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
6990 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6991 | tcg_temp_free_i32(t0); \ |
6992 | tcg_temp_free_i32(t1); \ | |
3d3a6a0a | 6993 | } |
57951c27 AJ |
6994 | #else |
6995 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
636aa200 | 6996 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
6997 | { \ |
6998 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 6999 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7000 | return; \ |
7001 | } \ | |
57951c27 AJ |
7002 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7003 | rB(ctx->opcode)); \ | |
7004 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7005 | rB(ctx->opcode)); \ | |
0487d6a8 | 7006 | } |
57951c27 AJ |
7007 | #endif |
7008 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); | |
7009 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
7010 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
7011 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 7012 | |
57951c27 AJ |
7013 | /* SPE arithmetic */ |
7014 | #if defined(TARGET_PPC64) | |
7015 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
636aa200 | 7016 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7017 | { \ |
7018 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7019 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7020 | return; \ |
7021 | } \ | |
a7812ae4 PB |
7022 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7023 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7024 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7025 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7026 | tcg_op(t0, t0); \ | |
7027 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7028 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7029 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7030 | tcg_op(t1, t1); \ |
7031 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7032 | tcg_temp_free_i32(t0); \ |
7033 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7034 | } |
57951c27 | 7035 | #else |
a7812ae4 | 7036 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 7037 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7038 | { \ |
7039 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7040 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7041 | return; \ |
7042 | } \ | |
7043 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ | |
7044 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
7045 | } | |
7046 | #endif | |
0487d6a8 | 7047 | |
636aa200 | 7048 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
7049 | { |
7050 | int l1 = gen_new_label(); | |
7051 | int l2 = gen_new_label(); | |
0487d6a8 | 7052 | |
57951c27 AJ |
7053 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
7054 | tcg_gen_neg_i32(ret, arg1); | |
7055 | tcg_gen_br(l2); | |
7056 | gen_set_label(l1); | |
a7812ae4 | 7057 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
7058 | gen_set_label(l2); |
7059 | } | |
7060 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
7061 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
7062 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
7063 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 7064 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 7065 | { |
57951c27 AJ |
7066 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
7067 | tcg_gen_ext16u_i32(ret, ret); | |
7068 | } | |
7069 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
7070 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
7071 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 7072 | |
57951c27 AJ |
7073 | #if defined(TARGET_PPC64) |
7074 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7075 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7076 | { \ |
7077 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7078 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7079 | return; \ |
7080 | } \ | |
a7812ae4 PB |
7081 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7082 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7083 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ | |
501e23c4 | 7084 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
57951c27 AJ |
7085 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7086 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ | |
7087 | tcg_op(t0, t0, t2); \ | |
7088 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7089 | tcg_gen_trunc_i64_i32(t1, t3); \ | |
7090 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7091 | tcg_gen_trunc_i64_i32(t2, t3); \ | |
a7812ae4 | 7092 | tcg_temp_free_i64(t3); \ |
57951c27 | 7093 | tcg_op(t1, t1, t2); \ |
a7812ae4 | 7094 | tcg_temp_free_i32(t2); \ |
57951c27 | 7095 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
a7812ae4 PB |
7096 | tcg_temp_free_i32(t0); \ |
7097 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7098 | } |
57951c27 AJ |
7099 | #else |
7100 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
636aa200 | 7101 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 JM |
7102 | { \ |
7103 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7104 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
7105 | return; \ |
7106 | } \ | |
57951c27 AJ |
7107 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7108 | cpu_gpr[rB(ctx->opcode)]); \ | |
7109 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7110 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 7111 | } |
57951c27 | 7112 | #endif |
0487d6a8 | 7113 | |
636aa200 | 7114 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7115 | { |
a7812ae4 | 7116 | TCGv_i32 t0; |
57951c27 | 7117 | int l1, l2; |
0487d6a8 | 7118 | |
57951c27 AJ |
7119 | l1 = gen_new_label(); |
7120 | l2 = gen_new_label(); | |
a7812ae4 | 7121 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7122 | /* No error here: 6 bits are used */ |
7123 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7124 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7125 | tcg_gen_shr_i32(ret, arg1, t0); | |
7126 | tcg_gen_br(l2); | |
7127 | gen_set_label(l1); | |
7128 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7129 | gen_set_label(l2); |
a7812ae4 | 7130 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7131 | } |
7132 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 7133 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7134 | { |
a7812ae4 | 7135 | TCGv_i32 t0; |
57951c27 AJ |
7136 | int l1, l2; |
7137 | ||
7138 | l1 = gen_new_label(); | |
7139 | l2 = gen_new_label(); | |
a7812ae4 | 7140 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7141 | /* No error here: 6 bits are used */ |
7142 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7143 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7144 | tcg_gen_sar_i32(ret, arg1, t0); | |
7145 | tcg_gen_br(l2); | |
7146 | gen_set_label(l1); | |
7147 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 7148 | gen_set_label(l2); |
a7812ae4 | 7149 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7150 | } |
7151 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 7152 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7153 | { |
a7812ae4 | 7154 | TCGv_i32 t0; |
57951c27 AJ |
7155 | int l1, l2; |
7156 | ||
7157 | l1 = gen_new_label(); | |
7158 | l2 = gen_new_label(); | |
a7812ae4 | 7159 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7160 | /* No error here: 6 bits are used */ |
7161 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7162 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7163 | tcg_gen_shl_i32(ret, arg1, t0); | |
7164 | tcg_gen_br(l2); | |
7165 | gen_set_label(l1); | |
7166 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 7167 | gen_set_label(l2); |
a7812ae4 | 7168 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7169 | } |
7170 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 7171 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7172 | { |
a7812ae4 | 7173 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
7174 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
7175 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 7176 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7177 | } |
7178 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 7179 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
7180 | { |
7181 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7182 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7183 | return; |
7184 | } | |
7185 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7186 | TCGv t0 = tcg_temp_new(); |
7187 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7188 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7189 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
7190 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7191 | tcg_temp_free(t0); | |
7192 | tcg_temp_free(t1); | |
7193 | #else | |
7194 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7195 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7196 | #endif | |
7197 | } | |
7198 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 7199 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 7200 | { |
57951c27 AJ |
7201 | tcg_gen_sub_i32(ret, arg2, arg1); |
7202 | } | |
7203 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 7204 | |
57951c27 AJ |
7205 | /* SPE arithmetic immediate */ |
7206 | #if defined(TARGET_PPC64) | |
7207 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7208 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7209 | { \ |
7210 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7211 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7212 | return; \ |
7213 | } \ | |
a7812ae4 PB |
7214 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7215 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7216 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7217 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7218 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
7219 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7220 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
e06fcd75 | 7221 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7222 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
7223 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7224 | tcg_temp_free_i32(t0); \ |
7225 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7226 | } |
7227 | #else | |
7228 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
636aa200 | 7229 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7230 | { \ |
7231 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7232 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7233 | return; \ |
7234 | } \ | |
7235 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
7236 | rA(ctx->opcode)); \ | |
7237 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ | |
7238 | rA(ctx->opcode)); \ | |
7239 | } | |
7240 | #endif | |
7241 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); | |
7242 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
7243 | ||
7244 | /* SPE comparison */ | |
7245 | #if defined(TARGET_PPC64) | |
7246 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7247 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7248 | { \ |
7249 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7250 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7251 | return; \ |
7252 | } \ | |
7253 | int l1 = gen_new_label(); \ | |
7254 | int l2 = gen_new_label(); \ | |
7255 | int l3 = gen_new_label(); \ | |
7256 | int l4 = gen_new_label(); \ | |
a7812ae4 PB |
7257 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7258 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7259 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7260 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7261 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7262 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ | |
a7812ae4 | 7263 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
7264 | tcg_gen_br(l2); \ |
7265 | gen_set_label(l1); \ | |
7266 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7267 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7268 | gen_set_label(l2); \ | |
7269 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7270 | tcg_gen_trunc_i64_i32(t0, t2); \ | |
7271 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7272 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7273 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7274 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
7275 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7276 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7277 | tcg_gen_br(l4); \ | |
7278 | gen_set_label(l3); \ | |
7279 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7280 | CRF_CH | CRF_CH_OR_CL); \ | |
7281 | gen_set_label(l4); \ | |
a7812ae4 PB |
7282 | tcg_temp_free_i32(t0); \ |
7283 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7284 | } |
7285 | #else | |
7286 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
636aa200 | 7287 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
7288 | { \ |
7289 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7290 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
7291 | return; \ |
7292 | } \ | |
7293 | int l1 = gen_new_label(); \ | |
7294 | int l2 = gen_new_label(); \ | |
7295 | int l3 = gen_new_label(); \ | |
7296 | int l4 = gen_new_label(); \ | |
7297 | \ | |
7298 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
7299 | cpu_gpr[rB(ctx->opcode)], l1); \ | |
7300 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ | |
7301 | tcg_gen_br(l2); \ | |
7302 | gen_set_label(l1); \ | |
7303 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7304 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7305 | gen_set_label(l2); \ | |
7306 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ | |
7307 | cpu_gprh[rB(ctx->opcode)], l3); \ | |
7308 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7309 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7310 | tcg_gen_br(l4); \ | |
7311 | gen_set_label(l3); \ | |
7312 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7313 | CRF_CH | CRF_CH_OR_CL); \ | |
7314 | gen_set_label(l4); \ | |
7315 | } | |
7316 | #endif | |
7317 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); | |
7318 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
7319 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
7320 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
7321 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
7322 | ||
7323 | /* SPE misc */ | |
636aa200 | 7324 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
7325 | { |
7326 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
7327 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
7328 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 7329 | } |
636aa200 | 7330 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
7331 | { |
7332 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7333 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7334 | return; |
7335 | } | |
7336 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7337 | TCGv t0 = tcg_temp_new(); |
7338 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7339 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7340 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); |
7341 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7342 | tcg_temp_free(t0); | |
7343 | tcg_temp_free(t1); | |
7344 | #else | |
57951c27 | 7345 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
33890b3e | 7346 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7347 | #endif |
7348 | } | |
636aa200 | 7349 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
7350 | { |
7351 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7352 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7353 | return; |
7354 | } | |
7355 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7356 | TCGv t0 = tcg_temp_new(); |
7357 | TCGv t1 = tcg_temp_new(); | |
17d9b3af | 7358 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7359 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); |
7360 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7361 | tcg_temp_free(t0); | |
7362 | tcg_temp_free(t1); | |
7363 | #else | |
7364 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7365 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7366 | #endif | |
7367 | } | |
636aa200 | 7368 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
7369 | { |
7370 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7371 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
7372 | return; |
7373 | } | |
7374 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7375 | TCGv t0 = tcg_temp_new(); |
7376 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7377 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7378 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
7379 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7380 | tcg_temp_free(t0); | |
7381 | tcg_temp_free(t1); | |
7382 | #else | |
33890b3e NF |
7383 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
7384 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
7385 | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); | |
7386 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7387 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); | |
7388 | tcg_temp_free_i32(tmp); | |
7389 | } else { | |
7390 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7391 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7392 | } | |
57951c27 AJ |
7393 | #endif |
7394 | } | |
636aa200 | 7395 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 7396 | { |
ae01847f | 7397 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 7398 | |
57951c27 | 7399 | #if defined(TARGET_PPC64) |
38d14952 | 7400 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7401 | #else |
7402 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7403 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7404 | #endif | |
7405 | } | |
636aa200 | 7406 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 7407 | { |
ae01847f | 7408 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 7409 | |
57951c27 | 7410 | #if defined(TARGET_PPC64) |
38d14952 | 7411 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7412 | #else |
7413 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7414 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7415 | #endif | |
0487d6a8 JM |
7416 | } |
7417 | ||
636aa200 | 7418 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 AJ |
7419 | { |
7420 | int l1 = gen_new_label(); | |
7421 | int l2 = gen_new_label(); | |
7422 | int l3 = gen_new_label(); | |
7423 | int l4 = gen_new_label(); | |
a7812ae4 | 7424 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 | 7425 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
7426 | TCGv t1 = tcg_temp_local_new(); |
7427 | TCGv t2 = tcg_temp_local_new(); | |
57951c27 AJ |
7428 | #endif |
7429 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); | |
7430 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
7431 | #if defined(TARGET_PPC64) | |
7432 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7433 | #else | |
7434 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7435 | #endif | |
7436 | tcg_gen_br(l2); | |
7437 | gen_set_label(l1); | |
7438 | #if defined(TARGET_PPC64) | |
7439 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7440 | #else | |
7441 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7442 | #endif | |
7443 | gen_set_label(l2); | |
7444 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
7445 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
7446 | #if defined(TARGET_PPC64) | |
17d9b3af | 7447 | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
7448 | #else |
7449 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7450 | #endif | |
7451 | tcg_gen_br(l4); | |
7452 | gen_set_label(l3); | |
7453 | #if defined(TARGET_PPC64) | |
17d9b3af | 7454 | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
57951c27 AJ |
7455 | #else |
7456 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7457 | #endif | |
7458 | gen_set_label(l4); | |
a7812ae4 | 7459 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7460 | #if defined(TARGET_PPC64) |
7461 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); | |
7462 | tcg_temp_free(t1); | |
7463 | tcg_temp_free(t2); | |
7464 | #endif | |
7465 | } | |
e8eaa2c0 BS |
7466 | |
7467 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
7468 | { |
7469 | gen_evsel(ctx); | |
7470 | } | |
e8eaa2c0 BS |
7471 | |
7472 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
7473 | { |
7474 | gen_evsel(ctx); | |
7475 | } | |
e8eaa2c0 BS |
7476 | |
7477 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
7478 | { |
7479 | gen_evsel(ctx); | |
7480 | } | |
e8eaa2c0 BS |
7481 | |
7482 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
7483 | { |
7484 | gen_evsel(ctx); | |
7485 | } | |
0487d6a8 | 7486 | |
a0e13900 FC |
7487 | /* Multiply */ |
7488 | ||
7489 | static inline void gen_evmwumi(DisasContext *ctx) | |
7490 | { | |
7491 | TCGv_i64 t0, t1; | |
7492 | ||
7493 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7494 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7495 | return; |
7496 | } | |
7497 | ||
7498 | t0 = tcg_temp_new_i64(); | |
7499 | t1 = tcg_temp_new_i64(); | |
7500 | ||
7501 | /* t0 := rA; t1 := rB */ | |
7502 | #if defined(TARGET_PPC64) | |
7503 | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7504 | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7505 | #else | |
7506 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7507 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7508 | #endif | |
7509 | ||
7510 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7511 | ||
7512 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7513 | ||
7514 | tcg_temp_free_i64(t0); | |
7515 | tcg_temp_free_i64(t1); | |
7516 | } | |
7517 | ||
7518 | static inline void gen_evmwumia(DisasContext *ctx) | |
7519 | { | |
7520 | TCGv_i64 tmp; | |
7521 | ||
7522 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7523 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7524 | return; |
7525 | } | |
7526 | ||
7527 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7528 | ||
7529 | tmp = tcg_temp_new_i64(); | |
7530 | ||
7531 | /* acc := rD */ | |
7532 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7533 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7534 | tcg_temp_free_i64(tmp); |
7535 | } | |
7536 | ||
7537 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
7538 | { | |
7539 | TCGv_i64 acc; | |
7540 | TCGv_i64 tmp; | |
7541 | ||
7542 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7543 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7544 | return; |
7545 | } | |
7546 | ||
7547 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
7548 | ||
7549 | acc = tcg_temp_new_i64(); | |
7550 | tmp = tcg_temp_new_i64(); | |
7551 | ||
7552 | /* tmp := rD */ | |
7553 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7554 | ||
7555 | /* Load acc */ | |
1328c2bf | 7556 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7557 | |
7558 | /* acc := tmp + acc */ | |
7559 | tcg_gen_add_i64(acc, acc, tmp); | |
7560 | ||
7561 | /* Store acc */ | |
1328c2bf | 7562 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7563 | |
7564 | /* rD := acc */ | |
7565 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7566 | ||
7567 | tcg_temp_free_i64(acc); | |
7568 | tcg_temp_free_i64(tmp); | |
7569 | } | |
7570 | ||
7571 | static inline void gen_evmwsmi(DisasContext *ctx) | |
7572 | { | |
7573 | TCGv_i64 t0, t1; | |
7574 | ||
7575 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 7576 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
7577 | return; |
7578 | } | |
7579 | ||
7580 | t0 = tcg_temp_new_i64(); | |
7581 | t1 = tcg_temp_new_i64(); | |
7582 | ||
7583 | /* t0 := rA; t1 := rB */ | |
7584 | #if defined(TARGET_PPC64) | |
7585 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
7586 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
7587 | #else | |
7588 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
7589 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
7590 | #endif | |
7591 | ||
7592 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
7593 | ||
7594 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
7595 | ||
7596 | tcg_temp_free_i64(t0); | |
7597 | tcg_temp_free_i64(t1); | |
7598 | } | |
7599 | ||
7600 | static inline void gen_evmwsmia(DisasContext *ctx) | |
7601 | { | |
7602 | TCGv_i64 tmp; | |
7603 | ||
7604 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7605 | ||
7606 | tmp = tcg_temp_new_i64(); | |
7607 | ||
7608 | /* acc := rD */ | |
7609 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 7610 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7611 | |
7612 | tcg_temp_free_i64(tmp); | |
7613 | } | |
7614 | ||
7615 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
7616 | { | |
7617 | TCGv_i64 acc = tcg_temp_new_i64(); | |
7618 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
7619 | ||
7620 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
7621 | ||
7622 | acc = tcg_temp_new_i64(); | |
7623 | tmp = tcg_temp_new_i64(); | |
7624 | ||
7625 | /* tmp := rD */ | |
7626 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
7627 | ||
7628 | /* Load acc */ | |
1328c2bf | 7629 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7630 | |
7631 | /* acc := tmp + acc */ | |
7632 | tcg_gen_add_i64(acc, acc, tmp); | |
7633 | ||
7634 | /* Store acc */ | |
1328c2bf | 7635 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
7636 | |
7637 | /* rD := acc */ | |
7638 | gen_store_gpr64(rD(ctx->opcode), acc); | |
7639 | ||
7640 | tcg_temp_free_i64(acc); | |
7641 | tcg_temp_free_i64(tmp); | |
7642 | } | |
7643 | ||
70560da7 FC |
7644 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
7645 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7646 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7647 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7648 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7649 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7650 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
7651 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // | |
7652 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); | |
7653 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7654 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7655 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7656 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7657 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7658 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
7659 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
7660 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
7661 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7662 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7663 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); | |
7664 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
7665 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
7666 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // | |
7667 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); | |
7668 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7669 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
7670 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7671 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
7672 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// | |
0487d6a8 | 7673 | |
6a6ae23f | 7674 | /* SPE load and stores */ |
636aa200 | 7675 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
7676 | { |
7677 | target_ulong uimm = rB(ctx->opcode); | |
7678 | ||
76db3ba4 | 7679 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 7680 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 7681 | } else { |
6a6ae23f | 7682 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
76db3ba4 AJ |
7683 | #if defined(TARGET_PPC64) |
7684 | if (!ctx->sf_mode) { | |
7685 | tcg_gen_ext32u_tl(EA, EA); | |
7686 | } | |
7687 | #endif | |
7688 | } | |
0487d6a8 | 7689 | } |
6a6ae23f | 7690 | |
636aa200 | 7691 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7692 | { |
7693 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7694 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
6a6ae23f AJ |
7695 | #else |
7696 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
76db3ba4 | 7697 | gen_qemu_ld64(ctx, t0, addr); |
6a6ae23f AJ |
7698 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7699 | tcg_gen_shri_i64(t0, t0, 32); | |
7700 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); | |
7701 | tcg_temp_free_i64(t0); | |
7702 | #endif | |
0487d6a8 | 7703 | } |
6a6ae23f | 7704 | |
636aa200 | 7705 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7706 | { |
0487d6a8 | 7707 | #if defined(TARGET_PPC64) |
6a6ae23f | 7708 | TCGv t0 = tcg_temp_new(); |
76db3ba4 | 7709 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f | 7710 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
76db3ba4 AJ |
7711 | gen_addr_add(ctx, addr, addr, 4); |
7712 | gen_qemu_ld32u(ctx, t0, addr); | |
6a6ae23f AJ |
7713 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7714 | tcg_temp_free(t0); | |
7715 | #else | |
76db3ba4 AJ |
7716 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7717 | gen_addr_add(ctx, addr, addr, 4); | |
7718 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f | 7719 | #endif |
0487d6a8 | 7720 | } |
6a6ae23f | 7721 | |
636aa200 | 7722 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7723 | { |
7724 | TCGv t0 = tcg_temp_new(); | |
7725 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7726 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7727 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7728 | gen_addr_add(ctx, addr, addr, 2); |
7729 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7730 | tcg_gen_shli_tl(t0, t0, 32); |
7731 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7732 | gen_addr_add(ctx, addr, addr, 2); |
7733 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7734 | tcg_gen_shli_tl(t0, t0, 16); |
7735 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7736 | gen_addr_add(ctx, addr, addr, 2); |
7737 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7738 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7739 | #else |
76db3ba4 | 7740 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7741 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7742 | gen_addr_add(ctx, addr, addr, 2); |
7743 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7744 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7745 | gen_addr_add(ctx, addr, addr, 2); |
7746 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7747 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7748 | gen_addr_add(ctx, addr, addr, 2); |
7749 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7750 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7751 | #endif |
6a6ae23f | 7752 | tcg_temp_free(t0); |
0487d6a8 JM |
7753 | } |
7754 | ||
636aa200 | 7755 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7756 | { |
7757 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7758 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7759 | #if defined(TARGET_PPC64) |
7760 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
7761 | tcg_gen_shli_tl(t0, t0, 16); | |
7762 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7763 | #else | |
7764 | tcg_gen_shli_tl(t0, t0, 16); | |
7765 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7766 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7767 | #endif | |
7768 | tcg_temp_free(t0); | |
0487d6a8 JM |
7769 | } |
7770 | ||
636aa200 | 7771 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7772 | { |
7773 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7774 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7775 | #if defined(TARGET_PPC64) |
7776 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7777 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7778 | #else | |
7779 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7780 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7781 | #endif | |
7782 | tcg_temp_free(t0); | |
0487d6a8 JM |
7783 | } |
7784 | ||
636aa200 | 7785 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7786 | { |
7787 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7788 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
7789 | #if defined(TARGET_PPC64) |
7790 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7791 | tcg_gen_ext32u_tl(t0, t0); | |
7792 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7793 | #else | |
7794 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7795 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7796 | #endif | |
7797 | tcg_temp_free(t0); | |
7798 | } | |
7799 | ||
636aa200 | 7800 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7801 | { |
7802 | TCGv t0 = tcg_temp_new(); | |
7803 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7804 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7805 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7806 | gen_addr_add(ctx, addr, addr, 2); |
7807 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7808 | tcg_gen_shli_tl(t0, t0, 16); |
7809 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7810 | #else | |
76db3ba4 | 7811 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7812 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7813 | gen_addr_add(ctx, addr, addr, 2); |
7814 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7815 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7816 | #endif | |
7817 | tcg_temp_free(t0); | |
7818 | } | |
7819 | ||
636aa200 | 7820 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7821 | { |
7822 | #if defined(TARGET_PPC64) | |
7823 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 AJ |
7824 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7825 | gen_addr_add(ctx, addr, addr, 2); | |
7826 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7827 | tcg_gen_shli_tl(t0, t0, 32); |
7828 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7829 | tcg_temp_free(t0); | |
7830 | #else | |
76db3ba4 AJ |
7831 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7832 | gen_addr_add(ctx, addr, addr, 2); | |
7833 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7834 | #endif |
7835 | } | |
7836 | ||
636aa200 | 7837 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7838 | { |
7839 | #if defined(TARGET_PPC64) | |
7840 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7841 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f | 7842 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7843 | gen_addr_add(ctx, addr, addr, 2); |
7844 | gen_qemu_ld16s(ctx, t0, addr); | |
6a6ae23f AJ |
7845 | tcg_gen_shli_tl(t0, t0, 32); |
7846 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7847 | tcg_temp_free(t0); | |
7848 | #else | |
76db3ba4 AJ |
7849 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7850 | gen_addr_add(ctx, addr, addr, 2); | |
7851 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7852 | #endif |
7853 | } | |
7854 | ||
636aa200 | 7855 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7856 | { |
7857 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7858 | gen_qemu_ld32u(ctx, t0, addr); |
0487d6a8 | 7859 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7860 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
7861 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7862 | #else | |
7863 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7864 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7865 | #endif | |
7866 | tcg_temp_free(t0); | |
7867 | } | |
7868 | ||
636aa200 | 7869 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7870 | { |
7871 | TCGv t0 = tcg_temp_new(); | |
7872 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7873 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7874 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
7875 | tcg_gen_shli_tl(t0, t0, 32); | |
7876 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7877 | gen_addr_add(ctx, addr, addr, 2); |
7878 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7879 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7880 | tcg_gen_shli_tl(t0, t0, 16); | |
7881 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7882 | #else | |
76db3ba4 | 7883 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7884 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
7885 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7886 | gen_addr_add(ctx, addr, addr, 2); |
7887 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7888 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7889 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
0487d6a8 | 7890 | #endif |
6a6ae23f AJ |
7891 | tcg_temp_free(t0); |
7892 | } | |
7893 | ||
636aa200 | 7894 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7895 | { |
7896 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7897 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
0487d6a8 | 7898 | #else |
6a6ae23f AJ |
7899 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7900 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); | |
76db3ba4 | 7901 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f AJ |
7902 | tcg_temp_free_i64(t0); |
7903 | #endif | |
7904 | } | |
7905 | ||
636aa200 | 7906 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7907 | { |
0487d6a8 | 7908 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7909 | TCGv t0 = tcg_temp_new(); |
7910 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7911 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7912 | tcg_temp_free(t0); |
7913 | #else | |
76db3ba4 | 7914 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7915 | #endif |
76db3ba4 AJ |
7916 | gen_addr_add(ctx, addr, addr, 4); |
7917 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7918 | } |
7919 | ||
636aa200 | 7920 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7921 | { |
7922 | TCGv t0 = tcg_temp_new(); | |
7923 | #if defined(TARGET_PPC64) | |
7924 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7925 | #else | |
7926 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7927 | #endif | |
76db3ba4 AJ |
7928 | gen_qemu_st16(ctx, t0, addr); |
7929 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f AJ |
7930 | #if defined(TARGET_PPC64) |
7931 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7932 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7933 | #else |
76db3ba4 | 7934 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7935 | #endif |
76db3ba4 | 7936 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 7937 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7938 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7939 | tcg_temp_free(t0); |
76db3ba4 AJ |
7940 | gen_addr_add(ctx, addr, addr, 2); |
7941 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7942 | } |
7943 | ||
636aa200 | 7944 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7945 | { |
7946 | TCGv t0 = tcg_temp_new(); | |
7947 | #if defined(TARGET_PPC64) | |
7948 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7949 | #else | |
7950 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7951 | #endif | |
76db3ba4 AJ |
7952 | gen_qemu_st16(ctx, t0, addr); |
7953 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 7954 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7955 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7956 | tcg_temp_free(t0); |
7957 | } | |
7958 | ||
636aa200 | 7959 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7960 | { |
7961 | #if defined(TARGET_PPC64) | |
7962 | TCGv t0 = tcg_temp_new(); | |
7963 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7964 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7965 | tcg_temp_free(t0); |
7966 | #else | |
76db3ba4 | 7967 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7968 | #endif |
76db3ba4 AJ |
7969 | gen_addr_add(ctx, addr, addr, 2); |
7970 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7971 | } |
7972 | ||
636aa200 | 7973 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
7974 | { |
7975 | #if defined(TARGET_PPC64) | |
7976 | TCGv t0 = tcg_temp_new(); | |
7977 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7978 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7979 | tcg_temp_free(t0); |
7980 | #else | |
76db3ba4 | 7981 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7982 | #endif |
7983 | } | |
7984 | ||
636aa200 | 7985 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 7986 | { |
76db3ba4 | 7987 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7988 | } |
7989 | ||
7990 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 7991 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
7992 | { \ |
7993 | TCGv t0; \ | |
7994 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 7995 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
6a6ae23f AJ |
7996 | return; \ |
7997 | } \ | |
76db3ba4 | 7998 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
7999 | t0 = tcg_temp_new(); \ |
8000 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 8001 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 8002 | } else { \ |
76db3ba4 | 8003 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
8004 | } \ |
8005 | gen_op_##name(ctx, t0); \ | |
8006 | tcg_temp_free(t0); \ | |
8007 | } | |
8008 | ||
8009 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
8010 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
8011 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
8012 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
8013 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
8014 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
8015 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
8016 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
8017 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
8018 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
8019 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
8020 | ||
8021 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
8022 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
8023 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
8024 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
8025 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
8026 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
8027 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
8028 | |
8029 | /* Multiply and add - TODO */ | |
8030 | #if 0 | |
70560da7 FC |
8031 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
8032 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8033 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8034 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8035 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8036 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8037 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8038 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8039 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8040 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8041 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
8042 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8043 | ||
8044 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8045 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8046 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8047 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8048 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8049 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8050 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8051 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8052 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8053 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8054 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8055 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8056 | ||
8057 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8058 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8059 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8060 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
8061 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); | |
8062 | ||
8063 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8064 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8065 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8066 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8067 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8068 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8069 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8070 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8071 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8072 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8073 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
8074 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8075 | ||
8076 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8077 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8078 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8079 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8080 | ||
8081 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8082 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8083 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8084 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8085 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8086 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8087 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8088 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8089 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8090 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8091 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
8092 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8093 | ||
8094 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8095 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8096 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
8097 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
8098 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
8099 | #endif |
8100 | ||
8101 | /*** SPE floating-point extension ***/ | |
1c97856d AJ |
8102 | #if defined(TARGET_PPC64) |
8103 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8104 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8105 | { \ |
1c97856d AJ |
8106 | TCGv_i32 t0; \ |
8107 | TCGv t1; \ | |
8108 | t0 = tcg_temp_new_i32(); \ | |
8109 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8110 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8111 | t1 = tcg_temp_new(); \ |
8112 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8113 | tcg_temp_free_i32(t0); \ | |
8114 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8115 | 0xFFFFFFFF00000000ULL); \ | |
8116 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8117 | tcg_temp_free(t1); \ | |
0487d6a8 | 8118 | } |
1c97856d | 8119 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8120 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8121 | { \ |
8122 | TCGv_i32 t0; \ | |
8123 | TCGv t1; \ | |
8124 | t0 = tcg_temp_new_i32(); \ | |
8e703949 | 8125 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8126 | t1 = tcg_temp_new(); \ |
8127 | tcg_gen_extu_i32_tl(t1, t0); \ | |
8128 | tcg_temp_free_i32(t0); \ | |
8129 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8130 | 0xFFFFFFFF00000000ULL); \ | |
8131 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
8132 | tcg_temp_free(t1); \ | |
8133 | } | |
8134 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8135 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8136 | { \ |
8137 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
8138 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8139 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8140 | tcg_temp_free_i32(t0); \ |
8141 | } | |
8142 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8143 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8144 | { \ |
8e703949 BS |
8145 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8146 | cpu_gpr[rB(ctx->opcode)]); \ | |
1c97856d AJ |
8147 | } |
8148 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8149 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8150 | { \ |
1c97856d AJ |
8151 | TCGv_i32 t0, t1; \ |
8152 | TCGv_i64 t2; \ | |
57951c27 | 8153 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8154 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8155 | return; \ |
8156 | } \ | |
1c97856d AJ |
8157 | t0 = tcg_temp_new_i32(); \ |
8158 | t1 = tcg_temp_new_i32(); \ | |
8159 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8160 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8161 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8162 | tcg_temp_free_i32(t1); \ |
8163 | t2 = tcg_temp_new(); \ | |
8164 | tcg_gen_extu_i32_tl(t2, t0); \ | |
8165 | tcg_temp_free_i32(t0); \ | |
8166 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
8167 | 0xFFFFFFFF00000000ULL); \ | |
8168 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ | |
8169 | tcg_temp_free(t2); \ | |
57951c27 | 8170 | } |
1c97856d | 8171 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
636aa200 | 8172 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8173 | { \ |
8174 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8175 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8176 | return; \ |
8177 | } \ | |
8e703949 BS |
8178 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8179 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8180 | } |
1c97856d | 8181 | #define GEN_SPEFPUOP_COMP_32(name) \ |
636aa200 | 8182 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8183 | { \ |
1c97856d | 8184 | TCGv_i32 t0, t1; \ |
57951c27 | 8185 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8186 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8187 | return; \ |
8188 | } \ | |
1c97856d AJ |
8189 | t0 = tcg_temp_new_i32(); \ |
8190 | t1 = tcg_temp_new_i32(); \ | |
8191 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8192 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8e703949 | 8193 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8194 | tcg_temp_free_i32(t0); \ |
8195 | tcg_temp_free_i32(t1); \ | |
8196 | } | |
8197 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8198 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8199 | { \ |
8200 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8201 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8202 | return; \ |
8203 | } \ | |
8e703949 | 8204 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8205 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8206 | } | |
8207 | #else | |
8208 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
636aa200 | 8209 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 8210 | { \ |
8e703949 BS |
8211 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
8212 | cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8213 | } |
1c97856d | 8214 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 8215 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8216 | { \ |
8217 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8218 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8219 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
1c97856d AJ |
8220 | tcg_temp_free_i64(t0); \ |
8221 | } | |
8222 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 8223 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8224 | { \ |
8225 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8e703949 | 8226 | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
1c97856d AJ |
8227 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8228 | tcg_temp_free_i64(t0); \ | |
8229 | } | |
8230 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 8231 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8232 | { \ |
8233 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8234 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 8235 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
8236 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8237 | tcg_temp_free_i64(t0); \ | |
8238 | } | |
8239 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 8240 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8241 | { \ |
8242 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8243 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8244 | return; \ |
8245 | } \ | |
8e703949 | 8246 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8247 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8248 | } | |
8249 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 8250 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8251 | { \ |
8252 | TCGv_i64 t0, t1; \ | |
8253 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8254 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8255 | return; \ |
8256 | } \ | |
8257 | t0 = tcg_temp_new_i64(); \ | |
8258 | t1 = tcg_temp_new_i64(); \ | |
8259 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8260 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8261 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
8262 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
8263 | tcg_temp_free_i64(t0); \ | |
8264 | tcg_temp_free_i64(t1); \ | |
8265 | } | |
8266 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 8267 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8268 | { \ |
8269 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8270 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8271 | return; \ |
8272 | } \ | |
8e703949 | 8273 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
1c97856d AJ |
8274 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
8275 | } | |
8276 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 8277 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
8278 | { \ |
8279 | TCGv_i64 t0, t1; \ | |
8280 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8281 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
8282 | return; \ |
8283 | } \ | |
8284 | t0 = tcg_temp_new_i64(); \ | |
8285 | t1 = tcg_temp_new_i64(); \ | |
8286 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8287 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 8288 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
8289 | tcg_temp_free_i64(t0); \ |
8290 | tcg_temp_free_i64(t1); \ | |
8291 | } | |
8292 | #endif | |
57951c27 | 8293 | |
0487d6a8 JM |
8294 | /* Single precision floating-point vectors operations */ |
8295 | /* Arithmetic */ | |
1c97856d AJ |
8296 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
8297 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
8298 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
8299 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 8300 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
8301 | { |
8302 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8303 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8304 | return; |
8305 | } | |
8306 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8307 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); |
1c97856d | 8308 | #else |
6d5c34fa MP |
8309 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); |
8310 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8311 | #endif |
8312 | } | |
636aa200 | 8313 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
8314 | { |
8315 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8316 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8317 | return; |
8318 | } | |
8319 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8320 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8321 | #else |
6d5c34fa MP |
8322 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8323 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8324 | #endif |
8325 | } | |
636aa200 | 8326 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
8327 | { |
8328 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8329 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8330 | return; |
8331 | } | |
8332 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8333 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
1c97856d | 8334 | #else |
6d5c34fa MP |
8335 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
8336 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8337 | #endif |
8338 | } | |
8339 | ||
0487d6a8 | 8340 | /* Conversion */ |
1c97856d AJ |
8341 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8342 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
8343 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
8344 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
8345 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
8346 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
8347 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
8348 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
8349 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
8350 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
8351 | ||
0487d6a8 | 8352 | /* Comparison */ |
1c97856d AJ |
8353 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8354 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
8355 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
8356 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
8357 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
8358 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
8359 | |
8360 | /* Opcodes definitions */ | |
70560da7 FC |
8361 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8362 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8363 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8364 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8365 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8366 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8367 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8368 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8369 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8370 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8371 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8372 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8373 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8374 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8375 | |
8376 | /* Single precision floating-point operations */ | |
8377 | /* Arithmetic */ | |
1c97856d AJ |
8378 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8379 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
8380 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
8381 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 8382 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
8383 | { |
8384 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8385 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8386 | return; |
8387 | } | |
6d5c34fa | 8388 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 8389 | } |
636aa200 | 8390 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
8391 | { |
8392 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8393 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8394 | return; |
8395 | } | |
6d5c34fa | 8396 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 8397 | } |
636aa200 | 8398 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
8399 | { |
8400 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8401 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8402 | return; |
8403 | } | |
6d5c34fa | 8404 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
8405 | } |
8406 | ||
0487d6a8 | 8407 | /* Conversion */ |
1c97856d AJ |
8408 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8409 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
8410 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
8411 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
8412 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
8413 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
8414 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
8415 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
8416 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
8417 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
8418 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
8419 | ||
0487d6a8 | 8420 | /* Comparison */ |
1c97856d AJ |
8421 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
8422 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
8423 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
8424 | GEN_SPEFPUOP_COMP_32(efststgt); | |
8425 | GEN_SPEFPUOP_COMP_32(efststlt); | |
8426 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
8427 | |
8428 | /* Opcodes definitions */ | |
70560da7 FC |
8429 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
8430 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
8431 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8432 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
8433 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8434 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // | |
8435 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8436 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8437 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8438 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
8439 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8440 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
8441 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
8442 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8443 | |
8444 | /* Double precision floating-point operations */ | |
8445 | /* Arithmetic */ | |
1c97856d AJ |
8446 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
8447 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
8448 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
8449 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 8450 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
8451 | { |
8452 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8453 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8454 | return; |
8455 | } | |
8456 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8457 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); |
1c97856d | 8458 | #else |
6d5c34fa MP |
8459 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8460 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
1c97856d AJ |
8461 | #endif |
8462 | } | |
636aa200 | 8463 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
8464 | { |
8465 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8466 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8467 | return; |
8468 | } | |
8469 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8470 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8471 | #else |
6d5c34fa MP |
8472 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8473 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8474 | #endif |
8475 | } | |
636aa200 | 8476 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
8477 | { |
8478 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8479 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
8480 | return; |
8481 | } | |
8482 | #if defined(TARGET_PPC64) | |
6d5c34fa | 8483 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
1c97856d | 8484 | #else |
6d5c34fa MP |
8485 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8486 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
1c97856d AJ |
8487 | #endif |
8488 | } | |
8489 | ||
0487d6a8 | 8490 | /* Conversion */ |
1c97856d AJ |
8491 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
8492 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
8493 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
8494 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
8495 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
8496 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
8497 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
8498 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
8499 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
8500 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
8501 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
8502 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
8503 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
8504 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
8505 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 8506 | |
0487d6a8 | 8507 | /* Comparison */ |
1c97856d AJ |
8508 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
8509 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
8510 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
8511 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
8512 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
8513 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
8514 | |
8515 | /* Opcodes definitions */ | |
70560da7 FC |
8516 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
8517 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8518 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // | |
8519 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8520 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // | |
8521 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8522 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8523 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // | |
8524 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8525 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8526 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8527 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
8528 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8529 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
8530 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
8531 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
0487d6a8 | 8532 | |
c227f099 | 8533 | static opcode_t opcodes[] = { |
5c55ff99 BS |
8534 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
8535 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
8536 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8537 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
8538 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
8539 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), | |
8540 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8541 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8542 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8543 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8544 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
8545 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
8546 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
8547 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
8548 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8549 | #if defined(TARGET_PPC64) | |
8550 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
8551 | #endif | |
8552 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
8553 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
8554 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8555 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8556 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8557 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
8558 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
8559 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
8560 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8561 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8562 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8563 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8564 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), | |
eaabeef2 | 8565 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 8566 | #if defined(TARGET_PPC64) |
eaabeef2 | 8567 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 BS |
8568 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
8569 | #endif | |
8570 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8571 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8572 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8573 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
8574 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
8575 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
8576 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
8577 | #if defined(TARGET_PPC64) | |
8578 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
8579 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
8580 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
8581 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
8582 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
8583 | #endif | |
8584 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
8585 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8586 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
8587 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
8588 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
8589 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), | |
8590 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), | |
8591 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
8592 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
8593 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
8594 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT), | |
8595 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT), | |
8596 | #if defined(TARGET_PPC64) | |
8597 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8598 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
8599 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8600 | #endif | |
8601 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8602 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
8603 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
8604 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
8605 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
8606 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
8607 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
8608 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
f844c817 | 8609 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
5c55ff99 BS |
8610 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
8611 | #if defined(TARGET_PPC64) | |
f844c817 | 8612 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
5c55ff99 BS |
8613 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
8614 | #endif | |
8615 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
8616 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
8617 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8618 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8619 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
8620 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
8621 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), | |
8622 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
8623 | #if defined(TARGET_PPC64) | |
8624 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
8625 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
8626 | #endif | |
8627 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
8628 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
8629 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
8630 | #if defined(TARGET_PPC64) | |
8631 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
8632 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
8633 | #endif | |
8634 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
8635 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
8636 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
8637 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
8638 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
8639 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
8640 | #if defined(TARGET_PPC64) | |
8641 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
8642 | #endif | |
8643 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
8644 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), | |
8645 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
8646 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
8647 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
8648 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), | |
8649 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), | |
8650 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ), | |
8651 | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT), | |
8652 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), | |
8653 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
8654 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
8655 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
8656 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
8657 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
8658 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
8659 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
8660 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
8661 | #if defined(TARGET_PPC64) | |
8662 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
8663 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
8664 | PPC_SEGMENT_64B), | |
8665 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
8666 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
8667 | PPC_SEGMENT_64B), | |
efdef95f DG |
8668 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
8669 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
8670 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
8671 | #endif |
8672 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
8673 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
8674 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
8675 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
8676 | #if defined(TARGET_PPC64) | |
8677 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
8678 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
8679 | #endif | |
8680 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
8681 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
8682 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
8683 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
8684 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
8685 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
8686 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
8687 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
8688 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
8689 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
8690 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
8691 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8692 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
8693 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
8694 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
8695 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
8696 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
8697 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
8698 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
8699 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
8700 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
8701 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
8702 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
8703 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
8704 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
8705 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
8706 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
8707 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
8708 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
8709 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
8710 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
8711 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
8712 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
8713 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
8714 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
8715 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
8716 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
8717 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
8718 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
8719 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
8720 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
8721 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
8722 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
8723 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
8724 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
8725 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
8726 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
8727 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
8728 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
8729 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8730 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8731 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
8732 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
8733 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8734 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
8735 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
8736 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
8737 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
8738 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
8739 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
8740 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
8741 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
8742 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
8743 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
8744 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
8745 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
8746 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
8747 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
8748 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
8749 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
8750 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 8751 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
8752 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
8753 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
8754 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
8755 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
8756 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
8757 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
8758 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
8759 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
8760 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
8761 | PPC_NONE, PPC2_BOOKE206), | |
8762 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
8763 | PPC_NONE, PPC2_BOOKE206), | |
8764 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
8765 | PPC_NONE, PPC2_BOOKE206), | |
8766 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
8767 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
8768 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
8769 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
8770 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
8771 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
8772 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
8773 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 8774 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 8775 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 8776 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
8777 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
8778 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 8779 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
8780 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
8781 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
8782 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
8783 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
8784 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
8785 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
8786 | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), | |
8787 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), | |
8788 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
8789 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
8790 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
8791 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
8792 | ||
8793 | #undef GEN_INT_ARITH_ADD | |
8794 | #undef GEN_INT_ARITH_ADD_CONST | |
8795 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8796 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
8797 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
8798 | add_ca, compute_ca, compute_ov) \ | |
8799 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
8800 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
8801 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
8802 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
8803 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
8804 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
8805 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
8806 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
8807 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
8808 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
8809 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
8810 | ||
8811 | #undef GEN_INT_ARITH_DIVW | |
8812 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
8813 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
8814 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
8815 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
8816 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
8817 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
8818 | ||
8819 | #if defined(TARGET_PPC64) | |
8820 | #undef GEN_INT_ARITH_DIVD | |
8821 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
8822 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8823 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
8824 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
8825 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
8826 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
8827 | ||
8828 | #undef GEN_INT_ARITH_MUL_HELPER | |
8829 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
8830 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
8831 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
8832 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
8833 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
8834 | #endif | |
8835 | ||
8836 | #undef GEN_INT_ARITH_SUBF | |
8837 | #undef GEN_INT_ARITH_SUBF_CONST | |
8838 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
8839 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
8840 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
8841 | add_ca, compute_ca, compute_ov) \ | |
8842 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
8843 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
8844 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
8845 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
8846 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
8847 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
8848 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
8849 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
8850 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
8851 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
8852 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
8853 | ||
8854 | #undef GEN_LOGICAL1 | |
8855 | #undef GEN_LOGICAL2 | |
8856 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
8857 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
8858 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
8859 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
8860 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
8861 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
8862 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
8863 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
8864 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
8865 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
8866 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
8867 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
8868 | #if defined(TARGET_PPC64) | |
8869 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
8870 | #endif | |
8871 | ||
8872 | #if defined(TARGET_PPC64) | |
8873 | #undef GEN_PPC64_R2 | |
8874 | #undef GEN_PPC64_R4 | |
8875 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
8876 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8877 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8878 | PPC_64B) | |
8879 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
8880 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
8881 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
8882 | PPC_64B), \ | |
8883 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
8884 | PPC_64B), \ | |
8885 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
8886 | PPC_64B) | |
8887 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
8888 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
8889 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
8890 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
8891 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
8892 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
8893 | #endif | |
8894 | ||
8895 | #undef _GEN_FLOAT_ACB | |
8896 | #undef GEN_FLOAT_ACB | |
8897 | #undef _GEN_FLOAT_AB | |
8898 | #undef GEN_FLOAT_AB | |
8899 | #undef _GEN_FLOAT_AC | |
8900 | #undef GEN_FLOAT_AC | |
8901 | #undef GEN_FLOAT_B | |
8902 | #undef GEN_FLOAT_BS | |
8903 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
8904 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
8905 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
8906 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
8907 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
8908 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8909 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8910 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
8911 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8912 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8913 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
8914 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
8915 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
8916 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
8917 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
8918 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
8919 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
8920 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
8921 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
8922 | ||
8923 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
8924 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
8925 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
8926 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
8927 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
8928 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
8929 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
8930 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
8931 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
8932 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
8933 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
8934 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
8935 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), | |
8936 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), | |
8937 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), | |
8938 | #if defined(TARGET_PPC64) | |
8939 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), | |
8940 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), | |
8941 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), | |
8942 | #endif | |
8943 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), | |
8944 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
8945 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
8946 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
8947 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT), | |
8948 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT), | |
8949 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT), | |
8950 | ||
8951 | #undef GEN_LD | |
8952 | #undef GEN_LDU | |
8953 | #undef GEN_LDUX | |
cd6e9320 | 8954 | #undef GEN_LDX_E |
5c55ff99 BS |
8955 | #undef GEN_LDS |
8956 | #define GEN_LD(name, ldop, opc, type) \ | |
8957 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8958 | #define GEN_LDU(name, ldop, opc, type) \ | |
8959 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8960 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
8961 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
8962 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
8963 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
8964 | #define GEN_LDS(name, ldop, op, type) \ |
8965 | GEN_LD(name, ldop, op | 0x20, type) \ | |
8966 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
8967 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
8968 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
8969 | ||
8970 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
8971 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
8972 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
8973 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
8974 | #if defined(TARGET_PPC64) | |
8975 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
8976 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
8977 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
8978 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
cd6e9320 | 8979 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
8980 | #endif |
8981 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
8982 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
8983 | ||
8984 | #undef GEN_ST | |
8985 | #undef GEN_STU | |
8986 | #undef GEN_STUX | |
cd6e9320 | 8987 | #undef GEN_STX_E |
5c55ff99 BS |
8988 | #undef GEN_STS |
8989 | #define GEN_ST(name, stop, opc, type) \ | |
8990 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
8991 | #define GEN_STU(name, stop, opc, type) \ | |
8992 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
8993 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
8994 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
8995 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
8996 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
8997 | #define GEN_STS(name, stop, op, type) \ |
8998 | GEN_ST(name, stop, op | 0x20, type) \ | |
8999 | GEN_STU(name, stop, op | 0x21, type) \ | |
9000 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
9001 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
9002 | ||
9003 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
9004 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
9005 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
9006 | #if defined(TARGET_PPC64) | |
9007 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
9008 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
cd6e9320 | 9009 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
9010 | #endif |
9011 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
9012 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
9013 | ||
9014 | #undef GEN_LDF | |
9015 | #undef GEN_LDUF | |
9016 | #undef GEN_LDUXF | |
9017 | #undef GEN_LDXF | |
9018 | #undef GEN_LDFS | |
9019 | #define GEN_LDF(name, ldop, opc, type) \ | |
9020 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9021 | #define GEN_LDUF(name, ldop, opc, type) \ | |
9022 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9023 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
9024 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
9025 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
9026 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
9027 | #define GEN_LDFS(name, ldop, op, type) \ | |
9028 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
9029 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
9030 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
9031 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
9032 | ||
9033 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
9034 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
9035 | ||
9036 | #undef GEN_STF | |
9037 | #undef GEN_STUF | |
9038 | #undef GEN_STUXF | |
9039 | #undef GEN_STXF | |
9040 | #undef GEN_STFS | |
9041 | #define GEN_STF(name, stop, opc, type) \ | |
9042 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
9043 | #define GEN_STUF(name, stop, opc, type) \ | |
9044 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
9045 | #define GEN_STUXF(name, stop, opc, type) \ | |
9046 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
9047 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
9048 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
9049 | #define GEN_STFS(name, stop, op, type) \ | |
9050 | GEN_STF(name, stop, op | 0x20, type) \ | |
9051 | GEN_STUF(name, stop, op | 0x21, type) \ | |
9052 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
9053 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
9054 | ||
9055 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
9056 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
9057 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
9058 | ||
9059 | #undef GEN_CRLOGIC | |
9060 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
9061 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
9062 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
9063 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
9064 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
9065 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
9066 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
9067 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
9068 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
9069 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
9070 | ||
9071 | #undef GEN_MAC_HANDLER | |
9072 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
9073 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
9074 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
9075 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
9076 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
9077 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
9078 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
9079 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
9080 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
9081 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
9082 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
9083 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
9084 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
9085 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
9086 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
9087 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
9088 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
9089 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
9090 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
9091 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
9092 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
9093 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
9094 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
9095 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
9096 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
9097 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
9098 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
9099 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
9100 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
9101 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
9102 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
9103 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
9104 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
9105 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
9106 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
9107 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
9108 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
9109 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
9110 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
9111 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
9112 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
9113 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
9114 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
9115 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
9116 | ||
9117 | #undef GEN_VR_LDX | |
9118 | #undef GEN_VR_STX | |
9119 | #undef GEN_VR_LVE | |
9120 | #undef GEN_VR_STVE | |
9121 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
9122 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9123 | #define GEN_VR_STX(name, opc2, opc3) \ | |
9124 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9125 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
9126 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9127 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
9128 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
9129 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
9130 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
9131 | GEN_VR_LVE(bx, 0x07, 0x00), | |
9132 | GEN_VR_LVE(hx, 0x07, 0x01), | |
9133 | GEN_VR_LVE(wx, 0x07, 0x02), | |
9134 | GEN_VR_STX(svx, 0x07, 0x07), | |
9135 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
9136 | GEN_VR_STVE(bx, 0x07, 0x04), | |
9137 | GEN_VR_STVE(hx, 0x07, 0x05), | |
9138 | GEN_VR_STVE(wx, 0x07, 0x06), | |
9139 | ||
9140 | #undef GEN_VX_LOGICAL | |
9141 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
9142 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9143 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), | |
9144 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
9145 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
9146 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
9147 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
9148 | ||
9149 | #undef GEN_VXFORM | |
9150 | #define GEN_VXFORM(name, opc2, opc3) \ | |
9151 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9152 | GEN_VXFORM(vaddubm, 0, 0), | |
9153 | GEN_VXFORM(vadduhm, 0, 1), | |
9154 | GEN_VXFORM(vadduwm, 0, 2), | |
9155 | GEN_VXFORM(vsububm, 0, 16), | |
9156 | GEN_VXFORM(vsubuhm, 0, 17), | |
9157 | GEN_VXFORM(vsubuwm, 0, 18), | |
9158 | GEN_VXFORM(vmaxub, 1, 0), | |
9159 | GEN_VXFORM(vmaxuh, 1, 1), | |
9160 | GEN_VXFORM(vmaxuw, 1, 2), | |
9161 | GEN_VXFORM(vmaxsb, 1, 4), | |
9162 | GEN_VXFORM(vmaxsh, 1, 5), | |
9163 | GEN_VXFORM(vmaxsw, 1, 6), | |
9164 | GEN_VXFORM(vminub, 1, 8), | |
9165 | GEN_VXFORM(vminuh, 1, 9), | |
9166 | GEN_VXFORM(vminuw, 1, 10), | |
9167 | GEN_VXFORM(vminsb, 1, 12), | |
9168 | GEN_VXFORM(vminsh, 1, 13), | |
9169 | GEN_VXFORM(vminsw, 1, 14), | |
9170 | GEN_VXFORM(vavgub, 1, 16), | |
9171 | GEN_VXFORM(vavguh, 1, 17), | |
9172 | GEN_VXFORM(vavguw, 1, 18), | |
9173 | GEN_VXFORM(vavgsb, 1, 20), | |
9174 | GEN_VXFORM(vavgsh, 1, 21), | |
9175 | GEN_VXFORM(vavgsw, 1, 22), | |
9176 | GEN_VXFORM(vmrghb, 6, 0), | |
9177 | GEN_VXFORM(vmrghh, 6, 1), | |
9178 | GEN_VXFORM(vmrghw, 6, 2), | |
9179 | GEN_VXFORM(vmrglb, 6, 4), | |
9180 | GEN_VXFORM(vmrglh, 6, 5), | |
9181 | GEN_VXFORM(vmrglw, 6, 6), | |
9182 | GEN_VXFORM(vmuloub, 4, 0), | |
9183 | GEN_VXFORM(vmulouh, 4, 1), | |
9184 | GEN_VXFORM(vmulosb, 4, 4), | |
9185 | GEN_VXFORM(vmulosh, 4, 5), | |
9186 | GEN_VXFORM(vmuleub, 4, 8), | |
9187 | GEN_VXFORM(vmuleuh, 4, 9), | |
9188 | GEN_VXFORM(vmulesb, 4, 12), | |
9189 | GEN_VXFORM(vmulesh, 4, 13), | |
9190 | GEN_VXFORM(vslb, 2, 4), | |
9191 | GEN_VXFORM(vslh, 2, 5), | |
9192 | GEN_VXFORM(vslw, 2, 6), | |
9193 | GEN_VXFORM(vsrb, 2, 8), | |
9194 | GEN_VXFORM(vsrh, 2, 9), | |
9195 | GEN_VXFORM(vsrw, 2, 10), | |
9196 | GEN_VXFORM(vsrab, 2, 12), | |
9197 | GEN_VXFORM(vsrah, 2, 13), | |
9198 | GEN_VXFORM(vsraw, 2, 14), | |
9199 | GEN_VXFORM(vslo, 6, 16), | |
9200 | GEN_VXFORM(vsro, 6, 17), | |
9201 | GEN_VXFORM(vaddcuw, 0, 6), | |
9202 | GEN_VXFORM(vsubcuw, 0, 22), | |
9203 | GEN_VXFORM(vaddubs, 0, 8), | |
9204 | GEN_VXFORM(vadduhs, 0, 9), | |
9205 | GEN_VXFORM(vadduws, 0, 10), | |
9206 | GEN_VXFORM(vaddsbs, 0, 12), | |
9207 | GEN_VXFORM(vaddshs, 0, 13), | |
9208 | GEN_VXFORM(vaddsws, 0, 14), | |
9209 | GEN_VXFORM(vsububs, 0, 24), | |
9210 | GEN_VXFORM(vsubuhs, 0, 25), | |
9211 | GEN_VXFORM(vsubuws, 0, 26), | |
9212 | GEN_VXFORM(vsubsbs, 0, 28), | |
9213 | GEN_VXFORM(vsubshs, 0, 29), | |
9214 | GEN_VXFORM(vsubsws, 0, 30), | |
9215 | GEN_VXFORM(vrlb, 2, 0), | |
9216 | GEN_VXFORM(vrlh, 2, 1), | |
9217 | GEN_VXFORM(vrlw, 2, 2), | |
9218 | GEN_VXFORM(vsl, 2, 7), | |
9219 | GEN_VXFORM(vsr, 2, 11), | |
9220 | GEN_VXFORM(vpkuhum, 7, 0), | |
9221 | GEN_VXFORM(vpkuwum, 7, 1), | |
9222 | GEN_VXFORM(vpkuhus, 7, 2), | |
9223 | GEN_VXFORM(vpkuwus, 7, 3), | |
9224 | GEN_VXFORM(vpkshus, 7, 4), | |
9225 | GEN_VXFORM(vpkswus, 7, 5), | |
9226 | GEN_VXFORM(vpkshss, 7, 6), | |
9227 | GEN_VXFORM(vpkswss, 7, 7), | |
9228 | GEN_VXFORM(vpkpx, 7, 12), | |
9229 | GEN_VXFORM(vsum4ubs, 4, 24), | |
9230 | GEN_VXFORM(vsum4sbs, 4, 28), | |
9231 | GEN_VXFORM(vsum4shs, 4, 25), | |
9232 | GEN_VXFORM(vsum2sws, 4, 26), | |
9233 | GEN_VXFORM(vsumsws, 4, 30), | |
9234 | GEN_VXFORM(vaddfp, 5, 0), | |
9235 | GEN_VXFORM(vsubfp, 5, 1), | |
9236 | GEN_VXFORM(vmaxfp, 5, 16), | |
9237 | GEN_VXFORM(vminfp, 5, 17), | |
9238 | ||
9239 | #undef GEN_VXRFORM1 | |
9240 | #undef GEN_VXRFORM | |
9241 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
9242 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
9243 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
9244 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
9245 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
9246 | GEN_VXRFORM(vcmpequb, 3, 0) | |
9247 | GEN_VXRFORM(vcmpequh, 3, 1) | |
9248 | GEN_VXRFORM(vcmpequw, 3, 2) | |
9249 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
9250 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
9251 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
9252 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
9253 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
9254 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
9255 | GEN_VXRFORM(vcmpeqfp, 3, 3) | |
9256 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
9257 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
9258 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
9259 | ||
9260 | #undef GEN_VXFORM_SIMM | |
9261 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
9262 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9263 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
9264 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
9265 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
9266 | ||
9267 | #undef GEN_VXFORM_NOA | |
9268 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
9269 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
9270 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
9271 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
9272 | GEN_VXFORM_NOA(vupklsb, 7, 10), | |
9273 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
9274 | GEN_VXFORM_NOA(vupkhpx, 7, 13), | |
9275 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
9276 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
9277 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 9278 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 BS |
9279 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
9280 | GEN_VXFORM_NOA(vrfim, 5, 8), | |
9281 | GEN_VXFORM_NOA(vrfin, 5, 9), | |
9282 | GEN_VXFORM_NOA(vrfip, 5, 10), | |
9283 | GEN_VXFORM_NOA(vrfiz, 5, 11), | |
9284 | ||
9285 | #undef GEN_VXFORM_UIMM | |
9286 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
9287 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
9288 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
9289 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
9290 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
9291 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
9292 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
9293 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
9294 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
9295 | ||
9296 | #undef GEN_VAFORM_PAIRED | |
9297 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
9298 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
9299 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
9300 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
9301 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
9302 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
9303 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
9304 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
9305 | ||
9306 | #undef GEN_SPE | |
70560da7 FC |
9307 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
9308 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) | |
9309 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9310 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9311 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9312 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9313 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9314 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9315 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
9316 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), | |
9317 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), | |
9318 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9319 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9320 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9321 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9322 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9323 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
9324 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), | |
9325 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
9326 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9327 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9328 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9329 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9330 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
9331 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9332 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
9333 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9334 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
9335 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9336 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
9337 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), | |
9338 | ||
9339 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9340 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9341 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9342 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9343 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9344 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9345 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9346 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9347 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9348 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9349 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9350 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9351 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9352 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9353 | ||
9354 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9355 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
9356 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9357 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
9358 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9359 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), | |
9360 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9361 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9362 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9363 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
9364 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9365 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9366 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
9367 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
9368 | ||
9369 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9370 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9371 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), | |
9372 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9373 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
9374 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9375 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9376 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), | |
9377 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9378 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9379 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9380 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
9381 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9382 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
9383 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
9384 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
5c55ff99 BS |
9385 | |
9386 | #undef GEN_SPEOP_LDST | |
9387 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
9388 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
9389 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
9390 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
9391 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
9392 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
9393 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
9394 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
9395 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
9396 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
9397 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
9398 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
9399 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
9400 | ||
9401 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
9402 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
9403 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
9404 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
9405 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
9406 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
9407 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
9408 | }; | |
9409 | ||
0411a972 | 9410 | #include "helper_regs.h" |
a1389542 | 9411 | #include "translate_init.c" |
79aceca5 | 9412 | |
9a64fbe4 | 9413 | /*****************************************************************************/ |
3fc6c082 | 9414 | /* Misc PowerPC helpers */ |
1328c2bf | 9415 | void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf, |
36081602 | 9416 | int flags) |
79aceca5 | 9417 | { |
3fc6c082 FB |
9418 | #define RGPL 4 |
9419 | #define RFPL 4 | |
3fc6c082 | 9420 | |
79aceca5 FB |
9421 | int i; |
9422 | ||
29979a8d AG |
9423 | cpu_synchronize_state(env); |
9424 | ||
90e189ec | 9425 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9a78eead SW |
9426 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
9427 | env->nip, env->lr, env->ctr, env->xer); | |
90e189ec BS |
9428 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9429 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
9430 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 9431 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 9432 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 9433 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 9434 | " DECR %08" PRIu32 |
76a66253 JM |
9435 | #endif |
9436 | "\n", | |
077fc206 | 9437 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
9438 | #if !defined(CONFIG_USER_ONLY) |
9439 | , cpu_ppc_load_decr(env) | |
9440 | #endif | |
9441 | ); | |
077fc206 | 9442 | #endif |
76a66253 | 9443 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
9444 | if ((i & (RGPL - 1)) == 0) |
9445 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 9446 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 9447 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 9448 | cpu_fprintf(f, "\n"); |
76a66253 | 9449 | } |
3fc6c082 | 9450 | cpu_fprintf(f, "CR "); |
76a66253 | 9451 | for (i = 0; i < 8; i++) |
7fe48483 FB |
9452 | cpu_fprintf(f, "%01x", env->crf[i]); |
9453 | cpu_fprintf(f, " ["); | |
76a66253 JM |
9454 | for (i = 0; i < 8; i++) { |
9455 | char a = '-'; | |
9456 | if (env->crf[i] & 0x08) | |
9457 | a = 'L'; | |
9458 | else if (env->crf[i] & 0x04) | |
9459 | a = 'G'; | |
9460 | else if (env->crf[i] & 0x02) | |
9461 | a = 'E'; | |
7fe48483 | 9462 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 9463 | } |
90e189ec BS |
9464 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
9465 | env->reserve_addr); | |
3fc6c082 FB |
9466 | for (i = 0; i < 32; i++) { |
9467 | if ((i & (RFPL - 1)) == 0) | |
9468 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 9469 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 9470 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 9471 | cpu_fprintf(f, "\n"); |
79aceca5 | 9472 | } |
30304420 | 9473 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 9474 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
9475 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
9476 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
9477 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
9478 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
9479 | ||
9480 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
9481 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
9482 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
9483 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
9484 | ||
9485 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
9486 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
9487 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
9488 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
9489 | ||
9490 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
9491 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
9492 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
9493 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
9494 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
9495 | ||
9496 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
9497 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
9498 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
9499 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
9500 | ||
9501 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
9502 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
9503 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
9504 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
9505 | ||
9506 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
9507 | " EPR " TARGET_FMT_lx "\n", | |
9508 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
9509 | env->spr[SPR_BOOKE_EPR]); | |
9510 | ||
9511 | /* FSL-specific */ | |
9512 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
9513 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
9514 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
9515 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
9516 | ||
9517 | /* | |
9518 | * IVORs are left out as they are large and do not change often -- | |
9519 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
9520 | */ | |
9521 | } | |
9522 | ||
697ab892 DG |
9523 | #if defined(TARGET_PPC64) |
9524 | if (env->flags & POWERPC_FLAG_CFAR) { | |
9525 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
9526 | } | |
9527 | #endif | |
9528 | ||
90dc8812 SW |
9529 | switch (env->mmu_model) { |
9530 | case POWERPC_MMU_32B: | |
9531 | case POWERPC_MMU_601: | |
9532 | case POWERPC_MMU_SOFT_6xx: | |
9533 | case POWERPC_MMU_SOFT_74xx: | |
9534 | #if defined(TARGET_PPC64) | |
9535 | case POWERPC_MMU_620: | |
9536 | case POWERPC_MMU_64B: | |
9537 | #endif | |
9538 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); | |
9539 | break; | |
01662f3e | 9540 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
9541 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
9542 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
9543 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
9544 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
9545 | ||
9546 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
9547 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
9548 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
9549 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
9550 | ||
9551 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
9552 | " TLB1CFG " TARGET_FMT_lx "\n", | |
9553 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
9554 | env->spr[SPR_BOOKE_TLB1CFG]); | |
9555 | break; | |
9556 | default: | |
9557 | break; | |
9558 | } | |
f2e63a42 | 9559 | #endif |
79aceca5 | 9560 | |
3fc6c082 FB |
9561 | #undef RGPL |
9562 | #undef RFPL | |
79aceca5 FB |
9563 | } |
9564 | ||
1328c2bf | 9565 | void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf, |
76a66253 JM |
9566 | int flags) |
9567 | { | |
9568 | #if defined(DO_PPC_STATISTICS) | |
c227f099 | 9569 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
9570 | int op1, op2, op3; |
9571 | ||
9572 | t1 = env->opcodes; | |
9573 | for (op1 = 0; op1 < 64; op1++) { | |
9574 | handler = t1[op1]; | |
9575 | if (is_indirect_opcode(handler)) { | |
9576 | t2 = ind_table(handler); | |
9577 | for (op2 = 0; op2 < 32; op2++) { | |
9578 | handler = t2[op2]; | |
9579 | if (is_indirect_opcode(handler)) { | |
9580 | t3 = ind_table(handler); | |
9581 | for (op3 = 0; op3 < 32; op3++) { | |
9582 | handler = t3[op3]; | |
9583 | if (handler->count == 0) | |
9584 | continue; | |
9585 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9586 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9587 | op1, op2, op3, op1, (op3 << 5) | op2, |
9588 | handler->oname, | |
9589 | handler->count, handler->count); | |
9590 | } | |
9591 | } else { | |
9592 | if (handler->count == 0) | |
9593 | continue; | |
9594 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 9595 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
9596 | op1, op2, op1, op2, handler->oname, |
9597 | handler->count, handler->count); | |
9598 | } | |
9599 | } | |
9600 | } else { | |
9601 | if (handler->count == 0) | |
9602 | continue; | |
0bfcd599 BS |
9603 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
9604 | " %" PRId64 "\n", | |
76a66253 JM |
9605 | op1, op1, handler->oname, |
9606 | handler->count, handler->count); | |
9607 | } | |
9608 | } | |
9609 | #endif | |
9610 | } | |
9611 | ||
9a64fbe4 | 9612 | /*****************************************************************************/ |
1328c2bf | 9613 | static inline void gen_intermediate_code_internal(CPUPPCState *env, |
636aa200 BS |
9614 | TranslationBlock *tb, |
9615 | int search_pc) | |
79aceca5 | 9616 | { |
9fddaa0c | 9617 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 9618 | opc_handler_t **table, *handler; |
0fa85d43 | 9619 | target_ulong pc_start; |
79aceca5 | 9620 | uint16_t *gen_opc_end; |
a1d1bb31 | 9621 | CPUBreakpoint *bp; |
79aceca5 | 9622 | int j, lj = -1; |
2e70f6ef PB |
9623 | int num_insns; |
9624 | int max_insns; | |
79aceca5 FB |
9625 | |
9626 | pc_start = tb->pc; | |
79aceca5 | 9627 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 9628 | ctx.nip = pc_start; |
79aceca5 | 9629 | ctx.tb = tb; |
e1833e1f | 9630 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 9631 | ctx.spr_cb = env->spr_cb; |
76db3ba4 AJ |
9632 | ctx.mem_idx = env->mmu_idx; |
9633 | ctx.access_type = -1; | |
9634 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
d9bce9d9 | 9635 | #if defined(TARGET_PPC64) |
e42a61f1 | 9636 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 9637 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 9638 | #endif |
3cc62370 | 9639 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 9640 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
9641 | ctx.spe_enabled = msr_spe; |
9642 | else | |
9643 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
9644 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
9645 | ctx.altivec_enabled = msr_vr; | |
9646 | else | |
9647 | ctx.altivec_enabled = 0; | |
d26bfc9a | 9648 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 9649 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 9650 | else |
8cbcb4fa | 9651 | ctx.singlestep_enabled = 0; |
d26bfc9a | 9652 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa AJ |
9653 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
9654 | if (unlikely(env->singlestep_enabled)) | |
9655 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
3fc6c082 | 9656 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
9657 | /* Single step trace mode */ |
9658 | msr_se = 1; | |
9659 | #endif | |
2e70f6ef PB |
9660 | num_insns = 0; |
9661 | max_insns = tb->cflags & CF_COUNT_MASK; | |
9662 | if (max_insns == 0) | |
9663 | max_insns = CF_COUNT_MASK; | |
9664 | ||
9665 | gen_icount_start(); | |
9a64fbe4 | 9666 | /* Set env in case of segfault during code fetch */ |
e1833e1f | 9667 | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) { |
72cf2d4f BS |
9668 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
9669 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 9670 | if (bp->pc == ctx.nip) { |
e06fcd75 | 9671 | gen_debug_exception(ctxp); |
ea4e754f FB |
9672 | break; |
9673 | } | |
9674 | } | |
9675 | } | |
76a66253 | 9676 | if (unlikely(search_pc)) { |
79aceca5 FB |
9677 | j = gen_opc_ptr - gen_opc_buf; |
9678 | if (lj < j) { | |
9679 | lj++; | |
9680 | while (lj < j) | |
9681 | gen_opc_instr_start[lj++] = 0; | |
79aceca5 | 9682 | } |
af4b6c54 AJ |
9683 | gen_opc_pc[lj] = ctx.nip; |
9684 | gen_opc_instr_start[lj] = 1; | |
9685 | gen_opc_icount[lj] = num_insns; | |
79aceca5 | 9686 | } |
d12d51d5 | 9687 | LOG_DISAS("----------------\n"); |
90e189ec | 9688 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 9689 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
2e70f6ef PB |
9690 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
9691 | gen_io_start(); | |
76db3ba4 | 9692 | if (unlikely(ctx.le_mode)) { |
2f5a189c | 9693 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 9694 | } else { |
2f5a189c | 9695 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 9696 | } |
d12d51d5 | 9697 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 9698 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
056401ea | 9699 | opc3(ctx.opcode), little_endian ? "little" : "big"); |
fdefe51c | 9700 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
731c54f8 | 9701 | tcg_gen_debug_insn_start(ctx.nip); |
fdefe51c | 9702 | } |
046d6672 | 9703 | ctx.nip += 4; |
3fc6c082 | 9704 | table = env->opcodes; |
2e70f6ef | 9705 | num_insns++; |
79aceca5 FB |
9706 | handler = table[opc1(ctx.opcode)]; |
9707 | if (is_indirect_opcode(handler)) { | |
9708 | table = ind_table(handler); | |
9709 | handler = table[opc2(ctx.opcode)]; | |
9710 | if (is_indirect_opcode(handler)) { | |
9711 | table = ind_table(handler); | |
9712 | handler = table[opc3(ctx.opcode)]; | |
9713 | } | |
9714 | } | |
9715 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 9716 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
9717 | if (qemu_log_enabled()) { |
9718 | qemu_log("invalid/unsupported opcode: " | |
90e189ec BS |
9719 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
9720 | opc1(ctx.opcode), opc2(ctx.opcode), | |
9721 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa | 9722 | } |
76a66253 | 9723 | } else { |
70560da7 FC |
9724 | uint32_t inval; |
9725 | ||
9726 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
9727 | inval = handler->inval2; | |
9728 | } else { | |
9729 | inval = handler->inval1; | |
9730 | } | |
9731 | ||
9732 | if (unlikely((ctx.opcode & inval) != 0)) { | |
93fcfe39 AL |
9733 | if (qemu_log_enabled()) { |
9734 | qemu_log("invalid bits: %08x for opcode: " | |
90e189ec | 9735 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
70560da7 | 9736 | ctx.opcode & inval, opc1(ctx.opcode), |
90e189ec BS |
9737 | opc2(ctx.opcode), opc3(ctx.opcode), |
9738 | ctx.opcode, ctx.nip - 4); | |
76a66253 | 9739 | } |
e06fcd75 | 9740 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 9741 | break; |
79aceca5 | 9742 | } |
79aceca5 | 9743 | } |
4b3686fa | 9744 | (*(handler->handler))(&ctx); |
76a66253 JM |
9745 | #if defined(DO_PPC_STATISTICS) |
9746 | handler->count++; | |
9747 | #endif | |
9a64fbe4 | 9748 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
9749 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
9750 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
9751 | ctx.exception != POWERPC_SYSCALL && | |
9752 | ctx.exception != POWERPC_EXCP_TRAP && | |
9753 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 9754 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 9755 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
2e70f6ef | 9756 | (env->singlestep_enabled) || |
1b530a6d | 9757 | singlestep || |
2e70f6ef | 9758 | num_insns >= max_insns)) { |
d26bfc9a JM |
9759 | /* if we reach a page boundary or are single stepping, stop |
9760 | * generation | |
9761 | */ | |
8dd4983c | 9762 | break; |
76a66253 | 9763 | } |
3fc6c082 | 9764 | } |
2e70f6ef PB |
9765 | if (tb->cflags & CF_LAST_IO) |
9766 | gen_io_end(); | |
e1833e1f | 9767 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 9768 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 9769 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
8cbcb4fa | 9770 | if (unlikely(env->singlestep_enabled)) { |
e06fcd75 | 9771 | gen_debug_exception(ctxp); |
8cbcb4fa | 9772 | } |
76a66253 | 9773 | /* Generate the return instruction */ |
57fec1fe | 9774 | tcg_gen_exit_tb(0); |
9a64fbe4 | 9775 | } |
2e70f6ef | 9776 | gen_icount_end(tb, num_insns); |
79aceca5 | 9777 | *gen_opc_ptr = INDEX_op_end; |
76a66253 | 9778 | if (unlikely(search_pc)) { |
9a64fbe4 FB |
9779 | j = gen_opc_ptr - gen_opc_buf; |
9780 | lj++; | |
9781 | while (lj <= j) | |
9782 | gen_opc_instr_start[lj++] = 0; | |
9a64fbe4 | 9783 | } else { |
046d6672 | 9784 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 9785 | tb->icount = num_insns; |
9a64fbe4 | 9786 | } |
d9bce9d9 | 9787 | #if defined(DEBUG_DISAS) |
8fec2b8c | 9788 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 9789 | int flags; |
237c0af0 | 9790 | flags = env->bfd_mach; |
76db3ba4 | 9791 | flags |= ctx.le_mode << 16; |
93fcfe39 | 9792 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
f4359b9f | 9793 | log_target_disas(env, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 9794 | qemu_log("\n"); |
9fddaa0c | 9795 | } |
79aceca5 | 9796 | #endif |
79aceca5 FB |
9797 | } |
9798 | ||
1328c2bf | 9799 | void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9800 | { |
2cfc5f17 | 9801 | gen_intermediate_code_internal(env, tb, 0); |
79aceca5 FB |
9802 | } |
9803 | ||
1328c2bf | 9804 | void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 9805 | { |
2cfc5f17 | 9806 | gen_intermediate_code_internal(env, tb, 1); |
79aceca5 | 9807 | } |
d2856f1a | 9808 | |
1328c2bf | 9809 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 9810 | { |
d2856f1a | 9811 | env->nip = gen_opc_pc[pc_pos]; |
d2856f1a | 9812 | } |