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Commit | Line | Data |
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3fc6c082 FB |
1 | /* |
2 | * PowerPC CPU initialization for qemu. | |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
f7aa5583 | 5 | * Copyright 2011 Freescale Semiconductor, Inc. |
3fc6c082 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
3fc6c082 FB |
19 | */ |
20 | ||
76cad711 | 21 | #include "disas/bfd.h" |
022c62cb | 22 | #include "exec/gdbstub.h" |
9c17d615 | 23 | #include <sysemu/kvm.h> |
a1e98583 | 24 | #include "kvm_ppc.h" |
9c17d615 | 25 | #include "sysemu/arch_init.h" |
fe828a4d | 26 | #include "sysemu/cpus.h" |
953af181 | 27 | #include "cpu-models.h" |
b632a148 DG |
28 | #include "mmu-hash32.h" |
29 | #include "mmu-hash64.h" | |
4a44d85e | 30 | #include "qemu/error-report.h" |
237c0af0 | 31 | |
3fc6c082 FB |
32 | //#define PPC_DUMP_CPU |
33 | //#define PPC_DEBUG_SPR | |
80d11f44 | 34 | //#define PPC_DUMP_SPR_ACCESSES |
3fc6c082 | 35 | |
e9df014c JM |
36 | /* For user-mode emulation, we don't emulate any IRQ controller */ |
37 | #if defined(CONFIG_USER_ONLY) | |
a750fc0b JM |
38 | #define PPC_IRQ_INIT_FN(name) \ |
39 | static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ | |
40 | { \ | |
e9df014c JM |
41 | } |
42 | #else | |
a750fc0b | 43 | #define PPC_IRQ_INIT_FN(name) \ |
e9df014c JM |
44 | void glue(glue(ppc, name),_irq_init) (CPUPPCState *env); |
45 | #endif | |
a750fc0b | 46 | |
4e290a0b | 47 | PPC_IRQ_INIT_FN(40x); |
e9df014c | 48 | PPC_IRQ_INIT_FN(6xx); |
d0dfae6e | 49 | PPC_IRQ_INIT_FN(970); |
9d52e907 | 50 | PPC_IRQ_INIT_FN(POWER7); |
9fdc60bf | 51 | PPC_IRQ_INIT_FN(e500); |
e9df014c | 52 | |
3fc6c082 FB |
53 | /* Generic callbacks: |
54 | * do nothing but store/retrieve spr value | |
55 | */ | |
91f477fd AG |
56 | static void spr_load_dump_spr(int sprn) |
57 | { | |
58 | #ifdef PPC_DUMP_SPR_ACCESSES | |
59 | TCGv_i32 t0 = tcg_const_i32(sprn); | |
edbe35e0 | 60 | gen_helper_load_dump_spr(cpu_env, t0); |
91f477fd AG |
61 | tcg_temp_free_i32(t0); |
62 | #endif | |
63 | } | |
64 | ||
45d827d2 | 65 | static void spr_read_generic (void *opaque, int gprn, int sprn) |
a496775f | 66 | { |
45d827d2 | 67 | gen_load_spr(cpu_gpr[gprn], sprn); |
91f477fd AG |
68 | spr_load_dump_spr(sprn); |
69 | } | |
70 | ||
71 | static void spr_store_dump_spr(int sprn) | |
72 | { | |
45d827d2 | 73 | #ifdef PPC_DUMP_SPR_ACCESSES |
91f477fd | 74 | TCGv_i32 t0 = tcg_const_i32(sprn); |
edbe35e0 | 75 | gen_helper_store_dump_spr(cpu_env, t0); |
91f477fd | 76 | tcg_temp_free_i32(t0); |
45d827d2 | 77 | #endif |
a496775f JM |
78 | } |
79 | ||
45d827d2 | 80 | static void spr_write_generic (void *opaque, int sprn, int gprn) |
a496775f | 81 | { |
45d827d2 | 82 | gen_store_spr(sprn, cpu_gpr[gprn]); |
91f477fd | 83 | spr_store_dump_spr(sprn); |
45d827d2 | 84 | } |
a496775f JM |
85 | |
86 | #if !defined(CONFIG_USER_ONLY) | |
ba38ab8d AG |
87 | static void spr_write_generic32(void *opaque, int sprn, int gprn) |
88 | { | |
89 | #ifdef TARGET_PPC64 | |
90 | TCGv t0 = tcg_temp_new(); | |
91 | tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); | |
92 | gen_store_spr(sprn, t0); | |
93 | tcg_temp_free(t0); | |
94 | spr_store_dump_spr(sprn); | |
95 | #else | |
96 | spr_write_generic(opaque, sprn, gprn); | |
97 | #endif | |
98 | } | |
99 | ||
45d827d2 | 100 | static void spr_write_clear (void *opaque, int sprn, int gprn) |
a496775f | 101 | { |
45d827d2 AJ |
102 | TCGv t0 = tcg_temp_new(); |
103 | TCGv t1 = tcg_temp_new(); | |
104 | gen_load_spr(t0, sprn); | |
105 | tcg_gen_neg_tl(t1, cpu_gpr[gprn]); | |
106 | tcg_gen_and_tl(t0, t0, t1); | |
107 | gen_store_spr(sprn, t0); | |
108 | tcg_temp_free(t0); | |
109 | tcg_temp_free(t1); | |
a496775f JM |
110 | } |
111 | #endif | |
112 | ||
76a66253 | 113 | /* SPR common to all PowerPC */ |
3fc6c082 | 114 | /* XER */ |
45d827d2 | 115 | static void spr_read_xer (void *opaque, int gprn, int sprn) |
3fc6c082 | 116 | { |
da91a00f | 117 | gen_read_xer(cpu_gpr[gprn]); |
3fc6c082 FB |
118 | } |
119 | ||
45d827d2 | 120 | static void spr_write_xer (void *opaque, int sprn, int gprn) |
3fc6c082 | 121 | { |
da91a00f | 122 | gen_write_xer(cpu_gpr[gprn]); |
3fc6c082 FB |
123 | } |
124 | ||
125 | /* LR */ | |
45d827d2 | 126 | static void spr_read_lr (void *opaque, int gprn, int sprn) |
3fc6c082 | 127 | { |
45d827d2 | 128 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); |
3fc6c082 FB |
129 | } |
130 | ||
45d827d2 | 131 | static void spr_write_lr (void *opaque, int sprn, int gprn) |
3fc6c082 | 132 | { |
45d827d2 | 133 | tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); |
3fc6c082 FB |
134 | } |
135 | ||
697ab892 DG |
136 | /* CFAR */ |
137 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
138 | static void spr_read_cfar (void *opaque, int gprn, int sprn) | |
139 | { | |
140 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); | |
141 | } | |
142 | ||
143 | static void spr_write_cfar (void *opaque, int sprn, int gprn) | |
144 | { | |
145 | tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); | |
146 | } | |
147 | #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ | |
148 | ||
3fc6c082 | 149 | /* CTR */ |
45d827d2 | 150 | static void spr_read_ctr (void *opaque, int gprn, int sprn) |
3fc6c082 | 151 | { |
45d827d2 | 152 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); |
3fc6c082 FB |
153 | } |
154 | ||
45d827d2 | 155 | static void spr_write_ctr (void *opaque, int sprn, int gprn) |
3fc6c082 | 156 | { |
45d827d2 | 157 | tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); |
3fc6c082 FB |
158 | } |
159 | ||
160 | /* User read access to SPR */ | |
161 | /* USPRx */ | |
162 | /* UMMCRx */ | |
163 | /* UPMCx */ | |
164 | /* USIA */ | |
165 | /* UDECR */ | |
45d827d2 | 166 | static void spr_read_ureg (void *opaque, int gprn, int sprn) |
3fc6c082 | 167 | { |
45d827d2 | 168 | gen_load_spr(cpu_gpr[gprn], sprn + 0x10); |
3fc6c082 FB |
169 | } |
170 | ||
76a66253 | 171 | /* SPR common to all non-embedded PowerPC */ |
3fc6c082 | 172 | /* DECR */ |
76a66253 | 173 | #if !defined(CONFIG_USER_ONLY) |
45d827d2 | 174 | static void spr_read_decr (void *opaque, int gprn, int sprn) |
3fc6c082 | 175 | { |
630ecca0 TG |
176 | if (use_icount) { |
177 | gen_io_start(); | |
178 | } | |
d0f1562d | 179 | gen_helper_load_decr(cpu_gpr[gprn], cpu_env); |
630ecca0 TG |
180 | if (use_icount) { |
181 | gen_io_end(); | |
182 | gen_stop_exception(opaque); | |
183 | } | |
3fc6c082 FB |
184 | } |
185 | ||
45d827d2 | 186 | static void spr_write_decr (void *opaque, int sprn, int gprn) |
3fc6c082 | 187 | { |
630ecca0 TG |
188 | if (use_icount) { |
189 | gen_io_start(); | |
190 | } | |
d0f1562d | 191 | gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); |
630ecca0 TG |
192 | if (use_icount) { |
193 | gen_io_end(); | |
194 | gen_stop_exception(opaque); | |
195 | } | |
3fc6c082 | 196 | } |
76a66253 | 197 | #endif |
3fc6c082 | 198 | |
76a66253 | 199 | /* SPR common to all non-embedded PowerPC, except 601 */ |
3fc6c082 | 200 | /* Time base */ |
45d827d2 | 201 | static void spr_read_tbl (void *opaque, int gprn, int sprn) |
3fc6c082 | 202 | { |
630ecca0 TG |
203 | if (use_icount) { |
204 | gen_io_start(); | |
205 | } | |
d0f1562d | 206 | gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); |
630ecca0 TG |
207 | if (use_icount) { |
208 | gen_io_end(); | |
209 | gen_stop_exception(opaque); | |
210 | } | |
3fc6c082 FB |
211 | } |
212 | ||
45d827d2 | 213 | static void spr_read_tbu (void *opaque, int gprn, int sprn) |
3fc6c082 | 214 | { |
630ecca0 TG |
215 | if (use_icount) { |
216 | gen_io_start(); | |
217 | } | |
d0f1562d | 218 | gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); |
630ecca0 TG |
219 | if (use_icount) { |
220 | gen_io_end(); | |
221 | gen_stop_exception(opaque); | |
222 | } | |
3fc6c082 FB |
223 | } |
224 | ||
a062e36c | 225 | __attribute__ (( unused )) |
45d827d2 | 226 | static void spr_read_atbl (void *opaque, int gprn, int sprn) |
a062e36c | 227 | { |
d0f1562d | 228 | gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); |
a062e36c JM |
229 | } |
230 | ||
231 | __attribute__ (( unused )) | |
45d827d2 | 232 | static void spr_read_atbu (void *opaque, int gprn, int sprn) |
a062e36c | 233 | { |
d0f1562d | 234 | gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); |
a062e36c JM |
235 | } |
236 | ||
76a66253 | 237 | #if !defined(CONFIG_USER_ONLY) |
45d827d2 | 238 | static void spr_write_tbl (void *opaque, int sprn, int gprn) |
3fc6c082 | 239 | { |
630ecca0 TG |
240 | if (use_icount) { |
241 | gen_io_start(); | |
242 | } | |
d0f1562d | 243 | gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); |
630ecca0 TG |
244 | if (use_icount) { |
245 | gen_io_end(); | |
246 | gen_stop_exception(opaque); | |
247 | } | |
3fc6c082 FB |
248 | } |
249 | ||
45d827d2 | 250 | static void spr_write_tbu (void *opaque, int sprn, int gprn) |
3fc6c082 | 251 | { |
630ecca0 TG |
252 | if (use_icount) { |
253 | gen_io_start(); | |
254 | } | |
d0f1562d | 255 | gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); |
630ecca0 TG |
256 | if (use_icount) { |
257 | gen_io_end(); | |
258 | gen_stop_exception(opaque); | |
259 | } | |
3fc6c082 | 260 | } |
a062e36c JM |
261 | |
262 | __attribute__ (( unused )) | |
45d827d2 | 263 | static void spr_write_atbl (void *opaque, int sprn, int gprn) |
a062e36c | 264 | { |
d0f1562d | 265 | gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); |
a062e36c JM |
266 | } |
267 | ||
268 | __attribute__ (( unused )) | |
45d827d2 | 269 | static void spr_write_atbu (void *opaque, int sprn, int gprn) |
a062e36c | 270 | { |
d0f1562d | 271 | gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); |
a062e36c | 272 | } |
3a7f009a DG |
273 | |
274 | #if defined(TARGET_PPC64) | |
275 | __attribute__ (( unused )) | |
276 | static void spr_read_purr (void *opaque, int gprn, int sprn) | |
277 | { | |
d0f1562d | 278 | gen_helper_load_purr(cpu_gpr[gprn], cpu_env); |
3a7f009a DG |
279 | } |
280 | #endif | |
76a66253 | 281 | #endif |
3fc6c082 | 282 | |
76a66253 | 283 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
284 | /* IBAT0U...IBAT0U */ |
285 | /* IBAT0L...IBAT7L */ | |
45d827d2 | 286 | static void spr_read_ibat (void *opaque, int gprn, int sprn) |
3fc6c082 | 287 | { |
1328c2bf | 288 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
3fc6c082 FB |
289 | } |
290 | ||
45d827d2 | 291 | static void spr_read_ibat_h (void *opaque, int gprn, int sprn) |
3fc6c082 | 292 | { |
1328c2bf | 293 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2])); |
3fc6c082 FB |
294 | } |
295 | ||
45d827d2 | 296 | static void spr_write_ibatu (void *opaque, int sprn, int gprn) |
3fc6c082 | 297 | { |
45d827d2 | 298 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
c6c7cf05 | 299 | gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 300 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
301 | } |
302 | ||
45d827d2 | 303 | static void spr_write_ibatu_h (void *opaque, int sprn, int gprn) |
3fc6c082 | 304 | { |
8daf1781 | 305 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); |
c6c7cf05 | 306 | gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 307 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
308 | } |
309 | ||
45d827d2 | 310 | static void spr_write_ibatl (void *opaque, int sprn, int gprn) |
3fc6c082 | 311 | { |
45d827d2 | 312 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); |
c6c7cf05 | 313 | gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 314 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
315 | } |
316 | ||
45d827d2 | 317 | static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) |
3fc6c082 | 318 | { |
8daf1781 | 319 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); |
c6c7cf05 | 320 | gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 321 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
322 | } |
323 | ||
324 | /* DBAT0U...DBAT7U */ | |
325 | /* DBAT0L...DBAT7L */ | |
45d827d2 | 326 | static void spr_read_dbat (void *opaque, int gprn, int sprn) |
3fc6c082 | 327 | { |
1328c2bf | 328 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); |
3fc6c082 FB |
329 | } |
330 | ||
45d827d2 | 331 | static void spr_read_dbat_h (void *opaque, int gprn, int sprn) |
3fc6c082 | 332 | { |
1328c2bf | 333 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); |
3fc6c082 FB |
334 | } |
335 | ||
45d827d2 | 336 | static void spr_write_dbatu (void *opaque, int sprn, int gprn) |
3fc6c082 | 337 | { |
45d827d2 | 338 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); |
c6c7cf05 | 339 | gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 340 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
341 | } |
342 | ||
45d827d2 | 343 | static void spr_write_dbatu_h (void *opaque, int sprn, int gprn) |
3fc6c082 | 344 | { |
45d827d2 | 345 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); |
c6c7cf05 | 346 | gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 347 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
348 | } |
349 | ||
45d827d2 | 350 | static void spr_write_dbatl (void *opaque, int sprn, int gprn) |
3fc6c082 | 351 | { |
45d827d2 | 352 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); |
c6c7cf05 | 353 | gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 354 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
355 | } |
356 | ||
45d827d2 | 357 | static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) |
3fc6c082 | 358 | { |
45d827d2 | 359 | TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); |
c6c7cf05 | 360 | gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 361 | tcg_temp_free_i32(t0); |
3fc6c082 FB |
362 | } |
363 | ||
364 | /* SDR1 */ | |
45d827d2 | 365 | static void spr_write_sdr1 (void *opaque, int sprn, int gprn) |
3fc6c082 | 366 | { |
d523dd00 | 367 | gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); |
3fc6c082 FB |
368 | } |
369 | ||
76a66253 | 370 | /* 64 bits PowerPC specific SPRs */ |
578bb252 | 371 | #if defined(TARGET_PPC64) |
2adab7d6 BS |
372 | static void spr_read_hior (void *opaque, int gprn, int sprn) |
373 | { | |
1328c2bf | 374 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); |
2adab7d6 BS |
375 | } |
376 | ||
377 | static void spr_write_hior (void *opaque, int sprn, int gprn) | |
378 | { | |
379 | TCGv t0 = tcg_temp_new(); | |
380 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); | |
1328c2bf | 381 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); |
2adab7d6 BS |
382 | tcg_temp_free(t0); |
383 | } | |
76a66253 | 384 | #endif |
a750fc0b | 385 | #endif |
76a66253 JM |
386 | |
387 | /* PowerPC 601 specific registers */ | |
388 | /* RTC */ | |
45d827d2 | 389 | static void spr_read_601_rtcl (void *opaque, int gprn, int sprn) |
76a66253 | 390 | { |
d0f1562d | 391 | gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); |
76a66253 JM |
392 | } |
393 | ||
45d827d2 | 394 | static void spr_read_601_rtcu (void *opaque, int gprn, int sprn) |
76a66253 | 395 | { |
d0f1562d | 396 | gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); |
76a66253 JM |
397 | } |
398 | ||
399 | #if !defined(CONFIG_USER_ONLY) | |
45d827d2 | 400 | static void spr_write_601_rtcu (void *opaque, int sprn, int gprn) |
76a66253 | 401 | { |
d0f1562d | 402 | gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); |
76a66253 JM |
403 | } |
404 | ||
45d827d2 | 405 | static void spr_write_601_rtcl (void *opaque, int sprn, int gprn) |
76a66253 | 406 | { |
d0f1562d | 407 | gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); |
76a66253 | 408 | } |
056401ea | 409 | |
45d827d2 | 410 | static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) |
056401ea JM |
411 | { |
412 | DisasContext *ctx = opaque; | |
413 | ||
d523dd00 | 414 | gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); |
056401ea | 415 | /* Must stop the translation as endianness may have changed */ |
e06fcd75 | 416 | gen_stop_exception(ctx); |
056401ea | 417 | } |
76a66253 JM |
418 | #endif |
419 | ||
420 | /* Unified bats */ | |
421 | #if !defined(CONFIG_USER_ONLY) | |
45d827d2 | 422 | static void spr_read_601_ubat (void *opaque, int gprn, int sprn) |
76a66253 | 423 | { |
1328c2bf | 424 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
76a66253 JM |
425 | } |
426 | ||
45d827d2 | 427 | static void spr_write_601_ubatu (void *opaque, int sprn, int gprn) |
76a66253 | 428 | { |
45d827d2 | 429 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
c6c7cf05 | 430 | gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 431 | tcg_temp_free_i32(t0); |
76a66253 JM |
432 | } |
433 | ||
45d827d2 | 434 | static void spr_write_601_ubatl (void *opaque, int sprn, int gprn) |
76a66253 | 435 | { |
45d827d2 | 436 | TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
c6c7cf05 | 437 | gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 438 | tcg_temp_free_i32(t0); |
76a66253 JM |
439 | } |
440 | #endif | |
441 | ||
442 | /* PowerPC 40x specific registers */ | |
443 | #if !defined(CONFIG_USER_ONLY) | |
45d827d2 | 444 | static void spr_read_40x_pit (void *opaque, int gprn, int sprn) |
76a66253 | 445 | { |
d0f1562d | 446 | gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); |
76a66253 JM |
447 | } |
448 | ||
45d827d2 | 449 | static void spr_write_40x_pit (void *opaque, int sprn, int gprn) |
76a66253 | 450 | { |
d0f1562d | 451 | gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); |
76a66253 JM |
452 | } |
453 | ||
45d827d2 | 454 | static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn) |
8ecc7913 JM |
455 | { |
456 | DisasContext *ctx = opaque; | |
457 | ||
d523dd00 | 458 | gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); |
8ecc7913 | 459 | /* We must stop translation as we may have rebooted */ |
e06fcd75 | 460 | gen_stop_exception(ctx); |
8ecc7913 JM |
461 | } |
462 | ||
45d827d2 | 463 | static void spr_write_40x_sler (void *opaque, int sprn, int gprn) |
c294fc58 | 464 | { |
d523dd00 | 465 | gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); |
c294fc58 JM |
466 | } |
467 | ||
45d827d2 | 468 | static void spr_write_booke_tcr (void *opaque, int sprn, int gprn) |
76a66253 | 469 | { |
d0f1562d | 470 | gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); |
76a66253 JM |
471 | } |
472 | ||
45d827d2 | 473 | static void spr_write_booke_tsr (void *opaque, int sprn, int gprn) |
76a66253 | 474 | { |
d0f1562d | 475 | gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); |
76a66253 JM |
476 | } |
477 | #endif | |
478 | ||
479 | /* PowerPC 403 specific registers */ | |
480 | /* PBL1 / PBU1 / PBL2 / PBU2 */ | |
481 | #if !defined(CONFIG_USER_ONLY) | |
45d827d2 | 482 | static void spr_read_403_pbr (void *opaque, int gprn, int sprn) |
76a66253 | 483 | { |
1328c2bf | 484 | tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); |
76a66253 JM |
485 | } |
486 | ||
45d827d2 | 487 | static void spr_write_403_pbr (void *opaque, int sprn, int gprn) |
76a66253 | 488 | { |
45d827d2 | 489 | TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); |
d523dd00 | 490 | gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); |
45d827d2 | 491 | tcg_temp_free_i32(t0); |
76a66253 JM |
492 | } |
493 | ||
45d827d2 | 494 | static void spr_write_pir (void *opaque, int sprn, int gprn) |
3fc6c082 | 495 | { |
45d827d2 AJ |
496 | TCGv t0 = tcg_temp_new(); |
497 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); | |
498 | gen_store_spr(SPR_PIR, t0); | |
499 | tcg_temp_free(t0); | |
3fc6c082 | 500 | } |
76a66253 | 501 | #endif |
3fc6c082 | 502 | |
d34defbc AJ |
503 | /* SPE specific registers */ |
504 | static void spr_read_spefscr (void *opaque, int gprn, int sprn) | |
505 | { | |
506 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1328c2bf | 507 | tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); |
d34defbc AJ |
508 | tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); |
509 | tcg_temp_free_i32(t0); | |
510 | } | |
511 | ||
512 | static void spr_write_spefscr (void *opaque, int sprn, int gprn) | |
513 | { | |
514 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
515 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); | |
1328c2bf | 516 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); |
d34defbc AJ |
517 | tcg_temp_free_i32(t0); |
518 | } | |
519 | ||
6f5d427d JM |
520 | #if !defined(CONFIG_USER_ONLY) |
521 | /* Callback used to write the exception vector base */ | |
45d827d2 | 522 | static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) |
6f5d427d | 523 | { |
45d827d2 | 524 | TCGv t0 = tcg_temp_new(); |
1328c2bf | 525 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); |
45d827d2 | 526 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
1328c2bf | 527 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); |
45d827d2 | 528 | gen_store_spr(sprn, t0); |
69bd5820 | 529 | tcg_temp_free(t0); |
6f5d427d JM |
530 | } |
531 | ||
45d827d2 | 532 | static void spr_write_excp_vector (void *opaque, int sprn, int gprn) |
6f5d427d JM |
533 | { |
534 | DisasContext *ctx = opaque; | |
e9205258 | 535 | int sprn_offs; |
6f5d427d JM |
536 | |
537 | if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { | |
e9205258 | 538 | sprn_offs = sprn - SPR_BOOKE_IVOR0; |
6f5d427d | 539 | } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { |
e9205258 AG |
540 | sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; |
541 | } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { | |
542 | sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; | |
6f5d427d JM |
543 | } else { |
544 | printf("Trying to write an unknown exception vector %d %03x\n", | |
545 | sprn, sprn); | |
e06fcd75 | 546 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
e9205258 | 547 | return; |
6f5d427d | 548 | } |
e9205258 AG |
549 | |
550 | TCGv t0 = tcg_temp_new(); | |
1328c2bf | 551 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); |
e9205258 | 552 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
1328c2bf | 553 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); |
e9205258 AG |
554 | gen_store_spr(sprn, t0); |
555 | tcg_temp_free(t0); | |
6f5d427d JM |
556 | } |
557 | #endif | |
558 | ||
cf8358c8 AJ |
559 | static inline void vscr_init (CPUPPCState *env, uint32_t val) |
560 | { | |
561 | env->vscr = val; | |
562 | /* Altivec always uses round-to-nearest */ | |
563 | set_float_rounding_mode(float_round_nearest_even, &env->vec_status); | |
564 | set_flush_to_zero(vscr_nj, &env->vec_status); | |
565 | } | |
566 | ||
d67d40ea DG |
567 | #ifdef CONFIG_USER_ONLY |
568 | #define spr_register_kvm(env, num, name, uea_read, uea_write, \ | |
569 | oea_read, oea_write, one_reg_id, initial_value) \ | |
570 | _spr_register(env, num, name, uea_read, uea_write, initial_value) | |
571 | #else | |
572 | #if !defined(CONFIG_KVM) | |
573 | #define spr_register_kvm(env, num, name, uea_read, uea_write, \ | |
574 | oea_read, oea_write, one_reg_id, initial_value) \ | |
575 | _spr_register(env, num, name, uea_read, uea_write, \ | |
576 | oea_read, oea_write, initial_value) | |
76a66253 | 577 | #else |
d67d40ea DG |
578 | #define spr_register_kvm(env, num, name, uea_read, uea_write, \ |
579 | oea_read, oea_write, one_reg_id, initial_value) \ | |
580 | _spr_register(env, num, name, uea_read, uea_write, \ | |
581 | oea_read, oea_write, one_reg_id, initial_value) | |
582 | #endif | |
583 | #endif | |
584 | ||
585 | #define spr_register(env, num, name, uea_read, uea_write, \ | |
586 | oea_read, oea_write, initial_value) \ | |
587 | spr_register_kvm(env, num, name, uea_read, uea_write, \ | |
588 | oea_read, oea_write, 0, initial_value) | |
589 | ||
590 | static inline void _spr_register(CPUPPCState *env, int num, | |
b55266b5 | 591 | const char *name, |
45d827d2 AJ |
592 | void (*uea_read)(void *opaque, int gprn, int sprn), |
593 | void (*uea_write)(void *opaque, int sprn, int gprn), | |
d67d40ea DG |
594 | #if !defined(CONFIG_USER_ONLY) |
595 | ||
45d827d2 AJ |
596 | void (*oea_read)(void *opaque, int gprn, int sprn), |
597 | void (*oea_write)(void *opaque, int sprn, int gprn), | |
76a66253 | 598 | #endif |
d67d40ea DG |
599 | #if defined(CONFIG_KVM) |
600 | uint64_t one_reg_id, | |
601 | #endif | |
602 | target_ulong initial_value) | |
3fc6c082 | 603 | { |
c227f099 | 604 | ppc_spr_t *spr; |
3fc6c082 FB |
605 | |
606 | spr = &env->spr_cb[num]; | |
607 | if (spr->name != NULL ||env-> spr[num] != 0x00000000 || | |
76a66253 JM |
608 | #if !defined(CONFIG_USER_ONLY) |
609 | spr->oea_read != NULL || spr->oea_write != NULL || | |
610 | #endif | |
611 | spr->uea_read != NULL || spr->uea_write != NULL) { | |
3fc6c082 FB |
612 | printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num); |
613 | exit(1); | |
614 | } | |
615 | #if defined(PPC_DEBUG_SPR) | |
90e189ec BS |
616 | printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num, |
617 | name, initial_value); | |
3fc6c082 FB |
618 | #endif |
619 | spr->name = name; | |
620 | spr->uea_read = uea_read; | |
621 | spr->uea_write = uea_write; | |
76a66253 | 622 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
623 | spr->oea_read = oea_read; |
624 | spr->oea_write = oea_write; | |
76a66253 | 625 | #endif |
3fc6c082 FB |
626 | env->spr[num] = initial_value; |
627 | } | |
628 | ||
629 | /* Generic PowerPC SPRs */ | |
630 | static void gen_spr_generic (CPUPPCState *env) | |
631 | { | |
632 | /* Integer processing */ | |
633 | spr_register(env, SPR_XER, "XER", | |
634 | &spr_read_xer, &spr_write_xer, | |
635 | &spr_read_xer, &spr_write_xer, | |
636 | 0x00000000); | |
637 | /* Branch contol */ | |
638 | spr_register(env, SPR_LR, "LR", | |
639 | &spr_read_lr, &spr_write_lr, | |
640 | &spr_read_lr, &spr_write_lr, | |
641 | 0x00000000); | |
642 | spr_register(env, SPR_CTR, "CTR", | |
643 | &spr_read_ctr, &spr_write_ctr, | |
644 | &spr_read_ctr, &spr_write_ctr, | |
645 | 0x00000000); | |
646 | /* Interrupt processing */ | |
647 | spr_register(env, SPR_SRR0, "SRR0", | |
648 | SPR_NOACCESS, SPR_NOACCESS, | |
649 | &spr_read_generic, &spr_write_generic, | |
650 | 0x00000000); | |
651 | spr_register(env, SPR_SRR1, "SRR1", | |
652 | SPR_NOACCESS, SPR_NOACCESS, | |
653 | &spr_read_generic, &spr_write_generic, | |
654 | 0x00000000); | |
655 | /* Processor control */ | |
656 | spr_register(env, SPR_SPRG0, "SPRG0", | |
657 | SPR_NOACCESS, SPR_NOACCESS, | |
658 | &spr_read_generic, &spr_write_generic, | |
659 | 0x00000000); | |
660 | spr_register(env, SPR_SPRG1, "SPRG1", | |
661 | SPR_NOACCESS, SPR_NOACCESS, | |
662 | &spr_read_generic, &spr_write_generic, | |
663 | 0x00000000); | |
664 | spr_register(env, SPR_SPRG2, "SPRG2", | |
665 | SPR_NOACCESS, SPR_NOACCESS, | |
666 | &spr_read_generic, &spr_write_generic, | |
667 | 0x00000000); | |
668 | spr_register(env, SPR_SPRG3, "SPRG3", | |
669 | SPR_NOACCESS, SPR_NOACCESS, | |
670 | &spr_read_generic, &spr_write_generic, | |
671 | 0x00000000); | |
672 | } | |
673 | ||
674 | /* SPR common to all non-embedded PowerPC, including 601 */ | |
675 | static void gen_spr_ne_601 (CPUPPCState *env) | |
676 | { | |
677 | /* Exception processing */ | |
d67d40ea DG |
678 | spr_register_kvm(env, SPR_DSISR, "DSISR", |
679 | SPR_NOACCESS, SPR_NOACCESS, | |
680 | &spr_read_generic, &spr_write_generic, | |
681 | KVM_REG_PPC_DSISR, 0x00000000); | |
682 | spr_register_kvm(env, SPR_DAR, "DAR", | |
683 | SPR_NOACCESS, SPR_NOACCESS, | |
684 | &spr_read_generic, &spr_write_generic, | |
685 | KVM_REG_PPC_DAR, 0x00000000); | |
3fc6c082 FB |
686 | /* Timer */ |
687 | spr_register(env, SPR_DECR, "DECR", | |
688 | SPR_NOACCESS, SPR_NOACCESS, | |
689 | &spr_read_decr, &spr_write_decr, | |
690 | 0x00000000); | |
691 | /* Memory management */ | |
692 | spr_register(env, SPR_SDR1, "SDR1", | |
693 | SPR_NOACCESS, SPR_NOACCESS, | |
bb593904 | 694 | &spr_read_generic, &spr_write_sdr1, |
3fc6c082 FB |
695 | 0x00000000); |
696 | } | |
697 | ||
698 | /* BATs 0-3 */ | |
699 | static void gen_low_BATs (CPUPPCState *env) | |
700 | { | |
f2e63a42 | 701 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
702 | spr_register(env, SPR_IBAT0U, "IBAT0U", |
703 | SPR_NOACCESS, SPR_NOACCESS, | |
704 | &spr_read_ibat, &spr_write_ibatu, | |
705 | 0x00000000); | |
706 | spr_register(env, SPR_IBAT0L, "IBAT0L", | |
707 | SPR_NOACCESS, SPR_NOACCESS, | |
708 | &spr_read_ibat, &spr_write_ibatl, | |
709 | 0x00000000); | |
710 | spr_register(env, SPR_IBAT1U, "IBAT1U", | |
711 | SPR_NOACCESS, SPR_NOACCESS, | |
712 | &spr_read_ibat, &spr_write_ibatu, | |
713 | 0x00000000); | |
714 | spr_register(env, SPR_IBAT1L, "IBAT1L", | |
715 | SPR_NOACCESS, SPR_NOACCESS, | |
716 | &spr_read_ibat, &spr_write_ibatl, | |
717 | 0x00000000); | |
718 | spr_register(env, SPR_IBAT2U, "IBAT2U", | |
719 | SPR_NOACCESS, SPR_NOACCESS, | |
720 | &spr_read_ibat, &spr_write_ibatu, | |
721 | 0x00000000); | |
722 | spr_register(env, SPR_IBAT2L, "IBAT2L", | |
723 | SPR_NOACCESS, SPR_NOACCESS, | |
724 | &spr_read_ibat, &spr_write_ibatl, | |
725 | 0x00000000); | |
726 | spr_register(env, SPR_IBAT3U, "IBAT3U", | |
727 | SPR_NOACCESS, SPR_NOACCESS, | |
728 | &spr_read_ibat, &spr_write_ibatu, | |
729 | 0x00000000); | |
730 | spr_register(env, SPR_IBAT3L, "IBAT3L", | |
731 | SPR_NOACCESS, SPR_NOACCESS, | |
732 | &spr_read_ibat, &spr_write_ibatl, | |
733 | 0x00000000); | |
734 | spr_register(env, SPR_DBAT0U, "DBAT0U", | |
735 | SPR_NOACCESS, SPR_NOACCESS, | |
736 | &spr_read_dbat, &spr_write_dbatu, | |
737 | 0x00000000); | |
738 | spr_register(env, SPR_DBAT0L, "DBAT0L", | |
739 | SPR_NOACCESS, SPR_NOACCESS, | |
740 | &spr_read_dbat, &spr_write_dbatl, | |
741 | 0x00000000); | |
742 | spr_register(env, SPR_DBAT1U, "DBAT1U", | |
743 | SPR_NOACCESS, SPR_NOACCESS, | |
744 | &spr_read_dbat, &spr_write_dbatu, | |
745 | 0x00000000); | |
746 | spr_register(env, SPR_DBAT1L, "DBAT1L", | |
747 | SPR_NOACCESS, SPR_NOACCESS, | |
748 | &spr_read_dbat, &spr_write_dbatl, | |
749 | 0x00000000); | |
750 | spr_register(env, SPR_DBAT2U, "DBAT2U", | |
751 | SPR_NOACCESS, SPR_NOACCESS, | |
752 | &spr_read_dbat, &spr_write_dbatu, | |
753 | 0x00000000); | |
754 | spr_register(env, SPR_DBAT2L, "DBAT2L", | |
755 | SPR_NOACCESS, SPR_NOACCESS, | |
756 | &spr_read_dbat, &spr_write_dbatl, | |
757 | 0x00000000); | |
758 | spr_register(env, SPR_DBAT3U, "DBAT3U", | |
759 | SPR_NOACCESS, SPR_NOACCESS, | |
760 | &spr_read_dbat, &spr_write_dbatu, | |
761 | 0x00000000); | |
762 | spr_register(env, SPR_DBAT3L, "DBAT3L", | |
763 | SPR_NOACCESS, SPR_NOACCESS, | |
764 | &spr_read_dbat, &spr_write_dbatl, | |
765 | 0x00000000); | |
a750fc0b | 766 | env->nb_BATs += 4; |
f2e63a42 | 767 | #endif |
3fc6c082 FB |
768 | } |
769 | ||
770 | /* BATs 4-7 */ | |
771 | static void gen_high_BATs (CPUPPCState *env) | |
772 | { | |
f2e63a42 | 773 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
774 | spr_register(env, SPR_IBAT4U, "IBAT4U", |
775 | SPR_NOACCESS, SPR_NOACCESS, | |
776 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
777 | 0x00000000); | |
778 | spr_register(env, SPR_IBAT4L, "IBAT4L", | |
779 | SPR_NOACCESS, SPR_NOACCESS, | |
780 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
781 | 0x00000000); | |
782 | spr_register(env, SPR_IBAT5U, "IBAT5U", | |
783 | SPR_NOACCESS, SPR_NOACCESS, | |
784 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
785 | 0x00000000); | |
786 | spr_register(env, SPR_IBAT5L, "IBAT5L", | |
787 | SPR_NOACCESS, SPR_NOACCESS, | |
788 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
789 | 0x00000000); | |
790 | spr_register(env, SPR_IBAT6U, "IBAT6U", | |
791 | SPR_NOACCESS, SPR_NOACCESS, | |
792 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
793 | 0x00000000); | |
794 | spr_register(env, SPR_IBAT6L, "IBAT6L", | |
795 | SPR_NOACCESS, SPR_NOACCESS, | |
796 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
797 | 0x00000000); | |
798 | spr_register(env, SPR_IBAT7U, "IBAT7U", | |
799 | SPR_NOACCESS, SPR_NOACCESS, | |
800 | &spr_read_ibat_h, &spr_write_ibatu_h, | |
801 | 0x00000000); | |
802 | spr_register(env, SPR_IBAT7L, "IBAT7L", | |
803 | SPR_NOACCESS, SPR_NOACCESS, | |
804 | &spr_read_ibat_h, &spr_write_ibatl_h, | |
805 | 0x00000000); | |
806 | spr_register(env, SPR_DBAT4U, "DBAT4U", | |
807 | SPR_NOACCESS, SPR_NOACCESS, | |
808 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
809 | 0x00000000); | |
810 | spr_register(env, SPR_DBAT4L, "DBAT4L", | |
811 | SPR_NOACCESS, SPR_NOACCESS, | |
812 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
813 | 0x00000000); | |
814 | spr_register(env, SPR_DBAT5U, "DBAT5U", | |
815 | SPR_NOACCESS, SPR_NOACCESS, | |
816 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
817 | 0x00000000); | |
818 | spr_register(env, SPR_DBAT5L, "DBAT5L", | |
819 | SPR_NOACCESS, SPR_NOACCESS, | |
820 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
821 | 0x00000000); | |
822 | spr_register(env, SPR_DBAT6U, "DBAT6U", | |
823 | SPR_NOACCESS, SPR_NOACCESS, | |
824 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
825 | 0x00000000); | |
826 | spr_register(env, SPR_DBAT6L, "DBAT6L", | |
827 | SPR_NOACCESS, SPR_NOACCESS, | |
828 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
829 | 0x00000000); | |
830 | spr_register(env, SPR_DBAT7U, "DBAT7U", | |
831 | SPR_NOACCESS, SPR_NOACCESS, | |
832 | &spr_read_dbat_h, &spr_write_dbatu_h, | |
833 | 0x00000000); | |
834 | spr_register(env, SPR_DBAT7L, "DBAT7L", | |
835 | SPR_NOACCESS, SPR_NOACCESS, | |
836 | &spr_read_dbat_h, &spr_write_dbatl_h, | |
837 | 0x00000000); | |
a750fc0b | 838 | env->nb_BATs += 4; |
f2e63a42 | 839 | #endif |
3fc6c082 FB |
840 | } |
841 | ||
842 | /* Generic PowerPC time base */ | |
843 | static void gen_tbl (CPUPPCState *env) | |
844 | { | |
845 | spr_register(env, SPR_VTBL, "TBL", | |
846 | &spr_read_tbl, SPR_NOACCESS, | |
847 | &spr_read_tbl, SPR_NOACCESS, | |
848 | 0x00000000); | |
849 | spr_register(env, SPR_TBL, "TBL", | |
de6a1dec DI |
850 | &spr_read_tbl, SPR_NOACCESS, |
851 | &spr_read_tbl, &spr_write_tbl, | |
3fc6c082 FB |
852 | 0x00000000); |
853 | spr_register(env, SPR_VTBU, "TBU", | |
854 | &spr_read_tbu, SPR_NOACCESS, | |
855 | &spr_read_tbu, SPR_NOACCESS, | |
856 | 0x00000000); | |
857 | spr_register(env, SPR_TBU, "TBU", | |
de6a1dec DI |
858 | &spr_read_tbu, SPR_NOACCESS, |
859 | &spr_read_tbu, &spr_write_tbu, | |
3fc6c082 FB |
860 | 0x00000000); |
861 | } | |
862 | ||
76a66253 JM |
863 | /* Softare table search registers */ |
864 | static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) | |
865 | { | |
f2e63a42 | 866 | #if !defined(CONFIG_USER_ONLY) |
76a66253 JM |
867 | env->nb_tlb = nb_tlbs; |
868 | env->nb_ways = nb_ways; | |
869 | env->id_tlbs = 1; | |
1c53accc | 870 | env->tlb_type = TLB_6XX; |
76a66253 JM |
871 | spr_register(env, SPR_DMISS, "DMISS", |
872 | SPR_NOACCESS, SPR_NOACCESS, | |
873 | &spr_read_generic, SPR_NOACCESS, | |
874 | 0x00000000); | |
875 | spr_register(env, SPR_DCMP, "DCMP", | |
876 | SPR_NOACCESS, SPR_NOACCESS, | |
877 | &spr_read_generic, SPR_NOACCESS, | |
878 | 0x00000000); | |
879 | spr_register(env, SPR_HASH1, "HASH1", | |
880 | SPR_NOACCESS, SPR_NOACCESS, | |
881 | &spr_read_generic, SPR_NOACCESS, | |
882 | 0x00000000); | |
883 | spr_register(env, SPR_HASH2, "HASH2", | |
884 | SPR_NOACCESS, SPR_NOACCESS, | |
885 | &spr_read_generic, SPR_NOACCESS, | |
886 | 0x00000000); | |
887 | spr_register(env, SPR_IMISS, "IMISS", | |
888 | SPR_NOACCESS, SPR_NOACCESS, | |
889 | &spr_read_generic, SPR_NOACCESS, | |
890 | 0x00000000); | |
891 | spr_register(env, SPR_ICMP, "ICMP", | |
892 | SPR_NOACCESS, SPR_NOACCESS, | |
893 | &spr_read_generic, SPR_NOACCESS, | |
894 | 0x00000000); | |
895 | spr_register(env, SPR_RPA, "RPA", | |
896 | SPR_NOACCESS, SPR_NOACCESS, | |
897 | &spr_read_generic, &spr_write_generic, | |
898 | 0x00000000); | |
f2e63a42 | 899 | #endif |
76a66253 JM |
900 | } |
901 | ||
902 | /* SPR common to MPC755 and G2 */ | |
903 | static void gen_spr_G2_755 (CPUPPCState *env) | |
904 | { | |
905 | /* SGPRs */ | |
906 | spr_register(env, SPR_SPRG4, "SPRG4", | |
907 | SPR_NOACCESS, SPR_NOACCESS, | |
908 | &spr_read_generic, &spr_write_generic, | |
909 | 0x00000000); | |
910 | spr_register(env, SPR_SPRG5, "SPRG5", | |
911 | SPR_NOACCESS, SPR_NOACCESS, | |
912 | &spr_read_generic, &spr_write_generic, | |
913 | 0x00000000); | |
914 | spr_register(env, SPR_SPRG6, "SPRG6", | |
915 | SPR_NOACCESS, SPR_NOACCESS, | |
916 | &spr_read_generic, &spr_write_generic, | |
917 | 0x00000000); | |
918 | spr_register(env, SPR_SPRG7, "SPRG7", | |
919 | SPR_NOACCESS, SPR_NOACCESS, | |
920 | &spr_read_generic, &spr_write_generic, | |
921 | 0x00000000); | |
76a66253 JM |
922 | } |
923 | ||
3fc6c082 FB |
924 | /* SPR common to all 7xx PowerPC implementations */ |
925 | static void gen_spr_7xx (CPUPPCState *env) | |
926 | { | |
927 | /* Breakpoints */ | |
928 | /* XXX : not implemented */ | |
d67d40ea DG |
929 | spr_register_kvm(env, SPR_DABR, "DABR", |
930 | SPR_NOACCESS, SPR_NOACCESS, | |
931 | &spr_read_generic, &spr_write_generic, | |
932 | KVM_REG_PPC_DABR, 0x00000000); | |
3fc6c082 FB |
933 | /* XXX : not implemented */ |
934 | spr_register(env, SPR_IABR, "IABR", | |
935 | SPR_NOACCESS, SPR_NOACCESS, | |
936 | &spr_read_generic, &spr_write_generic, | |
937 | 0x00000000); | |
938 | /* Cache management */ | |
939 | /* XXX : not implemented */ | |
940 | spr_register(env, SPR_ICTC, "ICTC", | |
941 | SPR_NOACCESS, SPR_NOACCESS, | |
942 | &spr_read_generic, &spr_write_generic, | |
943 | 0x00000000); | |
944 | /* Performance monitors */ | |
945 | /* XXX : not implemented */ | |
946 | spr_register(env, SPR_MMCR0, "MMCR0", | |
947 | SPR_NOACCESS, SPR_NOACCESS, | |
948 | &spr_read_generic, &spr_write_generic, | |
949 | 0x00000000); | |
950 | /* XXX : not implemented */ | |
951 | spr_register(env, SPR_MMCR1, "MMCR1", | |
952 | SPR_NOACCESS, SPR_NOACCESS, | |
953 | &spr_read_generic, &spr_write_generic, | |
954 | 0x00000000); | |
955 | /* XXX : not implemented */ | |
956 | spr_register(env, SPR_PMC1, "PMC1", | |
957 | SPR_NOACCESS, SPR_NOACCESS, | |
958 | &spr_read_generic, &spr_write_generic, | |
959 | 0x00000000); | |
960 | /* XXX : not implemented */ | |
961 | spr_register(env, SPR_PMC2, "PMC2", | |
962 | SPR_NOACCESS, SPR_NOACCESS, | |
963 | &spr_read_generic, &spr_write_generic, | |
964 | 0x00000000); | |
965 | /* XXX : not implemented */ | |
966 | spr_register(env, SPR_PMC3, "PMC3", | |
967 | SPR_NOACCESS, SPR_NOACCESS, | |
968 | &spr_read_generic, &spr_write_generic, | |
969 | 0x00000000); | |
970 | /* XXX : not implemented */ | |
971 | spr_register(env, SPR_PMC4, "PMC4", | |
972 | SPR_NOACCESS, SPR_NOACCESS, | |
973 | &spr_read_generic, &spr_write_generic, | |
974 | 0x00000000); | |
975 | /* XXX : not implemented */ | |
a750fc0b | 976 | spr_register(env, SPR_SIAR, "SIAR", |
3fc6c082 FB |
977 | SPR_NOACCESS, SPR_NOACCESS, |
978 | &spr_read_generic, SPR_NOACCESS, | |
979 | 0x00000000); | |
578bb252 | 980 | /* XXX : not implemented */ |
3fc6c082 FB |
981 | spr_register(env, SPR_UMMCR0, "UMMCR0", |
982 | &spr_read_ureg, SPR_NOACCESS, | |
983 | &spr_read_ureg, SPR_NOACCESS, | |
984 | 0x00000000); | |
578bb252 | 985 | /* XXX : not implemented */ |
3fc6c082 FB |
986 | spr_register(env, SPR_UMMCR1, "UMMCR1", |
987 | &spr_read_ureg, SPR_NOACCESS, | |
988 | &spr_read_ureg, SPR_NOACCESS, | |
989 | 0x00000000); | |
578bb252 | 990 | /* XXX : not implemented */ |
3fc6c082 FB |
991 | spr_register(env, SPR_UPMC1, "UPMC1", |
992 | &spr_read_ureg, SPR_NOACCESS, | |
993 | &spr_read_ureg, SPR_NOACCESS, | |
994 | 0x00000000); | |
578bb252 | 995 | /* XXX : not implemented */ |
3fc6c082 FB |
996 | spr_register(env, SPR_UPMC2, "UPMC2", |
997 | &spr_read_ureg, SPR_NOACCESS, | |
998 | &spr_read_ureg, SPR_NOACCESS, | |
999 | 0x00000000); | |
578bb252 | 1000 | /* XXX : not implemented */ |
3fc6c082 FB |
1001 | spr_register(env, SPR_UPMC3, "UPMC3", |
1002 | &spr_read_ureg, SPR_NOACCESS, | |
1003 | &spr_read_ureg, SPR_NOACCESS, | |
1004 | 0x00000000); | |
578bb252 | 1005 | /* XXX : not implemented */ |
3fc6c082 FB |
1006 | spr_register(env, SPR_UPMC4, "UPMC4", |
1007 | &spr_read_ureg, SPR_NOACCESS, | |
1008 | &spr_read_ureg, SPR_NOACCESS, | |
1009 | 0x00000000); | |
578bb252 | 1010 | /* XXX : not implemented */ |
a750fc0b | 1011 | spr_register(env, SPR_USIAR, "USIAR", |
3fc6c082 FB |
1012 | &spr_read_ureg, SPR_NOACCESS, |
1013 | &spr_read_ureg, SPR_NOACCESS, | |
1014 | 0x00000000); | |
a750fc0b | 1015 | /* External access control */ |
3fc6c082 | 1016 | /* XXX : not implemented */ |
a750fc0b | 1017 | spr_register(env, SPR_EAR, "EAR", |
3fc6c082 FB |
1018 | SPR_NOACCESS, SPR_NOACCESS, |
1019 | &spr_read_generic, &spr_write_generic, | |
1020 | 0x00000000); | |
a750fc0b JM |
1021 | } |
1022 | ||
f80872e2 DG |
1023 | #ifdef TARGET_PPC64 |
1024 | #ifndef CONFIG_USER_ONLY | |
1025 | static void spr_read_uamr (void *opaque, int gprn, int sprn) | |
1026 | { | |
1027 | gen_load_spr(cpu_gpr[gprn], SPR_AMR); | |
1028 | spr_load_dump_spr(SPR_AMR); | |
1029 | } | |
1030 | ||
1031 | static void spr_write_uamr (void *opaque, int sprn, int gprn) | |
1032 | { | |
1033 | gen_store_spr(SPR_AMR, cpu_gpr[gprn]); | |
1034 | spr_store_dump_spr(SPR_AMR); | |
1035 | } | |
1036 | ||
1037 | static void spr_write_uamr_pr (void *opaque, int sprn, int gprn) | |
1038 | { | |
1039 | TCGv t0 = tcg_temp_new(); | |
1040 | ||
1041 | gen_load_spr(t0, SPR_UAMOR); | |
1042 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); | |
1043 | gen_store_spr(SPR_AMR, t0); | |
1044 | spr_store_dump_spr(SPR_AMR); | |
1045 | } | |
1046 | #endif /* CONFIG_USER_ONLY */ | |
1047 | ||
1048 | static void gen_spr_amr (CPUPPCState *env) | |
1049 | { | |
1050 | #ifndef CONFIG_USER_ONLY | |
1051 | /* Virtual Page Class Key protection */ | |
1052 | /* The AMR is accessible either via SPR 13 or SPR 29. 13 is | |
1053 | * userspace accessible, 29 is privileged. So we only need to set | |
1054 | * the kvm ONE_REG id on one of them, we use 29 */ | |
1055 | spr_register(env, SPR_UAMR, "UAMR", | |
1056 | &spr_read_uamr, &spr_write_uamr_pr, | |
1057 | &spr_read_uamr, &spr_write_uamr, | |
1058 | 0); | |
1059 | spr_register_kvm(env, SPR_AMR, "AMR", | |
1060 | SPR_NOACCESS, SPR_NOACCESS, | |
1061 | &spr_read_generic, &spr_write_generic, | |
1062 | KVM_REG_PPC_AMR, 0xffffffffffffffffULL); | |
1063 | spr_register_kvm(env, SPR_UAMOR, "UAMOR", | |
1064 | SPR_NOACCESS, SPR_NOACCESS, | |
1065 | &spr_read_generic, &spr_write_generic, | |
1066 | KVM_REG_PPC_UAMOR, 0); | |
1067 | #endif /* !CONFIG_USER_ONLY */ | |
1068 | } | |
1069 | #endif /* TARGET_PPC64 */ | |
1070 | ||
a750fc0b JM |
1071 | static void gen_spr_thrm (CPUPPCState *env) |
1072 | { | |
1073 | /* Thermal management */ | |
3fc6c082 | 1074 | /* XXX : not implemented */ |
a750fc0b | 1075 | spr_register(env, SPR_THRM1, "THRM1", |
3fc6c082 FB |
1076 | SPR_NOACCESS, SPR_NOACCESS, |
1077 | &spr_read_generic, &spr_write_generic, | |
1078 | 0x00000000); | |
1079 | /* XXX : not implemented */ | |
a750fc0b | 1080 | spr_register(env, SPR_THRM2, "THRM2", |
3fc6c082 FB |
1081 | SPR_NOACCESS, SPR_NOACCESS, |
1082 | &spr_read_generic, &spr_write_generic, | |
1083 | 0x00000000); | |
3fc6c082 | 1084 | /* XXX : not implemented */ |
a750fc0b | 1085 | spr_register(env, SPR_THRM3, "THRM3", |
3fc6c082 FB |
1086 | SPR_NOACCESS, SPR_NOACCESS, |
1087 | &spr_read_generic, &spr_write_generic, | |
1088 | 0x00000000); | |
1089 | } | |
1090 | ||
1091 | /* SPR specific to PowerPC 604 implementation */ | |
1092 | static void gen_spr_604 (CPUPPCState *env) | |
1093 | { | |
1094 | /* Processor identification */ | |
1095 | spr_register(env, SPR_PIR, "PIR", | |
1096 | SPR_NOACCESS, SPR_NOACCESS, | |
1097 | &spr_read_generic, &spr_write_pir, | |
1098 | 0x00000000); | |
1099 | /* Breakpoints */ | |
1100 | /* XXX : not implemented */ | |
1101 | spr_register(env, SPR_IABR, "IABR", | |
1102 | SPR_NOACCESS, SPR_NOACCESS, | |
1103 | &spr_read_generic, &spr_write_generic, | |
1104 | 0x00000000); | |
1105 | /* XXX : not implemented */ | |
d67d40ea DG |
1106 | spr_register_kvm(env, SPR_DABR, "DABR", |
1107 | SPR_NOACCESS, SPR_NOACCESS, | |
1108 | &spr_read_generic, &spr_write_generic, | |
1109 | KVM_REG_PPC_DABR, 0x00000000); | |
3fc6c082 FB |
1110 | /* Performance counters */ |
1111 | /* XXX : not implemented */ | |
1112 | spr_register(env, SPR_MMCR0, "MMCR0", | |
1113 | SPR_NOACCESS, SPR_NOACCESS, | |
1114 | &spr_read_generic, &spr_write_generic, | |
1115 | 0x00000000); | |
1116 | /* XXX : not implemented */ | |
3fc6c082 FB |
1117 | spr_register(env, SPR_PMC1, "PMC1", |
1118 | SPR_NOACCESS, SPR_NOACCESS, | |
1119 | &spr_read_generic, &spr_write_generic, | |
1120 | 0x00000000); | |
1121 | /* XXX : not implemented */ | |
1122 | spr_register(env, SPR_PMC2, "PMC2", | |
1123 | SPR_NOACCESS, SPR_NOACCESS, | |
1124 | &spr_read_generic, &spr_write_generic, | |
1125 | 0x00000000); | |
1126 | /* XXX : not implemented */ | |
a750fc0b | 1127 | spr_register(env, SPR_SIAR, "SIAR", |
3fc6c082 FB |
1128 | SPR_NOACCESS, SPR_NOACCESS, |
1129 | &spr_read_generic, SPR_NOACCESS, | |
1130 | 0x00000000); | |
1131 | /* XXX : not implemented */ | |
1132 | spr_register(env, SPR_SDA, "SDA", | |
1133 | SPR_NOACCESS, SPR_NOACCESS, | |
1134 | &spr_read_generic, SPR_NOACCESS, | |
1135 | 0x00000000); | |
1136 | /* External access control */ | |
1137 | /* XXX : not implemented */ | |
1138 | spr_register(env, SPR_EAR, "EAR", | |
1139 | SPR_NOACCESS, SPR_NOACCESS, | |
1140 | &spr_read_generic, &spr_write_generic, | |
1141 | 0x00000000); | |
1142 | } | |
1143 | ||
76a66253 JM |
1144 | /* SPR specific to PowerPC 603 implementation */ |
1145 | static void gen_spr_603 (CPUPPCState *env) | |
3fc6c082 | 1146 | { |
76a66253 JM |
1147 | /* External access control */ |
1148 | /* XXX : not implemented */ | |
1149 | spr_register(env, SPR_EAR, "EAR", | |
3fc6c082 | 1150 | SPR_NOACCESS, SPR_NOACCESS, |
76a66253 JM |
1151 | &spr_read_generic, &spr_write_generic, |
1152 | 0x00000000); | |
2bc17322 FC |
1153 | /* Breakpoints */ |
1154 | /* XXX : not implemented */ | |
1155 | spr_register(env, SPR_IABR, "IABR", | |
1156 | SPR_NOACCESS, SPR_NOACCESS, | |
1157 | &spr_read_generic, &spr_write_generic, | |
1158 | 0x00000000); | |
1159 | ||
3fc6c082 FB |
1160 | } |
1161 | ||
76a66253 JM |
1162 | /* SPR specific to PowerPC G2 implementation */ |
1163 | static void gen_spr_G2 (CPUPPCState *env) | |
3fc6c082 | 1164 | { |
76a66253 JM |
1165 | /* Memory base address */ |
1166 | /* MBAR */ | |
578bb252 | 1167 | /* XXX : not implemented */ |
76a66253 JM |
1168 | spr_register(env, SPR_MBAR, "MBAR", |
1169 | SPR_NOACCESS, SPR_NOACCESS, | |
1170 | &spr_read_generic, &spr_write_generic, | |
1171 | 0x00000000); | |
76a66253 | 1172 | /* Exception processing */ |
363be49c | 1173 | spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
76a66253 JM |
1174 | SPR_NOACCESS, SPR_NOACCESS, |
1175 | &spr_read_generic, &spr_write_generic, | |
1176 | 0x00000000); | |
363be49c | 1177 | spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", |
76a66253 JM |
1178 | SPR_NOACCESS, SPR_NOACCESS, |
1179 | &spr_read_generic, &spr_write_generic, | |
1180 | 0x00000000); | |
1181 | /* Breakpoints */ | |
1182 | /* XXX : not implemented */ | |
1183 | spr_register(env, SPR_DABR, "DABR", | |
1184 | SPR_NOACCESS, SPR_NOACCESS, | |
1185 | &spr_read_generic, &spr_write_generic, | |
1186 | 0x00000000); | |
1187 | /* XXX : not implemented */ | |
1188 | spr_register(env, SPR_DABR2, "DABR2", | |
1189 | SPR_NOACCESS, SPR_NOACCESS, | |
1190 | &spr_read_generic, &spr_write_generic, | |
1191 | 0x00000000); | |
1192 | /* XXX : not implemented */ | |
1193 | spr_register(env, SPR_IABR, "IABR", | |
1194 | SPR_NOACCESS, SPR_NOACCESS, | |
1195 | &spr_read_generic, &spr_write_generic, | |
1196 | 0x00000000); | |
1197 | /* XXX : not implemented */ | |
1198 | spr_register(env, SPR_IABR2, "IABR2", | |
1199 | SPR_NOACCESS, SPR_NOACCESS, | |
1200 | &spr_read_generic, &spr_write_generic, | |
1201 | 0x00000000); | |
1202 | /* XXX : not implemented */ | |
1203 | spr_register(env, SPR_IBCR, "IBCR", | |
1204 | SPR_NOACCESS, SPR_NOACCESS, | |
1205 | &spr_read_generic, &spr_write_generic, | |
1206 | 0x00000000); | |
1207 | /* XXX : not implemented */ | |
1208 | spr_register(env, SPR_DBCR, "DBCR", | |
1209 | SPR_NOACCESS, SPR_NOACCESS, | |
1210 | &spr_read_generic, &spr_write_generic, | |
1211 | 0x00000000); | |
1212 | } | |
1213 | ||
1214 | /* SPR specific to PowerPC 602 implementation */ | |
1215 | static void gen_spr_602 (CPUPPCState *env) | |
1216 | { | |
1217 | /* ESA registers */ | |
1218 | /* XXX : not implemented */ | |
1219 | spr_register(env, SPR_SER, "SER", | |
1220 | SPR_NOACCESS, SPR_NOACCESS, | |
1221 | &spr_read_generic, &spr_write_generic, | |
1222 | 0x00000000); | |
1223 | /* XXX : not implemented */ | |
1224 | spr_register(env, SPR_SEBR, "SEBR", | |
1225 | SPR_NOACCESS, SPR_NOACCESS, | |
1226 | &spr_read_generic, &spr_write_generic, | |
1227 | 0x00000000); | |
1228 | /* XXX : not implemented */ | |
a750fc0b | 1229 | spr_register(env, SPR_ESASRR, "ESASRR", |
76a66253 JM |
1230 | SPR_NOACCESS, SPR_NOACCESS, |
1231 | &spr_read_generic, &spr_write_generic, | |
1232 | 0x00000000); | |
1233 | /* Floating point status */ | |
1234 | /* XXX : not implemented */ | |
1235 | spr_register(env, SPR_SP, "SP", | |
1236 | SPR_NOACCESS, SPR_NOACCESS, | |
1237 | &spr_read_generic, &spr_write_generic, | |
1238 | 0x00000000); | |
1239 | /* XXX : not implemented */ | |
1240 | spr_register(env, SPR_LT, "LT", | |
1241 | SPR_NOACCESS, SPR_NOACCESS, | |
1242 | &spr_read_generic, &spr_write_generic, | |
1243 | 0x00000000); | |
1244 | /* Watchdog timer */ | |
1245 | /* XXX : not implemented */ | |
1246 | spr_register(env, SPR_TCR, "TCR", | |
1247 | SPR_NOACCESS, SPR_NOACCESS, | |
1248 | &spr_read_generic, &spr_write_generic, | |
1249 | 0x00000000); | |
1250 | /* Interrupt base */ | |
1251 | spr_register(env, SPR_IBR, "IBR", | |
1252 | SPR_NOACCESS, SPR_NOACCESS, | |
1253 | &spr_read_generic, &spr_write_generic, | |
1254 | 0x00000000); | |
a750fc0b JM |
1255 | /* XXX : not implemented */ |
1256 | spr_register(env, SPR_IABR, "IABR", | |
1257 | SPR_NOACCESS, SPR_NOACCESS, | |
1258 | &spr_read_generic, &spr_write_generic, | |
1259 | 0x00000000); | |
76a66253 JM |
1260 | } |
1261 | ||
1262 | /* SPR specific to PowerPC 601 implementation */ | |
1263 | static void gen_spr_601 (CPUPPCState *env) | |
1264 | { | |
1265 | /* Multiplication/division register */ | |
1266 | /* MQ */ | |
1267 | spr_register(env, SPR_MQ, "MQ", | |
1268 | &spr_read_generic, &spr_write_generic, | |
1269 | &spr_read_generic, &spr_write_generic, | |
1270 | 0x00000000); | |
1271 | /* RTC registers */ | |
1272 | spr_register(env, SPR_601_RTCU, "RTCU", | |
1273 | SPR_NOACCESS, SPR_NOACCESS, | |
1274 | SPR_NOACCESS, &spr_write_601_rtcu, | |
1275 | 0x00000000); | |
1276 | spr_register(env, SPR_601_VRTCU, "RTCU", | |
1277 | &spr_read_601_rtcu, SPR_NOACCESS, | |
1278 | &spr_read_601_rtcu, SPR_NOACCESS, | |
1279 | 0x00000000); | |
1280 | spr_register(env, SPR_601_RTCL, "RTCL", | |
1281 | SPR_NOACCESS, SPR_NOACCESS, | |
1282 | SPR_NOACCESS, &spr_write_601_rtcl, | |
1283 | 0x00000000); | |
1284 | spr_register(env, SPR_601_VRTCL, "RTCL", | |
1285 | &spr_read_601_rtcl, SPR_NOACCESS, | |
1286 | &spr_read_601_rtcl, SPR_NOACCESS, | |
1287 | 0x00000000); | |
1288 | /* Timer */ | |
1289 | #if 0 /* ? */ | |
1290 | spr_register(env, SPR_601_UDECR, "UDECR", | |
1291 | &spr_read_decr, SPR_NOACCESS, | |
1292 | &spr_read_decr, SPR_NOACCESS, | |
1293 | 0x00000000); | |
1294 | #endif | |
1295 | /* External access control */ | |
1296 | /* XXX : not implemented */ | |
1297 | spr_register(env, SPR_EAR, "EAR", | |
1298 | SPR_NOACCESS, SPR_NOACCESS, | |
1299 | &spr_read_generic, &spr_write_generic, | |
1300 | 0x00000000); | |
1301 | /* Memory management */ | |
f2e63a42 | 1302 | #if !defined(CONFIG_USER_ONLY) |
76a66253 JM |
1303 | spr_register(env, SPR_IBAT0U, "IBAT0U", |
1304 | SPR_NOACCESS, SPR_NOACCESS, | |
1305 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1306 | 0x00000000); | |
1307 | spr_register(env, SPR_IBAT0L, "IBAT0L", | |
1308 | SPR_NOACCESS, SPR_NOACCESS, | |
1309 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1310 | 0x00000000); | |
1311 | spr_register(env, SPR_IBAT1U, "IBAT1U", | |
1312 | SPR_NOACCESS, SPR_NOACCESS, | |
1313 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1314 | 0x00000000); | |
1315 | spr_register(env, SPR_IBAT1L, "IBAT1L", | |
1316 | SPR_NOACCESS, SPR_NOACCESS, | |
1317 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1318 | 0x00000000); | |
1319 | spr_register(env, SPR_IBAT2U, "IBAT2U", | |
1320 | SPR_NOACCESS, SPR_NOACCESS, | |
1321 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1322 | 0x00000000); | |
1323 | spr_register(env, SPR_IBAT2L, "IBAT2L", | |
1324 | SPR_NOACCESS, SPR_NOACCESS, | |
1325 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1326 | 0x00000000); | |
1327 | spr_register(env, SPR_IBAT3U, "IBAT3U", | |
1328 | SPR_NOACCESS, SPR_NOACCESS, | |
1329 | &spr_read_601_ubat, &spr_write_601_ubatu, | |
1330 | 0x00000000); | |
1331 | spr_register(env, SPR_IBAT3L, "IBAT3L", | |
1332 | SPR_NOACCESS, SPR_NOACCESS, | |
1333 | &spr_read_601_ubat, &spr_write_601_ubatl, | |
1334 | 0x00000000); | |
a750fc0b | 1335 | env->nb_BATs = 4; |
f2e63a42 | 1336 | #endif |
a750fc0b JM |
1337 | } |
1338 | ||
1339 | static void gen_spr_74xx (CPUPPCState *env) | |
1340 | { | |
1341 | /* Processor identification */ | |
1342 | spr_register(env, SPR_PIR, "PIR", | |
1343 | SPR_NOACCESS, SPR_NOACCESS, | |
1344 | &spr_read_generic, &spr_write_pir, | |
1345 | 0x00000000); | |
1346 | /* XXX : not implemented */ | |
1347 | spr_register(env, SPR_MMCR2, "MMCR2", | |
1348 | SPR_NOACCESS, SPR_NOACCESS, | |
1349 | &spr_read_generic, &spr_write_generic, | |
1350 | 0x00000000); | |
578bb252 | 1351 | /* XXX : not implemented */ |
a750fc0b JM |
1352 | spr_register(env, SPR_UMMCR2, "UMMCR2", |
1353 | &spr_read_ureg, SPR_NOACCESS, | |
1354 | &spr_read_ureg, SPR_NOACCESS, | |
1355 | 0x00000000); | |
1356 | /* XXX: not implemented */ | |
1357 | spr_register(env, SPR_BAMR, "BAMR", | |
1358 | SPR_NOACCESS, SPR_NOACCESS, | |
1359 | &spr_read_generic, &spr_write_generic, | |
1360 | 0x00000000); | |
578bb252 | 1361 | /* XXX : not implemented */ |
a750fc0b JM |
1362 | spr_register(env, SPR_MSSCR0, "MSSCR0", |
1363 | SPR_NOACCESS, SPR_NOACCESS, | |
1364 | &spr_read_generic, &spr_write_generic, | |
1365 | 0x00000000); | |
1366 | /* Hardware implementation registers */ | |
1367 | /* XXX : not implemented */ | |
1368 | spr_register(env, SPR_HID0, "HID0", | |
1369 | SPR_NOACCESS, SPR_NOACCESS, | |
1370 | &spr_read_generic, &spr_write_generic, | |
1371 | 0x00000000); | |
1372 | /* XXX : not implemented */ | |
1373 | spr_register(env, SPR_HID1, "HID1", | |
1374 | SPR_NOACCESS, SPR_NOACCESS, | |
1375 | &spr_read_generic, &spr_write_generic, | |
1376 | 0x00000000); | |
1377 | /* Altivec */ | |
1378 | spr_register(env, SPR_VRSAVE, "VRSAVE", | |
1379 | &spr_read_generic, &spr_write_generic, | |
1380 | &spr_read_generic, &spr_write_generic, | |
1381 | 0x00000000); | |
bd928eba JM |
1382 | /* XXX : not implemented */ |
1383 | spr_register(env, SPR_L2CR, "L2CR", | |
1384 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 1385 | &spr_read_generic, NULL, |
bd928eba | 1386 | 0x00000000); |
cf8358c8 AJ |
1387 | /* Not strictly an SPR */ |
1388 | vscr_init(env, 0x00010000); | |
a750fc0b JM |
1389 | } |
1390 | ||
a750fc0b JM |
1391 | static void gen_l3_ctrl (CPUPPCState *env) |
1392 | { | |
1393 | /* L3CR */ | |
1394 | /* XXX : not implemented */ | |
1395 | spr_register(env, SPR_L3CR, "L3CR", | |
1396 | SPR_NOACCESS, SPR_NOACCESS, | |
1397 | &spr_read_generic, &spr_write_generic, | |
1398 | 0x00000000); | |
1399 | /* L3ITCR0 */ | |
578bb252 | 1400 | /* XXX : not implemented */ |
a750fc0b JM |
1401 | spr_register(env, SPR_L3ITCR0, "L3ITCR0", |
1402 | SPR_NOACCESS, SPR_NOACCESS, | |
1403 | &spr_read_generic, &spr_write_generic, | |
1404 | 0x00000000); | |
a750fc0b | 1405 | /* L3PM */ |
578bb252 | 1406 | /* XXX : not implemented */ |
a750fc0b JM |
1407 | spr_register(env, SPR_L3PM, "L3PM", |
1408 | SPR_NOACCESS, SPR_NOACCESS, | |
1409 | &spr_read_generic, &spr_write_generic, | |
1410 | 0x00000000); | |
1411 | } | |
a750fc0b | 1412 | |
578bb252 | 1413 | static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
a750fc0b | 1414 | { |
f2e63a42 | 1415 | #if !defined(CONFIG_USER_ONLY) |
578bb252 JM |
1416 | env->nb_tlb = nb_tlbs; |
1417 | env->nb_ways = nb_ways; | |
1418 | env->id_tlbs = 1; | |
1c53accc | 1419 | env->tlb_type = TLB_6XX; |
578bb252 | 1420 | /* XXX : not implemented */ |
a750fc0b JM |
1421 | spr_register(env, SPR_PTEHI, "PTEHI", |
1422 | SPR_NOACCESS, SPR_NOACCESS, | |
1423 | &spr_read_generic, &spr_write_generic, | |
1424 | 0x00000000); | |
578bb252 | 1425 | /* XXX : not implemented */ |
a750fc0b JM |
1426 | spr_register(env, SPR_PTELO, "PTELO", |
1427 | SPR_NOACCESS, SPR_NOACCESS, | |
1428 | &spr_read_generic, &spr_write_generic, | |
1429 | 0x00000000); | |
578bb252 | 1430 | /* XXX : not implemented */ |
a750fc0b JM |
1431 | spr_register(env, SPR_TLBMISS, "TLBMISS", |
1432 | SPR_NOACCESS, SPR_NOACCESS, | |
1433 | &spr_read_generic, &spr_write_generic, | |
1434 | 0x00000000); | |
f2e63a42 | 1435 | #endif |
76a66253 JM |
1436 | } |
1437 | ||
01662f3e AG |
1438 | #if !defined(CONFIG_USER_ONLY) |
1439 | static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn) | |
1440 | { | |
1441 | TCGv t0 = tcg_temp_new(); | |
1442 | ||
1443 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256); | |
1444 | gen_store_spr(sprn, t0); | |
1445 | tcg_temp_free(t0); | |
1446 | } | |
1447 | ||
1448 | static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn) | |
1449 | { | |
1ff7854e | 1450 | TCGv_i32 t0 = tcg_const_i32(sprn); |
c6c7cf05 | 1451 | gen_helper_booke206_tlbflush(cpu_env, t0); |
1ff7854e | 1452 | tcg_temp_free_i32(t0); |
01662f3e AG |
1453 | } |
1454 | ||
1455 | static void spr_write_booke_pid (void *opaque, int sprn, int gprn) | |
1456 | { | |
1ff7854e | 1457 | TCGv_i32 t0 = tcg_const_i32(sprn); |
c6c7cf05 | 1458 | gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); |
1ff7854e | 1459 | tcg_temp_free_i32(t0); |
01662f3e AG |
1460 | } |
1461 | #endif | |
1462 | ||
80d11f44 | 1463 | static void gen_spr_usprgh (CPUPPCState *env) |
76a66253 | 1464 | { |
80d11f44 JM |
1465 | spr_register(env, SPR_USPRG4, "USPRG4", |
1466 | &spr_read_ureg, SPR_NOACCESS, | |
1467 | &spr_read_ureg, SPR_NOACCESS, | |
1468 | 0x00000000); | |
1469 | spr_register(env, SPR_USPRG5, "USPRG5", | |
1470 | &spr_read_ureg, SPR_NOACCESS, | |
1471 | &spr_read_ureg, SPR_NOACCESS, | |
1472 | 0x00000000); | |
1473 | spr_register(env, SPR_USPRG6, "USPRG6", | |
1474 | &spr_read_ureg, SPR_NOACCESS, | |
1475 | &spr_read_ureg, SPR_NOACCESS, | |
1476 | 0x00000000); | |
1477 | spr_register(env, SPR_USPRG7, "USPRG7", | |
1478 | &spr_read_ureg, SPR_NOACCESS, | |
1479 | &spr_read_ureg, SPR_NOACCESS, | |
76a66253 | 1480 | 0x00000000); |
80d11f44 JM |
1481 | } |
1482 | ||
1483 | /* PowerPC BookE SPR */ | |
1484 | static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask) | |
1485 | { | |
b55266b5 | 1486 | const char *ivor_names[64] = { |
80d11f44 JM |
1487 | "IVOR0", "IVOR1", "IVOR2", "IVOR3", |
1488 | "IVOR4", "IVOR5", "IVOR6", "IVOR7", | |
1489 | "IVOR8", "IVOR9", "IVOR10", "IVOR11", | |
1490 | "IVOR12", "IVOR13", "IVOR14", "IVOR15", | |
1491 | "IVOR16", "IVOR17", "IVOR18", "IVOR19", | |
1492 | "IVOR20", "IVOR21", "IVOR22", "IVOR23", | |
1493 | "IVOR24", "IVOR25", "IVOR26", "IVOR27", | |
1494 | "IVOR28", "IVOR29", "IVOR30", "IVOR31", | |
1495 | "IVOR32", "IVOR33", "IVOR34", "IVOR35", | |
1496 | "IVOR36", "IVOR37", "IVOR38", "IVOR39", | |
1497 | "IVOR40", "IVOR41", "IVOR42", "IVOR43", | |
1498 | "IVOR44", "IVOR45", "IVOR46", "IVOR47", | |
1499 | "IVOR48", "IVOR49", "IVOR50", "IVOR51", | |
1500 | "IVOR52", "IVOR53", "IVOR54", "IVOR55", | |
1501 | "IVOR56", "IVOR57", "IVOR58", "IVOR59", | |
1502 | "IVOR60", "IVOR61", "IVOR62", "IVOR63", | |
1503 | }; | |
1504 | #define SPR_BOOKE_IVORxx (-1) | |
1505 | int ivor_sprn[64] = { | |
1506 | SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, | |
1507 | SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, | |
1508 | SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, | |
1509 | SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, | |
1510 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1511 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1512 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1513 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1514 | SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, | |
e9205258 AG |
1515 | SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, |
1516 | SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, | |
80d11f44 JM |
1517 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
1518 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1519 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1520 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1521 | SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, | |
1522 | }; | |
1523 | int i; | |
1524 | ||
76a66253 | 1525 | /* Interrupt processing */ |
363be49c | 1526 | spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
76a66253 JM |
1527 | SPR_NOACCESS, SPR_NOACCESS, |
1528 | &spr_read_generic, &spr_write_generic, | |
1529 | 0x00000000); | |
363be49c JM |
1530 | spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", |
1531 | SPR_NOACCESS, SPR_NOACCESS, | |
1532 | &spr_read_generic, &spr_write_generic, | |
1533 | 0x00000000); | |
76a66253 JM |
1534 | /* Debug */ |
1535 | /* XXX : not implemented */ | |
1536 | spr_register(env, SPR_BOOKE_IAC1, "IAC1", | |
1537 | SPR_NOACCESS, SPR_NOACCESS, | |
1538 | &spr_read_generic, &spr_write_generic, | |
1539 | 0x00000000); | |
1540 | /* XXX : not implemented */ | |
1541 | spr_register(env, SPR_BOOKE_IAC2, "IAC2", | |
1542 | SPR_NOACCESS, SPR_NOACCESS, | |
1543 | &spr_read_generic, &spr_write_generic, | |
1544 | 0x00000000); | |
1545 | /* XXX : not implemented */ | |
76a66253 JM |
1546 | spr_register(env, SPR_BOOKE_DAC1, "DAC1", |
1547 | SPR_NOACCESS, SPR_NOACCESS, | |
1548 | &spr_read_generic, &spr_write_generic, | |
1549 | 0x00000000); | |
1550 | /* XXX : not implemented */ | |
1551 | spr_register(env, SPR_BOOKE_DAC2, "DAC2", | |
1552 | SPR_NOACCESS, SPR_NOACCESS, | |
1553 | &spr_read_generic, &spr_write_generic, | |
1554 | 0x00000000); | |
1555 | /* XXX : not implemented */ | |
76a66253 JM |
1556 | spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", |
1557 | SPR_NOACCESS, SPR_NOACCESS, | |
e598a9c5 | 1558 | &spr_read_generic, &spr_write_40x_dbcr0, |
76a66253 JM |
1559 | 0x00000000); |
1560 | /* XXX : not implemented */ | |
1561 | spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", | |
1562 | SPR_NOACCESS, SPR_NOACCESS, | |
1563 | &spr_read_generic, &spr_write_generic, | |
1564 | 0x00000000); | |
1565 | /* XXX : not implemented */ | |
1566 | spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", | |
1567 | SPR_NOACCESS, SPR_NOACCESS, | |
1568 | &spr_read_generic, &spr_write_generic, | |
1569 | 0x00000000); | |
1570 | /* XXX : not implemented */ | |
1571 | spr_register(env, SPR_BOOKE_DBSR, "DBSR", | |
1572 | SPR_NOACCESS, SPR_NOACCESS, | |
8ecc7913 | 1573 | &spr_read_generic, &spr_write_clear, |
76a66253 JM |
1574 | 0x00000000); |
1575 | spr_register(env, SPR_BOOKE_DEAR, "DEAR", | |
1576 | SPR_NOACCESS, SPR_NOACCESS, | |
1577 | &spr_read_generic, &spr_write_generic, | |
1578 | 0x00000000); | |
1579 | spr_register(env, SPR_BOOKE_ESR, "ESR", | |
1580 | SPR_NOACCESS, SPR_NOACCESS, | |
1581 | &spr_read_generic, &spr_write_generic, | |
1582 | 0x00000000); | |
363be49c JM |
1583 | spr_register(env, SPR_BOOKE_IVPR, "IVPR", |
1584 | SPR_NOACCESS, SPR_NOACCESS, | |
6f5d427d | 1585 | &spr_read_generic, &spr_write_excp_prefix, |
363be49c JM |
1586 | 0x00000000); |
1587 | /* Exception vectors */ | |
80d11f44 JM |
1588 | for (i = 0; i < 64; i++) { |
1589 | if (ivor_mask & (1ULL << i)) { | |
1590 | if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { | |
1591 | fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); | |
1592 | exit(1); | |
1593 | } | |
1594 | spr_register(env, ivor_sprn[i], ivor_names[i], | |
1595 | SPR_NOACCESS, SPR_NOACCESS, | |
1596 | &spr_read_generic, &spr_write_excp_vector, | |
1597 | 0x00000000); | |
1598 | } | |
1599 | } | |
76a66253 JM |
1600 | spr_register(env, SPR_BOOKE_PID, "PID", |
1601 | SPR_NOACCESS, SPR_NOACCESS, | |
01662f3e | 1602 | &spr_read_generic, &spr_write_booke_pid, |
76a66253 JM |
1603 | 0x00000000); |
1604 | spr_register(env, SPR_BOOKE_TCR, "TCR", | |
1605 | SPR_NOACCESS, SPR_NOACCESS, | |
1606 | &spr_read_generic, &spr_write_booke_tcr, | |
1607 | 0x00000000); | |
1608 | spr_register(env, SPR_BOOKE_TSR, "TSR", | |
1609 | SPR_NOACCESS, SPR_NOACCESS, | |
1610 | &spr_read_generic, &spr_write_booke_tsr, | |
1611 | 0x00000000); | |
1612 | /* Timer */ | |
1613 | spr_register(env, SPR_DECR, "DECR", | |
1614 | SPR_NOACCESS, SPR_NOACCESS, | |
1615 | &spr_read_decr, &spr_write_decr, | |
1616 | 0x00000000); | |
1617 | spr_register(env, SPR_BOOKE_DECAR, "DECAR", | |
1618 | SPR_NOACCESS, SPR_NOACCESS, | |
1619 | SPR_NOACCESS, &spr_write_generic, | |
1620 | 0x00000000); | |
1621 | /* SPRGs */ | |
1622 | spr_register(env, SPR_USPRG0, "USPRG0", | |
1623 | &spr_read_generic, &spr_write_generic, | |
1624 | &spr_read_generic, &spr_write_generic, | |
1625 | 0x00000000); | |
1626 | spr_register(env, SPR_SPRG4, "SPRG4", | |
1627 | SPR_NOACCESS, SPR_NOACCESS, | |
1628 | &spr_read_generic, &spr_write_generic, | |
1629 | 0x00000000); | |
76a66253 JM |
1630 | spr_register(env, SPR_SPRG5, "SPRG5", |
1631 | SPR_NOACCESS, SPR_NOACCESS, | |
1632 | &spr_read_generic, &spr_write_generic, | |
1633 | 0x00000000); | |
76a66253 JM |
1634 | spr_register(env, SPR_SPRG6, "SPRG6", |
1635 | SPR_NOACCESS, SPR_NOACCESS, | |
1636 | &spr_read_generic, &spr_write_generic, | |
1637 | 0x00000000); | |
76a66253 JM |
1638 | spr_register(env, SPR_SPRG7, "SPRG7", |
1639 | SPR_NOACCESS, SPR_NOACCESS, | |
1640 | &spr_read_generic, &spr_write_generic, | |
1641 | 0x00000000); | |
76a66253 JM |
1642 | } |
1643 | ||
01662f3e AG |
1644 | static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize, |
1645 | uint32_t maxsize, uint32_t flags, | |
1646 | uint32_t nentries) | |
1647 | { | |
1648 | return (assoc << TLBnCFG_ASSOC_SHIFT) | | |
1649 | (minsize << TLBnCFG_MINSIZE_SHIFT) | | |
1650 | (maxsize << TLBnCFG_MAXSIZE_SHIFT) | | |
1651 | flags | nentries; | |
1652 | } | |
1653 | ||
1654 | /* BookE 2.06 storage control registers */ | |
1655 | static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, | |
1656 | uint32_t *tlbncfg) | |
363be49c | 1657 | { |
f2e63a42 | 1658 | #if !defined(CONFIG_USER_ONLY) |
b55266b5 | 1659 | const char *mas_names[8] = { |
80d11f44 JM |
1660 | "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", |
1661 | }; | |
1662 | int mas_sprn[8] = { | |
1663 | SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, | |
1664 | SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, | |
1665 | }; | |
1666 | int i; | |
1667 | ||
363be49c | 1668 | /* TLB assist registers */ |
578bb252 | 1669 | /* XXX : not implemented */ |
80d11f44 | 1670 | for (i = 0; i < 8; i++) { |
ba38ab8d AG |
1671 | void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32; |
1672 | if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { | |
1673 | uea_write = &spr_write_generic; | |
1674 | } | |
80d11f44 JM |
1675 | if (mas_mask & (1 << i)) { |
1676 | spr_register(env, mas_sprn[i], mas_names[i], | |
1677 | SPR_NOACCESS, SPR_NOACCESS, | |
ba38ab8d | 1678 | &spr_read_generic, uea_write, |
80d11f44 JM |
1679 | 0x00000000); |
1680 | } | |
1681 | } | |
363be49c | 1682 | if (env->nb_pids > 1) { |
578bb252 | 1683 | /* XXX : not implemented */ |
363be49c JM |
1684 | spr_register(env, SPR_BOOKE_PID1, "PID1", |
1685 | SPR_NOACCESS, SPR_NOACCESS, | |
01662f3e | 1686 | &spr_read_generic, &spr_write_booke_pid, |
363be49c JM |
1687 | 0x00000000); |
1688 | } | |
1689 | if (env->nb_pids > 2) { | |
578bb252 | 1690 | /* XXX : not implemented */ |
363be49c JM |
1691 | spr_register(env, SPR_BOOKE_PID2, "PID2", |
1692 | SPR_NOACCESS, SPR_NOACCESS, | |
01662f3e | 1693 | &spr_read_generic, &spr_write_booke_pid, |
363be49c JM |
1694 | 0x00000000); |
1695 | } | |
578bb252 | 1696 | /* XXX : not implemented */ |
65f9ee8d | 1697 | spr_register(env, SPR_MMUCFG, "MMUCFG", |
363be49c JM |
1698 | SPR_NOACCESS, SPR_NOACCESS, |
1699 | &spr_read_generic, SPR_NOACCESS, | |
1700 | 0x00000000); /* TOFIX */ | |
363be49c JM |
1701 | switch (env->nb_ways) { |
1702 | case 4: | |
1703 | spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", | |
1704 | SPR_NOACCESS, SPR_NOACCESS, | |
1705 | &spr_read_generic, SPR_NOACCESS, | |
01662f3e | 1706 | tlbncfg[3]); |
363be49c JM |
1707 | /* Fallthru */ |
1708 | case 3: | |
1709 | spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", | |
1710 | SPR_NOACCESS, SPR_NOACCESS, | |
1711 | &spr_read_generic, SPR_NOACCESS, | |
01662f3e | 1712 | tlbncfg[2]); |
363be49c JM |
1713 | /* Fallthru */ |
1714 | case 2: | |
1715 | spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", | |
1716 | SPR_NOACCESS, SPR_NOACCESS, | |
1717 | &spr_read_generic, SPR_NOACCESS, | |
01662f3e | 1718 | tlbncfg[1]); |
363be49c JM |
1719 | /* Fallthru */ |
1720 | case 1: | |
1721 | spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", | |
1722 | SPR_NOACCESS, SPR_NOACCESS, | |
1723 | &spr_read_generic, SPR_NOACCESS, | |
01662f3e | 1724 | tlbncfg[0]); |
363be49c JM |
1725 | /* Fallthru */ |
1726 | case 0: | |
1727 | default: | |
1728 | break; | |
1729 | } | |
f2e63a42 | 1730 | #endif |
01662f3e AG |
1731 | |
1732 | gen_spr_usprgh(env); | |
363be49c JM |
1733 | } |
1734 | ||
76a66253 JM |
1735 | /* SPR specific to PowerPC 440 implementation */ |
1736 | static void gen_spr_440 (CPUPPCState *env) | |
1737 | { | |
1738 | /* Cache control */ | |
1739 | /* XXX : not implemented */ | |
1740 | spr_register(env, SPR_440_DNV0, "DNV0", | |
1741 | SPR_NOACCESS, SPR_NOACCESS, | |
1742 | &spr_read_generic, &spr_write_generic, | |
1743 | 0x00000000); | |
1744 | /* XXX : not implemented */ | |
1745 | spr_register(env, SPR_440_DNV1, "DNV1", | |
1746 | SPR_NOACCESS, SPR_NOACCESS, | |
1747 | &spr_read_generic, &spr_write_generic, | |
1748 | 0x00000000); | |
1749 | /* XXX : not implemented */ | |
1750 | spr_register(env, SPR_440_DNV2, "DNV2", | |
1751 | SPR_NOACCESS, SPR_NOACCESS, | |
1752 | &spr_read_generic, &spr_write_generic, | |
1753 | 0x00000000); | |
1754 | /* XXX : not implemented */ | |
1755 | spr_register(env, SPR_440_DNV3, "DNV3", | |
1756 | SPR_NOACCESS, SPR_NOACCESS, | |
1757 | &spr_read_generic, &spr_write_generic, | |
1758 | 0x00000000); | |
1759 | /* XXX : not implemented */ | |
2662a059 | 1760 | spr_register(env, SPR_440_DTV0, "DTV0", |
76a66253 JM |
1761 | SPR_NOACCESS, SPR_NOACCESS, |
1762 | &spr_read_generic, &spr_write_generic, | |
1763 | 0x00000000); | |
1764 | /* XXX : not implemented */ | |
2662a059 | 1765 | spr_register(env, SPR_440_DTV1, "DTV1", |
76a66253 JM |
1766 | SPR_NOACCESS, SPR_NOACCESS, |
1767 | &spr_read_generic, &spr_write_generic, | |
1768 | 0x00000000); | |
1769 | /* XXX : not implemented */ | |
2662a059 | 1770 | spr_register(env, SPR_440_DTV2, "DTV2", |
76a66253 JM |
1771 | SPR_NOACCESS, SPR_NOACCESS, |
1772 | &spr_read_generic, &spr_write_generic, | |
1773 | 0x00000000); | |
1774 | /* XXX : not implemented */ | |
2662a059 | 1775 | spr_register(env, SPR_440_DTV3, "DTV3", |
76a66253 JM |
1776 | SPR_NOACCESS, SPR_NOACCESS, |
1777 | &spr_read_generic, &spr_write_generic, | |
1778 | 0x00000000); | |
1779 | /* XXX : not implemented */ | |
1780 | spr_register(env, SPR_440_DVLIM, "DVLIM", | |
1781 | SPR_NOACCESS, SPR_NOACCESS, | |
1782 | &spr_read_generic, &spr_write_generic, | |
1783 | 0x00000000); | |
1784 | /* XXX : not implemented */ | |
1785 | spr_register(env, SPR_440_INV0, "INV0", | |
1786 | SPR_NOACCESS, SPR_NOACCESS, | |
1787 | &spr_read_generic, &spr_write_generic, | |
1788 | 0x00000000); | |
1789 | /* XXX : not implemented */ | |
1790 | spr_register(env, SPR_440_INV1, "INV1", | |
1791 | SPR_NOACCESS, SPR_NOACCESS, | |
1792 | &spr_read_generic, &spr_write_generic, | |
1793 | 0x00000000); | |
1794 | /* XXX : not implemented */ | |
1795 | spr_register(env, SPR_440_INV2, "INV2", | |
1796 | SPR_NOACCESS, SPR_NOACCESS, | |
1797 | &spr_read_generic, &spr_write_generic, | |
1798 | 0x00000000); | |
1799 | /* XXX : not implemented */ | |
1800 | spr_register(env, SPR_440_INV3, "INV3", | |
1801 | SPR_NOACCESS, SPR_NOACCESS, | |
1802 | &spr_read_generic, &spr_write_generic, | |
1803 | 0x00000000); | |
1804 | /* XXX : not implemented */ | |
2662a059 | 1805 | spr_register(env, SPR_440_ITV0, "ITV0", |
76a66253 JM |
1806 | SPR_NOACCESS, SPR_NOACCESS, |
1807 | &spr_read_generic, &spr_write_generic, | |
1808 | 0x00000000); | |
1809 | /* XXX : not implemented */ | |
2662a059 | 1810 | spr_register(env, SPR_440_ITV1, "ITV1", |
76a66253 JM |
1811 | SPR_NOACCESS, SPR_NOACCESS, |
1812 | &spr_read_generic, &spr_write_generic, | |
1813 | 0x00000000); | |
1814 | /* XXX : not implemented */ | |
2662a059 | 1815 | spr_register(env, SPR_440_ITV2, "ITV2", |
76a66253 JM |
1816 | SPR_NOACCESS, SPR_NOACCESS, |
1817 | &spr_read_generic, &spr_write_generic, | |
1818 | 0x00000000); | |
1819 | /* XXX : not implemented */ | |
2662a059 | 1820 | spr_register(env, SPR_440_ITV3, "ITV3", |
76a66253 JM |
1821 | SPR_NOACCESS, SPR_NOACCESS, |
1822 | &spr_read_generic, &spr_write_generic, | |
1823 | 0x00000000); | |
1824 | /* XXX : not implemented */ | |
1825 | spr_register(env, SPR_440_IVLIM, "IVLIM", | |
1826 | SPR_NOACCESS, SPR_NOACCESS, | |
1827 | &spr_read_generic, &spr_write_generic, | |
1828 | 0x00000000); | |
1829 | /* Cache debug */ | |
1830 | /* XXX : not implemented */ | |
2662a059 | 1831 | spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", |
76a66253 JM |
1832 | SPR_NOACCESS, SPR_NOACCESS, |
1833 | &spr_read_generic, SPR_NOACCESS, | |
1834 | 0x00000000); | |
1835 | /* XXX : not implemented */ | |
2662a059 | 1836 | spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", |
76a66253 JM |
1837 | SPR_NOACCESS, SPR_NOACCESS, |
1838 | &spr_read_generic, SPR_NOACCESS, | |
1839 | 0x00000000); | |
1840 | /* XXX : not implemented */ | |
2662a059 | 1841 | spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", |
76a66253 JM |
1842 | SPR_NOACCESS, SPR_NOACCESS, |
1843 | &spr_read_generic, SPR_NOACCESS, | |
1844 | 0x00000000); | |
1845 | /* XXX : not implemented */ | |
2662a059 | 1846 | spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", |
76a66253 JM |
1847 | SPR_NOACCESS, SPR_NOACCESS, |
1848 | &spr_read_generic, SPR_NOACCESS, | |
1849 | 0x00000000); | |
1850 | /* XXX : not implemented */ | |
2662a059 | 1851 | spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", |
76a66253 JM |
1852 | SPR_NOACCESS, SPR_NOACCESS, |
1853 | &spr_read_generic, SPR_NOACCESS, | |
1854 | 0x00000000); | |
1855 | /* XXX : not implemented */ | |
1856 | spr_register(env, SPR_440_DBDR, "DBDR", | |
1857 | SPR_NOACCESS, SPR_NOACCESS, | |
1858 | &spr_read_generic, &spr_write_generic, | |
1859 | 0x00000000); | |
1860 | /* Processor control */ | |
1861 | spr_register(env, SPR_4xx_CCR0, "CCR0", | |
1862 | SPR_NOACCESS, SPR_NOACCESS, | |
1863 | &spr_read_generic, &spr_write_generic, | |
1864 | 0x00000000); | |
1865 | spr_register(env, SPR_440_RSTCFG, "RSTCFG", | |
1866 | SPR_NOACCESS, SPR_NOACCESS, | |
1867 | &spr_read_generic, SPR_NOACCESS, | |
1868 | 0x00000000); | |
1869 | /* Storage control */ | |
1870 | spr_register(env, SPR_440_MMUCR, "MMUCR", | |
1871 | SPR_NOACCESS, SPR_NOACCESS, | |
1872 | &spr_read_generic, &spr_write_generic, | |
1873 | 0x00000000); | |
1874 | } | |
1875 | ||
1876 | /* SPR shared between PowerPC 40x implementations */ | |
1877 | static void gen_spr_40x (CPUPPCState *env) | |
1878 | { | |
1879 | /* Cache */ | |
5cbdb3a3 | 1880 | /* not emulated, as QEMU do not emulate caches */ |
76a66253 JM |
1881 | spr_register(env, SPR_40x_DCCR, "DCCR", |
1882 | SPR_NOACCESS, SPR_NOACCESS, | |
1883 | &spr_read_generic, &spr_write_generic, | |
1884 | 0x00000000); | |
5cbdb3a3 | 1885 | /* not emulated, as QEMU do not emulate caches */ |
76a66253 JM |
1886 | spr_register(env, SPR_40x_ICCR, "ICCR", |
1887 | SPR_NOACCESS, SPR_NOACCESS, | |
1888 | &spr_read_generic, &spr_write_generic, | |
1889 | 0x00000000); | |
5cbdb3a3 | 1890 | /* not emulated, as QEMU do not emulate caches */ |
2662a059 | 1891 | spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", |
76a66253 JM |
1892 | SPR_NOACCESS, SPR_NOACCESS, |
1893 | &spr_read_generic, SPR_NOACCESS, | |
1894 | 0x00000000); | |
76a66253 JM |
1895 | /* Exception */ |
1896 | spr_register(env, SPR_40x_DEAR, "DEAR", | |
1897 | SPR_NOACCESS, SPR_NOACCESS, | |
1898 | &spr_read_generic, &spr_write_generic, | |
1899 | 0x00000000); | |
1900 | spr_register(env, SPR_40x_ESR, "ESR", | |
1901 | SPR_NOACCESS, SPR_NOACCESS, | |
1902 | &spr_read_generic, &spr_write_generic, | |
1903 | 0x00000000); | |
1904 | spr_register(env, SPR_40x_EVPR, "EVPR", | |
1905 | SPR_NOACCESS, SPR_NOACCESS, | |
6f5d427d | 1906 | &spr_read_generic, &spr_write_excp_prefix, |
76a66253 JM |
1907 | 0x00000000); |
1908 | spr_register(env, SPR_40x_SRR2, "SRR2", | |
1909 | &spr_read_generic, &spr_write_generic, | |
1910 | &spr_read_generic, &spr_write_generic, | |
1911 | 0x00000000); | |
1912 | spr_register(env, SPR_40x_SRR3, "SRR3", | |
1913 | &spr_read_generic, &spr_write_generic, | |
1914 | &spr_read_generic, &spr_write_generic, | |
1915 | 0x00000000); | |
1916 | /* Timers */ | |
1917 | spr_register(env, SPR_40x_PIT, "PIT", | |
1918 | SPR_NOACCESS, SPR_NOACCESS, | |
1919 | &spr_read_40x_pit, &spr_write_40x_pit, | |
1920 | 0x00000000); | |
1921 | spr_register(env, SPR_40x_TCR, "TCR", | |
1922 | SPR_NOACCESS, SPR_NOACCESS, | |
1923 | &spr_read_generic, &spr_write_booke_tcr, | |
1924 | 0x00000000); | |
1925 | spr_register(env, SPR_40x_TSR, "TSR", | |
1926 | SPR_NOACCESS, SPR_NOACCESS, | |
1927 | &spr_read_generic, &spr_write_booke_tsr, | |
1928 | 0x00000000); | |
2662a059 JM |
1929 | } |
1930 | ||
1931 | /* SPR specific to PowerPC 405 implementation */ | |
1932 | static void gen_spr_405 (CPUPPCState *env) | |
1933 | { | |
1934 | /* MMU */ | |
1935 | spr_register(env, SPR_40x_PID, "PID", | |
76a66253 JM |
1936 | SPR_NOACCESS, SPR_NOACCESS, |
1937 | &spr_read_generic, &spr_write_generic, | |
1938 | 0x00000000); | |
2662a059 | 1939 | spr_register(env, SPR_4xx_CCR0, "CCR0", |
76a66253 JM |
1940 | SPR_NOACCESS, SPR_NOACCESS, |
1941 | &spr_read_generic, &spr_write_generic, | |
2662a059 JM |
1942 | 0x00700000); |
1943 | /* Debug interface */ | |
76a66253 JM |
1944 | /* XXX : not implemented */ |
1945 | spr_register(env, SPR_40x_DBCR0, "DBCR0", | |
1946 | SPR_NOACCESS, SPR_NOACCESS, | |
8ecc7913 | 1947 | &spr_read_generic, &spr_write_40x_dbcr0, |
76a66253 JM |
1948 | 0x00000000); |
1949 | /* XXX : not implemented */ | |
2662a059 JM |
1950 | spr_register(env, SPR_405_DBCR1, "DBCR1", |
1951 | SPR_NOACCESS, SPR_NOACCESS, | |
1952 | &spr_read_generic, &spr_write_generic, | |
1953 | 0x00000000); | |
1954 | /* XXX : not implemented */ | |
76a66253 JM |
1955 | spr_register(env, SPR_40x_DBSR, "DBSR", |
1956 | SPR_NOACCESS, SPR_NOACCESS, | |
8ecc7913 JM |
1957 | &spr_read_generic, &spr_write_clear, |
1958 | /* Last reset was system reset */ | |
76a66253 JM |
1959 | 0x00000300); |
1960 | /* XXX : not implemented */ | |
2662a059 | 1961 | spr_register(env, SPR_40x_DAC1, "DAC1", |
76a66253 JM |
1962 | SPR_NOACCESS, SPR_NOACCESS, |
1963 | &spr_read_generic, &spr_write_generic, | |
1964 | 0x00000000); | |
2662a059 | 1965 | spr_register(env, SPR_40x_DAC2, "DAC2", |
76a66253 JM |
1966 | SPR_NOACCESS, SPR_NOACCESS, |
1967 | &spr_read_generic, &spr_write_generic, | |
1968 | 0x00000000); | |
2662a059 JM |
1969 | /* XXX : not implemented */ |
1970 | spr_register(env, SPR_405_DVC1, "DVC1", | |
76a66253 JM |
1971 | SPR_NOACCESS, SPR_NOACCESS, |
1972 | &spr_read_generic, &spr_write_generic, | |
2662a059 | 1973 | 0x00000000); |
76a66253 | 1974 | /* XXX : not implemented */ |
2662a059 | 1975 | spr_register(env, SPR_405_DVC2, "DVC2", |
76a66253 JM |
1976 | SPR_NOACCESS, SPR_NOACCESS, |
1977 | &spr_read_generic, &spr_write_generic, | |
1978 | 0x00000000); | |
1979 | /* XXX : not implemented */ | |
2662a059 | 1980 | spr_register(env, SPR_40x_IAC1, "IAC1", |
76a66253 JM |
1981 | SPR_NOACCESS, SPR_NOACCESS, |
1982 | &spr_read_generic, &spr_write_generic, | |
1983 | 0x00000000); | |
2662a059 | 1984 | spr_register(env, SPR_40x_IAC2, "IAC2", |
76a66253 JM |
1985 | SPR_NOACCESS, SPR_NOACCESS, |
1986 | &spr_read_generic, &spr_write_generic, | |
1987 | 0x00000000); | |
1988 | /* XXX : not implemented */ | |
1989 | spr_register(env, SPR_405_IAC3, "IAC3", | |
1990 | SPR_NOACCESS, SPR_NOACCESS, | |
1991 | &spr_read_generic, &spr_write_generic, | |
1992 | 0x00000000); | |
1993 | /* XXX : not implemented */ | |
1994 | spr_register(env, SPR_405_IAC4, "IAC4", | |
1995 | SPR_NOACCESS, SPR_NOACCESS, | |
1996 | &spr_read_generic, &spr_write_generic, | |
1997 | 0x00000000); | |
1998 | /* Storage control */ | |
035feb88 | 1999 | /* XXX: TODO: not implemented */ |
76a66253 JM |
2000 | spr_register(env, SPR_405_SLER, "SLER", |
2001 | SPR_NOACCESS, SPR_NOACCESS, | |
c294fc58 | 2002 | &spr_read_generic, &spr_write_40x_sler, |
76a66253 | 2003 | 0x00000000); |
2662a059 JM |
2004 | spr_register(env, SPR_40x_ZPR, "ZPR", |
2005 | SPR_NOACCESS, SPR_NOACCESS, | |
2006 | &spr_read_generic, &spr_write_generic, | |
2007 | 0x00000000); | |
76a66253 JM |
2008 | /* XXX : not implemented */ |
2009 | spr_register(env, SPR_405_SU0R, "SU0R", | |
2010 | SPR_NOACCESS, SPR_NOACCESS, | |
2011 | &spr_read_generic, &spr_write_generic, | |
2012 | 0x00000000); | |
2013 | /* SPRG */ | |
2014 | spr_register(env, SPR_USPRG0, "USPRG0", | |
2015 | &spr_read_ureg, SPR_NOACCESS, | |
2016 | &spr_read_ureg, SPR_NOACCESS, | |
2017 | 0x00000000); | |
2018 | spr_register(env, SPR_SPRG4, "SPRG4", | |
2019 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 2020 | &spr_read_generic, &spr_write_generic, |
76a66253 | 2021 | 0x00000000); |
76a66253 JM |
2022 | spr_register(env, SPR_SPRG5, "SPRG5", |
2023 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 2024 | spr_read_generic, &spr_write_generic, |
76a66253 | 2025 | 0x00000000); |
76a66253 JM |
2026 | spr_register(env, SPR_SPRG6, "SPRG6", |
2027 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 2028 | spr_read_generic, &spr_write_generic, |
76a66253 | 2029 | 0x00000000); |
76a66253 JM |
2030 | spr_register(env, SPR_SPRG7, "SPRG7", |
2031 | SPR_NOACCESS, SPR_NOACCESS, | |
04f20795 | 2032 | spr_read_generic, &spr_write_generic, |
76a66253 | 2033 | 0x00000000); |
80d11f44 | 2034 | gen_spr_usprgh(env); |
76a66253 JM |
2035 | } |
2036 | ||
2037 | /* SPR shared between PowerPC 401 & 403 implementations */ | |
2038 | static void gen_spr_401_403 (CPUPPCState *env) | |
2039 | { | |
2040 | /* Time base */ | |
2041 | spr_register(env, SPR_403_VTBL, "TBL", | |
2042 | &spr_read_tbl, SPR_NOACCESS, | |
2043 | &spr_read_tbl, SPR_NOACCESS, | |
2044 | 0x00000000); | |
2045 | spr_register(env, SPR_403_TBL, "TBL", | |
2046 | SPR_NOACCESS, SPR_NOACCESS, | |
2047 | SPR_NOACCESS, &spr_write_tbl, | |
2048 | 0x00000000); | |
2049 | spr_register(env, SPR_403_VTBU, "TBU", | |
2050 | &spr_read_tbu, SPR_NOACCESS, | |
2051 | &spr_read_tbu, SPR_NOACCESS, | |
2052 | 0x00000000); | |
2053 | spr_register(env, SPR_403_TBU, "TBU", | |
2054 | SPR_NOACCESS, SPR_NOACCESS, | |
2055 | SPR_NOACCESS, &spr_write_tbu, | |
2056 | 0x00000000); | |
2057 | /* Debug */ | |
5cbdb3a3 | 2058 | /* not emulated, as QEMU do not emulate caches */ |
76a66253 JM |
2059 | spr_register(env, SPR_403_CDBCR, "CDBCR", |
2060 | SPR_NOACCESS, SPR_NOACCESS, | |
2061 | &spr_read_generic, &spr_write_generic, | |
2062 | 0x00000000); | |
2063 | } | |
2064 | ||
2662a059 JM |
2065 | /* SPR specific to PowerPC 401 implementation */ |
2066 | static void gen_spr_401 (CPUPPCState *env) | |
2067 | { | |
2068 | /* Debug interface */ | |
2069 | /* XXX : not implemented */ | |
2070 | spr_register(env, SPR_40x_DBCR0, "DBCR", | |
2071 | SPR_NOACCESS, SPR_NOACCESS, | |
2072 | &spr_read_generic, &spr_write_40x_dbcr0, | |
2073 | 0x00000000); | |
2074 | /* XXX : not implemented */ | |
2075 | spr_register(env, SPR_40x_DBSR, "DBSR", | |
2076 | SPR_NOACCESS, SPR_NOACCESS, | |
2077 | &spr_read_generic, &spr_write_clear, | |
2078 | /* Last reset was system reset */ | |
2079 | 0x00000300); | |
2080 | /* XXX : not implemented */ | |
2081 | spr_register(env, SPR_40x_DAC1, "DAC", | |
2082 | SPR_NOACCESS, SPR_NOACCESS, | |
2083 | &spr_read_generic, &spr_write_generic, | |
2084 | 0x00000000); | |
2085 | /* XXX : not implemented */ | |
2086 | spr_register(env, SPR_40x_IAC1, "IAC", | |
2087 | SPR_NOACCESS, SPR_NOACCESS, | |
2088 | &spr_read_generic, &spr_write_generic, | |
2089 | 0x00000000); | |
2090 | /* Storage control */ | |
035feb88 | 2091 | /* XXX: TODO: not implemented */ |
2662a059 JM |
2092 | spr_register(env, SPR_405_SLER, "SLER", |
2093 | SPR_NOACCESS, SPR_NOACCESS, | |
2094 | &spr_read_generic, &spr_write_40x_sler, | |
2095 | 0x00000000); | |
5cbdb3a3 | 2096 | /* not emulated, as QEMU never does speculative access */ |
035feb88 JM |
2097 | spr_register(env, SPR_40x_SGR, "SGR", |
2098 | SPR_NOACCESS, SPR_NOACCESS, | |
2099 | &spr_read_generic, &spr_write_generic, | |
2100 | 0xFFFFFFFF); | |
5cbdb3a3 | 2101 | /* not emulated, as QEMU do not emulate caches */ |
035feb88 JM |
2102 | spr_register(env, SPR_40x_DCWR, "DCWR", |
2103 | SPR_NOACCESS, SPR_NOACCESS, | |
2104 | &spr_read_generic, &spr_write_generic, | |
2105 | 0x00000000); | |
2662a059 JM |
2106 | } |
2107 | ||
a750fc0b JM |
2108 | static void gen_spr_401x2 (CPUPPCState *env) |
2109 | { | |
2110 | gen_spr_401(env); | |
2111 | spr_register(env, SPR_40x_PID, "PID", | |
2112 | SPR_NOACCESS, SPR_NOACCESS, | |
2113 | &spr_read_generic, &spr_write_generic, | |
2114 | 0x00000000); | |
2115 | spr_register(env, SPR_40x_ZPR, "ZPR", | |
2116 | SPR_NOACCESS, SPR_NOACCESS, | |
2117 | &spr_read_generic, &spr_write_generic, | |
2118 | 0x00000000); | |
2119 | } | |
2120 | ||
76a66253 JM |
2121 | /* SPR specific to PowerPC 403 implementation */ |
2122 | static void gen_spr_403 (CPUPPCState *env) | |
2123 | { | |
2662a059 JM |
2124 | /* Debug interface */ |
2125 | /* XXX : not implemented */ | |
2126 | spr_register(env, SPR_40x_DBCR0, "DBCR0", | |
2127 | SPR_NOACCESS, SPR_NOACCESS, | |
2128 | &spr_read_generic, &spr_write_40x_dbcr0, | |
2129 | 0x00000000); | |
2130 | /* XXX : not implemented */ | |
2131 | spr_register(env, SPR_40x_DBSR, "DBSR", | |
2132 | SPR_NOACCESS, SPR_NOACCESS, | |
2133 | &spr_read_generic, &spr_write_clear, | |
2134 | /* Last reset was system reset */ | |
2135 | 0x00000300); | |
2136 | /* XXX : not implemented */ | |
2137 | spr_register(env, SPR_40x_DAC1, "DAC1", | |
2138 | SPR_NOACCESS, SPR_NOACCESS, | |
2139 | &spr_read_generic, &spr_write_generic, | |
2140 | 0x00000000); | |
578bb252 | 2141 | /* XXX : not implemented */ |
2662a059 JM |
2142 | spr_register(env, SPR_40x_DAC2, "DAC2", |
2143 | SPR_NOACCESS, SPR_NOACCESS, | |
2144 | &spr_read_generic, &spr_write_generic, | |
2145 | 0x00000000); | |
2146 | /* XXX : not implemented */ | |
2147 | spr_register(env, SPR_40x_IAC1, "IAC1", | |
2148 | SPR_NOACCESS, SPR_NOACCESS, | |
2149 | &spr_read_generic, &spr_write_generic, | |
2150 | 0x00000000); | |
578bb252 | 2151 | /* XXX : not implemented */ |
2662a059 JM |
2152 | spr_register(env, SPR_40x_IAC2, "IAC2", |
2153 | SPR_NOACCESS, SPR_NOACCESS, | |
2154 | &spr_read_generic, &spr_write_generic, | |
2155 | 0x00000000); | |
a750fc0b JM |
2156 | } |
2157 | ||
2158 | static void gen_spr_403_real (CPUPPCState *env) | |
2159 | { | |
76a66253 JM |
2160 | spr_register(env, SPR_403_PBL1, "PBL1", |
2161 | SPR_NOACCESS, SPR_NOACCESS, | |
2162 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2163 | 0x00000000); | |
2164 | spr_register(env, SPR_403_PBU1, "PBU1", | |
2165 | SPR_NOACCESS, SPR_NOACCESS, | |
2166 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2167 | 0x00000000); | |
2168 | spr_register(env, SPR_403_PBL2, "PBL2", | |
2169 | SPR_NOACCESS, SPR_NOACCESS, | |
2170 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2171 | 0x00000000); | |
2172 | spr_register(env, SPR_403_PBU2, "PBU2", | |
2173 | SPR_NOACCESS, SPR_NOACCESS, | |
2174 | &spr_read_403_pbr, &spr_write_403_pbr, | |
2175 | 0x00000000); | |
a750fc0b JM |
2176 | } |
2177 | ||
2178 | static void gen_spr_403_mmu (CPUPPCState *env) | |
2179 | { | |
2180 | /* MMU */ | |
2181 | spr_register(env, SPR_40x_PID, "PID", | |
2182 | SPR_NOACCESS, SPR_NOACCESS, | |
2183 | &spr_read_generic, &spr_write_generic, | |
2184 | 0x00000000); | |
2662a059 | 2185 | spr_register(env, SPR_40x_ZPR, "ZPR", |
76a66253 JM |
2186 | SPR_NOACCESS, SPR_NOACCESS, |
2187 | &spr_read_generic, &spr_write_generic, | |
2188 | 0x00000000); | |
2189 | } | |
2190 | ||
2191 | /* SPR specific to PowerPC compression coprocessor extension */ | |
76a66253 JM |
2192 | static void gen_spr_compress (CPUPPCState *env) |
2193 | { | |
578bb252 | 2194 | /* XXX : not implemented */ |
76a66253 JM |
2195 | spr_register(env, SPR_401_SKR, "SKR", |
2196 | SPR_NOACCESS, SPR_NOACCESS, | |
2197 | &spr_read_generic, &spr_write_generic, | |
2198 | 0x00000000); | |
2199 | } | |
a750fc0b | 2200 | |
80d11f44 | 2201 | static void gen_spr_5xx_8xx (CPUPPCState *env) |
e1833e1f | 2202 | { |
80d11f44 | 2203 | /* Exception processing */ |
d67d40ea DG |
2204 | spr_register_kvm(env, SPR_DSISR, "DSISR", |
2205 | SPR_NOACCESS, SPR_NOACCESS, | |
2206 | &spr_read_generic, &spr_write_generic, | |
2207 | KVM_REG_PPC_DSISR, 0x00000000); | |
2208 | spr_register_kvm(env, SPR_DAR, "DAR", | |
2209 | SPR_NOACCESS, SPR_NOACCESS, | |
2210 | &spr_read_generic, &spr_write_generic, | |
2211 | KVM_REG_PPC_DAR, 0x00000000); | |
80d11f44 JM |
2212 | /* Timer */ |
2213 | spr_register(env, SPR_DECR, "DECR", | |
2214 | SPR_NOACCESS, SPR_NOACCESS, | |
2215 | &spr_read_decr, &spr_write_decr, | |
2216 | 0x00000000); | |
2217 | /* XXX : not implemented */ | |
2218 | spr_register(env, SPR_MPC_EIE, "EIE", | |
2219 | SPR_NOACCESS, SPR_NOACCESS, | |
2220 | &spr_read_generic, &spr_write_generic, | |
2221 | 0x00000000); | |
2222 | /* XXX : not implemented */ | |
2223 | spr_register(env, SPR_MPC_EID, "EID", | |
2224 | SPR_NOACCESS, SPR_NOACCESS, | |
2225 | &spr_read_generic, &spr_write_generic, | |
2226 | 0x00000000); | |
2227 | /* XXX : not implemented */ | |
2228 | spr_register(env, SPR_MPC_NRI, "NRI", | |
2229 | SPR_NOACCESS, SPR_NOACCESS, | |
2230 | &spr_read_generic, &spr_write_generic, | |
2231 | 0x00000000); | |
2232 | /* XXX : not implemented */ | |
2233 | spr_register(env, SPR_MPC_CMPA, "CMPA", | |
2234 | SPR_NOACCESS, SPR_NOACCESS, | |
2235 | &spr_read_generic, &spr_write_generic, | |
2236 | 0x00000000); | |
2237 | /* XXX : not implemented */ | |
2238 | spr_register(env, SPR_MPC_CMPB, "CMPB", | |
2239 | SPR_NOACCESS, SPR_NOACCESS, | |
2240 | &spr_read_generic, &spr_write_generic, | |
2241 | 0x00000000); | |
2242 | /* XXX : not implemented */ | |
2243 | spr_register(env, SPR_MPC_CMPC, "CMPC", | |
2244 | SPR_NOACCESS, SPR_NOACCESS, | |
2245 | &spr_read_generic, &spr_write_generic, | |
2246 | 0x00000000); | |
2247 | /* XXX : not implemented */ | |
2248 | spr_register(env, SPR_MPC_CMPD, "CMPD", | |
2249 | SPR_NOACCESS, SPR_NOACCESS, | |
2250 | &spr_read_generic, &spr_write_generic, | |
2251 | 0x00000000); | |
2252 | /* XXX : not implemented */ | |
2253 | spr_register(env, SPR_MPC_ECR, "ECR", | |
2254 | SPR_NOACCESS, SPR_NOACCESS, | |
2255 | &spr_read_generic, &spr_write_generic, | |
2256 | 0x00000000); | |
2257 | /* XXX : not implemented */ | |
2258 | spr_register(env, SPR_MPC_DER, "DER", | |
2259 | SPR_NOACCESS, SPR_NOACCESS, | |
2260 | &spr_read_generic, &spr_write_generic, | |
2261 | 0x00000000); | |
2262 | /* XXX : not implemented */ | |
2263 | spr_register(env, SPR_MPC_COUNTA, "COUNTA", | |
2264 | SPR_NOACCESS, SPR_NOACCESS, | |
2265 | &spr_read_generic, &spr_write_generic, | |
2266 | 0x00000000); | |
2267 | /* XXX : not implemented */ | |
2268 | spr_register(env, SPR_MPC_COUNTB, "COUNTB", | |
2269 | SPR_NOACCESS, SPR_NOACCESS, | |
2270 | &spr_read_generic, &spr_write_generic, | |
2271 | 0x00000000); | |
2272 | /* XXX : not implemented */ | |
2273 | spr_register(env, SPR_MPC_CMPE, "CMPE", | |
2274 | SPR_NOACCESS, SPR_NOACCESS, | |
2275 | &spr_read_generic, &spr_write_generic, | |
2276 | 0x00000000); | |
2277 | /* XXX : not implemented */ | |
2278 | spr_register(env, SPR_MPC_CMPF, "CMPF", | |
2279 | SPR_NOACCESS, SPR_NOACCESS, | |
2280 | &spr_read_generic, &spr_write_generic, | |
2281 | 0x00000000); | |
2282 | /* XXX : not implemented */ | |
2283 | spr_register(env, SPR_MPC_CMPG, "CMPG", | |
2284 | SPR_NOACCESS, SPR_NOACCESS, | |
2285 | &spr_read_generic, &spr_write_generic, | |
2286 | 0x00000000); | |
2287 | /* XXX : not implemented */ | |
2288 | spr_register(env, SPR_MPC_CMPH, "CMPH", | |
2289 | SPR_NOACCESS, SPR_NOACCESS, | |
2290 | &spr_read_generic, &spr_write_generic, | |
2291 | 0x00000000); | |
2292 | /* XXX : not implemented */ | |
2293 | spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", | |
2294 | SPR_NOACCESS, SPR_NOACCESS, | |
2295 | &spr_read_generic, &spr_write_generic, | |
2296 | 0x00000000); | |
2297 | /* XXX : not implemented */ | |
2298 | spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", | |
2299 | SPR_NOACCESS, SPR_NOACCESS, | |
2300 | &spr_read_generic, &spr_write_generic, | |
2301 | 0x00000000); | |
2302 | /* XXX : not implemented */ | |
2303 | spr_register(env, SPR_MPC_BAR, "BAR", | |
2304 | SPR_NOACCESS, SPR_NOACCESS, | |
2305 | &spr_read_generic, &spr_write_generic, | |
2306 | 0x00000000); | |
2307 | /* XXX : not implemented */ | |
2308 | spr_register(env, SPR_MPC_DPDR, "DPDR", | |
2309 | SPR_NOACCESS, SPR_NOACCESS, | |
2310 | &spr_read_generic, &spr_write_generic, | |
2311 | 0x00000000); | |
2312 | /* XXX : not implemented */ | |
2313 | spr_register(env, SPR_MPC_IMMR, "IMMR", | |
2314 | SPR_NOACCESS, SPR_NOACCESS, | |
2315 | &spr_read_generic, &spr_write_generic, | |
2316 | 0x00000000); | |
2317 | } | |
2318 | ||
2319 | static void gen_spr_5xx (CPUPPCState *env) | |
2320 | { | |
2321 | /* XXX : not implemented */ | |
2322 | spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", | |
2323 | SPR_NOACCESS, SPR_NOACCESS, | |
2324 | &spr_read_generic, &spr_write_generic, | |
2325 | 0x00000000); | |
2326 | /* XXX : not implemented */ | |
2327 | spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", | |
2328 | SPR_NOACCESS, SPR_NOACCESS, | |
2329 | &spr_read_generic, &spr_write_generic, | |
2330 | 0x00000000); | |
2331 | /* XXX : not implemented */ | |
2332 | spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", | |
2333 | SPR_NOACCESS, SPR_NOACCESS, | |
2334 | &spr_read_generic, &spr_write_generic, | |
2335 | 0x00000000); | |
2336 | /* XXX : not implemented */ | |
2337 | spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", | |
2338 | SPR_NOACCESS, SPR_NOACCESS, | |
2339 | &spr_read_generic, &spr_write_generic, | |
2340 | 0x00000000); | |
2341 | /* XXX : not implemented */ | |
2342 | spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", | |
2343 | SPR_NOACCESS, SPR_NOACCESS, | |
2344 | &spr_read_generic, &spr_write_generic, | |
2345 | 0x00000000); | |
2346 | /* XXX : not implemented */ | |
2347 | spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", | |
2348 | SPR_NOACCESS, SPR_NOACCESS, | |
2349 | &spr_read_generic, &spr_write_generic, | |
2350 | 0x00000000); | |
2351 | /* XXX : not implemented */ | |
2352 | spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", | |
2353 | SPR_NOACCESS, SPR_NOACCESS, | |
2354 | &spr_read_generic, &spr_write_generic, | |
2355 | 0x00000000); | |
2356 | /* XXX : not implemented */ | |
2357 | spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", | |
2358 | SPR_NOACCESS, SPR_NOACCESS, | |
2359 | &spr_read_generic, &spr_write_generic, | |
2360 | 0x00000000); | |
2361 | /* XXX : not implemented */ | |
2362 | spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", | |
2363 | SPR_NOACCESS, SPR_NOACCESS, | |
2364 | &spr_read_generic, &spr_write_generic, | |
2365 | 0x00000000); | |
2366 | /* XXX : not implemented */ | |
2367 | spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", | |
2368 | SPR_NOACCESS, SPR_NOACCESS, | |
2369 | &spr_read_generic, &spr_write_generic, | |
2370 | 0x00000000); | |
2371 | /* XXX : not implemented */ | |
2372 | spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", | |
2373 | SPR_NOACCESS, SPR_NOACCESS, | |
2374 | &spr_read_generic, &spr_write_generic, | |
2375 | 0x00000000); | |
2376 | /* XXX : not implemented */ | |
2377 | spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", | |
2378 | SPR_NOACCESS, SPR_NOACCESS, | |
2379 | &spr_read_generic, &spr_write_generic, | |
2380 | 0x00000000); | |
2381 | /* XXX : not implemented */ | |
2382 | spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", | |
2383 | SPR_NOACCESS, SPR_NOACCESS, | |
2384 | &spr_read_generic, &spr_write_generic, | |
2385 | 0x00000000); | |
2386 | /* XXX : not implemented */ | |
2387 | spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", | |
2388 | SPR_NOACCESS, SPR_NOACCESS, | |
2389 | &spr_read_generic, &spr_write_generic, | |
2390 | 0x00000000); | |
2391 | /* XXX : not implemented */ | |
2392 | spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", | |
2393 | SPR_NOACCESS, SPR_NOACCESS, | |
2394 | &spr_read_generic, &spr_write_generic, | |
2395 | 0x00000000); | |
2396 | /* XXX : not implemented */ | |
2397 | spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", | |
2398 | SPR_NOACCESS, SPR_NOACCESS, | |
2399 | &spr_read_generic, &spr_write_generic, | |
2400 | 0x00000000); | |
2401 | /* XXX : not implemented */ | |
2402 | spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", | |
2403 | SPR_NOACCESS, SPR_NOACCESS, | |
2404 | &spr_read_generic, &spr_write_generic, | |
2405 | 0x00000000); | |
2406 | /* XXX : not implemented */ | |
2407 | spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", | |
2408 | SPR_NOACCESS, SPR_NOACCESS, | |
2409 | &spr_read_generic, &spr_write_generic, | |
2410 | 0x00000000); | |
2411 | /* XXX : not implemented */ | |
2412 | spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", | |
2413 | SPR_NOACCESS, SPR_NOACCESS, | |
2414 | &spr_read_generic, &spr_write_generic, | |
2415 | 0x00000000); | |
2416 | /* XXX : not implemented */ | |
2417 | spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", | |
2418 | SPR_NOACCESS, SPR_NOACCESS, | |
2419 | &spr_read_generic, &spr_write_generic, | |
2420 | 0x00000000); | |
2421 | /* XXX : not implemented */ | |
2422 | spr_register(env, SPR_RCPU_FPECR, "FPECR", | |
2423 | SPR_NOACCESS, SPR_NOACCESS, | |
2424 | &spr_read_generic, &spr_write_generic, | |
2425 | 0x00000000); | |
2426 | } | |
2427 | ||
2428 | static void gen_spr_8xx (CPUPPCState *env) | |
2429 | { | |
2430 | /* XXX : not implemented */ | |
2431 | spr_register(env, SPR_MPC_IC_CST, "IC_CST", | |
2432 | SPR_NOACCESS, SPR_NOACCESS, | |
2433 | &spr_read_generic, &spr_write_generic, | |
2434 | 0x00000000); | |
2435 | /* XXX : not implemented */ | |
2436 | spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", | |
2437 | SPR_NOACCESS, SPR_NOACCESS, | |
2438 | &spr_read_generic, &spr_write_generic, | |
2439 | 0x00000000); | |
2440 | /* XXX : not implemented */ | |
2441 | spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", | |
2442 | SPR_NOACCESS, SPR_NOACCESS, | |
2443 | &spr_read_generic, &spr_write_generic, | |
2444 | 0x00000000); | |
2445 | /* XXX : not implemented */ | |
2446 | spr_register(env, SPR_MPC_DC_CST, "DC_CST", | |
2447 | SPR_NOACCESS, SPR_NOACCESS, | |
2448 | &spr_read_generic, &spr_write_generic, | |
2449 | 0x00000000); | |
2450 | /* XXX : not implemented */ | |
2451 | spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", | |
2452 | SPR_NOACCESS, SPR_NOACCESS, | |
2453 | &spr_read_generic, &spr_write_generic, | |
2454 | 0x00000000); | |
2455 | /* XXX : not implemented */ | |
2456 | spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", | |
2457 | SPR_NOACCESS, SPR_NOACCESS, | |
2458 | &spr_read_generic, &spr_write_generic, | |
2459 | 0x00000000); | |
2460 | /* XXX : not implemented */ | |
2461 | spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", | |
2462 | SPR_NOACCESS, SPR_NOACCESS, | |
2463 | &spr_read_generic, &spr_write_generic, | |
2464 | 0x00000000); | |
2465 | /* XXX : not implemented */ | |
2466 | spr_register(env, SPR_MPC_MI_AP, "MI_AP", | |
2467 | SPR_NOACCESS, SPR_NOACCESS, | |
2468 | &spr_read_generic, &spr_write_generic, | |
2469 | 0x00000000); | |
2470 | /* XXX : not implemented */ | |
2471 | spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", | |
2472 | SPR_NOACCESS, SPR_NOACCESS, | |
2473 | &spr_read_generic, &spr_write_generic, | |
2474 | 0x00000000); | |
2475 | /* XXX : not implemented */ | |
2476 | spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", | |
2477 | SPR_NOACCESS, SPR_NOACCESS, | |
2478 | &spr_read_generic, &spr_write_generic, | |
2479 | 0x00000000); | |
2480 | /* XXX : not implemented */ | |
2481 | spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", | |
2482 | SPR_NOACCESS, SPR_NOACCESS, | |
2483 | &spr_read_generic, &spr_write_generic, | |
2484 | 0x00000000); | |
2485 | /* XXX : not implemented */ | |
2486 | spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", | |
2487 | SPR_NOACCESS, SPR_NOACCESS, | |
2488 | &spr_read_generic, &spr_write_generic, | |
2489 | 0x00000000); | |
2490 | /* XXX : not implemented */ | |
2491 | spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", | |
2492 | SPR_NOACCESS, SPR_NOACCESS, | |
2493 | &spr_read_generic, &spr_write_generic, | |
2494 | 0x00000000); | |
2495 | /* XXX : not implemented */ | |
2496 | spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", | |
2497 | SPR_NOACCESS, SPR_NOACCESS, | |
2498 | &spr_read_generic, &spr_write_generic, | |
2499 | 0x00000000); | |
2500 | /* XXX : not implemented */ | |
2501 | spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", | |
2502 | SPR_NOACCESS, SPR_NOACCESS, | |
2503 | &spr_read_generic, &spr_write_generic, | |
2504 | 0x00000000); | |
2505 | /* XXX : not implemented */ | |
2506 | spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", | |
2507 | SPR_NOACCESS, SPR_NOACCESS, | |
2508 | &spr_read_generic, &spr_write_generic, | |
2509 | 0x00000000); | |
2510 | /* XXX : not implemented */ | |
2511 | spr_register(env, SPR_MPC_MD_AP, "MD_AP", | |
2512 | SPR_NOACCESS, SPR_NOACCESS, | |
2513 | &spr_read_generic, &spr_write_generic, | |
2514 | 0x00000000); | |
2515 | /* XXX : not implemented */ | |
2516 | spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", | |
2517 | SPR_NOACCESS, SPR_NOACCESS, | |
2518 | &spr_read_generic, &spr_write_generic, | |
2519 | 0x00000000); | |
2520 | /* XXX : not implemented */ | |
2521 | spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", | |
2522 | SPR_NOACCESS, SPR_NOACCESS, | |
2523 | &spr_read_generic, &spr_write_generic, | |
2524 | 0x00000000); | |
2525 | /* XXX : not implemented */ | |
2526 | spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", | |
2527 | SPR_NOACCESS, SPR_NOACCESS, | |
2528 | &spr_read_generic, &spr_write_generic, | |
2529 | 0x00000000); | |
2530 | /* XXX : not implemented */ | |
2531 | spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", | |
2532 | SPR_NOACCESS, SPR_NOACCESS, | |
2533 | &spr_read_generic, &spr_write_generic, | |
2534 | 0x00000000); | |
2535 | /* XXX : not implemented */ | |
2536 | spr_register(env, SPR_MPC_MD_TW, "MD_TW", | |
2537 | SPR_NOACCESS, SPR_NOACCESS, | |
2538 | &spr_read_generic, &spr_write_generic, | |
2539 | 0x00000000); | |
2540 | /* XXX : not implemented */ | |
2541 | spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", | |
2542 | SPR_NOACCESS, SPR_NOACCESS, | |
2543 | &spr_read_generic, &spr_write_generic, | |
2544 | 0x00000000); | |
2545 | /* XXX : not implemented */ | |
2546 | spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", | |
2547 | SPR_NOACCESS, SPR_NOACCESS, | |
2548 | &spr_read_generic, &spr_write_generic, | |
2549 | 0x00000000); | |
2550 | /* XXX : not implemented */ | |
2551 | spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", | |
2552 | SPR_NOACCESS, SPR_NOACCESS, | |
2553 | &spr_read_generic, &spr_write_generic, | |
2554 | 0x00000000); | |
2555 | } | |
2556 | ||
2557 | // XXX: TODO | |
2558 | /* | |
2559 | * AMR => SPR 29 (Power 2.04) | |
2560 | * CTRL => SPR 136 (Power 2.04) | |
2561 | * CTRL => SPR 152 (Power 2.04) | |
2562 | * SCOMC => SPR 276 (64 bits ?) | |
2563 | * SCOMD => SPR 277 (64 bits ?) | |
2564 | * TBU40 => SPR 286 (Power 2.04 hypv) | |
2565 | * HSPRG0 => SPR 304 (Power 2.04 hypv) | |
2566 | * HSPRG1 => SPR 305 (Power 2.04 hypv) | |
2567 | * HDSISR => SPR 306 (Power 2.04 hypv) | |
2568 | * HDAR => SPR 307 (Power 2.04 hypv) | |
2569 | * PURR => SPR 309 (Power 2.04 hypv) | |
2570 | * HDEC => SPR 310 (Power 2.04 hypv) | |
2571 | * HIOR => SPR 311 (hypv) | |
2572 | * RMOR => SPR 312 (970) | |
2573 | * HRMOR => SPR 313 (Power 2.04 hypv) | |
2574 | * HSRR0 => SPR 314 (Power 2.04 hypv) | |
2575 | * HSRR1 => SPR 315 (Power 2.04 hypv) | |
2576 | * LPCR => SPR 316 (970) | |
2577 | * LPIDR => SPR 317 (970) | |
80d11f44 JM |
2578 | * EPR => SPR 702 (Power 2.04 emb) |
2579 | * perf => 768-783 (Power 2.04) | |
2580 | * perf => 784-799 (Power 2.04) | |
2581 | * PPR => SPR 896 (Power 2.04) | |
2582 | * EPLC => SPR 947 (Power 2.04 emb) | |
2583 | * EPSC => SPR 948 (Power 2.04 emb) | |
2584 | * DABRX => 1015 (Power 2.04 hypv) | |
2585 | * FPECR => SPR 1022 (?) | |
2586 | * ... and more (thermal management, performance counters, ...) | |
2587 | */ | |
2588 | ||
2589 | /*****************************************************************************/ | |
2590 | /* Exception vectors models */ | |
2591 | static void init_excp_4xx_real (CPUPPCState *env) | |
2592 | { | |
2593 | #if !defined(CONFIG_USER_ONLY) | |
2594 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; | |
2595 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2596 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2597 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2598 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2599 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2600 | env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; | |
2601 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; | |
2602 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; | |
2603 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; | |
80d11f44 | 2604 | env->ivor_mask = 0x0000FFF0UL; |
faadf50e | 2605 | env->ivpr_mask = 0xFFFF0000UL; |
1c27f8fb JM |
2606 | /* Hardware reset vector */ |
2607 | env->hreset_vector = 0xFFFFFFFCUL; | |
e1833e1f JM |
2608 | #endif |
2609 | } | |
2610 | ||
80d11f44 JM |
2611 | static void init_excp_4xx_softmmu (CPUPPCState *env) |
2612 | { | |
2613 | #if !defined(CONFIG_USER_ONLY) | |
2614 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; | |
2615 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2616 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2617 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2618 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2619 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2620 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2621 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2622 | env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; | |
2623 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; | |
2624 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; | |
2625 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; | |
2626 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; | |
2627 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; | |
80d11f44 JM |
2628 | env->ivor_mask = 0x0000FFF0UL; |
2629 | env->ivpr_mask = 0xFFFF0000UL; | |
2630 | /* Hardware reset vector */ | |
2631 | env->hreset_vector = 0xFFFFFFFCUL; | |
2632 | #endif | |
2633 | } | |
2634 | ||
2635 | static void init_excp_MPC5xx (CPUPPCState *env) | |
2636 | { | |
2637 | #if !defined(CONFIG_USER_ONLY) | |
2638 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2639 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2640 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2641 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2642 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2643 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; | |
2644 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2645 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2646 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2647 | env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; | |
2648 | env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; | |
2649 | env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; | |
2650 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; | |
2651 | env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; | |
2652 | env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; | |
80d11f44 JM |
2653 | env->ivor_mask = 0x0000FFF0UL; |
2654 | env->ivpr_mask = 0xFFFF0000UL; | |
2655 | /* Hardware reset vector */ | |
09d9828a | 2656 | env->hreset_vector = 0x00000100UL; |
80d11f44 JM |
2657 | #endif |
2658 | } | |
2659 | ||
2660 | static void init_excp_MPC8xx (CPUPPCState *env) | |
e1833e1f JM |
2661 | { |
2662 | #if !defined(CONFIG_USER_ONLY) | |
2663 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2664 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2665 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2666 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2667 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2668 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2669 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
80d11f44 | 2670 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; |
e1833e1f | 2671 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
e1833e1f | 2672 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
80d11f44 JM |
2673 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
2674 | env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; | |
2675 | env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; | |
2676 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; | |
2677 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; | |
2678 | env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; | |
2679 | env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; | |
2680 | env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; | |
2681 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; | |
2682 | env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; | |
2683 | env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; | |
80d11f44 JM |
2684 | env->ivor_mask = 0x0000FFF0UL; |
2685 | env->ivpr_mask = 0xFFFF0000UL; | |
1c27f8fb | 2686 | /* Hardware reset vector */ |
09d9828a | 2687 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2688 | #endif |
2689 | } | |
2690 | ||
80d11f44 | 2691 | static void init_excp_G2 (CPUPPCState *env) |
e1833e1f JM |
2692 | { |
2693 | #if !defined(CONFIG_USER_ONLY) | |
2694 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2695 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2696 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2697 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2698 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2699 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2700 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2701 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2702 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
80d11f44 | 2703 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; |
e1833e1f JM |
2704 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
2705 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
e1833e1f JM |
2706 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
2707 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2708 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
2709 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2710 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
80d11f44 | 2711 | /* Hardware reset vector */ |
09d9828a | 2712 | env->hreset_vector = 0x00000100UL; |
80d11f44 JM |
2713 | #endif |
2714 | } | |
2715 | ||
e9cd84b9 | 2716 | static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) |
80d11f44 JM |
2717 | { |
2718 | #if !defined(CONFIG_USER_ONLY) | |
2719 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; | |
2720 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; | |
2721 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; | |
2722 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; | |
2723 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; | |
2724 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; | |
2725 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; | |
2726 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; | |
2727 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; | |
2728 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; | |
2729 | env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; | |
2730 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; | |
2731 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; | |
2732 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; | |
2733 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; | |
2734 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; | |
2735 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; | |
2736 | env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; | |
2737 | env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; | |
2738 | env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; | |
80d11f44 | 2739 | env->ivor_mask = 0x0000FFF7UL; |
e9cd84b9 | 2740 | env->ivpr_mask = ivpr_mask; |
80d11f44 JM |
2741 | /* Hardware reset vector */ |
2742 | env->hreset_vector = 0xFFFFFFFCUL; | |
2743 | #endif | |
2744 | } | |
2745 | ||
2746 | static void init_excp_BookE (CPUPPCState *env) | |
2747 | { | |
2748 | #if !defined(CONFIG_USER_ONLY) | |
2749 | env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; | |
2750 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; | |
2751 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; | |
2752 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; | |
2753 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; | |
2754 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; | |
2755 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; | |
2756 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; | |
2757 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; | |
2758 | env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; | |
2759 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; | |
2760 | env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; | |
2761 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; | |
2762 | env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; | |
2763 | env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; | |
2764 | env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; | |
80d11f44 JM |
2765 | env->ivor_mask = 0x0000FFE0UL; |
2766 | env->ivpr_mask = 0xFFFF0000UL; | |
2767 | /* Hardware reset vector */ | |
2768 | env->hreset_vector = 0xFFFFFFFCUL; | |
2769 | #endif | |
2770 | } | |
2771 | ||
2772 | static void init_excp_601 (CPUPPCState *env) | |
2773 | { | |
2774 | #if !defined(CONFIG_USER_ONLY) | |
2775 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2776 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2777 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2778 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2779 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2780 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2781 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2782 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2783 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2784 | env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; | |
2785 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2786 | env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; | |
1c27f8fb | 2787 | /* Hardware reset vector */ |
80d11f44 | 2788 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2789 | #endif |
2790 | } | |
2791 | ||
80d11f44 | 2792 | static void init_excp_602 (CPUPPCState *env) |
e1833e1f JM |
2793 | { |
2794 | #if !defined(CONFIG_USER_ONLY) | |
082c6681 | 2795 | /* XXX: exception prefix has a special behavior on 602 */ |
e1833e1f JM |
2796 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
2797 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2798 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2799 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2800 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2801 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2802 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2803 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2804 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2805 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2806 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2807 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; | |
2808 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2809 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
2810 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2811 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
80d11f44 JM |
2812 | env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; |
2813 | env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; | |
1c27f8fb | 2814 | /* Hardware reset vector */ |
09d9828a | 2815 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2816 | #endif |
2817 | } | |
2818 | ||
80d11f44 | 2819 | static void init_excp_603 (CPUPPCState *env) |
e1833e1f JM |
2820 | { |
2821 | #if !defined(CONFIG_USER_ONLY) | |
2822 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2823 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2824 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2825 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2826 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2827 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2828 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2829 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2830 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
e1833e1f JM |
2831 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
2832 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2833 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; | |
2834 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2835 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
2836 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2837 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
1c27f8fb | 2838 | /* Hardware reset vector */ |
09d9828a | 2839 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2840 | #endif |
2841 | } | |
2842 | ||
2843 | static void init_excp_604 (CPUPPCState *env) | |
2844 | { | |
2845 | #if !defined(CONFIG_USER_ONLY) | |
2846 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2847 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2848 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2849 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2850 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2851 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2852 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2853 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2854 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2855 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2856 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2857 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2858 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2859 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
1c27f8fb | 2860 | /* Hardware reset vector */ |
2d3eb7bf | 2861 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2862 | #endif |
2863 | } | |
2864 | ||
e1833e1f JM |
2865 | static void init_excp_7x0 (CPUPPCState *env) |
2866 | { | |
2867 | #if !defined(CONFIG_USER_ONLY) | |
2868 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2869 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2870 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2871 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2872 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2873 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2874 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2875 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2876 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2877 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2878 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2879 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2880 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
bd928eba | 2881 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
e1833e1f | 2882 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
1c27f8fb | 2883 | /* Hardware reset vector */ |
09d9828a | 2884 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2885 | #endif |
2886 | } | |
2887 | ||
bd928eba | 2888 | static void init_excp_750cl (CPUPPCState *env) |
e1833e1f JM |
2889 | { |
2890 | #if !defined(CONFIG_USER_ONLY) | |
2891 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2892 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2893 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2894 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2895 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2896 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2897 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2898 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2899 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2900 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2901 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2902 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2903 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2904 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
bd928eba | 2905 | /* Hardware reset vector */ |
09d9828a | 2906 | env->hreset_vector = 0x00000100UL; |
bd928eba JM |
2907 | #endif |
2908 | } | |
2909 | ||
2910 | static void init_excp_750cx (CPUPPCState *env) | |
2911 | { | |
2912 | #if !defined(CONFIG_USER_ONLY) | |
2913 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2914 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2915 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2916 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2917 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2918 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2919 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2920 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2921 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2922 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2923 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2924 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2925 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
e1833e1f | 2926 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
1c27f8fb | 2927 | /* Hardware reset vector */ |
09d9828a | 2928 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2929 | #endif |
2930 | } | |
2931 | ||
7a3a6927 JM |
2932 | /* XXX: Check if this is correct */ |
2933 | static void init_excp_7x5 (CPUPPCState *env) | |
2934 | { | |
2935 | #if !defined(CONFIG_USER_ONLY) | |
2936 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2937 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2938 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2939 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2940 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2941 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2942 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2943 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2944 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2945 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2946 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
bd928eba | 2947 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
7a3a6927 JM |
2948 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
2949 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
2950 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
7a3a6927 JM |
2951 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
2952 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
bd928eba | 2953 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; |
7a3a6927 | 2954 | /* Hardware reset vector */ |
09d9828a | 2955 | env->hreset_vector = 0x00000100UL; |
7a3a6927 JM |
2956 | #endif |
2957 | } | |
2958 | ||
e1833e1f JM |
2959 | static void init_excp_7400 (CPUPPCState *env) |
2960 | { | |
2961 | #if !defined(CONFIG_USER_ONLY) | |
2962 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2963 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2964 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2965 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2966 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2967 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2968 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2969 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2970 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2971 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2972 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2973 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2974 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
2975 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
2976 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
2977 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; | |
2978 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; | |
1c27f8fb | 2979 | /* Hardware reset vector */ |
09d9828a | 2980 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
2981 | #endif |
2982 | } | |
2983 | ||
e1833e1f JM |
2984 | static void init_excp_7450 (CPUPPCState *env) |
2985 | { | |
2986 | #if !defined(CONFIG_USER_ONLY) | |
2987 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
2988 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
2989 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
2990 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
2991 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
2992 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
2993 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
2994 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
2995 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
2996 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
2997 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
2998 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
2999 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
3000 | env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; | |
3001 | env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; | |
3002 | env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; | |
3003 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3004 | env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; | |
3005 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; | |
1c27f8fb | 3006 | /* Hardware reset vector */ |
09d9828a | 3007 | env->hreset_vector = 0x00000100UL; |
e1833e1f JM |
3008 | #endif |
3009 | } | |
e1833e1f JM |
3010 | |
3011 | #if defined (TARGET_PPC64) | |
3012 | static void init_excp_970 (CPUPPCState *env) | |
3013 | { | |
3014 | #if !defined(CONFIG_USER_ONLY) | |
3015 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3016 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3017 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3018 | env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; | |
3019 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3020 | env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; | |
3021 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3022 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3023 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3024 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3025 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
e1833e1f | 3026 | env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; |
e1833e1f JM |
3027 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
3028 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3029 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3030 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
3031 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3032 | env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; | |
3033 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; | |
3034 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; | |
1c27f8fb JM |
3035 | /* Hardware reset vector */ |
3036 | env->hreset_vector = 0x0000000000000100ULL; | |
e1833e1f JM |
3037 | #endif |
3038 | } | |
9d52e907 DG |
3039 | |
3040 | static void init_excp_POWER7 (CPUPPCState *env) | |
3041 | { | |
3042 | #if !defined(CONFIG_USER_ONLY) | |
3043 | env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; | |
3044 | env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; | |
3045 | env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; | |
3046 | env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; | |
3047 | env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; | |
3048 | env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; | |
3049 | env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; | |
3050 | env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; | |
3051 | env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; | |
3052 | env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; | |
3053 | env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; | |
3054 | env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; | |
3055 | env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; | |
3056 | env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; | |
3057 | env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; | |
3058 | env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; | |
3059 | env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; | |
3060 | env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; | |
3061 | env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; | |
3062 | env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; | |
9d52e907 DG |
3063 | /* Hardware reset vector */ |
3064 | env->hreset_vector = 0x0000000000000100ULL; | |
3065 | #endif | |
3066 | } | |
e1833e1f JM |
3067 | #endif |
3068 | ||
2f462816 JM |
3069 | /*****************************************************************************/ |
3070 | /* Power management enable checks */ | |
3071 | static int check_pow_none (CPUPPCState *env) | |
3072 | { | |
3073 | return 0; | |
3074 | } | |
3075 | ||
3076 | static int check_pow_nocheck (CPUPPCState *env) | |
3077 | { | |
3078 | return 1; | |
3079 | } | |
3080 | ||
3081 | static int check_pow_hid0 (CPUPPCState *env) | |
3082 | { | |
3083 | if (env->spr[SPR_HID0] & 0x00E00000) | |
3084 | return 1; | |
3085 | ||
3086 | return 0; | |
3087 | } | |
3088 | ||
4e777442 JM |
3089 | static int check_pow_hid0_74xx (CPUPPCState *env) |
3090 | { | |
3091 | if (env->spr[SPR_HID0] & 0x00600000) | |
3092 | return 1; | |
3093 | ||
3094 | return 0; | |
3095 | } | |
3096 | ||
a750fc0b JM |
3097 | /*****************************************************************************/ |
3098 | /* PowerPC implementations definitions */ | |
76a66253 | 3099 | |
7856e3a4 AF |
3100 | #define POWERPC_FAMILY(_name) \ |
3101 | static void \ | |
3102 | glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ | |
3103 | \ | |
3104 | static const TypeInfo \ | |
3105 | glue(glue(ppc_, _name), _cpu_family_type_info) = { \ | |
3106 | .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ | |
3107 | .parent = TYPE_POWERPC_CPU, \ | |
3108 | .abstract = true, \ | |
3109 | .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ | |
3110 | }; \ | |
3111 | \ | |
3112 | static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ | |
3113 | { \ | |
3114 | type_register_static( \ | |
3115 | &glue(glue(ppc_, _name), _cpu_family_type_info)); \ | |
3116 | } \ | |
3117 | \ | |
3118 | type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ | |
3119 | \ | |
3120 | static void glue(glue(ppc_, _name), _cpu_family_class_init) | |
3121 | ||
a750fc0b JM |
3122 | static void init_proc_401 (CPUPPCState *env) |
3123 | { | |
3124 | gen_spr_40x(env); | |
3125 | gen_spr_401_403(env); | |
3126 | gen_spr_401(env); | |
e1833e1f | 3127 | init_excp_4xx_real(env); |
d63001d1 JM |
3128 | env->dcache_line_size = 32; |
3129 | env->icache_line_size = 32; | |
4e290a0b JM |
3130 | /* Allocate hardware IRQ controller */ |
3131 | ppc40x_irq_init(env); | |
ddd1055b FC |
3132 | |
3133 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3134 | SET_WDT_PERIOD(16, 20, 24, 28); | |
a750fc0b | 3135 | } |
76a66253 | 3136 | |
7856e3a4 AF |
3137 | POWERPC_FAMILY(401)(ObjectClass *oc, void *data) |
3138 | { | |
ca5dff0a | 3139 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3140 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3141 | ||
ca5dff0a | 3142 | dc->desc = "PowerPC 401"; |
7856e3a4 AF |
3143 | pcc->init_proc = init_proc_401; |
3144 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3145 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3146 | PPC_WRTEE | PPC_DCR | | |
3147 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3148 | PPC_CACHE_DCBZ | | |
3149 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3150 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
ba9fd9f1 AF |
3151 | pcc->msr_mask = 0x00000000000FD201ULL; |
3152 | pcc->mmu_model = POWERPC_MMU_REAL; | |
3153 | pcc->excp_model = POWERPC_EXCP_40x; | |
3154 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3155 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3156 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
3157 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3158 | } |
3159 | ||
a750fc0b JM |
3160 | static void init_proc_401x2 (CPUPPCState *env) |
3161 | { | |
3162 | gen_spr_40x(env); | |
3163 | gen_spr_401_403(env); | |
3164 | gen_spr_401x2(env); | |
3165 | gen_spr_compress(env); | |
a750fc0b | 3166 | /* Memory management */ |
f2e63a42 | 3167 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3168 | env->nb_tlb = 64; |
3169 | env->nb_ways = 1; | |
3170 | env->id_tlbs = 0; | |
1c53accc | 3171 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3172 | #endif |
e1833e1f | 3173 | init_excp_4xx_softmmu(env); |
d63001d1 JM |
3174 | env->dcache_line_size = 32; |
3175 | env->icache_line_size = 32; | |
4e290a0b JM |
3176 | /* Allocate hardware IRQ controller */ |
3177 | ppc40x_irq_init(env); | |
ddd1055b FC |
3178 | |
3179 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3180 | SET_WDT_PERIOD(16, 20, 24, 28); | |
76a66253 JM |
3181 | } |
3182 | ||
7856e3a4 AF |
3183 | POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) |
3184 | { | |
ca5dff0a | 3185 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3186 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3187 | ||
ca5dff0a | 3188 | dc->desc = "PowerPC 401x2"; |
7856e3a4 AF |
3189 | pcc->init_proc = init_proc_401x2; |
3190 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3191 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
3192 | PPC_DCR | PPC_WRTEE | | |
3193 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3194 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3195 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3196 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3197 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
ba9fd9f1 AF |
3198 | pcc->msr_mask = 0x00000000001FD231ULL; |
3199 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; | |
3200 | pcc->excp_model = POWERPC_EXCP_40x; | |
3201 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3202 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3203 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
3204 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3205 | } |
3206 | ||
e1833e1f | 3207 | static void init_proc_401x3 (CPUPPCState *env) |
76a66253 | 3208 | { |
4e290a0b JM |
3209 | gen_spr_40x(env); |
3210 | gen_spr_401_403(env); | |
3211 | gen_spr_401(env); | |
3212 | gen_spr_401x2(env); | |
3213 | gen_spr_compress(env); | |
e1833e1f | 3214 | init_excp_4xx_softmmu(env); |
d63001d1 JM |
3215 | env->dcache_line_size = 32; |
3216 | env->icache_line_size = 32; | |
4e290a0b JM |
3217 | /* Allocate hardware IRQ controller */ |
3218 | ppc40x_irq_init(env); | |
ddd1055b FC |
3219 | |
3220 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3221 | SET_WDT_PERIOD(16, 20, 24, 28); | |
3fc6c082 | 3222 | } |
a750fc0b | 3223 | |
7856e3a4 AF |
3224 | POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) |
3225 | { | |
ca5dff0a | 3226 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3227 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3228 | ||
ca5dff0a | 3229 | dc->desc = "PowerPC 401x3"; |
7856e3a4 AF |
3230 | pcc->init_proc = init_proc_401x3; |
3231 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3232 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
3233 | PPC_DCR | PPC_WRTEE | | |
3234 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3235 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3236 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3237 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3238 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
ba9fd9f1 AF |
3239 | pcc->msr_mask = 0x00000000001FD631ULL; |
3240 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; | |
3241 | pcc->excp_model = POWERPC_EXCP_40x; | |
3242 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3243 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3244 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
3245 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3246 | } |
3247 | ||
a750fc0b | 3248 | static void init_proc_IOP480 (CPUPPCState *env) |
3fc6c082 | 3249 | { |
a750fc0b JM |
3250 | gen_spr_40x(env); |
3251 | gen_spr_401_403(env); | |
3252 | gen_spr_401x2(env); | |
3253 | gen_spr_compress(env); | |
a750fc0b | 3254 | /* Memory management */ |
f2e63a42 | 3255 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3256 | env->nb_tlb = 64; |
3257 | env->nb_ways = 1; | |
3258 | env->id_tlbs = 0; | |
1c53accc | 3259 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3260 | #endif |
e1833e1f | 3261 | init_excp_4xx_softmmu(env); |
d63001d1 JM |
3262 | env->dcache_line_size = 32; |
3263 | env->icache_line_size = 32; | |
4e290a0b JM |
3264 | /* Allocate hardware IRQ controller */ |
3265 | ppc40x_irq_init(env); | |
ddd1055b FC |
3266 | |
3267 | SET_FIT_PERIOD(8, 12, 16, 20); | |
3268 | SET_WDT_PERIOD(16, 20, 24, 28); | |
3fc6c082 FB |
3269 | } |
3270 | ||
7856e3a4 AF |
3271 | POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) |
3272 | { | |
ca5dff0a | 3273 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3274 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3275 | ||
ca5dff0a | 3276 | dc->desc = "IOP480"; |
7856e3a4 AF |
3277 | pcc->init_proc = init_proc_IOP480; |
3278 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3279 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3280 | PPC_DCR | PPC_WRTEE | | |
3281 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3282 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3283 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3284 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3285 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
ba9fd9f1 AF |
3286 | pcc->msr_mask = 0x00000000001FD231ULL; |
3287 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; | |
3288 | pcc->excp_model = POWERPC_EXCP_40x; | |
3289 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3290 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3291 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
3292 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3293 | } |
3294 | ||
a750fc0b | 3295 | static void init_proc_403 (CPUPPCState *env) |
3fc6c082 | 3296 | { |
a750fc0b JM |
3297 | gen_spr_40x(env); |
3298 | gen_spr_401_403(env); | |
3299 | gen_spr_403(env); | |
3300 | gen_spr_403_real(env); | |
e1833e1f | 3301 | init_excp_4xx_real(env); |
d63001d1 JM |
3302 | env->dcache_line_size = 32; |
3303 | env->icache_line_size = 32; | |
4e290a0b JM |
3304 | /* Allocate hardware IRQ controller */ |
3305 | ppc40x_irq_init(env); | |
ddd1055b FC |
3306 | |
3307 | SET_FIT_PERIOD(8, 12, 16, 20); | |
3308 | SET_WDT_PERIOD(16, 20, 24, 28); | |
3fc6c082 FB |
3309 | } |
3310 | ||
7856e3a4 AF |
3311 | POWERPC_FAMILY(403)(ObjectClass *oc, void *data) |
3312 | { | |
ca5dff0a | 3313 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3314 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3315 | ||
ca5dff0a | 3316 | dc->desc = "PowerPC 403"; |
7856e3a4 AF |
3317 | pcc->init_proc = init_proc_403; |
3318 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3319 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3320 | PPC_DCR | PPC_WRTEE | | |
3321 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3322 | PPC_CACHE_DCBZ | | |
3323 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3324 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
ba9fd9f1 AF |
3325 | pcc->msr_mask = 0x000000000007D00DULL; |
3326 | pcc->mmu_model = POWERPC_MMU_REAL; | |
3327 | pcc->excp_model = POWERPC_EXCP_40x; | |
3328 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3329 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3330 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | | |
3331 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3332 | } |
3333 | ||
a750fc0b | 3334 | static void init_proc_403GCX (CPUPPCState *env) |
3fc6c082 | 3335 | { |
a750fc0b JM |
3336 | gen_spr_40x(env); |
3337 | gen_spr_401_403(env); | |
3338 | gen_spr_403(env); | |
3339 | gen_spr_403_real(env); | |
3340 | gen_spr_403_mmu(env); | |
3341 | /* Bus access control */ | |
5cbdb3a3 | 3342 | /* not emulated, as QEMU never does speculative access */ |
a750fc0b JM |
3343 | spr_register(env, SPR_40x_SGR, "SGR", |
3344 | SPR_NOACCESS, SPR_NOACCESS, | |
3345 | &spr_read_generic, &spr_write_generic, | |
3346 | 0xFFFFFFFF); | |
5cbdb3a3 | 3347 | /* not emulated, as QEMU do not emulate caches */ |
a750fc0b JM |
3348 | spr_register(env, SPR_40x_DCWR, "DCWR", |
3349 | SPR_NOACCESS, SPR_NOACCESS, | |
3350 | &spr_read_generic, &spr_write_generic, | |
3351 | 0x00000000); | |
3352 | /* Memory management */ | |
f2e63a42 | 3353 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3354 | env->nb_tlb = 64; |
3355 | env->nb_ways = 1; | |
3356 | env->id_tlbs = 0; | |
1c53accc | 3357 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3358 | #endif |
80d11f44 JM |
3359 | init_excp_4xx_softmmu(env); |
3360 | env->dcache_line_size = 32; | |
3361 | env->icache_line_size = 32; | |
3362 | /* Allocate hardware IRQ controller */ | |
3363 | ppc40x_irq_init(env); | |
ddd1055b FC |
3364 | |
3365 | SET_FIT_PERIOD(8, 12, 16, 20); | |
3366 | SET_WDT_PERIOD(16, 20, 24, 28); | |
80d11f44 JM |
3367 | } |
3368 | ||
7856e3a4 AF |
3369 | POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) |
3370 | { | |
ca5dff0a | 3371 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3372 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3373 | ||
ca5dff0a | 3374 | dc->desc = "PowerPC 403 GCX"; |
7856e3a4 AF |
3375 | pcc->init_proc = init_proc_403GCX; |
3376 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3377 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3378 | PPC_DCR | PPC_WRTEE | | |
3379 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3380 | PPC_CACHE_DCBZ | | |
3381 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3382 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3383 | PPC_4xx_COMMON | PPC_40x_EXCP; | |
ba9fd9f1 AF |
3384 | pcc->msr_mask = 0x000000000007D00DULL; |
3385 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; | |
3386 | pcc->excp_model = POWERPC_EXCP_40x; | |
3387 | pcc->bus_model = PPC_FLAGS_INPUT_401; | |
3388 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3389 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | | |
3390 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3391 | } |
3392 | ||
80d11f44 JM |
3393 | static void init_proc_405 (CPUPPCState *env) |
3394 | { | |
3395 | /* Time base */ | |
3396 | gen_tbl(env); | |
3397 | gen_spr_40x(env); | |
3398 | gen_spr_405(env); | |
3399 | /* Bus access control */ | |
5cbdb3a3 | 3400 | /* not emulated, as QEMU never does speculative access */ |
80d11f44 JM |
3401 | spr_register(env, SPR_40x_SGR, "SGR", |
3402 | SPR_NOACCESS, SPR_NOACCESS, | |
3403 | &spr_read_generic, &spr_write_generic, | |
3404 | 0xFFFFFFFF); | |
5cbdb3a3 | 3405 | /* not emulated, as QEMU do not emulate caches */ |
80d11f44 JM |
3406 | spr_register(env, SPR_40x_DCWR, "DCWR", |
3407 | SPR_NOACCESS, SPR_NOACCESS, | |
3408 | &spr_read_generic, &spr_write_generic, | |
3409 | 0x00000000); | |
3410 | /* Memory management */ | |
3411 | #if !defined(CONFIG_USER_ONLY) | |
3412 | env->nb_tlb = 64; | |
3413 | env->nb_ways = 1; | |
3414 | env->id_tlbs = 0; | |
1c53accc | 3415 | env->tlb_type = TLB_EMB; |
80d11f44 JM |
3416 | #endif |
3417 | init_excp_4xx_softmmu(env); | |
3418 | env->dcache_line_size = 32; | |
3419 | env->icache_line_size = 32; | |
3420 | /* Allocate hardware IRQ controller */ | |
3421 | ppc40x_irq_init(env); | |
ddd1055b FC |
3422 | |
3423 | SET_FIT_PERIOD(8, 12, 16, 20); | |
3424 | SET_WDT_PERIOD(16, 20, 24, 28); | |
80d11f44 JM |
3425 | } |
3426 | ||
7856e3a4 AF |
3427 | POWERPC_FAMILY(405)(ObjectClass *oc, void *data) |
3428 | { | |
ca5dff0a | 3429 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3430 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3431 | ||
ca5dff0a | 3432 | dc->desc = "PowerPC 405"; |
7856e3a4 AF |
3433 | pcc->init_proc = init_proc_405; |
3434 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3435 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
3436 | PPC_DCR | PPC_WRTEE | | |
3437 | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | | |
3438 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3439 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
3440 | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | | |
3441 | PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; | |
ba9fd9f1 AF |
3442 | pcc->msr_mask = 0x000000000006E630ULL; |
3443 | pcc->mmu_model = POWERPC_MMU_SOFT_4xx; | |
3444 | pcc->excp_model = POWERPC_EXCP_40x; | |
3445 | pcc->bus_model = PPC_FLAGS_INPUT_405; | |
3446 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3447 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3448 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3449 | } |
3450 | ||
80d11f44 JM |
3451 | static void init_proc_440EP (CPUPPCState *env) |
3452 | { | |
3453 | /* Time base */ | |
3454 | gen_tbl(env); | |
3455 | gen_spr_BookE(env, 0x000000000000FFFFULL); | |
3456 | gen_spr_440(env); | |
3457 | gen_spr_usprgh(env); | |
3458 | /* Processor identification */ | |
3459 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3460 | SPR_NOACCESS, SPR_NOACCESS, | |
3461 | &spr_read_generic, &spr_write_pir, | |
3462 | 0x00000000); | |
3463 | /* XXX : not implemented */ | |
3464 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3465 | SPR_NOACCESS, SPR_NOACCESS, | |
3466 | &spr_read_generic, &spr_write_generic, | |
3467 | 0x00000000); | |
3468 | /* XXX : not implemented */ | |
3469 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3470 | SPR_NOACCESS, SPR_NOACCESS, | |
3471 | &spr_read_generic, &spr_write_generic, | |
3472 | 0x00000000); | |
3473 | /* XXX : not implemented */ | |
3474 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3475 | SPR_NOACCESS, SPR_NOACCESS, | |
3476 | &spr_read_generic, &spr_write_generic, | |
3477 | 0x00000000); | |
3478 | /* XXX : not implemented */ | |
3479 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3480 | SPR_NOACCESS, SPR_NOACCESS, | |
3481 | &spr_read_generic, &spr_write_generic, | |
3482 | 0x00000000); | |
3483 | /* XXX : not implemented */ | |
3484 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", | |
3485 | SPR_NOACCESS, SPR_NOACCESS, | |
3486 | &spr_read_generic, &spr_write_generic, | |
3487 | 0x00000000); | |
3488 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3489 | SPR_NOACCESS, SPR_NOACCESS, | |
3490 | &spr_read_generic, &spr_write_generic, | |
3491 | 0x00000000); | |
3492 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3493 | SPR_NOACCESS, SPR_NOACCESS, | |
3494 | &spr_read_generic, &spr_write_generic, | |
3495 | 0x00000000); | |
3496 | /* XXX : not implemented */ | |
3497 | spr_register(env, SPR_440_CCR1, "CCR1", | |
3498 | SPR_NOACCESS, SPR_NOACCESS, | |
3499 | &spr_read_generic, &spr_write_generic, | |
3500 | 0x00000000); | |
3501 | /* Memory management */ | |
3502 | #if !defined(CONFIG_USER_ONLY) | |
3503 | env->nb_tlb = 64; | |
3504 | env->nb_ways = 1; | |
3505 | env->id_tlbs = 0; | |
1c53accc | 3506 | env->tlb_type = TLB_EMB; |
80d11f44 JM |
3507 | #endif |
3508 | init_excp_BookE(env); | |
3509 | env->dcache_line_size = 32; | |
3510 | env->icache_line_size = 32; | |
c0a7e81a | 3511 | ppc40x_irq_init(env); |
ddd1055b FC |
3512 | |
3513 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3514 | SET_WDT_PERIOD(20, 24, 28, 32); | |
80d11f44 JM |
3515 | } |
3516 | ||
7856e3a4 AF |
3517 | POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) |
3518 | { | |
ca5dff0a | 3519 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3520 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3521 | ||
ca5dff0a | 3522 | dc->desc = "PowerPC 440 EP"; |
7856e3a4 AF |
3523 | pcc->init_proc = init_proc_440EP; |
3524 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3525 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3526 | PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | | |
3527 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
3528 | PPC_FLOAT_STFIWX | | |
3529 | PPC_DCR | PPC_WRTEE | PPC_RFMCI | | |
3530 | PPC_CACHE | PPC_CACHE_ICBI | | |
3531 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3532 | PPC_MEM_TLBSYNC | PPC_MFTB | | |
3533 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
3534 | PPC_440_SPEC; | |
ba9fd9f1 AF |
3535 | pcc->msr_mask = 0x000000000006FF30ULL; |
3536 | pcc->mmu_model = POWERPC_MMU_BOOKE; | |
3537 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
3538 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
3539 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3540 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3541 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3542 | } |
3543 | ||
80d11f44 JM |
3544 | static void init_proc_440GP (CPUPPCState *env) |
3545 | { | |
3546 | /* Time base */ | |
3547 | gen_tbl(env); | |
3548 | gen_spr_BookE(env, 0x000000000000FFFFULL); | |
3549 | gen_spr_440(env); | |
3550 | gen_spr_usprgh(env); | |
3551 | /* Processor identification */ | |
3552 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3553 | SPR_NOACCESS, SPR_NOACCESS, | |
3554 | &spr_read_generic, &spr_write_pir, | |
3555 | 0x00000000); | |
3556 | /* XXX : not implemented */ | |
3557 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3558 | SPR_NOACCESS, SPR_NOACCESS, | |
3559 | &spr_read_generic, &spr_write_generic, | |
3560 | 0x00000000); | |
3561 | /* XXX : not implemented */ | |
3562 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3563 | SPR_NOACCESS, SPR_NOACCESS, | |
3564 | &spr_read_generic, &spr_write_generic, | |
3565 | 0x00000000); | |
3566 | /* XXX : not implemented */ | |
3567 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3568 | SPR_NOACCESS, SPR_NOACCESS, | |
3569 | &spr_read_generic, &spr_write_generic, | |
3570 | 0x00000000); | |
3571 | /* XXX : not implemented */ | |
3572 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3573 | SPR_NOACCESS, SPR_NOACCESS, | |
3574 | &spr_read_generic, &spr_write_generic, | |
3575 | 0x00000000); | |
3576 | /* Memory management */ | |
3577 | #if !defined(CONFIG_USER_ONLY) | |
3578 | env->nb_tlb = 64; | |
3579 | env->nb_ways = 1; | |
3580 | env->id_tlbs = 0; | |
1c53accc | 3581 | env->tlb_type = TLB_EMB; |
80d11f44 JM |
3582 | #endif |
3583 | init_excp_BookE(env); | |
3584 | env->dcache_line_size = 32; | |
3585 | env->icache_line_size = 32; | |
3586 | /* XXX: TODO: allocate internal IRQ controller */ | |
ddd1055b FC |
3587 | |
3588 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3589 | SET_WDT_PERIOD(20, 24, 28, 32); | |
80d11f44 JM |
3590 | } |
3591 | ||
7856e3a4 AF |
3592 | POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) |
3593 | { | |
ca5dff0a | 3594 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3595 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3596 | ||
ca5dff0a | 3597 | dc->desc = "PowerPC 440 GP"; |
7856e3a4 AF |
3598 | pcc->init_proc = init_proc_440GP; |
3599 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3600 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3601 | PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | | |
3602 | PPC_CACHE | PPC_CACHE_ICBI | | |
3603 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3604 | PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | | |
3605 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
3606 | PPC_440_SPEC; | |
ba9fd9f1 AF |
3607 | pcc->msr_mask = 0x000000000006FF30ULL; |
3608 | pcc->mmu_model = POWERPC_MMU_BOOKE; | |
3609 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
3610 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
3611 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3612 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3613 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3614 | } |
3615 | ||
80d11f44 JM |
3616 | static void init_proc_440x4 (CPUPPCState *env) |
3617 | { | |
3618 | /* Time base */ | |
3619 | gen_tbl(env); | |
3620 | gen_spr_BookE(env, 0x000000000000FFFFULL); | |
3621 | gen_spr_440(env); | |
3622 | gen_spr_usprgh(env); | |
3623 | /* Processor identification */ | |
3624 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3625 | SPR_NOACCESS, SPR_NOACCESS, | |
3626 | &spr_read_generic, &spr_write_pir, | |
3627 | 0x00000000); | |
3628 | /* XXX : not implemented */ | |
3629 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3630 | SPR_NOACCESS, SPR_NOACCESS, | |
3631 | &spr_read_generic, &spr_write_generic, | |
3632 | 0x00000000); | |
3633 | /* XXX : not implemented */ | |
3634 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3635 | SPR_NOACCESS, SPR_NOACCESS, | |
3636 | &spr_read_generic, &spr_write_generic, | |
3637 | 0x00000000); | |
3638 | /* XXX : not implemented */ | |
3639 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3640 | SPR_NOACCESS, SPR_NOACCESS, | |
3641 | &spr_read_generic, &spr_write_generic, | |
3642 | 0x00000000); | |
3643 | /* XXX : not implemented */ | |
3644 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3645 | SPR_NOACCESS, SPR_NOACCESS, | |
3646 | &spr_read_generic, &spr_write_generic, | |
3647 | 0x00000000); | |
3648 | /* Memory management */ | |
3649 | #if !defined(CONFIG_USER_ONLY) | |
3650 | env->nb_tlb = 64; | |
3651 | env->nb_ways = 1; | |
3652 | env->id_tlbs = 0; | |
1c53accc | 3653 | env->tlb_type = TLB_EMB; |
80d11f44 JM |
3654 | #endif |
3655 | init_excp_BookE(env); | |
d63001d1 JM |
3656 | env->dcache_line_size = 32; |
3657 | env->icache_line_size = 32; | |
80d11f44 | 3658 | /* XXX: TODO: allocate internal IRQ controller */ |
ddd1055b FC |
3659 | |
3660 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3661 | SET_WDT_PERIOD(20, 24, 28, 32); | |
3fc6c082 FB |
3662 | } |
3663 | ||
7856e3a4 AF |
3664 | POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) |
3665 | { | |
ca5dff0a | 3666 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3667 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3668 | ||
ca5dff0a | 3669 | dc->desc = "PowerPC 440x4"; |
7856e3a4 AF |
3670 | pcc->init_proc = init_proc_440x4; |
3671 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3672 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3673 | PPC_DCR | PPC_WRTEE | | |
3674 | PPC_CACHE | PPC_CACHE_ICBI | | |
3675 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3676 | PPC_MEM_TLBSYNC | PPC_MFTB | | |
3677 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
3678 | PPC_440_SPEC; | |
ba9fd9f1 AF |
3679 | pcc->msr_mask = 0x000000000006FF30ULL; |
3680 | pcc->mmu_model = POWERPC_MMU_BOOKE; | |
3681 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
3682 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
3683 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3684 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3685 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3686 | } |
3687 | ||
80d11f44 | 3688 | static void init_proc_440x5 (CPUPPCState *env) |
3fc6c082 | 3689 | { |
a750fc0b JM |
3690 | /* Time base */ |
3691 | gen_tbl(env); | |
80d11f44 JM |
3692 | gen_spr_BookE(env, 0x000000000000FFFFULL); |
3693 | gen_spr_440(env); | |
3694 | gen_spr_usprgh(env); | |
3695 | /* Processor identification */ | |
3696 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3697 | SPR_NOACCESS, SPR_NOACCESS, | |
3698 | &spr_read_generic, &spr_write_pir, | |
3699 | 0x00000000); | |
3700 | /* XXX : not implemented */ | |
3701 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
a750fc0b JM |
3702 | SPR_NOACCESS, SPR_NOACCESS, |
3703 | &spr_read_generic, &spr_write_generic, | |
80d11f44 JM |
3704 | 0x00000000); |
3705 | /* XXX : not implemented */ | |
3706 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3707 | SPR_NOACCESS, SPR_NOACCESS, | |
3708 | &spr_read_generic, &spr_write_generic, | |
3709 | 0x00000000); | |
3710 | /* XXX : not implemented */ | |
3711 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3712 | SPR_NOACCESS, SPR_NOACCESS, | |
3713 | &spr_read_generic, &spr_write_generic, | |
3714 | 0x00000000); | |
3715 | /* XXX : not implemented */ | |
3716 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3717 | SPR_NOACCESS, SPR_NOACCESS, | |
3718 | &spr_read_generic, &spr_write_generic, | |
3719 | 0x00000000); | |
3720 | /* XXX : not implemented */ | |
3721 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", | |
3722 | SPR_NOACCESS, SPR_NOACCESS, | |
3723 | &spr_read_generic, &spr_write_generic, | |
3724 | 0x00000000); | |
3725 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3726 | SPR_NOACCESS, SPR_NOACCESS, | |
3727 | &spr_read_generic, &spr_write_generic, | |
3728 | 0x00000000); | |
3729 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3730 | SPR_NOACCESS, SPR_NOACCESS, | |
3731 | &spr_read_generic, &spr_write_generic, | |
3732 | 0x00000000); | |
3733 | /* XXX : not implemented */ | |
3734 | spr_register(env, SPR_440_CCR1, "CCR1", | |
a750fc0b JM |
3735 | SPR_NOACCESS, SPR_NOACCESS, |
3736 | &spr_read_generic, &spr_write_generic, | |
3737 | 0x00000000); | |
3738 | /* Memory management */ | |
f2e63a42 | 3739 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3740 | env->nb_tlb = 64; |
3741 | env->nb_ways = 1; | |
3742 | env->id_tlbs = 0; | |
1c53accc | 3743 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3744 | #endif |
80d11f44 | 3745 | init_excp_BookE(env); |
d63001d1 JM |
3746 | env->dcache_line_size = 32; |
3747 | env->icache_line_size = 32; | |
95070372 | 3748 | ppc40x_irq_init(env); |
ddd1055b FC |
3749 | |
3750 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3751 | SET_WDT_PERIOD(20, 24, 28, 32); | |
3fc6c082 FB |
3752 | } |
3753 | ||
7856e3a4 AF |
3754 | POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) |
3755 | { | |
ca5dff0a | 3756 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3757 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3758 | ||
ca5dff0a | 3759 | dc->desc = "PowerPC 440x5"; |
7856e3a4 AF |
3760 | pcc->init_proc = init_proc_440x5; |
3761 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3762 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3763 | PPC_DCR | PPC_WRTEE | PPC_RFMCI | | |
3764 | PPC_CACHE | PPC_CACHE_ICBI | | |
3765 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3766 | PPC_MEM_TLBSYNC | PPC_MFTB | | |
3767 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
3768 | PPC_440_SPEC; | |
ba9fd9f1 AF |
3769 | pcc->msr_mask = 0x000000000006FF30ULL; |
3770 | pcc->mmu_model = POWERPC_MMU_BOOKE; | |
3771 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
3772 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
3773 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3774 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3775 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3776 | } |
3777 | ||
80d11f44 | 3778 | static void init_proc_460 (CPUPPCState *env) |
3fc6c082 | 3779 | { |
a750fc0b JM |
3780 | /* Time base */ |
3781 | gen_tbl(env); | |
80d11f44 | 3782 | gen_spr_BookE(env, 0x000000000000FFFFULL); |
a750fc0b | 3783 | gen_spr_440(env); |
80d11f44 JM |
3784 | gen_spr_usprgh(env); |
3785 | /* Processor identification */ | |
3786 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3787 | SPR_NOACCESS, SPR_NOACCESS, | |
3788 | &spr_read_generic, &spr_write_pir, | |
3789 | 0x00000000); | |
3790 | /* XXX : not implemented */ | |
3791 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3792 | SPR_NOACCESS, SPR_NOACCESS, | |
3793 | &spr_read_generic, &spr_write_generic, | |
3794 | 0x00000000); | |
3795 | /* XXX : not implemented */ | |
3796 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3797 | SPR_NOACCESS, SPR_NOACCESS, | |
3798 | &spr_read_generic, &spr_write_generic, | |
3799 | 0x00000000); | |
3800 | /* XXX : not implemented */ | |
3801 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3802 | SPR_NOACCESS, SPR_NOACCESS, | |
3803 | &spr_read_generic, &spr_write_generic, | |
3804 | 0x00000000); | |
3805 | /* XXX : not implemented */ | |
3806 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3807 | SPR_NOACCESS, SPR_NOACCESS, | |
3808 | &spr_read_generic, &spr_write_generic, | |
3809 | 0x00000000); | |
578bb252 | 3810 | /* XXX : not implemented */ |
a750fc0b JM |
3811 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", |
3812 | SPR_NOACCESS, SPR_NOACCESS, | |
3813 | &spr_read_generic, &spr_write_generic, | |
3814 | 0x00000000); | |
3815 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3816 | SPR_NOACCESS, SPR_NOACCESS, | |
3817 | &spr_read_generic, &spr_write_generic, | |
3818 | 0x00000000); | |
3819 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3820 | SPR_NOACCESS, SPR_NOACCESS, | |
3821 | &spr_read_generic, &spr_write_generic, | |
3822 | 0x00000000); | |
578bb252 | 3823 | /* XXX : not implemented */ |
a750fc0b JM |
3824 | spr_register(env, SPR_440_CCR1, "CCR1", |
3825 | SPR_NOACCESS, SPR_NOACCESS, | |
3826 | &spr_read_generic, &spr_write_generic, | |
3827 | 0x00000000); | |
80d11f44 JM |
3828 | /* XXX : not implemented */ |
3829 | spr_register(env, SPR_DCRIPR, "SPR_DCRIPR", | |
3830 | &spr_read_generic, &spr_write_generic, | |
3831 | &spr_read_generic, &spr_write_generic, | |
3832 | 0x00000000); | |
a750fc0b | 3833 | /* Memory management */ |
f2e63a42 | 3834 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3835 | env->nb_tlb = 64; |
3836 | env->nb_ways = 1; | |
3837 | env->id_tlbs = 0; | |
1c53accc | 3838 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3839 | #endif |
e1833e1f | 3840 | init_excp_BookE(env); |
d63001d1 JM |
3841 | env->dcache_line_size = 32; |
3842 | env->icache_line_size = 32; | |
a750fc0b | 3843 | /* XXX: TODO: allocate internal IRQ controller */ |
ddd1055b FC |
3844 | |
3845 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3846 | SET_WDT_PERIOD(20, 24, 28, 32); | |
3fc6c082 FB |
3847 | } |
3848 | ||
7856e3a4 AF |
3849 | POWERPC_FAMILY(460)(ObjectClass *oc, void *data) |
3850 | { | |
ca5dff0a | 3851 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3852 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3853 | ||
ca5dff0a | 3854 | dc->desc = "PowerPC 460 (guessed)"; |
7856e3a4 AF |
3855 | pcc->init_proc = init_proc_460; |
3856 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3857 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3858 | PPC_DCR | PPC_DCRX | PPC_DCRUX | | |
3859 | PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | | |
3860 | PPC_CACHE | PPC_CACHE_ICBI | | |
3861 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3862 | PPC_MEM_TLBSYNC | PPC_TLBIVA | | |
3863 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
3864 | PPC_440_SPEC; | |
ba9fd9f1 AF |
3865 | pcc->msr_mask = 0x000000000006FF30ULL; |
3866 | pcc->mmu_model = POWERPC_MMU_BOOKE; | |
3867 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
3868 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
3869 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3870 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3871 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3872 | } |
3873 | ||
80d11f44 | 3874 | static void init_proc_460F (CPUPPCState *env) |
3fc6c082 | 3875 | { |
a750fc0b JM |
3876 | /* Time base */ |
3877 | gen_tbl(env); | |
80d11f44 | 3878 | gen_spr_BookE(env, 0x000000000000FFFFULL); |
a750fc0b | 3879 | gen_spr_440(env); |
80d11f44 JM |
3880 | gen_spr_usprgh(env); |
3881 | /* Processor identification */ | |
3882 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
3883 | SPR_NOACCESS, SPR_NOACCESS, | |
3884 | &spr_read_generic, &spr_write_pir, | |
3885 | 0x00000000); | |
3886 | /* XXX : not implemented */ | |
3887 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
3888 | SPR_NOACCESS, SPR_NOACCESS, | |
3889 | &spr_read_generic, &spr_write_generic, | |
3890 | 0x00000000); | |
3891 | /* XXX : not implemented */ | |
3892 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
3893 | SPR_NOACCESS, SPR_NOACCESS, | |
3894 | &spr_read_generic, &spr_write_generic, | |
3895 | 0x00000000); | |
3896 | /* XXX : not implemented */ | |
3897 | spr_register(env, SPR_BOOKE_DVC1, "DVC1", | |
3898 | SPR_NOACCESS, SPR_NOACCESS, | |
3899 | &spr_read_generic, &spr_write_generic, | |
3900 | 0x00000000); | |
3901 | /* XXX : not implemented */ | |
3902 | spr_register(env, SPR_BOOKE_DVC2, "DVC2", | |
3903 | SPR_NOACCESS, SPR_NOACCESS, | |
3904 | &spr_read_generic, &spr_write_generic, | |
3905 | 0x00000000); | |
3906 | /* XXX : not implemented */ | |
3907 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", | |
3908 | SPR_NOACCESS, SPR_NOACCESS, | |
3909 | &spr_read_generic, &spr_write_generic, | |
3910 | 0x00000000); | |
3911 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", | |
3912 | SPR_NOACCESS, SPR_NOACCESS, | |
3913 | &spr_read_generic, &spr_write_generic, | |
3914 | 0x00000000); | |
3915 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
3916 | SPR_NOACCESS, SPR_NOACCESS, | |
3917 | &spr_read_generic, &spr_write_generic, | |
3918 | 0x00000000); | |
3919 | /* XXX : not implemented */ | |
3920 | spr_register(env, SPR_440_CCR1, "CCR1", | |
3921 | SPR_NOACCESS, SPR_NOACCESS, | |
3922 | &spr_read_generic, &spr_write_generic, | |
3923 | 0x00000000); | |
3924 | /* XXX : not implemented */ | |
3925 | spr_register(env, SPR_DCRIPR, "SPR_DCRIPR", | |
3926 | &spr_read_generic, &spr_write_generic, | |
3927 | &spr_read_generic, &spr_write_generic, | |
3928 | 0x00000000); | |
a750fc0b | 3929 | /* Memory management */ |
f2e63a42 | 3930 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
3931 | env->nb_tlb = 64; |
3932 | env->nb_ways = 1; | |
3933 | env->id_tlbs = 0; | |
1c53accc | 3934 | env->tlb_type = TLB_EMB; |
f2e63a42 | 3935 | #endif |
e1833e1f | 3936 | init_excp_BookE(env); |
d63001d1 JM |
3937 | env->dcache_line_size = 32; |
3938 | env->icache_line_size = 32; | |
a750fc0b | 3939 | /* XXX: TODO: allocate internal IRQ controller */ |
ddd1055b FC |
3940 | |
3941 | SET_FIT_PERIOD(12, 16, 20, 24); | |
3942 | SET_WDT_PERIOD(20, 24, 28, 32); | |
3fc6c082 FB |
3943 | } |
3944 | ||
7856e3a4 AF |
3945 | POWERPC_FAMILY(460F)(ObjectClass *oc, void *data) |
3946 | { | |
ca5dff0a | 3947 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3948 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3949 | ||
ca5dff0a | 3950 | dc->desc = "PowerPC 460F (guessed)"; |
7856e3a4 AF |
3951 | pcc->init_proc = init_proc_460F; |
3952 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
3953 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3954 | PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | | |
3955 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
3956 | PPC_FLOAT_STFIWX | PPC_MFTB | | |
3957 | PPC_DCR | PPC_DCRX | PPC_DCRUX | | |
3958 | PPC_WRTEE | PPC_MFAPIDI | | |
3959 | PPC_CACHE | PPC_CACHE_ICBI | | |
3960 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
3961 | PPC_MEM_TLBSYNC | PPC_TLBIVA | | |
3962 | PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | | |
3963 | PPC_440_SPEC; | |
ba9fd9f1 AF |
3964 | pcc->msr_mask = 0x000000000006FF30ULL; |
3965 | pcc->mmu_model = POWERPC_MMU_BOOKE; | |
3966 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
3967 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
3968 | pcc->bfd_mach = bfd_mach_ppc_403; | |
3969 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | | |
3970 | POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
3971 | } |
3972 | ||
80d11f44 JM |
3973 | static void init_proc_MPC5xx (CPUPPCState *env) |
3974 | { | |
3975 | /* Time base */ | |
3976 | gen_tbl(env); | |
3977 | gen_spr_5xx_8xx(env); | |
3978 | gen_spr_5xx(env); | |
3979 | init_excp_MPC5xx(env); | |
3980 | env->dcache_line_size = 32; | |
3981 | env->icache_line_size = 32; | |
3982 | /* XXX: TODO: allocate internal IRQ controller */ | |
3983 | } | |
3984 | ||
7856e3a4 AF |
3985 | POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) |
3986 | { | |
ca5dff0a | 3987 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
3988 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
3989 | ||
ca5dff0a | 3990 | dc->desc = "Freescale 5xx cores (aka RCPU)"; |
7856e3a4 AF |
3991 | pcc->init_proc = init_proc_MPC5xx; |
3992 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
3993 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
3994 | PPC_MEM_EIEIO | PPC_MEM_SYNC | | |
3995 | PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | | |
3996 | PPC_MFTB; | |
ba9fd9f1 AF |
3997 | pcc->msr_mask = 0x000000000001FF43ULL; |
3998 | pcc->mmu_model = POWERPC_MMU_REAL; | |
3999 | pcc->excp_model = POWERPC_EXCP_603; | |
4000 | pcc->bus_model = PPC_FLAGS_INPUT_RCPU; | |
4001 | pcc->bfd_mach = bfd_mach_ppc_505; | |
4002 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
4003 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4004 | } |
4005 | ||
80d11f44 JM |
4006 | static void init_proc_MPC8xx (CPUPPCState *env) |
4007 | { | |
4008 | /* Time base */ | |
4009 | gen_tbl(env); | |
4010 | gen_spr_5xx_8xx(env); | |
4011 | gen_spr_8xx(env); | |
4012 | init_excp_MPC8xx(env); | |
4013 | env->dcache_line_size = 32; | |
4014 | env->icache_line_size = 32; | |
4015 | /* XXX: TODO: allocate internal IRQ controller */ | |
4016 | } | |
4017 | ||
7856e3a4 AF |
4018 | POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) |
4019 | { | |
ca5dff0a | 4020 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4021 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4022 | ||
ca5dff0a | 4023 | dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; |
7856e3a4 AF |
4024 | pcc->init_proc = init_proc_MPC8xx; |
4025 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
4026 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | |
4027 | PPC_MEM_EIEIO | PPC_MEM_SYNC | | |
4028 | PPC_CACHE_ICBI | PPC_MFTB; | |
ba9fd9f1 AF |
4029 | pcc->msr_mask = 0x000000000001F673ULL; |
4030 | pcc->mmu_model = POWERPC_MMU_MPC8xx; | |
4031 | pcc->excp_model = POWERPC_EXCP_603; | |
4032 | pcc->bus_model = PPC_FLAGS_INPUT_RCPU; | |
4033 | pcc->bfd_mach = bfd_mach_ppc_860; | |
4034 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
4035 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4036 | } |
4037 | ||
80d11f44 | 4038 | /* Freescale 82xx cores (aka PowerQUICC-II) */ |
ca5dff0a | 4039 | |
80d11f44 | 4040 | static void init_proc_G2 (CPUPPCState *env) |
3fc6c082 | 4041 | { |
80d11f44 JM |
4042 | gen_spr_ne_601(env); |
4043 | gen_spr_G2_755(env); | |
4044 | gen_spr_G2(env); | |
a750fc0b JM |
4045 | /* Time base */ |
4046 | gen_tbl(env); | |
bd928eba JM |
4047 | /* External access control */ |
4048 | /* XXX : not implemented */ | |
4049 | spr_register(env, SPR_EAR, "EAR", | |
4050 | SPR_NOACCESS, SPR_NOACCESS, | |
4051 | &spr_read_generic, &spr_write_generic, | |
4052 | 0x00000000); | |
80d11f44 JM |
4053 | /* Hardware implementation register */ |
4054 | /* XXX : not implemented */ | |
4055 | spr_register(env, SPR_HID0, "HID0", | |
4056 | SPR_NOACCESS, SPR_NOACCESS, | |
4057 | &spr_read_generic, &spr_write_generic, | |
4058 | 0x00000000); | |
4059 | /* XXX : not implemented */ | |
4060 | spr_register(env, SPR_HID1, "HID1", | |
4061 | SPR_NOACCESS, SPR_NOACCESS, | |
4062 | &spr_read_generic, &spr_write_generic, | |
4063 | 0x00000000); | |
4064 | /* XXX : not implemented */ | |
4065 | spr_register(env, SPR_HID2, "HID2", | |
4066 | SPR_NOACCESS, SPR_NOACCESS, | |
4067 | &spr_read_generic, &spr_write_generic, | |
4068 | 0x00000000); | |
a750fc0b | 4069 | /* Memory management */ |
80d11f44 JM |
4070 | gen_low_BATs(env); |
4071 | gen_high_BATs(env); | |
4072 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
4073 | init_excp_G2(env); | |
d63001d1 JM |
4074 | env->dcache_line_size = 32; |
4075 | env->icache_line_size = 32; | |
80d11f44 JM |
4076 | /* Allocate hardware IRQ controller */ |
4077 | ppc6xx_irq_init(env); | |
3fc6c082 | 4078 | } |
a750fc0b | 4079 | |
7856e3a4 AF |
4080 | POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) |
4081 | { | |
ca5dff0a | 4082 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4083 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4084 | ||
ca5dff0a | 4085 | dc->desc = "PowerPC G2"; |
7856e3a4 AF |
4086 | pcc->init_proc = init_proc_G2; |
4087 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4088 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
4089 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
4090 | PPC_FLOAT_STFIWX | | |
4091 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4092 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
4093 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
4094 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
4095 | pcc->msr_mask = 0x000000000006FFF2ULL; |
4096 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; | |
4097 | pcc->excp_model = POWERPC_EXCP_G2; | |
4098 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4099 | pcc->bfd_mach = bfd_mach_ppc_ec603e; | |
4100 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
4101 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4102 | } |
4103 | ||
80d11f44 | 4104 | static void init_proc_G2LE (CPUPPCState *env) |
3fc6c082 | 4105 | { |
80d11f44 JM |
4106 | gen_spr_ne_601(env); |
4107 | gen_spr_G2_755(env); | |
4108 | gen_spr_G2(env); | |
a750fc0b JM |
4109 | /* Time base */ |
4110 | gen_tbl(env); | |
bd928eba JM |
4111 | /* External access control */ |
4112 | /* XXX : not implemented */ | |
4113 | spr_register(env, SPR_EAR, "EAR", | |
4114 | SPR_NOACCESS, SPR_NOACCESS, | |
4115 | &spr_read_generic, &spr_write_generic, | |
4116 | 0x00000000); | |
80d11f44 | 4117 | /* Hardware implementation register */ |
578bb252 | 4118 | /* XXX : not implemented */ |
80d11f44 | 4119 | spr_register(env, SPR_HID0, "HID0", |
a750fc0b JM |
4120 | SPR_NOACCESS, SPR_NOACCESS, |
4121 | &spr_read_generic, &spr_write_generic, | |
4122 | 0x00000000); | |
80d11f44 JM |
4123 | /* XXX : not implemented */ |
4124 | spr_register(env, SPR_HID1, "HID1", | |
a750fc0b JM |
4125 | SPR_NOACCESS, SPR_NOACCESS, |
4126 | &spr_read_generic, &spr_write_generic, | |
4127 | 0x00000000); | |
578bb252 | 4128 | /* XXX : not implemented */ |
80d11f44 | 4129 | spr_register(env, SPR_HID2, "HID2", |
a750fc0b JM |
4130 | SPR_NOACCESS, SPR_NOACCESS, |
4131 | &spr_read_generic, &spr_write_generic, | |
4132 | 0x00000000); | |
2bc17322 FC |
4133 | /* Breakpoints */ |
4134 | /* XXX : not implemented */ | |
4135 | spr_register(env, SPR_DABR, "DABR", | |
4136 | SPR_NOACCESS, SPR_NOACCESS, | |
4137 | &spr_read_generic, &spr_write_generic, | |
4138 | 0x00000000); | |
4139 | /* XXX : not implemented */ | |
4140 | spr_register(env, SPR_DABR2, "DABR2", | |
4141 | SPR_NOACCESS, SPR_NOACCESS, | |
4142 | &spr_read_generic, &spr_write_generic, | |
4143 | 0x00000000); | |
4144 | /* XXX : not implemented */ | |
4145 | spr_register(env, SPR_IABR2, "IABR2", | |
4146 | SPR_NOACCESS, SPR_NOACCESS, | |
4147 | &spr_read_generic, &spr_write_generic, | |
4148 | 0x00000000); | |
4149 | /* XXX : not implemented */ | |
4150 | spr_register(env, SPR_IBCR, "IBCR", | |
4151 | SPR_NOACCESS, SPR_NOACCESS, | |
4152 | &spr_read_generic, &spr_write_generic, | |
4153 | 0x00000000); | |
4154 | /* XXX : not implemented */ | |
4155 | spr_register(env, SPR_DBCR, "DBCR", | |
4156 | SPR_NOACCESS, SPR_NOACCESS, | |
4157 | &spr_read_generic, &spr_write_generic, | |
4158 | 0x00000000); | |
4159 | ||
a750fc0b | 4160 | /* Memory management */ |
80d11f44 JM |
4161 | gen_low_BATs(env); |
4162 | gen_high_BATs(env); | |
4163 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
4164 | init_excp_G2(env); | |
d63001d1 JM |
4165 | env->dcache_line_size = 32; |
4166 | env->icache_line_size = 32; | |
80d11f44 JM |
4167 | /* Allocate hardware IRQ controller */ |
4168 | ppc6xx_irq_init(env); | |
3fc6c082 FB |
4169 | } |
4170 | ||
7856e3a4 AF |
4171 | POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) |
4172 | { | |
ca5dff0a | 4173 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4174 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4175 | ||
ca5dff0a | 4176 | dc->desc = "PowerPC G2LE"; |
7856e3a4 AF |
4177 | pcc->init_proc = init_proc_G2LE; |
4178 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4179 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
4180 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
4181 | PPC_FLOAT_STFIWX | | |
4182 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4183 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
4184 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
4185 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
4186 | pcc->msr_mask = 0x000000000007FFF3ULL; |
4187 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; | |
4188 | pcc->excp_model = POWERPC_EXCP_G2; | |
4189 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4190 | pcc->bfd_mach = bfd_mach_ppc_ec603e; | |
4191 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
4192 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4193 | } |
4194 | ||
80d11f44 | 4195 | static void init_proc_e200 (CPUPPCState *env) |
3fc6c082 | 4196 | { |
e1833e1f JM |
4197 | /* Time base */ |
4198 | gen_tbl(env); | |
80d11f44 | 4199 | gen_spr_BookE(env, 0x000000070000FFFFULL); |
578bb252 | 4200 | /* XXX : not implemented */ |
80d11f44 | 4201 | spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", |
d34defbc AJ |
4202 | &spr_read_spefscr, &spr_write_spefscr, |
4203 | &spr_read_spefscr, &spr_write_spefscr, | |
e1833e1f | 4204 | 0x00000000); |
80d11f44 | 4205 | /* Memory management */ |
01662f3e | 4206 | gen_spr_BookE206(env, 0x0000005D, NULL); |
80d11f44 JM |
4207 | /* XXX : not implemented */ |
4208 | spr_register(env, SPR_HID0, "HID0", | |
e1833e1f JM |
4209 | SPR_NOACCESS, SPR_NOACCESS, |
4210 | &spr_read_generic, &spr_write_generic, | |
4211 | 0x00000000); | |
80d11f44 JM |
4212 | /* XXX : not implemented */ |
4213 | spr_register(env, SPR_HID1, "HID1", | |
e1833e1f JM |
4214 | SPR_NOACCESS, SPR_NOACCESS, |
4215 | &spr_read_generic, &spr_write_generic, | |
4216 | 0x00000000); | |
578bb252 | 4217 | /* XXX : not implemented */ |
80d11f44 | 4218 | spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", |
e1833e1f JM |
4219 | SPR_NOACCESS, SPR_NOACCESS, |
4220 | &spr_read_generic, &spr_write_generic, | |
4221 | 0x00000000); | |
578bb252 | 4222 | /* XXX : not implemented */ |
80d11f44 JM |
4223 | spr_register(env, SPR_Exxx_BUCSR, "BUCSR", |
4224 | SPR_NOACCESS, SPR_NOACCESS, | |
e1833e1f | 4225 | &spr_read_generic, &spr_write_generic, |
80d11f44 JM |
4226 | 0x00000000); |
4227 | /* XXX : not implemented */ | |
4228 | spr_register(env, SPR_Exxx_CTXCR, "CTXCR", | |
4229 | SPR_NOACCESS, SPR_NOACCESS, | |
4230 | &spr_read_generic, &spr_write_generic, | |
4231 | 0x00000000); | |
4232 | /* XXX : not implemented */ | |
4233 | spr_register(env, SPR_Exxx_DBCNT, "DBCNT", | |
4234 | SPR_NOACCESS, SPR_NOACCESS, | |
4235 | &spr_read_generic, &spr_write_generic, | |
4236 | 0x00000000); | |
4237 | /* XXX : not implemented */ | |
4238 | spr_register(env, SPR_Exxx_DBCR3, "DBCR3", | |
4239 | SPR_NOACCESS, SPR_NOACCESS, | |
4240 | &spr_read_generic, &spr_write_generic, | |
4241 | 0x00000000); | |
4242 | /* XXX : not implemented */ | |
4243 | spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", | |
4244 | SPR_NOACCESS, SPR_NOACCESS, | |
4245 | &spr_read_generic, &spr_write_generic, | |
4246 | 0x00000000); | |
4247 | /* XXX : not implemented */ | |
4248 | spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", | |
4249 | SPR_NOACCESS, SPR_NOACCESS, | |
4250 | &spr_read_generic, &spr_write_generic, | |
4251 | 0x00000000); | |
4252 | /* XXX : not implemented */ | |
4253 | spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", | |
4254 | SPR_NOACCESS, SPR_NOACCESS, | |
4255 | &spr_read_generic, &spr_write_generic, | |
4256 | 0x00000000); | |
4257 | /* XXX : not implemented */ | |
4258 | spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", | |
4259 | SPR_NOACCESS, SPR_NOACCESS, | |
4260 | &spr_read_generic, &spr_write_generic, | |
4261 | 0x00000000); | |
4262 | /* XXX : not implemented */ | |
4263 | spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", | |
4264 | SPR_NOACCESS, SPR_NOACCESS, | |
4265 | &spr_read_generic, &spr_write_generic, | |
4266 | 0x00000000); | |
4267 | /* XXX : not implemented */ | |
4268 | spr_register(env, SPR_BOOKE_IAC3, "IAC3", | |
4269 | SPR_NOACCESS, SPR_NOACCESS, | |
4270 | &spr_read_generic, &spr_write_generic, | |
4271 | 0x00000000); | |
4272 | /* XXX : not implemented */ | |
4273 | spr_register(env, SPR_BOOKE_IAC4, "IAC4", | |
4274 | SPR_NOACCESS, SPR_NOACCESS, | |
4275 | &spr_read_generic, &spr_write_generic, | |
4276 | 0x00000000); | |
01662f3e AG |
4277 | /* XXX : not implemented */ |
4278 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
4279 | SPR_NOACCESS, SPR_NOACCESS, | |
4280 | &spr_read_generic, &spr_write_generic, | |
4281 | 0x00000000); /* TOFIX */ | |
80d11f44 JM |
4282 | spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", |
4283 | SPR_NOACCESS, SPR_NOACCESS, | |
4284 | &spr_read_generic, &spr_write_generic, | |
4285 | 0x00000000); | |
4286 | spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", | |
4287 | SPR_NOACCESS, SPR_NOACCESS, | |
e1833e1f JM |
4288 | &spr_read_generic, &spr_write_generic, |
4289 | 0x00000000); | |
f2e63a42 | 4290 | #if !defined(CONFIG_USER_ONLY) |
e1833e1f JM |
4291 | env->nb_tlb = 64; |
4292 | env->nb_ways = 1; | |
4293 | env->id_tlbs = 0; | |
1c53accc | 4294 | env->tlb_type = TLB_EMB; |
f2e63a42 | 4295 | #endif |
e9cd84b9 | 4296 | init_excp_e200(env, 0xFFFF0000UL); |
d63001d1 JM |
4297 | env->dcache_line_size = 32; |
4298 | env->icache_line_size = 32; | |
e1833e1f | 4299 | /* XXX: TODO: allocate internal IRQ controller */ |
3fc6c082 | 4300 | } |
a750fc0b | 4301 | |
7856e3a4 AF |
4302 | POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) |
4303 | { | |
ca5dff0a | 4304 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4305 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4306 | ||
ca5dff0a | 4307 | dc->desc = "e200 core"; |
7856e3a4 AF |
4308 | pcc->init_proc = init_proc_e200; |
4309 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4310 | /* XXX: unimplemented instructions: |
4311 | * dcblc | |
4312 | * dcbtlst | |
4313 | * dcbtstls | |
4314 | * icblc | |
4315 | * icbtls | |
4316 | * tlbivax | |
4317 | * all SPE multiply-accumulate instructions | |
4318 | */ | |
4319 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | | |
4320 | PPC_SPE | PPC_SPE_SINGLE | | |
4321 | PPC_WRTEE | PPC_RFDI | | |
4322 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
4323 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4324 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | | |
4325 | PPC_BOOKE; | |
ba9fd9f1 AF |
4326 | pcc->msr_mask = 0x000000000606FF30ULL; |
4327 | pcc->mmu_model = POWERPC_MMU_BOOKE206; | |
4328 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4329 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4330 | pcc->bfd_mach = bfd_mach_ppc_860; | |
4331 | pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | | |
4332 | POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | | |
4333 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4334 | } |
4335 | ||
80d11f44 | 4336 | static void init_proc_e300 (CPUPPCState *env) |
3fc6c082 | 4337 | { |
80d11f44 JM |
4338 | gen_spr_ne_601(env); |
4339 | gen_spr_603(env); | |
a750fc0b JM |
4340 | /* Time base */ |
4341 | gen_tbl(env); | |
80d11f44 JM |
4342 | /* hardware implementation registers */ |
4343 | /* XXX : not implemented */ | |
4344 | spr_register(env, SPR_HID0, "HID0", | |
4345 | SPR_NOACCESS, SPR_NOACCESS, | |
4346 | &spr_read_generic, &spr_write_generic, | |
4347 | 0x00000000); | |
4348 | /* XXX : not implemented */ | |
4349 | spr_register(env, SPR_HID1, "HID1", | |
4350 | SPR_NOACCESS, SPR_NOACCESS, | |
4351 | &spr_read_generic, &spr_write_generic, | |
4352 | 0x00000000); | |
8daf1781 TM |
4353 | /* XXX : not implemented */ |
4354 | spr_register(env, SPR_HID2, "HID2", | |
4355 | SPR_NOACCESS, SPR_NOACCESS, | |
4356 | &spr_read_generic, &spr_write_generic, | |
4357 | 0x00000000); | |
80d11f44 JM |
4358 | /* Memory management */ |
4359 | gen_low_BATs(env); | |
8daf1781 | 4360 | gen_high_BATs(env); |
80d11f44 JM |
4361 | gen_6xx_7xx_soft_tlb(env, 64, 2); |
4362 | init_excp_603(env); | |
4363 | env->dcache_line_size = 32; | |
4364 | env->icache_line_size = 32; | |
4365 | /* Allocate hardware IRQ controller */ | |
4366 | ppc6xx_irq_init(env); | |
4367 | } | |
4368 | ||
7856e3a4 AF |
4369 | POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) |
4370 | { | |
ca5dff0a | 4371 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4372 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4373 | ||
ca5dff0a | 4374 | dc->desc = "e300 core"; |
7856e3a4 AF |
4375 | pcc->init_proc = init_proc_e300; |
4376 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4377 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
4378 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
4379 | PPC_FLOAT_STFIWX | | |
4380 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4381 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
4382 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
4383 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
4384 | pcc->msr_mask = 0x000000000007FFF3ULL; |
4385 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; | |
4386 | pcc->excp_model = POWERPC_EXCP_603; | |
4387 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4388 | pcc->bfd_mach = bfd_mach_ppc_603; | |
4389 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
4390 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4391 | } |
4392 | ||
b81ccf8a AG |
4393 | #if !defined(CONFIG_USER_ONLY) |
4394 | static void spr_write_mas73(void *opaque, int sprn, int gprn) | |
4395 | { | |
4396 | TCGv val = tcg_temp_new(); | |
4397 | tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); | |
4398 | gen_store_spr(SPR_BOOKE_MAS3, val); | |
cfee0218 | 4399 | tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); |
b81ccf8a AG |
4400 | gen_store_spr(SPR_BOOKE_MAS7, val); |
4401 | tcg_temp_free(val); | |
4402 | } | |
4403 | ||
4404 | static void spr_read_mas73(void *opaque, int gprn, int sprn) | |
4405 | { | |
4406 | TCGv mas7 = tcg_temp_new(); | |
4407 | TCGv mas3 = tcg_temp_new(); | |
4408 | gen_load_spr(mas7, SPR_BOOKE_MAS7); | |
4409 | tcg_gen_shli_tl(mas7, mas7, 32); | |
4410 | gen_load_spr(mas3, SPR_BOOKE_MAS3); | |
4411 | tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); | |
4412 | tcg_temp_free(mas3); | |
4413 | tcg_temp_free(mas7); | |
4414 | } | |
4415 | ||
b81ccf8a AG |
4416 | #endif |
4417 | ||
f7aa5583 VS |
4418 | enum fsl_e500_version { |
4419 | fsl_e500v1, | |
4420 | fsl_e500v2, | |
4421 | fsl_e500mc, | |
b81ccf8a | 4422 | fsl_e5500, |
f7aa5583 VS |
4423 | }; |
4424 | ||
01662f3e | 4425 | static void init_proc_e500 (CPUPPCState *env, int version) |
80d11f44 | 4426 | { |
01662f3e | 4427 | uint32_t tlbncfg[2]; |
b81ccf8a | 4428 | uint64_t ivor_mask; |
e9cd84b9 | 4429 | uint64_t ivpr_mask = 0xFFFF0000ULL; |
a496e8ee AG |
4430 | uint32_t l1cfg0 = 0x3800 /* 8 ways */ |
4431 | | 0x0020; /* 32 kb */ | |
01662f3e AG |
4432 | #if !defined(CONFIG_USER_ONLY) |
4433 | int i; | |
4434 | #endif | |
4435 | ||
80d11f44 JM |
4436 | /* Time base */ |
4437 | gen_tbl(env); | |
01662f3e AG |
4438 | /* |
4439 | * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't | |
4440 | * complain when accessing them. | |
4441 | * gen_spr_BookE(env, 0x0000000F0000FD7FULL); | |
4442 | */ | |
b81ccf8a AG |
4443 | switch (version) { |
4444 | case fsl_e500v1: | |
4445 | case fsl_e500v2: | |
4446 | default: | |
4447 | ivor_mask = 0x0000000F0000FFFFULL; | |
4448 | break; | |
4449 | case fsl_e500mc: | |
4450 | case fsl_e5500: | |
4451 | ivor_mask = 0x000003FE0000FFFFULL; | |
4452 | break; | |
2c9732db AG |
4453 | } |
4454 | gen_spr_BookE(env, ivor_mask); | |
80d11f44 JM |
4455 | /* Processor identification */ |
4456 | spr_register(env, SPR_BOOKE_PIR, "PIR", | |
4457 | SPR_NOACCESS, SPR_NOACCESS, | |
4458 | &spr_read_generic, &spr_write_pir, | |
4459 | 0x00000000); | |
4460 | /* XXX : not implemented */ | |
4461 | spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", | |
d34defbc AJ |
4462 | &spr_read_spefscr, &spr_write_spefscr, |
4463 | &spr_read_spefscr, &spr_write_spefscr, | |
80d11f44 | 4464 | 0x00000000); |
892c587f | 4465 | #if !defined(CONFIG_USER_ONLY) |
80d11f44 | 4466 | /* Memory management */ |
80d11f44 | 4467 | env->nb_pids = 3; |
01662f3e AG |
4468 | env->nb_ways = 2; |
4469 | env->id_tlbs = 0; | |
4470 | switch (version) { | |
f7aa5583 | 4471 | case fsl_e500v1: |
01662f3e AG |
4472 | tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); |
4473 | tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); | |
4474 | break; | |
f7aa5583 | 4475 | case fsl_e500v2: |
01662f3e AG |
4476 | tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); |
4477 | tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); | |
f7aa5583 VS |
4478 | break; |
4479 | case fsl_e500mc: | |
b81ccf8a | 4480 | case fsl_e5500: |
f7aa5583 VS |
4481 | tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); |
4482 | tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); | |
892c587f AG |
4483 | break; |
4484 | default: | |
4485 | cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); | |
4486 | } | |
4487 | #endif | |
4488 | /* Cache sizes */ | |
4489 | switch (version) { | |
4490 | case fsl_e500v1: | |
4491 | case fsl_e500v2: | |
4492 | env->dcache_line_size = 32; | |
4493 | env->icache_line_size = 32; | |
4494 | break; | |
4495 | case fsl_e500mc: | |
b81ccf8a | 4496 | case fsl_e5500: |
f7aa5583 VS |
4497 | env->dcache_line_size = 64; |
4498 | env->icache_line_size = 64; | |
a496e8ee | 4499 | l1cfg0 |= 0x1000000; /* 64 byte cache block size */ |
01662f3e AG |
4500 | break; |
4501 | default: | |
4502 | cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); | |
4503 | } | |
01662f3e | 4504 | gen_spr_BookE206(env, 0x000000DF, tlbncfg); |
80d11f44 JM |
4505 | /* XXX : not implemented */ |
4506 | spr_register(env, SPR_HID0, "HID0", | |
4507 | SPR_NOACCESS, SPR_NOACCESS, | |
4508 | &spr_read_generic, &spr_write_generic, | |
4509 | 0x00000000); | |
4510 | /* XXX : not implemented */ | |
4511 | spr_register(env, SPR_HID1, "HID1", | |
4512 | SPR_NOACCESS, SPR_NOACCESS, | |
4513 | &spr_read_generic, &spr_write_generic, | |
4514 | 0x00000000); | |
4515 | /* XXX : not implemented */ | |
4516 | spr_register(env, SPR_Exxx_BBEAR, "BBEAR", | |
4517 | SPR_NOACCESS, SPR_NOACCESS, | |
4518 | &spr_read_generic, &spr_write_generic, | |
4519 | 0x00000000); | |
4520 | /* XXX : not implemented */ | |
4521 | spr_register(env, SPR_Exxx_BBTAR, "BBTAR", | |
4522 | SPR_NOACCESS, SPR_NOACCESS, | |
4523 | &spr_read_generic, &spr_write_generic, | |
4524 | 0x00000000); | |
4525 | /* XXX : not implemented */ | |
4526 | spr_register(env, SPR_Exxx_MCAR, "MCAR", | |
4527 | SPR_NOACCESS, SPR_NOACCESS, | |
4528 | &spr_read_generic, &spr_write_generic, | |
4529 | 0x00000000); | |
578bb252 | 4530 | /* XXX : not implemented */ |
a750fc0b JM |
4531 | spr_register(env, SPR_BOOKE_MCSR, "MCSR", |
4532 | SPR_NOACCESS, SPR_NOACCESS, | |
4533 | &spr_read_generic, &spr_write_generic, | |
4534 | 0x00000000); | |
80d11f44 JM |
4535 | /* XXX : not implemented */ |
4536 | spr_register(env, SPR_Exxx_NPIDR, "NPIDR", | |
a750fc0b JM |
4537 | SPR_NOACCESS, SPR_NOACCESS, |
4538 | &spr_read_generic, &spr_write_generic, | |
4539 | 0x00000000); | |
80d11f44 JM |
4540 | /* XXX : not implemented */ |
4541 | spr_register(env, SPR_Exxx_BUCSR, "BUCSR", | |
a750fc0b JM |
4542 | SPR_NOACCESS, SPR_NOACCESS, |
4543 | &spr_read_generic, &spr_write_generic, | |
4544 | 0x00000000); | |
578bb252 | 4545 | /* XXX : not implemented */ |
80d11f44 | 4546 | spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", |
a750fc0b JM |
4547 | SPR_NOACCESS, SPR_NOACCESS, |
4548 | &spr_read_generic, &spr_write_generic, | |
a496e8ee | 4549 | l1cfg0); |
578bb252 | 4550 | /* XXX : not implemented */ |
80d11f44 JM |
4551 | spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", |
4552 | SPR_NOACCESS, SPR_NOACCESS, | |
01662f3e | 4553 | &spr_read_generic, &spr_write_e500_l1csr0, |
80d11f44 JM |
4554 | 0x00000000); |
4555 | /* XXX : not implemented */ | |
4556 | spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", | |
4557 | SPR_NOACCESS, SPR_NOACCESS, | |
4558 | &spr_read_generic, &spr_write_generic, | |
4559 | 0x00000000); | |
80d11f44 JM |
4560 | spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", |
4561 | SPR_NOACCESS, SPR_NOACCESS, | |
4562 | &spr_read_generic, &spr_write_generic, | |
4563 | 0x00000000); | |
4564 | spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", | |
4565 | SPR_NOACCESS, SPR_NOACCESS, | |
a750fc0b JM |
4566 | &spr_read_generic, &spr_write_generic, |
4567 | 0x00000000); | |
01662f3e AG |
4568 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", |
4569 | SPR_NOACCESS, SPR_NOACCESS, | |
4570 | &spr_read_generic, &spr_write_booke206_mmucsr0, | |
4571 | 0x00000000); | |
b81ccf8a AG |
4572 | spr_register(env, SPR_BOOKE_EPR, "EPR", |
4573 | SPR_NOACCESS, SPR_NOACCESS, | |
68c2dd70 | 4574 | &spr_read_generic, SPR_NOACCESS, |
b81ccf8a AG |
4575 | 0x00000000); |
4576 | /* XXX better abstract into Emb.xxx features */ | |
4577 | if (version == fsl_e5500) { | |
4578 | spr_register(env, SPR_BOOKE_EPCR, "EPCR", | |
4579 | SPR_NOACCESS, SPR_NOACCESS, | |
4580 | &spr_read_generic, &spr_write_generic, | |
4581 | 0x00000000); | |
4582 | spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", | |
4583 | SPR_NOACCESS, SPR_NOACCESS, | |
4584 | &spr_read_mas73, &spr_write_mas73, | |
4585 | 0x00000000); | |
4586 | ivpr_mask = (target_ulong)~0xFFFFULL; | |
4587 | } | |
01662f3e | 4588 | |
f2e63a42 | 4589 | #if !defined(CONFIG_USER_ONLY) |
01662f3e | 4590 | env->nb_tlb = 0; |
1c53accc | 4591 | env->tlb_type = TLB_MAS; |
01662f3e AG |
4592 | for (i = 0; i < BOOKE206_MAX_TLBN; i++) { |
4593 | env->nb_tlb += booke206_tlb_size(env, i); | |
4594 | } | |
f2e63a42 | 4595 | #endif |
01662f3e | 4596 | |
e9cd84b9 | 4597 | init_excp_e200(env, ivpr_mask); |
9fdc60bf AJ |
4598 | /* Allocate hardware IRQ controller */ |
4599 | ppce500_irq_init(env); | |
3fc6c082 | 4600 | } |
a750fc0b | 4601 | |
01662f3e AG |
4602 | static void init_proc_e500v1(CPUPPCState *env) |
4603 | { | |
f7aa5583 | 4604 | init_proc_e500(env, fsl_e500v1); |
01662f3e AG |
4605 | } |
4606 | ||
7856e3a4 AF |
4607 | POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) |
4608 | { | |
ca5dff0a | 4609 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4610 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4611 | ||
ca5dff0a | 4612 | dc->desc = "e500v1 core"; |
7856e3a4 AF |
4613 | pcc->init_proc = init_proc_e500v1; |
4614 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4615 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | |
4616 | PPC_SPE | PPC_SPE_SINGLE | | |
4617 | PPC_WRTEE | PPC_RFDI | | |
4618 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
4619 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4620 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; | |
4621 | pcc->insns_flags2 = PPC2_BOOKE206; | |
ba9fd9f1 AF |
4622 | pcc->msr_mask = 0x000000000606FF30ULL; |
4623 | pcc->mmu_model = POWERPC_MMU_BOOKE206; | |
4624 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4625 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4626 | pcc->bfd_mach = bfd_mach_ppc_860; | |
4627 | pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | | |
4628 | POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | | |
4629 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4630 | } |
4631 | ||
01662f3e AG |
4632 | static void init_proc_e500v2(CPUPPCState *env) |
4633 | { | |
f7aa5583 VS |
4634 | init_proc_e500(env, fsl_e500v2); |
4635 | } | |
4636 | ||
7856e3a4 AF |
4637 | POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) |
4638 | { | |
ca5dff0a | 4639 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4640 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4641 | ||
ca5dff0a | 4642 | dc->desc = "e500v2 core"; |
7856e3a4 AF |
4643 | pcc->init_proc = init_proc_e500v2; |
4644 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4645 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | |
4646 | PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | | |
4647 | PPC_WRTEE | PPC_RFDI | | |
4648 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
4649 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4650 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; | |
4651 | pcc->insns_flags2 = PPC2_BOOKE206; | |
ba9fd9f1 AF |
4652 | pcc->msr_mask = 0x000000000606FF30ULL; |
4653 | pcc->mmu_model = POWERPC_MMU_BOOKE206; | |
4654 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4655 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4656 | pcc->bfd_mach = bfd_mach_ppc_860; | |
4657 | pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | | |
4658 | POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | | |
4659 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4660 | } |
4661 | ||
f7aa5583 VS |
4662 | static void init_proc_e500mc(CPUPPCState *env) |
4663 | { | |
4664 | init_proc_e500(env, fsl_e500mc); | |
01662f3e AG |
4665 | } |
4666 | ||
7856e3a4 AF |
4667 | POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) |
4668 | { | |
ca5dff0a | 4669 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4670 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4671 | ||
ca5dff0a | 4672 | dc->desc = "e500mc core"; |
7856e3a4 AF |
4673 | pcc->init_proc = init_proc_e500mc; |
4674 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
4675 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | |
4676 | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | | |
4677 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
4678 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4679 | PPC_FLOAT | PPC_FLOAT_FRES | | |
4680 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | | |
4681 | PPC_FLOAT_STFIWX | PPC_WAIT | | |
4682 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; | |
4683 | pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; | |
ba9fd9f1 AF |
4684 | pcc->msr_mask = 0x000000001402FB36ULL; |
4685 | pcc->mmu_model = POWERPC_MMU_BOOKE206; | |
4686 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4687 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4688 | /* FIXME: figure out the correct flag for e500mc */ | |
4689 | pcc->bfd_mach = bfd_mach_ppc_e500; | |
4690 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
4691 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4692 | } |
4693 | ||
b81ccf8a AG |
4694 | #ifdef TARGET_PPC64 |
4695 | static void init_proc_e5500(CPUPPCState *env) | |
4696 | { | |
4697 | init_proc_e500(env, fsl_e5500); | |
4698 | } | |
7856e3a4 AF |
4699 | |
4700 | POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) | |
4701 | { | |
ca5dff0a | 4702 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4703 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4704 | ||
ca5dff0a | 4705 | dc->desc = "e5500 core"; |
7856e3a4 AF |
4706 | pcc->init_proc = init_proc_e5500; |
4707 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
4708 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | |
4709 | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | | |
4710 | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | | |
4711 | PPC_CACHE_DCBZ | PPC_CACHE_DCBA | | |
4712 | PPC_FLOAT | PPC_FLOAT_FRES | | |
4713 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | | |
4714 | PPC_FLOAT_STFIWX | PPC_WAIT | | |
4715 | PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | | |
4716 | PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; | |
4717 | pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; | |
ba9fd9f1 AF |
4718 | pcc->msr_mask = 0x000000009402FB36ULL; |
4719 | pcc->mmu_model = POWERPC_MMU_BOOKE206; | |
4720 | pcc->excp_model = POWERPC_EXCP_BOOKE; | |
4721 | pcc->bus_model = PPC_FLAGS_INPUT_BookE; | |
4722 | /* FIXME: figure out the correct flag for e5500 */ | |
4723 | pcc->bfd_mach = bfd_mach_ppc_e500; | |
4724 | pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | | |
4725 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 | 4726 | } |
b81ccf8a AG |
4727 | #endif |
4728 | ||
a750fc0b | 4729 | /* Non-embedded PowerPC */ |
a750fc0b JM |
4730 | |
4731 | /* POWER : same as 601, without mfmsr, mfsr */ | |
53116ebf AF |
4732 | POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data) |
4733 | { | |
ca5dff0a | 4734 | DeviceClass *dc = DEVICE_CLASS(oc); |
53116ebf AF |
4735 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4736 | ||
ca5dff0a | 4737 | dc->desc = "POWER"; |
953af181 | 4738 | /* pcc->insns_flags = XXX_TODO; */ |
ba9fd9f1 AF |
4739 | /* POWER RSC (from RAD6000) */ |
4740 | pcc->msr_mask = 0x00000000FEF0ULL; | |
53116ebf | 4741 | } |
a750fc0b | 4742 | |
082c6681 | 4743 | #define POWERPC_MSRR_601 (0x0000000000001040ULL) |
a750fc0b JM |
4744 | |
4745 | static void init_proc_601 (CPUPPCState *env) | |
3fc6c082 | 4746 | { |
a750fc0b JM |
4747 | gen_spr_ne_601(env); |
4748 | gen_spr_601(env); | |
4749 | /* Hardware implementation registers */ | |
4750 | /* XXX : not implemented */ | |
4751 | spr_register(env, SPR_HID0, "HID0", | |
4752 | SPR_NOACCESS, SPR_NOACCESS, | |
056401ea | 4753 | &spr_read_generic, &spr_write_hid0_601, |
faadf50e | 4754 | 0x80010080); |
a750fc0b JM |
4755 | /* XXX : not implemented */ |
4756 | spr_register(env, SPR_HID1, "HID1", | |
4757 | SPR_NOACCESS, SPR_NOACCESS, | |
4758 | &spr_read_generic, &spr_write_generic, | |
4759 | 0x00000000); | |
4760 | /* XXX : not implemented */ | |
4761 | spr_register(env, SPR_601_HID2, "HID2", | |
4762 | SPR_NOACCESS, SPR_NOACCESS, | |
4763 | &spr_read_generic, &spr_write_generic, | |
4764 | 0x00000000); | |
4765 | /* XXX : not implemented */ | |
4766 | spr_register(env, SPR_601_HID5, "HID5", | |
4767 | SPR_NOACCESS, SPR_NOACCESS, | |
4768 | &spr_read_generic, &spr_write_generic, | |
4769 | 0x00000000); | |
a750fc0b | 4770 | /* Memory management */ |
e1833e1f | 4771 | init_excp_601(env); |
082c6681 JM |
4772 | /* XXX: beware that dcache line size is 64 |
4773 | * but dcbz uses 32 bytes "sectors" | |
4774 | * XXX: this breaks clcs instruction ! | |
4775 | */ | |
4776 | env->dcache_line_size = 32; | |
d63001d1 | 4777 | env->icache_line_size = 64; |
faadf50e JM |
4778 | /* Allocate hardware IRQ controller */ |
4779 | ppc6xx_irq_init(env); | |
3fc6c082 FB |
4780 | } |
4781 | ||
7856e3a4 AF |
4782 | POWERPC_FAMILY(601)(ObjectClass *oc, void *data) |
4783 | { | |
ca5dff0a | 4784 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4785 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4786 | ||
ca5dff0a | 4787 | dc->desc = "PowerPC 601"; |
7856e3a4 AF |
4788 | pcc->init_proc = init_proc_601; |
4789 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
4790 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | |
4791 | PPC_FLOAT | | |
4792 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4793 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | | |
4794 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
4795 | pcc->msr_mask = 0x000000000000FD70ULL; |
4796 | pcc->mmu_model = POWERPC_MMU_601; | |
b632a148 DG |
4797 | #if defined(CONFIG_SOFTMMU) |
4798 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
4799 | #endif | |
ba9fd9f1 AF |
4800 | pcc->excp_model = POWERPC_EXCP_601; |
4801 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4802 | pcc->bfd_mach = bfd_mach_ppc_601; | |
4803 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; | |
7856e3a4 AF |
4804 | } |
4805 | ||
082c6681 | 4806 | #define POWERPC_MSRR_601v (0x0000000000001040ULL) |
082c6681 JM |
4807 | |
4808 | static void init_proc_601v (CPUPPCState *env) | |
4809 | { | |
4810 | init_proc_601(env); | |
4811 | /* XXX : not implemented */ | |
4812 | spr_register(env, SPR_601_HID15, "HID15", | |
4813 | SPR_NOACCESS, SPR_NOACCESS, | |
4814 | &spr_read_generic, &spr_write_generic, | |
4815 | 0x00000000); | |
4816 | } | |
4817 | ||
7856e3a4 AF |
4818 | POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) |
4819 | { | |
ca5dff0a | 4820 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4821 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4822 | ||
ca5dff0a | 4823 | dc->desc = "PowerPC 601v"; |
7856e3a4 AF |
4824 | pcc->init_proc = init_proc_601v; |
4825 | pcc->check_pow = check_pow_none; | |
53116ebf AF |
4826 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | |
4827 | PPC_FLOAT | | |
4828 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4829 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | | |
4830 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
4831 | pcc->msr_mask = 0x000000000000FD70ULL; |
4832 | pcc->mmu_model = POWERPC_MMU_601; | |
b632a148 DG |
4833 | #if defined(CONFIG_SOFTMMU) |
4834 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
4835 | #endif | |
ba9fd9f1 AF |
4836 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; |
4837 | pcc->bfd_mach = bfd_mach_ppc_601; | |
4838 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; | |
7856e3a4 AF |
4839 | } |
4840 | ||
a750fc0b | 4841 | static void init_proc_602 (CPUPPCState *env) |
3fc6c082 | 4842 | { |
a750fc0b JM |
4843 | gen_spr_ne_601(env); |
4844 | gen_spr_602(env); | |
4845 | /* Time base */ | |
4846 | gen_tbl(env); | |
4847 | /* hardware implementation registers */ | |
4848 | /* XXX : not implemented */ | |
4849 | spr_register(env, SPR_HID0, "HID0", | |
4850 | SPR_NOACCESS, SPR_NOACCESS, | |
4851 | &spr_read_generic, &spr_write_generic, | |
4852 | 0x00000000); | |
4853 | /* XXX : not implemented */ | |
4854 | spr_register(env, SPR_HID1, "HID1", | |
4855 | SPR_NOACCESS, SPR_NOACCESS, | |
4856 | &spr_read_generic, &spr_write_generic, | |
4857 | 0x00000000); | |
4858 | /* Memory management */ | |
4859 | gen_low_BATs(env); | |
4860 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
e1833e1f | 4861 | init_excp_602(env); |
d63001d1 JM |
4862 | env->dcache_line_size = 32; |
4863 | env->icache_line_size = 32; | |
a750fc0b JM |
4864 | /* Allocate hardware IRQ controller */ |
4865 | ppc6xx_irq_init(env); | |
4866 | } | |
3fc6c082 | 4867 | |
7856e3a4 AF |
4868 | POWERPC_FAMILY(602)(ObjectClass *oc, void *data) |
4869 | { | |
ca5dff0a | 4870 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4871 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4872 | ||
ca5dff0a | 4873 | dc->desc = "PowerPC 602"; |
7856e3a4 AF |
4874 | pcc->init_proc = init_proc_602; |
4875 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4876 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
4877 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
4878 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
4879 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4880 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
4881 | PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | | |
4882 | PPC_SEGMENT | PPC_602_SPEC; | |
ba9fd9f1 AF |
4883 | pcc->msr_mask = 0x0000000000C7FF73ULL; |
4884 | /* XXX: 602 MMU is quite specific. Should add a special case */ | |
4885 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; | |
4886 | pcc->excp_model = POWERPC_EXCP_602; | |
4887 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4888 | pcc->bfd_mach = bfd_mach_ppc_602; | |
4889 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
4890 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4891 | } |
4892 | ||
a750fc0b JM |
4893 | static void init_proc_603 (CPUPPCState *env) |
4894 | { | |
4895 | gen_spr_ne_601(env); | |
4896 | gen_spr_603(env); | |
4897 | /* Time base */ | |
4898 | gen_tbl(env); | |
4899 | /* hardware implementation registers */ | |
4900 | /* XXX : not implemented */ | |
4901 | spr_register(env, SPR_HID0, "HID0", | |
4902 | SPR_NOACCESS, SPR_NOACCESS, | |
4903 | &spr_read_generic, &spr_write_generic, | |
4904 | 0x00000000); | |
4905 | /* XXX : not implemented */ | |
4906 | spr_register(env, SPR_HID1, "HID1", | |
4907 | SPR_NOACCESS, SPR_NOACCESS, | |
4908 | &spr_read_generic, &spr_write_generic, | |
4909 | 0x00000000); | |
4910 | /* Memory management */ | |
4911 | gen_low_BATs(env); | |
4912 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
e1833e1f | 4913 | init_excp_603(env); |
d63001d1 JM |
4914 | env->dcache_line_size = 32; |
4915 | env->icache_line_size = 32; | |
a750fc0b JM |
4916 | /* Allocate hardware IRQ controller */ |
4917 | ppc6xx_irq_init(env); | |
3fc6c082 FB |
4918 | } |
4919 | ||
7856e3a4 AF |
4920 | POWERPC_FAMILY(603)(ObjectClass *oc, void *data) |
4921 | { | |
ca5dff0a | 4922 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4923 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4924 | ||
ca5dff0a | 4925 | dc->desc = "PowerPC 603"; |
7856e3a4 AF |
4926 | pcc->init_proc = init_proc_603; |
4927 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4928 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
4929 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
4930 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
4931 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4932 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
4933 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
4934 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
4935 | pcc->msr_mask = 0x000000000007FF73ULL; |
4936 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; | |
4937 | pcc->excp_model = POWERPC_EXCP_603; | |
4938 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4939 | pcc->bfd_mach = bfd_mach_ppc_603; | |
4940 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
4941 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4942 | } |
4943 | ||
a750fc0b JM |
4944 | static void init_proc_603E (CPUPPCState *env) |
4945 | { | |
4946 | gen_spr_ne_601(env); | |
4947 | gen_spr_603(env); | |
4948 | /* Time base */ | |
4949 | gen_tbl(env); | |
4950 | /* hardware implementation registers */ | |
4951 | /* XXX : not implemented */ | |
4952 | spr_register(env, SPR_HID0, "HID0", | |
4953 | SPR_NOACCESS, SPR_NOACCESS, | |
4954 | &spr_read_generic, &spr_write_generic, | |
4955 | 0x00000000); | |
4956 | /* XXX : not implemented */ | |
4957 | spr_register(env, SPR_HID1, "HID1", | |
4958 | SPR_NOACCESS, SPR_NOACCESS, | |
4959 | &spr_read_generic, &spr_write_generic, | |
4960 | 0x00000000); | |
a750fc0b JM |
4961 | /* Memory management */ |
4962 | gen_low_BATs(env); | |
4963 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
e1833e1f | 4964 | init_excp_603(env); |
d63001d1 JM |
4965 | env->dcache_line_size = 32; |
4966 | env->icache_line_size = 32; | |
a750fc0b JM |
4967 | /* Allocate hardware IRQ controller */ |
4968 | ppc6xx_irq_init(env); | |
4969 | } | |
4970 | ||
7856e3a4 AF |
4971 | POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) |
4972 | { | |
ca5dff0a | 4973 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
4974 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
4975 | ||
ca5dff0a | 4976 | dc->desc = "PowerPC 603e"; |
7856e3a4 AF |
4977 | pcc->init_proc = init_proc_603E; |
4978 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
4979 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
4980 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
4981 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
4982 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
4983 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
4984 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
4985 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
4986 | pcc->msr_mask = 0x000000000007FF73ULL; |
4987 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; | |
4988 | pcc->excp_model = POWERPC_EXCP_603E; | |
4989 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
4990 | pcc->bfd_mach = bfd_mach_ppc_ec603e; | |
4991 | pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | | |
4992 | POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
4993 | } |
4994 | ||
a750fc0b JM |
4995 | static void init_proc_604 (CPUPPCState *env) |
4996 | { | |
4997 | gen_spr_ne_601(env); | |
4998 | gen_spr_604(env); | |
4999 | /* Time base */ | |
5000 | gen_tbl(env); | |
5001 | /* Hardware implementation registers */ | |
5002 | /* XXX : not implemented */ | |
082c6681 JM |
5003 | spr_register(env, SPR_HID0, "HID0", |
5004 | SPR_NOACCESS, SPR_NOACCESS, | |
5005 | &spr_read_generic, &spr_write_generic, | |
5006 | 0x00000000); | |
5007 | /* Memory management */ | |
5008 | gen_low_BATs(env); | |
5009 | init_excp_604(env); | |
5010 | env->dcache_line_size = 32; | |
5011 | env->icache_line_size = 32; | |
5012 | /* Allocate hardware IRQ controller */ | |
5013 | ppc6xx_irq_init(env); | |
5014 | } | |
5015 | ||
7856e3a4 AF |
5016 | POWERPC_FAMILY(604)(ObjectClass *oc, void *data) |
5017 | { | |
ca5dff0a | 5018 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5019 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5020 | ||
ca5dff0a | 5021 | dc->desc = "PowerPC 604"; |
7856e3a4 AF |
5022 | pcc->init_proc = init_proc_604; |
5023 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
5024 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5025 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5026 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5027 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5028 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5029 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5030 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5031 | pcc->msr_mask = 0x000000000005FF77ULL; |
5032 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5033 | #if defined(CONFIG_SOFTMMU) |
5034 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5035 | #endif | |
ba9fd9f1 AF |
5036 | pcc->excp_model = POWERPC_EXCP_604; |
5037 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5038 | pcc->bfd_mach = bfd_mach_ppc_604; | |
5039 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5040 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5041 | } |
5042 | ||
082c6681 JM |
5043 | static void init_proc_604E (CPUPPCState *env) |
5044 | { | |
5045 | gen_spr_ne_601(env); | |
5046 | gen_spr_604(env); | |
5047 | /* XXX : not implemented */ | |
5048 | spr_register(env, SPR_MMCR1, "MMCR1", | |
5049 | SPR_NOACCESS, SPR_NOACCESS, | |
5050 | &spr_read_generic, &spr_write_generic, | |
5051 | 0x00000000); | |
5052 | /* XXX : not implemented */ | |
5053 | spr_register(env, SPR_PMC3, "PMC3", | |
5054 | SPR_NOACCESS, SPR_NOACCESS, | |
5055 | &spr_read_generic, &spr_write_generic, | |
5056 | 0x00000000); | |
5057 | /* XXX : not implemented */ | |
5058 | spr_register(env, SPR_PMC4, "PMC4", | |
5059 | SPR_NOACCESS, SPR_NOACCESS, | |
5060 | &spr_read_generic, &spr_write_generic, | |
5061 | 0x00000000); | |
5062 | /* Time base */ | |
5063 | gen_tbl(env); | |
5064 | /* Hardware implementation registers */ | |
5065 | /* XXX : not implemented */ | |
a750fc0b JM |
5066 | spr_register(env, SPR_HID0, "HID0", |
5067 | SPR_NOACCESS, SPR_NOACCESS, | |
5068 | &spr_read_generic, &spr_write_generic, | |
5069 | 0x00000000); | |
5070 | /* XXX : not implemented */ | |
5071 | spr_register(env, SPR_HID1, "HID1", | |
5072 | SPR_NOACCESS, SPR_NOACCESS, | |
5073 | &spr_read_generic, &spr_write_generic, | |
5074 | 0x00000000); | |
5075 | /* Memory management */ | |
5076 | gen_low_BATs(env); | |
e1833e1f | 5077 | init_excp_604(env); |
d63001d1 JM |
5078 | env->dcache_line_size = 32; |
5079 | env->icache_line_size = 32; | |
a750fc0b JM |
5080 | /* Allocate hardware IRQ controller */ |
5081 | ppc6xx_irq_init(env); | |
5082 | } | |
5083 | ||
7856e3a4 AF |
5084 | POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) |
5085 | { | |
ca5dff0a | 5086 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5087 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5088 | ||
ca5dff0a | 5089 | dc->desc = "PowerPC 604E"; |
7856e3a4 AF |
5090 | pcc->init_proc = init_proc_604E; |
5091 | pcc->check_pow = check_pow_nocheck; | |
53116ebf AF |
5092 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5093 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5094 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5095 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5096 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5097 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5098 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5099 | pcc->msr_mask = 0x000000000005FF77ULL; |
5100 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5101 | #if defined(CONFIG_SOFTMMU) |
5102 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5103 | #endif | |
ba9fd9f1 AF |
5104 | pcc->excp_model = POWERPC_EXCP_604; |
5105 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5106 | pcc->bfd_mach = bfd_mach_ppc_604; | |
5107 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5108 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5109 | } |
5110 | ||
bd928eba | 5111 | static void init_proc_740 (CPUPPCState *env) |
a750fc0b JM |
5112 | { |
5113 | gen_spr_ne_601(env); | |
5114 | gen_spr_7xx(env); | |
5115 | /* Time base */ | |
5116 | gen_tbl(env); | |
5117 | /* Thermal management */ | |
5118 | gen_spr_thrm(env); | |
5119 | /* Hardware implementation registers */ | |
5120 | /* XXX : not implemented */ | |
5121 | spr_register(env, SPR_HID0, "HID0", | |
5122 | SPR_NOACCESS, SPR_NOACCESS, | |
5123 | &spr_read_generic, &spr_write_generic, | |
5124 | 0x00000000); | |
5125 | /* XXX : not implemented */ | |
5126 | spr_register(env, SPR_HID1, "HID1", | |
5127 | SPR_NOACCESS, SPR_NOACCESS, | |
5128 | &spr_read_generic, &spr_write_generic, | |
5129 | 0x00000000); | |
5130 | /* Memory management */ | |
5131 | gen_low_BATs(env); | |
e1833e1f | 5132 | init_excp_7x0(env); |
d63001d1 JM |
5133 | env->dcache_line_size = 32; |
5134 | env->icache_line_size = 32; | |
a750fc0b JM |
5135 | /* Allocate hardware IRQ controller */ |
5136 | ppc6xx_irq_init(env); | |
5137 | } | |
5138 | ||
7856e3a4 AF |
5139 | POWERPC_FAMILY(740)(ObjectClass *oc, void *data) |
5140 | { | |
ca5dff0a | 5141 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5142 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5143 | ||
ca5dff0a | 5144 | dc->desc = "PowerPC 740"; |
7856e3a4 AF |
5145 | pcc->init_proc = init_proc_740; |
5146 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5147 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5148 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5149 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5150 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5151 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5152 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5153 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5154 | pcc->msr_mask = 0x000000000005FF77ULL; |
5155 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5156 | #if defined(CONFIG_SOFTMMU) |
5157 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5158 | #endif | |
ba9fd9f1 AF |
5159 | pcc->excp_model = POWERPC_EXCP_7x0; |
5160 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5161 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5162 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5163 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5164 | } |
5165 | ||
bd928eba JM |
5166 | static void init_proc_750 (CPUPPCState *env) |
5167 | { | |
5168 | gen_spr_ne_601(env); | |
5169 | gen_spr_7xx(env); | |
5170 | /* XXX : not implemented */ | |
5171 | spr_register(env, SPR_L2CR, "L2CR", | |
5172 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 5173 | &spr_read_generic, NULL, |
bd928eba JM |
5174 | 0x00000000); |
5175 | /* Time base */ | |
5176 | gen_tbl(env); | |
5177 | /* Thermal management */ | |
5178 | gen_spr_thrm(env); | |
5179 | /* Hardware implementation registers */ | |
5180 | /* XXX : not implemented */ | |
5181 | spr_register(env, SPR_HID0, "HID0", | |
5182 | SPR_NOACCESS, SPR_NOACCESS, | |
5183 | &spr_read_generic, &spr_write_generic, | |
5184 | 0x00000000); | |
5185 | /* XXX : not implemented */ | |
5186 | spr_register(env, SPR_HID1, "HID1", | |
5187 | SPR_NOACCESS, SPR_NOACCESS, | |
5188 | &spr_read_generic, &spr_write_generic, | |
5189 | 0x00000000); | |
5190 | /* Memory management */ | |
5191 | gen_low_BATs(env); | |
5192 | /* XXX: high BATs are also present but are known to be bugged on | |
5193 | * die version 1.x | |
5194 | */ | |
5195 | init_excp_7x0(env); | |
5196 | env->dcache_line_size = 32; | |
5197 | env->icache_line_size = 32; | |
5198 | /* Allocate hardware IRQ controller */ | |
5199 | ppc6xx_irq_init(env); | |
5200 | } | |
5201 | ||
7856e3a4 AF |
5202 | POWERPC_FAMILY(750)(ObjectClass *oc, void *data) |
5203 | { | |
ca5dff0a | 5204 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5205 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5206 | ||
ca5dff0a | 5207 | dc->desc = "PowerPC 750"; |
7856e3a4 AF |
5208 | pcc->init_proc = init_proc_750; |
5209 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5210 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5211 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5212 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5213 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5214 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5215 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5216 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5217 | pcc->msr_mask = 0x000000000005FF77ULL; |
5218 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5219 | #if defined(CONFIG_SOFTMMU) |
5220 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5221 | #endif | |
ba9fd9f1 AF |
5222 | pcc->excp_model = POWERPC_EXCP_7x0; |
5223 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5224 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5225 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5226 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5227 | } |
5228 | ||
bd928eba JM |
5229 | static void init_proc_750cl (CPUPPCState *env) |
5230 | { | |
5231 | gen_spr_ne_601(env); | |
5232 | gen_spr_7xx(env); | |
5233 | /* XXX : not implemented */ | |
5234 | spr_register(env, SPR_L2CR, "L2CR", | |
5235 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 5236 | &spr_read_generic, NULL, |
bd928eba JM |
5237 | 0x00000000); |
5238 | /* Time base */ | |
5239 | gen_tbl(env); | |
5240 | /* Thermal management */ | |
5241 | /* Those registers are fake on 750CL */ | |
5242 | spr_register(env, SPR_THRM1, "THRM1", | |
5243 | SPR_NOACCESS, SPR_NOACCESS, | |
5244 | &spr_read_generic, &spr_write_generic, | |
5245 | 0x00000000); | |
5246 | spr_register(env, SPR_THRM2, "THRM2", | |
5247 | SPR_NOACCESS, SPR_NOACCESS, | |
5248 | &spr_read_generic, &spr_write_generic, | |
5249 | 0x00000000); | |
5250 | spr_register(env, SPR_THRM3, "THRM3", | |
5251 | SPR_NOACCESS, SPR_NOACCESS, | |
5252 | &spr_read_generic, &spr_write_generic, | |
5253 | 0x00000000); | |
5254 | /* XXX: not implemented */ | |
5255 | spr_register(env, SPR_750_TDCL, "TDCL", | |
5256 | SPR_NOACCESS, SPR_NOACCESS, | |
5257 | &spr_read_generic, &spr_write_generic, | |
5258 | 0x00000000); | |
5259 | spr_register(env, SPR_750_TDCH, "TDCH", | |
5260 | SPR_NOACCESS, SPR_NOACCESS, | |
5261 | &spr_read_generic, &spr_write_generic, | |
5262 | 0x00000000); | |
5263 | /* DMA */ | |
5264 | /* XXX : not implemented */ | |
5265 | spr_register(env, SPR_750_WPAR, "WPAR", | |
5266 | SPR_NOACCESS, SPR_NOACCESS, | |
5267 | &spr_read_generic, &spr_write_generic, | |
5268 | 0x00000000); | |
5269 | spr_register(env, SPR_750_DMAL, "DMAL", | |
5270 | SPR_NOACCESS, SPR_NOACCESS, | |
5271 | &spr_read_generic, &spr_write_generic, | |
5272 | 0x00000000); | |
5273 | spr_register(env, SPR_750_DMAU, "DMAU", | |
5274 | SPR_NOACCESS, SPR_NOACCESS, | |
5275 | &spr_read_generic, &spr_write_generic, | |
5276 | 0x00000000); | |
5277 | /* Hardware implementation registers */ | |
5278 | /* XXX : not implemented */ | |
5279 | spr_register(env, SPR_HID0, "HID0", | |
5280 | SPR_NOACCESS, SPR_NOACCESS, | |
5281 | &spr_read_generic, &spr_write_generic, | |
5282 | 0x00000000); | |
5283 | /* XXX : not implemented */ | |
5284 | spr_register(env, SPR_HID1, "HID1", | |
5285 | SPR_NOACCESS, SPR_NOACCESS, | |
5286 | &spr_read_generic, &spr_write_generic, | |
5287 | 0x00000000); | |
5288 | /* XXX : not implemented */ | |
5289 | spr_register(env, SPR_750CL_HID2, "HID2", | |
5290 | SPR_NOACCESS, SPR_NOACCESS, | |
5291 | &spr_read_generic, &spr_write_generic, | |
5292 | 0x00000000); | |
5293 | /* XXX : not implemented */ | |
5294 | spr_register(env, SPR_750CL_HID4, "HID4", | |
5295 | SPR_NOACCESS, SPR_NOACCESS, | |
5296 | &spr_read_generic, &spr_write_generic, | |
5297 | 0x00000000); | |
5298 | /* Quantization registers */ | |
5299 | /* XXX : not implemented */ | |
5300 | spr_register(env, SPR_750_GQR0, "GQR0", | |
5301 | SPR_NOACCESS, SPR_NOACCESS, | |
5302 | &spr_read_generic, &spr_write_generic, | |
5303 | 0x00000000); | |
5304 | /* XXX : not implemented */ | |
5305 | spr_register(env, SPR_750_GQR1, "GQR1", | |
5306 | SPR_NOACCESS, SPR_NOACCESS, | |
5307 | &spr_read_generic, &spr_write_generic, | |
5308 | 0x00000000); | |
5309 | /* XXX : not implemented */ | |
5310 | spr_register(env, SPR_750_GQR2, "GQR2", | |
5311 | SPR_NOACCESS, SPR_NOACCESS, | |
5312 | &spr_read_generic, &spr_write_generic, | |
5313 | 0x00000000); | |
5314 | /* XXX : not implemented */ | |
5315 | spr_register(env, SPR_750_GQR3, "GQR3", | |
5316 | SPR_NOACCESS, SPR_NOACCESS, | |
5317 | &spr_read_generic, &spr_write_generic, | |
5318 | 0x00000000); | |
5319 | /* XXX : not implemented */ | |
5320 | spr_register(env, SPR_750_GQR4, "GQR4", | |
5321 | SPR_NOACCESS, SPR_NOACCESS, | |
5322 | &spr_read_generic, &spr_write_generic, | |
5323 | 0x00000000); | |
5324 | /* XXX : not implemented */ | |
5325 | spr_register(env, SPR_750_GQR5, "GQR5", | |
5326 | SPR_NOACCESS, SPR_NOACCESS, | |
5327 | &spr_read_generic, &spr_write_generic, | |
5328 | 0x00000000); | |
5329 | /* XXX : not implemented */ | |
5330 | spr_register(env, SPR_750_GQR6, "GQR6", | |
5331 | SPR_NOACCESS, SPR_NOACCESS, | |
5332 | &spr_read_generic, &spr_write_generic, | |
5333 | 0x00000000); | |
5334 | /* XXX : not implemented */ | |
5335 | spr_register(env, SPR_750_GQR7, "GQR7", | |
5336 | SPR_NOACCESS, SPR_NOACCESS, | |
5337 | &spr_read_generic, &spr_write_generic, | |
5338 | 0x00000000); | |
5339 | /* Memory management */ | |
5340 | gen_low_BATs(env); | |
5341 | /* PowerPC 750cl has 8 DBATs and 8 IBATs */ | |
5342 | gen_high_BATs(env); | |
5343 | init_excp_750cl(env); | |
5344 | env->dcache_line_size = 32; | |
5345 | env->icache_line_size = 32; | |
5346 | /* Allocate hardware IRQ controller */ | |
5347 | ppc6xx_irq_init(env); | |
5348 | } | |
5349 | ||
7856e3a4 AF |
5350 | POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) |
5351 | { | |
ca5dff0a | 5352 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5353 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5354 | ||
ca5dff0a | 5355 | dc->desc = "PowerPC 750 CL"; |
7856e3a4 AF |
5356 | pcc->init_proc = init_proc_750cl; |
5357 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5358 | /* XXX: not implemented: |
5359 | * cache lock instructions: | |
5360 | * dcbz_l | |
5361 | * floating point paired instructions | |
5362 | * psq_lux | |
5363 | * psq_lx | |
5364 | * psq_stux | |
5365 | * psq_stx | |
5366 | * ps_abs | |
5367 | * ps_add | |
5368 | * ps_cmpo0 | |
5369 | * ps_cmpo1 | |
5370 | * ps_cmpu0 | |
5371 | * ps_cmpu1 | |
5372 | * ps_div | |
5373 | * ps_madd | |
5374 | * ps_madds0 | |
5375 | * ps_madds1 | |
5376 | * ps_merge00 | |
5377 | * ps_merge01 | |
5378 | * ps_merge10 | |
5379 | * ps_merge11 | |
5380 | * ps_mr | |
5381 | * ps_msub | |
5382 | * ps_mul | |
5383 | * ps_muls0 | |
5384 | * ps_muls1 | |
5385 | * ps_nabs | |
5386 | * ps_neg | |
5387 | * ps_nmadd | |
5388 | * ps_nmsub | |
5389 | * ps_res | |
5390 | * ps_rsqrte | |
5391 | * ps_sel | |
5392 | * ps_sub | |
5393 | * ps_sum0 | |
5394 | * ps_sum1 | |
5395 | */ | |
5396 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | | |
5397 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5398 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5399 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5400 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5401 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5402 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5403 | pcc->msr_mask = 0x000000000005FF77ULL; |
5404 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5405 | #if defined(CONFIG_SOFTMMU) |
5406 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5407 | #endif | |
ba9fd9f1 AF |
5408 | pcc->excp_model = POWERPC_EXCP_7x0; |
5409 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5410 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5411 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5412 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5413 | } |
5414 | ||
bd928eba JM |
5415 | static void init_proc_750cx (CPUPPCState *env) |
5416 | { | |
5417 | gen_spr_ne_601(env); | |
5418 | gen_spr_7xx(env); | |
5419 | /* XXX : not implemented */ | |
5420 | spr_register(env, SPR_L2CR, "L2CR", | |
5421 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 5422 | &spr_read_generic, NULL, |
bd928eba JM |
5423 | 0x00000000); |
5424 | /* Time base */ | |
5425 | gen_tbl(env); | |
5426 | /* Thermal management */ | |
5427 | gen_spr_thrm(env); | |
5428 | /* This register is not implemented but is present for compatibility */ | |
5429 | spr_register(env, SPR_SDA, "SDA", | |
5430 | SPR_NOACCESS, SPR_NOACCESS, | |
5431 | &spr_read_generic, &spr_write_generic, | |
5432 | 0x00000000); | |
5433 | /* Hardware implementation registers */ | |
5434 | /* XXX : not implemented */ | |
5435 | spr_register(env, SPR_HID0, "HID0", | |
5436 | SPR_NOACCESS, SPR_NOACCESS, | |
5437 | &spr_read_generic, &spr_write_generic, | |
5438 | 0x00000000); | |
5439 | /* XXX : not implemented */ | |
5440 | spr_register(env, SPR_HID1, "HID1", | |
5441 | SPR_NOACCESS, SPR_NOACCESS, | |
5442 | &spr_read_generic, &spr_write_generic, | |
5443 | 0x00000000); | |
5444 | /* Memory management */ | |
5445 | gen_low_BATs(env); | |
4e777442 JM |
5446 | /* PowerPC 750cx has 8 DBATs and 8 IBATs */ |
5447 | gen_high_BATs(env); | |
bd928eba JM |
5448 | init_excp_750cx(env); |
5449 | env->dcache_line_size = 32; | |
5450 | env->icache_line_size = 32; | |
5451 | /* Allocate hardware IRQ controller */ | |
5452 | ppc6xx_irq_init(env); | |
5453 | } | |
5454 | ||
7856e3a4 AF |
5455 | POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) |
5456 | { | |
ca5dff0a | 5457 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5458 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5459 | ||
ca5dff0a | 5460 | dc->desc = "PowerPC 750CX"; |
7856e3a4 AF |
5461 | pcc->init_proc = init_proc_750cx; |
5462 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5463 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5464 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5465 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5466 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5467 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5468 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5469 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5470 | pcc->msr_mask = 0x000000000005FF77ULL; |
5471 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5472 | #if defined(CONFIG_SOFTMMU) |
5473 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5474 | #endif | |
ba9fd9f1 AF |
5475 | pcc->excp_model = POWERPC_EXCP_7x0; |
5476 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5477 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5478 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5479 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5480 | } |
5481 | ||
a750fc0b JM |
5482 | static void init_proc_750fx (CPUPPCState *env) |
5483 | { | |
5484 | gen_spr_ne_601(env); | |
5485 | gen_spr_7xx(env); | |
bd928eba JM |
5486 | /* XXX : not implemented */ |
5487 | spr_register(env, SPR_L2CR, "L2CR", | |
5488 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 5489 | &spr_read_generic, NULL, |
bd928eba | 5490 | 0x00000000); |
a750fc0b JM |
5491 | /* Time base */ |
5492 | gen_tbl(env); | |
5493 | /* Thermal management */ | |
5494 | gen_spr_thrm(env); | |
bd928eba JM |
5495 | /* XXX : not implemented */ |
5496 | spr_register(env, SPR_750_THRM4, "THRM4", | |
5497 | SPR_NOACCESS, SPR_NOACCESS, | |
5498 | &spr_read_generic, &spr_write_generic, | |
5499 | 0x00000000); | |
a750fc0b JM |
5500 | /* Hardware implementation registers */ |
5501 | /* XXX : not implemented */ | |
5502 | spr_register(env, SPR_HID0, "HID0", | |
5503 | SPR_NOACCESS, SPR_NOACCESS, | |
5504 | &spr_read_generic, &spr_write_generic, | |
5505 | 0x00000000); | |
5506 | /* XXX : not implemented */ | |
5507 | spr_register(env, SPR_HID1, "HID1", | |
5508 | SPR_NOACCESS, SPR_NOACCESS, | |
5509 | &spr_read_generic, &spr_write_generic, | |
5510 | 0x00000000); | |
5511 | /* XXX : not implemented */ | |
bd928eba | 5512 | spr_register(env, SPR_750FX_HID2, "HID2", |
a750fc0b JM |
5513 | SPR_NOACCESS, SPR_NOACCESS, |
5514 | &spr_read_generic, &spr_write_generic, | |
5515 | 0x00000000); | |
5516 | /* Memory management */ | |
5517 | gen_low_BATs(env); | |
5518 | /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ | |
5519 | gen_high_BATs(env); | |
bd928eba | 5520 | init_excp_7x0(env); |
d63001d1 JM |
5521 | env->dcache_line_size = 32; |
5522 | env->icache_line_size = 32; | |
a750fc0b JM |
5523 | /* Allocate hardware IRQ controller */ |
5524 | ppc6xx_irq_init(env); | |
5525 | } | |
5526 | ||
7856e3a4 AF |
5527 | POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) |
5528 | { | |
ca5dff0a | 5529 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5530 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5531 | ||
ca5dff0a | 5532 | dc->desc = "PowerPC 750FX"; |
7856e3a4 AF |
5533 | pcc->init_proc = init_proc_750fx; |
5534 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5535 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5536 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5537 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5538 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5539 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5540 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5541 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5542 | pcc->msr_mask = 0x000000000005FF77ULL; |
5543 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5544 | #if defined(CONFIG_SOFTMMU) |
5545 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5546 | #endif | |
ba9fd9f1 AF |
5547 | pcc->excp_model = POWERPC_EXCP_7x0; |
5548 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5549 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5550 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5551 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5552 | } |
5553 | ||
bd928eba JM |
5554 | static void init_proc_750gx (CPUPPCState *env) |
5555 | { | |
5556 | gen_spr_ne_601(env); | |
5557 | gen_spr_7xx(env); | |
5558 | /* XXX : not implemented (XXX: different from 750fx) */ | |
5559 | spr_register(env, SPR_L2CR, "L2CR", | |
5560 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 5561 | &spr_read_generic, NULL, |
bd928eba JM |
5562 | 0x00000000); |
5563 | /* Time base */ | |
5564 | gen_tbl(env); | |
5565 | /* Thermal management */ | |
5566 | gen_spr_thrm(env); | |
5567 | /* XXX : not implemented */ | |
5568 | spr_register(env, SPR_750_THRM4, "THRM4", | |
5569 | SPR_NOACCESS, SPR_NOACCESS, | |
5570 | &spr_read_generic, &spr_write_generic, | |
5571 | 0x00000000); | |
5572 | /* Hardware implementation registers */ | |
5573 | /* XXX : not implemented (XXX: different from 750fx) */ | |
5574 | spr_register(env, SPR_HID0, "HID0", | |
5575 | SPR_NOACCESS, SPR_NOACCESS, | |
5576 | &spr_read_generic, &spr_write_generic, | |
5577 | 0x00000000); | |
5578 | /* XXX : not implemented */ | |
5579 | spr_register(env, SPR_HID1, "HID1", | |
5580 | SPR_NOACCESS, SPR_NOACCESS, | |
5581 | &spr_read_generic, &spr_write_generic, | |
5582 | 0x00000000); | |
5583 | /* XXX : not implemented (XXX: different from 750fx) */ | |
5584 | spr_register(env, SPR_750FX_HID2, "HID2", | |
5585 | SPR_NOACCESS, SPR_NOACCESS, | |
5586 | &spr_read_generic, &spr_write_generic, | |
5587 | 0x00000000); | |
5588 | /* Memory management */ | |
5589 | gen_low_BATs(env); | |
5590 | /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ | |
5591 | gen_high_BATs(env); | |
5592 | init_excp_7x0(env); | |
5593 | env->dcache_line_size = 32; | |
5594 | env->icache_line_size = 32; | |
5595 | /* Allocate hardware IRQ controller */ | |
5596 | ppc6xx_irq_init(env); | |
5597 | } | |
5598 | ||
7856e3a4 AF |
5599 | POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) |
5600 | { | |
ca5dff0a | 5601 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5602 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5603 | ||
ca5dff0a | 5604 | dc->desc = "PowerPC 750GX"; |
7856e3a4 AF |
5605 | pcc->init_proc = init_proc_750gx; |
5606 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5607 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5608 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5609 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5610 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5611 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5612 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5613 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5614 | pcc->msr_mask = 0x000000000005FF77ULL; |
5615 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5616 | #if defined(CONFIG_SOFTMMU) |
5617 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5618 | #endif | |
ba9fd9f1 AF |
5619 | pcc->excp_model = POWERPC_EXCP_7x0; |
5620 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5621 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5622 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5623 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5624 | } |
5625 | ||
bd928eba JM |
5626 | static void init_proc_745 (CPUPPCState *env) |
5627 | { | |
5628 | gen_spr_ne_601(env); | |
5629 | gen_spr_7xx(env); | |
5630 | gen_spr_G2_755(env); | |
5631 | /* Time base */ | |
5632 | gen_tbl(env); | |
5633 | /* Thermal management */ | |
5634 | gen_spr_thrm(env); | |
5635 | /* Hardware implementation registers */ | |
5636 | /* XXX : not implemented */ | |
5637 | spr_register(env, SPR_HID0, "HID0", | |
5638 | SPR_NOACCESS, SPR_NOACCESS, | |
5639 | &spr_read_generic, &spr_write_generic, | |
5640 | 0x00000000); | |
5641 | /* XXX : not implemented */ | |
5642 | spr_register(env, SPR_HID1, "HID1", | |
5643 | SPR_NOACCESS, SPR_NOACCESS, | |
5644 | &spr_read_generic, &spr_write_generic, | |
5645 | 0x00000000); | |
5646 | /* XXX : not implemented */ | |
5647 | spr_register(env, SPR_HID2, "HID2", | |
5648 | SPR_NOACCESS, SPR_NOACCESS, | |
5649 | &spr_read_generic, &spr_write_generic, | |
5650 | 0x00000000); | |
5651 | /* Memory management */ | |
5652 | gen_low_BATs(env); | |
5653 | gen_high_BATs(env); | |
5654 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
5655 | init_excp_7x5(env); | |
5656 | env->dcache_line_size = 32; | |
5657 | env->icache_line_size = 32; | |
5658 | /* Allocate hardware IRQ controller */ | |
5659 | ppc6xx_irq_init(env); | |
5660 | } | |
5661 | ||
7856e3a4 AF |
5662 | POWERPC_FAMILY(745)(ObjectClass *oc, void *data) |
5663 | { | |
ca5dff0a | 5664 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5665 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5666 | ||
ca5dff0a | 5667 | dc->desc = "PowerPC 745"; |
7856e3a4 AF |
5668 | pcc->init_proc = init_proc_745; |
5669 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5670 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5671 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5672 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5673 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5674 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5675 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
5676 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5677 | pcc->msr_mask = 0x000000000005FF77ULL; |
5678 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; | |
5679 | pcc->excp_model = POWERPC_EXCP_7x5; | |
5680 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5681 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5682 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5683 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5684 | } |
5685 | ||
bd928eba | 5686 | static void init_proc_755 (CPUPPCState *env) |
a750fc0b JM |
5687 | { |
5688 | gen_spr_ne_601(env); | |
bd928eba | 5689 | gen_spr_7xx(env); |
a750fc0b JM |
5690 | gen_spr_G2_755(env); |
5691 | /* Time base */ | |
5692 | gen_tbl(env); | |
5693 | /* L2 cache control */ | |
5694 | /* XXX : not implemented */ | |
bd928eba | 5695 | spr_register(env, SPR_L2CR, "L2CR", |
a750fc0b | 5696 | SPR_NOACCESS, SPR_NOACCESS, |
2345f1c0 | 5697 | &spr_read_generic, NULL, |
a750fc0b JM |
5698 | 0x00000000); |
5699 | /* XXX : not implemented */ | |
5700 | spr_register(env, SPR_L2PMCR, "L2PMCR", | |
5701 | SPR_NOACCESS, SPR_NOACCESS, | |
5702 | &spr_read_generic, &spr_write_generic, | |
5703 | 0x00000000); | |
bd928eba JM |
5704 | /* Thermal management */ |
5705 | gen_spr_thrm(env); | |
a750fc0b JM |
5706 | /* Hardware implementation registers */ |
5707 | /* XXX : not implemented */ | |
5708 | spr_register(env, SPR_HID0, "HID0", | |
5709 | SPR_NOACCESS, SPR_NOACCESS, | |
5710 | &spr_read_generic, &spr_write_generic, | |
5711 | 0x00000000); | |
5712 | /* XXX : not implemented */ | |
5713 | spr_register(env, SPR_HID1, "HID1", | |
5714 | SPR_NOACCESS, SPR_NOACCESS, | |
5715 | &spr_read_generic, &spr_write_generic, | |
5716 | 0x00000000); | |
5717 | /* XXX : not implemented */ | |
5718 | spr_register(env, SPR_HID2, "HID2", | |
5719 | SPR_NOACCESS, SPR_NOACCESS, | |
5720 | &spr_read_generic, &spr_write_generic, | |
5721 | 0x00000000); | |
5722 | /* Memory management */ | |
5723 | gen_low_BATs(env); | |
5724 | gen_high_BATs(env); | |
5725 | gen_6xx_7xx_soft_tlb(env, 64, 2); | |
7a3a6927 | 5726 | init_excp_7x5(env); |
d63001d1 JM |
5727 | env->dcache_line_size = 32; |
5728 | env->icache_line_size = 32; | |
a750fc0b JM |
5729 | /* Allocate hardware IRQ controller */ |
5730 | ppc6xx_irq_init(env); | |
5731 | } | |
5732 | ||
7856e3a4 AF |
5733 | POWERPC_FAMILY(755)(ObjectClass *oc, void *data) |
5734 | { | |
ca5dff0a | 5735 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5736 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5737 | ||
ca5dff0a | 5738 | dc->desc = "PowerPC 755"; |
7856e3a4 AF |
5739 | pcc->init_proc = init_proc_755; |
5740 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5741 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5742 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5743 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | | |
5744 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
5745 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5746 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | | |
5747 | PPC_SEGMENT | PPC_EXTERN; | |
ba9fd9f1 AF |
5748 | pcc->msr_mask = 0x000000000005FF77ULL; |
5749 | pcc->mmu_model = POWERPC_MMU_SOFT_6xx; | |
5750 | pcc->excp_model = POWERPC_EXCP_7x5; | |
5751 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5752 | pcc->bfd_mach = bfd_mach_ppc_750; | |
5753 | pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | | |
5754 | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5755 | } |
5756 | ||
a750fc0b JM |
5757 | static void init_proc_7400 (CPUPPCState *env) |
5758 | { | |
5759 | gen_spr_ne_601(env); | |
5760 | gen_spr_7xx(env); | |
5761 | /* Time base */ | |
5762 | gen_tbl(env); | |
5763 | /* 74xx specific SPR */ | |
5764 | gen_spr_74xx(env); | |
4e777442 JM |
5765 | /* XXX : not implemented */ |
5766 | spr_register(env, SPR_UBAMR, "UBAMR", | |
5767 | &spr_read_ureg, SPR_NOACCESS, | |
5768 | &spr_read_ureg, SPR_NOACCESS, | |
5769 | 0x00000000); | |
5770 | /* XXX: this seems not implemented on all revisions. */ | |
5771 | /* XXX : not implemented */ | |
5772 | spr_register(env, SPR_MSSCR1, "MSSCR1", | |
5773 | SPR_NOACCESS, SPR_NOACCESS, | |
5774 | &spr_read_generic, &spr_write_generic, | |
5775 | 0x00000000); | |
a750fc0b JM |
5776 | /* Thermal management */ |
5777 | gen_spr_thrm(env); | |
5778 | /* Memory management */ | |
5779 | gen_low_BATs(env); | |
e1833e1f | 5780 | init_excp_7400(env); |
d63001d1 JM |
5781 | env->dcache_line_size = 32; |
5782 | env->icache_line_size = 32; | |
a750fc0b JM |
5783 | /* Allocate hardware IRQ controller */ |
5784 | ppc6xx_irq_init(env); | |
5785 | } | |
5786 | ||
7856e3a4 AF |
5787 | POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) |
5788 | { | |
ca5dff0a | 5789 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5790 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5791 | ||
ca5dff0a | 5792 | dc->desc = "PowerPC 7400 (aka G4)"; |
7856e3a4 AF |
5793 | pcc->init_proc = init_proc_7400; |
5794 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5795 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5796 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5797 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
5798 | PPC_FLOAT_STFIWX | | |
5799 | PPC_CACHE | PPC_CACHE_ICBI | | |
5800 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
5801 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5802 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5803 | PPC_MEM_TLBIA | | |
5804 | PPC_SEGMENT | PPC_EXTERN | | |
5805 | PPC_ALTIVEC; | |
ba9fd9f1 AF |
5806 | pcc->msr_mask = 0x000000000205FF77ULL; |
5807 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5808 | #if defined(CONFIG_SOFTMMU) |
5809 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5810 | #endif | |
ba9fd9f1 AF |
5811 | pcc->excp_model = POWERPC_EXCP_74xx; |
5812 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5813 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
5814 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
5815 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
5816 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5817 | } |
5818 | ||
a750fc0b JM |
5819 | static void init_proc_7410 (CPUPPCState *env) |
5820 | { | |
5821 | gen_spr_ne_601(env); | |
5822 | gen_spr_7xx(env); | |
5823 | /* Time base */ | |
5824 | gen_tbl(env); | |
5825 | /* 74xx specific SPR */ | |
5826 | gen_spr_74xx(env); | |
4e777442 JM |
5827 | /* XXX : not implemented */ |
5828 | spr_register(env, SPR_UBAMR, "UBAMR", | |
5829 | &spr_read_ureg, SPR_NOACCESS, | |
5830 | &spr_read_ureg, SPR_NOACCESS, | |
5831 | 0x00000000); | |
a750fc0b JM |
5832 | /* Thermal management */ |
5833 | gen_spr_thrm(env); | |
5834 | /* L2PMCR */ | |
5835 | /* XXX : not implemented */ | |
5836 | spr_register(env, SPR_L2PMCR, "L2PMCR", | |
5837 | SPR_NOACCESS, SPR_NOACCESS, | |
5838 | &spr_read_generic, &spr_write_generic, | |
5839 | 0x00000000); | |
5840 | /* LDSTDB */ | |
5841 | /* XXX : not implemented */ | |
5842 | spr_register(env, SPR_LDSTDB, "LDSTDB", | |
5843 | SPR_NOACCESS, SPR_NOACCESS, | |
5844 | &spr_read_generic, &spr_write_generic, | |
5845 | 0x00000000); | |
5846 | /* Memory management */ | |
5847 | gen_low_BATs(env); | |
e1833e1f | 5848 | init_excp_7400(env); |
d63001d1 JM |
5849 | env->dcache_line_size = 32; |
5850 | env->icache_line_size = 32; | |
a750fc0b JM |
5851 | /* Allocate hardware IRQ controller */ |
5852 | ppc6xx_irq_init(env); | |
5853 | } | |
5854 | ||
7856e3a4 AF |
5855 | POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) |
5856 | { | |
ca5dff0a | 5857 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5858 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5859 | ||
ca5dff0a | 5860 | dc->desc = "PowerPC 7410 (aka G4)"; |
7856e3a4 AF |
5861 | pcc->init_proc = init_proc_7410; |
5862 | pcc->check_pow = check_pow_hid0; | |
53116ebf AF |
5863 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5864 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5865 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
5866 | PPC_FLOAT_STFIWX | | |
5867 | PPC_CACHE | PPC_CACHE_ICBI | | |
5868 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
5869 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5870 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5871 | PPC_MEM_TLBIA | | |
5872 | PPC_SEGMENT | PPC_EXTERN | | |
5873 | PPC_ALTIVEC; | |
ba9fd9f1 AF |
5874 | pcc->msr_mask = 0x000000000205FF77ULL; |
5875 | pcc->mmu_model = POWERPC_MMU_32B; | |
b632a148 DG |
5876 | #if defined(CONFIG_SOFTMMU) |
5877 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
5878 | #endif | |
ba9fd9f1 AF |
5879 | pcc->excp_model = POWERPC_EXCP_74xx; |
5880 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5881 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
5882 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
5883 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
5884 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5885 | } |
5886 | ||
a750fc0b JM |
5887 | static void init_proc_7440 (CPUPPCState *env) |
5888 | { | |
5889 | gen_spr_ne_601(env); | |
5890 | gen_spr_7xx(env); | |
5891 | /* Time base */ | |
5892 | gen_tbl(env); | |
5893 | /* 74xx specific SPR */ | |
5894 | gen_spr_74xx(env); | |
4e777442 JM |
5895 | /* XXX : not implemented */ |
5896 | spr_register(env, SPR_UBAMR, "UBAMR", | |
5897 | &spr_read_ureg, SPR_NOACCESS, | |
5898 | &spr_read_ureg, SPR_NOACCESS, | |
5899 | 0x00000000); | |
a750fc0b JM |
5900 | /* LDSTCR */ |
5901 | /* XXX : not implemented */ | |
5902 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
5903 | SPR_NOACCESS, SPR_NOACCESS, | |
5904 | &spr_read_generic, &spr_write_generic, | |
5905 | 0x00000000); | |
5906 | /* ICTRL */ | |
5907 | /* XXX : not implemented */ | |
5908 | spr_register(env, SPR_ICTRL, "ICTRL", | |
5909 | SPR_NOACCESS, SPR_NOACCESS, | |
5910 | &spr_read_generic, &spr_write_generic, | |
5911 | 0x00000000); | |
5912 | /* MSSSR0 */ | |
578bb252 | 5913 | /* XXX : not implemented */ |
a750fc0b JM |
5914 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
5915 | SPR_NOACCESS, SPR_NOACCESS, | |
5916 | &spr_read_generic, &spr_write_generic, | |
5917 | 0x00000000); | |
5918 | /* PMC */ | |
5919 | /* XXX : not implemented */ | |
5920 | spr_register(env, SPR_PMC5, "PMC5", | |
5921 | SPR_NOACCESS, SPR_NOACCESS, | |
5922 | &spr_read_generic, &spr_write_generic, | |
5923 | 0x00000000); | |
578bb252 | 5924 | /* XXX : not implemented */ |
a750fc0b JM |
5925 | spr_register(env, SPR_UPMC5, "UPMC5", |
5926 | &spr_read_ureg, SPR_NOACCESS, | |
5927 | &spr_read_ureg, SPR_NOACCESS, | |
5928 | 0x00000000); | |
578bb252 | 5929 | /* XXX : not implemented */ |
a750fc0b JM |
5930 | spr_register(env, SPR_PMC6, "PMC6", |
5931 | SPR_NOACCESS, SPR_NOACCESS, | |
5932 | &spr_read_generic, &spr_write_generic, | |
5933 | 0x00000000); | |
578bb252 | 5934 | /* XXX : not implemented */ |
a750fc0b JM |
5935 | spr_register(env, SPR_UPMC6, "UPMC6", |
5936 | &spr_read_ureg, SPR_NOACCESS, | |
5937 | &spr_read_ureg, SPR_NOACCESS, | |
5938 | 0x00000000); | |
5939 | /* Memory management */ | |
5940 | gen_low_BATs(env); | |
578bb252 | 5941 | gen_74xx_soft_tlb(env, 128, 2); |
1c27f8fb | 5942 | init_excp_7450(env); |
d63001d1 JM |
5943 | env->dcache_line_size = 32; |
5944 | env->icache_line_size = 32; | |
a750fc0b JM |
5945 | /* Allocate hardware IRQ controller */ |
5946 | ppc6xx_irq_init(env); | |
5947 | } | |
a750fc0b | 5948 | |
7856e3a4 AF |
5949 | POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) |
5950 | { | |
ca5dff0a | 5951 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
5952 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
5953 | ||
ca5dff0a | 5954 | dc->desc = "PowerPC 7440 (aka G4)"; |
7856e3a4 AF |
5955 | pcc->init_proc = init_proc_7440; |
5956 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
5957 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
5958 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
5959 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
5960 | PPC_FLOAT_STFIWX | | |
5961 | PPC_CACHE | PPC_CACHE_ICBI | | |
5962 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
5963 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
5964 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
5965 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
5966 | PPC_SEGMENT | PPC_EXTERN | | |
5967 | PPC_ALTIVEC; | |
ba9fd9f1 AF |
5968 | pcc->msr_mask = 0x000000000205FF77ULL; |
5969 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; | |
5970 | pcc->excp_model = POWERPC_EXCP_74xx; | |
5971 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
5972 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
5973 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
5974 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
5975 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
5976 | } |
5977 | ||
a750fc0b JM |
5978 | static void init_proc_7450 (CPUPPCState *env) |
5979 | { | |
5980 | gen_spr_ne_601(env); | |
5981 | gen_spr_7xx(env); | |
5982 | /* Time base */ | |
5983 | gen_tbl(env); | |
5984 | /* 74xx specific SPR */ | |
5985 | gen_spr_74xx(env); | |
5986 | /* Level 3 cache control */ | |
5987 | gen_l3_ctrl(env); | |
4e777442 JM |
5988 | /* L3ITCR1 */ |
5989 | /* XXX : not implemented */ | |
5990 | spr_register(env, SPR_L3ITCR1, "L3ITCR1", | |
5991 | SPR_NOACCESS, SPR_NOACCESS, | |
5992 | &spr_read_generic, &spr_write_generic, | |
5993 | 0x00000000); | |
5994 | /* L3ITCR2 */ | |
5995 | /* XXX : not implemented */ | |
5996 | spr_register(env, SPR_L3ITCR2, "L3ITCR2", | |
5997 | SPR_NOACCESS, SPR_NOACCESS, | |
5998 | &spr_read_generic, &spr_write_generic, | |
5999 | 0x00000000); | |
6000 | /* L3ITCR3 */ | |
6001 | /* XXX : not implemented */ | |
6002 | spr_register(env, SPR_L3ITCR3, "L3ITCR3", | |
6003 | SPR_NOACCESS, SPR_NOACCESS, | |
6004 | &spr_read_generic, &spr_write_generic, | |
6005 | 0x00000000); | |
6006 | /* L3OHCR */ | |
6007 | /* XXX : not implemented */ | |
6008 | spr_register(env, SPR_L3OHCR, "L3OHCR", | |
6009 | SPR_NOACCESS, SPR_NOACCESS, | |
6010 | &spr_read_generic, &spr_write_generic, | |
6011 | 0x00000000); | |
6012 | /* XXX : not implemented */ | |
6013 | spr_register(env, SPR_UBAMR, "UBAMR", | |
6014 | &spr_read_ureg, SPR_NOACCESS, | |
6015 | &spr_read_ureg, SPR_NOACCESS, | |
6016 | 0x00000000); | |
a750fc0b JM |
6017 | /* LDSTCR */ |
6018 | /* XXX : not implemented */ | |
6019 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
6020 | SPR_NOACCESS, SPR_NOACCESS, | |
6021 | &spr_read_generic, &spr_write_generic, | |
6022 | 0x00000000); | |
6023 | /* ICTRL */ | |
6024 | /* XXX : not implemented */ | |
6025 | spr_register(env, SPR_ICTRL, "ICTRL", | |
6026 | SPR_NOACCESS, SPR_NOACCESS, | |
6027 | &spr_read_generic, &spr_write_generic, | |
6028 | 0x00000000); | |
6029 | /* MSSSR0 */ | |
578bb252 | 6030 | /* XXX : not implemented */ |
a750fc0b JM |
6031 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
6032 | SPR_NOACCESS, SPR_NOACCESS, | |
6033 | &spr_read_generic, &spr_write_generic, | |
6034 | 0x00000000); | |
6035 | /* PMC */ | |
6036 | /* XXX : not implemented */ | |
6037 | spr_register(env, SPR_PMC5, "PMC5", | |
6038 | SPR_NOACCESS, SPR_NOACCESS, | |
6039 | &spr_read_generic, &spr_write_generic, | |
6040 | 0x00000000); | |
578bb252 | 6041 | /* XXX : not implemented */ |
a750fc0b JM |
6042 | spr_register(env, SPR_UPMC5, "UPMC5", |
6043 | &spr_read_ureg, SPR_NOACCESS, | |
6044 | &spr_read_ureg, SPR_NOACCESS, | |
6045 | 0x00000000); | |
578bb252 | 6046 | /* XXX : not implemented */ |
a750fc0b JM |
6047 | spr_register(env, SPR_PMC6, "PMC6", |
6048 | SPR_NOACCESS, SPR_NOACCESS, | |
6049 | &spr_read_generic, &spr_write_generic, | |
6050 | 0x00000000); | |
578bb252 | 6051 | /* XXX : not implemented */ |
a750fc0b JM |
6052 | spr_register(env, SPR_UPMC6, "UPMC6", |
6053 | &spr_read_ureg, SPR_NOACCESS, | |
6054 | &spr_read_ureg, SPR_NOACCESS, | |
6055 | 0x00000000); | |
6056 | /* Memory management */ | |
6057 | gen_low_BATs(env); | |
578bb252 | 6058 | gen_74xx_soft_tlb(env, 128, 2); |
e1833e1f | 6059 | init_excp_7450(env); |
d63001d1 JM |
6060 | env->dcache_line_size = 32; |
6061 | env->icache_line_size = 32; | |
a750fc0b JM |
6062 | /* Allocate hardware IRQ controller */ |
6063 | ppc6xx_irq_init(env); | |
6064 | } | |
a750fc0b | 6065 | |
7856e3a4 AF |
6066 | POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) |
6067 | { | |
ca5dff0a | 6068 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6069 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6070 | ||
ca5dff0a | 6071 | dc->desc = "PowerPC 7450 (aka G4)"; |
7856e3a4 AF |
6072 | pcc->init_proc = init_proc_7450; |
6073 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
6074 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6075 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6076 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6077 | PPC_FLOAT_STFIWX | | |
6078 | PPC_CACHE | PPC_CACHE_ICBI | | |
6079 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6080 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6081 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6082 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
6083 | PPC_SEGMENT | PPC_EXTERN | | |
6084 | PPC_ALTIVEC; | |
ba9fd9f1 AF |
6085 | pcc->msr_mask = 0x000000000205FF77ULL; |
6086 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; | |
6087 | pcc->excp_model = POWERPC_EXCP_74xx; | |
6088 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6089 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6090 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6091 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6092 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6093 | } |
6094 | ||
a750fc0b JM |
6095 | static void init_proc_7445 (CPUPPCState *env) |
6096 | { | |
6097 | gen_spr_ne_601(env); | |
6098 | gen_spr_7xx(env); | |
6099 | /* Time base */ | |
6100 | gen_tbl(env); | |
6101 | /* 74xx specific SPR */ | |
6102 | gen_spr_74xx(env); | |
6103 | /* LDSTCR */ | |
6104 | /* XXX : not implemented */ | |
6105 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
6106 | SPR_NOACCESS, SPR_NOACCESS, | |
6107 | &spr_read_generic, &spr_write_generic, | |
6108 | 0x00000000); | |
6109 | /* ICTRL */ | |
6110 | /* XXX : not implemented */ | |
6111 | spr_register(env, SPR_ICTRL, "ICTRL", | |
6112 | SPR_NOACCESS, SPR_NOACCESS, | |
6113 | &spr_read_generic, &spr_write_generic, | |
6114 | 0x00000000); | |
6115 | /* MSSSR0 */ | |
578bb252 | 6116 | /* XXX : not implemented */ |
a750fc0b JM |
6117 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
6118 | SPR_NOACCESS, SPR_NOACCESS, | |
6119 | &spr_read_generic, &spr_write_generic, | |
6120 | 0x00000000); | |
6121 | /* PMC */ | |
6122 | /* XXX : not implemented */ | |
6123 | spr_register(env, SPR_PMC5, "PMC5", | |
6124 | SPR_NOACCESS, SPR_NOACCESS, | |
6125 | &spr_read_generic, &spr_write_generic, | |
6126 | 0x00000000); | |
578bb252 | 6127 | /* XXX : not implemented */ |
a750fc0b JM |
6128 | spr_register(env, SPR_UPMC5, "UPMC5", |
6129 | &spr_read_ureg, SPR_NOACCESS, | |
6130 | &spr_read_ureg, SPR_NOACCESS, | |
6131 | 0x00000000); | |
578bb252 | 6132 | /* XXX : not implemented */ |
a750fc0b JM |
6133 | spr_register(env, SPR_PMC6, "PMC6", |
6134 | SPR_NOACCESS, SPR_NOACCESS, | |
6135 | &spr_read_generic, &spr_write_generic, | |
6136 | 0x00000000); | |
578bb252 | 6137 | /* XXX : not implemented */ |
a750fc0b JM |
6138 | spr_register(env, SPR_UPMC6, "UPMC6", |
6139 | &spr_read_ureg, SPR_NOACCESS, | |
6140 | &spr_read_ureg, SPR_NOACCESS, | |
6141 | 0x00000000); | |
6142 | /* SPRGs */ | |
6143 | spr_register(env, SPR_SPRG4, "SPRG4", | |
6144 | SPR_NOACCESS, SPR_NOACCESS, | |
6145 | &spr_read_generic, &spr_write_generic, | |
6146 | 0x00000000); | |
6147 | spr_register(env, SPR_USPRG4, "USPRG4", | |
6148 | &spr_read_ureg, SPR_NOACCESS, | |
6149 | &spr_read_ureg, SPR_NOACCESS, | |
6150 | 0x00000000); | |
6151 | spr_register(env, SPR_SPRG5, "SPRG5", | |
6152 | SPR_NOACCESS, SPR_NOACCESS, | |
6153 | &spr_read_generic, &spr_write_generic, | |
6154 | 0x00000000); | |
6155 | spr_register(env, SPR_USPRG5, "USPRG5", | |
6156 | &spr_read_ureg, SPR_NOACCESS, | |
6157 | &spr_read_ureg, SPR_NOACCESS, | |
6158 | 0x00000000); | |
6159 | spr_register(env, SPR_SPRG6, "SPRG6", | |
6160 | SPR_NOACCESS, SPR_NOACCESS, | |
6161 | &spr_read_generic, &spr_write_generic, | |
6162 | 0x00000000); | |
6163 | spr_register(env, SPR_USPRG6, "USPRG6", | |
6164 | &spr_read_ureg, SPR_NOACCESS, | |
6165 | &spr_read_ureg, SPR_NOACCESS, | |
6166 | 0x00000000); | |
6167 | spr_register(env, SPR_SPRG7, "SPRG7", | |
6168 | SPR_NOACCESS, SPR_NOACCESS, | |
6169 | &spr_read_generic, &spr_write_generic, | |
6170 | 0x00000000); | |
6171 | spr_register(env, SPR_USPRG7, "USPRG7", | |
6172 | &spr_read_ureg, SPR_NOACCESS, | |
6173 | &spr_read_ureg, SPR_NOACCESS, | |
6174 | 0x00000000); | |
6175 | /* Memory management */ | |
6176 | gen_low_BATs(env); | |
6177 | gen_high_BATs(env); | |
578bb252 | 6178 | gen_74xx_soft_tlb(env, 128, 2); |
e1833e1f | 6179 | init_excp_7450(env); |
d63001d1 JM |
6180 | env->dcache_line_size = 32; |
6181 | env->icache_line_size = 32; | |
a750fc0b JM |
6182 | /* Allocate hardware IRQ controller */ |
6183 | ppc6xx_irq_init(env); | |
6184 | } | |
a750fc0b | 6185 | |
7856e3a4 AF |
6186 | POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) |
6187 | { | |
ca5dff0a | 6188 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6189 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6190 | ||
ca5dff0a | 6191 | dc->desc = "PowerPC 7445 (aka G4)"; |
7856e3a4 AF |
6192 | pcc->init_proc = init_proc_7445; |
6193 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
6194 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6195 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6196 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6197 | PPC_FLOAT_STFIWX | | |
6198 | PPC_CACHE | PPC_CACHE_ICBI | | |
6199 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6200 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6201 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6202 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
6203 | PPC_SEGMENT | PPC_EXTERN | | |
6204 | PPC_ALTIVEC; | |
ba9fd9f1 AF |
6205 | pcc->msr_mask = 0x000000000205FF77ULL; |
6206 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; | |
6207 | pcc->excp_model = POWERPC_EXCP_74xx; | |
6208 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6209 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6210 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6211 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6212 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6213 | } |
6214 | ||
a750fc0b JM |
6215 | static void init_proc_7455 (CPUPPCState *env) |
6216 | { | |
6217 | gen_spr_ne_601(env); | |
6218 | gen_spr_7xx(env); | |
6219 | /* Time base */ | |
6220 | gen_tbl(env); | |
6221 | /* 74xx specific SPR */ | |
6222 | gen_spr_74xx(env); | |
6223 | /* Level 3 cache control */ | |
6224 | gen_l3_ctrl(env); | |
6225 | /* LDSTCR */ | |
6226 | /* XXX : not implemented */ | |
6227 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
6228 | SPR_NOACCESS, SPR_NOACCESS, | |
6229 | &spr_read_generic, &spr_write_generic, | |
6230 | 0x00000000); | |
6231 | /* ICTRL */ | |
6232 | /* XXX : not implemented */ | |
6233 | spr_register(env, SPR_ICTRL, "ICTRL", | |
6234 | SPR_NOACCESS, SPR_NOACCESS, | |
6235 | &spr_read_generic, &spr_write_generic, | |
6236 | 0x00000000); | |
6237 | /* MSSSR0 */ | |
578bb252 | 6238 | /* XXX : not implemented */ |
a750fc0b JM |
6239 | spr_register(env, SPR_MSSSR0, "MSSSR0", |
6240 | SPR_NOACCESS, SPR_NOACCESS, | |
6241 | &spr_read_generic, &spr_write_generic, | |
6242 | 0x00000000); | |
6243 | /* PMC */ | |
6244 | /* XXX : not implemented */ | |
6245 | spr_register(env, SPR_PMC5, "PMC5", | |
6246 | SPR_NOACCESS, SPR_NOACCESS, | |
6247 | &spr_read_generic, &spr_write_generic, | |
6248 | 0x00000000); | |
578bb252 | 6249 | /* XXX : not implemented */ |
a750fc0b JM |
6250 | spr_register(env, SPR_UPMC5, "UPMC5", |
6251 | &spr_read_ureg, SPR_NOACCESS, | |
6252 | &spr_read_ureg, SPR_NOACCESS, | |
6253 | 0x00000000); | |
578bb252 | 6254 | /* XXX : not implemented */ |
a750fc0b JM |
6255 | spr_register(env, SPR_PMC6, "PMC6", |
6256 | SPR_NOACCESS, SPR_NOACCESS, | |
6257 | &spr_read_generic, &spr_write_generic, | |
6258 | 0x00000000); | |
578bb252 | 6259 | /* XXX : not implemented */ |
a750fc0b JM |
6260 | spr_register(env, SPR_UPMC6, "UPMC6", |
6261 | &spr_read_ureg, SPR_NOACCESS, | |
6262 | &spr_read_ureg, SPR_NOACCESS, | |
6263 | 0x00000000); | |
6264 | /* SPRGs */ | |
6265 | spr_register(env, SPR_SPRG4, "SPRG4", | |
6266 | SPR_NOACCESS, SPR_NOACCESS, | |
6267 | &spr_read_generic, &spr_write_generic, | |
6268 | 0x00000000); | |
6269 | spr_register(env, SPR_USPRG4, "USPRG4", | |
6270 | &spr_read_ureg, SPR_NOACCESS, | |
6271 | &spr_read_ureg, SPR_NOACCESS, | |
6272 | 0x00000000); | |
6273 | spr_register(env, SPR_SPRG5, "SPRG5", | |
6274 | SPR_NOACCESS, SPR_NOACCESS, | |
6275 | &spr_read_generic, &spr_write_generic, | |
6276 | 0x00000000); | |
6277 | spr_register(env, SPR_USPRG5, "USPRG5", | |
6278 | &spr_read_ureg, SPR_NOACCESS, | |
6279 | &spr_read_ureg, SPR_NOACCESS, | |
6280 | 0x00000000); | |
6281 | spr_register(env, SPR_SPRG6, "SPRG6", | |
6282 | SPR_NOACCESS, SPR_NOACCESS, | |
6283 | &spr_read_generic, &spr_write_generic, | |
6284 | 0x00000000); | |
6285 | spr_register(env, SPR_USPRG6, "USPRG6", | |
6286 | &spr_read_ureg, SPR_NOACCESS, | |
6287 | &spr_read_ureg, SPR_NOACCESS, | |
6288 | 0x00000000); | |
6289 | spr_register(env, SPR_SPRG7, "SPRG7", | |
6290 | SPR_NOACCESS, SPR_NOACCESS, | |
6291 | &spr_read_generic, &spr_write_generic, | |
6292 | 0x00000000); | |
6293 | spr_register(env, SPR_USPRG7, "USPRG7", | |
6294 | &spr_read_ureg, SPR_NOACCESS, | |
6295 | &spr_read_ureg, SPR_NOACCESS, | |
6296 | 0x00000000); | |
6297 | /* Memory management */ | |
6298 | gen_low_BATs(env); | |
6299 | gen_high_BATs(env); | |
578bb252 | 6300 | gen_74xx_soft_tlb(env, 128, 2); |
e1833e1f | 6301 | init_excp_7450(env); |
d63001d1 JM |
6302 | env->dcache_line_size = 32; |
6303 | env->icache_line_size = 32; | |
a750fc0b JM |
6304 | /* Allocate hardware IRQ controller */ |
6305 | ppc6xx_irq_init(env); | |
6306 | } | |
a750fc0b | 6307 | |
7856e3a4 AF |
6308 | POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) |
6309 | { | |
ca5dff0a | 6310 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6311 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6312 | ||
ca5dff0a | 6313 | dc->desc = "PowerPC 7455 (aka G4)"; |
7856e3a4 AF |
6314 | pcc->init_proc = init_proc_7455; |
6315 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
6316 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6317 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6318 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6319 | PPC_FLOAT_STFIWX | | |
6320 | PPC_CACHE | PPC_CACHE_ICBI | | |
6321 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6322 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6323 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6324 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
6325 | PPC_SEGMENT | PPC_EXTERN | | |
6326 | PPC_ALTIVEC; | |
ba9fd9f1 AF |
6327 | pcc->msr_mask = 0x000000000205FF77ULL; |
6328 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; | |
6329 | pcc->excp_model = POWERPC_EXCP_74xx; | |
6330 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6331 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6332 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6333 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6334 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6335 | } |
6336 | ||
4e777442 JM |
6337 | static void init_proc_7457 (CPUPPCState *env) |
6338 | { | |
6339 | gen_spr_ne_601(env); | |
6340 | gen_spr_7xx(env); | |
6341 | /* Time base */ | |
6342 | gen_tbl(env); | |
6343 | /* 74xx specific SPR */ | |
6344 | gen_spr_74xx(env); | |
6345 | /* Level 3 cache control */ | |
6346 | gen_l3_ctrl(env); | |
6347 | /* L3ITCR1 */ | |
6348 | /* XXX : not implemented */ | |
6349 | spr_register(env, SPR_L3ITCR1, "L3ITCR1", | |
6350 | SPR_NOACCESS, SPR_NOACCESS, | |
6351 | &spr_read_generic, &spr_write_generic, | |
6352 | 0x00000000); | |
6353 | /* L3ITCR2 */ | |
6354 | /* XXX : not implemented */ | |
6355 | spr_register(env, SPR_L3ITCR2, "L3ITCR2", | |
6356 | SPR_NOACCESS, SPR_NOACCESS, | |
6357 | &spr_read_generic, &spr_write_generic, | |
6358 | 0x00000000); | |
6359 | /* L3ITCR3 */ | |
6360 | /* XXX : not implemented */ | |
6361 | spr_register(env, SPR_L3ITCR3, "L3ITCR3", | |
6362 | SPR_NOACCESS, SPR_NOACCESS, | |
6363 | &spr_read_generic, &spr_write_generic, | |
6364 | 0x00000000); | |
6365 | /* L3OHCR */ | |
6366 | /* XXX : not implemented */ | |
6367 | spr_register(env, SPR_L3OHCR, "L3OHCR", | |
6368 | SPR_NOACCESS, SPR_NOACCESS, | |
6369 | &spr_read_generic, &spr_write_generic, | |
6370 | 0x00000000); | |
6371 | /* LDSTCR */ | |
6372 | /* XXX : not implemented */ | |
6373 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
6374 | SPR_NOACCESS, SPR_NOACCESS, | |
6375 | &spr_read_generic, &spr_write_generic, | |
6376 | 0x00000000); | |
6377 | /* ICTRL */ | |
6378 | /* XXX : not implemented */ | |
6379 | spr_register(env, SPR_ICTRL, "ICTRL", | |
6380 | SPR_NOACCESS, SPR_NOACCESS, | |
6381 | &spr_read_generic, &spr_write_generic, | |
6382 | 0x00000000); | |
6383 | /* MSSSR0 */ | |
6384 | /* XXX : not implemented */ | |
6385 | spr_register(env, SPR_MSSSR0, "MSSSR0", | |
6386 | SPR_NOACCESS, SPR_NOACCESS, | |
6387 | &spr_read_generic, &spr_write_generic, | |
6388 | 0x00000000); | |
6389 | /* PMC */ | |
6390 | /* XXX : not implemented */ | |
6391 | spr_register(env, SPR_PMC5, "PMC5", | |
6392 | SPR_NOACCESS, SPR_NOACCESS, | |
6393 | &spr_read_generic, &spr_write_generic, | |
6394 | 0x00000000); | |
6395 | /* XXX : not implemented */ | |
6396 | spr_register(env, SPR_UPMC5, "UPMC5", | |
6397 | &spr_read_ureg, SPR_NOACCESS, | |
6398 | &spr_read_ureg, SPR_NOACCESS, | |
6399 | 0x00000000); | |
6400 | /* XXX : not implemented */ | |
6401 | spr_register(env, SPR_PMC6, "PMC6", | |
6402 | SPR_NOACCESS, SPR_NOACCESS, | |
6403 | &spr_read_generic, &spr_write_generic, | |
6404 | 0x00000000); | |
6405 | /* XXX : not implemented */ | |
6406 | spr_register(env, SPR_UPMC6, "UPMC6", | |
6407 | &spr_read_ureg, SPR_NOACCESS, | |
6408 | &spr_read_ureg, SPR_NOACCESS, | |
6409 | 0x00000000); | |
6410 | /* SPRGs */ | |
6411 | spr_register(env, SPR_SPRG4, "SPRG4", | |
6412 | SPR_NOACCESS, SPR_NOACCESS, | |
6413 | &spr_read_generic, &spr_write_generic, | |
6414 | 0x00000000); | |
6415 | spr_register(env, SPR_USPRG4, "USPRG4", | |
6416 | &spr_read_ureg, SPR_NOACCESS, | |
6417 | &spr_read_ureg, SPR_NOACCESS, | |
6418 | 0x00000000); | |
6419 | spr_register(env, SPR_SPRG5, "SPRG5", | |
6420 | SPR_NOACCESS, SPR_NOACCESS, | |
6421 | &spr_read_generic, &spr_write_generic, | |
6422 | 0x00000000); | |
6423 | spr_register(env, SPR_USPRG5, "USPRG5", | |
6424 | &spr_read_ureg, SPR_NOACCESS, | |
6425 | &spr_read_ureg, SPR_NOACCESS, | |
6426 | 0x00000000); | |
6427 | spr_register(env, SPR_SPRG6, "SPRG6", | |
6428 | SPR_NOACCESS, SPR_NOACCESS, | |
6429 | &spr_read_generic, &spr_write_generic, | |
6430 | 0x00000000); | |
6431 | spr_register(env, SPR_USPRG6, "USPRG6", | |
6432 | &spr_read_ureg, SPR_NOACCESS, | |
6433 | &spr_read_ureg, SPR_NOACCESS, | |
6434 | 0x00000000); | |
6435 | spr_register(env, SPR_SPRG7, "SPRG7", | |
6436 | SPR_NOACCESS, SPR_NOACCESS, | |
6437 | &spr_read_generic, &spr_write_generic, | |
6438 | 0x00000000); | |
6439 | spr_register(env, SPR_USPRG7, "USPRG7", | |
6440 | &spr_read_ureg, SPR_NOACCESS, | |
6441 | &spr_read_ureg, SPR_NOACCESS, | |
6442 | 0x00000000); | |
6443 | /* Memory management */ | |
6444 | gen_low_BATs(env); | |
6445 | gen_high_BATs(env); | |
6446 | gen_74xx_soft_tlb(env, 128, 2); | |
6447 | init_excp_7450(env); | |
6448 | env->dcache_line_size = 32; | |
6449 | env->icache_line_size = 32; | |
6450 | /* Allocate hardware IRQ controller */ | |
6451 | ppc6xx_irq_init(env); | |
6452 | } | |
6453 | ||
7856e3a4 AF |
6454 | POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) |
6455 | { | |
ca5dff0a | 6456 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6457 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6458 | ||
ca5dff0a | 6459 | dc->desc = "PowerPC 7457 (aka G4)"; |
7856e3a4 AF |
6460 | pcc->init_proc = init_proc_7457; |
6461 | pcc->check_pow = check_pow_hid0_74xx; | |
53116ebf AF |
6462 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6463 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6464 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6465 | PPC_FLOAT_STFIWX | | |
6466 | PPC_CACHE | PPC_CACHE_ICBI | | |
6467 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6468 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6469 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6470 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
6471 | PPC_SEGMENT | PPC_EXTERN | | |
6472 | PPC_ALTIVEC; | |
ba9fd9f1 AF |
6473 | pcc->msr_mask = 0x000000000205FF77ULL; |
6474 | pcc->mmu_model = POWERPC_MMU_SOFT_74xx; | |
6475 | pcc->excp_model = POWERPC_EXCP_74xx; | |
6476 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6477 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6478 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6479 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6480 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6481 | } |
6482 | ||
7162bdea JG |
6483 | static void init_proc_e600 (CPUPPCState *env) |
6484 | { | |
6485 | gen_spr_ne_601(env); | |
6486 | gen_spr_7xx(env); | |
6487 | /* Time base */ | |
6488 | gen_tbl(env); | |
6489 | /* 74xx specific SPR */ | |
6490 | gen_spr_74xx(env); | |
6491 | /* XXX : not implemented */ | |
6492 | spr_register(env, SPR_UBAMR, "UBAMR", | |
6493 | &spr_read_ureg, SPR_NOACCESS, | |
6494 | &spr_read_ureg, SPR_NOACCESS, | |
6495 | 0x00000000); | |
6496 | /* XXX : not implemented */ | |
6497 | spr_register(env, SPR_LDSTCR, "LDSTCR", | |
6498 | SPR_NOACCESS, SPR_NOACCESS, | |
6499 | &spr_read_generic, &spr_write_generic, | |
6500 | 0x00000000); | |
6501 | /* XXX : not implemented */ | |
6502 | spr_register(env, SPR_ICTRL, "ICTRL", | |
6503 | SPR_NOACCESS, SPR_NOACCESS, | |
6504 | &spr_read_generic, &spr_write_generic, | |
6505 | 0x00000000); | |
6506 | /* XXX : not implemented */ | |
6507 | spr_register(env, SPR_MSSSR0, "MSSSR0", | |
6508 | SPR_NOACCESS, SPR_NOACCESS, | |
6509 | &spr_read_generic, &spr_write_generic, | |
6510 | 0x00000000); | |
6511 | /* XXX : not implemented */ | |
6512 | spr_register(env, SPR_PMC5, "PMC5", | |
6513 | SPR_NOACCESS, SPR_NOACCESS, | |
6514 | &spr_read_generic, &spr_write_generic, | |
6515 | 0x00000000); | |
6516 | /* XXX : not implemented */ | |
6517 | spr_register(env, SPR_UPMC5, "UPMC5", | |
6518 | &spr_read_ureg, SPR_NOACCESS, | |
6519 | &spr_read_ureg, SPR_NOACCESS, | |
6520 | 0x00000000); | |
6521 | /* XXX : not implemented */ | |
6522 | spr_register(env, SPR_PMC6, "PMC6", | |
6523 | SPR_NOACCESS, SPR_NOACCESS, | |
6524 | &spr_read_generic, &spr_write_generic, | |
6525 | 0x00000000); | |
6526 | /* XXX : not implemented */ | |
6527 | spr_register(env, SPR_UPMC6, "UPMC6", | |
6528 | &spr_read_ureg, SPR_NOACCESS, | |
6529 | &spr_read_ureg, SPR_NOACCESS, | |
6530 | 0x00000000); | |
6531 | /* SPRGs */ | |
6532 | spr_register(env, SPR_SPRG4, "SPRG4", | |
6533 | SPR_NOACCESS, SPR_NOACCESS, | |
6534 | &spr_read_generic, &spr_write_generic, | |
6535 | 0x00000000); | |
6536 | spr_register(env, SPR_USPRG4, "USPRG4", | |
6537 | &spr_read_ureg, SPR_NOACCESS, | |
6538 | &spr_read_ureg, SPR_NOACCESS, | |
6539 | 0x00000000); | |
6540 | spr_register(env, SPR_SPRG5, "SPRG5", | |
6541 | SPR_NOACCESS, SPR_NOACCESS, | |
6542 | &spr_read_generic, &spr_write_generic, | |
6543 | 0x00000000); | |
6544 | spr_register(env, SPR_USPRG5, "USPRG5", | |
6545 | &spr_read_ureg, SPR_NOACCESS, | |
6546 | &spr_read_ureg, SPR_NOACCESS, | |
6547 | 0x00000000); | |
6548 | spr_register(env, SPR_SPRG6, "SPRG6", | |
6549 | SPR_NOACCESS, SPR_NOACCESS, | |
6550 | &spr_read_generic, &spr_write_generic, | |
6551 | 0x00000000); | |
6552 | spr_register(env, SPR_USPRG6, "USPRG6", | |
6553 | &spr_read_ureg, SPR_NOACCESS, | |
6554 | &spr_read_ureg, SPR_NOACCESS, | |
6555 | 0x00000000); | |
6556 | spr_register(env, SPR_SPRG7, "SPRG7", | |
6557 | SPR_NOACCESS, SPR_NOACCESS, | |
6558 | &spr_read_generic, &spr_write_generic, | |
6559 | 0x00000000); | |
6560 | spr_register(env, SPR_USPRG7, "USPRG7", | |
6561 | &spr_read_ureg, SPR_NOACCESS, | |
6562 | &spr_read_ureg, SPR_NOACCESS, | |
6563 | 0x00000000); | |
6564 | /* Memory management */ | |
6565 | gen_low_BATs(env); | |
6566 | gen_high_BATs(env); | |
6567 | gen_74xx_soft_tlb(env, 128, 2); | |
6568 | init_excp_7450(env); | |
6569 | env->dcache_line_size = 32; | |
6570 | env->icache_line_size = 32; | |
6571 | /* Allocate hardware IRQ controller */ | |
6572 | ppc6xx_irq_init(env); | |
6573 | } | |
6574 | ||
6575 | POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) | |
6576 | { | |
6577 | DeviceClass *dc = DEVICE_CLASS(oc); | |
6578 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
6579 | ||
6580 | dc->desc = "PowerPC e600"; | |
6581 | pcc->init_proc = init_proc_e600; | |
6582 | pcc->check_pow = check_pow_hid0_74xx; | |
6583 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | | |
6584 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6585 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6586 | PPC_FLOAT_STFIWX | | |
6587 | PPC_CACHE | PPC_CACHE_ICBI | | |
6588 | PPC_CACHE_DCBA | PPC_CACHE_DCBZ | | |
6589 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6590 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6591 | PPC_MEM_TLBIA | PPC_74xx_TLB | | |
6592 | PPC_SEGMENT | PPC_EXTERN | | |
6593 | PPC_ALTIVEC; | |
6594 | pcc->insns_flags2 = PPC_NONE; | |
6595 | pcc->msr_mask = 0x000000000205FF77ULL; | |
6596 | pcc->mmu_model = POWERPC_MMU_32B; | |
6597 | #if defined(CONFIG_SOFTMMU) | |
6598 | pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; | |
6599 | #endif | |
6600 | pcc->excp_model = POWERPC_EXCP_74xx; | |
6601 | pcc->bus_model = PPC_FLAGS_INPUT_6xx; | |
6602 | pcc->bfd_mach = bfd_mach_ppc_7400; | |
6603 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6604 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6605 | POWERPC_FLAG_BUS_CLK; | |
6606 | } | |
6607 | ||
a750fc0b | 6608 | #if defined (TARGET_PPC64) |
417bf010 JM |
6609 | #if defined(CONFIG_USER_ONLY) |
6610 | #define POWERPC970_HID5_INIT 0x00000080 | |
6611 | #else | |
6612 | #define POWERPC970_HID5_INIT 0x00000000 | |
6613 | #endif | |
6614 | ||
2f462816 JM |
6615 | static int check_pow_970 (CPUPPCState *env) |
6616 | { | |
6617 | if (env->spr[SPR_HID0] & 0x00600000) | |
6618 | return 1; | |
6619 | ||
6620 | return 0; | |
6621 | } | |
6622 | ||
a750fc0b JM |
6623 | static void init_proc_970 (CPUPPCState *env) |
6624 | { | |
6625 | gen_spr_ne_601(env); | |
6626 | gen_spr_7xx(env); | |
6627 | /* Time base */ | |
6628 | gen_tbl(env); | |
6629 | /* Hardware implementation registers */ | |
6630 | /* XXX : not implemented */ | |
6631 | spr_register(env, SPR_HID0, "HID0", | |
6632 | SPR_NOACCESS, SPR_NOACCESS, | |
06403421 | 6633 | &spr_read_generic, &spr_write_clear, |
d63001d1 | 6634 | 0x60000000); |
a750fc0b JM |
6635 | /* XXX : not implemented */ |
6636 | spr_register(env, SPR_HID1, "HID1", | |
6637 | SPR_NOACCESS, SPR_NOACCESS, | |
6638 | &spr_read_generic, &spr_write_generic, | |
6639 | 0x00000000); | |
6640 | /* XXX : not implemented */ | |
bd928eba | 6641 | spr_register(env, SPR_750FX_HID2, "HID2", |
a750fc0b JM |
6642 | SPR_NOACCESS, SPR_NOACCESS, |
6643 | &spr_read_generic, &spr_write_generic, | |
6644 | 0x00000000); | |
e57448f1 JM |
6645 | /* XXX : not implemented */ |
6646 | spr_register(env, SPR_970_HID5, "HID5", | |
6647 | SPR_NOACCESS, SPR_NOACCESS, | |
6648 | &spr_read_generic, &spr_write_generic, | |
417bf010 | 6649 | POWERPC970_HID5_INIT); |
bd928eba JM |
6650 | /* XXX : not implemented */ |
6651 | spr_register(env, SPR_L2CR, "L2CR", | |
6652 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 6653 | &spr_read_generic, NULL, |
bd928eba | 6654 | 0x00000000); |
a750fc0b JM |
6655 | /* Memory management */ |
6656 | /* XXX: not correct */ | |
6657 | gen_low_BATs(env); | |
12de9a39 JM |
6658 | /* XXX : not implemented */ |
6659 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
6660 | SPR_NOACCESS, SPR_NOACCESS, | |
6661 | &spr_read_generic, SPR_NOACCESS, | |
6662 | 0x00000000); /* TOFIX */ | |
6663 | /* XXX : not implemented */ | |
6664 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
6665 | SPR_NOACCESS, SPR_NOACCESS, | |
6666 | &spr_read_generic, &spr_write_generic, | |
6667 | 0x00000000); /* TOFIX */ | |
6668 | spr_register(env, SPR_HIOR, "SPR_HIOR", | |
6669 | SPR_NOACCESS, SPR_NOACCESS, | |
2adab7d6 BS |
6670 | &spr_read_hior, &spr_write_hior, |
6671 | 0x00000000); | |
f2e63a42 | 6672 | #if !defined(CONFIG_USER_ONLY) |
12de9a39 | 6673 | env->slb_nr = 32; |
f2e63a42 | 6674 | #endif |
e1833e1f | 6675 | init_excp_970(env); |
d63001d1 JM |
6676 | env->dcache_line_size = 128; |
6677 | env->icache_line_size = 128; | |
a750fc0b JM |
6678 | /* Allocate hardware IRQ controller */ |
6679 | ppc970_irq_init(env); | |
cf8358c8 AJ |
6680 | /* Can't find information on what this should be on reset. This |
6681 | * value is the one used by 74xx processors. */ | |
6682 | vscr_init(env, 0x00010000); | |
a750fc0b | 6683 | } |
a750fc0b | 6684 | |
7856e3a4 AF |
6685 | POWERPC_FAMILY(970)(ObjectClass *oc, void *data) |
6686 | { | |
ca5dff0a | 6687 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6688 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6689 | ||
ca5dff0a | 6690 | dc->desc = "PowerPC 970"; |
7856e3a4 AF |
6691 | pcc->init_proc = init_proc_970; |
6692 | pcc->check_pow = check_pow_970; | |
53116ebf AF |
6693 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6694 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6695 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6696 | PPC_FLOAT_STFIWX | | |
6697 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
6698 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6699 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6700 | PPC_64B | PPC_ALTIVEC | | |
6701 | PPC_SEGMENT_64B | PPC_SLBI; | |
ba9fd9f1 AF |
6702 | pcc->msr_mask = 0x900000000204FF36ULL; |
6703 | pcc->mmu_model = POWERPC_MMU_64B; | |
b632a148 DG |
6704 | #if defined(CONFIG_SOFTMMU) |
6705 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
6706 | #endif | |
ba9fd9f1 AF |
6707 | pcc->excp_model = POWERPC_EXCP_970; |
6708 | pcc->bus_model = PPC_FLAGS_INPUT_970; | |
6709 | pcc->bfd_mach = bfd_mach_ppc64; | |
6710 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6711 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6712 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6713 | } |
6714 | ||
2f462816 JM |
6715 | static int check_pow_970FX (CPUPPCState *env) |
6716 | { | |
6717 | if (env->spr[SPR_HID0] & 0x00600000) | |
6718 | return 1; | |
6719 | ||
6720 | return 0; | |
6721 | } | |
6722 | ||
a750fc0b JM |
6723 | static void init_proc_970FX (CPUPPCState *env) |
6724 | { | |
6725 | gen_spr_ne_601(env); | |
6726 | gen_spr_7xx(env); | |
6727 | /* Time base */ | |
6728 | gen_tbl(env); | |
6729 | /* Hardware implementation registers */ | |
6730 | /* XXX : not implemented */ | |
6731 | spr_register(env, SPR_HID0, "HID0", | |
6732 | SPR_NOACCESS, SPR_NOACCESS, | |
06403421 | 6733 | &spr_read_generic, &spr_write_clear, |
d63001d1 | 6734 | 0x60000000); |
a750fc0b JM |
6735 | /* XXX : not implemented */ |
6736 | spr_register(env, SPR_HID1, "HID1", | |
6737 | SPR_NOACCESS, SPR_NOACCESS, | |
6738 | &spr_read_generic, &spr_write_generic, | |
6739 | 0x00000000); | |
6740 | /* XXX : not implemented */ | |
bd928eba | 6741 | spr_register(env, SPR_750FX_HID2, "HID2", |
a750fc0b JM |
6742 | SPR_NOACCESS, SPR_NOACCESS, |
6743 | &spr_read_generic, &spr_write_generic, | |
6744 | 0x00000000); | |
d63001d1 JM |
6745 | /* XXX : not implemented */ |
6746 | spr_register(env, SPR_970_HID5, "HID5", | |
6747 | SPR_NOACCESS, SPR_NOACCESS, | |
6748 | &spr_read_generic, &spr_write_generic, | |
417bf010 | 6749 | POWERPC970_HID5_INIT); |
bd928eba JM |
6750 | /* XXX : not implemented */ |
6751 | spr_register(env, SPR_L2CR, "L2CR", | |
6752 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 6753 | &spr_read_generic, NULL, |
bd928eba | 6754 | 0x00000000); |
a750fc0b JM |
6755 | /* Memory management */ |
6756 | /* XXX: not correct */ | |
6757 | gen_low_BATs(env); | |
12de9a39 JM |
6758 | /* XXX : not implemented */ |
6759 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
6760 | SPR_NOACCESS, SPR_NOACCESS, | |
6761 | &spr_read_generic, SPR_NOACCESS, | |
6762 | 0x00000000); /* TOFIX */ | |
6763 | /* XXX : not implemented */ | |
6764 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
6765 | SPR_NOACCESS, SPR_NOACCESS, | |
6766 | &spr_read_generic, &spr_write_generic, | |
6767 | 0x00000000); /* TOFIX */ | |
6768 | spr_register(env, SPR_HIOR, "SPR_HIOR", | |
6769 | SPR_NOACCESS, SPR_NOACCESS, | |
2adab7d6 BS |
6770 | &spr_read_hior, &spr_write_hior, |
6771 | 0x00000000); | |
4e98d8cf BS |
6772 | spr_register(env, SPR_CTRL, "SPR_CTRL", |
6773 | SPR_NOACCESS, SPR_NOACCESS, | |
6774 | &spr_read_generic, &spr_write_generic, | |
6775 | 0x00000000); | |
6776 | spr_register(env, SPR_UCTRL, "SPR_UCTRL", | |
6777 | SPR_NOACCESS, SPR_NOACCESS, | |
6778 | &spr_read_generic, &spr_write_generic, | |
6779 | 0x00000000); | |
6780 | spr_register(env, SPR_VRSAVE, "SPR_VRSAVE", | |
6781 | &spr_read_generic, &spr_write_generic, | |
6782 | &spr_read_generic, &spr_write_generic, | |
6783 | 0x00000000); | |
f2e63a42 | 6784 | #if !defined(CONFIG_USER_ONLY) |
8eee0af9 | 6785 | env->slb_nr = 64; |
f2e63a42 | 6786 | #endif |
e1833e1f | 6787 | init_excp_970(env); |
d63001d1 JM |
6788 | env->dcache_line_size = 128; |
6789 | env->icache_line_size = 128; | |
a750fc0b JM |
6790 | /* Allocate hardware IRQ controller */ |
6791 | ppc970_irq_init(env); | |
cf8358c8 AJ |
6792 | /* Can't find information on what this should be on reset. This |
6793 | * value is the one used by 74xx processors. */ | |
6794 | vscr_init(env, 0x00010000); | |
a750fc0b | 6795 | } |
a750fc0b | 6796 | |
7856e3a4 AF |
6797 | POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data) |
6798 | { | |
ca5dff0a | 6799 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6800 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6801 | ||
ca5dff0a | 6802 | dc->desc = "PowerPC 970FX (aka G5)"; |
7856e3a4 AF |
6803 | pcc->init_proc = init_proc_970FX; |
6804 | pcc->check_pow = check_pow_970FX; | |
53116ebf AF |
6805 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6806 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6807 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6808 | PPC_FLOAT_STFIWX | | |
6809 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
6810 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6811 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6812 | PPC_64B | PPC_ALTIVEC | | |
6813 | PPC_SEGMENT_64B | PPC_SLBI; | |
ba9fd9f1 AF |
6814 | pcc->msr_mask = 0x800000000204FF36ULL; |
6815 | pcc->mmu_model = POWERPC_MMU_64B; | |
b632a148 DG |
6816 | #if defined(CONFIG_SOFTMMU) |
6817 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
6818 | #endif | |
ba9fd9f1 AF |
6819 | pcc->excp_model = POWERPC_EXCP_970; |
6820 | pcc->bus_model = PPC_FLAGS_INPUT_970; | |
6821 | pcc->bfd_mach = bfd_mach_ppc64; | |
6822 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6823 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6824 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6825 | } |
6826 | ||
2f462816 JM |
6827 | static int check_pow_970GX (CPUPPCState *env) |
6828 | { | |
6829 | if (env->spr[SPR_HID0] & 0x00600000) | |
6830 | return 1; | |
6831 | ||
6832 | return 0; | |
6833 | } | |
6834 | ||
a750fc0b JM |
6835 | static void init_proc_970GX (CPUPPCState *env) |
6836 | { | |
6837 | gen_spr_ne_601(env); | |
6838 | gen_spr_7xx(env); | |
6839 | /* Time base */ | |
6840 | gen_tbl(env); | |
6841 | /* Hardware implementation registers */ | |
6842 | /* XXX : not implemented */ | |
6843 | spr_register(env, SPR_HID0, "HID0", | |
6844 | SPR_NOACCESS, SPR_NOACCESS, | |
06403421 | 6845 | &spr_read_generic, &spr_write_clear, |
d63001d1 | 6846 | 0x60000000); |
a750fc0b JM |
6847 | /* XXX : not implemented */ |
6848 | spr_register(env, SPR_HID1, "HID1", | |
6849 | SPR_NOACCESS, SPR_NOACCESS, | |
6850 | &spr_read_generic, &spr_write_generic, | |
6851 | 0x00000000); | |
6852 | /* XXX : not implemented */ | |
bd928eba | 6853 | spr_register(env, SPR_750FX_HID2, "HID2", |
a750fc0b JM |
6854 | SPR_NOACCESS, SPR_NOACCESS, |
6855 | &spr_read_generic, &spr_write_generic, | |
6856 | 0x00000000); | |
d63001d1 JM |
6857 | /* XXX : not implemented */ |
6858 | spr_register(env, SPR_970_HID5, "HID5", | |
6859 | SPR_NOACCESS, SPR_NOACCESS, | |
6860 | &spr_read_generic, &spr_write_generic, | |
417bf010 | 6861 | POWERPC970_HID5_INIT); |
bd928eba JM |
6862 | /* XXX : not implemented */ |
6863 | spr_register(env, SPR_L2CR, "L2CR", | |
6864 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 6865 | &spr_read_generic, NULL, |
bd928eba | 6866 | 0x00000000); |
a750fc0b JM |
6867 | /* Memory management */ |
6868 | /* XXX: not correct */ | |
6869 | gen_low_BATs(env); | |
12de9a39 JM |
6870 | /* XXX : not implemented */ |
6871 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
6872 | SPR_NOACCESS, SPR_NOACCESS, | |
6873 | &spr_read_generic, SPR_NOACCESS, | |
6874 | 0x00000000); /* TOFIX */ | |
6875 | /* XXX : not implemented */ | |
6876 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
6877 | SPR_NOACCESS, SPR_NOACCESS, | |
6878 | &spr_read_generic, &spr_write_generic, | |
6879 | 0x00000000); /* TOFIX */ | |
6880 | spr_register(env, SPR_HIOR, "SPR_HIOR", | |
6881 | SPR_NOACCESS, SPR_NOACCESS, | |
2adab7d6 BS |
6882 | &spr_read_hior, &spr_write_hior, |
6883 | 0x00000000); | |
f2e63a42 | 6884 | #if !defined(CONFIG_USER_ONLY) |
12de9a39 | 6885 | env->slb_nr = 32; |
f2e63a42 | 6886 | #endif |
e1833e1f | 6887 | init_excp_970(env); |
d63001d1 JM |
6888 | env->dcache_line_size = 128; |
6889 | env->icache_line_size = 128; | |
a750fc0b JM |
6890 | /* Allocate hardware IRQ controller */ |
6891 | ppc970_irq_init(env); | |
cf8358c8 AJ |
6892 | /* Can't find information on what this should be on reset. This |
6893 | * value is the one used by 74xx processors. */ | |
6894 | vscr_init(env, 0x00010000); | |
a750fc0b | 6895 | } |
a750fc0b | 6896 | |
7856e3a4 AF |
6897 | POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data) |
6898 | { | |
ca5dff0a | 6899 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
6900 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
6901 | ||
ca5dff0a | 6902 | dc->desc = "PowerPC 970 GX"; |
7856e3a4 AF |
6903 | pcc->init_proc = init_proc_970GX; |
6904 | pcc->check_pow = check_pow_970GX; | |
53116ebf AF |
6905 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
6906 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
6907 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
6908 | PPC_FLOAT_STFIWX | | |
6909 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
6910 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
6911 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
6912 | PPC_64B | PPC_ALTIVEC | | |
6913 | PPC_SEGMENT_64B | PPC_SLBI; | |
ba9fd9f1 AF |
6914 | pcc->msr_mask = 0x800000000204FF36ULL; |
6915 | pcc->mmu_model = POWERPC_MMU_64B; | |
b632a148 DG |
6916 | #if defined(CONFIG_SOFTMMU) |
6917 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
6918 | #endif | |
ba9fd9f1 AF |
6919 | pcc->excp_model = POWERPC_EXCP_970; |
6920 | pcc->bus_model = PPC_FLAGS_INPUT_970; | |
6921 | pcc->bfd_mach = bfd_mach_ppc64; | |
6922 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
6923 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
6924 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
6925 | } |
6926 | ||
2f462816 JM |
6927 | static int check_pow_970MP (CPUPPCState *env) |
6928 | { | |
6929 | if (env->spr[SPR_HID0] & 0x01C00000) | |
6930 | return 1; | |
6931 | ||
6932 | return 0; | |
6933 | } | |
6934 | ||
6935 | static void init_proc_970MP (CPUPPCState *env) | |
6936 | { | |
6937 | gen_spr_ne_601(env); | |
6938 | gen_spr_7xx(env); | |
6939 | /* Time base */ | |
6940 | gen_tbl(env); | |
6941 | /* Hardware implementation registers */ | |
6942 | /* XXX : not implemented */ | |
6943 | spr_register(env, SPR_HID0, "HID0", | |
6944 | SPR_NOACCESS, SPR_NOACCESS, | |
6945 | &spr_read_generic, &spr_write_clear, | |
6946 | 0x60000000); | |
6947 | /* XXX : not implemented */ | |
6948 | spr_register(env, SPR_HID1, "HID1", | |
6949 | SPR_NOACCESS, SPR_NOACCESS, | |
6950 | &spr_read_generic, &spr_write_generic, | |
6951 | 0x00000000); | |
6952 | /* XXX : not implemented */ | |
bd928eba | 6953 | spr_register(env, SPR_750FX_HID2, "HID2", |
2f462816 JM |
6954 | SPR_NOACCESS, SPR_NOACCESS, |
6955 | &spr_read_generic, &spr_write_generic, | |
6956 | 0x00000000); | |
6957 | /* XXX : not implemented */ | |
6958 | spr_register(env, SPR_970_HID5, "HID5", | |
6959 | SPR_NOACCESS, SPR_NOACCESS, | |
6960 | &spr_read_generic, &spr_write_generic, | |
6961 | POWERPC970_HID5_INIT); | |
bd928eba JM |
6962 | /* XXX : not implemented */ |
6963 | spr_register(env, SPR_L2CR, "L2CR", | |
6964 | SPR_NOACCESS, SPR_NOACCESS, | |
2345f1c0 | 6965 | &spr_read_generic, NULL, |
bd928eba | 6966 | 0x00000000); |
2f462816 JM |
6967 | /* Memory management */ |
6968 | /* XXX: not correct */ | |
6969 | gen_low_BATs(env); | |
6970 | /* XXX : not implemented */ | |
6971 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
6972 | SPR_NOACCESS, SPR_NOACCESS, | |
6973 | &spr_read_generic, SPR_NOACCESS, | |
6974 | 0x00000000); /* TOFIX */ | |
6975 | /* XXX : not implemented */ | |
6976 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
6977 | SPR_NOACCESS, SPR_NOACCESS, | |
6978 | &spr_read_generic, &spr_write_generic, | |
6979 | 0x00000000); /* TOFIX */ | |
6980 | spr_register(env, SPR_HIOR, "SPR_HIOR", | |
6981 | SPR_NOACCESS, SPR_NOACCESS, | |
2adab7d6 BS |
6982 | &spr_read_hior, &spr_write_hior, |
6983 | 0x00000000); | |
2f462816 JM |
6984 | #if !defined(CONFIG_USER_ONLY) |
6985 | env->slb_nr = 32; | |
6986 | #endif | |
6987 | init_excp_970(env); | |
6988 | env->dcache_line_size = 128; | |
6989 | env->icache_line_size = 128; | |
6990 | /* Allocate hardware IRQ controller */ | |
6991 | ppc970_irq_init(env); | |
cf8358c8 AJ |
6992 | /* Can't find information on what this should be on reset. This |
6993 | * value is the one used by 74xx processors. */ | |
6994 | vscr_init(env, 0x00010000); | |
2f462816 JM |
6995 | } |
6996 | ||
7856e3a4 AF |
6997 | POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data) |
6998 | { | |
ca5dff0a | 6999 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
7000 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
7001 | ||
ca5dff0a | 7002 | dc->desc = "PowerPC 970 MP"; |
7856e3a4 AF |
7003 | pcc->init_proc = init_proc_970MP; |
7004 | pcc->check_pow = check_pow_970MP; | |
53116ebf AF |
7005 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | |
7006 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
7007 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
7008 | PPC_FLOAT_STFIWX | | |
7009 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
7010 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
7011 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
7012 | PPC_64B | PPC_ALTIVEC | | |
7013 | PPC_SEGMENT_64B | PPC_SLBI; | |
ba9fd9f1 AF |
7014 | pcc->msr_mask = 0x900000000204FF36ULL; |
7015 | pcc->mmu_model = POWERPC_MMU_64B; | |
b632a148 DG |
7016 | #if defined(CONFIG_SOFTMMU) |
7017 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
7018 | #endif | |
ba9fd9f1 AF |
7019 | pcc->excp_model = POWERPC_EXCP_970; |
7020 | pcc->bus_model = PPC_FLAGS_INPUT_970; | |
7021 | pcc->bfd_mach = bfd_mach_ppc64; | |
7022 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
7023 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
7024 | POWERPC_FLAG_BUS_CLK; | |
7856e3a4 AF |
7025 | } |
7026 | ||
35ebcb2b AF |
7027 | static void init_proc_power5plus(CPUPPCState *env) |
7028 | { | |
7029 | gen_spr_ne_601(env); | |
7030 | gen_spr_7xx(env); | |
7031 | /* Time base */ | |
7032 | gen_tbl(env); | |
7033 | /* Hardware implementation registers */ | |
7034 | /* XXX : not implemented */ | |
7035 | spr_register(env, SPR_HID0, "HID0", | |
7036 | SPR_NOACCESS, SPR_NOACCESS, | |
7037 | &spr_read_generic, &spr_write_clear, | |
7038 | 0x60000000); | |
7039 | /* XXX : not implemented */ | |
7040 | spr_register(env, SPR_HID1, "HID1", | |
7041 | SPR_NOACCESS, SPR_NOACCESS, | |
7042 | &spr_read_generic, &spr_write_generic, | |
7043 | 0x00000000); | |
7044 | /* XXX : not implemented */ | |
7045 | spr_register(env, SPR_750FX_HID2, "HID2", | |
7046 | SPR_NOACCESS, SPR_NOACCESS, | |
7047 | &spr_read_generic, &spr_write_generic, | |
7048 | 0x00000000); | |
7049 | /* XXX : not implemented */ | |
7050 | spr_register(env, SPR_970_HID5, "HID5", | |
7051 | SPR_NOACCESS, SPR_NOACCESS, | |
7052 | &spr_read_generic, &spr_write_generic, | |
7053 | POWERPC970_HID5_INIT); | |
7054 | /* XXX : not implemented */ | |
7055 | spr_register(env, SPR_L2CR, "L2CR", | |
7056 | SPR_NOACCESS, SPR_NOACCESS, | |
7057 | &spr_read_generic, NULL, | |
7058 | 0x00000000); | |
7059 | /* Memory management */ | |
7060 | /* XXX: not correct */ | |
7061 | gen_low_BATs(env); | |
7062 | /* XXX : not implemented */ | |
7063 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
7064 | SPR_NOACCESS, SPR_NOACCESS, | |
7065 | &spr_read_generic, SPR_NOACCESS, | |
7066 | 0x00000000); /* TOFIX */ | |
7067 | /* XXX : not implemented */ | |
7068 | spr_register(env, SPR_MMUCSR0, "MMUCSR0", | |
7069 | SPR_NOACCESS, SPR_NOACCESS, | |
7070 | &spr_read_generic, &spr_write_generic, | |
7071 | 0x00000000); /* TOFIX */ | |
7072 | spr_register(env, SPR_HIOR, "SPR_HIOR", | |
7073 | SPR_NOACCESS, SPR_NOACCESS, | |
7074 | &spr_read_hior, &spr_write_hior, | |
7075 | 0x00000000); | |
7076 | spr_register(env, SPR_CTRL, "SPR_CTRL", | |
7077 | SPR_NOACCESS, SPR_NOACCESS, | |
7078 | &spr_read_generic, &spr_write_generic, | |
7079 | 0x00000000); | |
7080 | spr_register(env, SPR_UCTRL, "SPR_UCTRL", | |
7081 | SPR_NOACCESS, SPR_NOACCESS, | |
7082 | &spr_read_generic, &spr_write_generic, | |
7083 | 0x00000000); | |
7084 | spr_register(env, SPR_VRSAVE, "SPR_VRSAVE", | |
7085 | &spr_read_generic, &spr_write_generic, | |
7086 | &spr_read_generic, &spr_write_generic, | |
7087 | 0x00000000); | |
7088 | #if !defined(CONFIG_USER_ONLY) | |
7089 | env->slb_nr = 64; | |
7090 | #endif | |
7091 | init_excp_970(env); | |
7092 | env->dcache_line_size = 128; | |
7093 | env->icache_line_size = 128; | |
7094 | /* Allocate hardware IRQ controller */ | |
7095 | ppc970_irq_init(env); | |
7096 | /* Can't find information on what this should be on reset. This | |
7097 | * value is the one used by 74xx processors. */ | |
7098 | vscr_init(env, 0x00010000); | |
7099 | } | |
7100 | ||
7101 | POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) | |
7102 | { | |
7103 | DeviceClass *dc = DEVICE_CLASS(oc); | |
7104 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
7105 | ||
7106 | dc->desc = "POWER5+"; | |
7107 | pcc->init_proc = init_proc_power5plus; | |
7108 | pcc->check_pow = check_pow_970FX; | |
7109 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | | |
7110 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
7111 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
7112 | PPC_FLOAT_STFIWX | | |
7113 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
7114 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
7115 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
7116 | PPC_64B | | |
7117 | PPC_SEGMENT_64B | PPC_SLBI; | |
7118 | pcc->msr_mask = 0x800000000204FF36ULL; | |
7119 | pcc->mmu_model = POWERPC_MMU_64B; | |
7120 | #if defined(CONFIG_SOFTMMU) | |
7121 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
7122 | #endif | |
7123 | pcc->excp_model = POWERPC_EXCP_970; | |
7124 | pcc->bus_model = PPC_FLAGS_INPUT_970; | |
7125 | pcc->bfd_mach = bfd_mach_ppc64; | |
7126 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
7127 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
7128 | POWERPC_FLAG_BUS_CLK; | |
7129 | } | |
7130 | ||
9d52e907 DG |
7131 | static void init_proc_POWER7 (CPUPPCState *env) |
7132 | { | |
7133 | gen_spr_ne_601(env); | |
7134 | gen_spr_7xx(env); | |
7135 | /* Time base */ | |
7136 | gen_tbl(env); | |
2e06214f NW |
7137 | /* Processor identification */ |
7138 | spr_register(env, SPR_PIR, "PIR", | |
7139 | SPR_NOACCESS, SPR_NOACCESS, | |
7140 | &spr_read_generic, &spr_write_pir, | |
7141 | 0x00000000); | |
9d52e907 DG |
7142 | #if !defined(CONFIG_USER_ONLY) |
7143 | /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ | |
d67d40ea DG |
7144 | spr_register_kvm(env, SPR_PURR, "PURR", |
7145 | &spr_read_purr, SPR_NOACCESS, | |
7146 | &spr_read_purr, SPR_NOACCESS, | |
7147 | KVM_REG_PPC_PURR, 0x00000000); | |
7148 | spr_register_kvm(env, SPR_SPURR, "SPURR", | |
7149 | &spr_read_purr, SPR_NOACCESS, | |
7150 | &spr_read_purr, SPR_NOACCESS, | |
7151 | KVM_REG_PPC_SPURR, 0x00000000); | |
697ab892 DG |
7152 | spr_register(env, SPR_CFAR, "SPR_CFAR", |
7153 | SPR_NOACCESS, SPR_NOACCESS, | |
7154 | &spr_read_cfar, &spr_write_cfar, | |
7155 | 0x00000000); | |
d67d40ea DG |
7156 | spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", |
7157 | SPR_NOACCESS, SPR_NOACCESS, | |
7158 | &spr_read_generic, &spr_write_generic, | |
7159 | KVM_REG_PPC_DSCR, 0x00000000); | |
702763fa DG |
7160 | spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA", |
7161 | SPR_NOACCESS, SPR_NOACCESS, | |
7162 | &spr_read_generic, &spr_write_generic, | |
7163 | KVM_REG_PPC_MMCRA, 0x00000000); | |
7164 | spr_register_kvm(env, SPR_PMC5, "SPR_PMC5", | |
7165 | SPR_NOACCESS, SPR_NOACCESS, | |
7166 | &spr_read_generic, &spr_write_generic, | |
7167 | KVM_REG_PPC_PMC5, 0x00000000); | |
7168 | spr_register_kvm(env, SPR_PMC6, "SPR_PMC6", | |
7169 | SPR_NOACCESS, SPR_NOACCESS, | |
7170 | &spr_read_generic, &spr_write_generic, | |
7171 | KVM_REG_PPC_PMC6, 0x00000000); | |
9d52e907 DG |
7172 | #endif /* !CONFIG_USER_ONLY */ |
7173 | /* Memory management */ | |
7174 | /* XXX : not implemented */ | |
7175 | spr_register(env, SPR_MMUCFG, "MMUCFG", | |
7176 | SPR_NOACCESS, SPR_NOACCESS, | |
7177 | &spr_read_generic, SPR_NOACCESS, | |
7178 | 0x00000000); /* TOFIX */ | |
f80872e2 | 7179 | gen_spr_amr(env); |
9d52e907 DG |
7180 | /* XXX : not implemented */ |
7181 | spr_register(env, SPR_CTRL, "SPR_CTRLT", | |
7182 | SPR_NOACCESS, SPR_NOACCESS, | |
7183 | &spr_read_generic, &spr_write_generic, | |
7184 | 0x80800000); | |
7185 | spr_register(env, SPR_UCTRL, "SPR_CTRLF", | |
7186 | SPR_NOACCESS, SPR_NOACCESS, | |
7187 | &spr_read_generic, &spr_write_generic, | |
7188 | 0x80800000); | |
7189 | spr_register(env, SPR_VRSAVE, "SPR_VRSAVE", | |
7190 | &spr_read_generic, &spr_write_generic, | |
7191 | &spr_read_generic, &spr_write_generic, | |
7192 | 0x00000000); | |
04559d52 AB |
7193 | spr_register(env, SPR_PPR, "PPR", |
7194 | &spr_read_generic, &spr_write_generic, | |
7195 | &spr_read_generic, &spr_write_generic, | |
7196 | 0x00000000); | |
9d52e907 DG |
7197 | #if !defined(CONFIG_USER_ONLY) |
7198 | env->slb_nr = 32; | |
7199 | #endif | |
7200 | init_excp_POWER7(env); | |
7201 | env->dcache_line_size = 128; | |
7202 | env->icache_line_size = 128; | |
0cbad81f | 7203 | |
9d52e907 DG |
7204 | /* Allocate hardware IRQ controller */ |
7205 | ppcPOWER7_irq_init(env); | |
7206 | /* Can't find information on what this should be on reset. This | |
7207 | * value is the one used by 74xx processors. */ | |
7208 | vscr_init(env, 0x00010000); | |
7209 | } | |
9d52e907 | 7210 | |
7856e3a4 AF |
7211 | POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) |
7212 | { | |
ca5dff0a | 7213 | DeviceClass *dc = DEVICE_CLASS(oc); |
7856e3a4 AF |
7214 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
7215 | ||
ca5dff0a | 7216 | dc->desc = "POWER7"; |
7856e3a4 AF |
7217 | pcc->init_proc = init_proc_POWER7; |
7218 | pcc->check_pow = check_pow_nocheck; | |
e71ec2e9 | 7219 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | |
53116ebf AF |
7220 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | |
7221 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
7222 | PPC_FLOAT_STFIWX | | |
7223 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
7224 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
7225 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
7226 | PPC_64B | PPC_ALTIVEC | | |
7227 | PPC_SEGMENT_64B | PPC_SLBI | | |
7228 | PPC_POPCNTB | PPC_POPCNTWD; | |
9c2627b0 | 7229 | pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205; |
bb429d22 | 7230 | pcc->msr_mask = 0x800000000204FF37ULL; |
ba9fd9f1 | 7231 | pcc->mmu_model = POWERPC_MMU_2_06; |
b632a148 DG |
7232 | #if defined(CONFIG_SOFTMMU) |
7233 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
7234 | #endif | |
ba9fd9f1 AF |
7235 | pcc->excp_model = POWERPC_EXCP_POWER7; |
7236 | pcc->bus_model = PPC_FLAGS_INPUT_POWER7; | |
7237 | pcc->bfd_mach = bfd_mach_ppc64; | |
7238 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
7239 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
7240 | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR; | |
0cbad81f DG |
7241 | pcc->l1_dcache_size = 0x8000; |
7242 | pcc->l1_icache_size = 0x8000; | |
7856e3a4 | 7243 | } |
8d43ea1c PS |
7244 | |
7245 | POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) | |
7246 | { | |
7247 | DeviceClass *dc = DEVICE_CLASS(oc); | |
7248 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
7249 | ||
7250 | dc->desc = "POWER8"; | |
7251 | pcc->init_proc = init_proc_POWER7; | |
7252 | pcc->check_pow = check_pow_nocheck; | |
7253 | pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | | |
7254 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | |
7255 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | |
7256 | PPC_FLOAT_STFIWX | | |
7257 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | | |
7258 | PPC_MEM_SYNC | PPC_MEM_EIEIO | | |
7259 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | | |
7260 | PPC_64B | PPC_ALTIVEC | | |
7261 | PPC_SEGMENT_64B | PPC_SLBI | | |
7262 | PPC_POPCNTB | PPC_POPCNTWD; | |
7263 | pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX; | |
7264 | pcc->msr_mask = 0x800000000204FF36ULL; | |
7265 | pcc->mmu_model = POWERPC_MMU_2_06; | |
7266 | #if defined(CONFIG_SOFTMMU) | |
7267 | pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; | |
7268 | #endif | |
7269 | pcc->excp_model = POWERPC_EXCP_POWER7; | |
7270 | pcc->bus_model = PPC_FLAGS_INPUT_POWER7; | |
7271 | pcc->bfd_mach = bfd_mach_ppc64; | |
7272 | pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | | |
7273 | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | | |
7274 | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR; | |
7275 | pcc->l1_dcache_size = 0x8000; | |
7276 | pcc->l1_icache_size = 0x8000; | |
7277 | } | |
a750fc0b JM |
7278 | #endif /* defined (TARGET_PPC64) */ |
7279 | ||
fd5ed418 | 7280 | |
a750fc0b | 7281 | /*****************************************************************************/ |
60b14d95 | 7282 | /* Generic CPU instantiation routine */ |
cfe34f44 | 7283 | static void init_ppc_proc(PowerPCCPU *cpu) |
a750fc0b | 7284 | { |
cfe34f44 AF |
7285 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
7286 | CPUPPCState *env = &cpu->env; | |
a750fc0b | 7287 | #if !defined(CONFIG_USER_ONLY) |
e1833e1f JM |
7288 | int i; |
7289 | ||
a750fc0b | 7290 | env->irq_inputs = NULL; |
e1833e1f JM |
7291 | /* Set all exception vectors to an invalid address */ |
7292 | for (i = 0; i < POWERPC_EXCP_NB; i++) | |
7293 | env->excp_vectors[i] = (target_ulong)(-1ULL); | |
e1833e1f JM |
7294 | env->ivor_mask = 0x00000000; |
7295 | env->ivpr_mask = 0x00000000; | |
a750fc0b JM |
7296 | /* Default MMU definitions */ |
7297 | env->nb_BATs = 0; | |
7298 | env->nb_tlb = 0; | |
7299 | env->nb_ways = 0; | |
1c53accc | 7300 | env->tlb_type = TLB_NONE; |
f2e63a42 | 7301 | #endif |
a750fc0b JM |
7302 | /* Register SPR common to all PowerPC implementations */ |
7303 | gen_spr_generic(env); | |
7304 | spr_register(env, SPR_PVR, "PVR", | |
a139aa17 NF |
7305 | /* Linux permits userspace to read PVR */ |
7306 | #if defined(CONFIG_LINUX_USER) | |
7307 | &spr_read_generic, | |
7308 | #else | |
7309 | SPR_NOACCESS, | |
7310 | #endif | |
7311 | SPR_NOACCESS, | |
a750fc0b | 7312 | &spr_read_generic, SPR_NOACCESS, |
cfe34f44 | 7313 | pcc->pvr); |
80d11f44 | 7314 | /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ |
cfe34f44 AF |
7315 | if (pcc->svr != POWERPC_SVR_NONE) { |
7316 | if (pcc->svr & POWERPC_SVR_E500) { | |
80d11f44 JM |
7317 | spr_register(env, SPR_E500_SVR, "SVR", |
7318 | SPR_NOACCESS, SPR_NOACCESS, | |
7319 | &spr_read_generic, SPR_NOACCESS, | |
cfe34f44 | 7320 | pcc->svr & ~POWERPC_SVR_E500); |
80d11f44 JM |
7321 | } else { |
7322 | spr_register(env, SPR_SVR, "SVR", | |
7323 | SPR_NOACCESS, SPR_NOACCESS, | |
7324 | &spr_read_generic, SPR_NOACCESS, | |
cfe34f44 | 7325 | pcc->svr); |
80d11f44 JM |
7326 | } |
7327 | } | |
a750fc0b | 7328 | /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ |
cfe34f44 | 7329 | (*pcc->init_proc)(env); |
2cf3eb6d | 7330 | |
25ba3a68 JM |
7331 | /* MSR bits & flags consistency checks */ |
7332 | if (env->msr_mask & (1 << 25)) { | |
7333 | switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { | |
7334 | case POWERPC_FLAG_SPE: | |
7335 | case POWERPC_FLAG_VRE: | |
7336 | break; | |
7337 | default: | |
7338 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7339 | "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); | |
7340 | exit(1); | |
7341 | } | |
7342 | } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { | |
7343 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7344 | "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); | |
7345 | exit(1); | |
7346 | } | |
7347 | if (env->msr_mask & (1 << 17)) { | |
7348 | switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { | |
7349 | case POWERPC_FLAG_TGPR: | |
7350 | case POWERPC_FLAG_CE: | |
7351 | break; | |
7352 | default: | |
7353 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7354 | "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); | |
7355 | exit(1); | |
7356 | } | |
7357 | } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { | |
7358 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7359 | "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); | |
7360 | exit(1); | |
7361 | } | |
7362 | if (env->msr_mask & (1 << 10)) { | |
7363 | switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | | |
7364 | POWERPC_FLAG_UBLE)) { | |
7365 | case POWERPC_FLAG_SE: | |
7366 | case POWERPC_FLAG_DWE: | |
7367 | case POWERPC_FLAG_UBLE: | |
7368 | break; | |
7369 | default: | |
7370 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7371 | "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " | |
7372 | "POWERPC_FLAG_UBLE\n"); | |
7373 | exit(1); | |
7374 | } | |
7375 | } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | | |
7376 | POWERPC_FLAG_UBLE)) { | |
7377 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7378 | "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " | |
7379 | "POWERPC_FLAG_UBLE\n"); | |
7380 | exit(1); | |
7381 | } | |
7382 | if (env->msr_mask & (1 << 9)) { | |
7383 | switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { | |
7384 | case POWERPC_FLAG_BE: | |
7385 | case POWERPC_FLAG_DE: | |
7386 | break; | |
7387 | default: | |
7388 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7389 | "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); | |
7390 | exit(1); | |
7391 | } | |
7392 | } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { | |
7393 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7394 | "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); | |
7395 | exit(1); | |
7396 | } | |
7397 | if (env->msr_mask & (1 << 2)) { | |
7398 | switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { | |
7399 | case POWERPC_FLAG_PX: | |
7400 | case POWERPC_FLAG_PMM: | |
7401 | break; | |
7402 | default: | |
7403 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7404 | "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); | |
7405 | exit(1); | |
7406 | } | |
7407 | } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { | |
7408 | fprintf(stderr, "PowerPC MSR definition inconsistency\n" | |
7409 | "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); | |
7410 | exit(1); | |
7411 | } | |
4018bae9 JM |
7412 | if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { |
7413 | fprintf(stderr, "PowerPC flags inconsistency\n" | |
7414 | "Should define the time-base and decrementer clock source\n"); | |
7415 | exit(1); | |
7416 | } | |
a750fc0b | 7417 | /* Allocate TLBs buffer when needed */ |
f2e63a42 | 7418 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
7419 | if (env->nb_tlb != 0) { |
7420 | int nb_tlb = env->nb_tlb; | |
7421 | if (env->id_tlbs != 0) | |
7422 | nb_tlb *= 2; | |
1c53accc AG |
7423 | switch (env->tlb_type) { |
7424 | case TLB_6XX: | |
7267c094 | 7425 | env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t)); |
1c53accc AG |
7426 | break; |
7427 | case TLB_EMB: | |
7267c094 | 7428 | env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t)); |
1c53accc AG |
7429 | break; |
7430 | case TLB_MAS: | |
7267c094 | 7431 | env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t)); |
1c53accc AG |
7432 | break; |
7433 | } | |
a750fc0b JM |
7434 | /* Pre-compute some useful values */ |
7435 | env->tlb_per_way = env->nb_tlb / env->nb_ways; | |
7436 | } | |
a750fc0b JM |
7437 | if (env->irq_inputs == NULL) { |
7438 | fprintf(stderr, "WARNING: no internal IRQ controller registered.\n" | |
5cbdb3a3 | 7439 | " Attempt QEMU to crash very soon !\n"); |
a750fc0b JM |
7440 | } |
7441 | #endif | |
2f462816 JM |
7442 | if (env->check_pow == NULL) { |
7443 | fprintf(stderr, "WARNING: no power management check handler " | |
7444 | "registered.\n" | |
5cbdb3a3 | 7445 | " Attempt QEMU to crash very soon !\n"); |
2f462816 | 7446 | } |
a750fc0b JM |
7447 | } |
7448 | ||
7449 | #if defined(PPC_DUMP_CPU) | |
7450 | static void dump_ppc_sprs (CPUPPCState *env) | |
7451 | { | |
7452 | ppc_spr_t *spr; | |
7453 | #if !defined(CONFIG_USER_ONLY) | |
7454 | uint32_t sr, sw; | |
7455 | #endif | |
7456 | uint32_t ur, uw; | |
7457 | int i, j, n; | |
7458 | ||
7459 | printf("Special purpose registers:\n"); | |
7460 | for (i = 0; i < 32; i++) { | |
7461 | for (j = 0; j < 32; j++) { | |
7462 | n = (i << 5) | j; | |
7463 | spr = &env->spr_cb[n]; | |
7464 | uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; | |
7465 | ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; | |
7466 | #if !defined(CONFIG_USER_ONLY) | |
7467 | sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; | |
7468 | sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; | |
7469 | if (sw || sr || uw || ur) { | |
7470 | printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", | |
7471 | (i << 5) | j, (i << 5) | j, spr->name, | |
7472 | sw ? 'w' : '-', sr ? 'r' : '-', | |
7473 | uw ? 'w' : '-', ur ? 'r' : '-'); | |
7474 | } | |
7475 | #else | |
7476 | if (uw || ur) { | |
7477 | printf("SPR: %4d (%03x) %-8s u%c%c\n", | |
7478 | (i << 5) | j, (i << 5) | j, spr->name, | |
7479 | uw ? 'w' : '-', ur ? 'r' : '-'); | |
7480 | } | |
7481 | #endif | |
7482 | } | |
7483 | } | |
7484 | fflush(stdout); | |
7485 | fflush(stderr); | |
7486 | } | |
7487 | #endif | |
7488 | ||
7489 | /*****************************************************************************/ | |
7490 | #include <stdlib.h> | |
7491 | #include <string.h> | |
7492 | ||
a750fc0b JM |
7493 | /* Opcode types */ |
7494 | enum { | |
7495 | PPC_DIRECT = 0, /* Opcode routine */ | |
7496 | PPC_INDIRECT = 1, /* Indirect opcode table */ | |
7497 | }; | |
7498 | ||
7499 | static inline int is_indirect_opcode (void *handler) | |
7500 | { | |
5724753e | 7501 | return ((uintptr_t)handler & 0x03) == PPC_INDIRECT; |
a750fc0b JM |
7502 | } |
7503 | ||
c227f099 | 7504 | static inline opc_handler_t **ind_table(void *handler) |
a750fc0b | 7505 | { |
5724753e | 7506 | return (opc_handler_t **)((uintptr_t)handler & ~3); |
a750fc0b JM |
7507 | } |
7508 | ||
7509 | /* Instruction table creation */ | |
7510 | /* Opcodes tables creation */ | |
c227f099 | 7511 | static void fill_new_table (opc_handler_t **table, int len) |
a750fc0b JM |
7512 | { |
7513 | int i; | |
7514 | ||
7515 | for (i = 0; i < len; i++) | |
7516 | table[i] = &invalid_handler; | |
7517 | } | |
7518 | ||
c227f099 | 7519 | static int create_new_table (opc_handler_t **table, unsigned char idx) |
a750fc0b | 7520 | { |
c227f099 | 7521 | opc_handler_t **tmp; |
a750fc0b | 7522 | |
b048960f | 7523 | tmp = g_malloc(0x20 * sizeof(opc_handler_t)); |
a750fc0b | 7524 | fill_new_table(tmp, 0x20); |
5724753e | 7525 | table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); |
a750fc0b JM |
7526 | |
7527 | return 0; | |
7528 | } | |
7529 | ||
c227f099 AL |
7530 | static int insert_in_table (opc_handler_t **table, unsigned char idx, |
7531 | opc_handler_t *handler) | |
a750fc0b JM |
7532 | { |
7533 | if (table[idx] != &invalid_handler) | |
7534 | return -1; | |
7535 | table[idx] = handler; | |
7536 | ||
7537 | return 0; | |
7538 | } | |
7539 | ||
c227f099 AL |
7540 | static int register_direct_insn (opc_handler_t **ppc_opcodes, |
7541 | unsigned char idx, opc_handler_t *handler) | |
a750fc0b JM |
7542 | { |
7543 | if (insert_in_table(ppc_opcodes, idx, handler) < 0) { | |
7544 | printf("*** ERROR: opcode %02x already assigned in main " | |
7545 | "opcode table\n", idx); | |
4c1b1bfe JM |
7546 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
7547 | printf(" Registered handler '%s' - new handler '%s'\n", | |
7548 | ppc_opcodes[idx]->oname, handler->oname); | |
7549 | #endif | |
a750fc0b JM |
7550 | return -1; |
7551 | } | |
7552 | ||
7553 | return 0; | |
7554 | } | |
7555 | ||
c227f099 | 7556 | static int register_ind_in_table (opc_handler_t **table, |
a750fc0b | 7557 | unsigned char idx1, unsigned char idx2, |
c227f099 | 7558 | opc_handler_t *handler) |
a750fc0b JM |
7559 | { |
7560 | if (table[idx1] == &invalid_handler) { | |
7561 | if (create_new_table(table, idx1) < 0) { | |
7562 | printf("*** ERROR: unable to create indirect table " | |
7563 | "idx=%02x\n", idx1); | |
7564 | return -1; | |
7565 | } | |
7566 | } else { | |
7567 | if (!is_indirect_opcode(table[idx1])) { | |
7568 | printf("*** ERROR: idx %02x already assigned to a direct " | |
7569 | "opcode\n", idx1); | |
4c1b1bfe JM |
7570 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
7571 | printf(" Registered handler '%s' - new handler '%s'\n", | |
7572 | ind_table(table[idx1])[idx2]->oname, handler->oname); | |
7573 | #endif | |
a750fc0b JM |
7574 | return -1; |
7575 | } | |
3a607854 | 7576 | } |
a750fc0b JM |
7577 | if (handler != NULL && |
7578 | insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { | |
7579 | printf("*** ERROR: opcode %02x already assigned in " | |
7580 | "opcode table %02x\n", idx2, idx1); | |
4c1b1bfe JM |
7581 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
7582 | printf(" Registered handler '%s' - new handler '%s'\n", | |
7583 | ind_table(table[idx1])[idx2]->oname, handler->oname); | |
7584 | #endif | |
a750fc0b | 7585 | return -1; |
3a607854 | 7586 | } |
a750fc0b JM |
7587 | |
7588 | return 0; | |
7589 | } | |
7590 | ||
c227f099 | 7591 | static int register_ind_insn (opc_handler_t **ppc_opcodes, |
a750fc0b | 7592 | unsigned char idx1, unsigned char idx2, |
c227f099 | 7593 | opc_handler_t *handler) |
a750fc0b JM |
7594 | { |
7595 | int ret; | |
7596 | ||
7597 | ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); | |
7598 | ||
7599 | return ret; | |
7600 | } | |
7601 | ||
c227f099 | 7602 | static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
a750fc0b | 7603 | unsigned char idx1, unsigned char idx2, |
c227f099 | 7604 | unsigned char idx3, opc_handler_t *handler) |
a750fc0b JM |
7605 | { |
7606 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { | |
7607 | printf("*** ERROR: unable to join indirect table idx " | |
7608 | "[%02x-%02x]\n", idx1, idx2); | |
7609 | return -1; | |
7610 | } | |
7611 | if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, | |
7612 | handler) < 0) { | |
7613 | printf("*** ERROR: unable to insert opcode " | |
7614 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); | |
7615 | return -1; | |
7616 | } | |
7617 | ||
7618 | return 0; | |
7619 | } | |
7620 | ||
c227f099 | 7621 | static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
a750fc0b JM |
7622 | { |
7623 | if (insn->opc2 != 0xFF) { | |
7624 | if (insn->opc3 != 0xFF) { | |
7625 | if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, | |
7626 | insn->opc3, &insn->handler) < 0) | |
7627 | return -1; | |
7628 | } else { | |
7629 | if (register_ind_insn(ppc_opcodes, insn->opc1, | |
7630 | insn->opc2, &insn->handler) < 0) | |
7631 | return -1; | |
7632 | } | |
7633 | } else { | |
7634 | if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) | |
7635 | return -1; | |
7636 | } | |
7637 | ||
7638 | return 0; | |
7639 | } | |
7640 | ||
c227f099 | 7641 | static int test_opcode_table (opc_handler_t **table, int len) |
a750fc0b JM |
7642 | { |
7643 | int i, count, tmp; | |
7644 | ||
7645 | for (i = 0, count = 0; i < len; i++) { | |
7646 | /* Consistency fixup */ | |
7647 | if (table[i] == NULL) | |
7648 | table[i] = &invalid_handler; | |
7649 | if (table[i] != &invalid_handler) { | |
7650 | if (is_indirect_opcode(table[i])) { | |
c227f099 | 7651 | tmp = test_opcode_table(ind_table(table[i]), 0x20); |
a750fc0b JM |
7652 | if (tmp == 0) { |
7653 | free(table[i]); | |
7654 | table[i] = &invalid_handler; | |
7655 | } else { | |
7656 | count++; | |
7657 | } | |
7658 | } else { | |
7659 | count++; | |
7660 | } | |
7661 | } | |
7662 | } | |
7663 | ||
7664 | return count; | |
7665 | } | |
7666 | ||
c227f099 | 7667 | static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
a750fc0b | 7668 | { |
c227f099 | 7669 | if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
a750fc0b JM |
7670 | printf("*** WARNING: no opcode defined !\n"); |
7671 | } | |
7672 | ||
7673 | /*****************************************************************************/ | |
2985b86b | 7674 | static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) |
a750fc0b | 7675 | { |
2985b86b AF |
7676 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
7677 | CPUPPCState *env = &cpu->env; | |
c227f099 | 7678 | opcode_t *opc; |
a750fc0b JM |
7679 | |
7680 | fill_new_table(env->opcodes, 0x40); | |
5c55ff99 | 7681 | for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { |
cfe34f44 AF |
7682 | if (((opc->handler.type & pcc->insns_flags) != 0) || |
7683 | ((opc->handler.type2 & pcc->insns_flags2) != 0)) { | |
a750fc0b | 7684 | if (register_insn(env->opcodes, opc) < 0) { |
2985b86b | 7685 | error_setg(errp, "ERROR initializing PowerPC instruction " |
312fd5f2 | 7686 | "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, |
2985b86b AF |
7687 | opc->opc3); |
7688 | return; | |
a750fc0b JM |
7689 | } |
7690 | } | |
7691 | } | |
c227f099 | 7692 | fix_opcode_tables(env->opcodes); |
a750fc0b JM |
7693 | fflush(stdout); |
7694 | fflush(stderr); | |
a750fc0b JM |
7695 | } |
7696 | ||
7697 | #if defined(PPC_DUMP_CPU) | |
25ba3a68 | 7698 | static void dump_ppc_insns (CPUPPCState *env) |
a750fc0b | 7699 | { |
c227f099 | 7700 | opc_handler_t **table, *handler; |
b55266b5 | 7701 | const char *p, *q; |
a750fc0b JM |
7702 | uint8_t opc1, opc2, opc3; |
7703 | ||
7704 | printf("Instructions set:\n"); | |
7705 | /* opc1 is 6 bits long */ | |
7706 | for (opc1 = 0x00; opc1 < 0x40; opc1++) { | |
7707 | table = env->opcodes; | |
7708 | handler = table[opc1]; | |
7709 | if (is_indirect_opcode(handler)) { | |
7710 | /* opc2 is 5 bits long */ | |
7711 | for (opc2 = 0; opc2 < 0x20; opc2++) { | |
7712 | table = env->opcodes; | |
7713 | handler = env->opcodes[opc1]; | |
7714 | table = ind_table(handler); | |
7715 | handler = table[opc2]; | |
7716 | if (is_indirect_opcode(handler)) { | |
7717 | table = ind_table(handler); | |
7718 | /* opc3 is 5 bits long */ | |
7719 | for (opc3 = 0; opc3 < 0x20; opc3++) { | |
7720 | handler = table[opc3]; | |
7721 | if (handler->handler != &gen_invalid) { | |
4c1b1bfe JM |
7722 | /* Special hack to properly dump SPE insns */ |
7723 | p = strchr(handler->oname, '_'); | |
7724 | if (p == NULL) { | |
7725 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
7726 | "%s\n", | |
7727 | opc1, opc2, opc3, opc1, | |
7728 | (opc3 << 5) | opc2, | |
7729 | handler->oname); | |
7730 | } else { | |
7731 | q = "speundef"; | |
7732 | if ((p - handler->oname) != strlen(q) || | |
7733 | memcmp(handler->oname, q, strlen(q)) != 0) { | |
7734 | /* First instruction */ | |
7735 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
7736 | "%.*s\n", | |
7737 | opc1, opc2 << 1, opc3, opc1, | |
7738 | (opc3 << 6) | (opc2 << 1), | |
7739 | (int)(p - handler->oname), | |
7740 | handler->oname); | |
7741 | } | |
7742 | if (strcmp(p + 1, q) != 0) { | |
7743 | /* Second instruction */ | |
7744 | printf("INSN: %02x %02x %02x (%02d %04d) : " | |
7745 | "%s\n", | |
7746 | opc1, (opc2 << 1) | 1, opc3, opc1, | |
7747 | (opc3 << 6) | (opc2 << 1) | 1, | |
7748 | p + 1); | |
7749 | } | |
7750 | } | |
a750fc0b JM |
7751 | } |
7752 | } | |
7753 | } else { | |
7754 | if (handler->handler != &gen_invalid) { | |
7755 | printf("INSN: %02x %02x -- (%02d %04d) : %s\n", | |
7756 | opc1, opc2, opc1, opc2, handler->oname); | |
7757 | } | |
7758 | } | |
7759 | } | |
7760 | } else { | |
7761 | if (handler->handler != &gen_invalid) { | |
7762 | printf("INSN: %02x -- -- (%02d ----) : %s\n", | |
7763 | opc1, opc1, handler->oname); | |
7764 | } | |
7765 | } | |
7766 | } | |
7767 | } | |
3a607854 | 7768 | #endif |
a750fc0b | 7769 | |
1328c2bf | 7770 | static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
24951522 AJ |
7771 | { |
7772 | if (n < 32) { | |
7773 | stfq_p(mem_buf, env->fpr[n]); | |
7774 | return 8; | |
7775 | } | |
7776 | if (n == 32) { | |
5a576fb3 | 7777 | stl_p(mem_buf, env->fpscr); |
24951522 AJ |
7778 | return 4; |
7779 | } | |
7780 | return 0; | |
7781 | } | |
7782 | ||
1328c2bf | 7783 | static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
24951522 AJ |
7784 | { |
7785 | if (n < 32) { | |
7786 | env->fpr[n] = ldfq_p(mem_buf); | |
7787 | return 8; | |
7788 | } | |
7789 | if (n == 32) { | |
d6478bc7 | 7790 | helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff); |
24951522 AJ |
7791 | return 4; |
7792 | } | |
7793 | return 0; | |
7794 | } | |
7795 | ||
1328c2bf | 7796 | static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
b4f8d821 AJ |
7797 | { |
7798 | if (n < 32) { | |
e2542fe2 | 7799 | #ifdef HOST_WORDS_BIGENDIAN |
b4f8d821 AJ |
7800 | stq_p(mem_buf, env->avr[n].u64[0]); |
7801 | stq_p(mem_buf+8, env->avr[n].u64[1]); | |
7802 | #else | |
7803 | stq_p(mem_buf, env->avr[n].u64[1]); | |
7804 | stq_p(mem_buf+8, env->avr[n].u64[0]); | |
7805 | #endif | |
7806 | return 16; | |
7807 | } | |
70976a79 | 7808 | if (n == 32) { |
b4f8d821 AJ |
7809 | stl_p(mem_buf, env->vscr); |
7810 | return 4; | |
7811 | } | |
70976a79 | 7812 | if (n == 33) { |
b4f8d821 AJ |
7813 | stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]); |
7814 | return 4; | |
7815 | } | |
7816 | return 0; | |
7817 | } | |
7818 | ||
1328c2bf | 7819 | static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
b4f8d821 AJ |
7820 | { |
7821 | if (n < 32) { | |
e2542fe2 | 7822 | #ifdef HOST_WORDS_BIGENDIAN |
b4f8d821 AJ |
7823 | env->avr[n].u64[0] = ldq_p(mem_buf); |
7824 | env->avr[n].u64[1] = ldq_p(mem_buf+8); | |
7825 | #else | |
7826 | env->avr[n].u64[1] = ldq_p(mem_buf); | |
7827 | env->avr[n].u64[0] = ldq_p(mem_buf+8); | |
7828 | #endif | |
7829 | return 16; | |
7830 | } | |
70976a79 | 7831 | if (n == 32) { |
b4f8d821 AJ |
7832 | env->vscr = ldl_p(mem_buf); |
7833 | return 4; | |
7834 | } | |
70976a79 | 7835 | if (n == 33) { |
b4f8d821 AJ |
7836 | env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); |
7837 | return 4; | |
7838 | } | |
7839 | return 0; | |
7840 | } | |
7841 | ||
1328c2bf | 7842 | static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
688890f7 AJ |
7843 | { |
7844 | if (n < 32) { | |
7845 | #if defined(TARGET_PPC64) | |
7846 | stl_p(mem_buf, env->gpr[n] >> 32); | |
7847 | #else | |
7848 | stl_p(mem_buf, env->gprh[n]); | |
7849 | #endif | |
7850 | return 4; | |
7851 | } | |
70976a79 | 7852 | if (n == 32) { |
688890f7 AJ |
7853 | stq_p(mem_buf, env->spe_acc); |
7854 | return 8; | |
7855 | } | |
70976a79 | 7856 | if (n == 33) { |
d34defbc | 7857 | stl_p(mem_buf, env->spe_fscr); |
688890f7 AJ |
7858 | return 4; |
7859 | } | |
7860 | return 0; | |
7861 | } | |
7862 | ||
1328c2bf | 7863 | static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) |
688890f7 AJ |
7864 | { |
7865 | if (n < 32) { | |
7866 | #if defined(TARGET_PPC64) | |
7867 | target_ulong lo = (uint32_t)env->gpr[n]; | |
7868 | target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32; | |
7869 | env->gpr[n] = lo | hi; | |
7870 | #else | |
7871 | env->gprh[n] = ldl_p(mem_buf); | |
7872 | #endif | |
7873 | return 4; | |
7874 | } | |
70976a79 | 7875 | if (n == 32) { |
688890f7 AJ |
7876 | env->spe_acc = ldq_p(mem_buf); |
7877 | return 8; | |
7878 | } | |
70976a79 | 7879 | if (n == 33) { |
d34defbc | 7880 | env->spe_fscr = ldl_p(mem_buf); |
688890f7 AJ |
7881 | return 4; |
7882 | } | |
7883 | return 0; | |
7884 | } | |
7885 | ||
55e5c285 | 7886 | static int ppc_fixup_cpu(PowerPCCPU *cpu) |
12b1143b | 7887 | { |
55e5c285 AF |
7888 | CPUPPCState *env = &cpu->env; |
7889 | ||
12b1143b DG |
7890 | /* TCG doesn't (yet) emulate some groups of instructions that |
7891 | * are implemented on some otherwise supported CPUs (e.g. VSX | |
7892 | * and decimal floating point instructions on POWER7). We | |
7893 | * remove unsupported instruction groups from the cpu state's | |
7894 | * instruction masks and hope the guest can cope. For at | |
7895 | * least the pseries machine, the unavailability of these | |
7896 | * instructions can be advertised to the guest via the device | |
7897 | * tree. */ | |
7898 | if ((env->insns_flags & ~PPC_TCG_INSNS) | |
7899 | || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { | |
7900 | fprintf(stderr, "Warning: Disabling some instructions which are not " | |
7901 | "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n", | |
7902 | env->insns_flags & ~PPC_TCG_INSNS, | |
7903 | env->insns_flags2 & ~PPC_TCG_INSNS2); | |
7904 | } | |
7905 | env->insns_flags &= PPC_TCG_INSNS; | |
7906 | env->insns_flags2 &= PPC_TCG_INSNS2; | |
7907 | return 0; | |
7908 | } | |
7909 | ||
4776ce60 | 7910 | static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) |
a750fc0b | 7911 | { |
22169d41 | 7912 | CPUState *cs = CPU(dev); |
4776ce60 | 7913 | PowerPCCPU *cpu = POWERPC_CPU(dev); |
2985b86b | 7914 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
2985b86b | 7915 | Error *local_err = NULL; |
fe828a4d MQ |
7916 | #if !defined(CONFIG_USER_ONLY) |
7917 | int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1; | |
7918 | #endif | |
7919 | ||
7920 | #if !defined(CONFIG_USER_ONLY) | |
7921 | if (smp_threads > max_smt) { | |
5e95acc8 AF |
7922 | error_setg(errp, "Cannot support more than %d threads on PPC with %s", |
7923 | max_smt, kvm_enabled() ? "KVM" : "TCG"); | |
7924 | return; | |
fe828a4d MQ |
7925 | } |
7926 | #endif | |
4656e1f0 | 7927 | |
12b1143b | 7928 | if (kvm_enabled()) { |
55e5c285 | 7929 | if (kvmppc_fixup_cpu(cpu) != 0) { |
2985b86b AF |
7930 | error_setg(errp, "Unable to virtualize selected CPU with KVM"); |
7931 | return; | |
12b1143b | 7932 | } |
96b3bfa0 | 7933 | } else if (tcg_enabled()) { |
55e5c285 | 7934 | if (ppc_fixup_cpu(cpu) != 0) { |
2985b86b AF |
7935 | error_setg(errp, "Unable to emulate selected CPU with TCG"); |
7936 | return; | |
12b1143b DG |
7937 | } |
7938 | } | |
7939 | ||
4d7fb187 AF |
7940 | #if defined(TARGET_PPCEMB) |
7941 | if (pcc->mmu_model != POWERPC_MMU_BOOKE) { | |
7942 | error_setg(errp, "CPU does not possess a BookE MMU. " | |
7943 | "Please use qemu-system-ppc or qemu-system-ppc64 instead " | |
7944 | "or choose another CPU model."); | |
7945 | return; | |
7946 | } | |
7947 | #endif | |
7948 | ||
2985b86b AF |
7949 | create_ppc_opcodes(cpu, &local_err); |
7950 | if (local_err != NULL) { | |
7951 | error_propagate(errp, local_err); | |
7952 | return; | |
7953 | } | |
cfe34f44 | 7954 | init_ppc_proc(cpu); |
24951522 | 7955 | |
cfe34f44 | 7956 | if (pcc->insns_flags & PPC_FLOAT) { |
22169d41 | 7957 | gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, |
24951522 AJ |
7958 | 33, "power-fpu.xml", 0); |
7959 | } | |
cfe34f44 | 7960 | if (pcc->insns_flags & PPC_ALTIVEC) { |
22169d41 | 7961 | gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, |
b4f8d821 AJ |
7962 | 34, "power-altivec.xml", 0); |
7963 | } | |
cfe34f44 | 7964 | if (pcc->insns_flags & PPC_SPE) { |
22169d41 | 7965 | gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, |
688890f7 AJ |
7966 | 34, "power-spe.xml", 0); |
7967 | } | |
7968 | ||
14a10fc3 AF |
7969 | qemu_init_vcpu(cs); |
7970 | ||
4776ce60 AF |
7971 | pcc->parent_realize(dev, errp); |
7972 | ||
a750fc0b | 7973 | #if defined(PPC_DUMP_CPU) |
3a607854 | 7974 | { |
22169d41 | 7975 | CPUPPCState *env = &cpu->env; |
b55266b5 | 7976 | const char *mmu_model, *excp_model, *bus_model; |
a750fc0b JM |
7977 | switch (env->mmu_model) { |
7978 | case POWERPC_MMU_32B: | |
7979 | mmu_model = "PowerPC 32"; | |
7980 | break; | |
a750fc0b JM |
7981 | case POWERPC_MMU_SOFT_6xx: |
7982 | mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; | |
7983 | break; | |
7984 | case POWERPC_MMU_SOFT_74xx: | |
7985 | mmu_model = "PowerPC 74xx with software driven TLBs"; | |
7986 | break; | |
7987 | case POWERPC_MMU_SOFT_4xx: | |
7988 | mmu_model = "PowerPC 4xx with software driven TLBs"; | |
7989 | break; | |
7990 | case POWERPC_MMU_SOFT_4xx_Z: | |
7991 | mmu_model = "PowerPC 4xx with software driven TLBs " | |
7992 | "and zones protections"; | |
7993 | break; | |
b4095fed JM |
7994 | case POWERPC_MMU_REAL: |
7995 | mmu_model = "PowerPC real mode only"; | |
7996 | break; | |
7997 | case POWERPC_MMU_MPC8xx: | |
7998 | mmu_model = "PowerPC MPC8xx"; | |
a750fc0b JM |
7999 | break; |
8000 | case POWERPC_MMU_BOOKE: | |
8001 | mmu_model = "PowerPC BookE"; | |
8002 | break; | |
01662f3e AG |
8003 | case POWERPC_MMU_BOOKE206: |
8004 | mmu_model = "PowerPC BookE 2.06"; | |
a750fc0b | 8005 | break; |
b4095fed JM |
8006 | case POWERPC_MMU_601: |
8007 | mmu_model = "PowerPC 601"; | |
8008 | break; | |
00af685f JM |
8009 | #if defined (TARGET_PPC64) |
8010 | case POWERPC_MMU_64B: | |
8011 | mmu_model = "PowerPC 64"; | |
8012 | break; | |
00af685f | 8013 | #endif |
a750fc0b JM |
8014 | default: |
8015 | mmu_model = "Unknown or invalid"; | |
8016 | break; | |
8017 | } | |
8018 | switch (env->excp_model) { | |
8019 | case POWERPC_EXCP_STD: | |
8020 | excp_model = "PowerPC"; | |
8021 | break; | |
8022 | case POWERPC_EXCP_40x: | |
8023 | excp_model = "PowerPC 40x"; | |
8024 | break; | |
8025 | case POWERPC_EXCP_601: | |
8026 | excp_model = "PowerPC 601"; | |
8027 | break; | |
8028 | case POWERPC_EXCP_602: | |
8029 | excp_model = "PowerPC 602"; | |
8030 | break; | |
8031 | case POWERPC_EXCP_603: | |
8032 | excp_model = "PowerPC 603"; | |
8033 | break; | |
8034 | case POWERPC_EXCP_603E: | |
8035 | excp_model = "PowerPC 603e"; | |
8036 | break; | |
8037 | case POWERPC_EXCP_604: | |
8038 | excp_model = "PowerPC 604"; | |
8039 | break; | |
8040 | case POWERPC_EXCP_7x0: | |
8041 | excp_model = "PowerPC 740/750"; | |
8042 | break; | |
8043 | case POWERPC_EXCP_7x5: | |
8044 | excp_model = "PowerPC 745/755"; | |
8045 | break; | |
8046 | case POWERPC_EXCP_74xx: | |
8047 | excp_model = "PowerPC 74xx"; | |
8048 | break; | |
a750fc0b JM |
8049 | case POWERPC_EXCP_BOOKE: |
8050 | excp_model = "PowerPC BookE"; | |
8051 | break; | |
00af685f JM |
8052 | #if defined (TARGET_PPC64) |
8053 | case POWERPC_EXCP_970: | |
8054 | excp_model = "PowerPC 970"; | |
8055 | break; | |
8056 | #endif | |
a750fc0b JM |
8057 | default: |
8058 | excp_model = "Unknown or invalid"; | |
8059 | break; | |
8060 | } | |
8061 | switch (env->bus_model) { | |
8062 | case PPC_FLAGS_INPUT_6xx: | |
8063 | bus_model = "PowerPC 6xx"; | |
8064 | break; | |
8065 | case PPC_FLAGS_INPUT_BookE: | |
8066 | bus_model = "PowerPC BookE"; | |
8067 | break; | |
8068 | case PPC_FLAGS_INPUT_405: | |
8069 | bus_model = "PowerPC 405"; | |
8070 | break; | |
a750fc0b JM |
8071 | case PPC_FLAGS_INPUT_401: |
8072 | bus_model = "PowerPC 401/403"; | |
8073 | break; | |
b4095fed JM |
8074 | case PPC_FLAGS_INPUT_RCPU: |
8075 | bus_model = "RCPU / MPC8xx"; | |
8076 | break; | |
00af685f JM |
8077 | #if defined (TARGET_PPC64) |
8078 | case PPC_FLAGS_INPUT_970: | |
8079 | bus_model = "PowerPC 970"; | |
8080 | break; | |
8081 | #endif | |
a750fc0b JM |
8082 | default: |
8083 | bus_model = "Unknown or invalid"; | |
8084 | break; | |
8085 | } | |
8086 | printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" | |
8087 | " MMU model : %s\n", | |
cfe34f44 | 8088 | pcc->name, pcc->pvr, pcc->msr_mask, mmu_model); |
f2e63a42 | 8089 | #if !defined(CONFIG_USER_ONLY) |
a750fc0b JM |
8090 | if (env->tlb != NULL) { |
8091 | printf(" %d %s TLB in %d ways\n", | |
8092 | env->nb_tlb, env->id_tlbs ? "splitted" : "merged", | |
8093 | env->nb_ways); | |
8094 | } | |
f2e63a42 | 8095 | #endif |
a750fc0b JM |
8096 | printf(" Exceptions model : %s\n" |
8097 | " Bus model : %s\n", | |
8098 | excp_model, bus_model); | |
25ba3a68 JM |
8099 | printf(" MSR features :\n"); |
8100 | if (env->flags & POWERPC_FLAG_SPE) | |
8101 | printf(" signal processing engine enable" | |
8102 | "\n"); | |
8103 | else if (env->flags & POWERPC_FLAG_VRE) | |
8104 | printf(" vector processor enable\n"); | |
8105 | if (env->flags & POWERPC_FLAG_TGPR) | |
8106 | printf(" temporary GPRs\n"); | |
8107 | else if (env->flags & POWERPC_FLAG_CE) | |
8108 | printf(" critical input enable\n"); | |
8109 | if (env->flags & POWERPC_FLAG_SE) | |
8110 | printf(" single-step trace mode\n"); | |
8111 | else if (env->flags & POWERPC_FLAG_DWE) | |
8112 | printf(" debug wait enable\n"); | |
8113 | else if (env->flags & POWERPC_FLAG_UBLE) | |
8114 | printf(" user BTB lock enable\n"); | |
8115 | if (env->flags & POWERPC_FLAG_BE) | |
8116 | printf(" branch-step trace mode\n"); | |
8117 | else if (env->flags & POWERPC_FLAG_DE) | |
8118 | printf(" debug interrupt enable\n"); | |
8119 | if (env->flags & POWERPC_FLAG_PX) | |
8120 | printf(" inclusive protection\n"); | |
8121 | else if (env->flags & POWERPC_FLAG_PMM) | |
8122 | printf(" performance monitor mark\n"); | |
8123 | if (env->flags == POWERPC_FLAG_NONE) | |
8124 | printf(" none\n"); | |
4018bae9 JM |
8125 | printf(" Time-base/decrementer clock source: %s\n", |
8126 | env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); | |
22169d41 AF |
8127 | dump_ppc_insns(env); |
8128 | dump_ppc_sprs(env); | |
8129 | fflush(stdout); | |
a750fc0b | 8130 | } |
3a607854 | 8131 | #endif |
a750fc0b | 8132 | } |
3fc6c082 | 8133 | |
b048960f AF |
8134 | static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp) |
8135 | { | |
8136 | PowerPCCPU *cpu = POWERPC_CPU(dev); | |
8137 | CPUPPCState *env = &cpu->env; | |
8138 | int i; | |
8139 | ||
8140 | for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { | |
8141 | if (env->opcodes[i] != &invalid_handler) { | |
8142 | g_free(env->opcodes[i]); | |
8143 | } | |
8144 | } | |
8145 | } | |
8146 | ||
2985b86b | 8147 | static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) |
f0ad8c34 | 8148 | { |
2985b86b AF |
8149 | ObjectClass *oc = (ObjectClass *)a; |
8150 | uint32_t pvr = *(uint32_t *)b; | |
8151 | PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; | |
8152 | ||
8153 | /* -cpu host does a PVR lookup during construction */ | |
8154 | if (unlikely(strcmp(object_class_get_name(oc), | |
8155 | TYPE_HOST_POWERPC_CPU) == 0)) { | |
8156 | return -1; | |
f0ad8c34 | 8157 | } |
f0ad8c34 | 8158 | |
4d7fb187 AF |
8159 | #if defined(TARGET_PPCEMB) |
8160 | if (pcc->mmu_model != POWERPC_MMU_BOOKE) { | |
8161 | return -1; | |
8162 | } | |
8163 | #endif | |
8164 | ||
cfe34f44 | 8165 | return pcc->pvr == pvr ? 0 : -1; |
f0ad8c34 AG |
8166 | } |
8167 | ||
2985b86b | 8168 | PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) |
3fc6c082 | 8169 | { |
2985b86b AF |
8170 | GSList *list, *item; |
8171 | PowerPCCPUClass *pcc = NULL; | |
be40edcd | 8172 | |
2985b86b AF |
8173 | list = object_class_get_list(TYPE_POWERPC_CPU, false); |
8174 | item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); | |
8175 | if (item != NULL) { | |
8176 | pcc = POWERPC_CPU_CLASS(item->data); | |
3fc6c082 | 8177 | } |
2985b86b AF |
8178 | g_slist_free(list); |
8179 | ||
8180 | return pcc; | |
8181 | } | |
8182 | ||
8183 | static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b) | |
8184 | { | |
8185 | ObjectClass *oc = (ObjectClass *)a; | |
8186 | const char *name = b; | |
4d7fb187 AF |
8187 | #if defined(TARGET_PPCEMB) |
8188 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
8189 | #endif | |
ee4e83ed | 8190 | |
2985b86b | 8191 | if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 && |
4d7fb187 AF |
8192 | #if defined(TARGET_PPCEMB) |
8193 | pcc->mmu_model == POWERPC_MMU_BOOKE && | |
8194 | #endif | |
2985b86b AF |
8195 | strcmp(object_class_get_name(oc) + strlen(name), |
8196 | "-" TYPE_POWERPC_CPU) == 0) { | |
8197 | return 0; | |
8198 | } | |
8199 | return -1; | |
3fc6c082 FB |
8200 | } |
8201 | ||
ee4e83ed | 8202 | #include <ctype.h> |
3fc6c082 | 8203 | |
9761ad75 AG |
8204 | static ObjectClass *ppc_cpu_class_by_name(const char *name); |
8205 | ||
8206 | static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias) | |
8207 | { | |
8208 | ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias; | |
8209 | ||
8210 | /* Cache target class lookups in the alias table */ | |
8211 | if (!alias->oc) { | |
8212 | alias->oc = ppc_cpu_class_by_name(alias->model); | |
8213 | if (!alias->oc) { | |
8214 | /* Fast check for non-existing aliases */ | |
8215 | alias->oc = invalid_class; | |
8216 | } | |
8217 | } | |
8218 | ||
8219 | if (alias->oc == invalid_class) { | |
8220 | return NULL; | |
8221 | } else { | |
8222 | return alias->oc; | |
8223 | } | |
8224 | } | |
8225 | ||
2985b86b | 8226 | static ObjectClass *ppc_cpu_class_by_name(const char *name) |
ee4e83ed | 8227 | { |
2985b86b AF |
8228 | GSList *list, *item; |
8229 | ObjectClass *ret = NULL; | |
b55266b5 | 8230 | const char *p; |
2985b86b | 8231 | int i, len; |
ee4e83ed JM |
8232 | |
8233 | /* Check if the given name is a PVR */ | |
8234 | len = strlen(name); | |
8235 | if (len == 10 && name[0] == '0' && name[1] == 'x') { | |
8236 | p = name + 2; | |
8237 | goto check_pvr; | |
8238 | } else if (len == 8) { | |
8239 | p = name; | |
8240 | check_pvr: | |
8241 | for (i = 0; i < 8; i++) { | |
cd390083 | 8242 | if (!qemu_isxdigit(*p++)) |
ee4e83ed JM |
8243 | break; |
8244 | } | |
2985b86b AF |
8245 | if (i == 8) { |
8246 | ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16))); | |
8247 | return ret; | |
f0ad8c34 | 8248 | } |
2985b86b | 8249 | } |
f0ad8c34 | 8250 | |
e9a96075 | 8251 | for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { |
fd5ed418 | 8252 | if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) { |
9761ad75 | 8253 | return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]); |
fd5ed418 AF |
8254 | } |
8255 | } | |
8256 | ||
2985b86b AF |
8257 | list = object_class_get_list(TYPE_POWERPC_CPU, false); |
8258 | item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name); | |
8259 | if (item != NULL) { | |
8260 | ret = OBJECT_CLASS(item->data); | |
3fc6c082 | 8261 | } |
2985b86b | 8262 | g_slist_free(list); |
ee4e83ed JM |
8263 | |
8264 | return ret; | |
3fc6c082 FB |
8265 | } |
8266 | ||
2985b86b | 8267 | PowerPCCPU *cpu_ppc_init(const char *cpu_model) |
3fc6c082 | 8268 | { |
2985b86b | 8269 | PowerPCCPU *cpu; |
2985b86b AF |
8270 | ObjectClass *oc; |
8271 | Error *err = NULL; | |
3fc6c082 | 8272 | |
2985b86b AF |
8273 | oc = ppc_cpu_class_by_name(cpu_model); |
8274 | if (oc == NULL) { | |
8275 | return NULL; | |
8276 | } | |
f0ad8c34 | 8277 | |
2985b86b | 8278 | cpu = POWERPC_CPU(object_new(object_class_get_name(oc))); |
2985b86b | 8279 | |
4776ce60 | 8280 | object_property_set_bool(OBJECT(cpu), true, "realized", &err); |
2985b86b | 8281 | if (err != NULL) { |
4a44d85e | 8282 | error_report("%s", error_get_pretty(err)); |
2985b86b | 8283 | error_free(err); |
5c099537 | 8284 | object_unref(OBJECT(cpu)); |
2985b86b AF |
8285 | return NULL; |
8286 | } | |
8287 | ||
8288 | return cpu; | |
8289 | } | |
8290 | ||
8291 | /* Sort by PVR, ordering special case "host" last. */ | |
8292 | static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) | |
8293 | { | |
8294 | ObjectClass *oc_a = (ObjectClass *)a; | |
8295 | ObjectClass *oc_b = (ObjectClass *)b; | |
8296 | PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); | |
8297 | PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); | |
8298 | const char *name_a = object_class_get_name(oc_a); | |
8299 | const char *name_b = object_class_get_name(oc_b); | |
8300 | ||
8301 | if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { | |
8302 | return 1; | |
8303 | } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { | |
8304 | return -1; | |
8305 | } else { | |
8306 | /* Avoid an integer overflow during subtraction */ | |
cfe34f44 | 8307 | if (pcc_a->pvr < pcc_b->pvr) { |
2985b86b | 8308 | return -1; |
cfe34f44 | 8309 | } else if (pcc_a->pvr > pcc_b->pvr) { |
2985b86b AF |
8310 | return 1; |
8311 | } else { | |
8312 | return 0; | |
8313 | } | |
8314 | } | |
8315 | } | |
8316 | ||
8317 | static void ppc_cpu_list_entry(gpointer data, gpointer user_data) | |
8318 | { | |
8319 | ObjectClass *oc = data; | |
8320 | CPUListState *s = user_data; | |
8321 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
de400129 AF |
8322 | const char *typename = object_class_get_name(oc); |
8323 | char *name; | |
55d3d1a4 | 8324 | int i; |
2985b86b | 8325 | |
4d7fb187 AF |
8326 | #if defined(TARGET_PPCEMB) |
8327 | if (pcc->mmu_model != POWERPC_MMU_BOOKE) { | |
8328 | return; | |
8329 | } | |
8330 | #endif | |
5ba4576b AF |
8331 | if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { |
8332 | return; | |
8333 | } | |
4d7fb187 | 8334 | |
de400129 AF |
8335 | name = g_strndup(typename, |
8336 | strlen(typename) - strlen("-" TYPE_POWERPC_CPU)); | |
2985b86b | 8337 | (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n", |
cfe34f44 | 8338 | name, pcc->pvr); |
e9a96075 | 8339 | for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { |
9761ad75 AG |
8340 | PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; |
8341 | ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias); | |
55d3d1a4 AF |
8342 | |
8343 | if (alias_oc != oc) { | |
8344 | continue; | |
8345 | } | |
8346 | (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n", | |
8347 | alias->alias, name); | |
8348 | } | |
de400129 | 8349 | g_free(name); |
2985b86b AF |
8350 | } |
8351 | ||
8352 | void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
8353 | { | |
8354 | CPUListState s = { | |
8355 | .file = f, | |
8356 | .cpu_fprintf = cpu_fprintf, | |
8357 | }; | |
8358 | GSList *list; | |
8359 | ||
8360 | list = object_class_get_list(TYPE_POWERPC_CPU, false); | |
8361 | list = g_slist_sort(list, ppc_cpu_list_compare); | |
8362 | g_slist_foreach(list, ppc_cpu_list_entry, &s); | |
8363 | g_slist_free(list); | |
fd5ed418 | 8364 | |
5ba4576b AF |
8365 | #ifdef CONFIG_KVM |
8366 | cpu_fprintf(f, "\n"); | |
8367 | cpu_fprintf(f, "PowerPC %-16s\n", "host"); | |
8368 | #endif | |
2985b86b AF |
8369 | } |
8370 | ||
8371 | static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) | |
8372 | { | |
8373 | ObjectClass *oc = data; | |
8374 | CpuDefinitionInfoList **first = user_data; | |
de400129 | 8375 | const char *typename; |
2985b86b AF |
8376 | CpuDefinitionInfoList *entry; |
8377 | CpuDefinitionInfo *info; | |
4d7fb187 AF |
8378 | #if defined(TARGET_PPCEMB) |
8379 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
8380 | ||
8381 | if (pcc->mmu_model != POWERPC_MMU_BOOKE) { | |
8382 | return; | |
8383 | } | |
8384 | #endif | |
2985b86b | 8385 | |
de400129 | 8386 | typename = object_class_get_name(oc); |
2985b86b | 8387 | info = g_malloc0(sizeof(*info)); |
de400129 AF |
8388 | info->name = g_strndup(typename, |
8389 | strlen(typename) - strlen("-" TYPE_POWERPC_CPU)); | |
2985b86b AF |
8390 | |
8391 | entry = g_malloc0(sizeof(*entry)); | |
8392 | entry->value = info; | |
8393 | entry->next = *first; | |
8394 | *first = entry; | |
3fc6c082 | 8395 | } |
1d0cb67d | 8396 | |
76b64a7a | 8397 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) |
70b7660a AL |
8398 | { |
8399 | CpuDefinitionInfoList *cpu_list = NULL; | |
2985b86b | 8400 | GSList *list; |
35e21d3f | 8401 | int i; |
70b7660a | 8402 | |
2985b86b AF |
8403 | list = object_class_get_list(TYPE_POWERPC_CPU, false); |
8404 | g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); | |
8405 | g_slist_free(list); | |
70b7660a | 8406 | |
e9a96075 | 8407 | for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { |
9761ad75 | 8408 | PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; |
35e21d3f AF |
8409 | ObjectClass *oc; |
8410 | CpuDefinitionInfoList *entry; | |
8411 | CpuDefinitionInfo *info; | |
8412 | ||
9761ad75 | 8413 | oc = ppc_cpu_class_by_alias(alias); |
35e21d3f AF |
8414 | if (oc == NULL) { |
8415 | continue; | |
8416 | } | |
8417 | ||
8418 | info = g_malloc0(sizeof(*info)); | |
8419 | info->name = g_strdup(alias->alias); | |
8420 | ||
8421 | entry = g_malloc0(sizeof(*entry)); | |
8422 | entry->value = info; | |
8423 | entry->next = cpu_list; | |
8424 | cpu_list = entry; | |
8425 | } | |
8426 | ||
2985b86b AF |
8427 | return cpu_list; |
8428 | } | |
70b7660a | 8429 | |
f45748f1 AF |
8430 | static void ppc_cpu_set_pc(CPUState *cs, vaddr value) |
8431 | { | |
8432 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
8433 | ||
8434 | cpu->env.nip = value; | |
8435 | } | |
8436 | ||
1d0cb67d AF |
8437 | /* CPUClass::reset() */ |
8438 | static void ppc_cpu_reset(CPUState *s) | |
8439 | { | |
8440 | PowerPCCPU *cpu = POWERPC_CPU(s); | |
8441 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
8442 | CPUPPCState *env = &cpu->env; | |
a1389542 AF |
8443 | target_ulong msr; |
8444 | ||
1d0cb67d AF |
8445 | pcc->parent_reset(s); |
8446 | ||
a1389542 AF |
8447 | msr = (target_ulong)0; |
8448 | if (0) { | |
8449 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
8450 | msr |= (target_ulong)MSR_HVB; | |
8451 | } | |
8452 | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ | |
8453 | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ | |
8454 | msr |= (target_ulong)1 << MSR_EP; | |
8455 | #if defined(DO_SINGLE_STEP) && 0 | |
8456 | /* Single step trace mode */ | |
8457 | msr |= (target_ulong)1 << MSR_SE; | |
8458 | msr |= (target_ulong)1 << MSR_BE; | |
8459 | #endif | |
8460 | #if defined(CONFIG_USER_ONLY) | |
8461 | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ | |
8462 | msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ | |
8463 | msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ | |
8464 | msr |= (target_ulong)1 << MSR_PR; | |
a1389542 | 8465 | #endif |
2cf3eb6d | 8466 | |
a1389542 AF |
8467 | #if defined(TARGET_PPC64) |
8468 | if (env->mmu_model & POWERPC_MMU_64) { | |
8469 | env->msr |= (1ULL << MSR_SF); | |
8470 | } | |
8471 | #endif | |
2cf3eb6d FC |
8472 | |
8473 | hreg_store_msr(env, msr, 1); | |
8474 | ||
8475 | #if !defined(CONFIG_USER_ONLY) | |
8476 | env->nip = env->hreset_vector | env->excp_prefix; | |
8477 | if (env->mmu_model != POWERPC_MMU_REAL) { | |
8478 | ppc_tlb_invalidate_all(env); | |
8479 | } | |
8480 | #endif | |
8481 | ||
a1389542 AF |
8482 | hreg_compute_hflags(env); |
8483 | env->reserve_addr = (target_ulong)-1ULL; | |
8484 | /* Be sure no exception or interrupt is pending */ | |
8485 | env->pending_interrupts = 0; | |
8486 | env->exception_index = POWERPC_EXCP_NONE; | |
8487 | env->error_code = 0; | |
2b15811c DG |
8488 | |
8489 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
1bfb37d1 DG |
8490 | env->vpa_addr = 0; |
8491 | env->slb_shadow_addr = 0; | |
8492 | env->slb_shadow_size = 0; | |
8493 | env->dtl_addr = 0; | |
2b15811c DG |
8494 | env->dtl_size = 0; |
8495 | #endif /* TARGET_PPC64 */ | |
8496 | ||
a1389542 AF |
8497 | /* Flush all TLBs */ |
8498 | tlb_flush(env, 1); | |
1d0cb67d AF |
8499 | } |
8500 | ||
6cca7ad6 AF |
8501 | static void ppc_cpu_initfn(Object *obj) |
8502 | { | |
c05efcb1 | 8503 | CPUState *cs = CPU(obj); |
6cca7ad6 | 8504 | PowerPCCPU *cpu = POWERPC_CPU(obj); |
2985b86b | 8505 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
6cca7ad6 AF |
8506 | CPUPPCState *env = &cpu->env; |
8507 | ||
c05efcb1 | 8508 | cs->env_ptr = env; |
6cca7ad6 | 8509 | cpu_exec_init(env); |
2985b86b | 8510 | |
cfe34f44 AF |
8511 | env->msr_mask = pcc->msr_mask; |
8512 | env->mmu_model = pcc->mmu_model; | |
8513 | env->excp_model = pcc->excp_model; | |
8514 | env->bus_model = pcc->bus_model; | |
8515 | env->insns_flags = pcc->insns_flags; | |
8516 | env->insns_flags2 = pcc->insns_flags2; | |
8517 | env->flags = pcc->flags; | |
8518 | env->bfd_mach = pcc->bfd_mach; | |
8519 | env->check_pow = pcc->check_pow; | |
2985b86b AF |
8520 | |
8521 | #if defined(TARGET_PPC64) | |
cfe34f44 AF |
8522 | if (pcc->sps) { |
8523 | env->sps = *pcc->sps; | |
2985b86b AF |
8524 | } else if (env->mmu_model & POWERPC_MMU_64) { |
8525 | /* Use default sets of page sizes */ | |
8526 | static const struct ppc_segment_page_sizes defsps = { | |
8527 | .sps = { | |
8528 | { .page_shift = 12, /* 4K */ | |
8529 | .slb_enc = 0, | |
8530 | .enc = { { .page_shift = 12, .pte_enc = 0 } } | |
8531 | }, | |
8532 | { .page_shift = 24, /* 16M */ | |
8533 | .slb_enc = 0x100, | |
8534 | .enc = { { .page_shift = 24, .pte_enc = 0 } } | |
8535 | }, | |
8536 | }, | |
8537 | }; | |
8538 | env->sps = defsps; | |
8539 | } | |
8540 | #endif /* defined(TARGET_PPC64) */ | |
60925d26 AF |
8541 | |
8542 | if (tcg_enabled()) { | |
8543 | ppc_translate_init(); | |
8544 | } | |
6cca7ad6 AF |
8545 | } |
8546 | ||
1d0cb67d AF |
8547 | static void ppc_cpu_class_init(ObjectClass *oc, void *data) |
8548 | { | |
8549 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
8550 | CPUClass *cc = CPU_CLASS(oc); | |
4776ce60 AF |
8551 | DeviceClass *dc = DEVICE_CLASS(oc); |
8552 | ||
8553 | pcc->parent_realize = dc->realize; | |
8554 | dc->realize = ppc_cpu_realizefn; | |
b048960f | 8555 | dc->unrealize = ppc_cpu_unrealizefn; |
1d0cb67d AF |
8556 | |
8557 | pcc->parent_reset = cc->reset; | |
8558 | cc->reset = ppc_cpu_reset; | |
2b8c2754 AF |
8559 | |
8560 | cc->class_by_name = ppc_cpu_class_by_name; | |
97a8ea5a | 8561 | cc->do_interrupt = ppc_cpu_do_interrupt; |
878096ee AF |
8562 | cc->dump_state = ppc_cpu_dump_state; |
8563 | cc->dump_statistics = ppc_cpu_dump_statistics; | |
f45748f1 | 8564 | cc->set_pc = ppc_cpu_set_pc; |
5b50e790 AF |
8565 | cc->gdb_read_register = ppc_cpu_gdb_read_register; |
8566 | cc->gdb_write_register = ppc_cpu_gdb_write_register; | |
00b941e5 AF |
8567 | #ifndef CONFIG_USER_ONLY |
8568 | cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; | |
a90db158 | 8569 | cc->vmsd = &vmstate_ppc_cpu; |
00b941e5 | 8570 | #endif |
a0e372f0 AF |
8571 | |
8572 | cc->gdb_num_core_regs = 71; | |
5b24c641 AF |
8573 | #if defined(TARGET_PPC64) |
8574 | cc->gdb_core_xml_file = "power64-core.xml"; | |
8575 | #else | |
8576 | cc->gdb_core_xml_file = "power-core.xml"; | |
8577 | #endif | |
1d0cb67d AF |
8578 | } |
8579 | ||
8580 | static const TypeInfo ppc_cpu_type_info = { | |
8581 | .name = TYPE_POWERPC_CPU, | |
8582 | .parent = TYPE_CPU, | |
8583 | .instance_size = sizeof(PowerPCCPU), | |
6cca7ad6 | 8584 | .instance_init = ppc_cpu_initfn, |
2985b86b | 8585 | .abstract = true, |
1d0cb67d AF |
8586 | .class_size = sizeof(PowerPCCPUClass), |
8587 | .class_init = ppc_cpu_class_init, | |
8588 | }; | |
8589 | ||
8590 | static void ppc_cpu_register_types(void) | |
8591 | { | |
8592 | type_register_static(&ppc_cpu_type_info); | |
8593 | } | |
8594 | ||
8595 | type_init(ppc_cpu_register_types) |