[qemu.git] / target-sh4 / cpu.h

/*
 *  SH4 emulation
 *
 *  Copyright (c) 2005 Samuel Tardieu
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef _CPU_SH4_H
#define _CPU_SH4_H

#include "config.h"

#define TARGET_LONG_BITS 32
#define TARGET_HAS_ICE 1

#define ELF_MACHINE	EM_SH

/* CPU Subtypes */
#define SH_CPU_SH7750  (1 << 0)
#define SH_CPU_SH7750S (1 << 1)
#define SH_CPU_SH7750R (1 << 2)
#define SH_CPU_SH7751  (1 << 3)
#define SH_CPU_SH7751R (1 << 4)
#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_PAGE_BITS 12	/* 4k XXXXX */

#define SR_MD (1 << 30)
#define SR_RB (1 << 29)
#define SR_BL (1 << 28)
#define SR_FD (1 << 15)
#define SR_M  (1 << 9)
#define SR_Q  (1 << 8)
#define SR_S  (1 << 1)
#define SR_T  (1 << 0)

#define FPSCR_FR (1 << 21)
#define FPSCR_SZ (1 << 20)
#define FPSCR_PR (1 << 19)
#define FPSCR_DN (1 << 18)
#define DELAY_SLOT             (1 << 0)
#define DELAY_SLOT_CONDITIONAL (1 << 1)
#define DELAY_SLOT_TRUE        (1 << 2)
#define DELAY_SLOT_CLEARME     (1 << 3)
/* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
 * after the delay slot should be taken or not. It is calculated from SR_T.
 *
 * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
 */

/* XXXXX The structure could be made more compact */
typedef struct tlb_t {
    uint8_t asid;		/* address space identifier */
    uint32_t vpn;		/* virtual page number */
    uint8_t v;			/* validity */
    uint32_t ppn;		/* physical page number */
    uint8_t sz;			/* page size */
    uint32_t size;		/* cached page size in bytes */
    uint8_t sh;			/* share status */
    uint8_t c;			/* cacheability */
    uint8_t pr;			/* protection key */
    uint8_t d;			/* dirty */
    uint8_t wt;			/* write through */
    uint8_t sa;			/* space attribute (PCMCIA) */
    uint8_t tc;			/* timing control */
} tlb_t;

#define UTLB_SIZE 64
#define ITLB_SIZE 4

#define NB_MMU_MODES 2

typedef struct CPUSH4State {
    int id;			/* CPU model */

    uint32_t flags;		/* general execution flags */
    uint32_t gregs[24];		/* general registers */
    float32 fregs[32];		/* floating point registers */
    uint32_t sr;		/* status register */
    uint32_t ssr;		/* saved status register */
    uint32_t spc;		/* saved program counter */
    uint32_t gbr;		/* global base register */
    uint32_t vbr;		/* vector base register */
    uint32_t sgr;		/* saved global register 15 */
    uint32_t dbr;		/* debug base register */
    uint32_t pc;		/* program counter */
    uint32_t delayed_pc;	/* target of delayed jump */
    uint32_t mach;		/* multiply and accumulate high */
    uint32_t macl;		/* multiply and accumulate low */
    uint32_t pr;		/* procedure register */
    uint32_t fpscr;		/* floating point status/control register */
    uint32_t fpul;		/* floating point communication register */

    /* float point status register */
    float_status fp_status;

    /* Those belong to the specific unit (SH7750) but are handled here */
    uint32_t mmucr;		/* MMU control register */
    uint32_t pteh;		/* page table entry high register */
    uint32_t ptel;		/* page table entry low register */
    uint32_t ptea;		/* page table entry assistance register */
    uint32_t ttb;		/* tranlation table base register */
    uint32_t tea;		/* TLB exception address register */
    uint32_t tra;		/* TRAPA exception register */
    uint32_t expevt;		/* exception event register */
    uint32_t intevt;		/* interrupt event register */

    uint32_t pvr;		/* Processor Version Register */
    uint32_t prr;		/* Processor Revision Register */
    uint32_t cvr;		/* Cache Version Register */

     CPU_COMMON tlb_t utlb[UTLB_SIZE];	/* unified translation table */
    tlb_t itlb[ITLB_SIZE];	/* instruction translation table */
    void *intc_handle;
    int intr_at_halt;		/* SR_BL ignored during sleep */
} CPUSH4State;

CPUSH4State *cpu_sh4_init(const char *cpu_model);
int cpu_sh4_exec(CPUSH4State * s);
int cpu_sh4_signal_handler(int host_signum, void *pinfo,
                           void *puc);
int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
			     int mmu_idx, int is_softmmu);
void do_interrupt(CPUSH4State * env);

void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
				    uint32_t mem_value);

static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
{
  env->gbr = newtls;
}

#include "softfloat.h"

#define CPUState CPUSH4State
#define cpu_init cpu_sh4_init
#define cpu_exec cpu_sh4_exec
#define cpu_gen_code cpu_sh4_gen_code
#define cpu_signal_handler cpu_sh4_signal_handler
#define cpu_list sh4_cpu_list

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env)
{
    return (env->sr & SR_MD) == 0 ? 1 : 0;
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
    if (newsp)
        env->gregs[15] = newsp;
    env->gregs[0] = 0;
}
#endif

#include "cpu-all.h"
#include "exec-all.h"

/* Memory access type */
enum {
    /* Privilege */
    ACCESS_PRIV = 0x01,
    /* Direction */
    ACCESS_WRITE = 0x02,
    /* Type of instruction */
    ACCESS_CODE = 0x10,
    ACCESS_INT = 0x20
};

/* MMU control register */
#define MMUCR    0x1F000010
#define MMUCR_AT (1<<0)
#define MMUCR_SV (1<<8)
#define MMUCR_URC_BITS (6)
#define MMUCR_URC_OFFSET (10)
#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
static inline int cpu_mmucr_urc (uint32_t mmucr)
{
    return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
}

/* PTEH : Page Translation Entry High register */
#define PTEH_ASID_BITS (8)
#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
#define PTEH_VPN_BITS (22)
#define PTEH_VPN_OFFSET (10)
#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
static inline int cpu_pteh_vpn (uint32_t pteh)
{
    return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
}

/* PTEL : Page Translation Entry Low register */
#define PTEL_V        (1 << 8)
#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
#define PTEL_C        (1 << 3)
#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
#define PTEL_D        (1 << 2)
#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
#define PTEL_SH       (1 << 1)
#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
#define PTEL_WT       (1 << 0)
#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)

#define PTEL_SZ_HIGH_OFFSET  (7)
#define PTEL_SZ_HIGH  (1 << PTEL_SZ_HIGH_OFFSET)
#define PTEL_SZ_LOW_OFFSET   (4)
#define PTEL_SZ_LOW   (1 << PTEL_SZ_LOW_OFFSET)
static inline int cpu_ptel_sz (uint32_t ptel)
{
    int sz;
    sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
    sz <<= 1;
    sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
    return sz;
}

#define PTEL_PPN_BITS (19)
#define PTEL_PPN_OFFSET (10)
#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
static inline int cpu_ptel_ppn (uint32_t ptel)
{
    return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
}

#define PTEL_PR_BITS   (2)
#define PTEL_PR_OFFSET (5)
#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
static inline int cpu_ptel_pr (uint32_t ptel)
{
    return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
}

/* PTEA : Page Translation Entry Assistance register */
#define PTEA_SA_BITS (3)
#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
#define PTEA_TC        (1 << 3)
#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)

static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
    env->flags = tb->flags;
}

static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
                    | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME))   /* Bits  0- 3 */
            | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */
            | (env->sr & (SR_MD | SR_RB))                      /* Bits 29-30 */
            | (env->sr & SR_FD);                               /* Bit 15 */
}

#endif				/* _CPU_SH4_H */
Commit	Line	Data
fdf9b3e8 FB	1	/*
fdf9b3e8 FB	2	* SH4 emulation
5fafdf24	3	*
fdf9b3e8 FB	4	* Copyright (c) 2005 Samuel Tardieu
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef _CPU_SH4_H
	21	#define _CPU_SH4_H
	22
	23	#include "config.h"
	24
	25	#define TARGET_LONG_BITS 32
	26	#define TARGET_HAS_ICE 1
	27
9042c0e2 TS	28	#define ELF_MACHINE EM_SH
9042c0e2 TS	29
0fd3ca30 AJ	30	/* CPU Subtypes */
	31	#define SH_CPU_SH7750 (1 << 0)
	32	#define SH_CPU_SH7750S (1 << 1)
	33	#define SH_CPU_SH7750R (1 << 2)
	34	#define SH_CPU_SH7751 (1 << 3)
	35	#define SH_CPU_SH7751R (1 << 4)
	36	#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 \| SH_CPU_SH7750S \| SH_CPU_SH7750R)
	37	#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 \| SH_CPU_SH7751R)
	38
fdf9b3e8 FB	39	#include "cpu-defs.h"
fdf9b3e8 FB	40
eda9b09b FB	41	#include "softfloat.h"
eda9b09b FB	42
fdf9b3e8 FB	43	#define TARGET_PAGE_BITS 12 /* 4k XXXXX */
	44
	45	#define SR_MD (1 << 30)
	46	#define SR_RB (1 << 29)
	47	#define SR_BL (1 << 28)
	48	#define SR_FD (1 << 15)
	49	#define SR_M (1 << 9)
	50	#define SR_Q (1 << 8)
	51	#define SR_S (1 << 1)
	52	#define SR_T (1 << 0)
	53
	54	#define FPSCR_FR (1 << 21)
	55	#define FPSCR_SZ (1 << 20)
	56	#define FPSCR_PR (1 << 19)
	57	#define FPSCR_DN (1 << 18)
823029f9	58	#define DELAY_SLOT (1 << 0)
fdf9b3e8	59	#define DELAY_SLOT_CONDITIONAL (1 << 1)
823029f9 TS	60	#define DELAY_SLOT_TRUE (1 << 2)
	61	#define DELAY_SLOT_CLEARME (1 << 3)
	62	/* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
	63	* after the delay slot should be taken or not. It is calculated from SR_T.
	64	*
	65	* It is unclear if it is permitted to modify the SR_T flag in a delay slot.
	66	* The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
	67	*/
fdf9b3e8 FB	68
	69	/* XXXXX The structure could be made more compact */
	70	typedef struct tlb_t {
	71	uint8_t asid; /* address space identifier */
	72	uint32_t vpn; /* virtual page number */
	73	uint8_t v; /* validity */
	74	uint32_t ppn; /* physical page number */
	75	uint8_t sz; /* page size */
	76	uint32_t size; /* cached page size in bytes */
	77	uint8_t sh; /* share status */
	78	uint8_t c; /* cacheability */
	79	uint8_t pr; /* protection key */
	80	uint8_t d; /* dirty */
	81	uint8_t wt; /* write through */
	82	uint8_t sa; /* space attribute (PCMCIA) */
	83	uint8_t tc; /* timing control */
	84	} tlb_t;
	85
	86	#define UTLB_SIZE 64
	87	#define ITLB_SIZE 4
	88
6ebbf390 JM	89	#define NB_MMU_MODES 2
6ebbf390 JM	90
fdf9b3e8	91	typedef struct CPUSH4State {
0fd3ca30 AJ	92	int id; /* CPU model */
0fd3ca30 AJ	93
fdf9b3e8 FB	94	uint32_t flags; /* general execution flags */
fdf9b3e8 FB	95	uint32_t gregs[24]; /* general registers */
e04ea3dc	96	float32 fregs[32]; /* floating point registers */
fdf9b3e8 FB	97	uint32_t sr; /* status register */
	98	uint32_t ssr; /* saved status register */
	99	uint32_t spc; /* saved program counter */
	100	uint32_t gbr; /* global base register */
	101	uint32_t vbr; /* vector base register */
	102	uint32_t sgr; /* saved global register 15 */
	103	uint32_t dbr; /* debug base register */
	104	uint32_t pc; /* program counter */
	105	uint32_t delayed_pc; /* target of delayed jump */
	106	uint32_t mach; /* multiply and accumulate high */
	107	uint32_t macl; /* multiply and accumulate low */
	108	uint32_t pr; /* procedure register */
	109	uint32_t fpscr; /* floating point status/control register */
	110	uint32_t fpul; /* floating point communication register */
	111
17b086f7	112	/* float point status register */
ea6cf6be	113	float_status fp_status;
eda9b09b	114
fdf9b3e8 FB	115	/* Those belong to the specific unit (SH7750) but are handled here */
	116	uint32_t mmucr; /* MMU control register */
	117	uint32_t pteh; /* page table entry high register */
	118	uint32_t ptel; /* page table entry low register */
	119	uint32_t ptea; /* page table entry assistance register */
	120	uint32_t ttb; /* tranlation table base register */
	121	uint32_t tea; /* TLB exception address register */
	122	uint32_t tra; /* TRAPA exception register */
	123	uint32_t expevt; /* exception event register */
	124	uint32_t intevt; /* interrupt event register */
	125
0fd3ca30 AJ	126	uint32_t pvr; /* Processor Version Register */
	127	uint32_t prr; /* Processor Revision Register */
	128	uint32_t cvr; /* Cache Version Register */
	129
fdf9b3e8 FB	130	CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
fdf9b3e8 FB	131	tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
e96e2044	132	void *intc_handle;
833ed386	133	int intr_at_halt; /* SR_BL ignored during sleep */
fdf9b3e8 FB	134	} CPUSH4State;
fdf9b3e8 FB	135
aaed909a	136	CPUSH4State cpu_sh4_init(const char cpu_model);
fdf9b3e8	137	int cpu_sh4_exec(CPUSH4State * s);
5fafdf24	138	int cpu_sh4_signal_handler(int host_signum, void *pinfo,
5a7b542b	139	void *puc);
42083220 AJ	140	int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
	141	int mmu_idx, int is_softmmu);
	142	void do_interrupt(CPUSH4State * env);
	143
0fd3ca30	144	void sh4_cpu_list(FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...));
29e179bc AJ	145	void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
29e179bc AJ	146	uint32_t mem_value);
fdf9b3e8	147
0b6d3ae0 AJ	148	static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
	149	{
	150	env->gbr = newtls;
	151	}
	152
fdf9b3e8 FB	153	#include "softfloat.h"
fdf9b3e8 FB	154
9467d44c TS	155	#define CPUState CPUSH4State
	156	#define cpu_init cpu_sh4_init
	157	#define cpu_exec cpu_sh4_exec
	158	#define cpu_gen_code cpu_sh4_gen_code
	159	#define cpu_signal_handler cpu_sh4_signal_handler
0fd3ca30	160	#define cpu_list sh4_cpu_list
9467d44c	161
6ebbf390 JM	162	/* MMU modes definitions */
	163	#define MMU_MODE0_SUFFIX _kernel
	164	#define MMU_MODE1_SUFFIX _user
	165	#define MMU_USER_IDX 1
	166	static inline int cpu_mmu_index (CPUState *env)
	167	{
	168	return (env->sr & SR_MD) == 0 ? 1 : 0;
	169	}
	170
6e68e076 PB	171	#if defined(CONFIG_USER_ONLY)
	172	static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
	173	{
f8ed7070	174	if (newsp)
6e68e076 PB	175	env->gregs[15] = newsp;
	176	env->gregs[0] = 0;
	177	}
	178	#endif
	179
fdf9b3e8	180	#include "cpu-all.h"
622ed360	181	#include "exec-all.h"
fdf9b3e8 FB	182
	183	/* Memory access type */
	184	enum {
	185	/* Privilege */
	186	ACCESS_PRIV = 0x01,
	187	/* Direction */
	188	ACCESS_WRITE = 0x02,
	189	/* Type of instruction */
	190	ACCESS_CODE = 0x10,
	191	ACCESS_INT = 0x20
	192	};
	193
	194	/* MMU control register */
	195	#define MMUCR 0x1F000010
	196	#define MMUCR_AT (1<<0)
	197	#define MMUCR_SV (1<<8)
ea2b542a AJ	198	#define MMUCR_URC_BITS (6)
	199	#define MMUCR_URC_OFFSET (10)
	200	#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
	201	#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
	202	static inline int cpu_mmucr_urc (uint32_t mmucr)
	203	{
	204	return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
	205	}
	206
	207	/* PTEH : Page Translation Entry High register */
	208	#define PTEH_ASID_BITS (8)
	209	#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
	210	#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
	211	#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
	212	#define PTEH_VPN_BITS (22)
	213	#define PTEH_VPN_OFFSET (10)
	214	#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
	215	#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
	216	static inline int cpu_pteh_vpn (uint32_t pteh)
	217	{
	218	return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
	219	}
	220
	221	/* PTEL : Page Translation Entry Low register */
	222	#define PTEL_V (1 << 8)
	223	#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
	224	#define PTEL_C (1 << 3)
	225	#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
	226	#define PTEL_D (1 << 2)
	227	#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
	228	#define PTEL_SH (1 << 1)
	229	#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
	230	#define PTEL_WT (1 << 0)
	231	#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
	232
	233	#define PTEL_SZ_HIGH_OFFSET (7)
	234	#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
	235	#define PTEL_SZ_LOW_OFFSET (4)
	236	#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
	237	static inline int cpu_ptel_sz (uint32_t ptel)
	238	{
	239	int sz;
	240	sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
	241	sz <<= 1;
	242	sz \|= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
	243	return sz;
	244	}
	245
	246	#define PTEL_PPN_BITS (19)
	247	#define PTEL_PPN_OFFSET (10)
	248	#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
	249	#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
	250	static inline int cpu_ptel_ppn (uint32_t ptel)
	251	{
	252	return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
	253	}
	254
	255	#define PTEL_PR_BITS (2)
	256	#define PTEL_PR_OFFSET (5)
	257	#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
	258	#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
	259	static inline int cpu_ptel_pr (uint32_t ptel)
	260	{
	261	return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
262	}
263
264	/* PTEA : Page Translation Entry Assistance register */
265	#define PTEA_SA_BITS (3)
266	#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
267	#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
268	#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
269	#define PTEA_TC (1 << 3)
270	#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
fdf9b3e8	271
622ed360 AL	272	static inline void cpu_pc_from_tb(CPUState env, TranslationBlock tb)
	273	{
	274	env->pc = tb->pc;
	275	env->flags = tb->flags;
	276	}
	277
6b917547 AL	278	static inline void cpu_get_tb_cpu_state(CPUState env, target_ulong pc,
	279	target_ulong cs_base, int flags)
	280	{
	281	*pc = env->pc;
	282	*cs_base = 0;
	283	*flags = (env->flags & (DELAY_SLOT \| DELAY_SLOT_CONDITIONAL
	284	\| DELAY_SLOT_TRUE \| DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
	285	\| (env->fpscr & (FPSCR_FR \| FPSCR_SZ \| FPSCR_PR)) /* Bits 19-21 */
d8299bcc AJ	286	\| (env->sr & (SR_MD \| SR_RB)) /* Bits 29-30 */
d8299bcc AJ	287	\| (env->sr & SR_FD); /* Bit 15 */
6b917547 AL	288	}
6b917547 AL	289
fdf9b3e8	290	#endif /* _CPU_SH4_H */