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fdf9b3e8 FB |
1 | /* |
2 | * SH4 emulation | |
5fafdf24 | 3 | * |
fdf9b3e8 FB |
4 | * Copyright (c) 2005 Samuel Tardieu |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <stdarg.h> | |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <signal.h> | |
26 | #include <assert.h> | |
27 | ||
28 | #include "cpu.h" | |
29 | #include "exec-all.h" | |
e96e2044 | 30 | #include "hw/sh_intc.h" |
fdf9b3e8 | 31 | |
355fb23d PB |
32 | #if defined(CONFIG_USER_ONLY) |
33 | ||
34 | void do_interrupt (CPUState *env) | |
35 | { | |
36 | env->exception_index = -1; | |
37 | } | |
38 | ||
39 | int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, | |
6ebbf390 | 40 | int mmu_idx, int is_softmmu) |
355fb23d PB |
41 | { |
42 | env->tea = address; | |
c3b5bc8a | 43 | env->exception_index = 0; |
355fb23d PB |
44 | switch (rw) { |
45 | case 0: | |
c3b5bc8a | 46 | env->tea = address; |
355fb23d PB |
47 | env->exception_index = 0x0a0; |
48 | break; | |
49 | case 1: | |
c3b5bc8a | 50 | env->tea = address; |
355fb23d PB |
51 | env->exception_index = 0x0c0; |
52 | break; | |
355fb23d PB |
53 | } |
54 | return 1; | |
55 | } | |
56 | ||
9b3c35e0 | 57 | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
355fb23d PB |
58 | { |
59 | return addr; | |
60 | } | |
61 | ||
62 | #else /* !CONFIG_USER_ONLY */ | |
63 | ||
fdf9b3e8 FB |
64 | #define MMU_OK 0 |
65 | #define MMU_ITLB_MISS (-1) | |
66 | #define MMU_ITLB_MULTIPLE (-2) | |
67 | #define MMU_ITLB_VIOLATION (-3) | |
68 | #define MMU_DTLB_MISS_READ (-4) | |
69 | #define MMU_DTLB_MISS_WRITE (-5) | |
70 | #define MMU_DTLB_INITIAL_WRITE (-6) | |
71 | #define MMU_DTLB_VIOLATION_READ (-7) | |
72 | #define MMU_DTLB_VIOLATION_WRITE (-8) | |
73 | #define MMU_DTLB_MULTIPLE (-9) | |
74 | #define MMU_DTLB_MISS (-10) | |
75 | ||
76 | void do_interrupt(CPUState * env) | |
77 | { | |
e96e2044 TS |
78 | int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD; |
79 | int do_exp, irq_vector = env->exception_index; | |
80 | ||
81 | /* prioritize exceptions over interrupts */ | |
82 | ||
83 | do_exp = env->exception_index != -1; | |
84 | do_irq = do_irq && (env->exception_index == -1); | |
85 | ||
86 | if (env->sr & SR_BL) { | |
87 | if (do_exp && env->exception_index != 0x1e0) { | |
88 | env->exception_index = 0x000; /* masked exception -> reset */ | |
89 | } | |
90 | if (do_irq) { | |
91 | return; /* masked */ | |
92 | } | |
93 | } | |
94 | ||
95 | if (do_irq) { | |
96 | irq_vector = sh_intc_get_pending_vector(env->intc_handle, | |
97 | (env->sr >> 4) & 0xf); | |
98 | if (irq_vector == -1) { | |
99 | return; /* masked */ | |
100 | } | |
101 | } | |
102 | ||
fdf9b3e8 FB |
103 | if (loglevel & CPU_LOG_INT) { |
104 | const char *expname; | |
105 | switch (env->exception_index) { | |
106 | case 0x0e0: | |
107 | expname = "addr_error"; | |
108 | break; | |
109 | case 0x040: | |
110 | expname = "tlb_miss"; | |
111 | break; | |
112 | case 0x0a0: | |
113 | expname = "tlb_violation"; | |
114 | break; | |
115 | case 0x180: | |
116 | expname = "illegal_instruction"; | |
117 | break; | |
118 | case 0x1a0: | |
119 | expname = "slot_illegal_instruction"; | |
120 | break; | |
121 | case 0x800: | |
122 | expname = "fpu_disable"; | |
123 | break; | |
124 | case 0x820: | |
125 | expname = "slot_fpu"; | |
126 | break; | |
127 | case 0x100: | |
128 | expname = "data_write"; | |
129 | break; | |
130 | case 0x060: | |
131 | expname = "dtlb_miss_write"; | |
132 | break; | |
133 | case 0x0c0: | |
134 | expname = "dtlb_violation_write"; | |
135 | break; | |
136 | case 0x120: | |
137 | expname = "fpu_exception"; | |
138 | break; | |
139 | case 0x080: | |
140 | expname = "initial_page_write"; | |
141 | break; | |
142 | case 0x160: | |
143 | expname = "trapa"; | |
144 | break; | |
145 | default: | |
e96e2044 TS |
146 | expname = do_irq ? "interrupt" : "???"; |
147 | break; | |
fdf9b3e8 FB |
148 | } |
149 | fprintf(logfile, "exception 0x%03x [%s] raised\n", | |
e96e2044 | 150 | irq_vector, expname); |
fdf9b3e8 FB |
151 | cpu_dump_state(env, logfile, fprintf, 0); |
152 | } | |
153 | ||
154 | env->ssr = env->sr; | |
e96e2044 | 155 | env->spc = env->pc; |
fdf9b3e8 FB |
156 | env->sgr = env->gregs[15]; |
157 | env->sr |= SR_BL | SR_MD | SR_RB; | |
158 | ||
e96e2044 TS |
159 | if (do_exp) { |
160 | env->expevt = env->exception_index; | |
161 | switch (env->exception_index) { | |
162 | case 0x000: | |
163 | case 0x020: | |
164 | case 0x140: | |
165 | env->sr &= ~SR_FD; | |
166 | env->sr |= 0xf << 4; /* IMASK */ | |
167 | env->pc = 0xa0000000; | |
168 | break; | |
169 | case 0x040: | |
170 | case 0x060: | |
171 | env->pc = env->vbr + 0x400; | |
172 | break; | |
173 | case 0x160: | |
174 | env->spc += 2; /* special case for TRAPA */ | |
175 | /* fall through */ | |
176 | default: | |
177 | env->pc = env->vbr + 0x100; | |
178 | break; | |
179 | } | |
180 | return; | |
181 | } | |
182 | ||
183 | if (do_irq) { | |
184 | env->intevt = irq_vector; | |
185 | env->pc = env->vbr + 0x600; | |
186 | return; | |
fdf9b3e8 FB |
187 | } |
188 | } | |
189 | ||
190 | static void update_itlb_use(CPUState * env, int itlbnb) | |
191 | { | |
192 | uint8_t or_mask = 0, and_mask = (uint8_t) - 1; | |
193 | ||
194 | switch (itlbnb) { | |
195 | case 0: | |
ea2b542a | 196 | and_mask = 0x1f; |
fdf9b3e8 FB |
197 | break; |
198 | case 1: | |
199 | and_mask = 0xe7; | |
200 | or_mask = 0x80; | |
201 | break; | |
202 | case 2: | |
203 | and_mask = 0xfb; | |
204 | or_mask = 0x50; | |
205 | break; | |
206 | case 3: | |
207 | or_mask = 0x2c; | |
208 | break; | |
209 | } | |
210 | ||
ea2b542a | 211 | env->mmucr &= (and_mask << 24) | 0x00ffffff; |
fdf9b3e8 FB |
212 | env->mmucr |= (or_mask << 24); |
213 | } | |
214 | ||
215 | static int itlb_replacement(CPUState * env) | |
216 | { | |
217 | if ((env->mmucr & 0xe0000000) == 0xe0000000) | |
218 | return 0; | |
ea2b542a | 219 | if ((env->mmucr & 0x98000000) == 0x18000000) |
fdf9b3e8 FB |
220 | return 1; |
221 | if ((env->mmucr & 0x54000000) == 0x04000000) | |
222 | return 2; | |
223 | if ((env->mmucr & 0x2c000000) == 0x00000000) | |
224 | return 3; | |
225 | assert(0); | |
226 | } | |
227 | ||
228 | /* Find the corresponding entry in the right TLB | |
229 | Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE | |
230 | */ | |
231 | static int find_tlb_entry(CPUState * env, target_ulong address, | |
232 | tlb_t * entries, uint8_t nbtlb, int use_asid) | |
233 | { | |
234 | int match = MMU_DTLB_MISS; | |
235 | uint32_t start, end; | |
236 | uint8_t asid; | |
237 | int i; | |
238 | ||
239 | asid = env->pteh & 0xff; | |
240 | ||
241 | for (i = 0; i < nbtlb; i++) { | |
242 | if (!entries[i].v) | |
243 | continue; /* Invalid entry */ | |
244 | if (use_asid && entries[i].asid != asid && !entries[i].sh) | |
245 | continue; /* Bad ASID */ | |
246 | #if 0 | |
247 | switch (entries[i].sz) { | |
248 | case 0: | |
249 | size = 1024; /* 1kB */ | |
250 | break; | |
251 | case 1: | |
252 | size = 4 * 1024; /* 4kB */ | |
253 | break; | |
254 | case 2: | |
255 | size = 64 * 1024; /* 64kB */ | |
256 | break; | |
257 | case 3: | |
258 | size = 1024 * 1024; /* 1MB */ | |
259 | break; | |
260 | default: | |
261 | assert(0); | |
262 | } | |
263 | #endif | |
264 | start = (entries[i].vpn << 10) & ~(entries[i].size - 1); | |
265 | end = start + entries[i].size - 1; | |
266 | if (address >= start && address <= end) { /* Match */ | |
ea2b542a | 267 | if (match != MMU_DTLB_MISS) |
fdf9b3e8 FB |
268 | return MMU_DTLB_MULTIPLE; /* Multiple match */ |
269 | match = i; | |
270 | } | |
271 | } | |
272 | return match; | |
273 | } | |
274 | ||
275 | /* Find itlb entry - update itlb from utlb if necessary and asked for | |
276 | Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE | |
277 | Update the itlb from utlb if update is not 0 | |
278 | */ | |
279 | int find_itlb_entry(CPUState * env, target_ulong address, | |
280 | int use_asid, int update) | |
281 | { | |
282 | int e, n; | |
283 | ||
284 | e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); | |
285 | if (e == MMU_DTLB_MULTIPLE) | |
286 | e = MMU_ITLB_MULTIPLE; | |
287 | else if (e == MMU_DTLB_MISS && update) { | |
288 | e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); | |
289 | if (e >= 0) { | |
290 | n = itlb_replacement(env); | |
291 | env->itlb[n] = env->utlb[e]; | |
292 | e = n; | |
ea2b542a AJ |
293 | } else if (e == MMU_DTLB_MISS) |
294 | e = MMU_ITLB_MISS; | |
295 | } else if (e == MMU_DTLB_MISS) | |
296 | e = MMU_ITLB_MISS; | |
fdf9b3e8 FB |
297 | if (e >= 0) |
298 | update_itlb_use(env, e); | |
299 | return e; | |
300 | } | |
301 | ||
302 | /* Find utlb entry | |
303 | Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ | |
304 | int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) | |
305 | { | |
306 | uint8_t urb, urc; | |
307 | ||
308 | /* Increment URC */ | |
309 | urb = ((env->mmucr) >> 18) & 0x3f; | |
310 | urc = ((env->mmucr) >> 10) & 0x3f; | |
311 | urc++; | |
312 | if (urc == urb || urc == UTLB_SIZE - 1) | |
313 | urc = 0; | |
314 | env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); | |
315 | ||
316 | /* Return entry */ | |
317 | return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); | |
318 | } | |
319 | ||
320 | /* Match address against MMU | |
321 | Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE, | |
322 | MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ, | |
323 | MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS, | |
324 | MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION | |
325 | */ | |
326 | static int get_mmu_address(CPUState * env, target_ulong * physical, | |
327 | int *prot, target_ulong address, | |
328 | int rw, int access_type) | |
329 | { | |
330 | int use_asid, is_code, n; | |
331 | tlb_t *matching = NULL; | |
332 | ||
333 | use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0; | |
334 | is_code = env->pc == address; /* Hack */ | |
335 | ||
336 | /* Use a hack to find if this is an instruction or data access */ | |
337 | if (env->pc == address && !(rw & PAGE_WRITE)) { | |
338 | n = find_itlb_entry(env, address, use_asid, 1); | |
339 | if (n >= 0) { | |
340 | matching = &env->itlb[n]; | |
341 | if ((env->sr & SR_MD) & !(matching->pr & 2)) | |
342 | n = MMU_ITLB_VIOLATION; | |
343 | else | |
344 | *prot = PAGE_READ; | |
345 | } | |
346 | } else { | |
347 | n = find_utlb_entry(env, address, use_asid); | |
348 | if (n >= 0) { | |
349 | matching = &env->utlb[n]; | |
350 | switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) { | |
351 | case 0: /* 000 */ | |
352 | case 2: /* 010 */ | |
353 | n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE : | |
354 | MMU_DTLB_VIOLATION_READ; | |
355 | break; | |
356 | case 1: /* 001 */ | |
357 | case 4: /* 100 */ | |
358 | case 5: /* 101 */ | |
359 | if (rw & PAGE_WRITE) | |
360 | n = MMU_DTLB_VIOLATION_WRITE; | |
361 | else | |
362 | *prot = PAGE_READ; | |
363 | break; | |
364 | case 3: /* 011 */ | |
365 | case 6: /* 110 */ | |
366 | case 7: /* 111 */ | |
367 | *prot = rw & (PAGE_READ | PAGE_WRITE); | |
368 | break; | |
369 | } | |
370 | } else if (n == MMU_DTLB_MISS) { | |
371 | n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE : | |
372 | MMU_DTLB_MISS_READ; | |
373 | } | |
374 | } | |
375 | if (n >= 0) { | |
376 | *physical = ((matching->ppn << 10) & ~(matching->size - 1)) | | |
377 | (address & (matching->size - 1)); | |
378 | if ((rw & PAGE_WRITE) & !matching->d) | |
379 | n = MMU_DTLB_INITIAL_WRITE; | |
380 | else | |
381 | n = MMU_OK; | |
382 | } | |
383 | return n; | |
384 | } | |
385 | ||
386 | int get_physical_address(CPUState * env, target_ulong * physical, | |
387 | int *prot, target_ulong address, | |
388 | int rw, int access_type) | |
389 | { | |
390 | /* P1, P2 and P4 areas do not use translation */ | |
391 | if ((address >= 0x80000000 && address < 0xc0000000) || | |
392 | address >= 0xe0000000) { | |
393 | if (!(env->sr & SR_MD) | |
394 | && (address < 0xe0000000 || address > 0xe4000000)) { | |
395 | /* Unauthorized access in user mode (only store queues are available) */ | |
396 | fprintf(stderr, "Unauthorized access\n"); | |
397 | return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE : | |
398 | MMU_DTLB_MISS_READ; | |
399 | } | |
400 | /* Mask upper 3 bits */ | |
401 | *physical = address & 0x1FFFFFFF; | |
402 | *prot = PAGE_READ | PAGE_WRITE; | |
403 | return MMU_OK; | |
404 | } | |
405 | ||
406 | /* If MMU is disabled, return the corresponding physical page */ | |
407 | if (!env->mmucr & MMUCR_AT) { | |
408 | *physical = address & 0x1FFFFFFF; | |
409 | *prot = PAGE_READ | PAGE_WRITE; | |
410 | return MMU_OK; | |
411 | } | |
412 | ||
413 | /* We need to resort to the MMU */ | |
414 | return get_mmu_address(env, physical, prot, address, rw, access_type); | |
415 | } | |
416 | ||
417 | int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, | |
6ebbf390 | 418 | int mmu_idx, int is_softmmu) |
fdf9b3e8 FB |
419 | { |
420 | target_ulong physical, page_offset, page_size; | |
421 | int prot, ret, access_type; | |
422 | ||
ea2b542a AJ |
423 | switch (rw) { |
424 | case 0: | |
425 | rw = PAGE_READ; | |
426 | break; | |
427 | case 1: | |
428 | rw = PAGE_WRITE; | |
429 | break; | |
430 | case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */ | |
431 | rw = PAGE_READ; | |
432 | break; | |
433 | default: | |
434 | /* fatal error */ | |
435 | assert(0); | |
436 | } | |
437 | ||
fdf9b3e8 FB |
438 | /* XXXXX */ |
439 | #if 0 | |
6ebbf390 JM |
440 | fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n", |
441 | __func__, env->pc, address, rw, mmu_idx, is_softmmu); | |
fdf9b3e8 FB |
442 | #endif |
443 | ||
444 | access_type = ACCESS_INT; | |
445 | ret = | |
446 | get_physical_address(env, &physical, &prot, address, rw, | |
447 | access_type); | |
448 | ||
449 | if (ret != MMU_OK) { | |
450 | env->tea = address; | |
451 | switch (ret) { | |
452 | case MMU_ITLB_MISS: | |
453 | case MMU_DTLB_MISS_READ: | |
454 | env->exception_index = 0x040; | |
455 | break; | |
456 | case MMU_DTLB_MULTIPLE: | |
457 | case MMU_ITLB_MULTIPLE: | |
458 | env->exception_index = 0x140; | |
459 | break; | |
460 | case MMU_ITLB_VIOLATION: | |
461 | env->exception_index = 0x0a0; | |
462 | break; | |
463 | case MMU_DTLB_MISS_WRITE: | |
464 | env->exception_index = 0x060; | |
465 | break; | |
466 | case MMU_DTLB_INITIAL_WRITE: | |
467 | env->exception_index = 0x080; | |
468 | break; | |
469 | case MMU_DTLB_VIOLATION_READ: | |
470 | env->exception_index = 0x0a0; | |
471 | break; | |
472 | case MMU_DTLB_VIOLATION_WRITE: | |
473 | env->exception_index = 0x0c0; | |
474 | break; | |
475 | default: | |
476 | assert(0); | |
477 | } | |
478 | return 1; | |
479 | } | |
480 | ||
481 | page_size = TARGET_PAGE_SIZE; | |
482 | page_offset = | |
483 | (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1); | |
484 | address = (address & TARGET_PAGE_MASK) + page_offset; | |
485 | physical = (physical & TARGET_PAGE_MASK) + page_offset; | |
486 | ||
6ebbf390 | 487 | return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu); |
fdf9b3e8 | 488 | } |
355fb23d | 489 | |
9b3c35e0 | 490 | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
355fb23d PB |
491 | { |
492 | target_ulong physical; | |
493 | int prot; | |
494 | ||
495 | get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0); | |
496 | return physical; | |
497 | } | |
498 | ||
ea2b542a AJ |
499 | void cpu_load_tlb(CPUState * env) |
500 | { | |
501 | int n = cpu_mmucr_urc(env->mmucr); | |
502 | tlb_t * entry = &env->utlb[n]; | |
503 | ||
504 | /* Take values into cpu status from registers. */ | |
505 | entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); | |
506 | entry->vpn = cpu_pteh_vpn(env->pteh); | |
507 | entry->v = (uint8_t)cpu_ptel_v(env->ptel); | |
508 | entry->ppn = cpu_ptel_ppn(env->ptel); | |
509 | entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); | |
510 | switch (entry->sz) { | |
511 | case 0: /* 00 */ | |
512 | entry->size = 1024; /* 1K */ | |
513 | break; | |
514 | case 1: /* 01 */ | |
515 | entry->size = 1024 * 4; /* 4K */ | |
516 | break; | |
517 | case 2: /* 10 */ | |
518 | entry->size = 1024 * 64; /* 64K */ | |
519 | break; | |
520 | case 3: /* 11 */ | |
521 | entry->size = 1024 * 1024; /* 1M */ | |
522 | break; | |
523 | default: | |
524 | assert(0); | |
525 | break; | |
526 | } | |
527 | entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); | |
528 | entry->c = (uint8_t)cpu_ptel_c(env->ptel); | |
529 | entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); | |
530 | entry->d = (uint8_t)cpu_ptel_d(env->ptel); | |
531 | entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); | |
532 | entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); | |
533 | entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); | |
534 | } | |
535 | ||
355fb23d | 536 | #endif |