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Commit | Line | Data |
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fdf9b3e8 FB |
1 | /* |
2 | * SH4 translation | |
5fafdf24 | 3 | * |
fdf9b3e8 FB |
4 | * Copyright (c) 2005 Samuel Tardieu |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <stdarg.h> | |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <assert.h> | |
26 | ||
27 | #define DEBUG_DISAS | |
28 | #define SH4_DEBUG_DISAS | |
29 | //#define SH4_SINGLE_STEP | |
30 | ||
31 | #include "cpu.h" | |
32 | #include "exec-all.h" | |
33 | #include "disas.h" | |
57fec1fe | 34 | #include "tcg-op.h" |
ca10f867 | 35 | #include "qemu-common.h" |
fdf9b3e8 | 36 | |
a7812ae4 PB |
37 | #include "helper.h" |
38 | #define GEN_HELPER 1 | |
39 | #include "helper.h" | |
40 | ||
fdf9b3e8 FB |
41 | typedef struct DisasContext { |
42 | struct TranslationBlock *tb; | |
43 | target_ulong pc; | |
44 | uint32_t sr; | |
eda9b09b | 45 | uint32_t fpscr; |
fdf9b3e8 FB |
46 | uint16_t opcode; |
47 | uint32_t flags; | |
823029f9 | 48 | int bstate; |
fdf9b3e8 FB |
49 | int memidx; |
50 | uint32_t delayed_pc; | |
51 | int singlestep_enabled; | |
52 | } DisasContext; | |
53 | ||
fe25591e AJ |
54 | #if defined(CONFIG_USER_ONLY) |
55 | #define IS_USER(ctx) 1 | |
56 | #else | |
57 | #define IS_USER(ctx) (!(ctx->sr & SR_MD)) | |
58 | #endif | |
59 | ||
823029f9 TS |
60 | enum { |
61 | BS_NONE = 0, /* We go out of the TB without reaching a branch or an | |
62 | * exception condition | |
63 | */ | |
64 | BS_STOP = 1, /* We want to stop translation for any reason */ | |
65 | BS_BRANCH = 2, /* We reached a branch condition */ | |
66 | BS_EXCP = 3, /* We reached an exception condition */ | |
67 | }; | |
68 | ||
1e8864f7 | 69 | /* global register indexes */ |
a7812ae4 | 70 | static TCGv_ptr cpu_env; |
1e8864f7 | 71 | static TCGv cpu_gregs[24]; |
3a8a44c4 AJ |
72 | static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; |
73 | static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; | |
1000822b AJ |
74 | static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags; |
75 | ||
76 | /* internal register indexes */ | |
77 | static TCGv cpu_flags, cpu_delayed_pc; | |
1e8864f7 | 78 | |
2e70f6ef PB |
79 | #include "gen-icount.h" |
80 | ||
a5f1b965 | 81 | static void sh4_translate_init(void) |
2e70f6ef | 82 | { |
1e8864f7 | 83 | int i; |
2e70f6ef | 84 | static int done_init = 0; |
559dd74d | 85 | static const char * const gregnames[24] = { |
1e8864f7 AJ |
86 | "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", |
87 | "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", | |
88 | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", | |
89 | "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1", | |
90 | "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1" | |
91 | }; | |
92 | ||
2e70f6ef PB |
93 | if (done_init) |
94 | return; | |
1e8864f7 | 95 | |
a7812ae4 | 96 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
1e8864f7 AJ |
97 | |
98 | for (i = 0; i < 24; i++) | |
a7812ae4 | 99 | cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1e8864f7 AJ |
100 | offsetof(CPUState, gregs[i]), |
101 | gregnames[i]); | |
988d7eaa | 102 | |
a7812ae4 PB |
103 | cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, |
104 | offsetof(CPUState, pc), "PC"); | |
105 | cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, | |
106 | offsetof(CPUState, sr), "SR"); | |
107 | cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, | |
108 | offsetof(CPUState, ssr), "SSR"); | |
109 | cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, | |
110 | offsetof(CPUState, spc), "SPC"); | |
111 | cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0, | |
112 | offsetof(CPUState, gbr), "GBR"); | |
113 | cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0, | |
114 | offsetof(CPUState, vbr), "VBR"); | |
115 | cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0, | |
116 | offsetof(CPUState, sgr), "SGR"); | |
117 | cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0, | |
118 | offsetof(CPUState, dbr), "DBR"); | |
119 | cpu_mach = tcg_global_mem_new_i32(TCG_AREG0, | |
120 | offsetof(CPUState, mach), "MACH"); | |
121 | cpu_macl = tcg_global_mem_new_i32(TCG_AREG0, | |
122 | offsetof(CPUState, macl), "MACL"); | |
123 | cpu_pr = tcg_global_mem_new_i32(TCG_AREG0, | |
124 | offsetof(CPUState, pr), "PR"); | |
125 | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, | |
126 | offsetof(CPUState, fpscr), "FPSCR"); | |
127 | cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0, | |
128 | offsetof(CPUState, fpul), "FPUL"); | |
129 | ||
130 | cpu_flags = tcg_global_mem_new_i32(TCG_AREG0, | |
131 | offsetof(CPUState, flags), "_flags_"); | |
132 | cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, | |
133 | offsetof(CPUState, delayed_pc), | |
134 | "_delayed_pc_"); | |
1000822b | 135 | |
988d7eaa | 136 | /* register helpers */ |
a7812ae4 | 137 | #define GEN_HELPER 2 |
988d7eaa AJ |
138 | #include "helper.h" |
139 | ||
2e70f6ef PB |
140 | done_init = 1; |
141 | } | |
142 | ||
fdf9b3e8 FB |
143 | void cpu_dump_state(CPUState * env, FILE * f, |
144 | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), | |
145 | int flags) | |
146 | { | |
147 | int i; | |
eda9b09b FB |
148 | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", |
149 | env->pc, env->sr, env->pr, env->fpscr); | |
274a9e70 AJ |
150 | cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", |
151 | env->spc, env->ssr, env->gbr, env->vbr); | |
152 | cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", | |
153 | env->sgr, env->dbr, env->delayed_pc, env->fpul); | |
fdf9b3e8 FB |
154 | for (i = 0; i < 24; i += 4) { |
155 | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", | |
156 | i, env->gregs[i], i + 1, env->gregs[i + 1], | |
157 | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); | |
158 | } | |
159 | if (env->flags & DELAY_SLOT) { | |
160 | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", | |
161 | env->delayed_pc); | |
162 | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { | |
163 | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", | |
164 | env->delayed_pc); | |
165 | } | |
166 | } | |
167 | ||
168 | void cpu_sh4_reset(CPUSH4State * env) | |
169 | { | |
9c2a9ea1 | 170 | #if defined(CONFIG_USER_ONLY) |
4c909d14 | 171 | env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */ |
9c2a9ea1 | 172 | #else |
fdf9b3e8 | 173 | env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */ |
9c2a9ea1 | 174 | #endif |
fdf9b3e8 FB |
175 | env->vbr = 0; |
176 | env->pc = 0xA0000000; | |
ea6cf6be TS |
177 | #if defined(CONFIG_USER_ONLY) |
178 | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ | |
b0b3de89 | 179 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ |
ea6cf6be TS |
180 | #else |
181 | env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ | |
b0b3de89 | 182 | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
ea6cf6be | 183 | #endif |
fdf9b3e8 FB |
184 | env->mmucr = 0; |
185 | } | |
186 | ||
0fd3ca30 | 187 | typedef struct { |
b55266b5 | 188 | const char *name; |
0fd3ca30 AJ |
189 | int id; |
190 | uint32_t pvr; | |
191 | uint32_t prr; | |
192 | uint32_t cvr; | |
193 | } sh4_def_t; | |
194 | ||
195 | static sh4_def_t sh4_defs[] = { | |
196 | { | |
197 | .name = "SH7750R", | |
198 | .id = SH_CPU_SH7750R, | |
199 | .pvr = 0x00050000, | |
200 | .prr = 0x00000100, | |
201 | .cvr = 0x00110000, | |
202 | }, { | |
203 | .name = "SH7751R", | |
204 | .id = SH_CPU_SH7751R, | |
205 | .pvr = 0x04050005, | |
206 | .prr = 0x00000113, | |
207 | .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */ | |
208 | }, | |
209 | }; | |
210 | ||
b55266b5 | 211 | static const sh4_def_t *cpu_sh4_find_by_name(const char *name) |
0fd3ca30 AJ |
212 | { |
213 | int i; | |
214 | ||
215 | if (strcasecmp(name, "any") == 0) | |
216 | return &sh4_defs[0]; | |
217 | ||
218 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) | |
219 | if (strcasecmp(name, sh4_defs[i].name) == 0) | |
220 | return &sh4_defs[i]; | |
221 | ||
222 | return NULL; | |
223 | } | |
224 | ||
225 | void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
226 | { | |
227 | int i; | |
228 | ||
229 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) | |
230 | (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name); | |
231 | } | |
232 | ||
1ed1a787 | 233 | static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def) |
0fd3ca30 AJ |
234 | { |
235 | env->pvr = def->pvr; | |
236 | env->prr = def->prr; | |
237 | env->cvr = def->cvr; | |
238 | env->id = def->id; | |
239 | } | |
240 | ||
aaed909a | 241 | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
fdf9b3e8 FB |
242 | { |
243 | CPUSH4State *env; | |
0fd3ca30 | 244 | const sh4_def_t *def; |
fdf9b3e8 | 245 | |
0fd3ca30 AJ |
246 | def = cpu_sh4_find_by_name(cpu_model); |
247 | if (!def) | |
248 | return NULL; | |
fdf9b3e8 FB |
249 | env = qemu_mallocz(sizeof(CPUSH4State)); |
250 | if (!env) | |
251 | return NULL; | |
252 | cpu_exec_init(env); | |
2e70f6ef | 253 | sh4_translate_init(); |
7478757e | 254 | env->cpu_model_str = cpu_model; |
fdf9b3e8 | 255 | cpu_sh4_reset(env); |
0fd3ca30 | 256 | cpu_sh4_register(env, def); |
fdf9b3e8 FB |
257 | tlb_flush(env, 1); |
258 | return env; | |
259 | } | |
260 | ||
fdf9b3e8 FB |
261 | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
262 | { | |
263 | TranslationBlock *tb; | |
264 | tb = ctx->tb; | |
265 | ||
266 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && | |
267 | !ctx->singlestep_enabled) { | |
268 | /* Use a direct jump if in same page and singlestep not enabled */ | |
57fec1fe | 269 | tcg_gen_goto_tb(n); |
3a8a44c4 | 270 | tcg_gen_movi_i32(cpu_pc, dest); |
57fec1fe | 271 | tcg_gen_exit_tb((long) tb + n); |
fdf9b3e8 | 272 | } else { |
3a8a44c4 | 273 | tcg_gen_movi_i32(cpu_pc, dest); |
57fec1fe | 274 | if (ctx->singlestep_enabled) |
a7812ae4 | 275 | gen_helper_debug(); |
57fec1fe | 276 | tcg_gen_exit_tb(0); |
fdf9b3e8 | 277 | } |
fdf9b3e8 FB |
278 | } |
279 | ||
fdf9b3e8 FB |
280 | static void gen_jump(DisasContext * ctx) |
281 | { | |
282 | if (ctx->delayed_pc == (uint32_t) - 1) { | |
283 | /* Target is not statically known, it comes necessarily from a | |
284 | delayed jump as immediate jump are conditinal jumps */ | |
1000822b | 285 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
fdf9b3e8 | 286 | if (ctx->singlestep_enabled) |
a7812ae4 | 287 | gen_helper_debug(); |
57fec1fe | 288 | tcg_gen_exit_tb(0); |
fdf9b3e8 FB |
289 | } else { |
290 | gen_goto_tb(ctx, 0, ctx->delayed_pc); | |
291 | } | |
292 | } | |
293 | ||
1000822b AJ |
294 | static inline void gen_branch_slot(uint32_t delayed_pc, int t) |
295 | { | |
c55497ec | 296 | TCGv sr; |
1000822b AJ |
297 | int label = gen_new_label(); |
298 | tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); | |
a7812ae4 | 299 | sr = tcg_temp_new(); |
c55497ec AJ |
300 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
301 | tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label); | |
1000822b AJ |
302 | tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
303 | gen_set_label(label); | |
304 | } | |
305 | ||
fdf9b3e8 FB |
306 | /* Immediate conditional jump (bt or bf) */ |
307 | static void gen_conditional_jump(DisasContext * ctx, | |
308 | target_ulong ift, target_ulong ifnott) | |
309 | { | |
310 | int l1; | |
c55497ec | 311 | TCGv sr; |
fdf9b3e8 FB |
312 | |
313 | l1 = gen_new_label(); | |
a7812ae4 | 314 | sr = tcg_temp_new(); |
c55497ec AJ |
315 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
316 | tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1); | |
fdf9b3e8 FB |
317 | gen_goto_tb(ctx, 0, ifnott); |
318 | gen_set_label(l1); | |
319 | gen_goto_tb(ctx, 1, ift); | |
320 | } | |
321 | ||
322 | /* Delayed conditional jump (bt or bf) */ | |
323 | static void gen_delayed_conditional_jump(DisasContext * ctx) | |
324 | { | |
325 | int l1; | |
c55497ec | 326 | TCGv ds; |
fdf9b3e8 FB |
327 | |
328 | l1 = gen_new_label(); | |
a7812ae4 | 329 | ds = tcg_temp_new(); |
c55497ec AJ |
330 | tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE); |
331 | tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1); | |
823029f9 | 332 | gen_goto_tb(ctx, 1, ctx->pc + 2); |
fdf9b3e8 | 333 | gen_set_label(l1); |
1000822b | 334 | tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE); |
9c2a9ea1 | 335 | gen_jump(ctx); |
fdf9b3e8 FB |
336 | } |
337 | ||
a4625612 AJ |
338 | static inline void gen_set_t(void) |
339 | { | |
340 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); | |
341 | } | |
342 | ||
343 | static inline void gen_clr_t(void) | |
344 | { | |
345 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); | |
346 | } | |
347 | ||
348 | static inline void gen_cmp(int cond, TCGv t0, TCGv t1) | |
349 | { | |
350 | int label1 = gen_new_label(); | |
351 | int label2 = gen_new_label(); | |
352 | tcg_gen_brcond_i32(cond, t1, t0, label1); | |
353 | gen_clr_t(); | |
354 | tcg_gen_br(label2); | |
355 | gen_set_label(label1); | |
356 | gen_set_t(); | |
357 | gen_set_label(label2); | |
358 | } | |
359 | ||
360 | static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) | |
361 | { | |
362 | int label1 = gen_new_label(); | |
363 | int label2 = gen_new_label(); | |
364 | tcg_gen_brcondi_i32(cond, t0, imm, label1); | |
365 | gen_clr_t(); | |
366 | tcg_gen_br(label2); | |
367 | gen_set_label(label1); | |
368 | gen_set_t(); | |
369 | gen_set_label(label2); | |
370 | } | |
371 | ||
1000822b AJ |
372 | static inline void gen_store_flags(uint32_t flags) |
373 | { | |
374 | tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); | |
375 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); | |
376 | } | |
377 | ||
69d6275b AJ |
378 | static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) |
379 | { | |
a7812ae4 | 380 | TCGv tmp = tcg_temp_new(); |
69d6275b AJ |
381 | |
382 | p0 &= 0x1f; | |
383 | p1 &= 0x1f; | |
384 | ||
385 | tcg_gen_andi_i32(tmp, t1, (1 << p1)); | |
386 | tcg_gen_andi_i32(t0, t0, ~(1 << p0)); | |
387 | if (p0 < p1) | |
388 | tcg_gen_shri_i32(tmp, tmp, p1 - p0); | |
389 | else if (p0 > p1) | |
390 | tcg_gen_shli_i32(tmp, tmp, p0 - p1); | |
391 | tcg_gen_or_i32(t0, t0, tmp); | |
392 | ||
393 | tcg_temp_free(tmp); | |
394 | } | |
395 | ||
cc4ba6a9 | 396 | |
a7812ae4 | 397 | static inline void gen_load_fpr32(TCGv_i32 t, int reg) |
cc4ba6a9 AJ |
398 | { |
399 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg])); | |
400 | } | |
401 | ||
a7812ae4 | 402 | static inline void gen_load_fpr64(TCGv_i64 t, int reg) |
cc4ba6a9 | 403 | { |
a7812ae4 PB |
404 | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
405 | TCGv_i32 tmp2 = tcg_temp_new_i32(); | |
cc4ba6a9 AJ |
406 | |
407 | tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg])); | |
36aa55dc PB |
408 | tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1])); |
409 | tcg_gen_concat_i32_i64(t, tmp2, tmp1); | |
a7812ae4 PB |
410 | tcg_temp_free_i32(tmp1); |
411 | tcg_temp_free_i32(tmp2); | |
cc4ba6a9 AJ |
412 | } |
413 | ||
a7812ae4 | 414 | static inline void gen_store_fpr32(TCGv_i32 t, int reg) |
cc4ba6a9 AJ |
415 | { |
416 | tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg])); | |
417 | } | |
418 | ||
a7812ae4 | 419 | static inline void gen_store_fpr64 (TCGv_i64 t, int reg) |
cc4ba6a9 | 420 | { |
a7812ae4 | 421 | TCGv_i32 tmp = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
422 | |
423 | tcg_gen_trunc_i64_i32(tmp, t); | |
424 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1])); | |
425 | tcg_gen_shri_i64(t, t, 32); | |
426 | tcg_gen_trunc_i64_i32(tmp, t); | |
427 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg])); | |
a7812ae4 | 428 | tcg_temp_free_i32(tmp); |
cc4ba6a9 AJ |
429 | } |
430 | ||
fdf9b3e8 FB |
431 | #define B3_0 (ctx->opcode & 0xf) |
432 | #define B6_4 ((ctx->opcode >> 4) & 0x7) | |
433 | #define B7_4 ((ctx->opcode >> 4) & 0xf) | |
434 | #define B7_0 (ctx->opcode & 0xff) | |
435 | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) | |
436 | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ | |
437 | (ctx->opcode & 0xfff)) | |
438 | #define B11_8 ((ctx->opcode >> 8) & 0xf) | |
439 | #define B15_12 ((ctx->opcode >> 12) & 0xf) | |
440 | ||
441 | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ | |
7efbe241 | 442 | (cpu_gregs[x + 16]) : (cpu_gregs[x])) |
fdf9b3e8 FB |
443 | |
444 | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ | |
7efbe241 | 445 | ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) |
fdf9b3e8 | 446 | |
eda9b09b | 447 | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
f09111e0 | 448 | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
eda9b09b | 449 | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
ea6cf6be | 450 | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
eda9b09b | 451 | |
fdf9b3e8 FB |
452 | #define CHECK_NOT_DELAY_SLOT \ |
453 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \ | |
a7812ae4 | 454 | {gen_helper_raise_slot_illegal_instruction(); ctx->bstate = BS_EXCP; \ |
fdf9b3e8 FB |
455 | return;} |
456 | ||
fe25591e AJ |
457 | #define CHECK_PRIVILEGED \ |
458 | if (IS_USER(ctx)) { \ | |
a7812ae4 | 459 | gen_helper_raise_illegal_instruction(); \ |
fe25591e AJ |
460 | ctx->bstate = BS_EXCP; \ |
461 | return; \ | |
462 | } | |
463 | ||
b1d8e52e | 464 | static void _decode_opc(DisasContext * ctx) |
fdf9b3e8 FB |
465 | { |
466 | #if 0 | |
467 | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); | |
468 | #endif | |
469 | switch (ctx->opcode) { | |
470 | case 0x0019: /* div0u */ | |
3a8a44c4 | 471 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); |
fdf9b3e8 FB |
472 | return; |
473 | case 0x000b: /* rts */ | |
1000822b AJ |
474 | CHECK_NOT_DELAY_SLOT |
475 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); | |
fdf9b3e8 FB |
476 | ctx->flags |= DELAY_SLOT; |
477 | ctx->delayed_pc = (uint32_t) - 1; | |
478 | return; | |
479 | case 0x0028: /* clrmac */ | |
3a8a44c4 AJ |
480 | tcg_gen_movi_i32(cpu_mach, 0); |
481 | tcg_gen_movi_i32(cpu_macl, 0); | |
fdf9b3e8 FB |
482 | return; |
483 | case 0x0048: /* clrs */ | |
3a8a44c4 | 484 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); |
fdf9b3e8 FB |
485 | return; |
486 | case 0x0008: /* clrt */ | |
a4625612 | 487 | gen_clr_t(); |
fdf9b3e8 FB |
488 | return; |
489 | case 0x0038: /* ldtlb */ | |
fe25591e | 490 | CHECK_PRIVILEGED |
a7812ae4 | 491 | gen_helper_ldtlb(); |
fdf9b3e8 | 492 | return; |
c5e814b2 | 493 | case 0x002b: /* rte */ |
fe25591e | 494 | CHECK_PRIVILEGED |
1000822b AJ |
495 | CHECK_NOT_DELAY_SLOT |
496 | tcg_gen_mov_i32(cpu_sr, cpu_ssr); | |
497 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); | |
fdf9b3e8 FB |
498 | ctx->flags |= DELAY_SLOT; |
499 | ctx->delayed_pc = (uint32_t) - 1; | |
500 | return; | |
501 | case 0x0058: /* sets */ | |
3a8a44c4 | 502 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); |
fdf9b3e8 FB |
503 | return; |
504 | case 0x0018: /* sett */ | |
a4625612 | 505 | gen_set_t(); |
fdf9b3e8 | 506 | return; |
24988dc2 | 507 | case 0xfbfd: /* frchg */ |
6f06939b | 508 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); |
823029f9 | 509 | ctx->bstate = BS_STOP; |
fdf9b3e8 | 510 | return; |
24988dc2 | 511 | case 0xf3fd: /* fschg */ |
6f06939b | 512 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); |
823029f9 | 513 | ctx->bstate = BS_STOP; |
fdf9b3e8 FB |
514 | return; |
515 | case 0x0009: /* nop */ | |
516 | return; | |
517 | case 0x001b: /* sleep */ | |
fe25591e | 518 | CHECK_PRIVILEGED |
a7812ae4 | 519 | gen_helper_sleep(tcg_const_i32(ctx->pc + 2)); |
fdf9b3e8 FB |
520 | return; |
521 | } | |
522 | ||
523 | switch (ctx->opcode & 0xf000) { | |
524 | case 0x1000: /* mov.l Rm,@(disp,Rn) */ | |
c55497ec | 525 | { |
a7812ae4 | 526 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
527 | tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); |
528 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
529 | tcg_temp_free(addr); | |
530 | } | |
fdf9b3e8 FB |
531 | return; |
532 | case 0x5000: /* mov.l @(disp,Rm),Rn */ | |
c55497ec | 533 | { |
a7812ae4 | 534 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
535 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); |
536 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
537 | tcg_temp_free(addr); | |
538 | } | |
fdf9b3e8 | 539 | return; |
24988dc2 | 540 | case 0xe000: /* mov #imm,Rn */ |
7efbe241 | 541 | tcg_gen_movi_i32(REG(B11_8), B7_0s); |
fdf9b3e8 FB |
542 | return; |
543 | case 0x9000: /* mov.w @(disp,PC),Rn */ | |
c55497ec AJ |
544 | { |
545 | TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2); | |
546 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); | |
547 | tcg_temp_free(addr); | |
548 | } | |
fdf9b3e8 FB |
549 | return; |
550 | case 0xd000: /* mov.l @(disp,PC),Rn */ | |
c55497ec AJ |
551 | { |
552 | TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); | |
553 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
554 | tcg_temp_free(addr); | |
555 | } | |
fdf9b3e8 | 556 | return; |
24988dc2 | 557 | case 0x7000: /* add #imm,Rn */ |
7efbe241 | 558 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s); |
fdf9b3e8 FB |
559 | return; |
560 | case 0xa000: /* bra disp */ | |
561 | CHECK_NOT_DELAY_SLOT | |
1000822b AJ |
562 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
563 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); | |
fdf9b3e8 FB |
564 | ctx->flags |= DELAY_SLOT; |
565 | return; | |
566 | case 0xb000: /* bsr disp */ | |
567 | CHECK_NOT_DELAY_SLOT | |
1000822b AJ |
568 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
569 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; | |
570 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); | |
fdf9b3e8 FB |
571 | ctx->flags |= DELAY_SLOT; |
572 | return; | |
573 | } | |
574 | ||
575 | switch (ctx->opcode & 0xf00f) { | |
576 | case 0x6003: /* mov Rm,Rn */ | |
7efbe241 | 577 | tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
578 | return; |
579 | case 0x2000: /* mov.b Rm,@Rn */ | |
7efbe241 | 580 | tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
581 | return; |
582 | case 0x2001: /* mov.w Rm,@Rn */ | |
7efbe241 | 583 | tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
584 | return; |
585 | case 0x2002: /* mov.l Rm,@Rn */ | |
7efbe241 | 586 | tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx); |
fdf9b3e8 FB |
587 | return; |
588 | case 0x6000: /* mov.b @Rm,Rn */ | |
7efbe241 | 589 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
590 | return; |
591 | case 0x6001: /* mov.w @Rm,Rn */ | |
7efbe241 | 592 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
593 | return; |
594 | case 0x6002: /* mov.l @Rm,Rn */ | |
7efbe241 | 595 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
fdf9b3e8 FB |
596 | return; |
597 | case 0x2004: /* mov.b Rm,@-Rn */ | |
c55497ec | 598 | { |
a7812ae4 | 599 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
600 | tcg_gen_subi_i32(addr, REG(B11_8), 1); |
601 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */ | |
602 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */ | |
603 | tcg_temp_free(addr); | |
604 | } | |
fdf9b3e8 FB |
605 | return; |
606 | case 0x2005: /* mov.w Rm,@-Rn */ | |
c55497ec | 607 | { |
a7812ae4 | 608 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
609 | tcg_gen_subi_i32(addr, REG(B11_8), 2); |
610 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); | |
611 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2); | |
612 | tcg_temp_free(addr); | |
613 | } | |
fdf9b3e8 FB |
614 | return; |
615 | case 0x2006: /* mov.l Rm,@-Rn */ | |
c55497ec | 616 | { |
a7812ae4 | 617 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
618 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
619 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
620 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
621 | } | |
fdf9b3e8 | 622 | return; |
eda9b09b | 623 | case 0x6004: /* mov.b @Rm+,Rn */ |
7efbe241 | 624 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 625 | if ( B11_8 != B7_4 ) |
7efbe241 | 626 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); |
fdf9b3e8 FB |
627 | return; |
628 | case 0x6005: /* mov.w @Rm+,Rn */ | |
7efbe241 | 629 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 630 | if ( B11_8 != B7_4 ) |
7efbe241 | 631 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); |
fdf9b3e8 FB |
632 | return; |
633 | case 0x6006: /* mov.l @Rm+,Rn */ | |
7efbe241 | 634 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
24988dc2 | 635 | if ( B11_8 != B7_4 ) |
7efbe241 | 636 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
fdf9b3e8 FB |
637 | return; |
638 | case 0x0004: /* mov.b Rm,@(R0,Rn) */ | |
c55497ec | 639 | { |
a7812ae4 | 640 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
641 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
642 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); | |
643 | tcg_temp_free(addr); | |
644 | } | |
fdf9b3e8 FB |
645 | return; |
646 | case 0x0005: /* mov.w Rm,@(R0,Rn) */ | |
c55497ec | 647 | { |
a7812ae4 | 648 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
649 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
650 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); | |
651 | tcg_temp_free(addr); | |
652 | } | |
fdf9b3e8 FB |
653 | return; |
654 | case 0x0006: /* mov.l Rm,@(R0,Rn) */ | |
c55497ec | 655 | { |
a7812ae4 | 656 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
657 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
658 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); | |
659 | tcg_temp_free(addr); | |
660 | } | |
fdf9b3e8 FB |
661 | return; |
662 | case 0x000c: /* mov.b @(R0,Rm),Rn */ | |
c55497ec | 663 | { |
a7812ae4 | 664 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
665 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
666 | tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx); | |
667 | tcg_temp_free(addr); | |
668 | } | |
fdf9b3e8 FB |
669 | return; |
670 | case 0x000d: /* mov.w @(R0,Rm),Rn */ | |
c55497ec | 671 | { |
a7812ae4 | 672 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
673 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
674 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); | |
675 | tcg_temp_free(addr); | |
676 | } | |
fdf9b3e8 FB |
677 | return; |
678 | case 0x000e: /* mov.l @(R0,Rm),Rn */ | |
c55497ec | 679 | { |
a7812ae4 | 680 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
681 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
682 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); | |
683 | tcg_temp_free(addr); | |
684 | } | |
fdf9b3e8 FB |
685 | return; |
686 | case 0x6008: /* swap.b Rm,Rn */ | |
c55497ec | 687 | { |
c69e3264 | 688 | TCGv highw, high, low; |
a7812ae4 | 689 | highw = tcg_temp_new(); |
c69e3264 | 690 | tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000); |
a7812ae4 | 691 | high = tcg_temp_new(); |
c55497ec AJ |
692 | tcg_gen_ext8u_i32(high, REG(B7_4)); |
693 | tcg_gen_shli_i32(high, high, 8); | |
a7812ae4 | 694 | low = tcg_temp_new(); |
c55497ec AJ |
695 | tcg_gen_shri_i32(low, REG(B7_4), 8); |
696 | tcg_gen_ext8u_i32(low, low); | |
697 | tcg_gen_or_i32(REG(B11_8), high, low); | |
c69e3264 | 698 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw); |
c55497ec AJ |
699 | tcg_temp_free(low); |
700 | tcg_temp_free(high); | |
701 | } | |
fdf9b3e8 FB |
702 | return; |
703 | case 0x6009: /* swap.w Rm,Rn */ | |
c55497ec AJ |
704 | { |
705 | TCGv high, low; | |
a7812ae4 | 706 | high = tcg_temp_new(); |
c55497ec AJ |
707 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
708 | tcg_gen_shli_i32(high, high, 16); | |
a7812ae4 | 709 | low = tcg_temp_new(); |
c55497ec AJ |
710 | tcg_gen_shri_i32(low, REG(B7_4), 16); |
711 | tcg_gen_ext16u_i32(low, low); | |
712 | tcg_gen_or_i32(REG(B11_8), high, low); | |
713 | tcg_temp_free(low); | |
714 | tcg_temp_free(high); | |
715 | } | |
fdf9b3e8 FB |
716 | return; |
717 | case 0x200d: /* xtrct Rm,Rn */ | |
c55497ec AJ |
718 | { |
719 | TCGv high, low; | |
a7812ae4 | 720 | high = tcg_temp_new(); |
c55497ec AJ |
721 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
722 | tcg_gen_shli_i32(high, high, 16); | |
a7812ae4 | 723 | low = tcg_temp_new(); |
c55497ec AJ |
724 | tcg_gen_shri_i32(low, REG(B11_8), 16); |
725 | tcg_gen_ext16u_i32(low, low); | |
726 | tcg_gen_or_i32(REG(B11_8), high, low); | |
727 | tcg_temp_free(low); | |
728 | tcg_temp_free(high); | |
729 | } | |
fdf9b3e8 FB |
730 | return; |
731 | case 0x300c: /* add Rm,Rn */ | |
7efbe241 | 732 | tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
733 | return; |
734 | case 0x300e: /* addc Rm,Rn */ | |
a7812ae4 | 735 | gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
736 | return; |
737 | case 0x300f: /* addv Rm,Rn */ | |
a7812ae4 | 738 | gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
739 | return; |
740 | case 0x2009: /* and Rm,Rn */ | |
7efbe241 | 741 | tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
742 | return; |
743 | case 0x3000: /* cmp/eq Rm,Rn */ | |
7efbe241 | 744 | gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
745 | return; |
746 | case 0x3003: /* cmp/ge Rm,Rn */ | |
7efbe241 | 747 | gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
748 | return; |
749 | case 0x3007: /* cmp/gt Rm,Rn */ | |
7efbe241 | 750 | gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
751 | return; |
752 | case 0x3006: /* cmp/hi Rm,Rn */ | |
7efbe241 | 753 | gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
754 | return; |
755 | case 0x3002: /* cmp/hs Rm,Rn */ | |
7efbe241 | 756 | gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
757 | return; |
758 | case 0x200c: /* cmp/str Rm,Rn */ | |
69d6275b AJ |
759 | { |
760 | int label1 = gen_new_label(); | |
761 | int label2 = gen_new_label(); | |
c55497ec AJ |
762 | TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32); |
763 | TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32); | |
764 | tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8)); | |
765 | tcg_gen_andi_i32(cmp2, cmp1, 0xff000000); | |
766 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
767 | tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000); | |
768 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
769 | tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00); | |
770 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
771 | tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff); | |
772 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1); | |
69d6275b AJ |
773 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
774 | tcg_gen_br(label2); | |
775 | gen_set_label(label1); | |
776 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); | |
777 | gen_set_label(label2); | |
c55497ec AJ |
778 | tcg_temp_free(cmp2); |
779 | tcg_temp_free(cmp1); | |
69d6275b | 780 | } |
fdf9b3e8 FB |
781 | return; |
782 | case 0x2007: /* div0s Rm,Rn */ | |
c55497ec AJ |
783 | { |
784 | gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */ | |
785 | gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */ | |
a7812ae4 | 786 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
787 | tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); |
788 | gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */ | |
789 | tcg_temp_free(val); | |
790 | } | |
fdf9b3e8 FB |
791 | return; |
792 | case 0x3004: /* div1 Rm,Rn */ | |
a7812ae4 | 793 | gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
794 | return; |
795 | case 0x300d: /* dmuls.l Rm,Rn */ | |
6f06939b | 796 | { |
a7812ae4 PB |
797 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
798 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
6f06939b | 799 | |
7efbe241 AJ |
800 | tcg_gen_ext_i32_i64(tmp1, REG(B7_4)); |
801 | tcg_gen_ext_i32_i64(tmp2, REG(B11_8)); | |
6f06939b AJ |
802 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
803 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); | |
804 | tcg_gen_shri_i64(tmp1, tmp1, 32); | |
805 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); | |
806 | ||
a7812ae4 PB |
807 | tcg_temp_free_i64(tmp2); |
808 | tcg_temp_free_i64(tmp1); | |
6f06939b | 809 | } |
fdf9b3e8 FB |
810 | return; |
811 | case 0x3005: /* dmulu.l Rm,Rn */ | |
6f06939b | 812 | { |
a7812ae4 PB |
813 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
814 | TCGv_i64 tmp2 = tcg_temp_new_i64(); | |
6f06939b | 815 | |
7efbe241 AJ |
816 | tcg_gen_extu_i32_i64(tmp1, REG(B7_4)); |
817 | tcg_gen_extu_i32_i64(tmp2, REG(B11_8)); | |
6f06939b AJ |
818 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
819 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); | |
820 | tcg_gen_shri_i64(tmp1, tmp1, 32); | |
821 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); | |
822 | ||
a7812ae4 PB |
823 | tcg_temp_free_i64(tmp2); |
824 | tcg_temp_free_i64(tmp1); | |
6f06939b | 825 | } |
fdf9b3e8 FB |
826 | return; |
827 | case 0x600e: /* exts.b Rm,Rn */ | |
7efbe241 | 828 | tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
829 | return; |
830 | case 0x600f: /* exts.w Rm,Rn */ | |
7efbe241 | 831 | tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
832 | return; |
833 | case 0x600c: /* extu.b Rm,Rn */ | |
7efbe241 | 834 | tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
835 | return; |
836 | case 0x600d: /* extu.w Rm,Rn */ | |
7efbe241 | 837 | tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 | 838 | return; |
24988dc2 | 839 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
c55497ec AJ |
840 | { |
841 | TCGv arg0, arg1; | |
a7812ae4 | 842 | arg0 = tcg_temp_new(); |
c55497ec | 843 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
a7812ae4 | 844 | arg1 = tcg_temp_new(); |
c55497ec | 845 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
a7812ae4 | 846 | gen_helper_macl(arg0, arg1); |
c55497ec AJ |
847 | tcg_temp_free(arg1); |
848 | tcg_temp_free(arg0); | |
849 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); | |
850 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
851 | } | |
fdf9b3e8 FB |
852 | return; |
853 | case 0x400f: /* mac.w @Rm+,@Rn+ */ | |
c55497ec AJ |
854 | { |
855 | TCGv arg0, arg1; | |
a7812ae4 | 856 | arg0 = tcg_temp_new(); |
c55497ec | 857 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
a7812ae4 | 858 | arg1 = tcg_temp_new(); |
c55497ec | 859 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
a7812ae4 | 860 | gen_helper_macw(arg0, arg1); |
c55497ec AJ |
861 | tcg_temp_free(arg1); |
862 | tcg_temp_free(arg0); | |
863 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); | |
864 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); | |
865 | } | |
fdf9b3e8 FB |
866 | return; |
867 | case 0x0007: /* mul.l Rm,Rn */ | |
7efbe241 | 868 | tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
869 | return; |
870 | case 0x200f: /* muls.w Rm,Rn */ | |
c55497ec AJ |
871 | { |
872 | TCGv arg0, arg1; | |
a7812ae4 | 873 | arg0 = tcg_temp_new(); |
c55497ec | 874 | tcg_gen_ext16s_i32(arg0, REG(B7_4)); |
a7812ae4 | 875 | arg1 = tcg_temp_new(); |
c55497ec AJ |
876 | tcg_gen_ext16s_i32(arg1, REG(B11_8)); |
877 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); | |
878 | tcg_temp_free(arg1); | |
879 | tcg_temp_free(arg0); | |
880 | } | |
fdf9b3e8 FB |
881 | return; |
882 | case 0x200e: /* mulu.w Rm,Rn */ | |
c55497ec AJ |
883 | { |
884 | TCGv arg0, arg1; | |
a7812ae4 | 885 | arg0 = tcg_temp_new(); |
c55497ec | 886 | tcg_gen_ext16u_i32(arg0, REG(B7_4)); |
a7812ae4 | 887 | arg1 = tcg_temp_new(); |
c55497ec AJ |
888 | tcg_gen_ext16u_i32(arg1, REG(B11_8)); |
889 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); | |
890 | tcg_temp_free(arg1); | |
891 | tcg_temp_free(arg0); | |
892 | } | |
fdf9b3e8 FB |
893 | return; |
894 | case 0x600b: /* neg Rm,Rn */ | |
7efbe241 | 895 | tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
896 | return; |
897 | case 0x600a: /* negc Rm,Rn */ | |
a7812ae4 | 898 | gen_helper_negc(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
899 | return; |
900 | case 0x6007: /* not Rm,Rn */ | |
7efbe241 | 901 | tcg_gen_not_i32(REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
902 | return; |
903 | case 0x200b: /* or Rm,Rn */ | |
7efbe241 | 904 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
905 | return; |
906 | case 0x400c: /* shad Rm,Rn */ | |
69d6275b AJ |
907 | { |
908 | int label1 = gen_new_label(); | |
909 | int label2 = gen_new_label(); | |
910 | int label3 = gen_new_label(); | |
911 | int label4 = gen_new_label(); | |
c55497ec | 912 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
7efbe241 | 913 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
69d6275b | 914 | /* Rm positive, shift to the left */ |
c55497ec AJ |
915 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
916 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
917 | tcg_gen_br(label4); |
918 | /* Rm negative, shift to the right */ | |
919 | gen_set_label(label1); | |
c55497ec AJ |
920 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
921 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); | |
922 | tcg_gen_not_i32(shift, REG(B7_4)); | |
923 | tcg_gen_andi_i32(shift, shift, 0x1f); | |
924 | tcg_gen_addi_i32(shift, shift, 1); | |
925 | tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
926 | tcg_gen_br(label4); |
927 | /* Rm = -32 */ | |
928 | gen_set_label(label2); | |
7efbe241 AJ |
929 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3); |
930 | tcg_gen_movi_i32(REG(B11_8), 0); | |
69d6275b AJ |
931 | tcg_gen_br(label4); |
932 | gen_set_label(label3); | |
7efbe241 | 933 | tcg_gen_movi_i32(REG(B11_8), 0xffffffff); |
69d6275b | 934 | gen_set_label(label4); |
c55497ec | 935 | tcg_temp_free(shift); |
69d6275b | 936 | } |
fdf9b3e8 FB |
937 | return; |
938 | case 0x400d: /* shld Rm,Rn */ | |
69d6275b AJ |
939 | { |
940 | int label1 = gen_new_label(); | |
941 | int label2 = gen_new_label(); | |
942 | int label3 = gen_new_label(); | |
c55497ec | 943 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
7efbe241 | 944 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1); |
69d6275b | 945 | /* Rm positive, shift to the left */ |
c55497ec AJ |
946 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
947 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
948 | tcg_gen_br(label3); |
949 | /* Rm negative, shift to the right */ | |
950 | gen_set_label(label1); | |
c55497ec AJ |
951 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f); |
952 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2); | |
953 | tcg_gen_not_i32(shift, REG(B7_4)); | |
954 | tcg_gen_andi_i32(shift, shift, 0x1f); | |
955 | tcg_gen_addi_i32(shift, shift, 1); | |
956 | tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift); | |
69d6275b AJ |
957 | tcg_gen_br(label3); |
958 | /* Rm = -32 */ | |
959 | gen_set_label(label2); | |
7efbe241 | 960 | tcg_gen_movi_i32(REG(B11_8), 0); |
69d6275b | 961 | gen_set_label(label3); |
c55497ec | 962 | tcg_temp_free(shift); |
69d6275b | 963 | } |
fdf9b3e8 FB |
964 | return; |
965 | case 0x3008: /* sub Rm,Rn */ | |
7efbe241 | 966 | tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 FB |
967 | return; |
968 | case 0x300a: /* subc Rm,Rn */ | |
a7812ae4 | 969 | gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
970 | return; |
971 | case 0x300b: /* subv Rm,Rn */ | |
a7812ae4 | 972 | gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8)); |
fdf9b3e8 FB |
973 | return; |
974 | case 0x2008: /* tst Rm,Rn */ | |
c55497ec | 975 | { |
a7812ae4 | 976 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
977 | tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); |
978 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
979 | tcg_temp_free(val); | |
980 | } | |
fdf9b3e8 FB |
981 | return; |
982 | case 0x200a: /* xor Rm,Rn */ | |
7efbe241 | 983 | tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
fdf9b3e8 | 984 | return; |
e67888a7 | 985 | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
022a22c7 | 986 | if (ctx->fpscr & FPSCR_SZ) { |
a7812ae4 | 987 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 AJ |
988 | gen_load_fpr64(fp, XREG(B7_4)); |
989 | gen_store_fpr64(fp, XREG(B11_8)); | |
a7812ae4 | 990 | tcg_temp_free_i64(fp); |
eda9b09b | 991 | } else { |
a7812ae4 | 992 | TCGv_i32 fp = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
993 | gen_load_fpr32(fp, FREG(B7_4)); |
994 | gen_store_fpr32(fp, FREG(B11_8)); | |
a7812ae4 | 995 | tcg_temp_free_i32(fp); |
eda9b09b FB |
996 | } |
997 | return; | |
e67888a7 | 998 | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
022a22c7 | 999 | if (ctx->fpscr & FPSCR_SZ) { |
a7812ae4 | 1000 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 AJ |
1001 | gen_load_fpr64(fp, XREG(B7_4)); |
1002 | tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx); | |
a7812ae4 | 1003 | tcg_temp_free_i64(fp); |
eda9b09b | 1004 | } else { |
a7812ae4 | 1005 | TCGv_i32 fp = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
1006 | gen_load_fpr32(fp, FREG(B7_4)); |
1007 | tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx); | |
a7812ae4 | 1008 | tcg_temp_free_i32(fp); |
eda9b09b FB |
1009 | } |
1010 | return; | |
e67888a7 | 1011 | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
022a22c7 | 1012 | if (ctx->fpscr & FPSCR_SZ) { |
a7812ae4 | 1013 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 AJ |
1014 | tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); |
1015 | gen_store_fpr64(fp, XREG(B11_8)); | |
a7812ae4 | 1016 | tcg_temp_free_i64(fp); |
eda9b09b | 1017 | } else { |
a7812ae4 | 1018 | TCGv_i32 fp = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
1019 | tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx); |
1020 | gen_store_fpr32(fp, FREG(B11_8)); | |
a7812ae4 | 1021 | tcg_temp_free_i32(fp); |
eda9b09b FB |
1022 | } |
1023 | return; | |
e67888a7 | 1024 | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
022a22c7 | 1025 | if (ctx->fpscr & FPSCR_SZ) { |
a7812ae4 | 1026 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 AJ |
1027 | tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx); |
1028 | gen_store_fpr64(fp, XREG(B11_8)); | |
a7812ae4 | 1029 | tcg_temp_free_i64(fp); |
cc4ba6a9 | 1030 | tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8); |
eda9b09b | 1031 | } else { |
a7812ae4 | 1032 | TCGv_i32 fp = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
1033 | tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx); |
1034 | gen_store_fpr32(fp, FREG(B11_8)); | |
a7812ae4 | 1035 | tcg_temp_free_i32(fp); |
cc4ba6a9 | 1036 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
eda9b09b FB |
1037 | } |
1038 | return; | |
e67888a7 | 1039 | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
022a22c7 | 1040 | if (ctx->fpscr & FPSCR_SZ) { |
a7812ae4 PB |
1041 | TCGv addr; |
1042 | TCGv_i64 fp; | |
1043 | addr = tcg_temp_new(); | |
cc4ba6a9 | 1044 | tcg_gen_subi_i32(addr, REG(B11_8), 8); |
a7812ae4 | 1045 | fp = tcg_temp_new_i64(); |
cc4ba6a9 AJ |
1046 | gen_load_fpr64(fp, XREG(B7_4)); |
1047 | tcg_gen_qemu_st64(fp, addr, ctx->memidx); | |
a7812ae4 | 1048 | tcg_temp_free_i64(fp); |
cc4ba6a9 | 1049 | tcg_temp_free(addr); |
7efbe241 | 1050 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8); |
eda9b09b | 1051 | } else { |
a7812ae4 PB |
1052 | TCGv addr; |
1053 | TCGv_i32 fp; | |
1054 | addr = tcg_temp_new_i32(); | |
cc4ba6a9 | 1055 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
a7812ae4 | 1056 | fp = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
1057 | gen_load_fpr32(fp, FREG(B7_4)); |
1058 | tcg_gen_qemu_st32(fp, addr, ctx->memidx); | |
a7812ae4 | 1059 | tcg_temp_free_i32(fp); |
cc4ba6a9 | 1060 | tcg_temp_free(addr); |
7efbe241 | 1061 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); |
eda9b09b FB |
1062 | } |
1063 | return; | |
e67888a7 | 1064 | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
cc4ba6a9 | 1065 | { |
a7812ae4 | 1066 | TCGv addr = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
1067 | tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
1068 | if (ctx->fpscr & FPSCR_SZ) { | |
a7812ae4 | 1069 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 AJ |
1070 | tcg_gen_qemu_ld64(fp, addr, ctx->memidx); |
1071 | gen_store_fpr64(fp, XREG(B11_8)); | |
a7812ae4 | 1072 | tcg_temp_free_i64(fp); |
cc4ba6a9 | 1073 | } else { |
a7812ae4 | 1074 | TCGv_i32 fp = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
1075 | tcg_gen_qemu_ld32u(fp, addr, ctx->memidx); |
1076 | gen_store_fpr32(fp, FREG(B11_8)); | |
a7812ae4 | 1077 | tcg_temp_free_i32(fp); |
cc4ba6a9 AJ |
1078 | } |
1079 | tcg_temp_free(addr); | |
eda9b09b FB |
1080 | } |
1081 | return; | |
e67888a7 | 1082 | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
cc4ba6a9 | 1083 | { |
a7812ae4 | 1084 | TCGv addr = tcg_temp_new(); |
cc4ba6a9 AJ |
1085 | tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
1086 | if (ctx->fpscr & FPSCR_SZ) { | |
a7812ae4 | 1087 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 AJ |
1088 | gen_load_fpr64(fp, XREG(B7_4)); |
1089 | tcg_gen_qemu_st64(fp, addr, ctx->memidx); | |
a7812ae4 | 1090 | tcg_temp_free_i64(fp); |
cc4ba6a9 | 1091 | } else { |
a7812ae4 | 1092 | TCGv_i32 fp = tcg_temp_new_i32(); |
cc4ba6a9 AJ |
1093 | gen_load_fpr32(fp, FREG(B7_4)); |
1094 | tcg_gen_qemu_st32(fp, addr, ctx->memidx); | |
a7812ae4 | 1095 | tcg_temp_free_i32(fp); |
cc4ba6a9 AJ |
1096 | } |
1097 | tcg_temp_free(addr); | |
eda9b09b FB |
1098 | } |
1099 | return; | |
e67888a7 TS |
1100 | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1101 | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1102 | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1103 | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ | |
1104 | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ | |
1105 | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ | |
cc4ba6a9 | 1106 | { |
cc4ba6a9 | 1107 | if (ctx->fpscr & FPSCR_PR) { |
a7812ae4 PB |
1108 | TCGv_i64 fp0, fp1; |
1109 | ||
cc4ba6a9 AJ |
1110 | if (ctx->opcode & 0x0110) |
1111 | break; /* illegal instruction */ | |
a7812ae4 PB |
1112 | fp0 = tcg_temp_new_i64(); |
1113 | fp1 = tcg_temp_new_i64(); | |
cc4ba6a9 AJ |
1114 | gen_load_fpr64(fp0, DREG(B11_8)); |
1115 | gen_load_fpr64(fp1, DREG(B7_4)); | |
a7812ae4 PB |
1116 | switch (ctx->opcode & 0xf00f) { |
1117 | case 0xf000: /* fadd Rm,Rn */ | |
1118 | gen_helper_fadd_DT(fp0, fp0, fp1); | |
1119 | break; | |
1120 | case 0xf001: /* fsub Rm,Rn */ | |
1121 | gen_helper_fsub_DT(fp0, fp0, fp1); | |
1122 | break; | |
1123 | case 0xf002: /* fmul Rm,Rn */ | |
1124 | gen_helper_fmul_DT(fp0, fp0, fp1); | |
1125 | break; | |
1126 | case 0xf003: /* fdiv Rm,Rn */ | |
1127 | gen_helper_fdiv_DT(fp0, fp0, fp1); | |
1128 | break; | |
1129 | case 0xf004: /* fcmp/eq Rm,Rn */ | |
1130 | gen_helper_fcmp_eq_DT(fp0, fp1); | |
1131 | return; | |
1132 | case 0xf005: /* fcmp/gt Rm,Rn */ | |
1133 | gen_helper_fcmp_gt_DT(fp0, fp1); | |
1134 | return; | |
1135 | } | |
1136 | gen_store_fpr64(fp0, DREG(B11_8)); | |
1137 | tcg_temp_free_i64(fp0); | |
1138 | tcg_temp_free_i64(fp1); | |
1139 | } else { | |
1140 | TCGv_i32 fp0, fp1; | |
1141 | ||
1142 | fp0 = tcg_temp_new_i32(); | |
1143 | fp1 = tcg_temp_new_i32(); | |
cc4ba6a9 AJ |
1144 | gen_load_fpr32(fp0, FREG(B11_8)); |
1145 | gen_load_fpr32(fp1, FREG(B7_4)); | |
cc4ba6a9 | 1146 | |
a7812ae4 PB |
1147 | switch (ctx->opcode & 0xf00f) { |
1148 | case 0xf000: /* fadd Rm,Rn */ | |
1149 | gen_helper_fadd_FT(fp0, fp0, fp1); | |
1150 | break; | |
1151 | case 0xf001: /* fsub Rm,Rn */ | |
1152 | gen_helper_fsub_FT(fp0, fp0, fp1); | |
1153 | break; | |
1154 | case 0xf002: /* fmul Rm,Rn */ | |
1155 | gen_helper_fmul_FT(fp0, fp0, fp1); | |
1156 | break; | |
1157 | case 0xf003: /* fdiv Rm,Rn */ | |
1158 | gen_helper_fdiv_FT(fp0, fp0, fp1); | |
1159 | break; | |
1160 | case 0xf004: /* fcmp/eq Rm,Rn */ | |
1161 | gen_helper_fcmp_eq_FT(fp0, fp1); | |
1162 | return; | |
1163 | case 0xf005: /* fcmp/gt Rm,Rn */ | |
1164 | gen_helper_fcmp_gt_FT(fp0, fp1); | |
1165 | return; | |
1166 | } | |
cc4ba6a9 | 1167 | gen_store_fpr32(fp0, FREG(B11_8)); |
a7812ae4 PB |
1168 | tcg_temp_free_i32(fp0); |
1169 | tcg_temp_free_i32(fp1); | |
cc4ba6a9 | 1170 | } |
ea6cf6be TS |
1171 | } |
1172 | return; | |
fdf9b3e8 FB |
1173 | } |
1174 | ||
1175 | switch (ctx->opcode & 0xff00) { | |
1176 | case 0xc900: /* and #imm,R0 */ | |
7efbe241 | 1177 | tcg_gen_andi_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1178 | return; |
24988dc2 | 1179 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1180 | { |
1181 | TCGv addr, val; | |
a7812ae4 | 1182 | addr = tcg_temp_new(); |
c55497ec | 1183 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
a7812ae4 | 1184 | val = tcg_temp_new(); |
c55497ec AJ |
1185 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1186 | tcg_gen_andi_i32(val, val, B7_0); | |
1187 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1188 | tcg_temp_free(val); | |
1189 | tcg_temp_free(addr); | |
1190 | } | |
fdf9b3e8 FB |
1191 | return; |
1192 | case 0x8b00: /* bf label */ | |
1193 | CHECK_NOT_DELAY_SLOT | |
1194 | gen_conditional_jump(ctx, ctx->pc + 2, | |
1195 | ctx->pc + 4 + B7_0s * 2); | |
823029f9 | 1196 | ctx->bstate = BS_BRANCH; |
fdf9b3e8 FB |
1197 | return; |
1198 | case 0x8f00: /* bf/s label */ | |
1199 | CHECK_NOT_DELAY_SLOT | |
1000822b | 1200 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0); |
fdf9b3e8 FB |
1201 | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1202 | return; | |
1203 | case 0x8900: /* bt label */ | |
1204 | CHECK_NOT_DELAY_SLOT | |
1205 | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, | |
1206 | ctx->pc + 2); | |
823029f9 | 1207 | ctx->bstate = BS_BRANCH; |
fdf9b3e8 FB |
1208 | return; |
1209 | case 0x8d00: /* bt/s label */ | |
1210 | CHECK_NOT_DELAY_SLOT | |
1000822b | 1211 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1); |
fdf9b3e8 FB |
1212 | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1213 | return; | |
1214 | case 0x8800: /* cmp/eq #imm,R0 */ | |
7efbe241 | 1215 | gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s); |
fdf9b3e8 FB |
1216 | return; |
1217 | case 0xc400: /* mov.b @(disp,GBR),R0 */ | |
c55497ec | 1218 | { |
a7812ae4 | 1219 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1220 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1221 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); | |
1222 | tcg_temp_free(addr); | |
1223 | } | |
fdf9b3e8 FB |
1224 | return; |
1225 | case 0xc500: /* mov.w @(disp,GBR),R0 */ | |
c55497ec | 1226 | { |
a7812ae4 | 1227 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1228 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
1229 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); | |
1230 | tcg_temp_free(addr); | |
1231 | } | |
fdf9b3e8 FB |
1232 | return; |
1233 | case 0xc600: /* mov.l @(disp,GBR),R0 */ | |
c55497ec | 1234 | { |
a7812ae4 | 1235 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1236 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
1237 | tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx); | |
1238 | tcg_temp_free(addr); | |
1239 | } | |
fdf9b3e8 FB |
1240 | return; |
1241 | case 0xc000: /* mov.b R0,@(disp,GBR) */ | |
c55497ec | 1242 | { |
a7812ae4 | 1243 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1244 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1245 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); | |
1246 | tcg_temp_free(addr); | |
1247 | } | |
fdf9b3e8 FB |
1248 | return; |
1249 | case 0xc100: /* mov.w R0,@(disp,GBR) */ | |
c55497ec | 1250 | { |
a7812ae4 | 1251 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1252 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
1253 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); | |
1254 | tcg_temp_free(addr); | |
1255 | } | |
fdf9b3e8 FB |
1256 | return; |
1257 | case 0xc200: /* mov.l R0,@(disp,GBR) */ | |
c55497ec | 1258 | { |
a7812ae4 | 1259 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1260 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
1261 | tcg_gen_qemu_st32(REG(0), addr, ctx->memidx); | |
1262 | tcg_temp_free(addr); | |
1263 | } | |
fdf9b3e8 FB |
1264 | return; |
1265 | case 0x8000: /* mov.b R0,@(disp,Rn) */ | |
c55497ec | 1266 | { |
a7812ae4 | 1267 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1268 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1269 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx); | |
1270 | tcg_temp_free(addr); | |
1271 | } | |
fdf9b3e8 FB |
1272 | return; |
1273 | case 0x8100: /* mov.w R0,@(disp,Rn) */ | |
c55497ec | 1274 | { |
a7812ae4 | 1275 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1276 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
1277 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx); | |
1278 | tcg_temp_free(addr); | |
1279 | } | |
fdf9b3e8 FB |
1280 | return; |
1281 | case 0x8400: /* mov.b @(disp,Rn),R0 */ | |
c55497ec | 1282 | { |
a7812ae4 | 1283 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1284 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1285 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx); | |
1286 | tcg_temp_free(addr); | |
1287 | } | |
fdf9b3e8 FB |
1288 | return; |
1289 | case 0x8500: /* mov.w @(disp,Rn),R0 */ | |
c55497ec | 1290 | { |
a7812ae4 | 1291 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1292 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
1293 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx); | |
1294 | tcg_temp_free(addr); | |
1295 | } | |
fdf9b3e8 FB |
1296 | return; |
1297 | case 0xc700: /* mova @(disp,PC),R0 */ | |
7efbe241 | 1298 | tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
fdf9b3e8 FB |
1299 | return; |
1300 | case 0xcb00: /* or #imm,R0 */ | |
7efbe241 | 1301 | tcg_gen_ori_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1302 | return; |
24988dc2 | 1303 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1304 | { |
1305 | TCGv addr, val; | |
a7812ae4 | 1306 | addr = tcg_temp_new(); |
c55497ec | 1307 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
a7812ae4 | 1308 | val = tcg_temp_new(); |
c55497ec AJ |
1309 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1310 | tcg_gen_ori_i32(val, val, B7_0); | |
1311 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1312 | tcg_temp_free(val); | |
1313 | tcg_temp_free(addr); | |
1314 | } | |
fdf9b3e8 FB |
1315 | return; |
1316 | case 0xc300: /* trapa #imm */ | |
c55497ec AJ |
1317 | { |
1318 | TCGv imm; | |
1319 | CHECK_NOT_DELAY_SLOT | |
1320 | tcg_gen_movi_i32(cpu_pc, ctx->pc); | |
1321 | imm = tcg_const_i32(B7_0); | |
a7812ae4 | 1322 | gen_helper_trapa(imm); |
c55497ec AJ |
1323 | tcg_temp_free(imm); |
1324 | ctx->bstate = BS_BRANCH; | |
1325 | } | |
fdf9b3e8 FB |
1326 | return; |
1327 | case 0xc800: /* tst #imm,R0 */ | |
c55497ec | 1328 | { |
a7812ae4 | 1329 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1330 | tcg_gen_andi_i32(val, REG(0), B7_0); |
1331 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1332 | tcg_temp_free(val); | |
1333 | } | |
fdf9b3e8 | 1334 | return; |
24988dc2 | 1335 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
c55497ec | 1336 | { |
a7812ae4 | 1337 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1338 | tcg_gen_add_i32(val, REG(0), cpu_gbr); |
1339 | tcg_gen_qemu_ld8u(val, val, ctx->memidx); | |
1340 | tcg_gen_andi_i32(val, val, B7_0); | |
1341 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1342 | tcg_temp_free(val); | |
1343 | } | |
fdf9b3e8 FB |
1344 | return; |
1345 | case 0xca00: /* xor #imm,R0 */ | |
7efbe241 | 1346 | tcg_gen_xori_i32(REG(0), REG(0), B7_0); |
fdf9b3e8 | 1347 | return; |
24988dc2 | 1348 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
c55497ec AJ |
1349 | { |
1350 | TCGv addr, val; | |
a7812ae4 | 1351 | addr = tcg_temp_new(); |
c55497ec | 1352 | tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
a7812ae4 | 1353 | val = tcg_temp_new(); |
c55497ec AJ |
1354 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1355 | tcg_gen_xori_i32(val, val, B7_0); | |
1356 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1357 | tcg_temp_free(val); | |
1358 | tcg_temp_free(addr); | |
1359 | } | |
fdf9b3e8 FB |
1360 | return; |
1361 | } | |
1362 | ||
1363 | switch (ctx->opcode & 0xf08f) { | |
1364 | case 0x408e: /* ldc Rm,Rn_BANK */ | |
fe25591e | 1365 | CHECK_PRIVILEGED |
7efbe241 | 1366 | tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8)); |
fdf9b3e8 FB |
1367 | return; |
1368 | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ | |
fe25591e | 1369 | CHECK_PRIVILEGED |
7efbe241 AJ |
1370 | tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx); |
1371 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
fdf9b3e8 FB |
1372 | return; |
1373 | case 0x0082: /* stc Rm_BANK,Rn */ | |
fe25591e | 1374 | CHECK_PRIVILEGED |
7efbe241 | 1375 | tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4)); |
fdf9b3e8 FB |
1376 | return; |
1377 | case 0x4083: /* stc.l Rm_BANK,@-Rn */ | |
fe25591e | 1378 | CHECK_PRIVILEGED |
c55497ec | 1379 | { |
a7812ae4 | 1380 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1381 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
1382 | tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); | |
1383 | tcg_temp_free(addr); | |
1384 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1385 | } | |
fdf9b3e8 FB |
1386 | return; |
1387 | } | |
1388 | ||
1389 | switch (ctx->opcode & 0xf0ff) { | |
1390 | case 0x0023: /* braf Rn */ | |
7efbe241 AJ |
1391 | CHECK_NOT_DELAY_SLOT |
1392 | tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4); | |
fdf9b3e8 FB |
1393 | ctx->flags |= DELAY_SLOT; |
1394 | ctx->delayed_pc = (uint32_t) - 1; | |
1395 | return; | |
1396 | case 0x0003: /* bsrf Rn */ | |
7efbe241 | 1397 | CHECK_NOT_DELAY_SLOT |
1000822b | 1398 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
7efbe241 | 1399 | tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); |
fdf9b3e8 FB |
1400 | ctx->flags |= DELAY_SLOT; |
1401 | ctx->delayed_pc = (uint32_t) - 1; | |
1402 | return; | |
1403 | case 0x4015: /* cmp/pl Rn */ | |
7efbe241 | 1404 | gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0); |
fdf9b3e8 FB |
1405 | return; |
1406 | case 0x4011: /* cmp/pz Rn */ | |
7efbe241 | 1407 | gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0); |
fdf9b3e8 FB |
1408 | return; |
1409 | case 0x4010: /* dt Rn */ | |
7efbe241 AJ |
1410 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); |
1411 | gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0); | |
fdf9b3e8 FB |
1412 | return; |
1413 | case 0x402b: /* jmp @Rn */ | |
7efbe241 AJ |
1414 | CHECK_NOT_DELAY_SLOT |
1415 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); | |
fdf9b3e8 FB |
1416 | ctx->flags |= DELAY_SLOT; |
1417 | ctx->delayed_pc = (uint32_t) - 1; | |
1418 | return; | |
1419 | case 0x400b: /* jsr @Rn */ | |
7efbe241 | 1420 | CHECK_NOT_DELAY_SLOT |
1000822b | 1421 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); |
7efbe241 | 1422 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
fdf9b3e8 FB |
1423 | ctx->flags |= DELAY_SLOT; |
1424 | ctx->delayed_pc = (uint32_t) - 1; | |
1425 | return; | |
fe25591e AJ |
1426 | case 0x400e: /* ldc Rm,SR */ |
1427 | CHECK_PRIVILEGED | |
7efbe241 | 1428 | tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3); |
390af821 AJ |
1429 | ctx->bstate = BS_STOP; |
1430 | return; | |
fe25591e AJ |
1431 | case 0x4007: /* ldc.l @Rm+,SR */ |
1432 | CHECK_PRIVILEGED | |
c55497ec | 1433 | { |
a7812ae4 | 1434 | TCGv val = tcg_temp_new(); |
c55497ec AJ |
1435 | tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx); |
1436 | tcg_gen_andi_i32(cpu_sr, val, 0x700083f3); | |
1437 | tcg_temp_free(val); | |
1438 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
1439 | ctx->bstate = BS_STOP; | |
1440 | } | |
390af821 | 1441 | return; |
fe25591e AJ |
1442 | case 0x0002: /* stc SR,Rn */ |
1443 | CHECK_PRIVILEGED | |
7efbe241 | 1444 | tcg_gen_mov_i32(REG(B11_8), cpu_sr); |
390af821 | 1445 | return; |
fe25591e AJ |
1446 | case 0x4003: /* stc SR,@-Rn */ |
1447 | CHECK_PRIVILEGED | |
c55497ec | 1448 | { |
a7812ae4 | 1449 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1450 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
1451 | tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); | |
1452 | tcg_temp_free(addr); | |
1453 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1454 | } | |
390af821 | 1455 | return; |
fe25591e | 1456 | #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ |
fdf9b3e8 | 1457 | case ldnum: \ |
fe25591e | 1458 | prechk \ |
7efbe241 | 1459 | tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ |
fdf9b3e8 FB |
1460 | return; \ |
1461 | case ldpnum: \ | |
fe25591e | 1462 | prechk \ |
7efbe241 AJ |
1463 | tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ |
1464 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ | |
fdf9b3e8 FB |
1465 | return; \ |
1466 | case stnum: \ | |
fe25591e | 1467 | prechk \ |
7efbe241 | 1468 | tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ |
fdf9b3e8 FB |
1469 | return; \ |
1470 | case stpnum: \ | |
fe25591e | 1471 | prechk \ |
c55497ec | 1472 | { \ |
a7812ae4 | 1473 | TCGv addr = tcg_temp_new(); \ |
c55497ec AJ |
1474 | tcg_gen_subi_i32(addr, REG(B11_8), 4); \ |
1475 | tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ | |
1476 | tcg_temp_free(addr); \ | |
1477 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \ | |
86e0abc7 | 1478 | } \ |
fdf9b3e8 | 1479 | return; |
fe25591e AJ |
1480 | LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) |
1481 | LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) | |
1482 | LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) | |
1483 | LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) | |
1484 | LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) | |
1485 | LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) | |
1486 | LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) | |
1487 | LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) | |
1488 | LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {}) | |
390af821 | 1489 | case 0x406a: /* lds Rm,FPSCR */ |
a7812ae4 | 1490 | gen_helper_ld_fpscr(REG(B11_8)); |
390af821 AJ |
1491 | ctx->bstate = BS_STOP; |
1492 | return; | |
1493 | case 0x4066: /* lds.l @Rm+,FPSCR */ | |
c55497ec | 1494 | { |
a7812ae4 | 1495 | TCGv addr = tcg_temp_new(); |
c55497ec AJ |
1496 | tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx); |
1497 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
a7812ae4 | 1498 | gen_helper_ld_fpscr(addr); |
c55497ec AJ |
1499 | tcg_temp_free(addr); |
1500 | ctx->bstate = BS_STOP; | |
1501 | } | |
390af821 AJ |
1502 | return; |
1503 | case 0x006a: /* sts FPSCR,Rn */ | |
c55497ec | 1504 | tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff); |
390af821 AJ |
1505 | return; |
1506 | case 0x4062: /* sts FPSCR,@-Rn */ | |
c55497ec AJ |
1507 | { |
1508 | TCGv addr, val; | |
a7812ae4 | 1509 | val = tcg_temp_new(); |
c55497ec | 1510 | tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff); |
a7812ae4 | 1511 | addr = tcg_temp_new(); |
c55497ec AJ |
1512 | tcg_gen_subi_i32(addr, REG(B11_8), 4); |
1513 | tcg_gen_qemu_st32(val, addr, ctx->memidx); | |
1514 | tcg_temp_free(addr); | |
1515 | tcg_temp_free(val); | |
1516 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); | |
1517 | } | |
390af821 | 1518 | return; |
fdf9b3e8 | 1519 | case 0x00c3: /* movca.l R0,@Rm */ |
7efbe241 | 1520 | tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx); |
fdf9b3e8 | 1521 | return; |
7526aa2d AJ |
1522 | case 0x40a9: |
1523 | /* MOVUA.L @Rm,R0 (Rm) -> R0 | |
1524 | Load non-boundary-aligned data */ | |
1525 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx); | |
1526 | return; | |
1527 | case 0x40e9: | |
1528 | /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm | |
1529 | Load non-boundary-aligned data */ | |
1530 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx); | |
1531 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); | |
1532 | return; | |
fdf9b3e8 | 1533 | case 0x0029: /* movt Rn */ |
7efbe241 | 1534 | tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); |
fdf9b3e8 FB |
1535 | return; |
1536 | case 0x0093: /* ocbi @Rn */ | |
c55497ec | 1537 | { |
a7812ae4 | 1538 | TCGv dummy = tcg_temp_new(); |
c55497ec AJ |
1539 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1540 | tcg_temp_free(dummy); | |
1541 | } | |
fdf9b3e8 | 1542 | return; |
24988dc2 | 1543 | case 0x00a3: /* ocbp @Rn */ |
c55497ec | 1544 | { |
a7812ae4 | 1545 | TCGv dummy = tcg_temp_new(); |
c55497ec AJ |
1546 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1547 | tcg_temp_free(dummy); | |
1548 | } | |
fdf9b3e8 FB |
1549 | return; |
1550 | case 0x00b3: /* ocbwb @Rn */ | |
c55497ec | 1551 | { |
a7812ae4 | 1552 | TCGv dummy = tcg_temp_new(); |
c55497ec AJ |
1553 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1554 | tcg_temp_free(dummy); | |
1555 | } | |
fdf9b3e8 FB |
1556 | return; |
1557 | case 0x0083: /* pref @Rn */ | |
1558 | return; | |
1559 | case 0x4024: /* rotcl Rn */ | |
c55497ec | 1560 | { |
a7812ae4 | 1561 | TCGv tmp = tcg_temp_new(); |
c55497ec AJ |
1562 | tcg_gen_mov_i32(tmp, cpu_sr); |
1563 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); | |
1564 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
1565 | gen_copy_bit_i32(REG(B11_8), 0, tmp, 0); | |
1566 | tcg_temp_free(tmp); | |
1567 | } | |
fdf9b3e8 FB |
1568 | return; |
1569 | case 0x4025: /* rotcr Rn */ | |
c55497ec | 1570 | { |
a7812ae4 | 1571 | TCGv tmp = tcg_temp_new(); |
c55497ec AJ |
1572 | tcg_gen_mov_i32(tmp, cpu_sr); |
1573 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); | |
1574 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
1575 | gen_copy_bit_i32(REG(B11_8), 31, tmp, 0); | |
1576 | tcg_temp_free(tmp); | |
1577 | } | |
fdf9b3e8 FB |
1578 | return; |
1579 | case 0x4004: /* rotl Rn */ | |
7efbe241 AJ |
1580 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1581 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
1582 | gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0); | |
fdf9b3e8 FB |
1583 | return; |
1584 | case 0x4005: /* rotr Rn */ | |
7efbe241 AJ |
1585 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1586 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
1587 | gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0); | |
fdf9b3e8 FB |
1588 | return; |
1589 | case 0x4000: /* shll Rn */ | |
1590 | case 0x4020: /* shal Rn */ | |
7efbe241 AJ |
1591 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1592 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1593 | return; |
1594 | case 0x4021: /* shar Rn */ | |
7efbe241 AJ |
1595 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1596 | tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1597 | return; |
1598 | case 0x4001: /* shlr Rn */ | |
7efbe241 AJ |
1599 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1600 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); | |
fdf9b3e8 FB |
1601 | return; |
1602 | case 0x4008: /* shll2 Rn */ | |
7efbe241 | 1603 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2); |
fdf9b3e8 FB |
1604 | return; |
1605 | case 0x4018: /* shll8 Rn */ | |
7efbe241 | 1606 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8); |
fdf9b3e8 FB |
1607 | return; |
1608 | case 0x4028: /* shll16 Rn */ | |
7efbe241 | 1609 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16); |
fdf9b3e8 FB |
1610 | return; |
1611 | case 0x4009: /* shlr2 Rn */ | |
7efbe241 | 1612 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2); |
fdf9b3e8 FB |
1613 | return; |
1614 | case 0x4019: /* shlr8 Rn */ | |
7efbe241 | 1615 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8); |
fdf9b3e8 FB |
1616 | return; |
1617 | case 0x4029: /* shlr16 Rn */ | |
7efbe241 | 1618 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16); |
fdf9b3e8 FB |
1619 | return; |
1620 | case 0x401b: /* tas.b @Rn */ | |
c55497ec AJ |
1621 | { |
1622 | TCGv addr, val; | |
1623 | addr = tcg_temp_local_new(TCG_TYPE_I32); | |
1624 | tcg_gen_mov_i32(addr, REG(B11_8)); | |
1625 | val = tcg_temp_local_new(TCG_TYPE_I32); | |
1626 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); | |
1627 | gen_cmp_imm(TCG_COND_EQ, val, 0); | |
1628 | tcg_gen_ori_i32(val, val, 0x80); | |
1629 | tcg_gen_qemu_st8(val, addr, ctx->memidx); | |
1630 | tcg_temp_free(val); | |
1631 | tcg_temp_free(addr); | |
1632 | } | |
fdf9b3e8 | 1633 | return; |
e67888a7 | 1634 | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
cc4ba6a9 | 1635 | { |
a7812ae4 | 1636 | TCGv fp = tcg_temp_new(); |
cc4ba6a9 AJ |
1637 | tcg_gen_mov_i32(fp, cpu_fpul); |
1638 | gen_store_fpr32(fp, FREG(B11_8)); | |
1639 | tcg_temp_free(fp); | |
1640 | } | |
eda9b09b | 1641 | return; |
e67888a7 | 1642 | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
cc4ba6a9 | 1643 | { |
a7812ae4 | 1644 | TCGv fp = tcg_temp_new(); |
cc4ba6a9 AJ |
1645 | gen_load_fpr32(fp, FREG(B11_8)); |
1646 | tcg_gen_mov_i32(cpu_fpul, fp); | |
1647 | tcg_temp_free(fp); | |
1648 | } | |
eda9b09b | 1649 | return; |
e67888a7 | 1650 | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
ea6cf6be | 1651 | if (ctx->fpscr & FPSCR_PR) { |
a7812ae4 | 1652 | TCGv_i64 fp; |
ea6cf6be TS |
1653 | if (ctx->opcode & 0x0100) |
1654 | break; /* illegal instruction */ | |
a7812ae4 PB |
1655 | fp = tcg_temp_new_i64(); |
1656 | gen_helper_float_DT(fp, cpu_fpul); | |
cc4ba6a9 | 1657 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1658 | tcg_temp_free_i64(fp); |
ea6cf6be TS |
1659 | } |
1660 | else { | |
a7812ae4 PB |
1661 | TCGv_i32 fp = tcg_temp_new_i32(); |
1662 | gen_helper_float_FT(fp, cpu_fpul); | |
cc4ba6a9 | 1663 | gen_store_fpr32(fp, FREG(B11_8)); |
a7812ae4 | 1664 | tcg_temp_free_i32(fp); |
ea6cf6be TS |
1665 | } |
1666 | return; | |
e67888a7 | 1667 | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
ea6cf6be | 1668 | if (ctx->fpscr & FPSCR_PR) { |
a7812ae4 | 1669 | TCGv_i64 fp; |
ea6cf6be TS |
1670 | if (ctx->opcode & 0x0100) |
1671 | break; /* illegal instruction */ | |
a7812ae4 | 1672 | fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1673 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 PB |
1674 | gen_helper_ftrc_DT(cpu_fpul, fp); |
1675 | tcg_temp_free_i64(fp); | |
ea6cf6be TS |
1676 | } |
1677 | else { | |
a7812ae4 | 1678 | TCGv_i32 fp = tcg_temp_new_i32(); |
cc4ba6a9 | 1679 | gen_load_fpr32(fp, FREG(B11_8)); |
a7812ae4 PB |
1680 | gen_helper_ftrc_FT(cpu_fpul, fp); |
1681 | tcg_temp_free_i32(fp); | |
ea6cf6be TS |
1682 | } |
1683 | return; | |
24988dc2 | 1684 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
7fdf924f | 1685 | { |
a7812ae4 | 1686 | TCGv_i32 fp = tcg_temp_new_i32(); |
7fdf924f | 1687 | gen_load_fpr32(fp, FREG(B11_8)); |
a7812ae4 | 1688 | gen_helper_fneg_T(fp, fp); |
7fdf924f | 1689 | gen_store_fpr32(fp, FREG(B11_8)); |
a7812ae4 | 1690 | tcg_temp_free_i32(fp); |
7fdf924f | 1691 | } |
24988dc2 AJ |
1692 | return; |
1693 | case 0xf05d: /* fabs FRn/DRn */ | |
1694 | if (ctx->fpscr & FPSCR_PR) { | |
1695 | if (ctx->opcode & 0x0100) | |
1696 | break; /* illegal instruction */ | |
a7812ae4 | 1697 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1698 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1699 | gen_helper_fabs_DT(fp, fp); |
cc4ba6a9 | 1700 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1701 | tcg_temp_free_i64(fp); |
24988dc2 | 1702 | } else { |
a7812ae4 | 1703 | TCGv_i32 fp = tcg_temp_new_i32(); |
cc4ba6a9 | 1704 | gen_load_fpr32(fp, FREG(B11_8)); |
a7812ae4 | 1705 | gen_helper_fabs_FT(fp, fp); |
cc4ba6a9 | 1706 | gen_store_fpr32(fp, FREG(B11_8)); |
a7812ae4 | 1707 | tcg_temp_free_i32(fp); |
24988dc2 AJ |
1708 | } |
1709 | return; | |
1710 | case 0xf06d: /* fsqrt FRn */ | |
1711 | if (ctx->fpscr & FPSCR_PR) { | |
1712 | if (ctx->opcode & 0x0100) | |
1713 | break; /* illegal instruction */ | |
a7812ae4 | 1714 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1715 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1716 | gen_helper_fsqrt_DT(fp, fp); |
cc4ba6a9 | 1717 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1718 | tcg_temp_free_i64(fp); |
24988dc2 | 1719 | } else { |
a7812ae4 | 1720 | TCGv_i32 fp = tcg_temp_new_i32(); |
cc4ba6a9 | 1721 | gen_load_fpr32(fp, FREG(B11_8)); |
a7812ae4 | 1722 | gen_helper_fsqrt_FT(fp, fp); |
cc4ba6a9 | 1723 | gen_store_fpr32(fp, FREG(B11_8)); |
a7812ae4 | 1724 | tcg_temp_free_i32(fp); |
24988dc2 AJ |
1725 | } |
1726 | return; | |
1727 | case 0xf07d: /* fsrra FRn */ | |
1728 | break; | |
e67888a7 | 1729 | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
ea6cf6be | 1730 | if (!(ctx->fpscr & FPSCR_PR)) { |
a7812ae4 | 1731 | TCGv_i32 val = tcg_const_i32(0); |
cc4ba6a9 | 1732 | gen_load_fpr32(val, FREG(B11_8)); |
a7812ae4 | 1733 | tcg_temp_free_i32(val); |
ea6cf6be TS |
1734 | return; |
1735 | } | |
1736 | break; | |
e67888a7 | 1737 | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
ea6cf6be | 1738 | if (!(ctx->fpscr & FPSCR_PR)) { |
a7812ae4 | 1739 | TCGv_i32 val = tcg_const_i32(0x3f800000); |
cc4ba6a9 | 1740 | gen_load_fpr32(val, FREG(B11_8)); |
a7812ae4 | 1741 | tcg_temp_free_i32(val); |
ea6cf6be TS |
1742 | return; |
1743 | } | |
1744 | break; | |
24988dc2 | 1745 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
cc4ba6a9 | 1746 | { |
a7812ae4 PB |
1747 | TCGv_i64 fp = tcg_temp_new_i64(); |
1748 | gen_helper_fcnvsd_FT_DT(fp, cpu_fpul); | |
cc4ba6a9 | 1749 | gen_store_fpr64(fp, DREG(B11_8)); |
a7812ae4 | 1750 | tcg_temp_free_i64(fp); |
cc4ba6a9 | 1751 | } |
24988dc2 AJ |
1752 | return; |
1753 | case 0xf0bd: /* fcnvds DRn,FPUL */ | |
cc4ba6a9 | 1754 | { |
a7812ae4 | 1755 | TCGv_i64 fp = tcg_temp_new_i64(); |
cc4ba6a9 | 1756 | gen_load_fpr64(fp, DREG(B11_8)); |
a7812ae4 PB |
1757 | gen_helper_fcnvds_DT_FT(cpu_fpul, fp); |
1758 | tcg_temp_free_i64(fp); | |
cc4ba6a9 | 1759 | } |
24988dc2 | 1760 | return; |
fdf9b3e8 FB |
1761 | } |
1762 | ||
1763 | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", | |
1764 | ctx->opcode, ctx->pc); | |
a7812ae4 | 1765 | gen_helper_raise_illegal_instruction(); |
823029f9 TS |
1766 | ctx->bstate = BS_EXCP; |
1767 | } | |
1768 | ||
b1d8e52e | 1769 | static void decode_opc(DisasContext * ctx) |
823029f9 TS |
1770 | { |
1771 | uint32_t old_flags = ctx->flags; | |
1772 | ||
1773 | _decode_opc(ctx); | |
1774 | ||
1775 | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { | |
1776 | if (ctx->flags & DELAY_SLOT_CLEARME) { | |
1000822b | 1777 | gen_store_flags(0); |
274a9e70 AJ |
1778 | } else { |
1779 | /* go out of the delay slot */ | |
1780 | uint32_t new_flags = ctx->flags; | |
1781 | new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
1000822b | 1782 | gen_store_flags(new_flags); |
823029f9 TS |
1783 | } |
1784 | ctx->flags = 0; | |
1785 | ctx->bstate = BS_BRANCH; | |
1786 | if (old_flags & DELAY_SLOT_CONDITIONAL) { | |
1787 | gen_delayed_conditional_jump(ctx); | |
1788 | } else if (old_flags & DELAY_SLOT) { | |
1789 | gen_jump(ctx); | |
1790 | } | |
1791 | ||
1792 | } | |
274a9e70 AJ |
1793 | |
1794 | /* go into a delay slot */ | |
1795 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) | |
1000822b | 1796 | gen_store_flags(ctx->flags); |
fdf9b3e8 FB |
1797 | } |
1798 | ||
2cfc5f17 | 1799 | static inline void |
820e00f2 TS |
1800 | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1801 | int search_pc) | |
fdf9b3e8 FB |
1802 | { |
1803 | DisasContext ctx; | |
1804 | target_ulong pc_start; | |
1805 | static uint16_t *gen_opc_end; | |
a1d1bb31 | 1806 | CPUBreakpoint *bp; |
355fb23d | 1807 | int i, ii; |
2e70f6ef PB |
1808 | int num_insns; |
1809 | int max_insns; | |
fdf9b3e8 FB |
1810 | |
1811 | pc_start = tb->pc; | |
fdf9b3e8 | 1812 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
fdf9b3e8 | 1813 | ctx.pc = pc_start; |
823029f9 TS |
1814 | ctx.flags = (uint32_t)tb->flags; |
1815 | ctx.bstate = BS_NONE; | |
fdf9b3e8 | 1816 | ctx.sr = env->sr; |
eda9b09b | 1817 | ctx.fpscr = env->fpscr; |
fdf9b3e8 | 1818 | ctx.memidx = (env->sr & SR_MD) ? 1 : 0; |
9854bc46 PB |
1819 | /* We don't know if the delayed pc came from a dynamic or static branch, |
1820 | so assume it is a dynamic branch. */ | |
823029f9 | 1821 | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
fdf9b3e8 FB |
1822 | ctx.tb = tb; |
1823 | ctx.singlestep_enabled = env->singlestep_enabled; | |
fdf9b3e8 FB |
1824 | |
1825 | #ifdef DEBUG_DISAS | |
1826 | if (loglevel & CPU_LOG_TB_CPU) { | |
1827 | fprintf(logfile, | |
1828 | "------------------------------------------------\n"); | |
1829 | cpu_dump_state(env, logfile, fprintf, 0); | |
1830 | } | |
1831 | #endif | |
1832 | ||
355fb23d | 1833 | ii = -1; |
2e70f6ef PB |
1834 | num_insns = 0; |
1835 | max_insns = tb->cflags & CF_COUNT_MASK; | |
1836 | if (max_insns == 0) | |
1837 | max_insns = CF_COUNT_MASK; | |
1838 | gen_icount_start(); | |
823029f9 | 1839 | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) { |
a1d1bb31 AL |
1840 | if (unlikely(env->breakpoints)) { |
1841 | for (bp = env->breakpoints; bp != NULL; bp = bp->next) { | |
1842 | if (ctx.pc == bp->pc) { | |
fdf9b3e8 | 1843 | /* We have hit a breakpoint - make sure PC is up-to-date */ |
3a8a44c4 | 1844 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
a7812ae4 | 1845 | gen_helper_debug(); |
823029f9 | 1846 | ctx.bstate = BS_EXCP; |
fdf9b3e8 FB |
1847 | break; |
1848 | } | |
1849 | } | |
1850 | } | |
355fb23d PB |
1851 | if (search_pc) { |
1852 | i = gen_opc_ptr - gen_opc_buf; | |
1853 | if (ii < i) { | |
1854 | ii++; | |
1855 | while (ii < i) | |
1856 | gen_opc_instr_start[ii++] = 0; | |
1857 | } | |
1858 | gen_opc_pc[ii] = ctx.pc; | |
823029f9 | 1859 | gen_opc_hflags[ii] = ctx.flags; |
355fb23d | 1860 | gen_opc_instr_start[ii] = 1; |
2e70f6ef | 1861 | gen_opc_icount[ii] = num_insns; |
355fb23d | 1862 | } |
2e70f6ef PB |
1863 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1864 | gen_io_start(); | |
fdf9b3e8 FB |
1865 | #if 0 |
1866 | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc); | |
1867 | fflush(stderr); | |
1868 | #endif | |
1869 | ctx.opcode = lduw_code(ctx.pc); | |
1870 | decode_opc(&ctx); | |
2e70f6ef | 1871 | num_insns++; |
fdf9b3e8 FB |
1872 | ctx.pc += 2; |
1873 | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
1874 | break; | |
1875 | if (env->singlestep_enabled) | |
1876 | break; | |
2e70f6ef PB |
1877 | if (num_insns >= max_insns) |
1878 | break; | |
fdf9b3e8 FB |
1879 | #ifdef SH4_SINGLE_STEP |
1880 | break; | |
1881 | #endif | |
1882 | } | |
2e70f6ef PB |
1883 | if (tb->cflags & CF_LAST_IO) |
1884 | gen_io_end(); | |
fdf9b3e8 | 1885 | if (env->singlestep_enabled) { |
bdbf22e6 | 1886 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
a7812ae4 | 1887 | gen_helper_debug(); |
823029f9 TS |
1888 | } else { |
1889 | switch (ctx.bstate) { | |
1890 | case BS_STOP: | |
1891 | /* gen_op_interrupt_restart(); */ | |
1892 | /* fall through */ | |
1893 | case BS_NONE: | |
1894 | if (ctx.flags) { | |
1000822b | 1895 | gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
823029f9 TS |
1896 | } |
1897 | gen_goto_tb(&ctx, 0, ctx.pc); | |
1898 | break; | |
1899 | case BS_EXCP: | |
1900 | /* gen_op_interrupt_restart(); */ | |
57fec1fe | 1901 | tcg_gen_exit_tb(0); |
823029f9 TS |
1902 | break; |
1903 | case BS_BRANCH: | |
1904 | default: | |
1905 | break; | |
1906 | } | |
fdf9b3e8 | 1907 | } |
823029f9 | 1908 | |
2e70f6ef | 1909 | gen_icount_end(tb, num_insns); |
fdf9b3e8 | 1910 | *gen_opc_ptr = INDEX_op_end; |
355fb23d PB |
1911 | if (search_pc) { |
1912 | i = gen_opc_ptr - gen_opc_buf; | |
1913 | ii++; | |
1914 | while (ii <= i) | |
1915 | gen_opc_instr_start[ii++] = 0; | |
355fb23d PB |
1916 | } else { |
1917 | tb->size = ctx.pc - pc_start; | |
2e70f6ef | 1918 | tb->icount = num_insns; |
355fb23d | 1919 | } |
fdf9b3e8 FB |
1920 | |
1921 | #ifdef DEBUG_DISAS | |
1922 | #ifdef SH4_DEBUG_DISAS | |
1923 | if (loglevel & CPU_LOG_TB_IN_ASM) | |
1924 | fprintf(logfile, "\n"); | |
1925 | #endif | |
1926 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
1927 | fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ | |
1928 | target_disas(logfile, pc_start, ctx.pc - pc_start, 0); | |
1929 | fprintf(logfile, "\n"); | |
1930 | } | |
fdf9b3e8 | 1931 | #endif |
fdf9b3e8 FB |
1932 | } |
1933 | ||
2cfc5f17 | 1934 | void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
fdf9b3e8 | 1935 | { |
2cfc5f17 | 1936 | gen_intermediate_code_internal(env, tb, 0); |
fdf9b3e8 FB |
1937 | } |
1938 | ||
2cfc5f17 | 1939 | void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
fdf9b3e8 | 1940 | { |
2cfc5f17 | 1941 | gen_intermediate_code_internal(env, tb, 1); |
fdf9b3e8 | 1942 | } |
d2856f1a AJ |
1943 | |
1944 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
1945 | unsigned long searched_pc, int pc_pos, void *puc) | |
1946 | { | |
1947 | env->pc = gen_opc_pc[pc_pos]; | |
1948 | env->flags = gen_opc_hflags[pc_pos]; | |
1949 | } |