]>
Commit | Line | Data |
---|---|---|
7a3f1944 FB |
1 | #ifndef CPU_SPARC_H |
2 | #define CPU_SPARC_H | |
3 | ||
af7bf89b FB |
4 | #include "config.h" |
5 | ||
6 | #if !defined(TARGET_SPARC64) | |
3cf1e035 | 7 | #define TARGET_LONG_BITS 32 |
af7bf89b | 8 | #define TARGET_FPREGS 32 |
83469015 | 9 | #define TARGET_PAGE_BITS 12 /* 4k */ |
af7bf89b FB |
10 | #else |
11 | #define TARGET_LONG_BITS 64 | |
12 | #define TARGET_FPREGS 64 | |
33b37802 | 13 | #define TARGET_PAGE_BITS 13 /* 8k */ |
af7bf89b | 14 | #endif |
3cf1e035 | 15 | |
c2764719 PB |
16 | #define CPUState struct CPUSPARCState |
17 | ||
7a3f1944 FB |
18 | #include "cpu-defs.h" |
19 | ||
7a0e1f41 FB |
20 | #include "softfloat.h" |
21 | ||
1fddef4b FB |
22 | #define TARGET_HAS_ICE 1 |
23 | ||
9042c0e2 | 24 | #if !defined(TARGET_SPARC64) |
0f8a249a | 25 | #define ELF_MACHINE EM_SPARC |
9042c0e2 | 26 | #else |
0f8a249a | 27 | #define ELF_MACHINE EM_SPARCV9 |
9042c0e2 TS |
28 | #endif |
29 | ||
7a3f1944 FB |
30 | /*#define EXCP_INTERRUPT 0x100*/ |
31 | ||
cf495bcf | 32 | /* trap definitions */ |
3475187d | 33 | #ifndef TARGET_SPARC64 |
878d3096 | 34 | #define TT_TFAULT 0x01 |
cf495bcf | 35 | #define TT_ILL_INSN 0x02 |
e8af50a3 | 36 | #define TT_PRIV_INSN 0x03 |
e80cfcfc | 37 | #define TT_NFPU_INSN 0x04 |
cf495bcf | 38 | #define TT_WIN_OVF 0x05 |
5fafdf24 | 39 | #define TT_WIN_UNF 0x06 |
d2889a3e | 40 | #define TT_UNALIGNED 0x07 |
e8af50a3 | 41 | #define TT_FP_EXCP 0x08 |
878d3096 | 42 | #define TT_DFAULT 0x09 |
e32f879d | 43 | #define TT_TOVF 0x0a |
878d3096 | 44 | #define TT_EXTINT 0x10 |
1b2e93c1 | 45 | #define TT_CODE_ACCESS 0x21 |
64a88d5d | 46 | #define TT_UNIMP_FLUSH 0x25 |
b4f0a316 | 47 | #define TT_DATA_ACCESS 0x29 |
cf495bcf | 48 | #define TT_DIV_ZERO 0x2a |
fcc72045 | 49 | #define TT_NCP_INSN 0x24 |
cf495bcf | 50 | #define TT_TRAP 0x80 |
3475187d | 51 | #else |
8194f35a | 52 | #define TT_POWER_ON_RESET 0x01 |
3475187d | 53 | #define TT_TFAULT 0x08 |
1b2e93c1 | 54 | #define TT_CODE_ACCESS 0x0a |
3475187d | 55 | #define TT_ILL_INSN 0x10 |
64a88d5d | 56 | #define TT_UNIMP_FLUSH TT_ILL_INSN |
3475187d FB |
57 | #define TT_PRIV_INSN 0x11 |
58 | #define TT_NFPU_INSN 0x20 | |
59 | #define TT_FP_EXCP 0x21 | |
e32f879d | 60 | #define TT_TOVF 0x23 |
3475187d FB |
61 | #define TT_CLRWIN 0x24 |
62 | #define TT_DIV_ZERO 0x28 | |
63 | #define TT_DFAULT 0x30 | |
b4f0a316 | 64 | #define TT_DATA_ACCESS 0x32 |
d2889a3e | 65 | #define TT_UNALIGNED 0x34 |
83469015 | 66 | #define TT_PRIV_ACT 0x37 |
3475187d | 67 | #define TT_EXTINT 0x40 |
74b9decc | 68 | #define TT_IVEC 0x60 |
e19e4efe BS |
69 | #define TT_TMISS 0x64 |
70 | #define TT_DMISS 0x68 | |
74b9decc | 71 | #define TT_DPROT 0x6c |
3475187d FB |
72 | #define TT_SPILL 0x80 |
73 | #define TT_FILL 0xc0 | |
74 | #define TT_WOTHER 0x10 | |
75 | #define TT_TRAP 0x100 | |
76 | #endif | |
7a3f1944 | 77 | |
4b8b8b76 BS |
78 | #define PSR_NEG_SHIFT 23 |
79 | #define PSR_NEG (1 << PSR_NEG_SHIFT) | |
80 | #define PSR_ZERO_SHIFT 22 | |
81 | #define PSR_ZERO (1 << PSR_ZERO_SHIFT) | |
82 | #define PSR_OVF_SHIFT 21 | |
83 | #define PSR_OVF (1 << PSR_OVF_SHIFT) | |
84 | #define PSR_CARRY_SHIFT 20 | |
85 | #define PSR_CARRY (1 << PSR_CARRY_SHIFT) | |
e8af50a3 | 86 | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) |
e80cfcfc FB |
87 | #define PSR_EF (1<<12) |
88 | #define PSR_PIL 0xf00 | |
e8af50a3 FB |
89 | #define PSR_S (1<<7) |
90 | #define PSR_PS (1<<6) | |
91 | #define PSR_ET (1<<5) | |
92 | #define PSR_CWP 0x1f | |
e8af50a3 | 93 | |
8393617c BS |
94 | #define CC_SRC (env->cc_src) |
95 | #define CC_SRC2 (env->cc_src2) | |
96 | #define CC_DST (env->cc_dst) | |
97 | #define CC_OP (env->cc_op) | |
98 | ||
99 | enum { | |
100 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ | |
101 | CC_OP_FLAGS, /* all cc are back in status register */ | |
102 | CC_OP_DIV, /* modify N, Z and V, C = 0*/ | |
103 | CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
104 | CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
105 | CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
106 | CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ | |
107 | CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
108 | CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
109 | CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
110 | CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ | |
111 | CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */ | |
112 | CC_OP_NB, | |
113 | }; | |
114 | ||
e8af50a3 FB |
115 | /* Trap base register */ |
116 | #define TBR_BASE_MASK 0xfffff000 | |
117 | ||
3475187d | 118 | #if defined(TARGET_SPARC64) |
5210977a IK |
119 | #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ |
120 | #define PS_IG (1<<11) /* v9, zero on UA2007 */ | |
121 | #define PS_MG (1<<10) /* v9, zero on UA2007 */ | |
122 | #define PS_CLE (1<<9) /* UA2007 */ | |
123 | #define PS_TLE (1<<8) /* UA2007 */ | |
6ef905f6 | 124 | #define PS_RMO (1<<7) |
5210977a IK |
125 | #define PS_RED (1<<5) /* v9, zero on UA2007 */ |
126 | #define PS_PEF (1<<4) /* enable fpu */ | |
127 | #define PS_AM (1<<3) /* address mask */ | |
3475187d FB |
128 | #define PS_PRIV (1<<2) |
129 | #define PS_IE (1<<1) | |
5210977a | 130 | #define PS_AG (1<<0) /* v9, zero on UA2007 */ |
a80dde08 FB |
131 | |
132 | #define FPRS_FEF (1<<2) | |
6f27aba6 BS |
133 | |
134 | #define HS_PRIV (1<<2) | |
3475187d FB |
135 | #endif |
136 | ||
e8af50a3 | 137 | /* Fcc */ |
ba6a9d8c BS |
138 | #define FSR_RD1 (1ULL << 31) |
139 | #define FSR_RD0 (1ULL << 30) | |
e8af50a3 FB |
140 | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) |
141 | #define FSR_RD_NEAREST 0 | |
142 | #define FSR_RD_ZERO FSR_RD0 | |
143 | #define FSR_RD_POS FSR_RD1 | |
144 | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) | |
145 | ||
ba6a9d8c BS |
146 | #define FSR_NVM (1ULL << 27) |
147 | #define FSR_OFM (1ULL << 26) | |
148 | #define FSR_UFM (1ULL << 25) | |
149 | #define FSR_DZM (1ULL << 24) | |
150 | #define FSR_NXM (1ULL << 23) | |
e8af50a3 FB |
151 | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) |
152 | ||
ba6a9d8c BS |
153 | #define FSR_NVA (1ULL << 9) |
154 | #define FSR_OFA (1ULL << 8) | |
155 | #define FSR_UFA (1ULL << 7) | |
156 | #define FSR_DZA (1ULL << 6) | |
157 | #define FSR_NXA (1ULL << 5) | |
e8af50a3 FB |
158 | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) |
159 | ||
ba6a9d8c BS |
160 | #define FSR_NVC (1ULL << 4) |
161 | #define FSR_OFC (1ULL << 3) | |
162 | #define FSR_UFC (1ULL << 2) | |
163 | #define FSR_DZC (1ULL << 1) | |
164 | #define FSR_NXC (1ULL << 0) | |
e8af50a3 FB |
165 | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) |
166 | ||
ba6a9d8c BS |
167 | #define FSR_FTT2 (1ULL << 16) |
168 | #define FSR_FTT1 (1ULL << 15) | |
169 | #define FSR_FTT0 (1ULL << 14) | |
47ad35f1 BS |
170 | //gcc warns about constant overflow for ~FSR_FTT_MASK |
171 | //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) | |
172 | #ifdef TARGET_SPARC64 | |
173 | #define FSR_FTT_NMASK 0xfffffffffffe3fffULL | |
174 | #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL | |
3a3b925d BS |
175 | #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL |
176 | #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL | |
177 | #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL | |
47ad35f1 BS |
178 | #else |
179 | #define FSR_FTT_NMASK 0xfffe3fffULL | |
180 | #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL | |
3a3b925d | 181 | #define FSR_LDFSR_OLDMASK 0x000fc000ULL |
47ad35f1 | 182 | #endif |
3a3b925d | 183 | #define FSR_LDFSR_MASK 0xcfc00fffULL |
ba6a9d8c BS |
184 | #define FSR_FTT_IEEE_EXCP (1ULL << 14) |
185 | #define FSR_FTT_UNIMPFPOP (3ULL << 14) | |
186 | #define FSR_FTT_SEQ_ERROR (4ULL << 14) | |
187 | #define FSR_FTT_INVAL_FPR (6ULL << 14) | |
e8af50a3 | 188 | |
4b8b8b76 | 189 | #define FSR_FCC1_SHIFT 11 |
ba6a9d8c | 190 | #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) |
4b8b8b76 | 191 | #define FSR_FCC0_SHIFT 10 |
ba6a9d8c | 192 | #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) |
e8af50a3 FB |
193 | |
194 | /* MMU */ | |
0f8a249a BS |
195 | #define MMU_E (1<<0) |
196 | #define MMU_NF (1<<1) | |
e8af50a3 FB |
197 | |
198 | #define PTE_ENTRYTYPE_MASK 3 | |
199 | #define PTE_ACCESS_MASK 0x1c | |
200 | #define PTE_ACCESS_SHIFT 2 | |
8d5f07fa | 201 | #define PTE_PPN_SHIFT 7 |
e8af50a3 FB |
202 | #define PTE_ADDR_MASK 0xffffff00 |
203 | ||
0f8a249a BS |
204 | #define PG_ACCESSED_BIT 5 |
205 | #define PG_MODIFIED_BIT 6 | |
e8af50a3 FB |
206 | #define PG_CACHE_BIT 7 |
207 | ||
208 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
209 | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) | |
210 | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) | |
211 | ||
1a14026e BS |
212 | /* 3 <= NWINDOWS <= 32. */ |
213 | #define MIN_NWINDOWS 3 | |
214 | #define MAX_NWINDOWS 32 | |
cf495bcf | 215 | |
6f27aba6 | 216 | #if !defined(TARGET_SPARC64) |
6ebbf390 | 217 | #define NB_MMU_MODES 2 |
6f27aba6 BS |
218 | #else |
219 | #define NB_MMU_MODES 3 | |
375ee38b BS |
220 | typedef struct trap_state { |
221 | uint64_t tpc; | |
222 | uint64_t tnpc; | |
223 | uint64_t tstate; | |
224 | uint32_t tt; | |
225 | } trap_state; | |
6f27aba6 | 226 | #endif |
6ebbf390 | 227 | |
5578ceab BS |
228 | typedef struct sparc_def_t { |
229 | const char *name; | |
230 | target_ulong iu_version; | |
231 | uint32_t fpu_version; | |
232 | uint32_t mmu_version; | |
233 | uint32_t mmu_bm; | |
234 | uint32_t mmu_ctpr_mask; | |
235 | uint32_t mmu_cxr_mask; | |
236 | uint32_t mmu_sfsr_mask; | |
237 | uint32_t mmu_trcr_mask; | |
963262de | 238 | uint32_t mxcc_version; |
5578ceab BS |
239 | uint32_t features; |
240 | uint32_t nwindows; | |
241 | uint32_t maxtl; | |
242 | } sparc_def_t; | |
243 | ||
244 | #define CPU_FEATURE_FLOAT (1 << 0) | |
245 | #define CPU_FEATURE_FLOAT128 (1 << 1) | |
246 | #define CPU_FEATURE_SWAP (1 << 2) | |
247 | #define CPU_FEATURE_MUL (1 << 3) | |
248 | #define CPU_FEATURE_DIV (1 << 4) | |
249 | #define CPU_FEATURE_FLUSH (1 << 5) | |
250 | #define CPU_FEATURE_FSQRT (1 << 6) | |
251 | #define CPU_FEATURE_FMUL (1 << 7) | |
252 | #define CPU_FEATURE_VIS1 (1 << 8) | |
253 | #define CPU_FEATURE_VIS2 (1 << 9) | |
254 | #define CPU_FEATURE_FSMULD (1 << 10) | |
255 | #define CPU_FEATURE_HYPV (1 << 11) | |
256 | #define CPU_FEATURE_CMT (1 << 12) | |
257 | #define CPU_FEATURE_GL (1 << 13) | |
258 | #ifndef TARGET_SPARC64 | |
259 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ | |
260 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ | |
261 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ | |
262 | CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) | |
263 | #else | |
264 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ | |
265 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ | |
266 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ | |
267 | CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ | |
268 | CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) | |
269 | enum { | |
270 | mmu_us_12, // Ultrasparc < III (64 entry TLB) | |
271 | mmu_us_3, // Ultrasparc III (512 entry TLB) | |
272 | mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) | |
273 | mmu_sun4v, // T1, T2 | |
274 | }; | |
275 | #endif | |
276 | ||
f707726e IK |
277 | #define TTE_VALID_BIT (1ULL << 63) |
278 | #define TTE_USED_BIT (1ULL << 41) | |
279 | #define TTE_LOCKED_BIT (1ULL << 6) | |
2a90358f | 280 | #define TTE_GLOBAL_BIT (1ULL << 0) |
f707726e IK |
281 | |
282 | #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) | |
283 | #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) | |
284 | #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) | |
2a90358f | 285 | #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) |
f707726e IK |
286 | |
287 | #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) | |
288 | #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) | |
289 | ||
6e8e7d4c IK |
290 | typedef struct SparcTLBEntry { |
291 | uint64_t tag; | |
292 | uint64_t tte; | |
293 | } SparcTLBEntry; | |
294 | ||
7a3f1944 | 295 | typedef struct CPUSPARCState { |
af7bf89b FB |
296 | target_ulong gregs[8]; /* general registers */ |
297 | target_ulong *regwptr; /* pointer to current register window */ | |
af7bf89b FB |
298 | target_ulong pc; /* program counter */ |
299 | target_ulong npc; /* next program counter */ | |
300 | target_ulong y; /* multiply/divide register */ | |
dc99a3f2 BS |
301 | |
302 | /* emulator internal flags handling */ | |
d9bdab86 | 303 | target_ulong cc_src, cc_src2; |
dc99a3f2 | 304 | target_ulong cc_dst; |
8393617c | 305 | uint32_t cc_op; |
dc99a3f2 | 306 | |
7c60cc4b FB |
307 | target_ulong t0, t1; /* temporaries live across basic blocks */ |
308 | target_ulong cond; /* conditional branch result (XXX: save it in a | |
309 | temporary register when possible) */ | |
310 | ||
cf495bcf | 311 | uint32_t psr; /* processor state register */ |
3475187d | 312 | target_ulong fsr; /* FPU state register */ |
7c60cc4b | 313 | float32 fpr[TARGET_FPREGS]; /* floating point registers */ |
cf495bcf FB |
314 | uint32_t cwp; /* index of current register window (extracted |
315 | from PSR) */ | |
5210977a | 316 | #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) |
cf495bcf | 317 | uint32_t wim; /* window invalid mask */ |
5210977a | 318 | #endif |
3475187d | 319 | target_ulong tbr; /* trap base register */ |
e8af50a3 FB |
320 | int psrs; /* supervisor mode (extracted from PSR) */ |
321 | int psrps; /* previous supervisor mode */ | |
5210977a | 322 | #if !defined(TARGET_SPARC64) |
e8af50a3 | 323 | int psret; /* enable traps */ |
5210977a | 324 | #endif |
327ac2e7 BS |
325 | uint32_t psrpil; /* interrupt blocking level */ |
326 | uint32_t pil_in; /* incoming interrupt level bitmap */ | |
e80cfcfc | 327 | int psref; /* enable fpu */ |
62724a37 | 328 | target_ulong version; |
cf495bcf | 329 | int interrupt_index; |
1a14026e | 330 | uint32_t nwindows; |
cf495bcf | 331 | /* NOTE: we allow 8 more registers to handle wrapping */ |
1a14026e | 332 | target_ulong regbase[MAX_NWINDOWS * 16 + 8]; |
d720b93d | 333 | |
a316d335 FB |
334 | CPU_COMMON |
335 | ||
e8af50a3 | 336 | /* MMU regs */ |
3475187d FB |
337 | #if defined(TARGET_SPARC64) |
338 | uint64_t lsu; | |
339 | #define DMMU_E 0x8 | |
340 | #define IMMU_E 0x4 | |
6e8e7d4c IK |
341 | //typedef struct SparcMMU |
342 | union { | |
343 | uint64_t immuregs[16]; | |
344 | struct { | |
345 | uint64_t tsb_tag_target; | |
346 | uint64_t unused_mmu_primary_context; // use DMMU | |
347 | uint64_t unused_mmu_secondary_context; // use DMMU | |
348 | uint64_t sfsr; | |
349 | uint64_t sfar; | |
350 | uint64_t tsb; | |
351 | uint64_t tag_access; | |
352 | } immu; | |
353 | }; | |
354 | union { | |
355 | uint64_t dmmuregs[16]; | |
356 | struct { | |
357 | uint64_t tsb_tag_target; | |
358 | uint64_t mmu_primary_context; | |
359 | uint64_t mmu_secondary_context; | |
360 | uint64_t sfsr; | |
361 | uint64_t sfar; | |
362 | uint64_t tsb; | |
363 | uint64_t tag_access; | |
364 | } dmmu; | |
365 | }; | |
366 | SparcTLBEntry itlb[64]; | |
367 | SparcTLBEntry dtlb[64]; | |
fb79ceb9 | 368 | uint32_t mmu_version; |
3475187d | 369 | #else |
3dd9a152 | 370 | uint32_t mmuregs[32]; |
952a328f BS |
371 | uint64_t mxccdata[4]; |
372 | uint64_t mxccregs[8]; | |
4017190e | 373 | uint64_t mmubpregs[4]; |
3ebf5aaf | 374 | uint64_t prom_addr; |
3475187d | 375 | #endif |
e8af50a3 | 376 | /* temporary float registers */ |
65ce8c2f | 377 | float64 dt0, dt1; |
1f587329 | 378 | float128 qt0, qt1; |
7a0e1f41 | 379 | float_status fp_status; |
af7bf89b | 380 | #if defined(TARGET_SPARC64) |
c19148bd BS |
381 | #define MAXTL_MAX 8 |
382 | #define MAXTL_MASK (MAXTL_MAX - 1) | |
c19148bd | 383 | trap_state ts[MAXTL_MAX]; |
0f8a249a | 384 | uint32_t xcc; /* Extended integer condition codes */ |
3475187d FB |
385 | uint32_t asi; |
386 | uint32_t pstate; | |
387 | uint32_t tl; | |
c19148bd | 388 | uint32_t maxtl; |
3475187d | 389 | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
83469015 FB |
390 | uint64_t agregs[8]; /* alternate general registers */ |
391 | uint64_t bgregs[8]; /* backup for normal global registers */ | |
392 | uint64_t igregs[8]; /* interrupt general registers */ | |
393 | uint64_t mgregs[8]; /* mmu general registers */ | |
3475187d | 394 | uint64_t fprs; |
83469015 | 395 | uint64_t tick_cmpr, stick_cmpr; |
20c9f095 | 396 | void *tick, *stick; |
709f2c1b IK |
397 | #define TICK_NPT_MASK 0x8000000000000000ULL |
398 | #define TICK_INT_DIS 0x8000000000000000ULL | |
725cb90b | 399 | uint64_t gsr; |
e9ebed4d BS |
400 | uint32_t gl; // UA2005 |
401 | /* UA 2005 hyperprivileged registers */ | |
c19148bd | 402 | uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; |
20c9f095 | 403 | void *hstick; // UA 2005 |
9d926598 | 404 | uint32_t softint; |
8fa211e8 BS |
405 | #define SOFTINT_TIMER 1 |
406 | #define SOFTINT_STIMER (1 << 16) | |
709f2c1b IK |
407 | #define SOFTINT_INTRMASK (0xFFFE) |
408 | #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) | |
3475187d | 409 | #endif |
5578ceab | 410 | sparc_def_t *def; |
7a3f1944 | 411 | } CPUSPARCState; |
64a88d5d | 412 | |
91736d37 | 413 | /* helper.c */ |
aaed909a | 414 | CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
91736d37 | 415 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
62724a37 BS |
416 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, |
417 | ...)); | |
48585ec5 BS |
418 | void cpu_lock(void); |
419 | void cpu_unlock(void); | |
420 | int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw, | |
421 | int mmu_idx, int is_softmmu); | |
0b5c1ce8 | 422 | #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault |
48585ec5 BS |
423 | target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); |
424 | void dump_mmu(CPUSPARCState *env); | |
91736d37 BS |
425 | |
426 | /* translate.c */ | |
427 | void gen_intermediate_code_init(CPUSPARCState *env); | |
428 | ||
429 | /* cpu-exec.c */ | |
430 | int cpu_sparc_exec(CPUSPARCState *s); | |
7a3f1944 | 431 | |
5210977a | 432 | #if !defined (TARGET_SPARC64) |
62724a37 | 433 | #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \ |
0f8a249a BS |
434 | (env->psref? PSR_EF : 0) | \ |
435 | (env->psrpil << 8) | \ | |
436 | (env->psrs? PSR_S : 0) | \ | |
437 | (env->psrps? PSR_PS : 0) | \ | |
438 | (env->psret? PSR_ET : 0) | env->cwp) | |
5210977a IK |
439 | #else |
440 | #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \ | |
441 | (env->psref? PSR_EF : 0) | \ | |
442 | (env->psrpil << 8) | \ | |
443 | (env->psrs? PSR_S : 0) | \ | |
444 | (env->psrps? PSR_PS : 0) | \ | |
445 | env->cwp) | |
446 | #endif | |
b4ff5987 FB |
447 | |
448 | #ifndef NO_CPU_IO_DEFS | |
4c6aa085 BS |
449 | |
450 | static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp) | |
451 | { | |
452 | if (unlikely(cwp >= env1->nwindows)) | |
453 | cwp -= env1->nwindows; | |
454 | return cwp; | |
455 | } | |
456 | ||
457 | static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp) | |
458 | { | |
459 | if (unlikely(cwp < 0)) | |
460 | cwp += env1->nwindows; | |
461 | return cwp; | |
462 | } | |
463 | #endif | |
464 | ||
91736d37 BS |
465 | static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
466 | { | |
467 | dst[0] = src[0]; | |
468 | dst[1] = src[1]; | |
469 | dst[2] = src[2]; | |
470 | dst[3] = src[3]; | |
471 | dst[4] = src[4]; | |
472 | dst[5] = src[5]; | |
473 | dst[6] = src[6]; | |
474 | dst[7] = src[7]; | |
475 | } | |
476 | ||
477 | static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp) | |
478 | { | |
479 | /* put the modified wrap registers at their proper location */ | |
480 | if (env1->cwp == env1->nwindows - 1) | |
481 | memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16); | |
482 | env1->cwp = new_cwp; | |
483 | /* put the wrap registers at their temporary location */ | |
484 | if (new_cwp == env1->nwindows - 1) | |
485 | memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase); | |
486 | env1->regwptr = env1->regbase + (new_cwp * 16); | |
487 | } | |
1a14026e | 488 | |
4c6aa085 BS |
489 | /* sun4m.c, sun4u.c */ |
490 | void cpu_check_irqs(CPUSPARCState *env); | |
1a14026e | 491 | |
4c6aa085 | 492 | static inline void PUT_PSR(CPUSPARCState *env1, target_ulong val) |
1a14026e | 493 | { |
4c6aa085 BS |
494 | env1->psr = val & PSR_ICC; |
495 | env1->psref = (val & PSR_EF)? 1 : 0; | |
496 | env1->psrpil = (val & PSR_PIL) >> 8; | |
497 | #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY)) | |
498 | cpu_check_irqs(env1); | |
b4ff5987 | 499 | #endif |
4c6aa085 BS |
500 | env1->psrs = (val & PSR_S)? 1 : 0; |
501 | env1->psrps = (val & PSR_PS)? 1 : 0; | |
5210977a | 502 | #if !defined (TARGET_SPARC64) |
4c6aa085 | 503 | env1->psret = (val & PSR_ET)? 1 : 0; |
5210977a | 504 | #endif |
4c6aa085 BS |
505 | cpu_set_cwp(env1, val & PSR_CWP); |
506 | env1->cc_op = CC_OP_FLAGS; | |
507 | } | |
b4ff5987 | 508 | |
3475187d | 509 | #ifdef TARGET_SPARC64 |
17d996e1 | 510 | #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) |
0f8a249a | 511 | #define PUT_CCR(env, val) do { int _tmp = val; \ |
77f193da | 512 | env->xcc = (_tmp >> 4) << 20; \ |
0f8a249a | 513 | env->psr = (_tmp & 0xf) << 20; \ |
8393617c | 514 | CC_OP = CC_OP_FLAGS; \ |
3475187d | 515 | } while (0) |
1a14026e BS |
516 | #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp) |
517 | ||
0bbd4a0d | 518 | #ifndef NO_CPU_IO_DEFS |
1a14026e BS |
519 | static inline void PUT_CWP64(CPUSPARCState *env1, int cwp) |
520 | { | |
521 | if (unlikely(cwp >= env1->nwindows || cwp < 0)) | |
522 | cwp = 0; | |
523 | cpu_set_cwp(env1, env1->nwindows - 1 - cwp); | |
524 | } | |
0bbd4a0d | 525 | #endif |
3475187d FB |
526 | #endif |
527 | ||
91736d37 | 528 | /* cpu-exec.c */ |
c227f099 | 529 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
e18231a3 | 530 | int is_asi, int size); |
f0d5e471 | 531 | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
7a3f1944 | 532 | |
9467d44c TS |
533 | #define cpu_init cpu_sparc_init |
534 | #define cpu_exec cpu_sparc_exec | |
535 | #define cpu_gen_code cpu_sparc_gen_code | |
536 | #define cpu_signal_handler cpu_sparc_signal_handler | |
c732abe2 | 537 | #define cpu_list sparc_cpu_list |
9467d44c | 538 | |
0b8f1b10 | 539 | #define CPU_SAVE_VERSION 5 |
b3c7724c | 540 | |
6ebbf390 | 541 | /* MMU modes definitions */ |
6f27aba6 BS |
542 | #define MMU_MODE0_SUFFIX _user |
543 | #define MMU_MODE1_SUFFIX _kernel | |
544 | #ifdef TARGET_SPARC64 | |
545 | #define MMU_MODE2_SUFFIX _hypv | |
546 | #endif | |
9e31b9e2 BS |
547 | #define MMU_USER_IDX 0 |
548 | #define MMU_KERNEL_IDX 1 | |
549 | #define MMU_HYPV_IDX 2 | |
550 | ||
22548760 | 551 | static inline int cpu_mmu_index(CPUState *env1) |
6ebbf390 | 552 | { |
6f27aba6 | 553 | #if defined(CONFIG_USER_ONLY) |
9e31b9e2 | 554 | return MMU_USER_IDX; |
6f27aba6 | 555 | #elif !defined(TARGET_SPARC64) |
22548760 | 556 | return env1->psrs; |
6f27aba6 | 557 | #else |
22548760 | 558 | if (!env1->psrs) |
9e31b9e2 | 559 | return MMU_USER_IDX; |
22548760 | 560 | else if ((env1->hpstate & HS_PRIV) == 0) |
9e31b9e2 | 561 | return MMU_KERNEL_IDX; |
6f27aba6 | 562 | else |
9e31b9e2 | 563 | return MMU_HYPV_IDX; |
6f27aba6 BS |
564 | #endif |
565 | } | |
566 | ||
2df6c2d0 IK |
567 | static inline int cpu_interrupts_enabled(CPUState *env1) |
568 | { | |
569 | #if !defined (TARGET_SPARC64) | |
570 | if (env1->psret != 0) | |
571 | return 1; | |
572 | #else | |
573 | if (env1->pstate & PS_IE) | |
574 | return 1; | |
575 | #endif | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
22548760 | 580 | static inline int cpu_fpu_enabled(CPUState *env1) |
6f27aba6 BS |
581 | { |
582 | #if defined(CONFIG_USER_ONLY) | |
583 | return 1; | |
584 | #elif !defined(TARGET_SPARC64) | |
22548760 | 585 | return env1->psref; |
6f27aba6 | 586 | #else |
22548760 | 587 | return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0); |
6f27aba6 | 588 | #endif |
6ebbf390 JM |
589 | } |
590 | ||
6e68e076 PB |
591 | #if defined(CONFIG_USER_ONLY) |
592 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) | |
593 | { | |
f8ed7070 | 594 | if (newsp) |
6e68e076 PB |
595 | env->regwptr[22] = newsp; |
596 | env->regwptr[0] = 0; | |
597 | /* FIXME: Do we also need to clear CF? */ | |
598 | /* XXXXX */ | |
599 | printf ("HELPME: %s:%d\n", __FILE__, __LINE__); | |
600 | } | |
601 | #endif | |
602 | ||
7a3f1944 | 603 | #include "cpu-all.h" |
622ed360 | 604 | #include "exec-all.h" |
7a3f1944 | 605 | |
f4b1a842 BS |
606 | #ifdef TARGET_SPARC64 |
607 | /* sun4u.c */ | |
608 | void cpu_tick_set_count(void *opaque, uint64_t count); | |
609 | uint64_t cpu_tick_get_count(void *opaque); | |
610 | void cpu_tick_set_limit(void *opaque, uint64_t limit); | |
8194f35a | 611 | trap_state* cpu_tsptr(CPUState* env); |
f4b1a842 BS |
612 | #endif |
613 | ||
622ed360 AL |
614 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
615 | { | |
616 | env->pc = tb->pc; | |
617 | env->npc = tb->cs_base; | |
618 | } | |
619 | ||
6b917547 AL |
620 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
621 | target_ulong *cs_base, int *flags) | |
622 | { | |
623 | *pc = env->pc; | |
624 | *cs_base = env->npc; | |
625 | #ifdef TARGET_SPARC64 | |
626 | // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled | |
627 | *flags = ((env->pstate & PS_AM) << 2) | |
628 | | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) | |
629 | | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); | |
630 | #else | |
631 | // FPU enable . Supervisor | |
632 | *flags = (env->psref << 4) | env->psrs; | |
633 | #endif | |
634 | } | |
635 | ||
7a3f1944 | 636 | #endif |