[qemu.git] / target-sparc / fop_helper.c

/*
 * FPU op helpers
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "helper.h"

#define QT0 (env->qt0)
#define QT1 (env->qt1)

static void check_ieee_exceptions(CPUState *env)
{
    target_ulong status;

    status = get_float_exception_flags(&env->fp_status);
    if (status) {
        /* Copy IEEE 754 flags into FSR */
        if (status & float_flag_invalid) {
            env->fsr |= FSR_NVC;
        }
        if (status & float_flag_overflow) {
            env->fsr |= FSR_OFC;
        }
        if (status & float_flag_underflow) {
            env->fsr |= FSR_UFC;
        }
        if (status & float_flag_divbyzero) {
            env->fsr |= FSR_DZC;
        }
        if (status & float_flag_inexact) {
            env->fsr |= FSR_NXC;
        }

        if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
            /* Unmasked exception, generate a trap */
            env->fsr |= FSR_FTT_IEEE_EXCP;
            helper_raise_exception(env, TT_FP_EXCP);
        } else {
            /* Accumulate exceptions */
            env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
        }
    }
}

static inline void clear_float_exceptions(CPUState *env)
{
    set_float_exception_flags(0, &env->fp_status);
}

#define F_HELPER(name, p) void helper_f##name##p(CPUState *env)

#define F_BINOP(name)                                           \
    float32 helper_f ## name ## s (CPUState *env, float32 src1, \
                                   float32 src2)                \
    {                                                           \
        float32 ret;                                            \
        clear_float_exceptions(env);                            \
        ret = float32_ ## name (src1, src2, &env->fp_status);   \
        check_ieee_exceptions(env);                             \
        return ret;                                             \
    }                                                           \
    float64 helper_f ## name ## d (CPUState * env, float64 src1,\
                                   float64 src2)                \
    {                                                           \
        float64 ret;                                            \
        clear_float_exceptions(env);                            \
        ret = float64_ ## name (src1, src2, &env->fp_status);   \
        check_ieee_exceptions(env);                             \
        return ret;                                             \
    }                                                           \
    F_HELPER(name, q)                                           \
    {                                                           \
        clear_float_exceptions(env);                            \
        QT0 = float128_ ## name (QT0, QT1, &env->fp_status);    \
        check_ieee_exceptions(env);                             \
    }

F_BINOP(add);
F_BINOP(sub);
F_BINOP(mul);
F_BINOP(div);
#undef F_BINOP

float64 helper_fsmuld(CPUState *env, float32 src1, float32 src2)
{
    float64 ret;
    clear_float_exceptions(env);
    ret = float64_mul(float32_to_float64(src1, &env->fp_status),
                      float32_to_float64(src2, &env->fp_status),
                      &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

void helper_fdmulq(CPUState *env, float64 src1, float64 src2)
{
    clear_float_exceptions(env);
    QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
                       float64_to_float128(src2, &env->fp_status),
                       &env->fp_status);
    check_ieee_exceptions(env);
}

float32 helper_fnegs(float32 src)
{
    return float32_chs(src);
}

#ifdef TARGET_SPARC64
float64 helper_fnegd(float64 src)
{
    return float64_chs(src);
}

F_HELPER(neg, q)
{
    QT0 = float128_chs(QT1);
}
#endif

/* Integer to float conversion.  */
float32 helper_fitos(CPUState *env, int32_t src)
{
    /* Inexact error possible converting int to float.  */
    float32 ret;
    clear_float_exceptions(env);
    ret = int32_to_float32(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

float64 helper_fitod(CPUState *env, int32_t src)
{
    /* No possible exceptions converting int to double.  */
    return int32_to_float64(src, &env->fp_status);
}

void helper_fitoq(CPUState *env, int32_t src)
{
    /* No possible exceptions converting int to long double.  */
    QT0 = int32_to_float128(src, &env->fp_status);
}

#ifdef TARGET_SPARC64
float32 helper_fxtos(CPUState *env, int64_t src)
{
    float32 ret;
    clear_float_exceptions(env);
    ret = int64_to_float32(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

float64 helper_fxtod(CPUState *env, int64_t src)
{
    float64 ret;
    clear_float_exceptions(env);
    ret = int64_to_float64(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

void helper_fxtoq(CPUState *env, int64_t src)
{
    /* No possible exceptions converting long long to long double.  */
    QT0 = int64_to_float128(src, &env->fp_status);
}
#endif
#undef F_HELPER

/* floating point conversion */
float32 helper_fdtos(CPUState *env, float64 src)
{
    float32 ret;
    clear_float_exceptions(env);
    ret = float64_to_float32(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

float64 helper_fstod(CPUState *env, float32 src)
{
    float64 ret;
    clear_float_exceptions(env);
    ret = float32_to_float64(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

float32 helper_fqtos(CPUState *env)
{
    float32 ret;
    clear_float_exceptions(env);
    ret = float128_to_float32(QT1, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

void helper_fstoq(CPUState *env, float32 src)
{
    clear_float_exceptions(env);
    QT0 = float32_to_float128(src, &env->fp_status);
    check_ieee_exceptions(env);
}

float64 helper_fqtod(CPUState *env)
{
    float64 ret;
    clear_float_exceptions(env);
    ret = float128_to_float64(QT1, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

void helper_fdtoq(CPUState *env, float64 src)
{
    clear_float_exceptions(env);
    QT0 = float64_to_float128(src, &env->fp_status);
    check_ieee_exceptions(env);
}

/* Float to integer conversion.  */
int32_t helper_fstoi(CPUState *env, float32 src)
{
    int32_t ret;
    clear_float_exceptions(env);
    ret = float32_to_int32_round_to_zero(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

int32_t helper_fdtoi(CPUState *env, float64 src)
{
    int32_t ret;
    clear_float_exceptions(env);
    ret = float64_to_int32_round_to_zero(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

int32_t helper_fqtoi(CPUState *env)
{
    int32_t ret;
    clear_float_exceptions(env);
    ret = float128_to_int32_round_to_zero(QT1, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

#ifdef TARGET_SPARC64
int64_t helper_fstox(CPUState *env, float32 src)
{
    int64_t ret;
    clear_float_exceptions(env);
    ret = float32_to_int64_round_to_zero(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

int64_t helper_fdtox(CPUState *env, float64 src)
{
    int64_t ret;
    clear_float_exceptions(env);
    ret = float64_to_int64_round_to_zero(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

int64_t helper_fqtox(CPUState *env)
{
    int64_t ret;
    clear_float_exceptions(env);
    ret = float128_to_int64_round_to_zero(QT1, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}
#endif

float32 helper_fabss(float32 src)
{
    return float32_abs(src);
}

#ifdef TARGET_SPARC64
float64 helper_fabsd(float64 src)
{
    return float64_abs(src);
}

void helper_fabsq(CPUState *env)
{
    QT0 = float128_abs(QT1);
}
#endif

float32 helper_fsqrts(CPUState *env, float32 src)
{
    float32 ret;
    clear_float_exceptions(env);
    ret = float32_sqrt(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

float64 helper_fsqrtd(CPUState *env, float64 src)
{
    float64 ret;
    clear_float_exceptions(env);
    ret = float64_sqrt(src, &env->fp_status);
    check_ieee_exceptions(env);
    return ret;
}

void helper_fsqrtq(CPUState *env)
{
    clear_float_exceptions(env);
    QT0 = float128_sqrt(QT1, &env->fp_status);
    check_ieee_exceptions(env);
}

#define GEN_FCMP(name, size, reg1, reg2, FS, E)                         \
    void glue(helper_, name) (CPUState *env)                            \
    {                                                                   \
        env->fsr &= FSR_FTT_NMASK;                                      \
        if (E && (glue(size, _is_any_nan)(reg1) ||                      \
                  glue(size, _is_any_nan)(reg2)) &&                     \
            (env->fsr & FSR_NVM)) {                                     \
            env->fsr |= FSR_NVC;                                        \
            env->fsr |= FSR_FTT_IEEE_EXCP;                              \
            helper_raise_exception(env, TT_FP_EXCP);                    \
        }                                                               \
        switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
        case float_relation_unordered:                                  \
            if ((env->fsr & FSR_NVM)) {                                 \
                env->fsr |= FSR_NVC;                                    \
                env->fsr |= FSR_FTT_IEEE_EXCP;                          \
                helper_raise_exception(env, TT_FP_EXCP);                \
            } else {                                                    \
                env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);             \
                env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                \
                env->fsr |= FSR_NVA;                                    \
            }                                                           \
            break;                                                      \
        case float_relation_less:                                       \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            env->fsr |= FSR_FCC0 << FS;                                 \
            break;                                                      \
        case float_relation_greater:                                    \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            env->fsr |= FSR_FCC1 << FS;                                 \
            break;                                                      \
        default:                                                        \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            break;                                                      \
        }                                                               \
    }
#define GEN_FCMP_T(name, size, FS, E)                                   \
    void glue(helper_, name)(CPUState *env, size src1, size src2)       \
    {                                                                   \
        env->fsr &= FSR_FTT_NMASK;                                      \
        if (E && (glue(size, _is_any_nan)(src1) ||                      \
                  glue(size, _is_any_nan)(src2)) &&                     \
            (env->fsr & FSR_NVM)) {                                     \
            env->fsr |= FSR_NVC;                                        \
            env->fsr |= FSR_FTT_IEEE_EXCP;                              \
            helper_raise_exception(env, TT_FP_EXCP);                    \
        }                                                               \
        switch (glue(size, _compare) (src1, src2, &env->fp_status)) {   \
        case float_relation_unordered:                                  \
            if ((env->fsr & FSR_NVM)) {                                 \
                env->fsr |= FSR_NVC;                                    \
                env->fsr |= FSR_FTT_IEEE_EXCP;                          \
                helper_raise_exception(env, TT_FP_EXCP);                \
            } else {                                                    \
                env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);             \
                env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                \
                env->fsr |= FSR_NVA;                                    \
            }                                                           \
            break;                                                      \
        case float_relation_less:                                       \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            env->fsr |= FSR_FCC0 << FS;                                 \
            break;                                                      \
        case float_relation_greater:                                    \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            env->fsr |= FSR_FCC1 << FS;                                 \
            break;                                                      \
        default:                                                        \
            env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
            break;                                                      \
        }                                                               \
    }

GEN_FCMP_T(fcmps, float32, 0, 0);
GEN_FCMP_T(fcmpd, float64, 0, 0);

GEN_FCMP_T(fcmpes, float32, 0, 1);
GEN_FCMP_T(fcmped, float64, 0, 1);

GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);

#ifdef TARGET_SPARC64
GEN_FCMP_T(fcmps_fcc1, float32, 22, 0);
GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0);
GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);

GEN_FCMP_T(fcmps_fcc2, float32, 24, 0);
GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0);
GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);

GEN_FCMP_T(fcmps_fcc3, float32, 26, 0);
GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0);
GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);

GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1);
GEN_FCMP_T(fcmped_fcc1, float64, 22, 1);
GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);

GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1);
GEN_FCMP_T(fcmped_fcc2, float64, 24, 1);
GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);

GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1);
GEN_FCMP_T(fcmped_fcc3, float64, 26, 1);
GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
#endif
#undef GEN_FCMP_T
#undef GEN_FCMP

static inline void set_fsr(CPUState *env)
{
    int rnd_mode;

    switch (env->fsr & FSR_RD_MASK) {
    case FSR_RD_NEAREST:
        rnd_mode = float_round_nearest_even;
        break;
    default:
    case FSR_RD_ZERO:
        rnd_mode = float_round_to_zero;
        break;
    case FSR_RD_POS:
        rnd_mode = float_round_up;
        break;
    case FSR_RD_NEG:
        rnd_mode = float_round_down;
        break;
    }
    set_float_rounding_mode(rnd_mode, &env->fp_status);
}

void helper_ldfsr(CPUState *env, uint32_t new_fsr)
{
    env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
    set_fsr(env);
}

#ifdef TARGET_SPARC64
void helper_ldxfsr(CPUState *env, uint64_t new_fsr)
{
    env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
    set_fsr(env);
}
#endif
Commit	Line	Data
1bccec25 BS	1	/*
	2	* FPU op helpers
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "cpu.h"
1bccec25 BS	21	#include "helper.h"
1bccec25 BS	22
1bccec25 BS	23	#define QT0 (env->qt0)
	24	#define QT1 (env->qt1)
	25
44516772 RH	26	static void check_ieee_exceptions(CPUState *env)
	27	{
	28	target_ulong status;
	29
	30	status = get_float_exception_flags(&env->fp_status);
	31	if (status) {
	32	/* Copy IEEE 754 flags into FSR */
	33	if (status & float_flag_invalid) {
	34	env->fsr \|= FSR_NVC;
	35	}
	36	if (status & float_flag_overflow) {
	37	env->fsr \|= FSR_OFC;
	38	}
	39	if (status & float_flag_underflow) {
	40	env->fsr \|= FSR_UFC;
	41	}
	42	if (status & float_flag_divbyzero) {
	43	env->fsr \|= FSR_DZC;
	44	}
	45	if (status & float_flag_inexact) {
	46	env->fsr \|= FSR_NXC;
	47	}
	48
	49	if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
	50	/* Unmasked exception, generate a trap */
	51	env->fsr \|= FSR_FTT_IEEE_EXCP;
	52	helper_raise_exception(env, TT_FP_EXCP);
	53	} else {
	54	/* Accumulate exceptions */
	55	env->fsr \|= (env->fsr & FSR_CEXC_MASK) << 5;
	56	}
	57	}
	58	}
	59
	60	static inline void clear_float_exceptions(CPUState *env)
	61	{
	62	set_float_exception_flags(0, &env->fp_status);
	63	}
	64
2e2f4ade	65	#define F_HELPER(name, p) void helper_f##name##p(CPUState *env)
1bccec25 BS	66
1bccec25 BS	67	#define F_BINOP(name) \
44516772	68	float32 helper_f ## name ## s (CPUState *env, float32 src1, \
2e2f4ade	69	float32 src2) \
1bccec25	70	{ \
44516772 RH	71	float32 ret; \
	72	clear_float_exceptions(env); \
	73	ret = float32_ ## name (src1, src2, &env->fp_status); \
	74	check_ieee_exceptions(env); \
	75	return ret; \
1bccec25	76	} \
03fb8cfc RH	77	float64 helper_f ## name ## d (CPUState * env, float64 src1,\
03fb8cfc RH	78	float64 src2) \
1bccec25	79	{ \
44516772 RH	80	float64 ret; \
	81	clear_float_exceptions(env); \
	82	ret = float64_ ## name (src1, src2, &env->fp_status); \
	83	check_ieee_exceptions(env); \
	84	return ret; \
1bccec25 BS	85	} \
	86	F_HELPER(name, q) \
	87	{ \
44516772	88	clear_float_exceptions(env); \
1bccec25	89	QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
44516772	90	check_ieee_exceptions(env); \
1bccec25 BS	91	}
	92
	93	F_BINOP(add);
	94	F_BINOP(sub);
	95	F_BINOP(mul);
	96	F_BINOP(div);
	97	#undef F_BINOP
	98
03fb8cfc	99	float64 helper_fsmuld(CPUState *env, float32 src1, float32 src2)
1bccec25	100	{
44516772 RH	101	float64 ret;
	102	clear_float_exceptions(env);
	103	ret = float64_mul(float32_to_float64(src1, &env->fp_status),
	104	float32_to_float64(src2, &env->fp_status),
	105	&env->fp_status);
	106	check_ieee_exceptions(env);
	107	return ret;
1bccec25 BS	108	}
1bccec25 BS	109
03fb8cfc	110	void helper_fdmulq(CPUState *env, float64 src1, float64 src2)
1bccec25	111	{
44516772	112	clear_float_exceptions(env);
03fb8cfc RH	113	QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
03fb8cfc RH	114	float64_to_float128(src2, &env->fp_status),
1bccec25	115	&env->fp_status);
44516772	116	check_ieee_exceptions(env);
1bccec25 BS	117	}
	118
	119	float32 helper_fnegs(float32 src)
	120	{
	121	return float32_chs(src);
	122	}
	123
	124	#ifdef TARGET_SPARC64
03fb8cfc	125	float64 helper_fnegd(float64 src)
1bccec25	126	{
03fb8cfc	127	return float64_chs(src);
1bccec25 BS	128	}
	129
	130	F_HELPER(neg, q)
	131	{
	132	QT0 = float128_chs(QT1);
	133	}
	134	#endif
	135
	136	/* Integer to float conversion. */
2e2f4ade	137	float32 helper_fitos(CPUState *env, int32_t src)
1bccec25	138	{
44516772 RH	139	/* Inexact error possible converting int to float. */
	140	float32 ret;
	141	clear_float_exceptions(env);
	142	ret = int32_to_float32(src, &env->fp_status);
	143	check_ieee_exceptions(env);
	144	return ret;
1bccec25 BS	145	}
1bccec25 BS	146
03fb8cfc	147	float64 helper_fitod(CPUState *env, int32_t src)
1bccec25	148	{
44516772	149	/* No possible exceptions converting int to double. */
03fb8cfc	150	return int32_to_float64(src, &env->fp_status);
1bccec25 BS	151	}
1bccec25 BS	152
2e2f4ade	153	void helper_fitoq(CPUState *env, int32_t src)
1bccec25	154	{
44516772	155	/* No possible exceptions converting int to long double. */
1bccec25 BS	156	QT0 = int32_to_float128(src, &env->fp_status);
	157	}
	158
	159	#ifdef TARGET_SPARC64
03fb8cfc	160	float32 helper_fxtos(CPUState *env, int64_t src)
1bccec25	161	{
44516772 RH	162	float32 ret;
	163	clear_float_exceptions(env);
	164	ret = int64_to_float32(src, &env->fp_status);
	165	check_ieee_exceptions(env);
	166	return ret;
1bccec25 BS	167	}
1bccec25 BS	168
03fb8cfc	169	float64 helper_fxtod(CPUState *env, int64_t src)
1bccec25	170	{
44516772 RH	171	float64 ret;
	172	clear_float_exceptions(env);
	173	ret = int64_to_float64(src, &env->fp_status);
	174	check_ieee_exceptions(env);
	175	return ret;
1bccec25 BS	176	}
1bccec25 BS	177
03fb8cfc	178	void helper_fxtoq(CPUState *env, int64_t src)
1bccec25	179	{
44516772	180	/* No possible exceptions converting long long to long double. */
03fb8cfc	181	QT0 = int64_to_float128(src, &env->fp_status);
1bccec25 BS	182	}
	183	#endif
	184	#undef F_HELPER
	185
	186	/* floating point conversion */
03fb8cfc	187	float32 helper_fdtos(CPUState *env, float64 src)
1bccec25	188	{
44516772 RH	189	float32 ret;
	190	clear_float_exceptions(env);
	191	ret = float64_to_float32(src, &env->fp_status);
	192	check_ieee_exceptions(env);
	193	return ret;
1bccec25 BS	194	}
1bccec25 BS	195
03fb8cfc	196	float64 helper_fstod(CPUState *env, float32 src)
1bccec25	197	{
44516772 RH	198	float64 ret;
	199	clear_float_exceptions(env);
	200	ret = float32_to_float64(src, &env->fp_status);
	201	check_ieee_exceptions(env);
	202	return ret;
1bccec25 BS	203	}
1bccec25 BS	204
2e2f4ade	205	float32 helper_fqtos(CPUState *env)
1bccec25	206	{
44516772 RH	207	float32 ret;
	208	clear_float_exceptions(env);
	209	ret = float128_to_float32(QT1, &env->fp_status);
	210	check_ieee_exceptions(env);
	211	return ret;
1bccec25 BS	212	}
1bccec25 BS	213
2e2f4ade	214	void helper_fstoq(CPUState *env, float32 src)
1bccec25	215	{
44516772	216	clear_float_exceptions(env);
1bccec25	217	QT0 = float32_to_float128(src, &env->fp_status);
44516772	218	check_ieee_exceptions(env);
1bccec25 BS	219	}
1bccec25 BS	220
03fb8cfc	221	float64 helper_fqtod(CPUState *env)
1bccec25	222	{
44516772 RH	223	float64 ret;
	224	clear_float_exceptions(env);
	225	ret = float128_to_float64(QT1, &env->fp_status);
	226	check_ieee_exceptions(env);
	227	return ret;
1bccec25 BS	228	}
1bccec25 BS	229
03fb8cfc	230	void helper_fdtoq(CPUState *env, float64 src)
1bccec25	231	{
44516772	232	clear_float_exceptions(env);
03fb8cfc	233	QT0 = float64_to_float128(src, &env->fp_status);
44516772	234	check_ieee_exceptions(env);
1bccec25 BS	235	}
	236
	237	/* Float to integer conversion. */
2e2f4ade	238	int32_t helper_fstoi(CPUState *env, float32 src)
1bccec25	239	{
44516772 RH	240	int32_t ret;
	241	clear_float_exceptions(env);
	242	ret = float32_to_int32_round_to_zero(src, &env->fp_status);
	243	check_ieee_exceptions(env);
	244	return ret;
1bccec25 BS	245	}
1bccec25 BS	246
03fb8cfc	247	int32_t helper_fdtoi(CPUState *env, float64 src)
1bccec25	248	{
44516772 RH	249	int32_t ret;
	250	clear_float_exceptions(env);
	251	ret = float64_to_int32_round_to_zero(src, &env->fp_status);
	252	check_ieee_exceptions(env);
	253	return ret;
1bccec25 BS	254	}
1bccec25 BS	255
2e2f4ade	256	int32_t helper_fqtoi(CPUState *env)
1bccec25	257	{
44516772 RH	258	int32_t ret;
	259	clear_float_exceptions(env);
	260	ret = float128_to_int32_round_to_zero(QT1, &env->fp_status);
	261	check_ieee_exceptions(env);
	262	return ret;
1bccec25 BS	263	}
	264
	265	#ifdef TARGET_SPARC64
03fb8cfc	266	int64_t helper_fstox(CPUState *env, float32 src)
1bccec25	267	{
44516772 RH	268	int64_t ret;
	269	clear_float_exceptions(env);
	270	ret = float32_to_int64_round_to_zero(src, &env->fp_status);
	271	check_ieee_exceptions(env);
	272	return ret;
1bccec25 BS	273	}
1bccec25 BS	274
03fb8cfc	275	int64_t helper_fdtox(CPUState *env, float64 src)
1bccec25	276	{
44516772 RH	277	int64_t ret;
	278	clear_float_exceptions(env);
	279	ret = float64_to_int64_round_to_zero(src, &env->fp_status);
	280	check_ieee_exceptions(env);
	281	return ret;
1bccec25 BS	282	}
1bccec25 BS	283
03fb8cfc	284	int64_t helper_fqtox(CPUState *env)
1bccec25	285	{
44516772 RH	286	int64_t ret;
	287	clear_float_exceptions(env);
	288	ret = float128_to_int64_round_to_zero(QT1, &env->fp_status);
	289	check_ieee_exceptions(env);
	290	return ret;
1bccec25 BS	291	}
	292	#endif
	293
	294	float32 helper_fabss(float32 src)
	295	{
	296	return float32_abs(src);
	297	}
	298
	299	#ifdef TARGET_SPARC64
f027c3b1	300	float64 helper_fabsd(float64 src)
1bccec25	301	{
03fb8cfc	302	return float64_abs(src);
1bccec25 BS	303	}
1bccec25 BS	304
2e2f4ade	305	void helper_fabsq(CPUState *env)
1bccec25 BS	306	{
	307	QT0 = float128_abs(QT1);
	308	}
	309	#endif
	310
2e2f4ade	311	float32 helper_fsqrts(CPUState *env, float32 src)
1bccec25	312	{
44516772 RH	313	float32 ret;
	314	clear_float_exceptions(env);
	315	ret = float32_sqrt(src, &env->fp_status);
	316	check_ieee_exceptions(env);
	317	return ret;
1bccec25 BS	318	}
1bccec25 BS	319
03fb8cfc	320	float64 helper_fsqrtd(CPUState *env, float64 src)
1bccec25	321	{
44516772 RH	322	float64 ret;
	323	clear_float_exceptions(env);
	324	ret = float64_sqrt(src, &env->fp_status);
	325	check_ieee_exceptions(env);
	326	return ret;
1bccec25 BS	327	}
1bccec25 BS	328
2e2f4ade	329	void helper_fsqrtq(CPUState *env)
1bccec25	330	{
44516772	331	clear_float_exceptions(env);
1bccec25	332	QT0 = float128_sqrt(QT1, &env->fp_status);
44516772	333	check_ieee_exceptions(env);
1bccec25 BS	334	}
	335
	336	#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
2e2f4ade	337	void glue(helper_, name) (CPUState *env) \
1bccec25 BS	338	{ \
	339	env->fsr &= FSR_FTT_NMASK; \
	340	if (E && (glue(size, _is_any_nan)(reg1) \|\| \
	341	glue(size, _is_any_nan)(reg2)) && \
	342	(env->fsr & FSR_NVM)) { \
	343	env->fsr \|= FSR_NVC; \
	344	env->fsr \|= FSR_FTT_IEEE_EXCP; \
	345	helper_raise_exception(env, TT_FP_EXCP); \
	346	} \
	347	switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
	348	case float_relation_unordered: \
	349	if ((env->fsr & FSR_NVM)) { \
	350	env->fsr \|= FSR_NVC; \
	351	env->fsr \|= FSR_FTT_IEEE_EXCP; \
	352	helper_raise_exception(env, TT_FP_EXCP); \
	353	} else { \
	354	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	355	env->fsr \|= (FSR_FCC1 \| FSR_FCC0) << FS; \
	356	env->fsr \|= FSR_NVA; \
	357	} \
	358	break; \
	359	case float_relation_less: \
	360	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	361	env->fsr \|= FSR_FCC0 << FS; \
	362	break; \
	363	case float_relation_greater: \
	364	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	365	env->fsr \|= FSR_FCC1 << FS; \
	366	break; \
	367	default: \
	368	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	369	break; \
	370	} \
	371	}
03fb8cfc RH	372	#define GEN_FCMP_T(name, size, FS, E) \
03fb8cfc RH	373	void glue(helper_, name)(CPUState *env, size src1, size src2) \
1bccec25 BS	374	{ \
	375	env->fsr &= FSR_FTT_NMASK; \
	376	if (E && (glue(size, _is_any_nan)(src1) \|\| \
	377	glue(size, _is_any_nan)(src2)) && \
	378	(env->fsr & FSR_NVM)) { \
	379	env->fsr \|= FSR_NVC; \
	380	env->fsr \|= FSR_FTT_IEEE_EXCP; \
	381	helper_raise_exception(env, TT_FP_EXCP); \
	382	} \
	383	switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
	384	case float_relation_unordered: \
	385	if ((env->fsr & FSR_NVM)) { \
	386	env->fsr \|= FSR_NVC; \
	387	env->fsr \|= FSR_FTT_IEEE_EXCP; \
	388	helper_raise_exception(env, TT_FP_EXCP); \
	389	} else { \
	390	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	391	env->fsr \|= (FSR_FCC1 \| FSR_FCC0) << FS; \
	392	env->fsr \|= FSR_NVA; \
	393	} \
	394	break; \
	395	case float_relation_less: \
	396	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	397	env->fsr \|= FSR_FCC0 << FS; \
	398	break; \
	399	case float_relation_greater: \
	400	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	401	env->fsr \|= FSR_FCC1 << FS; \
	402	break; \
	403	default: \
	404	env->fsr &= ~((FSR_FCC1 \| FSR_FCC0) << FS); \
	405	break; \
	406	} \
	407	}
	408
03fb8cfc RH	409	GEN_FCMP_T(fcmps, float32, 0, 0);
03fb8cfc RH	410	GEN_FCMP_T(fcmpd, float64, 0, 0);
1bccec25	411
03fb8cfc RH	412	GEN_FCMP_T(fcmpes, float32, 0, 1);
03fb8cfc RH	413	GEN_FCMP_T(fcmped, float64, 0, 1);
1bccec25 BS	414
	415	GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
	416	GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
	417
	418	#ifdef TARGET_SPARC64
03fb8cfc RH	419	GEN_FCMP_T(fcmps_fcc1, float32, 22, 0);
03fb8cfc RH	420	GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0);
1bccec25 BS	421	GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
1bccec25 BS	422
03fb8cfc RH	423	GEN_FCMP_T(fcmps_fcc2, float32, 24, 0);
03fb8cfc RH	424	GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0);
1bccec25 BS	425	GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
1bccec25 BS	426
03fb8cfc RH	427	GEN_FCMP_T(fcmps_fcc3, float32, 26, 0);
03fb8cfc RH	428	GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0);
1bccec25 BS	429	GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
1bccec25 BS	430
03fb8cfc RH	431	GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1);
03fb8cfc RH	432	GEN_FCMP_T(fcmped_fcc1, float64, 22, 1);
1bccec25 BS	433	GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
1bccec25 BS	434
03fb8cfc RH	435	GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1);
03fb8cfc RH	436	GEN_FCMP_T(fcmped_fcc2, float64, 24, 1);
1bccec25 BS	437	GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
1bccec25 BS	438
03fb8cfc RH	439	GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1);
03fb8cfc RH	440	GEN_FCMP_T(fcmped_fcc3, float64, 26, 1);
1bccec25 BS	441	GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
1bccec25 BS	442	#endif
03fb8cfc RH	443	#undef GEN_FCMP_T
03fb8cfc RH	444	#undef GEN_FCMP
1bccec25	445
2e2f4ade	446	static inline void set_fsr(CPUState *env)
1bccec25 BS	447	{
	448	int rnd_mode;
	449
	450	switch (env->fsr & FSR_RD_MASK) {
	451	case FSR_RD_NEAREST:
	452	rnd_mode = float_round_nearest_even;
	453	break;
	454	default:
	455	case FSR_RD_ZERO:
	456	rnd_mode = float_round_to_zero;
	457	break;
	458	case FSR_RD_POS:
	459	rnd_mode = float_round_up;
	460	break;
	461	case FSR_RD_NEG:
	462	rnd_mode = float_round_down;
	463	break;
	464	}
	465	set_float_rounding_mode(rnd_mode, &env->fp_status);
	466	}
	467
2e2f4ade	468	void helper_ldfsr(CPUState *env, uint32_t new_fsr)
1bccec25 BS	469	{
1bccec25 BS	470	env->fsr = (new_fsr & FSR_LDFSR_MASK) \| (env->fsr & FSR_LDFSR_OLDMASK);
2e2f4ade	471	set_fsr(env);
1bccec25 BS	472	}
	473
	474	#ifdef TARGET_SPARC64
2e2f4ade	475	void helper_ldxfsr(CPUState *env, uint64_t new_fsr)
1bccec25 BS	476	{
1bccec25 BS	477	env->fsr = (new_fsr & FSR_LDXFSR_MASK) \| (env->fsr & FSR_LDXFSR_OLDMASK);
2e2f4ade	478	set_fsr(env);
1bccec25 BS	479	}
1bccec25 BS	480	#endif