[mirror_qemu.git] / target-sparc / helper.c

/*
 *  sparc helpers
 * 
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"

//#define DEBUG_MMU

/* Sparc MMU emulation */

/* thread support */

spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void cpu_lock(void)
{
    spin_lock(&global_cpu_lock);
}

void cpu_unlock(void)
{
    spin_unlock(&global_cpu_lock);
}

#if defined(CONFIG_USER_ONLY) 

int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
                               int is_user, int is_softmmu)
{
    if (rw & 2)
        env->exception_index = TT_TFAULT;
    else
        env->exception_index = TT_DFAULT;
    return 1;
}

#else

#ifndef TARGET_SPARC64
/*
 * Sparc V8 Reference MMU (SRMMU)
 */
static const int access_table[8][8] = {
    { 0, 0, 0, 0, 2, 0, 3, 3 },
    { 0, 0, 0, 0, 2, 0, 0, 0 },
    { 2, 2, 0, 0, 0, 2, 3, 3 },
    { 2, 2, 0, 0, 0, 2, 0, 0 },
    { 2, 0, 2, 0, 2, 2, 3, 3 },
    { 2, 0, 2, 0, 2, 0, 2, 0 },
    { 2, 2, 2, 0, 2, 2, 3, 3 },
    { 2, 2, 2, 0, 2, 2, 2, 0 }
};

/* 1 = write OK */
static const int rw_table[2][8] = {
    { 0, 1, 0, 1, 0, 1, 0, 1 },
    { 0, 1, 0, 1, 0, 0, 0, 0 }
};

int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
			  int *access_index, target_ulong address, int rw,
			  int is_user)
{
    int access_perms = 0;
    target_phys_addr_t pde_ptr;
    uint32_t pde;
    target_ulong virt_addr;
    int error_code = 0, is_dirty;
    unsigned long page_offset;

    virt_addr = address & TARGET_PAGE_MASK;
    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
	*physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
        return 0;
    }

    *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
    *physical = 0xfffff000;

    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
    /* Context base + context number */
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);

    /* Ctx pde */
    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
	return 1 << 2;
    case 2: /* L0 PTE, maybe should not happen? */
    case 3: /* Reserved */
        return 4 << 2;
    case 1: /* L0 PDE */
	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
        pde = ldl_phys(pde_ptr);

	switch (pde & PTE_ENTRYTYPE_MASK) {
	default:
	case 0: /* Invalid */
	    return (1 << 8) | (1 << 2);
	case 3: /* Reserved */
	    return (1 << 8) | (4 << 2);
	case 1: /* L1 PDE */
	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
            pde = ldl_phys(pde_ptr);

	    switch (pde & PTE_ENTRYTYPE_MASK) {
	    default:
	    case 0: /* Invalid */
		return (2 << 8) | (1 << 2);
	    case 3: /* Reserved */
		return (2 << 8) | (4 << 2);
	    case 1: /* L2 PDE */
		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                pde = ldl_phys(pde_ptr);

		switch (pde & PTE_ENTRYTYPE_MASK) {
		default:
		case 0: /* Invalid */
		    return (3 << 8) | (1 << 2);
		case 1: /* PDE, should not happen */
		case 3: /* Reserved */
		    return (3 << 8) | (4 << 2);
		case 2: /* L3 PTE */
		    virt_addr = address & TARGET_PAGE_MASK;
		    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
		}
		break;
	    case 2: /* L2 PTE */
		virt_addr = address & ~0x3ffff;
		page_offset = address & 0x3ffff;
	    }
	    break;
	case 2: /* L1 PTE */
	    virt_addr = address & ~0xffffff;
	    page_offset = address & 0xffffff;
	}
    }

    /* update page modified and dirty bits */
    is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
    if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
	pde |= PG_ACCESSED_MASK;
	if (is_dirty)
	    pde |= PG_MODIFIED_MASK;
        stl_phys_notdirty(pde_ptr, pde);
    }
    /* check access */
    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
    error_code = access_table[*access_index][access_perms];
    if (error_code && !(env->mmuregs[0] & MMU_NF))
	return error_code;

    /* the page can be put in the TLB */
    *prot = PAGE_READ;
    if (pde & PG_MODIFIED_MASK) {
        /* only set write access if already dirty... otherwise wait
           for dirty access */
	if (rw_table[is_user][access_perms])
	        *prot |= PAGE_WRITE;
    }

    /* Even if large ptes, we map only one 4KB page in the cache to
       avoid filling it too fast */
    *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
    return error_code;
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                              int is_user, int is_softmmu)
{
    target_phys_addr_t paddr;
    unsigned long vaddr;
    int error_code = 0, prot, ret = 0, access_index;

    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
    if (error_code == 0) {
	vaddr = address & TARGET_PAGE_MASK;
	paddr &= TARGET_PAGE_MASK;
#ifdef DEBUG_MMU
	printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
#endif
	ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	return ret;
    }

    if (env->mmuregs[3]) /* Fault status register */
	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
    env->mmuregs[3] |= (access_index << 5) | error_code | 2;
    env->mmuregs[4] = address; /* Fault address register */

    if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
        // No fault mode: if a mapping is available, just override
        // permissions. If no mapping is available, redirect accesses to
        // neverland. Fake/overridden mappings will be flushed when
        // switching to normal mode.
	vaddr = address & TARGET_PAGE_MASK;
        prot = PAGE_READ | PAGE_WRITE;
        ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	return ret;
    } else {
        if (rw & 2)
            env->exception_index = TT_TFAULT;
        else
            env->exception_index = TT_DFAULT;
        return 1;
    }
}

target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
{
    target_phys_addr_t pde_ptr;
    uint32_t pde;

    /* Context base + context number */
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);

    switch (pde & PTE_ENTRYTYPE_MASK) {
    default:
    case 0: /* Invalid */
    case 2: /* PTE, maybe should not happen? */
    case 3: /* Reserved */
	return 0;
    case 1: /* L1 PDE */
	if (mmulev == 3)
	    return pde;
	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
        pde = ldl_phys(pde_ptr);

	switch (pde & PTE_ENTRYTYPE_MASK) {
	default:
	case 0: /* Invalid */
	case 3: /* Reserved */
	    return 0;
	case 2: /* L1 PTE */
	    return pde;
	case 1: /* L2 PDE */
	    if (mmulev == 2)
		return pde;
	    pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
            pde = ldl_phys(pde_ptr);

	    switch (pde & PTE_ENTRYTYPE_MASK) {
	    default:
	    case 0: /* Invalid */
	    case 3: /* Reserved */
		return 0;
	    case 2: /* L2 PTE */
		return pde;
	    case 1: /* L3 PDE */
		if (mmulev == 1)
		    return pde;
		pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
                pde = ldl_phys(pde_ptr);

		switch (pde & PTE_ENTRYTYPE_MASK) {
		default:
		case 0: /* Invalid */
		case 1: /* PDE, should not happen */
		case 3: /* Reserved */
		    return 0;
		case 2: /* L3 PTE */
		    return pde;
		}
	    }
	}
    }
    return 0;
}

#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
     target_ulong va, va1, va2;
     unsigned int n, m, o;
     target_phys_addr_t pde_ptr, pa;
    uint32_t pde;

    printf("MMU dump:\n");
    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
    pde = ldl_phys(pde_ptr);
    printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
    for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
	pde_ptr = mmu_probe(env, va, 2);
	if (pde_ptr) {
	    pa = cpu_get_phys_page_debug(env, va);
 	    printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
	    for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
		pde_ptr = mmu_probe(env, va1, 1);
		if (pde_ptr) {
		    pa = cpu_get_phys_page_debug(env, va1);
 		    printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
		    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
			pde_ptr = mmu_probe(env, va2, 0);
			if (pde_ptr) {
			    pa = cpu_get_phys_page_debug(env, va2);
 			    printf("  VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
			}
		    }
		}
	    }
	}
    }
    printf("MMU dump ends\n");
}
#endif /* DEBUG_MMU */

#else /* !TARGET_SPARC64 */
/*
 * UltraSparc IIi I/DMMUs
 */
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
			  int *access_index, target_ulong address, int rw,
			  int is_user)
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
	*physical = address;
	*prot = PAGE_READ | PAGE_WRITE;
        return 0;
    }

    for (i = 0; i < 64; i++) {
	switch ((env->dtlb_tte[i] >> 61) & 3) {
	default:
	case 0x0: // 8k
	    mask = 0xffffffffffffe000ULL;
	    break;
	case 0x1: // 64k
	    mask = 0xffffffffffff0000ULL;
	    break;
	case 0x2: // 512k
	    mask = 0xfffffffffff80000ULL;
	    break;
	case 0x3: // 4M
	    mask = 0xffffffffffc00000ULL;
	    break;
	}
	// ctx match, vaddr match?
	if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
	    (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
	    // valid, access ok?
	    if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
		((env->dtlb_tte[i] & 0x4) && is_user) ||
		(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
		if (env->dmmuregs[3]) /* Fault status register */
		    env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
		env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
		env->dmmuregs[4] = address; /* Fault address register */
		env->exception_index = TT_DFAULT;
#ifdef DEBUG_MMU
		printf("DFAULT at 0x%llx\n", address);
#endif
		return 1;
	    }
	    *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
	    *prot = PAGE_READ;
	    if (env->dtlb_tte[i] & 0x2)
		*prot |= PAGE_WRITE;
	    return 0;
	}
    }
#ifdef DEBUG_MMU
    printf("DMISS at 0x%llx\n", address);
#endif
    env->exception_index = TT_DMISS;
    return 1;
}

static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
			  int *access_index, target_ulong address, int rw,
			  int is_user)
{
    target_ulong mask;
    unsigned int i;

    if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
	*physical = address;
	*prot = PAGE_READ;
        return 0;
    }

    for (i = 0; i < 64; i++) {
	switch ((env->itlb_tte[i] >> 61) & 3) {
	default:
	case 0x0: // 8k
	    mask = 0xffffffffffffe000ULL;
	    break;
	case 0x1: // 64k
	    mask = 0xffffffffffff0000ULL;
	    break;
	case 0x2: // 512k
	    mask = 0xfffffffffff80000ULL;
	    break;
	case 0x3: // 4M
	    mask = 0xffffffffffc00000ULL;
		break;
	}
	// ctx match, vaddr match?
	if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
	    (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
	    // valid, access ok?
	    if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
		((env->itlb_tte[i] & 0x4) && is_user)) {
		if (env->immuregs[3]) /* Fault status register */
		    env->immuregs[3] = 2; /* overflow (not read before another fault) */
		env->immuregs[3] |= (is_user << 3) | 1;
		env->exception_index = TT_TFAULT;
#ifdef DEBUG_MMU
		printf("TFAULT at 0x%llx\n", address);
#endif
		return 1;
	    }
	    *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
	    *prot = PAGE_READ;
	    return 0;
	}
    }
#ifdef DEBUG_MMU
    printf("TMISS at 0x%llx\n", address);
#endif
    env->exception_index = TT_TMISS;
    return 1;
}

int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
			  int *access_index, target_ulong address, int rw,
			  int is_user)
{
    if (rw == 2)
	return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
    else
	return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
}

/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                              int is_user, int is_softmmu)
{
    target_ulong virt_addr, vaddr;
    target_phys_addr_t paddr;
    int error_code = 0, prot, ret = 0, access_index;

    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
    if (error_code == 0) {
	virt_addr = address & TARGET_PAGE_MASK;
	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
#ifdef DEBUG_MMU
	printf("Translate at 0x%llx -> 0x%llx, vaddr 0x%llx\n", address, paddr, vaddr);
#endif
	ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	return ret;
    }
    // XXX
    return 1;
}

#ifdef DEBUG_MMU
void dump_mmu(CPUState *env)
{
    unsigned int i;
    const char *mask;

    printf("MMU contexts: Primary: %lld, Secondary: %lld\n", env->dmmuregs[1], env->dmmuregs[2]);
    if ((env->lsu & DMMU_E) == 0) {
	printf("DMMU disabled\n");
    } else {
	printf("DMMU dump:\n");
	for (i = 0; i < 64; i++) {
	    switch ((env->dtlb_tte[i] >> 61) & 3) {
	    default:
	    case 0x0:
		mask = "  8k";
		break;
	    case 0x1:
		mask = " 64k";
		break;
	    case 0x2:
		mask = "512k";
		break;
	    case 0x3:
		mask = "  4M";
		break;
	    }
	    if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
		printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %lld\n",
		       env->dtlb_tag[i] & ~0x1fffULL,
		       env->dtlb_tte[i] & 0x1ffffffe000ULL,
		       mask,
		       env->dtlb_tte[i] & 0x4? "priv": "user",
		       env->dtlb_tte[i] & 0x2? "RW": "RO",
		       env->dtlb_tte[i] & 0x40? "locked": "unlocked",
		       env->dtlb_tag[i] & 0x1fffULL);
	    }
	}
    }
    if ((env->lsu & IMMU_E) == 0) {
	printf("IMMU disabled\n");
    } else {
	printf("IMMU dump:\n");
	for (i = 0; i < 64; i++) {
	    switch ((env->itlb_tte[i] >> 61) & 3) {
	    default:
	    case 0x0:
		mask = "  8k";
		break;
	    case 0x1:
		mask = " 64k";
		break;
	    case 0x2:
		mask = "512k";
		break;
	    case 0x3:
		mask = "  4M";
		break;
	    }
	    if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
		printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %lld\n",
		       env->itlb_tag[i] & ~0x1fffULL,
		       env->itlb_tte[i] & 0x1ffffffe000ULL,
		       mask,
		       env->itlb_tte[i] & 0x4? "priv": "user",
		       env->itlb_tte[i] & 0x40? "locked": "unlocked",
		       env->itlb_tag[i] & 0x1fffULL);
	    }
	}
    }
}
#endif /* DEBUG_MMU */

#endif /* TARGET_SPARC64 */
#endif /* !CONFIG_USER_ONLY */

void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}
Commit	Line	Data
e8af50a3 FB	1	/*
	2	* sparc helpers
	3	*
83469015	4	* Copyright (c) 2003-2005 Fabrice Bellard
e8af50a3 FB	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
ee5bbe38 FB	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
e8af50a3	30
e80cfcfc	31	//#define DEBUG_MMU
e8af50a3	32
e8af50a3	33	/* Sparc MMU emulation */
e8af50a3	34
e8af50a3 FB	35	/* thread support */
	36
	37	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
	38
	39	void cpu_lock(void)
	40	{
	41	spin_lock(&global_cpu_lock);
	42	}
	43
	44	void cpu_unlock(void)
	45	{
	46	spin_unlock(&global_cpu_lock);
	47	}
	48
9d893301 FB	49	#if defined(CONFIG_USER_ONLY)
	50
	51	int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
	52	int is_user, int is_softmmu)
	53	{
878d3096 FB	54	if (rw & 2)
	55	env->exception_index = TT_TFAULT;
	56	else
	57	env->exception_index = TT_DFAULT;
9d893301 FB	58	return 1;
	59	}
	60
	61	#else
e8af50a3	62
3475187d	63	#ifndef TARGET_SPARC64
83469015 FB	64	/*
	65	* Sparc V8 Reference MMU (SRMMU)
	66	*/
e8af50a3 FB	67	static const int access_table[8][8] = {
	68	{ 0, 0, 0, 0, 2, 0, 3, 3 },
	69	{ 0, 0, 0, 0, 2, 0, 0, 0 },
	70	{ 2, 2, 0, 0, 0, 2, 3, 3 },
	71	{ 2, 2, 0, 0, 0, 2, 0, 0 },
	72	{ 2, 0, 2, 0, 2, 2, 3, 3 },
	73	{ 2, 0, 2, 0, 2, 0, 2, 0 },
	74	{ 2, 2, 2, 0, 2, 2, 3, 3 },
	75	{ 2, 2, 2, 0, 2, 2, 2, 0 }
	76	};
	77
	78	/* 1 = write OK */
	79	static const int rw_table[2][8] = {
	80	{ 0, 1, 0, 1, 0, 1, 0, 1 },
	81	{ 0, 1, 0, 1, 0, 0, 0, 0 }
	82	};
	83
af7bf89b FB	84	int get_physical_address (CPUState env, target_phys_addr_t physical, int *prot,
af7bf89b FB	85	int *access_index, target_ulong address, int rw,
e80cfcfc	86	int is_user)
e8af50a3	87	{
e80cfcfc FB	88	int access_perms = 0;
e80cfcfc FB	89	target_phys_addr_t pde_ptr;
af7bf89b FB	90	uint32_t pde;
af7bf89b FB	91	target_ulong virt_addr;
e80cfcfc FB	92	int error_code = 0, is_dirty;
e80cfcfc FB	93	unsigned long page_offset;
e8af50a3 FB	94
	95	virt_addr = address & TARGET_PAGE_MASK;
	96	if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
e80cfcfc FB	97	*physical = address;
	98	*prot = PAGE_READ \| PAGE_WRITE;
	99	return 0;
e8af50a3 FB	100	}
e8af50a3 FB	101
7483750d	102	*access_index = ((rw & 1) << 2) \| (rw & 2) \| (is_user? 0 : 1);
6f7e9aec	103	*physical = 0xfffff000;
7483750d	104
e8af50a3 FB	105	/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
e8af50a3 FB	106	/* Context base + context number */
b3180cdc	107	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
49be8030	108	pde = ldl_phys(pde_ptr);
e8af50a3 FB	109
	110	/* Ctx pde */
	111	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	112	default:
e8af50a3	113	case 0: /* Invalid */
7483750d	114	return 1 << 2;
e80cfcfc	115	case 2: /* L0 PTE, maybe should not happen? */
e8af50a3	116	case 3: /* Reserved */
7483750d	117	return 4 << 2;
e80cfcfc FB	118	case 1: /* L0 PDE */
e80cfcfc FB	119	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
49be8030	120	pde = ldl_phys(pde_ptr);
e8af50a3 FB	121
e8af50a3 FB	122	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	123	default:
e8af50a3	124	case 0: /* Invalid */
7483750d	125	return (1 << 8) \| (1 << 2);
e8af50a3	126	case 3: /* Reserved */
7483750d	127	return (1 << 8) \| (4 << 2);
e80cfcfc FB	128	case 1: /* L1 PDE */
e80cfcfc FB	129	pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
49be8030	130	pde = ldl_phys(pde_ptr);
e8af50a3 FB	131
e8af50a3 FB	132	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	133	default:
e8af50a3	134	case 0: /* Invalid */
7483750d	135	return (2 << 8) \| (1 << 2);
e8af50a3	136	case 3: /* Reserved */
7483750d	137	return (2 << 8) \| (4 << 2);
e80cfcfc FB	138	case 1: /* L2 PDE */
e80cfcfc FB	139	pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
49be8030	140	pde = ldl_phys(pde_ptr);
e8af50a3 FB	141
e8af50a3 FB	142	switch (pde & PTE_ENTRYTYPE_MASK) {
e80cfcfc	143	default:
e8af50a3	144	case 0: /* Invalid */
7483750d	145	return (3 << 8) \| (1 << 2);
e8af50a3 FB	146	case 1: /* PDE, should not happen */
e8af50a3 FB	147	case 3: /* Reserved */
7483750d	148	return (3 << 8) \| (4 << 2);
e8af50a3 FB	149	case 2: /* L3 PTE */
	150	virt_addr = address & TARGET_PAGE_MASK;
	151	page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
	152	}
	153	break;
	154	case 2: /* L2 PTE */
	155	virt_addr = address & ~0x3ffff;
	156	page_offset = address & 0x3ffff;
	157	}
	158	break;
	159	case 2: /* L1 PTE */
	160	virt_addr = address & ~0xffffff;
	161	page_offset = address & 0xffffff;
	162	}
	163	}
	164
	165	/* update page modified and dirty bits */
b769d8fe	166	is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
e8af50a3 FB	167	if (!(pde & PG_ACCESSED_MASK) \|\| is_dirty) {
	168	pde \|= PG_ACCESSED_MASK;
	169	if (is_dirty)
	170	pde \|= PG_MODIFIED_MASK;
49be8030	171	stl_phys_notdirty(pde_ptr, pde);
e8af50a3	172	}
e8af50a3	173	/* check access */
e8af50a3	174	access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
e80cfcfc	175	error_code = access_table[*access_index][access_perms];
6f7e9aec	176	if (error_code && !(env->mmuregs[0] & MMU_NF))
e80cfcfc	177	return error_code;
e8af50a3 FB	178
e8af50a3 FB	179	/* the page can be put in the TLB */
e80cfcfc	180	*prot = PAGE_READ;
e8af50a3 FB	181	if (pde & PG_MODIFIED_MASK) {
	182	/* only set write access if already dirty... otherwise wait
	183	for dirty access */
	184	if (rw_table[is_user][access_perms])
e80cfcfc	185	*prot \|= PAGE_WRITE;
e8af50a3 FB	186	}
	187
	188	/* Even if large ptes, we map only one 4KB page in the cache to
	189	avoid filling it too fast */
e80cfcfc	190	*physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
6f7e9aec	191	return error_code;
e80cfcfc FB	192	}
	193
	194	/* Perform address translation */
af7bf89b	195	int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
e80cfcfc FB	196	int is_user, int is_softmmu)
e80cfcfc FB	197	{
af7bf89b	198	target_phys_addr_t paddr;
e80cfcfc FB	199	unsigned long vaddr;
e80cfcfc FB	200	int error_code = 0, prot, ret = 0, access_index;
e8af50a3	201
e80cfcfc FB	202	error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
e80cfcfc FB	203	if (error_code == 0) {
9e61bde5 FB	204	vaddr = address & TARGET_PAGE_MASK;
	205	paddr &= TARGET_PAGE_MASK;
	206	#ifdef DEBUG_MMU
	207	printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
	208	#endif
e80cfcfc FB	209	ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	210	return ret;
	211	}
e8af50a3	212
e8af50a3 FB	213	if (env->mmuregs[3]) /* Fault status register */
e8af50a3 FB	214	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
7483750d	215	env->mmuregs[3] \|= (access_index << 5) \| error_code \| 2;
e8af50a3 FB	216	env->mmuregs[4] = address; /* Fault address register */
e8af50a3 FB	217
878d3096	218	if ((env->mmuregs[0] & MMU_NF) \|\| env->psret == 0) {
6f7e9aec FB	219	// No fault mode: if a mapping is available, just override
	220	// permissions. If no mapping is available, redirect accesses to
	221	// neverland. Fake/overridden mappings will be flushed when
	222	// switching to normal mode.
7483750d	223	vaddr = address & TARGET_PAGE_MASK;
7483750d FB	224	prot = PAGE_READ \| PAGE_WRITE;
	225	ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	226	return ret;
7483750d FB	227	} else {
	228	if (rw & 2)
	229	env->exception_index = TT_TFAULT;
	230	else
	231	env->exception_index = TT_DFAULT;
	232	return 1;
878d3096	233	}
e8af50a3	234	}
24741ef3 FB	235
	236	target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
	237	{
	238	target_phys_addr_t pde_ptr;
	239	uint32_t pde;
	240
	241	/* Context base + context number */
	242	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
	243	pde = ldl_phys(pde_ptr);
	244
	245	switch (pde & PTE_ENTRYTYPE_MASK) {
	246	default:
	247	case 0: /* Invalid */
	248	case 2: /* PTE, maybe should not happen? */
	249	case 3: /* Reserved */
	250	return 0;
	251	case 1: /* L1 PDE */
	252	if (mmulev == 3)
	253	return pde;
	254	pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
	255	pde = ldl_phys(pde_ptr);
	256
	257	switch (pde & PTE_ENTRYTYPE_MASK) {
	258	default:
	259	case 0: /* Invalid */
	260	case 3: /* Reserved */
	261	return 0;
	262	case 2: /* L1 PTE */
	263	return pde;
	264	case 1: /* L2 PDE */
	265	if (mmulev == 2)
	266	return pde;
	267	pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
	268	pde = ldl_phys(pde_ptr);
	269
	270	switch (pde & PTE_ENTRYTYPE_MASK) {
	271	default:
	272	case 0: /* Invalid */
	273	case 3: /* Reserved */
	274	return 0;
	275	case 2: /* L2 PTE */
	276	return pde;
	277	case 1: /* L3 PDE */
	278	if (mmulev == 1)
	279	return pde;
	280	pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
	281	pde = ldl_phys(pde_ptr);
	282
	283	switch (pde & PTE_ENTRYTYPE_MASK) {
	284	default:
	285	case 0: /* Invalid */
	286	case 1: /* PDE, should not happen */
	287	case 3: /* Reserved */
	288	return 0;
	289	case 2: /* L3 PTE */
	290	return pde;
	291	}
	292	}
	293	}
	294	}
	295	return 0;
	296	}
	297
	298	#ifdef DEBUG_MMU
299	void dump_mmu(CPUState *env)
300	{
301	target_ulong va, va1, va2;
302	unsigned int n, m, o;
303	target_phys_addr_t pde_ptr, pa;
304	uint32_t pde;
305
306	printf("MMU dump:\n");
307	pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
308	pde = ldl_phys(pde_ptr);
309	printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
310	for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
311	pde_ptr = mmu_probe(env, va, 2);
312	if (pde_ptr) {
313	pa = cpu_get_phys_page_debug(env, va);
314	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
315	for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
316	pde_ptr = mmu_probe(env, va1, 1);
317	if (pde_ptr) {
318	pa = cpu_get_phys_page_debug(env, va1);
319	printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
320	for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
321	pde_ptr = mmu_probe(env, va2, 0);
322	if (pde_ptr) {
323	pa = cpu_get_phys_page_debug(env, va2);
324	printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
325	}
326	}
327	}
328	}
329	}
330	}
331	printf("MMU dump ends\n");
332	}
333	#endif /* DEBUG_MMU */
334
335	#else /* !TARGET_SPARC64 */
83469015 FB	336	/*
	337	* UltraSparc IIi I/DMMUs
	338	*/
3475187d FB	339	static int get_physical_address_data(CPUState env, target_phys_addr_t physical, int *prot,
	340	int *access_index, target_ulong address, int rw,
	341	int is_user)
	342	{
	343	target_ulong mask;
	344	unsigned int i;
	345
	346	if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
83469015	347	*physical = address;
3475187d FB	348	*prot = PAGE_READ \| PAGE_WRITE;
	349	return 0;
	350	}
	351
	352	for (i = 0; i < 64; i++) {
83469015 FB	353	switch ((env->dtlb_tte[i] >> 61) & 3) {
	354	default:
	355	case 0x0: // 8k
	356	mask = 0xffffffffffffe000ULL;
	357	break;
	358	case 0x1: // 64k
	359	mask = 0xffffffffffff0000ULL;
	360	break;
	361	case 0x2: // 512k
	362	mask = 0xfffffffffff80000ULL;
	363	break;
	364	case 0x3: // 4M
	365	mask = 0xffffffffffc00000ULL;
	366	break;
	367	}
	368	// ctx match, vaddr match?
	369	if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
	370	(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
	371	// valid, access ok?
	372	if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 \|\|
	373	((env->dtlb_tte[i] & 0x4) && is_user) \|\|
	374	(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
	375	if (env->dmmuregs[3]) /* Fault status register */
	376	env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
	377	env->dmmuregs[3] \|= (is_user << 3) \| ((rw == 1) << 2) \| 1;
	378	env->dmmuregs[4] = address; /* Fault address register */
	379	env->exception_index = TT_DFAULT;
	380	#ifdef DEBUG_MMU
	381	printf("DFAULT at 0x%llx\n", address);
	382	#endif
	383	return 1;
3475187d	384	}
83469015 FB	385	*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
	386	*prot = PAGE_READ;
	387	if (env->dtlb_tte[i] & 0x2)
	388	*prot \|= PAGE_WRITE;
	389	return 0;
3475187d FB	390	}
3475187d FB	391	}
83469015 FB	392	#ifdef DEBUG_MMU
	393	printf("DMISS at 0x%llx\n", address);
	394	#endif
	395	env->exception_index = TT_DMISS;
3475187d FB	396	return 1;
	397	}
	398
	399	static int get_physical_address_code(CPUState env, target_phys_addr_t physical, int *prot,
	400	int *access_index, target_ulong address, int rw,
	401	int is_user)
	402	{
	403	target_ulong mask;
	404	unsigned int i;
	405
	406	if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
83469015	407	*physical = address;
3475187d FB	408	*prot = PAGE_READ;
	409	return 0;
	410	}
83469015	411
3475187d	412	for (i = 0; i < 64; i++) {
83469015 FB	413	switch ((env->itlb_tte[i] >> 61) & 3) {
	414	default:
	415	case 0x0: // 8k
	416	mask = 0xffffffffffffe000ULL;
	417	break;
	418	case 0x1: // 64k
	419	mask = 0xffffffffffff0000ULL;
	420	break;
	421	case 0x2: // 512k
	422	mask = 0xfffffffffff80000ULL;
	423	break;
	424	case 0x3: // 4M
	425	mask = 0xffffffffffc00000ULL;
3475187d	426	break;
83469015 FB	427	}
	428	// ctx match, vaddr match?
	429	if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
	430	(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
	431	// valid, access ok?
	432	if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 \|\|
	433	((env->itlb_tte[i] & 0x4) && is_user)) {
	434	if (env->immuregs[3]) /* Fault status register */
	435	env->immuregs[3] = 2; /* overflow (not read before another fault) */
	436	env->immuregs[3] \|= (is_user << 3) \| 1;
	437	env->exception_index = TT_TFAULT;
	438	#ifdef DEBUG_MMU
	439	printf("TFAULT at 0x%llx\n", address);
	440	#endif
	441	return 1;
3475187d	442	}
83469015 FB	443	*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
	444	*prot = PAGE_READ;
	445	return 0;
3475187d FB	446	}
3475187d FB	447	}
83469015 FB	448	#ifdef DEBUG_MMU
	449	printf("TMISS at 0x%llx\n", address);
	450	#endif
	451	env->exception_index = TT_TMISS;
3475187d FB	452	return 1;
	453	}
	454
	455	int get_physical_address(CPUState env, target_phys_addr_t physical, int *prot,
	456	int *access_index, target_ulong address, int rw,
	457	int is_user)
	458	{
	459	if (rw == 2)
	460	return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
	461	else
	462	return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
	463	}
	464
	465	/* Perform address translation */
	466	int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
	467	int is_user, int is_softmmu)
	468	{
83469015	469	target_ulong virt_addr, vaddr;
3475187d	470	target_phys_addr_t paddr;
3475187d FB	471	int error_code = 0, prot, ret = 0, access_index;
	472
	473	error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
	474	if (error_code == 0) {
	475	virt_addr = address & TARGET_PAGE_MASK;
	476	vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
83469015 FB	477	#ifdef DEBUG_MMU
	478	printf("Translate at 0x%llx -> 0x%llx, vaddr 0x%llx\n", address, paddr, vaddr);
	479	#endif
3475187d FB	480	ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
	481	return ret;
	482	}
	483	// XXX
	484	return 1;
	485	}
	486
83469015 FB	487	#ifdef DEBUG_MMU
	488	void dump_mmu(CPUState *env)
	489	{
	490	unsigned int i;
	491	const char *mask;
	492
	493	printf("MMU contexts: Primary: %lld, Secondary: %lld\n", env->dmmuregs[1], env->dmmuregs[2]);
	494	if ((env->lsu & DMMU_E) == 0) {
	495	printf("DMMU disabled\n");
	496	} else {
	497	printf("DMMU dump:\n");
	498	for (i = 0; i < 64; i++) {
	499	switch ((env->dtlb_tte[i] >> 61) & 3) {
	500	default:
	501	case 0x0:
	502	mask = " 8k";
	503	break;
	504	case 0x1:
	505	mask = " 64k";
	506	break;
	507	case 0x2:
	508	mask = "512k";
	509	break;
	510	case 0x3:
	511	mask = " 4M";
	512	break;
	513	}
	514	if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
	515	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %lld\n",
	516	env->dtlb_tag[i] & ~0x1fffULL,
	517	env->dtlb_tte[i] & 0x1ffffffe000ULL,
	518	mask,
	519	env->dtlb_tte[i] & 0x4? "priv": "user",
	520	env->dtlb_tte[i] & 0x2? "RW": "RO",
	521	env->dtlb_tte[i] & 0x40? "locked": "unlocked",
	522	env->dtlb_tag[i] & 0x1fffULL);
	523	}
	524	}
	525	}
	526	if ((env->lsu & IMMU_E) == 0) {
	527	printf("IMMU disabled\n");
	528	} else {
	529	printf("IMMU dump:\n");
	530	for (i = 0; i < 64; i++) {
	531	switch ((env->itlb_tte[i] >> 61) & 3) {
	532	default:
	533	case 0x0:
	534	mask = " 8k";
	535	break;
	536	case 0x1:
	537	mask = " 64k";
	538	break;
	539	case 0x2:
	540	mask = "512k";
	541	break;
	542	case 0x3:
	543	mask = " 4M";
	544	break;
	545	}
	546	if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
	547	printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %lld\n",
	548	env->itlb_tag[i] & ~0x1fffULL,
	549	env->itlb_tte[i] & 0x1ffffffe000ULL,
	550	mask,
551	env->itlb_tte[i] & 0x4? "priv": "user",
552	env->itlb_tte[i] & 0x40? "locked": "unlocked",
553	env->itlb_tag[i] & 0x1fffULL);
554	}
555	}
556	}
557	}
24741ef3 FB	558	#endif /* DEBUG_MMU */
	559
	560	#endif /* TARGET_SPARC64 */
	561	#endif /* !CONFIG_USER_ONLY */
	562
	563	void memcpy32(target_ulong dst, const target_ulong src)
	564	{
	565	dst[0] = src[0];
	566	dst[1] = src[1];
	567	dst[2] = src[2];
	568	dst[3] = src[3];
	569	dst[4] = src[4];
	570	dst[5] = src[5];
	571	dst[6] = src[6];
	572	dst[7] = src[7];
	573	}