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fafd8bce BS |
1 | /* |
2 | * Helpers for loads and stores | |
3 | * | |
4 | * Copyright (c) 2003-2005 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
fafd8bce BS |
21 | #include "helper.h" |
22 | ||
fafd8bce BS |
23 | //#define DEBUG_MMU |
24 | //#define DEBUG_MXCC | |
25 | //#define DEBUG_UNALIGNED | |
26 | //#define DEBUG_UNASSIGNED | |
27 | //#define DEBUG_ASI | |
28 | //#define DEBUG_CACHE_CONTROL | |
29 | ||
30 | #ifdef DEBUG_MMU | |
31 | #define DPRINTF_MMU(fmt, ...) \ | |
32 | do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) | |
33 | #else | |
34 | #define DPRINTF_MMU(fmt, ...) do {} while (0) | |
35 | #endif | |
36 | ||
37 | #ifdef DEBUG_MXCC | |
38 | #define DPRINTF_MXCC(fmt, ...) \ | |
39 | do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) | |
40 | #else | |
41 | #define DPRINTF_MXCC(fmt, ...) do {} while (0) | |
42 | #endif | |
43 | ||
44 | #ifdef DEBUG_ASI | |
45 | #define DPRINTF_ASI(fmt, ...) \ | |
46 | do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) | |
47 | #endif | |
48 | ||
49 | #ifdef DEBUG_CACHE_CONTROL | |
50 | #define DPRINTF_CACHE_CONTROL(fmt, ...) \ | |
51 | do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) | |
52 | #else | |
53 | #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) | |
54 | #endif | |
55 | ||
56 | #ifdef TARGET_SPARC64 | |
57 | #ifndef TARGET_ABI32 | |
58 | #define AM_CHECK(env1) ((env1)->pstate & PS_AM) | |
59 | #else | |
60 | #define AM_CHECK(env1) (1) | |
61 | #endif | |
62 | #endif | |
63 | ||
fafd8bce BS |
64 | #define QT0 (env->qt0) |
65 | #define QT1 (env->qt1) | |
66 | ||
0184e266 | 67 | #if !defined(CONFIG_USER_ONLY) |
8f721967 BS |
68 | static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, |
69 | target_ulong addr, int is_write, | |
70 | int is_user, uintptr_t retaddr); | |
022c62cb | 71 | #include "exec/softmmu_exec.h" |
0184e266 BS |
72 | #define MMUSUFFIX _mmu |
73 | #define ALIGNED_ONLY | |
74 | ||
75 | #define SHIFT 0 | |
022c62cb | 76 | #include "exec/softmmu_template.h" |
0184e266 BS |
77 | |
78 | #define SHIFT 1 | |
022c62cb | 79 | #include "exec/softmmu_template.h" |
0184e266 BS |
80 | |
81 | #define SHIFT 2 | |
022c62cb | 82 | #include "exec/softmmu_template.h" |
0184e266 BS |
83 | |
84 | #define SHIFT 3 | |
022c62cb | 85 | #include "exec/softmmu_template.h" |
0184e266 BS |
86 | #endif |
87 | ||
fafd8bce BS |
88 | #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) |
89 | /* Calculates TSB pointer value for fault page size 8k or 64k */ | |
90 | static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register, | |
91 | uint64_t tag_access_register, | |
92 | int page_size) | |
93 | { | |
94 | uint64_t tsb_base = tsb_register & ~0x1fffULL; | |
95 | int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; | |
96 | int tsb_size = tsb_register & 0xf; | |
97 | ||
98 | /* discard lower 13 bits which hold tag access context */ | |
99 | uint64_t tag_access_va = tag_access_register & ~0x1fffULL; | |
100 | ||
101 | /* now reorder bits */ | |
102 | uint64_t tsb_base_mask = ~0x1fffULL; | |
103 | uint64_t va = tag_access_va; | |
104 | ||
105 | /* move va bits to correct position */ | |
106 | if (page_size == 8*1024) { | |
107 | va >>= 9; | |
108 | } else if (page_size == 64*1024) { | |
109 | va >>= 12; | |
110 | } | |
111 | ||
112 | if (tsb_size) { | |
113 | tsb_base_mask <<= tsb_size; | |
114 | } | |
115 | ||
116 | /* calculate tsb_base mask and adjust va if split is in use */ | |
117 | if (tsb_split) { | |
118 | if (page_size == 8*1024) { | |
119 | va &= ~(1ULL << (13 + tsb_size)); | |
120 | } else if (page_size == 64*1024) { | |
121 | va |= (1ULL << (13 + tsb_size)); | |
122 | } | |
123 | tsb_base_mask <<= 1; | |
124 | } | |
125 | ||
126 | return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; | |
127 | } | |
128 | ||
129 | /* Calculates tag target register value by reordering bits | |
130 | in tag access register */ | |
131 | static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) | |
132 | { | |
133 | return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); | |
134 | } | |
135 | ||
136 | static void replace_tlb_entry(SparcTLBEntry *tlb, | |
137 | uint64_t tlb_tag, uint64_t tlb_tte, | |
c5f9864e | 138 | CPUSPARCState *env1) |
fafd8bce BS |
139 | { |
140 | target_ulong mask, size, va, offset; | |
141 | ||
142 | /* flush page range if translation is valid */ | |
143 | if (TTE_IS_VALID(tlb->tte)) { | |
144 | ||
145 | mask = 0xffffffffffffe000ULL; | |
146 | mask <<= 3 * ((tlb->tte >> 61) & 3); | |
147 | size = ~mask + 1; | |
148 | ||
149 | va = tlb->tag & mask; | |
150 | ||
151 | for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { | |
152 | tlb_flush_page(env1, va + offset); | |
153 | } | |
154 | } | |
155 | ||
156 | tlb->tag = tlb_tag; | |
157 | tlb->tte = tlb_tte; | |
158 | } | |
159 | ||
160 | static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, | |
c5f9864e | 161 | const char *strmmu, CPUSPARCState *env1) |
fafd8bce BS |
162 | { |
163 | unsigned int i; | |
164 | target_ulong mask; | |
165 | uint64_t context; | |
166 | ||
167 | int is_demap_context = (demap_addr >> 6) & 1; | |
168 | ||
169 | /* demap context */ | |
170 | switch ((demap_addr >> 4) & 3) { | |
171 | case 0: /* primary */ | |
172 | context = env1->dmmu.mmu_primary_context; | |
173 | break; | |
174 | case 1: /* secondary */ | |
175 | context = env1->dmmu.mmu_secondary_context; | |
176 | break; | |
177 | case 2: /* nucleus */ | |
178 | context = 0; | |
179 | break; | |
180 | case 3: /* reserved */ | |
181 | default: | |
182 | return; | |
183 | } | |
184 | ||
185 | for (i = 0; i < 64; i++) { | |
186 | if (TTE_IS_VALID(tlb[i].tte)) { | |
187 | ||
188 | if (is_demap_context) { | |
189 | /* will remove non-global entries matching context value */ | |
190 | if (TTE_IS_GLOBAL(tlb[i].tte) || | |
191 | !tlb_compare_context(&tlb[i], context)) { | |
192 | continue; | |
193 | } | |
194 | } else { | |
195 | /* demap page | |
196 | will remove any entry matching VA */ | |
197 | mask = 0xffffffffffffe000ULL; | |
198 | mask <<= 3 * ((tlb[i].tte >> 61) & 3); | |
199 | ||
200 | if (!compare_masked(demap_addr, tlb[i].tag, mask)) { | |
201 | continue; | |
202 | } | |
203 | ||
204 | /* entry should be global or matching context value */ | |
205 | if (!TTE_IS_GLOBAL(tlb[i].tte) && | |
206 | !tlb_compare_context(&tlb[i], context)) { | |
207 | continue; | |
208 | } | |
209 | } | |
210 | ||
211 | replace_tlb_entry(&tlb[i], 0, 0, env1); | |
212 | #ifdef DEBUG_MMU | |
213 | DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); | |
214 | dump_mmu(stdout, fprintf, env1); | |
215 | #endif | |
216 | } | |
217 | } | |
218 | } | |
219 | ||
220 | static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, | |
221 | uint64_t tlb_tag, uint64_t tlb_tte, | |
c5f9864e | 222 | const char *strmmu, CPUSPARCState *env1) |
fafd8bce BS |
223 | { |
224 | unsigned int i, replace_used; | |
225 | ||
226 | /* Try replacing invalid entry */ | |
227 | for (i = 0; i < 64; i++) { | |
228 | if (!TTE_IS_VALID(tlb[i].tte)) { | |
229 | replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); | |
230 | #ifdef DEBUG_MMU | |
231 | DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); | |
232 | dump_mmu(stdout, fprintf, env1); | |
233 | #endif | |
234 | return; | |
235 | } | |
236 | } | |
237 | ||
238 | /* All entries are valid, try replacing unlocked entry */ | |
239 | ||
240 | for (replace_used = 0; replace_used < 2; ++replace_used) { | |
241 | ||
242 | /* Used entries are not replaced on first pass */ | |
243 | ||
244 | for (i = 0; i < 64; i++) { | |
245 | if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) { | |
246 | ||
247 | replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); | |
248 | #ifdef DEBUG_MMU | |
249 | DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", | |
250 | strmmu, (replace_used ? "used" : "unused"), i); | |
251 | dump_mmu(stdout, fprintf, env1); | |
252 | #endif | |
253 | return; | |
254 | } | |
255 | } | |
256 | ||
257 | /* Now reset used bit and search for unused entries again */ | |
258 | ||
259 | for (i = 0; i < 64; i++) { | |
260 | TTE_SET_UNUSED(tlb[i].tte); | |
261 | } | |
262 | } | |
263 | ||
264 | #ifdef DEBUG_MMU | |
265 | DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu); | |
266 | #endif | |
267 | /* error state? */ | |
268 | } | |
269 | ||
270 | #endif | |
271 | ||
c5f9864e | 272 | static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr) |
fafd8bce BS |
273 | { |
274 | #ifdef TARGET_SPARC64 | |
275 | if (AM_CHECK(env1)) { | |
276 | addr &= 0xffffffffULL; | |
277 | } | |
278 | #endif | |
279 | return addr; | |
280 | } | |
281 | ||
282 | /* returns true if access using this ASI is to have address translated by MMU | |
283 | otherwise access is to raw physical address */ | |
284 | static inline int is_translating_asi(int asi) | |
285 | { | |
286 | #ifdef TARGET_SPARC64 | |
287 | /* Ultrasparc IIi translating asi | |
288 | - note this list is defined by cpu implementation | |
289 | */ | |
290 | switch (asi) { | |
291 | case 0x04 ... 0x11: | |
292 | case 0x16 ... 0x19: | |
293 | case 0x1E ... 0x1F: | |
294 | case 0x24 ... 0x2C: | |
295 | case 0x70 ... 0x73: | |
296 | case 0x78 ... 0x79: | |
297 | case 0x80 ... 0xFF: | |
298 | return 1; | |
299 | ||
300 | default: | |
301 | return 0; | |
302 | } | |
303 | #else | |
304 | /* TODO: check sparc32 bits */ | |
305 | return 0; | |
306 | #endif | |
307 | } | |
308 | ||
fe8d8f0f | 309 | static inline target_ulong asi_address_mask(CPUSPARCState *env, |
fafd8bce BS |
310 | int asi, target_ulong addr) |
311 | { | |
312 | if (is_translating_asi(asi)) { | |
313 | return address_mask(env, addr); | |
314 | } else { | |
315 | return addr; | |
316 | } | |
317 | } | |
318 | ||
fe8d8f0f | 319 | void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align) |
fafd8bce BS |
320 | { |
321 | if (addr & align) { | |
322 | #ifdef DEBUG_UNALIGNED | |
323 | printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx | |
324 | "\n", addr, env->pc); | |
325 | #endif | |
326 | helper_raise_exception(env, TT_UNALIGNED); | |
327 | } | |
328 | } | |
329 | ||
330 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \ | |
331 | defined(DEBUG_MXCC) | |
c5f9864e | 332 | static void dump_mxcc(CPUSPARCState *env) |
fafd8bce BS |
333 | { |
334 | printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 | |
335 | "\n", | |
336 | env->mxccdata[0], env->mxccdata[1], | |
337 | env->mxccdata[2], env->mxccdata[3]); | |
338 | printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 | |
339 | "\n" | |
340 | " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 | |
341 | "\n", | |
342 | env->mxccregs[0], env->mxccregs[1], | |
343 | env->mxccregs[2], env->mxccregs[3], | |
344 | env->mxccregs[4], env->mxccregs[5], | |
345 | env->mxccregs[6], env->mxccregs[7]); | |
346 | } | |
347 | #endif | |
348 | ||
349 | #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \ | |
350 | && defined(DEBUG_ASI) | |
351 | static void dump_asi(const char *txt, target_ulong addr, int asi, int size, | |
352 | uint64_t r1) | |
353 | { | |
354 | switch (size) { | |
355 | case 1: | |
356 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, | |
357 | addr, asi, r1 & 0xff); | |
358 | break; | |
359 | case 2: | |
360 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, | |
361 | addr, asi, r1 & 0xffff); | |
362 | break; | |
363 | case 4: | |
364 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, | |
365 | addr, asi, r1 & 0xffffffff); | |
366 | break; | |
367 | case 8: | |
368 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, | |
369 | addr, asi, r1); | |
370 | break; | |
371 | } | |
372 | } | |
373 | #endif | |
374 | ||
375 | #ifndef TARGET_SPARC64 | |
376 | #ifndef CONFIG_USER_ONLY | |
377 | ||
378 | ||
379 | /* Leon3 cache control */ | |
380 | ||
fe8d8f0f BS |
381 | static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr, |
382 | uint64_t val, int size) | |
fafd8bce BS |
383 | { |
384 | DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", | |
385 | addr, val, size); | |
386 | ||
387 | if (size != 4) { | |
388 | DPRINTF_CACHE_CONTROL("32bits only\n"); | |
389 | return; | |
390 | } | |
391 | ||
392 | switch (addr) { | |
393 | case 0x00: /* Cache control */ | |
394 | ||
395 | /* These values must always be read as zeros */ | |
396 | val &= ~CACHE_CTRL_FD; | |
397 | val &= ~CACHE_CTRL_FI; | |
398 | val &= ~CACHE_CTRL_IB; | |
399 | val &= ~CACHE_CTRL_IP; | |
400 | val &= ~CACHE_CTRL_DP; | |
401 | ||
402 | env->cache_control = val; | |
403 | break; | |
404 | case 0x04: /* Instruction cache configuration */ | |
405 | case 0x08: /* Data cache configuration */ | |
406 | /* Read Only */ | |
407 | break; | |
408 | default: | |
409 | DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr); | |
410 | break; | |
411 | }; | |
412 | } | |
413 | ||
fe8d8f0f BS |
414 | static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr, |
415 | int size) | |
fafd8bce BS |
416 | { |
417 | uint64_t ret = 0; | |
418 | ||
419 | if (size != 4) { | |
420 | DPRINTF_CACHE_CONTROL("32bits only\n"); | |
421 | return 0; | |
422 | } | |
423 | ||
424 | switch (addr) { | |
425 | case 0x00: /* Cache control */ | |
426 | ret = env->cache_control; | |
427 | break; | |
428 | ||
429 | /* Configuration registers are read and only always keep those | |
430 | predefined values */ | |
431 | ||
432 | case 0x04: /* Instruction cache configuration */ | |
433 | ret = 0x10220000; | |
434 | break; | |
435 | case 0x08: /* Data cache configuration */ | |
436 | ret = 0x18220000; | |
437 | break; | |
438 | default: | |
439 | DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr); | |
440 | break; | |
441 | }; | |
442 | DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", | |
443 | addr, ret, size); | |
444 | return ret; | |
445 | } | |
446 | ||
fe8d8f0f BS |
447 | uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, |
448 | int sign) | |
fafd8bce | 449 | { |
fdfba1a2 | 450 | CPUState *cs = ENV_GET_CPU(env); |
fafd8bce BS |
451 | uint64_t ret = 0; |
452 | #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) | |
453 | uint32_t last_addr = addr; | |
454 | #endif | |
455 | ||
fe8d8f0f | 456 | helper_check_align(env, addr, size - 1); |
fafd8bce BS |
457 | switch (asi) { |
458 | case 2: /* SuperSparc MXCC registers and Leon3 cache control */ | |
459 | switch (addr) { | |
460 | case 0x00: /* Leon3 Cache Control */ | |
461 | case 0x08: /* Leon3 Instruction Cache config */ | |
462 | case 0x0C: /* Leon3 Date Cache config */ | |
463 | if (env->def->features & CPU_FEATURE_CACHE_CTRL) { | |
fe8d8f0f | 464 | ret = leon3_cache_control_ld(env, addr, size); |
fafd8bce BS |
465 | } |
466 | break; | |
467 | case 0x01c00a00: /* MXCC control register */ | |
468 | if (size == 8) { | |
469 | ret = env->mxccregs[3]; | |
470 | } else { | |
71547a3b BS |
471 | qemu_log_mask(LOG_UNIMP, |
472 | "%08x: unimplemented access size: %d\n", addr, | |
473 | size); | |
fafd8bce BS |
474 | } |
475 | break; | |
476 | case 0x01c00a04: /* MXCC control register */ | |
477 | if (size == 4) { | |
478 | ret = env->mxccregs[3]; | |
479 | } else { | |
71547a3b BS |
480 | qemu_log_mask(LOG_UNIMP, |
481 | "%08x: unimplemented access size: %d\n", addr, | |
482 | size); | |
fafd8bce BS |
483 | } |
484 | break; | |
485 | case 0x01c00c00: /* Module reset register */ | |
486 | if (size == 8) { | |
487 | ret = env->mxccregs[5]; | |
488 | /* should we do something here? */ | |
489 | } else { | |
71547a3b BS |
490 | qemu_log_mask(LOG_UNIMP, |
491 | "%08x: unimplemented access size: %d\n", addr, | |
492 | size); | |
fafd8bce BS |
493 | } |
494 | break; | |
495 | case 0x01c00f00: /* MBus port address register */ | |
496 | if (size == 8) { | |
497 | ret = env->mxccregs[7]; | |
498 | } else { | |
71547a3b BS |
499 | qemu_log_mask(LOG_UNIMP, |
500 | "%08x: unimplemented access size: %d\n", addr, | |
501 | size); | |
fafd8bce BS |
502 | } |
503 | break; | |
504 | default: | |
71547a3b BS |
505 | qemu_log_mask(LOG_UNIMP, |
506 | "%08x: unimplemented address, size: %d\n", addr, | |
507 | size); | |
fafd8bce BS |
508 | break; |
509 | } | |
510 | DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " | |
511 | "addr = %08x -> ret = %" PRIx64 "," | |
512 | "addr = %08x\n", asi, size, sign, last_addr, ret, addr); | |
513 | #ifdef DEBUG_MXCC | |
514 | dump_mxcc(env); | |
515 | #endif | |
516 | break; | |
517 | case 3: /* MMU probe */ | |
7a0a9c2c | 518 | case 0x18: /* LEON3 MMU probe */ |
fafd8bce BS |
519 | { |
520 | int mmulev; | |
521 | ||
522 | mmulev = (addr >> 8) & 15; | |
523 | if (mmulev > 4) { | |
524 | ret = 0; | |
525 | } else { | |
526 | ret = mmu_probe(env, addr, mmulev); | |
527 | } | |
528 | DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", | |
529 | addr, mmulev, ret); | |
530 | } | |
531 | break; | |
532 | case 4: /* read MMU regs */ | |
7a0a9c2c | 533 | case 0x19: /* LEON3 read MMU regs */ |
fafd8bce BS |
534 | { |
535 | int reg = (addr >> 8) & 0x1f; | |
536 | ||
537 | ret = env->mmuregs[reg]; | |
538 | if (reg == 3) { /* Fault status cleared on read */ | |
539 | env->mmuregs[3] = 0; | |
540 | } else if (reg == 0x13) { /* Fault status read */ | |
541 | ret = env->mmuregs[3]; | |
542 | } else if (reg == 0x14) { /* Fault address read */ | |
543 | ret = env->mmuregs[4]; | |
544 | } | |
545 | DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); | |
546 | } | |
547 | break; | |
548 | case 5: /* Turbosparc ITLB Diagnostic */ | |
549 | case 6: /* Turbosparc DTLB Diagnostic */ | |
550 | case 7: /* Turbosparc IOTLB Diagnostic */ | |
551 | break; | |
552 | case 9: /* Supervisor code access */ | |
553 | switch (size) { | |
554 | case 1: | |
0184e266 | 555 | ret = cpu_ldub_code(env, addr); |
fafd8bce BS |
556 | break; |
557 | case 2: | |
0184e266 | 558 | ret = cpu_lduw_code(env, addr); |
fafd8bce BS |
559 | break; |
560 | default: | |
561 | case 4: | |
0184e266 | 562 | ret = cpu_ldl_code(env, addr); |
fafd8bce BS |
563 | break; |
564 | case 8: | |
0184e266 | 565 | ret = cpu_ldq_code(env, addr); |
fafd8bce BS |
566 | break; |
567 | } | |
568 | break; | |
569 | case 0xa: /* User data access */ | |
570 | switch (size) { | |
571 | case 1: | |
fe8d8f0f | 572 | ret = cpu_ldub_user(env, addr); |
fafd8bce BS |
573 | break; |
574 | case 2: | |
fe8d8f0f | 575 | ret = cpu_lduw_user(env, addr); |
fafd8bce BS |
576 | break; |
577 | default: | |
578 | case 4: | |
fe8d8f0f | 579 | ret = cpu_ldl_user(env, addr); |
fafd8bce BS |
580 | break; |
581 | case 8: | |
fe8d8f0f | 582 | ret = cpu_ldq_user(env, addr); |
fafd8bce BS |
583 | break; |
584 | } | |
585 | break; | |
586 | case 0xb: /* Supervisor data access */ | |
587 | switch (size) { | |
588 | case 1: | |
fe8d8f0f | 589 | ret = cpu_ldub_kernel(env, addr); |
fafd8bce BS |
590 | break; |
591 | case 2: | |
fe8d8f0f | 592 | ret = cpu_lduw_kernel(env, addr); |
fafd8bce BS |
593 | break; |
594 | default: | |
595 | case 4: | |
fe8d8f0f | 596 | ret = cpu_ldl_kernel(env, addr); |
fafd8bce BS |
597 | break; |
598 | case 8: | |
fe8d8f0f | 599 | ret = cpu_ldq_kernel(env, addr); |
fafd8bce BS |
600 | break; |
601 | } | |
602 | break; | |
603 | case 0xc: /* I-cache tag */ | |
604 | case 0xd: /* I-cache data */ | |
605 | case 0xe: /* D-cache tag */ | |
606 | case 0xf: /* D-cache data */ | |
607 | break; | |
608 | case 0x20: /* MMU passthrough */ | |
7a0a9c2c | 609 | case 0x1c: /* LEON MMU passthrough */ |
fafd8bce BS |
610 | switch (size) { |
611 | case 1: | |
612 | ret = ldub_phys(addr); | |
613 | break; | |
614 | case 2: | |
615 | ret = lduw_phys(addr); | |
616 | break; | |
617 | default: | |
618 | case 4: | |
fdfba1a2 | 619 | ret = ldl_phys(cs->as, addr); |
fafd8bce BS |
620 | break; |
621 | case 8: | |
622 | ret = ldq_phys(addr); | |
623 | break; | |
624 | } | |
625 | break; | |
626 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ | |
627 | switch (size) { | |
628 | case 1: | |
a8170e5e AK |
629 | ret = ldub_phys((hwaddr)addr |
630 | | ((hwaddr)(asi & 0xf) << 32)); | |
fafd8bce BS |
631 | break; |
632 | case 2: | |
a8170e5e AK |
633 | ret = lduw_phys((hwaddr)addr |
634 | | ((hwaddr)(asi & 0xf) << 32)); | |
fafd8bce BS |
635 | break; |
636 | default: | |
637 | case 4: | |
fdfba1a2 | 638 | ret = ldl_phys(cs->as, (hwaddr)addr |
a8170e5e | 639 | | ((hwaddr)(asi & 0xf) << 32)); |
fafd8bce BS |
640 | break; |
641 | case 8: | |
a8170e5e AK |
642 | ret = ldq_phys((hwaddr)addr |
643 | | ((hwaddr)(asi & 0xf) << 32)); | |
fafd8bce BS |
644 | break; |
645 | } | |
646 | break; | |
647 | case 0x30: /* Turbosparc secondary cache diagnostic */ | |
648 | case 0x31: /* Turbosparc RAM snoop */ | |
649 | case 0x32: /* Turbosparc page table descriptor diagnostic */ | |
650 | case 0x39: /* data cache diagnostic register */ | |
651 | ret = 0; | |
652 | break; | |
653 | case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ | |
654 | { | |
655 | int reg = (addr >> 8) & 3; | |
656 | ||
657 | switch (reg) { | |
658 | case 0: /* Breakpoint Value (Addr) */ | |
659 | ret = env->mmubpregs[reg]; | |
660 | break; | |
661 | case 1: /* Breakpoint Mask */ | |
662 | ret = env->mmubpregs[reg]; | |
663 | break; | |
664 | case 2: /* Breakpoint Control */ | |
665 | ret = env->mmubpregs[reg]; | |
666 | break; | |
667 | case 3: /* Breakpoint Status */ | |
668 | ret = env->mmubpregs[reg]; | |
669 | env->mmubpregs[reg] = 0ULL; | |
670 | break; | |
671 | } | |
672 | DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, | |
673 | ret); | |
674 | } | |
675 | break; | |
676 | case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ | |
677 | ret = env->mmubpctrv; | |
678 | break; | |
679 | case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ | |
680 | ret = env->mmubpctrc; | |
681 | break; | |
682 | case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ | |
683 | ret = env->mmubpctrs; | |
684 | break; | |
685 | case 0x4c: /* SuperSPARC MMU Breakpoint Action */ | |
686 | ret = env->mmubpaction; | |
687 | break; | |
688 | case 8: /* User code access, XXX */ | |
689 | default: | |
c658b94f AF |
690 | cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), |
691 | addr, false, false, asi, size); | |
fafd8bce BS |
692 | ret = 0; |
693 | break; | |
694 | } | |
695 | if (sign) { | |
696 | switch (size) { | |
697 | case 1: | |
698 | ret = (int8_t) ret; | |
699 | break; | |
700 | case 2: | |
701 | ret = (int16_t) ret; | |
702 | break; | |
703 | case 4: | |
704 | ret = (int32_t) ret; | |
705 | break; | |
706 | default: | |
707 | break; | |
708 | } | |
709 | } | |
710 | #ifdef DEBUG_ASI | |
711 | dump_asi("read ", last_addr, asi, size, ret); | |
712 | #endif | |
713 | return ret; | |
714 | } | |
715 | ||
fe8d8f0f BS |
716 | void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, |
717 | int size) | |
fafd8bce | 718 | { |
fe8d8f0f | 719 | helper_check_align(env, addr, size - 1); |
fafd8bce BS |
720 | switch (asi) { |
721 | case 2: /* SuperSparc MXCC registers and Leon3 cache control */ | |
722 | switch (addr) { | |
723 | case 0x00: /* Leon3 Cache Control */ | |
724 | case 0x08: /* Leon3 Instruction Cache config */ | |
725 | case 0x0C: /* Leon3 Date Cache config */ | |
726 | if (env->def->features & CPU_FEATURE_CACHE_CTRL) { | |
fe8d8f0f | 727 | leon3_cache_control_st(env, addr, val, size); |
fafd8bce BS |
728 | } |
729 | break; | |
730 | ||
731 | case 0x01c00000: /* MXCC stream data register 0 */ | |
732 | if (size == 8) { | |
733 | env->mxccdata[0] = val; | |
734 | } else { | |
71547a3b BS |
735 | qemu_log_mask(LOG_UNIMP, |
736 | "%08x: unimplemented access size: %d\n", addr, | |
737 | size); | |
fafd8bce BS |
738 | } |
739 | break; | |
740 | case 0x01c00008: /* MXCC stream data register 1 */ | |
741 | if (size == 8) { | |
742 | env->mxccdata[1] = val; | |
743 | } else { | |
71547a3b BS |
744 | qemu_log_mask(LOG_UNIMP, |
745 | "%08x: unimplemented access size: %d\n", addr, | |
746 | size); | |
fafd8bce BS |
747 | } |
748 | break; | |
749 | case 0x01c00010: /* MXCC stream data register 2 */ | |
750 | if (size == 8) { | |
751 | env->mxccdata[2] = val; | |
752 | } else { | |
71547a3b BS |
753 | qemu_log_mask(LOG_UNIMP, |
754 | "%08x: unimplemented access size: %d\n", addr, | |
755 | size); | |
fafd8bce BS |
756 | } |
757 | break; | |
758 | case 0x01c00018: /* MXCC stream data register 3 */ | |
759 | if (size == 8) { | |
760 | env->mxccdata[3] = val; | |
761 | } else { | |
71547a3b BS |
762 | qemu_log_mask(LOG_UNIMP, |
763 | "%08x: unimplemented access size: %d\n", addr, | |
764 | size); | |
fafd8bce BS |
765 | } |
766 | break; | |
767 | case 0x01c00100: /* MXCC stream source */ | |
768 | if (size == 8) { | |
769 | env->mxccregs[0] = val; | |
770 | } else { | |
71547a3b BS |
771 | qemu_log_mask(LOG_UNIMP, |
772 | "%08x: unimplemented access size: %d\n", addr, | |
773 | size); | |
fafd8bce BS |
774 | } |
775 | env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + | |
776 | 0); | |
777 | env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + | |
778 | 8); | |
779 | env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + | |
780 | 16); | |
781 | env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + | |
782 | 24); | |
783 | break; | |
784 | case 0x01c00200: /* MXCC stream destination */ | |
785 | if (size == 8) { | |
786 | env->mxccregs[1] = val; | |
787 | } else { | |
71547a3b BS |
788 | qemu_log_mask(LOG_UNIMP, |
789 | "%08x: unimplemented access size: %d\n", addr, | |
790 | size); | |
fafd8bce BS |
791 | } |
792 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, | |
793 | env->mxccdata[0]); | |
794 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, | |
795 | env->mxccdata[1]); | |
796 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, | |
797 | env->mxccdata[2]); | |
798 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, | |
799 | env->mxccdata[3]); | |
800 | break; | |
801 | case 0x01c00a00: /* MXCC control register */ | |
802 | if (size == 8) { | |
803 | env->mxccregs[3] = val; | |
804 | } else { | |
71547a3b BS |
805 | qemu_log_mask(LOG_UNIMP, |
806 | "%08x: unimplemented access size: %d\n", addr, | |
807 | size); | |
fafd8bce BS |
808 | } |
809 | break; | |
810 | case 0x01c00a04: /* MXCC control register */ | |
811 | if (size == 4) { | |
812 | env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) | |
813 | | val; | |
814 | } else { | |
71547a3b BS |
815 | qemu_log_mask(LOG_UNIMP, |
816 | "%08x: unimplemented access size: %d\n", addr, | |
817 | size); | |
fafd8bce BS |
818 | } |
819 | break; | |
820 | case 0x01c00e00: /* MXCC error register */ | |
821 | /* writing a 1 bit clears the error */ | |
822 | if (size == 8) { | |
823 | env->mxccregs[6] &= ~val; | |
824 | } else { | |
71547a3b BS |
825 | qemu_log_mask(LOG_UNIMP, |
826 | "%08x: unimplemented access size: %d\n", addr, | |
827 | size); | |
fafd8bce BS |
828 | } |
829 | break; | |
830 | case 0x01c00f00: /* MBus port address register */ | |
831 | if (size == 8) { | |
832 | env->mxccregs[7] = val; | |
833 | } else { | |
71547a3b BS |
834 | qemu_log_mask(LOG_UNIMP, |
835 | "%08x: unimplemented access size: %d\n", addr, | |
836 | size); | |
fafd8bce BS |
837 | } |
838 | break; | |
839 | default: | |
71547a3b BS |
840 | qemu_log_mask(LOG_UNIMP, |
841 | "%08x: unimplemented address, size: %d\n", addr, | |
842 | size); | |
fafd8bce BS |
843 | break; |
844 | } | |
845 | DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", | |
846 | asi, size, addr, val); | |
847 | #ifdef DEBUG_MXCC | |
848 | dump_mxcc(env); | |
849 | #endif | |
850 | break; | |
851 | case 3: /* MMU flush */ | |
7a0a9c2c | 852 | case 0x18: /* LEON3 MMU flush */ |
fafd8bce BS |
853 | { |
854 | int mmulev; | |
855 | ||
856 | mmulev = (addr >> 8) & 15; | |
857 | DPRINTF_MMU("mmu flush level %d\n", mmulev); | |
858 | switch (mmulev) { | |
859 | case 0: /* flush page */ | |
860 | tlb_flush_page(env, addr & 0xfffff000); | |
861 | break; | |
862 | case 1: /* flush segment (256k) */ | |
863 | case 2: /* flush region (16M) */ | |
864 | case 3: /* flush context (4G) */ | |
865 | case 4: /* flush entire */ | |
866 | tlb_flush(env, 1); | |
867 | break; | |
868 | default: | |
869 | break; | |
870 | } | |
871 | #ifdef DEBUG_MMU | |
872 | dump_mmu(stdout, fprintf, env); | |
873 | #endif | |
874 | } | |
875 | break; | |
876 | case 4: /* write MMU regs */ | |
7a0a9c2c | 877 | case 0x19: /* LEON3 write MMU regs */ |
fafd8bce BS |
878 | { |
879 | int reg = (addr >> 8) & 0x1f; | |
880 | uint32_t oldreg; | |
881 | ||
882 | oldreg = env->mmuregs[reg]; | |
883 | switch (reg) { | |
884 | case 0: /* Control Register */ | |
885 | env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | | |
886 | (val & 0x00ffffff); | |
887 | /* Mappings generated during no-fault mode or MMU | |
888 | disabled mode are invalid in normal mode */ | |
889 | if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) != | |
890 | (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) { | |
891 | tlb_flush(env, 1); | |
892 | } | |
893 | break; | |
894 | case 1: /* Context Table Pointer Register */ | |
895 | env->mmuregs[reg] = val & env->def->mmu_ctpr_mask; | |
896 | break; | |
897 | case 2: /* Context Register */ | |
898 | env->mmuregs[reg] = val & env->def->mmu_cxr_mask; | |
899 | if (oldreg != env->mmuregs[reg]) { | |
900 | /* we flush when the MMU context changes because | |
901 | QEMU has no MMU context support */ | |
902 | tlb_flush(env, 1); | |
903 | } | |
904 | break; | |
905 | case 3: /* Synchronous Fault Status Register with Clear */ | |
906 | case 4: /* Synchronous Fault Address Register */ | |
907 | break; | |
908 | case 0x10: /* TLB Replacement Control Register */ | |
909 | env->mmuregs[reg] = val & env->def->mmu_trcr_mask; | |
910 | break; | |
911 | case 0x13: /* Synchronous Fault Status Register with Read | |
912 | and Clear */ | |
913 | env->mmuregs[3] = val & env->def->mmu_sfsr_mask; | |
914 | break; | |
915 | case 0x14: /* Synchronous Fault Address Register */ | |
916 | env->mmuregs[4] = val; | |
917 | break; | |
918 | default: | |
919 | env->mmuregs[reg] = val; | |
920 | break; | |
921 | } | |
922 | if (oldreg != env->mmuregs[reg]) { | |
923 | DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", | |
924 | reg, oldreg, env->mmuregs[reg]); | |
925 | } | |
926 | #ifdef DEBUG_MMU | |
927 | dump_mmu(stdout, fprintf, env); | |
928 | #endif | |
929 | } | |
930 | break; | |
931 | case 5: /* Turbosparc ITLB Diagnostic */ | |
932 | case 6: /* Turbosparc DTLB Diagnostic */ | |
933 | case 7: /* Turbosparc IOTLB Diagnostic */ | |
934 | break; | |
935 | case 0xa: /* User data access */ | |
936 | switch (size) { | |
937 | case 1: | |
fe8d8f0f | 938 | cpu_stb_user(env, addr, val); |
fafd8bce BS |
939 | break; |
940 | case 2: | |
fe8d8f0f | 941 | cpu_stw_user(env, addr, val); |
fafd8bce BS |
942 | break; |
943 | default: | |
944 | case 4: | |
fe8d8f0f | 945 | cpu_stl_user(env, addr, val); |
fafd8bce BS |
946 | break; |
947 | case 8: | |
fe8d8f0f | 948 | cpu_stq_user(env, addr, val); |
fafd8bce BS |
949 | break; |
950 | } | |
951 | break; | |
952 | case 0xb: /* Supervisor data access */ | |
953 | switch (size) { | |
954 | case 1: | |
fe8d8f0f | 955 | cpu_stb_kernel(env, addr, val); |
fafd8bce BS |
956 | break; |
957 | case 2: | |
fe8d8f0f | 958 | cpu_stw_kernel(env, addr, val); |
fafd8bce BS |
959 | break; |
960 | default: | |
961 | case 4: | |
fe8d8f0f | 962 | cpu_stl_kernel(env, addr, val); |
fafd8bce BS |
963 | break; |
964 | case 8: | |
fe8d8f0f | 965 | cpu_stq_kernel(env, addr, val); |
fafd8bce BS |
966 | break; |
967 | } | |
968 | break; | |
969 | case 0xc: /* I-cache tag */ | |
970 | case 0xd: /* I-cache data */ | |
971 | case 0xe: /* D-cache tag */ | |
972 | case 0xf: /* D-cache data */ | |
973 | case 0x10: /* I/D-cache flush page */ | |
974 | case 0x11: /* I/D-cache flush segment */ | |
975 | case 0x12: /* I/D-cache flush region */ | |
976 | case 0x13: /* I/D-cache flush context */ | |
977 | case 0x14: /* I/D-cache flush user */ | |
978 | break; | |
979 | case 0x17: /* Block copy, sta access */ | |
980 | { | |
981 | /* val = src | |
982 | addr = dst | |
983 | copy 32 bytes */ | |
984 | unsigned int i; | |
985 | uint32_t src = val & ~3, dst = addr & ~3, temp; | |
986 | ||
987 | for (i = 0; i < 32; i += 4, src += 4, dst += 4) { | |
fe8d8f0f BS |
988 | temp = cpu_ldl_kernel(env, src); |
989 | cpu_stl_kernel(env, dst, temp); | |
fafd8bce BS |
990 | } |
991 | } | |
992 | break; | |
993 | case 0x1f: /* Block fill, stda access */ | |
994 | { | |
995 | /* addr = dst | |
996 | fill 32 bytes with val */ | |
997 | unsigned int i; | |
998 | uint32_t dst = addr & 7; | |
999 | ||
1000 | for (i = 0; i < 32; i += 8, dst += 8) { | |
fe8d8f0f | 1001 | cpu_stq_kernel(env, dst, val); |
fafd8bce BS |
1002 | } |
1003 | } | |
1004 | break; | |
1005 | case 0x20: /* MMU passthrough */ | |
7a0a9c2c | 1006 | case 0x1c: /* LEON MMU passthrough */ |
fafd8bce BS |
1007 | { |
1008 | switch (size) { | |
1009 | case 1: | |
1010 | stb_phys(addr, val); | |
1011 | break; | |
1012 | case 2: | |
1013 | stw_phys(addr, val); | |
1014 | break; | |
1015 | case 4: | |
1016 | default: | |
1017 | stl_phys(addr, val); | |
1018 | break; | |
1019 | case 8: | |
1020 | stq_phys(addr, val); | |
1021 | break; | |
1022 | } | |
1023 | } | |
1024 | break; | |
1025 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ | |
1026 | { | |
1027 | switch (size) { | |
1028 | case 1: | |
a8170e5e AK |
1029 | stb_phys((hwaddr)addr |
1030 | | ((hwaddr)(asi & 0xf) << 32), val); | |
fafd8bce BS |
1031 | break; |
1032 | case 2: | |
a8170e5e AK |
1033 | stw_phys((hwaddr)addr |
1034 | | ((hwaddr)(asi & 0xf) << 32), val); | |
fafd8bce BS |
1035 | break; |
1036 | case 4: | |
1037 | default: | |
a8170e5e AK |
1038 | stl_phys((hwaddr)addr |
1039 | | ((hwaddr)(asi & 0xf) << 32), val); | |
fafd8bce BS |
1040 | break; |
1041 | case 8: | |
a8170e5e AK |
1042 | stq_phys((hwaddr)addr |
1043 | | ((hwaddr)(asi & 0xf) << 32), val); | |
fafd8bce BS |
1044 | break; |
1045 | } | |
1046 | } | |
1047 | break; | |
1048 | case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ | |
1049 | case 0x31: /* store buffer data, Ross RT620 I-cache flush or | |
1050 | Turbosparc snoop RAM */ | |
1051 | case 0x32: /* store buffer control or Turbosparc page table | |
1052 | descriptor diagnostic */ | |
1053 | case 0x36: /* I-cache flash clear */ | |
1054 | case 0x37: /* D-cache flash clear */ | |
1055 | break; | |
1056 | case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ | |
1057 | { | |
1058 | int reg = (addr >> 8) & 3; | |
1059 | ||
1060 | switch (reg) { | |
1061 | case 0: /* Breakpoint Value (Addr) */ | |
1062 | env->mmubpregs[reg] = (val & 0xfffffffffULL); | |
1063 | break; | |
1064 | case 1: /* Breakpoint Mask */ | |
1065 | env->mmubpregs[reg] = (val & 0xfffffffffULL); | |
1066 | break; | |
1067 | case 2: /* Breakpoint Control */ | |
1068 | env->mmubpregs[reg] = (val & 0x7fULL); | |
1069 | break; | |
1070 | case 3: /* Breakpoint Status */ | |
1071 | env->mmubpregs[reg] = (val & 0xfULL); | |
1072 | break; | |
1073 | } | |
1074 | DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg, | |
1075 | env->mmuregs[reg]); | |
1076 | } | |
1077 | break; | |
1078 | case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ | |
1079 | env->mmubpctrv = val & 0xffffffff; | |
1080 | break; | |
1081 | case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ | |
1082 | env->mmubpctrc = val & 0x3; | |
1083 | break; | |
1084 | case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ | |
1085 | env->mmubpctrs = val & 0x3; | |
1086 | break; | |
1087 | case 0x4c: /* SuperSPARC MMU Breakpoint Action */ | |
1088 | env->mmubpaction = val & 0x1fff; | |
1089 | break; | |
1090 | case 8: /* User code access, XXX */ | |
1091 | case 9: /* Supervisor code access, XXX */ | |
1092 | default: | |
c658b94f AF |
1093 | cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), |
1094 | addr, true, false, asi, size); | |
fafd8bce BS |
1095 | break; |
1096 | } | |
1097 | #ifdef DEBUG_ASI | |
1098 | dump_asi("write", addr, asi, size, val); | |
1099 | #endif | |
1100 | } | |
1101 | ||
1102 | #endif /* CONFIG_USER_ONLY */ | |
1103 | #else /* TARGET_SPARC64 */ | |
1104 | ||
1105 | #ifdef CONFIG_USER_ONLY | |
fe8d8f0f BS |
1106 | uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, |
1107 | int sign) | |
fafd8bce BS |
1108 | { |
1109 | uint64_t ret = 0; | |
1110 | #if defined(DEBUG_ASI) | |
1111 | target_ulong last_addr = addr; | |
1112 | #endif | |
1113 | ||
1114 | if (asi < 0x80) { | |
1115 | helper_raise_exception(env, TT_PRIV_ACT); | |
1116 | } | |
1117 | ||
fe8d8f0f | 1118 | helper_check_align(env, addr, size - 1); |
fafd8bce BS |
1119 | addr = asi_address_mask(env, asi, addr); |
1120 | ||
1121 | switch (asi) { | |
1122 | case 0x82: /* Primary no-fault */ | |
1123 | case 0x8a: /* Primary no-fault LE */ | |
1124 | if (page_check_range(addr, size, PAGE_READ) == -1) { | |
1125 | #ifdef DEBUG_ASI | |
1126 | dump_asi("read ", last_addr, asi, size, ret); | |
1127 | #endif | |
1128 | return 0; | |
1129 | } | |
1130 | /* Fall through */ | |
1131 | case 0x80: /* Primary */ | |
1132 | case 0x88: /* Primary LE */ | |
1133 | { | |
1134 | switch (size) { | |
1135 | case 1: | |
1136 | ret = ldub_raw(addr); | |
1137 | break; | |
1138 | case 2: | |
1139 | ret = lduw_raw(addr); | |
1140 | break; | |
1141 | case 4: | |
1142 | ret = ldl_raw(addr); | |
1143 | break; | |
1144 | default: | |
1145 | case 8: | |
1146 | ret = ldq_raw(addr); | |
1147 | break; | |
1148 | } | |
1149 | } | |
1150 | break; | |
1151 | case 0x83: /* Secondary no-fault */ | |
1152 | case 0x8b: /* Secondary no-fault LE */ | |
1153 | if (page_check_range(addr, size, PAGE_READ) == -1) { | |
1154 | #ifdef DEBUG_ASI | |
1155 | dump_asi("read ", last_addr, asi, size, ret); | |
1156 | #endif | |
1157 | return 0; | |
1158 | } | |
1159 | /* Fall through */ | |
1160 | case 0x81: /* Secondary */ | |
1161 | case 0x89: /* Secondary LE */ | |
1162 | /* XXX */ | |
1163 | break; | |
1164 | default: | |
1165 | break; | |
1166 | } | |
1167 | ||
1168 | /* Convert from little endian */ | |
1169 | switch (asi) { | |
1170 | case 0x88: /* Primary LE */ | |
1171 | case 0x89: /* Secondary LE */ | |
1172 | case 0x8a: /* Primary no-fault LE */ | |
1173 | case 0x8b: /* Secondary no-fault LE */ | |
1174 | switch (size) { | |
1175 | case 2: | |
1176 | ret = bswap16(ret); | |
1177 | break; | |
1178 | case 4: | |
1179 | ret = bswap32(ret); | |
1180 | break; | |
1181 | case 8: | |
1182 | ret = bswap64(ret); | |
1183 | break; | |
1184 | default: | |
1185 | break; | |
1186 | } | |
1187 | default: | |
1188 | break; | |
1189 | } | |
1190 | ||
1191 | /* Convert to signed number */ | |
1192 | if (sign) { | |
1193 | switch (size) { | |
1194 | case 1: | |
1195 | ret = (int8_t) ret; | |
1196 | break; | |
1197 | case 2: | |
1198 | ret = (int16_t) ret; | |
1199 | break; | |
1200 | case 4: | |
1201 | ret = (int32_t) ret; | |
1202 | break; | |
1203 | default: | |
1204 | break; | |
1205 | } | |
1206 | } | |
1207 | #ifdef DEBUG_ASI | |
1208 | dump_asi("read ", last_addr, asi, size, ret); | |
1209 | #endif | |
1210 | return ret; | |
1211 | } | |
1212 | ||
fe8d8f0f BS |
1213 | void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, |
1214 | int asi, int size) | |
fafd8bce BS |
1215 | { |
1216 | #ifdef DEBUG_ASI | |
1217 | dump_asi("write", addr, asi, size, val); | |
1218 | #endif | |
1219 | if (asi < 0x80) { | |
1220 | helper_raise_exception(env, TT_PRIV_ACT); | |
1221 | } | |
1222 | ||
fe8d8f0f | 1223 | helper_check_align(env, addr, size - 1); |
fafd8bce BS |
1224 | addr = asi_address_mask(env, asi, addr); |
1225 | ||
1226 | /* Convert to little endian */ | |
1227 | switch (asi) { | |
1228 | case 0x88: /* Primary LE */ | |
1229 | case 0x89: /* Secondary LE */ | |
1230 | switch (size) { | |
1231 | case 2: | |
1232 | val = bswap16(val); | |
1233 | break; | |
1234 | case 4: | |
1235 | val = bswap32(val); | |
1236 | break; | |
1237 | case 8: | |
1238 | val = bswap64(val); | |
1239 | break; | |
1240 | default: | |
1241 | break; | |
1242 | } | |
1243 | default: | |
1244 | break; | |
1245 | } | |
1246 | ||
1247 | switch (asi) { | |
1248 | case 0x80: /* Primary */ | |
1249 | case 0x88: /* Primary LE */ | |
1250 | { | |
1251 | switch (size) { | |
1252 | case 1: | |
1253 | stb_raw(addr, val); | |
1254 | break; | |
1255 | case 2: | |
1256 | stw_raw(addr, val); | |
1257 | break; | |
1258 | case 4: | |
1259 | stl_raw(addr, val); | |
1260 | break; | |
1261 | case 8: | |
1262 | default: | |
1263 | stq_raw(addr, val); | |
1264 | break; | |
1265 | } | |
1266 | } | |
1267 | break; | |
1268 | case 0x81: /* Secondary */ | |
1269 | case 0x89: /* Secondary LE */ | |
1270 | /* XXX */ | |
1271 | return; | |
1272 | ||
1273 | case 0x82: /* Primary no-fault, RO */ | |
1274 | case 0x83: /* Secondary no-fault, RO */ | |
1275 | case 0x8a: /* Primary no-fault LE, RO */ | |
1276 | case 0x8b: /* Secondary no-fault LE, RO */ | |
1277 | default: | |
fe8d8f0f | 1278 | helper_raise_exception(env, TT_DATA_ACCESS); |
fafd8bce BS |
1279 | return; |
1280 | } | |
1281 | } | |
1282 | ||
1283 | #else /* CONFIG_USER_ONLY */ | |
1284 | ||
fe8d8f0f BS |
1285 | uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, |
1286 | int sign) | |
fafd8bce | 1287 | { |
fdfba1a2 | 1288 | CPUState *cs = ENV_GET_CPU(env); |
fafd8bce BS |
1289 | uint64_t ret = 0; |
1290 | #if defined(DEBUG_ASI) | |
1291 | target_ulong last_addr = addr; | |
1292 | #endif | |
1293 | ||
1294 | asi &= 0xff; | |
1295 | ||
1296 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) | |
1297 | || (cpu_has_hypervisor(env) | |
1298 | && asi >= 0x30 && asi < 0x80 | |
1299 | && !(env->hpstate & HS_PRIV))) { | |
1300 | helper_raise_exception(env, TT_PRIV_ACT); | |
1301 | } | |
1302 | ||
fe8d8f0f | 1303 | helper_check_align(env, addr, size - 1); |
fafd8bce BS |
1304 | addr = asi_address_mask(env, asi, addr); |
1305 | ||
1306 | /* process nonfaulting loads first */ | |
1307 | if ((asi & 0xf6) == 0x82) { | |
1308 | int mmu_idx; | |
1309 | ||
1310 | /* secondary space access has lowest asi bit equal to 1 */ | |
1311 | if (env->pstate & PS_PRIV) { | |
1312 | mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX; | |
1313 | } else { | |
1314 | mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX; | |
1315 | } | |
1316 | ||
1317 | if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) { | |
1318 | #ifdef DEBUG_ASI | |
1319 | dump_asi("read ", last_addr, asi, size, ret); | |
1320 | #endif | |
1321 | /* env->exception_index is set in get_physical_address_data(). */ | |
1322 | helper_raise_exception(env, env->exception_index); | |
1323 | } | |
1324 | ||
1325 | /* convert nonfaulting load ASIs to normal load ASIs */ | |
1326 | asi &= ~0x02; | |
1327 | } | |
1328 | ||
1329 | switch (asi) { | |
1330 | case 0x10: /* As if user primary */ | |
1331 | case 0x11: /* As if user secondary */ | |
1332 | case 0x18: /* As if user primary LE */ | |
1333 | case 0x19: /* As if user secondary LE */ | |
1334 | case 0x80: /* Primary */ | |
1335 | case 0x81: /* Secondary */ | |
1336 | case 0x88: /* Primary LE */ | |
1337 | case 0x89: /* Secondary LE */ | |
1338 | case 0xe2: /* UA2007 Primary block init */ | |
1339 | case 0xe3: /* UA2007 Secondary block init */ | |
1340 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { | |
1341 | if (cpu_hypervisor_mode(env)) { | |
1342 | switch (size) { | |
1343 | case 1: | |
fe8d8f0f | 1344 | ret = cpu_ldub_hypv(env, addr); |
fafd8bce BS |
1345 | break; |
1346 | case 2: | |
fe8d8f0f | 1347 | ret = cpu_lduw_hypv(env, addr); |
fafd8bce BS |
1348 | break; |
1349 | case 4: | |
fe8d8f0f | 1350 | ret = cpu_ldl_hypv(env, addr); |
fafd8bce BS |
1351 | break; |
1352 | default: | |
1353 | case 8: | |
fe8d8f0f | 1354 | ret = cpu_ldq_hypv(env, addr); |
fafd8bce BS |
1355 | break; |
1356 | } | |
1357 | } else { | |
1358 | /* secondary space access has lowest asi bit equal to 1 */ | |
1359 | if (asi & 1) { | |
1360 | switch (size) { | |
1361 | case 1: | |
fe8d8f0f | 1362 | ret = cpu_ldub_kernel_secondary(env, addr); |
fafd8bce BS |
1363 | break; |
1364 | case 2: | |
fe8d8f0f | 1365 | ret = cpu_lduw_kernel_secondary(env, addr); |
fafd8bce BS |
1366 | break; |
1367 | case 4: | |
fe8d8f0f | 1368 | ret = cpu_ldl_kernel_secondary(env, addr); |
fafd8bce BS |
1369 | break; |
1370 | default: | |
1371 | case 8: | |
fe8d8f0f | 1372 | ret = cpu_ldq_kernel_secondary(env, addr); |
fafd8bce BS |
1373 | break; |
1374 | } | |
1375 | } else { | |
1376 | switch (size) { | |
1377 | case 1: | |
fe8d8f0f | 1378 | ret = cpu_ldub_kernel(env, addr); |
fafd8bce BS |
1379 | break; |
1380 | case 2: | |
fe8d8f0f | 1381 | ret = cpu_lduw_kernel(env, addr); |
fafd8bce BS |
1382 | break; |
1383 | case 4: | |
fe8d8f0f | 1384 | ret = cpu_ldl_kernel(env, addr); |
fafd8bce BS |
1385 | break; |
1386 | default: | |
1387 | case 8: | |
fe8d8f0f | 1388 | ret = cpu_ldq_kernel(env, addr); |
fafd8bce BS |
1389 | break; |
1390 | } | |
1391 | } | |
1392 | } | |
1393 | } else { | |
1394 | /* secondary space access has lowest asi bit equal to 1 */ | |
1395 | if (asi & 1) { | |
1396 | switch (size) { | |
1397 | case 1: | |
fe8d8f0f | 1398 | ret = cpu_ldub_user_secondary(env, addr); |
fafd8bce BS |
1399 | break; |
1400 | case 2: | |
fe8d8f0f | 1401 | ret = cpu_lduw_user_secondary(env, addr); |
fafd8bce BS |
1402 | break; |
1403 | case 4: | |
fe8d8f0f | 1404 | ret = cpu_ldl_user_secondary(env, addr); |
fafd8bce BS |
1405 | break; |
1406 | default: | |
1407 | case 8: | |
fe8d8f0f | 1408 | ret = cpu_ldq_user_secondary(env, addr); |
fafd8bce BS |
1409 | break; |
1410 | } | |
1411 | } else { | |
1412 | switch (size) { | |
1413 | case 1: | |
fe8d8f0f | 1414 | ret = cpu_ldub_user(env, addr); |
fafd8bce BS |
1415 | break; |
1416 | case 2: | |
fe8d8f0f | 1417 | ret = cpu_lduw_user(env, addr); |
fafd8bce BS |
1418 | break; |
1419 | case 4: | |
fe8d8f0f | 1420 | ret = cpu_ldl_user(env, addr); |
fafd8bce BS |
1421 | break; |
1422 | default: | |
1423 | case 8: | |
fe8d8f0f | 1424 | ret = cpu_ldq_user(env, addr); |
fafd8bce BS |
1425 | break; |
1426 | } | |
1427 | } | |
1428 | } | |
1429 | break; | |
1430 | case 0x14: /* Bypass */ | |
1431 | case 0x15: /* Bypass, non-cacheable */ | |
1432 | case 0x1c: /* Bypass LE */ | |
1433 | case 0x1d: /* Bypass, non-cacheable LE */ | |
1434 | { | |
1435 | switch (size) { | |
1436 | case 1: | |
1437 | ret = ldub_phys(addr); | |
1438 | break; | |
1439 | case 2: | |
1440 | ret = lduw_phys(addr); | |
1441 | break; | |
1442 | case 4: | |
fdfba1a2 | 1443 | ret = ldl_phys(cs->as, addr); |
fafd8bce BS |
1444 | break; |
1445 | default: | |
1446 | case 8: | |
1447 | ret = ldq_phys(addr); | |
1448 | break; | |
1449 | } | |
1450 | break; | |
1451 | } | |
1452 | case 0x24: /* Nucleus quad LDD 128 bit atomic */ | |
1453 | case 0x2c: /* Nucleus quad LDD 128 bit atomic LE | |
1454 | Only ldda allowed */ | |
1455 | helper_raise_exception(env, TT_ILL_INSN); | |
1456 | return 0; | |
1457 | case 0x04: /* Nucleus */ | |
1458 | case 0x0c: /* Nucleus Little Endian (LE) */ | |
1459 | { | |
1460 | switch (size) { | |
1461 | case 1: | |
fe8d8f0f | 1462 | ret = cpu_ldub_nucleus(env, addr); |
fafd8bce BS |
1463 | break; |
1464 | case 2: | |
fe8d8f0f | 1465 | ret = cpu_lduw_nucleus(env, addr); |
fafd8bce BS |
1466 | break; |
1467 | case 4: | |
fe8d8f0f | 1468 | ret = cpu_ldl_nucleus(env, addr); |
fafd8bce BS |
1469 | break; |
1470 | default: | |
1471 | case 8: | |
fe8d8f0f | 1472 | ret = cpu_ldq_nucleus(env, addr); |
fafd8bce BS |
1473 | break; |
1474 | } | |
1475 | break; | |
1476 | } | |
1477 | case 0x4a: /* UPA config */ | |
1478 | /* XXX */ | |
1479 | break; | |
1480 | case 0x45: /* LSU */ | |
1481 | ret = env->lsu; | |
1482 | break; | |
1483 | case 0x50: /* I-MMU regs */ | |
1484 | { | |
1485 | int reg = (addr >> 3) & 0xf; | |
1486 | ||
1487 | if (reg == 0) { | |
1488 | /* I-TSB Tag Target register */ | |
1489 | ret = ultrasparc_tag_target(env->immu.tag_access); | |
1490 | } else { | |
1491 | ret = env->immuregs[reg]; | |
1492 | } | |
1493 | ||
1494 | break; | |
1495 | } | |
1496 | case 0x51: /* I-MMU 8k TSB pointer */ | |
1497 | { | |
1498 | /* env->immuregs[5] holds I-MMU TSB register value | |
1499 | env->immuregs[6] holds I-MMU Tag Access register value */ | |
1500 | ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, | |
1501 | 8*1024); | |
1502 | break; | |
1503 | } | |
1504 | case 0x52: /* I-MMU 64k TSB pointer */ | |
1505 | { | |
1506 | /* env->immuregs[5] holds I-MMU TSB register value | |
1507 | env->immuregs[6] holds I-MMU Tag Access register value */ | |
1508 | ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, | |
1509 | 64*1024); | |
1510 | break; | |
1511 | } | |
1512 | case 0x55: /* I-MMU data access */ | |
1513 | { | |
1514 | int reg = (addr >> 3) & 0x3f; | |
1515 | ||
1516 | ret = env->itlb[reg].tte; | |
1517 | break; | |
1518 | } | |
1519 | case 0x56: /* I-MMU tag read */ | |
1520 | { | |
1521 | int reg = (addr >> 3) & 0x3f; | |
1522 | ||
1523 | ret = env->itlb[reg].tag; | |
1524 | break; | |
1525 | } | |
1526 | case 0x58: /* D-MMU regs */ | |
1527 | { | |
1528 | int reg = (addr >> 3) & 0xf; | |
1529 | ||
1530 | if (reg == 0) { | |
1531 | /* D-TSB Tag Target register */ | |
1532 | ret = ultrasparc_tag_target(env->dmmu.tag_access); | |
1533 | } else { | |
1534 | ret = env->dmmuregs[reg]; | |
1535 | } | |
1536 | break; | |
1537 | } | |
1538 | case 0x59: /* D-MMU 8k TSB pointer */ | |
1539 | { | |
1540 | /* env->dmmuregs[5] holds D-MMU TSB register value | |
1541 | env->dmmuregs[6] holds D-MMU Tag Access register value */ | |
1542 | ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, | |
1543 | 8*1024); | |
1544 | break; | |
1545 | } | |
1546 | case 0x5a: /* D-MMU 64k TSB pointer */ | |
1547 | { | |
1548 | /* env->dmmuregs[5] holds D-MMU TSB register value | |
1549 | env->dmmuregs[6] holds D-MMU Tag Access register value */ | |
1550 | ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, | |
1551 | 64*1024); | |
1552 | break; | |
1553 | } | |
1554 | case 0x5d: /* D-MMU data access */ | |
1555 | { | |
1556 | int reg = (addr >> 3) & 0x3f; | |
1557 | ||
1558 | ret = env->dtlb[reg].tte; | |
1559 | break; | |
1560 | } | |
1561 | case 0x5e: /* D-MMU tag read */ | |
1562 | { | |
1563 | int reg = (addr >> 3) & 0x3f; | |
1564 | ||
1565 | ret = env->dtlb[reg].tag; | |
1566 | break; | |
1567 | } | |
361dea40 BS |
1568 | case 0x48: /* Interrupt dispatch, RO */ |
1569 | break; | |
1570 | case 0x49: /* Interrupt data receive */ | |
1571 | ret = env->ivec_status; | |
1572 | break; | |
1573 | case 0x7f: /* Incoming interrupt vector, RO */ | |
1574 | { | |
1575 | int reg = (addr >> 4) & 0x3; | |
1576 | if (reg < 3) { | |
1577 | ret = env->ivec_data[reg]; | |
1578 | } | |
1579 | break; | |
1580 | } | |
fafd8bce BS |
1581 | case 0x46: /* D-cache data */ |
1582 | case 0x47: /* D-cache tag access */ | |
1583 | case 0x4b: /* E-cache error enable */ | |
1584 | case 0x4c: /* E-cache asynchronous fault status */ | |
1585 | case 0x4d: /* E-cache asynchronous fault address */ | |
1586 | case 0x4e: /* E-cache tag data */ | |
1587 | case 0x66: /* I-cache instruction access */ | |
1588 | case 0x67: /* I-cache tag access */ | |
1589 | case 0x6e: /* I-cache predecode */ | |
1590 | case 0x6f: /* I-cache LRU etc. */ | |
1591 | case 0x76: /* E-cache tag */ | |
1592 | case 0x7e: /* E-cache tag */ | |
1593 | break; | |
1594 | case 0x5b: /* D-MMU data pointer */ | |
fafd8bce BS |
1595 | case 0x54: /* I-MMU data in, WO */ |
1596 | case 0x57: /* I-MMU demap, WO */ | |
1597 | case 0x5c: /* D-MMU data in, WO */ | |
1598 | case 0x5f: /* D-MMU demap, WO */ | |
1599 | case 0x77: /* Interrupt vector, WO */ | |
1600 | default: | |
c658b94f AF |
1601 | cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), |
1602 | addr, false, false, 1, size); | |
fafd8bce BS |
1603 | ret = 0; |
1604 | break; | |
1605 | } | |
1606 | ||
1607 | /* Convert from little endian */ | |
1608 | switch (asi) { | |
1609 | case 0x0c: /* Nucleus Little Endian (LE) */ | |
1610 | case 0x18: /* As if user primary LE */ | |
1611 | case 0x19: /* As if user secondary LE */ | |
1612 | case 0x1c: /* Bypass LE */ | |
1613 | case 0x1d: /* Bypass, non-cacheable LE */ | |
1614 | case 0x88: /* Primary LE */ | |
1615 | case 0x89: /* Secondary LE */ | |
1616 | switch(size) { | |
1617 | case 2: | |
1618 | ret = bswap16(ret); | |
1619 | break; | |
1620 | case 4: | |
1621 | ret = bswap32(ret); | |
1622 | break; | |
1623 | case 8: | |
1624 | ret = bswap64(ret); | |
1625 | break; | |
1626 | default: | |
1627 | break; | |
1628 | } | |
1629 | default: | |
1630 | break; | |
1631 | } | |
1632 | ||
1633 | /* Convert to signed number */ | |
1634 | if (sign) { | |
1635 | switch (size) { | |
1636 | case 1: | |
1637 | ret = (int8_t) ret; | |
1638 | break; | |
1639 | case 2: | |
1640 | ret = (int16_t) ret; | |
1641 | break; | |
1642 | case 4: | |
1643 | ret = (int32_t) ret; | |
1644 | break; | |
1645 | default: | |
1646 | break; | |
1647 | } | |
1648 | } | |
1649 | #ifdef DEBUG_ASI | |
1650 | dump_asi("read ", last_addr, asi, size, ret); | |
1651 | #endif | |
1652 | return ret; | |
1653 | } | |
1654 | ||
fe8d8f0f BS |
1655 | void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, |
1656 | int asi, int size) | |
fafd8bce BS |
1657 | { |
1658 | #ifdef DEBUG_ASI | |
1659 | dump_asi("write", addr, asi, size, val); | |
1660 | #endif | |
1661 | ||
1662 | asi &= 0xff; | |
1663 | ||
1664 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) | |
1665 | || (cpu_has_hypervisor(env) | |
1666 | && asi >= 0x30 && asi < 0x80 | |
1667 | && !(env->hpstate & HS_PRIV))) { | |
1668 | helper_raise_exception(env, TT_PRIV_ACT); | |
1669 | } | |
1670 | ||
fe8d8f0f | 1671 | helper_check_align(env, addr, size - 1); |
fafd8bce BS |
1672 | addr = asi_address_mask(env, asi, addr); |
1673 | ||
1674 | /* Convert to little endian */ | |
1675 | switch (asi) { | |
1676 | case 0x0c: /* Nucleus Little Endian (LE) */ | |
1677 | case 0x18: /* As if user primary LE */ | |
1678 | case 0x19: /* As if user secondary LE */ | |
1679 | case 0x1c: /* Bypass LE */ | |
1680 | case 0x1d: /* Bypass, non-cacheable LE */ | |
1681 | case 0x88: /* Primary LE */ | |
1682 | case 0x89: /* Secondary LE */ | |
1683 | switch (size) { | |
1684 | case 2: | |
1685 | val = bswap16(val); | |
1686 | break; | |
1687 | case 4: | |
1688 | val = bswap32(val); | |
1689 | break; | |
1690 | case 8: | |
1691 | val = bswap64(val); | |
1692 | break; | |
1693 | default: | |
1694 | break; | |
1695 | } | |
1696 | default: | |
1697 | break; | |
1698 | } | |
1699 | ||
1700 | switch (asi) { | |
1701 | case 0x10: /* As if user primary */ | |
1702 | case 0x11: /* As if user secondary */ | |
1703 | case 0x18: /* As if user primary LE */ | |
1704 | case 0x19: /* As if user secondary LE */ | |
1705 | case 0x80: /* Primary */ | |
1706 | case 0x81: /* Secondary */ | |
1707 | case 0x88: /* Primary LE */ | |
1708 | case 0x89: /* Secondary LE */ | |
1709 | case 0xe2: /* UA2007 Primary block init */ | |
1710 | case 0xe3: /* UA2007 Secondary block init */ | |
1711 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { | |
1712 | if (cpu_hypervisor_mode(env)) { | |
1713 | switch (size) { | |
1714 | case 1: | |
fe8d8f0f | 1715 | cpu_stb_hypv(env, addr, val); |
fafd8bce BS |
1716 | break; |
1717 | case 2: | |
fe8d8f0f | 1718 | cpu_stw_hypv(env, addr, val); |
fafd8bce BS |
1719 | break; |
1720 | case 4: | |
fe8d8f0f | 1721 | cpu_stl_hypv(env, addr, val); |
fafd8bce BS |
1722 | break; |
1723 | case 8: | |
1724 | default: | |
fe8d8f0f | 1725 | cpu_stq_hypv(env, addr, val); |
fafd8bce BS |
1726 | break; |
1727 | } | |
1728 | } else { | |
1729 | /* secondary space access has lowest asi bit equal to 1 */ | |
1730 | if (asi & 1) { | |
1731 | switch (size) { | |
1732 | case 1: | |
fe8d8f0f | 1733 | cpu_stb_kernel_secondary(env, addr, val); |
fafd8bce BS |
1734 | break; |
1735 | case 2: | |
fe8d8f0f | 1736 | cpu_stw_kernel_secondary(env, addr, val); |
fafd8bce BS |
1737 | break; |
1738 | case 4: | |
fe8d8f0f | 1739 | cpu_stl_kernel_secondary(env, addr, val); |
fafd8bce BS |
1740 | break; |
1741 | case 8: | |
1742 | default: | |
fe8d8f0f | 1743 | cpu_stq_kernel_secondary(env, addr, val); |
fafd8bce BS |
1744 | break; |
1745 | } | |
1746 | } else { | |
1747 | switch (size) { | |
1748 | case 1: | |
fe8d8f0f | 1749 | cpu_stb_kernel(env, addr, val); |
fafd8bce BS |
1750 | break; |
1751 | case 2: | |
fe8d8f0f | 1752 | cpu_stw_kernel(env, addr, val); |
fafd8bce BS |
1753 | break; |
1754 | case 4: | |
fe8d8f0f | 1755 | cpu_stl_kernel(env, addr, val); |
fafd8bce BS |
1756 | break; |
1757 | case 8: | |
1758 | default: | |
fe8d8f0f | 1759 | cpu_stq_kernel(env, addr, val); |
fafd8bce BS |
1760 | break; |
1761 | } | |
1762 | } | |
1763 | } | |
1764 | } else { | |
1765 | /* secondary space access has lowest asi bit equal to 1 */ | |
1766 | if (asi & 1) { | |
1767 | switch (size) { | |
1768 | case 1: | |
fe8d8f0f | 1769 | cpu_stb_user_secondary(env, addr, val); |
fafd8bce BS |
1770 | break; |
1771 | case 2: | |
fe8d8f0f | 1772 | cpu_stw_user_secondary(env, addr, val); |
fafd8bce BS |
1773 | break; |
1774 | case 4: | |
fe8d8f0f | 1775 | cpu_stl_user_secondary(env, addr, val); |
fafd8bce BS |
1776 | break; |
1777 | case 8: | |
1778 | default: | |
fe8d8f0f | 1779 | cpu_stq_user_secondary(env, addr, val); |
fafd8bce BS |
1780 | break; |
1781 | } | |
1782 | } else { | |
1783 | switch (size) { | |
1784 | case 1: | |
fe8d8f0f | 1785 | cpu_stb_user(env, addr, val); |
fafd8bce BS |
1786 | break; |
1787 | case 2: | |
fe8d8f0f | 1788 | cpu_stw_user(env, addr, val); |
fafd8bce BS |
1789 | break; |
1790 | case 4: | |
fe8d8f0f | 1791 | cpu_stl_user(env, addr, val); |
fafd8bce BS |
1792 | break; |
1793 | case 8: | |
1794 | default: | |
fe8d8f0f | 1795 | cpu_stq_user(env, addr, val); |
fafd8bce BS |
1796 | break; |
1797 | } | |
1798 | } | |
1799 | } | |
1800 | break; | |
1801 | case 0x14: /* Bypass */ | |
1802 | case 0x15: /* Bypass, non-cacheable */ | |
1803 | case 0x1c: /* Bypass LE */ | |
1804 | case 0x1d: /* Bypass, non-cacheable LE */ | |
1805 | { | |
1806 | switch (size) { | |
1807 | case 1: | |
1808 | stb_phys(addr, val); | |
1809 | break; | |
1810 | case 2: | |
1811 | stw_phys(addr, val); | |
1812 | break; | |
1813 | case 4: | |
1814 | stl_phys(addr, val); | |
1815 | break; | |
1816 | case 8: | |
1817 | default: | |
1818 | stq_phys(addr, val); | |
1819 | break; | |
1820 | } | |
1821 | } | |
1822 | return; | |
1823 | case 0x24: /* Nucleus quad LDD 128 bit atomic */ | |
1824 | case 0x2c: /* Nucleus quad LDD 128 bit atomic LE | |
1825 | Only ldda allowed */ | |
1826 | helper_raise_exception(env, TT_ILL_INSN); | |
1827 | return; | |
1828 | case 0x04: /* Nucleus */ | |
1829 | case 0x0c: /* Nucleus Little Endian (LE) */ | |
1830 | { | |
1831 | switch (size) { | |
1832 | case 1: | |
fe8d8f0f | 1833 | cpu_stb_nucleus(env, addr, val); |
fafd8bce BS |
1834 | break; |
1835 | case 2: | |
fe8d8f0f | 1836 | cpu_stw_nucleus(env, addr, val); |
fafd8bce BS |
1837 | break; |
1838 | case 4: | |
fe8d8f0f | 1839 | cpu_stl_nucleus(env, addr, val); |
fafd8bce BS |
1840 | break; |
1841 | default: | |
1842 | case 8: | |
fe8d8f0f | 1843 | cpu_stq_nucleus(env, addr, val); |
fafd8bce BS |
1844 | break; |
1845 | } | |
1846 | break; | |
1847 | } | |
1848 | ||
1849 | case 0x4a: /* UPA config */ | |
1850 | /* XXX */ | |
1851 | return; | |
1852 | case 0x45: /* LSU */ | |
1853 | { | |
1854 | uint64_t oldreg; | |
1855 | ||
1856 | oldreg = env->lsu; | |
1857 | env->lsu = val & (DMMU_E | IMMU_E); | |
1858 | /* Mappings generated during D/I MMU disabled mode are | |
1859 | invalid in normal mode */ | |
1860 | if (oldreg != env->lsu) { | |
1861 | DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", | |
1862 | oldreg, env->lsu); | |
1863 | #ifdef DEBUG_MMU | |
05499f4b | 1864 | dump_mmu(stdout, fprintf, env); |
fafd8bce BS |
1865 | #endif |
1866 | tlb_flush(env, 1); | |
1867 | } | |
1868 | return; | |
1869 | } | |
1870 | case 0x50: /* I-MMU regs */ | |
1871 | { | |
1872 | int reg = (addr >> 3) & 0xf; | |
1873 | uint64_t oldreg; | |
1874 | ||
1875 | oldreg = env->immuregs[reg]; | |
1876 | switch (reg) { | |
1877 | case 0: /* RO */ | |
1878 | return; | |
1879 | case 1: /* Not in I-MMU */ | |
1880 | case 2: | |
1881 | return; | |
1882 | case 3: /* SFSR */ | |
1883 | if ((val & 1) == 0) { | |
1884 | val = 0; /* Clear SFSR */ | |
1885 | } | |
1886 | env->immu.sfsr = val; | |
1887 | break; | |
1888 | case 4: /* RO */ | |
1889 | return; | |
1890 | case 5: /* TSB access */ | |
1891 | DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" | |
1892 | PRIx64 "\n", env->immu.tsb, val); | |
1893 | env->immu.tsb = val; | |
1894 | break; | |
1895 | case 6: /* Tag access */ | |
1896 | env->immu.tag_access = val; | |
1897 | break; | |
1898 | case 7: | |
1899 | case 8: | |
1900 | return; | |
1901 | default: | |
1902 | break; | |
1903 | } | |
1904 | ||
1905 | if (oldreg != env->immuregs[reg]) { | |
1906 | DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" | |
1907 | PRIx64 "\n", reg, oldreg, env->immuregs[reg]); | |
1908 | } | |
1909 | #ifdef DEBUG_MMU | |
1910 | dump_mmu(stdout, fprintf, env); | |
1911 | #endif | |
1912 | return; | |
1913 | } | |
1914 | case 0x54: /* I-MMU data in */ | |
1915 | replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env); | |
1916 | return; | |
1917 | case 0x55: /* I-MMU data access */ | |
1918 | { | |
1919 | /* TODO: auto demap */ | |
1920 | ||
1921 | unsigned int i = (addr >> 3) & 0x3f; | |
1922 | ||
1923 | replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env); | |
1924 | ||
1925 | #ifdef DEBUG_MMU | |
1926 | DPRINTF_MMU("immu data access replaced entry [%i]\n", i); | |
1927 | dump_mmu(stdout, fprintf, env); | |
1928 | #endif | |
1929 | return; | |
1930 | } | |
1931 | case 0x57: /* I-MMU demap */ | |
1932 | demap_tlb(env->itlb, addr, "immu", env); | |
1933 | return; | |
1934 | case 0x58: /* D-MMU regs */ | |
1935 | { | |
1936 | int reg = (addr >> 3) & 0xf; | |
1937 | uint64_t oldreg; | |
1938 | ||
1939 | oldreg = env->dmmuregs[reg]; | |
1940 | switch (reg) { | |
1941 | case 0: /* RO */ | |
1942 | case 4: | |
1943 | return; | |
1944 | case 3: /* SFSR */ | |
1945 | if ((val & 1) == 0) { | |
1946 | val = 0; /* Clear SFSR, Fault address */ | |
1947 | env->dmmu.sfar = 0; | |
1948 | } | |
1949 | env->dmmu.sfsr = val; | |
1950 | break; | |
1951 | case 1: /* Primary context */ | |
1952 | env->dmmu.mmu_primary_context = val; | |
1953 | /* can be optimized to only flush MMU_USER_IDX | |
1954 | and MMU_KERNEL_IDX entries */ | |
1955 | tlb_flush(env, 1); | |
1956 | break; | |
1957 | case 2: /* Secondary context */ | |
1958 | env->dmmu.mmu_secondary_context = val; | |
1959 | /* can be optimized to only flush MMU_USER_SECONDARY_IDX | |
1960 | and MMU_KERNEL_SECONDARY_IDX entries */ | |
1961 | tlb_flush(env, 1); | |
1962 | break; | |
1963 | case 5: /* TSB access */ | |
1964 | DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" | |
1965 | PRIx64 "\n", env->dmmu.tsb, val); | |
1966 | env->dmmu.tsb = val; | |
1967 | break; | |
1968 | case 6: /* Tag access */ | |
1969 | env->dmmu.tag_access = val; | |
1970 | break; | |
1971 | case 7: /* Virtual Watchpoint */ | |
1972 | case 8: /* Physical Watchpoint */ | |
1973 | default: | |
1974 | env->dmmuregs[reg] = val; | |
1975 | break; | |
1976 | } | |
1977 | ||
1978 | if (oldreg != env->dmmuregs[reg]) { | |
1979 | DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" | |
1980 | PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); | |
1981 | } | |
1982 | #ifdef DEBUG_MMU | |
1983 | dump_mmu(stdout, fprintf, env); | |
1984 | #endif | |
1985 | return; | |
1986 | } | |
1987 | case 0x5c: /* D-MMU data in */ | |
1988 | replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env); | |
1989 | return; | |
1990 | case 0x5d: /* D-MMU data access */ | |
1991 | { | |
1992 | unsigned int i = (addr >> 3) & 0x3f; | |
1993 | ||
1994 | replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env); | |
1995 | ||
1996 | #ifdef DEBUG_MMU | |
1997 | DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); | |
1998 | dump_mmu(stdout, fprintf, env); | |
1999 | #endif | |
2000 | return; | |
2001 | } | |
2002 | case 0x5f: /* D-MMU demap */ | |
2003 | demap_tlb(env->dtlb, addr, "dmmu", env); | |
2004 | return; | |
2005 | case 0x49: /* Interrupt data receive */ | |
361dea40 | 2006 | env->ivec_status = val & 0x20; |
fafd8bce BS |
2007 | return; |
2008 | case 0x46: /* D-cache data */ | |
2009 | case 0x47: /* D-cache tag access */ | |
2010 | case 0x4b: /* E-cache error enable */ | |
2011 | case 0x4c: /* E-cache asynchronous fault status */ | |
2012 | case 0x4d: /* E-cache asynchronous fault address */ | |
2013 | case 0x4e: /* E-cache tag data */ | |
2014 | case 0x66: /* I-cache instruction access */ | |
2015 | case 0x67: /* I-cache tag access */ | |
2016 | case 0x6e: /* I-cache predecode */ | |
2017 | case 0x6f: /* I-cache LRU etc. */ | |
2018 | case 0x76: /* E-cache tag */ | |
2019 | case 0x7e: /* E-cache tag */ | |
2020 | return; | |
2021 | case 0x51: /* I-MMU 8k TSB pointer, RO */ | |
2022 | case 0x52: /* I-MMU 64k TSB pointer, RO */ | |
2023 | case 0x56: /* I-MMU tag read, RO */ | |
2024 | case 0x59: /* D-MMU 8k TSB pointer, RO */ | |
2025 | case 0x5a: /* D-MMU 64k TSB pointer, RO */ | |
2026 | case 0x5b: /* D-MMU data pointer, RO */ | |
2027 | case 0x5e: /* D-MMU tag read, RO */ | |
2028 | case 0x48: /* Interrupt dispatch, RO */ | |
2029 | case 0x7f: /* Incoming interrupt vector, RO */ | |
2030 | case 0x82: /* Primary no-fault, RO */ | |
2031 | case 0x83: /* Secondary no-fault, RO */ | |
2032 | case 0x8a: /* Primary no-fault LE, RO */ | |
2033 | case 0x8b: /* Secondary no-fault LE, RO */ | |
2034 | default: | |
c658b94f AF |
2035 | cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), |
2036 | addr, true, false, 1, size); | |
fafd8bce BS |
2037 | return; |
2038 | } | |
2039 | } | |
2040 | #endif /* CONFIG_USER_ONLY */ | |
2041 | ||
fe8d8f0f | 2042 | void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd) |
fafd8bce BS |
2043 | { |
2044 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) | |
2045 | || (cpu_has_hypervisor(env) | |
2046 | && asi >= 0x30 && asi < 0x80 | |
2047 | && !(env->hpstate & HS_PRIV))) { | |
2048 | helper_raise_exception(env, TT_PRIV_ACT); | |
2049 | } | |
2050 | ||
2051 | addr = asi_address_mask(env, asi, addr); | |
2052 | ||
2053 | switch (asi) { | |
2054 | #if !defined(CONFIG_USER_ONLY) | |
2055 | case 0x24: /* Nucleus quad LDD 128 bit atomic */ | |
2056 | case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */ | |
fe8d8f0f | 2057 | helper_check_align(env, addr, 0xf); |
fafd8bce | 2058 | if (rd == 0) { |
fe8d8f0f | 2059 | env->gregs[1] = cpu_ldq_nucleus(env, addr + 8); |
fafd8bce BS |
2060 | if (asi == 0x2c) { |
2061 | bswap64s(&env->gregs[1]); | |
2062 | } | |
2063 | } else if (rd < 8) { | |
fe8d8f0f BS |
2064 | env->gregs[rd] = cpu_ldq_nucleus(env, addr); |
2065 | env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8); | |
fafd8bce BS |
2066 | if (asi == 0x2c) { |
2067 | bswap64s(&env->gregs[rd]); | |
2068 | bswap64s(&env->gregs[rd + 1]); | |
2069 | } | |
2070 | } else { | |
fe8d8f0f BS |
2071 | env->regwptr[rd] = cpu_ldq_nucleus(env, addr); |
2072 | env->regwptr[rd + 1] = cpu_ldq_nucleus(env, addr + 8); | |
fafd8bce BS |
2073 | if (asi == 0x2c) { |
2074 | bswap64s(&env->regwptr[rd]); | |
2075 | bswap64s(&env->regwptr[rd + 1]); | |
2076 | } | |
2077 | } | |
2078 | break; | |
2079 | #endif | |
2080 | default: | |
fe8d8f0f | 2081 | helper_check_align(env, addr, 0x3); |
fafd8bce | 2082 | if (rd == 0) { |
fe8d8f0f | 2083 | env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0); |
fafd8bce | 2084 | } else if (rd < 8) { |
fe8d8f0f BS |
2085 | env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0); |
2086 | env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0); | |
fafd8bce | 2087 | } else { |
fe8d8f0f BS |
2088 | env->regwptr[rd] = helper_ld_asi(env, addr, asi, 4, 0); |
2089 | env->regwptr[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0); | |
fafd8bce BS |
2090 | } |
2091 | break; | |
2092 | } | |
2093 | } | |
2094 | ||
fe8d8f0f BS |
2095 | void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, |
2096 | int rd) | |
fafd8bce BS |
2097 | { |
2098 | unsigned int i; | |
30038fd8 | 2099 | target_ulong val; |
fafd8bce | 2100 | |
fe8d8f0f | 2101 | helper_check_align(env, addr, 3); |
fafd8bce BS |
2102 | addr = asi_address_mask(env, asi, addr); |
2103 | ||
2104 | switch (asi) { | |
2105 | case 0xf0: /* UA2007/JPS1 Block load primary */ | |
2106 | case 0xf1: /* UA2007/JPS1 Block load secondary */ | |
2107 | case 0xf8: /* UA2007/JPS1 Block load primary LE */ | |
2108 | case 0xf9: /* UA2007/JPS1 Block load secondary LE */ | |
2109 | if (rd & 7) { | |
2110 | helper_raise_exception(env, TT_ILL_INSN); | |
2111 | return; | |
2112 | } | |
fe8d8f0f | 2113 | helper_check_align(env, addr, 0x3f); |
30038fd8 | 2114 | for (i = 0; i < 8; i++, rd += 2, addr += 8) { |
fe8d8f0f | 2115 | env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0); |
fafd8bce | 2116 | } |
fafd8bce | 2117 | return; |
30038fd8 | 2118 | |
fafd8bce BS |
2119 | case 0x16: /* UA2007 Block load primary, user privilege */ |
2120 | case 0x17: /* UA2007 Block load secondary, user privilege */ | |
2121 | case 0x1e: /* UA2007 Block load primary LE, user privilege */ | |
2122 | case 0x1f: /* UA2007 Block load secondary LE, user privilege */ | |
2123 | case 0x70: /* JPS1 Block load primary, user privilege */ | |
2124 | case 0x71: /* JPS1 Block load secondary, user privilege */ | |
2125 | case 0x78: /* JPS1 Block load primary LE, user privilege */ | |
2126 | case 0x79: /* JPS1 Block load secondary LE, user privilege */ | |
2127 | if (rd & 7) { | |
2128 | helper_raise_exception(env, TT_ILL_INSN); | |
2129 | return; | |
2130 | } | |
fe8d8f0f | 2131 | helper_check_align(env, addr, 0x3f); |
00b2ace5 | 2132 | for (i = 0; i < 8; i++, rd += 2, addr += 8) { |
fe8d8f0f | 2133 | env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0); |
fafd8bce | 2134 | } |
fafd8bce | 2135 | return; |
30038fd8 | 2136 | |
fafd8bce BS |
2137 | default: |
2138 | break; | |
2139 | } | |
2140 | ||
2141 | switch (size) { | |
2142 | default: | |
2143 | case 4: | |
fe8d8f0f | 2144 | val = helper_ld_asi(env, addr, asi, size, 0); |
30038fd8 | 2145 | if (rd & 1) { |
fe8d8f0f | 2146 | env->fpr[rd / 2].l.lower = val; |
30038fd8 | 2147 | } else { |
fe8d8f0f | 2148 | env->fpr[rd / 2].l.upper = val; |
30038fd8 | 2149 | } |
fafd8bce BS |
2150 | break; |
2151 | case 8: | |
fe8d8f0f | 2152 | env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0); |
fafd8bce BS |
2153 | break; |
2154 | case 16: | |
fe8d8f0f BS |
2155 | env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0); |
2156 | env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0); | |
fafd8bce BS |
2157 | break; |
2158 | } | |
2159 | } | |
2160 | ||
fe8d8f0f BS |
2161 | void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, |
2162 | int rd) | |
fafd8bce BS |
2163 | { |
2164 | unsigned int i; | |
30038fd8 | 2165 | target_ulong val; |
fafd8bce | 2166 | |
fe8d8f0f | 2167 | helper_check_align(env, addr, 3); |
fafd8bce BS |
2168 | addr = asi_address_mask(env, asi, addr); |
2169 | ||
2170 | switch (asi) { | |
2171 | case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */ | |
2172 | case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */ | |
2173 | case 0xf0: /* UA2007/JPS1 Block store primary */ | |
2174 | case 0xf1: /* UA2007/JPS1 Block store secondary */ | |
2175 | case 0xf8: /* UA2007/JPS1 Block store primary LE */ | |
2176 | case 0xf9: /* UA2007/JPS1 Block store secondary LE */ | |
2177 | if (rd & 7) { | |
2178 | helper_raise_exception(env, TT_ILL_INSN); | |
2179 | return; | |
2180 | } | |
fe8d8f0f | 2181 | helper_check_align(env, addr, 0x3f); |
30038fd8 | 2182 | for (i = 0; i < 8; i++, rd += 2, addr += 8) { |
fe8d8f0f | 2183 | helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8); |
fafd8bce BS |
2184 | } |
2185 | ||
2186 | return; | |
2187 | case 0x16: /* UA2007 Block load primary, user privilege */ | |
2188 | case 0x17: /* UA2007 Block load secondary, user privilege */ | |
2189 | case 0x1e: /* UA2007 Block load primary LE, user privilege */ | |
2190 | case 0x1f: /* UA2007 Block load secondary LE, user privilege */ | |
2191 | case 0x70: /* JPS1 Block store primary, user privilege */ | |
2192 | case 0x71: /* JPS1 Block store secondary, user privilege */ | |
2193 | case 0x78: /* JPS1 Block load primary LE, user privilege */ | |
2194 | case 0x79: /* JPS1 Block load secondary LE, user privilege */ | |
2195 | if (rd & 7) { | |
2196 | helper_raise_exception(env, TT_ILL_INSN); | |
2197 | return; | |
2198 | } | |
fe8d8f0f | 2199 | helper_check_align(env, addr, 0x3f); |
30038fd8 | 2200 | for (i = 0; i < 8; i++, rd += 2, addr += 8) { |
fe8d8f0f | 2201 | helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8); |
fafd8bce BS |
2202 | } |
2203 | ||
2204 | return; | |
2205 | default: | |
2206 | break; | |
2207 | } | |
2208 | ||
2209 | switch (size) { | |
2210 | default: | |
2211 | case 4: | |
30038fd8 | 2212 | if (rd & 1) { |
fe8d8f0f | 2213 | val = env->fpr[rd / 2].l.lower; |
30038fd8 | 2214 | } else { |
fe8d8f0f | 2215 | val = env->fpr[rd / 2].l.upper; |
30038fd8 | 2216 | } |
fe8d8f0f | 2217 | helper_st_asi(env, addr, val, asi, size); |
fafd8bce BS |
2218 | break; |
2219 | case 8: | |
fe8d8f0f | 2220 | helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size); |
fafd8bce BS |
2221 | break; |
2222 | case 16: | |
fe8d8f0f BS |
2223 | helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8); |
2224 | helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8); | |
fafd8bce BS |
2225 | break; |
2226 | } | |
2227 | } | |
2228 | ||
fe8d8f0f BS |
2229 | target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr, |
2230 | target_ulong val1, target_ulong val2, uint32_t asi) | |
fafd8bce BS |
2231 | { |
2232 | target_ulong ret; | |
2233 | ||
2234 | val2 &= 0xffffffffUL; | |
fe8d8f0f | 2235 | ret = helper_ld_asi(env, addr, asi, 4, 0); |
fafd8bce BS |
2236 | ret &= 0xffffffffUL; |
2237 | if (val2 == ret) { | |
fe8d8f0f | 2238 | helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4); |
fafd8bce BS |
2239 | } |
2240 | return ret; | |
2241 | } | |
2242 | ||
fe8d8f0f BS |
2243 | target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr, |
2244 | target_ulong val1, target_ulong val2, | |
2245 | uint32_t asi) | |
fafd8bce BS |
2246 | { |
2247 | target_ulong ret; | |
2248 | ||
fe8d8f0f | 2249 | ret = helper_ld_asi(env, addr, asi, 8, 0); |
fafd8bce | 2250 | if (val2 == ret) { |
fe8d8f0f | 2251 | helper_st_asi(env, addr, val1, asi, 8); |
fafd8bce BS |
2252 | } |
2253 | return ret; | |
2254 | } | |
2255 | #endif /* TARGET_SPARC64 */ | |
2256 | ||
fe8d8f0f | 2257 | void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx) |
fafd8bce BS |
2258 | { |
2259 | /* XXX add 128 bit load */ | |
2260 | CPU_QuadU u; | |
2261 | ||
fe8d8f0f | 2262 | helper_check_align(env, addr, 7); |
fafd8bce BS |
2263 | #if !defined(CONFIG_USER_ONLY) |
2264 | switch (mem_idx) { | |
2265 | case MMU_USER_IDX: | |
fe8d8f0f BS |
2266 | u.ll.upper = cpu_ldq_user(env, addr); |
2267 | u.ll.lower = cpu_ldq_user(env, addr + 8); | |
fafd8bce BS |
2268 | QT0 = u.q; |
2269 | break; | |
2270 | case MMU_KERNEL_IDX: | |
fe8d8f0f BS |
2271 | u.ll.upper = cpu_ldq_kernel(env, addr); |
2272 | u.ll.lower = cpu_ldq_kernel(env, addr + 8); | |
fafd8bce BS |
2273 | QT0 = u.q; |
2274 | break; | |
2275 | #ifdef TARGET_SPARC64 | |
2276 | case MMU_HYPV_IDX: | |
fe8d8f0f BS |
2277 | u.ll.upper = cpu_ldq_hypv(env, addr); |
2278 | u.ll.lower = cpu_ldq_hypv(env, addr + 8); | |
fafd8bce BS |
2279 | QT0 = u.q; |
2280 | break; | |
2281 | #endif | |
2282 | default: | |
2283 | DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx); | |
2284 | break; | |
2285 | } | |
2286 | #else | |
2287 | u.ll.upper = ldq_raw(address_mask(env, addr)); | |
2288 | u.ll.lower = ldq_raw(address_mask(env, addr + 8)); | |
2289 | QT0 = u.q; | |
2290 | #endif | |
2291 | } | |
2292 | ||
fe8d8f0f | 2293 | void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx) |
fafd8bce BS |
2294 | { |
2295 | /* XXX add 128 bit store */ | |
2296 | CPU_QuadU u; | |
2297 | ||
fe8d8f0f | 2298 | helper_check_align(env, addr, 7); |
fafd8bce BS |
2299 | #if !defined(CONFIG_USER_ONLY) |
2300 | switch (mem_idx) { | |
2301 | case MMU_USER_IDX: | |
2302 | u.q = QT0; | |
fe8d8f0f BS |
2303 | cpu_stq_user(env, addr, u.ll.upper); |
2304 | cpu_stq_user(env, addr + 8, u.ll.lower); | |
fafd8bce BS |
2305 | break; |
2306 | case MMU_KERNEL_IDX: | |
2307 | u.q = QT0; | |
fe8d8f0f BS |
2308 | cpu_stq_kernel(env, addr, u.ll.upper); |
2309 | cpu_stq_kernel(env, addr + 8, u.ll.lower); | |
fafd8bce BS |
2310 | break; |
2311 | #ifdef TARGET_SPARC64 | |
2312 | case MMU_HYPV_IDX: | |
2313 | u.q = QT0; | |
fe8d8f0f BS |
2314 | cpu_stq_hypv(env, addr, u.ll.upper); |
2315 | cpu_stq_hypv(env, addr + 8, u.ll.lower); | |
fafd8bce BS |
2316 | break; |
2317 | #endif | |
2318 | default: | |
2319 | DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx); | |
2320 | break; | |
2321 | } | |
2322 | #else | |
2323 | u.q = QT0; | |
2324 | stq_raw(address_mask(env, addr), u.ll.upper); | |
2325 | stq_raw(address_mask(env, addr + 8), u.ll.lower); | |
2326 | #endif | |
2327 | } | |
2328 | ||
fafd8bce | 2329 | #if !defined(CONFIG_USER_ONLY) |
fe8d8f0f | 2330 | #ifndef TARGET_SPARC64 |
c658b94f AF |
2331 | void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, |
2332 | bool is_write, bool is_exec, int is_asi, | |
2333 | unsigned size) | |
fafd8bce | 2334 | { |
c658b94f AF |
2335 | SPARCCPU *cpu = SPARC_CPU(cs); |
2336 | CPUSPARCState *env = &cpu->env; | |
fafd8bce BS |
2337 | int fault_type; |
2338 | ||
2339 | #ifdef DEBUG_UNASSIGNED | |
2340 | if (is_asi) { | |
2341 | printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx | |
2342 | " asi 0x%02x from " TARGET_FMT_lx "\n", | |
2343 | is_exec ? "exec" : is_write ? "write" : "read", size, | |
2344 | size == 1 ? "" : "s", addr, is_asi, env->pc); | |
2345 | } else { | |
2346 | printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx | |
2347 | " from " TARGET_FMT_lx "\n", | |
2348 | is_exec ? "exec" : is_write ? "write" : "read", size, | |
2349 | size == 1 ? "" : "s", addr, env->pc); | |
2350 | } | |
2351 | #endif | |
2352 | /* Don't overwrite translation and access faults */ | |
2353 | fault_type = (env->mmuregs[3] & 0x1c) >> 2; | |
2354 | if ((fault_type > 4) || (fault_type == 0)) { | |
2355 | env->mmuregs[3] = 0; /* Fault status register */ | |
2356 | if (is_asi) { | |
2357 | env->mmuregs[3] |= 1 << 16; | |
2358 | } | |
2359 | if (env->psrs) { | |
2360 | env->mmuregs[3] |= 1 << 5; | |
2361 | } | |
2362 | if (is_exec) { | |
2363 | env->mmuregs[3] |= 1 << 6; | |
2364 | } | |
2365 | if (is_write) { | |
2366 | env->mmuregs[3] |= 1 << 7; | |
2367 | } | |
2368 | env->mmuregs[3] |= (5 << 2) | 2; | |
2369 | /* SuperSPARC will never place instruction fault addresses in the FAR */ | |
2370 | if (!is_exec) { | |
2371 | env->mmuregs[4] = addr; /* Fault address register */ | |
2372 | } | |
2373 | } | |
2374 | /* overflow (same type fault was not read before another fault) */ | |
2375 | if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { | |
2376 | env->mmuregs[3] |= 1; | |
2377 | } | |
2378 | ||
2379 | if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { | |
2380 | if (is_exec) { | |
2381 | helper_raise_exception(env, TT_CODE_ACCESS); | |
2382 | } else { | |
2383 | helper_raise_exception(env, TT_DATA_ACCESS); | |
2384 | } | |
2385 | } | |
2386 | ||
2387 | /* flush neverland mappings created during no-fault mode, | |
2388 | so the sequential MMU faults report proper fault types */ | |
2389 | if (env->mmuregs[0] & MMU_NF) { | |
2390 | tlb_flush(env, 1); | |
2391 | } | |
2392 | } | |
fafd8bce | 2393 | #else |
c658b94f AF |
2394 | void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, |
2395 | bool is_write, bool is_exec, int is_asi, | |
2396 | unsigned size) | |
fafd8bce | 2397 | { |
c658b94f AF |
2398 | SPARCCPU *cpu = SPARC_CPU(cs); |
2399 | CPUSPARCState *env = &cpu->env; | |
2400 | ||
fafd8bce BS |
2401 | #ifdef DEBUG_UNASSIGNED |
2402 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx | |
2403 | "\n", addr, env->pc); | |
2404 | #endif | |
2405 | ||
2406 | if (is_exec) { | |
2407 | helper_raise_exception(env, TT_CODE_ACCESS); | |
2408 | } else { | |
2409 | helper_raise_exception(env, TT_DATA_ACCESS); | |
2410 | } | |
2411 | } | |
2412 | #endif | |
fafd8bce | 2413 | #endif |
0184e266 | 2414 | |
c28ae41e | 2415 | #if !defined(CONFIG_USER_ONLY) |
8f721967 BS |
2416 | static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, |
2417 | target_ulong addr, int is_write, | |
2418 | int is_user, uintptr_t retaddr) | |
0184e266 BS |
2419 | { |
2420 | #ifdef DEBUG_UNALIGNED | |
2421 | printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx | |
2422 | "\n", addr, env->pc); | |
2423 | #endif | |
a8a826a3 BS |
2424 | if (retaddr) { |
2425 | cpu_restore_state(env, retaddr); | |
2426 | } | |
0184e266 BS |
2427 | helper_raise_exception(env, TT_UNALIGNED); |
2428 | } | |
2429 | ||
2430 | /* try to fill the TLB and return an exception if error. If retaddr is | |
2431 | NULL, it means that the function was called in C code (i.e. not | |
2432 | from generated code or from helper.c) */ | |
2433 | /* XXX: fix it to restore all registers */ | |
2434 | void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx, | |
20503968 | 2435 | uintptr_t retaddr) |
0184e266 BS |
2436 | { |
2437 | int ret; | |
2438 | ||
2439 | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx); | |
2440 | if (ret) { | |
a8a826a3 BS |
2441 | if (retaddr) { |
2442 | cpu_restore_state(env, retaddr); | |
2443 | } | |
0184e266 BS |
2444 | cpu_loop_exit(env); |
2445 | } | |
2446 | } | |
2447 | #endif |